Design of a Low Volage Low Power and High Speed CMOS

Comparator

A
PRELIMINARY DISSERTATION CUM SYNOPSIS REPORT
SUBMITTED
OF
MASTER OF TECHNOLOGY
IN
STREAM

SUBMITTED TO
RAJIV GANDHI PROUDYOGIKI VISHWAVIDYALAYA, BHOPAL (M.P.)

SUBMITTED BY
Student Name
ENROLLMENT NO:
UNDER THE GUIDANCE OF
Prof. (Guide)
DESIGNATION

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

LAKSHMI NARAIN COLLEGE OF TECHNOLOGY
BHOPAL, (M.P.)
 Lakshmi Narain College of Technology, Bhopal
Department of Electronics & Communication Engineering

CANDIDATE’S DECLARATION

I hereby declare that the work that to the best of my knowledge this
preliminary dissertation cum synopsis report entitled “Design of a Low
Volage Low Power and High Speed CMOS Comparator” in partial
fulfillment of the requirements for the award of degree of Master of
Technology in (Branch Name & Specialization) submitted in the department
of _______ (Institution Name) is an authentic record of my own work carried
under the Guidance of ____ (Name of the Guide). The work presented does
not infringe any patented work and has not been submitted to any University
for the award of any degree or any professional diploma. The references in
this work have been duly referred.
.

Name of the Student

(Enrollment No.)

Supervisor

Director/Principal
Sign.with Seal

i
 Lakshmi Narain College of Technology, Bhopal
Department of Electronics & Communication Engineering

CERTIFICATE

This is to certify that the preliminary dissertation cum synopsis report

entitled “Design of a Low Volage Low Power and High Speed CMOS
Comparator” the bonafide research work carried out independently by
NAME OF RESEARCH SCHOLAR, student of Master of Technology
in “STREAM” from Rajiv Gandhi Proudyogiki Vishwavidyalaya,
Bhopal for the partial fulfillment of the requirement for the award of the
degree of Master of Technology and this dissertation has not formed
previously the basis for the award of any degree, diploma, associate ship,
fellowship or any other similar title according to our knowledge.

Guided by Approved by
NAME OF GUIDE
(Designation) (Professor & HOD)
LNCT, Bhopal LNCT, Bhopal

Forwarded by

Principal
LNCT, Bhopal

ii
 Lakshmi Narain College of Technology, Bhopal
Department of Electronics & Communication Engineering

APPROVAL CERTIFICATE

The dissertation work entitled “Design of a Low Volage Low Power

and High Speed CMOS Comparator” being submitted by NAME OF
THE RESEARCH SCHOLAR, ENROLLMENT NO. has been
examined by us and is hereby approved for the award of degree of Master
of Technology in STREAM for which it has been submitted to Rajiv
Gandhi Proudyogiki Vishwavidyalaya, Bhopal (M.P.).

Internal Examiner External Examiner

Date: Date:

iii
 ACKNOWLEDGEMENT

I take the opportunity to express my cordial gratitude to Prof. Prashant

Purohit, Associate Professor in the Department of Electronics and
communication Engineering. Lakshmi Narain College of Technology, Bhopal
for the valuable guidance and inspiration throughout the dissertation work I feel
thankful for his innovative ideas, which led to successful completion of this
work.

I give special thanks to Dr. Soni Changlani, Prof. & Head of Department of
Electronics and communication Engineering, Lakshmi Narain College of
Technology, Bhopal, to always being willing to help find solutions to any
problems I had with my work

I also want to acknowledge Dr. Ashok Kumar Rai, Director Administration,

Lakshmi Narain College of Technology, Bhopal, for giving me the opportunity
to present my work successfully and giving me the assistance for my
dissertation works.

I express my gratitude and thanks to all the staff members of Department of

Electronics and communication engineering for supporting my work and
providing me the proper guidance during my work.

At last I thanks to my parents, my friends for their encouragement and

motivation. I am also thankful to my classmates for all the thoughtful and mind
stimulating discussions we had, which prompted us to think beyond the
obvious.

NAME
ENROLMENT No.

iv
 CONTENTS

List of Figures…………………………………………………………………........ vi
List of Abbreviations……………………………………………………………… vii
Abstract…………………………………………………………………………….. viii

Chapter 1 – Introduction………………………………………………………... 1-4

1.1 Introduction…………………………………………………………... 1
1.2 Motivation …………………………………………………………… 3
1.3 Objective of the Project……………………………………………… 4
Chapter 2 - Literature review………………………………………………….. 5-7
Chapter 3 – Problem Formulation……………………………………………. 8
Chapter 4 – Proposed Methodology………………………………………….. 9-12
Chapter 5 – System components / Algorithm……………………………….. 13
Chapter 6 – Expect Implementation / Simulations and Result……………… 14
Chapter 7 Conclusion and Future Scope……………………………............ 15-16
7.1 Conclusion...................................................................................... 15
7.2 Future Scope................................................................................. 15
Chapter 8 – References.............……………………………………………….. 16-17
Appendix I – Base Paper ……………………………...…………….

v
 LIST OF FIGURES

Figure No. Description of the figure Page No.

Figure 1.1 Principle electrical function of a comparator 02
Figure 4.1 Block Diagram of Shared charge logic used in cross-coupled latch
stage using pass transistor 09
Figure 4.2 Transient behavior of proposed shared charge logic during the
reset phase 10

vi
 LIST OF ABBREVIATIONS

A/D : Analog to Digital Converter

D/A : Digital to Analog Converter
CMOS : Complementary Metal Oxide Semiconductor
IOT : Internet of Things
DTDC : Double Tail Dynamic Comparator

viii
 ABSTRACT

Analog-to-digital converters (ADCs) and Digital-to-Analog converters (DACs) are key

components of modern microelectronics applications where an interface between the analog
world and the progressive digital signal processing world is needed. They are found in an
extensive range of devices in consumer electronics, medical equipment, communication and
instrumentation applications, and current growing areas (e.g. Internet of Things (IoT), all
portable systems in today s life, and wearable devices etc.) just to name a few. With the fast
development of CMOS technology, more and more signal processing circuits and building
blocks are implemented in the digital domain for lower cost, lower power consumption, high-
speed, higher yield, and higher re-configurability. To minimize production steps and the cost of
the final product, several functional circuit blocks are combined into one chip and form a System
on a Chip (SoC). It is common to implement digital and analog blocks into one chip with
additional ADCs or DACs. The basic building blocks of an ADCs and DACs consist of analog
circuits such as voltage reference, operational amplifiers as well as mixed signal circuits such as
comparators. The comparator is also known as 1-bit ADC and for that reason, it is mostly used in
abundance in ADCs. Besides ADCs and DACs, the comparator has many other applications such
as VLSI logic circuits, memory, relaxation oscillators, null detector, zero-crossing detectors,
peak detectors, switching power regulators, high-speed wireless and wireline communication
systems, and many more. This has generated a great demand for high-speed, low-power, and
low-voltage comparator that can be realized in a mainstream deep submicron Complementary
Metal Oxide Semiconductor (CMOS) technology.

ix
 Design of a Low Volage Low Power and High Speed CMOS Comparator

CHAPTER 1
INTRODUCTION

1.1 Introduction
The environmental quantities in nature operate in the analog domain. To get a
better insight into these analog signals, they should be converted to digital signals.
There are many advantages of the digitization of the information. The data converters
(i.e. Analog to Digital Converter (ADCs) and Digital to Analog Converter (DACs))
are the bridge between the analog and digital world. These data converter converts
one type of data (i.e. analog) into another form (i.e. digital) or vice versa. It is the
backbone of all state of art digital systems, which interact with the environment and
carry out the data processing in the digital domain. The basic building blocks of
ADCs/DACs consist of analog circuits such as voltage reference, operational
amplifiers as well as mixed signal circuits like comparators. The comparator is
also known as 1-bit ADC and is one of the most important blocks in ADCs.
Data converters, i.e. ADCs have become a constituent component which drives
the semiconductor industry over the past few years. More and more functional
blocks are integrated within a single chip, making this component more conventional
and they are able to provide high-speed with low-power dissipation.
In the modern era, it is essential that the electronic systems consume ultra-low power.
Biomedical implantable or transportable systems are such systems which demand
low-power operation (Tang, et al., 2014) (Yuan, et al., 2011) (Zuo, et al., 2008).
Other than ADC, the comparator also plays a vital role in the design of oscillators,
null detectors, peak detectors, a zero-crossing detector, switching power regulators
and many more electronics devices. In addition to these, as most of the devices are
becoming portable and battery operated, the features of ADCs like high-speed, low-
power, and a smaller area on the die, make them widely acceptable to the
semiconductor industry. All these concerns apply to the most usable representative
of the ADCs: the comparator. It necessary to implement ADC and mainly the
comparator, which is one of the main parts of ADC, using low power design techniques
(Abo et al., 1999) (Hong, et al., 2007) (Plassche et al., 2002) (Sharuddin, et al., 2014)
(Wang, et al., 2007) (Zhang, et al., 2012).

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 1
 Design of a Low Volage Low Power and High Speed CMOS Comparator

The basic configuration of the comparator can be one of the three type, namely (i)
Simple inverter, (ii) Operation amplifier (in open loop configuration), and (iii)
Differential amplifier along with cross-coupled latch. Operational amplifier (op-
amp) is the most widely used component in electronics and normally used with
negative feedback. It can also be used as a comparator in open loop configuration.
The comparator is the second most widely used component/circuit in electronics
after op-amp. The comparator configuration is typically designed without feedback
in open loop configuration. Normally, the inverter based configuration is not used in
ADCs as the switching threshold (which is highly influenced by the mismatch) of
inverter works as the reference voltage and have high static power consumption.
The thesis mainly focuses on differential amplifier (with the cross-coupled latch)
configuration.
In the analog-to-digital conversion process, it is essential to first sample the input.
The sampled signal is then applied to a combination of comparators to determine the
digital equivalence of the analog signal. The conversion speed of these comparators
is restricted by the decision making response time of it. The basic application of a
CMOS comparator is to find out whether a given signal is greater or smaller than
the reference signal. It compares one analog input signal with the reference signal
and outputs a binary signal based on the comparison. As a result, the comparator
gives a logical value, e.g. the voltage levels of the supply voltage or the ground level
for logical high or low, which indicates, whether one input signal value is higher or
lower than the other input signal value. The principal electrical function of a
comparator and the schematic symbol of a comparator are depicted in Fig. 1.1.

Fig. 1.1 Principle electrical function of a comparator

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 2
 Design of a Low Volage Low Power and High Speed CMOS Comparator

The comparator can be thought of as a decision-making circuit. If Wm (V+ or Vp)

input of the comparator is at a greater potential than VINN (V- or VN) input, the
output of the comparator is at Vdd (High or Logic 1), whereas if ViNp input is at a
potential less than VINN input, output of the comparator is ground (Vss or Low or
Logic 0). An ideal comparator can detect an infinitesimally small voltage difference
between ViNp and VINN and convert it into a sharp transition at output between
VOUT = 0 to VOUT = 1 or from 1 to 0. In practical cases, this transition is not sharp
and thus a delay is observed in between the input change and corresponding
updation in the output signal. Thus, for high speed operations, this transition must
occur as quickly as possible. Normally, both the inputs are not the same in practically
real time applications. A slight difference in the input voltages should also result in
the large output. So, the comparator is designed to have Gain as high as possible to
detect even small differences in the inputs. To incorporate the equality of both the
signals at the same time, the hysteresis or adding sub-circuits for indication of equal
input values can be introduced.

1.2 Motivation
The advancement and progress of technology are always coupled with the
growing demands of handling more operations in limited/shorter duration of time.
As a tendency, more functional blocks are transferred and implemented in the digital
domain to invent the possibilities of easier and more individualized
implementation of blocks, hence subsequently software adoption is required. As
discussed earlier, ADCs and DACs are the key components/blocks for interfacing-
link between the two different domains: Analog and Digital. ADCs convert the
analog signal into digital, which are discrete in amplitude and time. The reciprocal
translation from the digital domain into the analog is carried out by DACs. Fast
computation, less influenced by noise, less bandwidth requirement, encryption,
security, minimal electromagnetic interference, easy storage, sophisticated DSP
signal algorithm implementation, etc., are the key factors that force to use the digital
domain, which requires high-speed ADCs.
The comparator is the key building block in the design process of ADC, which controls
the performance and the accuracy of ADCs. The requirement of bandwidth is also
increasing day by day and almost all lower bands are already occupied so to

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 3
 Design of a Low Volage Low Power and High Speed CMOS Comparator

design ADC which works on higher frequencies is needed in this modern world.
Current growing areas, such as the Internet of Things (IoT) require high-speed and
ultra-low power devices and on the other hand, wearable device demands small
size. Portable electronic systems such as devices used in the wireless
communication, consumer electronics or medical equipment, elevates the requirement
of producing low—power, high-speed circuit methods and building blocks.

1.3 Objectives of Project

 To propose a new low voltage, low power, and high-speed double tail current
dynamic (clocked regenerative) latch comparator architecture.
 To derive a generalized analytical expression for the conventional (referred)
and proposed comparator for their performance parameters (like speed,
power, offset) which helps the designer to obtain an intuition about the main
contributors to the comparator delay, power consumption, PDP, offset voltage.
 To analyze the effect of parametric variation (like input common-mode voltage,
input differential voltage, supply voltage variation), process variation, and
device mismatch on the performance of proposed comparators.

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 4
 Design of a Low Volage Low Power and High Speed CMOS Comparator

CHAPTER 2
LITERATURE REVIEW

Nagesh Mantravadia et al. [1], Dynamic comparators are highly utilized in design of
high-speed digital circuits. More precisely, Low power and high-speed dynamic
comparators are the key elements in manufacturing of CPUs in many electronic
devices. These CPUs consist of many comparison circuits known as comparators.
This journal paper presents a low voltage thereby a low power Double Tail Dynamic
Comparator (DTDC) with relatively less power consumption when compared to
existing designs. In this journal paper, various types of dynamic comparators are
discussed and compared with the proposed design. Dynamic comparators based on
Double Tail technique, floating inverter amplifier technique and regenerative latch
technique etc., are compared to the proposed design. This design is simulated using
250nm technology with the aid of Tanner EDA simulation tool. The pre-amplification
process in this proposed design is implemented using Self-biasing technique. Self-
biasing technique produces low kick back noise during the operation of this proposed
design.

N. Soumya et al. [2], in the electronics sector, in particular digital signal processing
(DSP), picture processing or even math systems in microprocessors, a quick as well as
effort modifier is often required. Multiplier really is an significant component that
significantly adds to the system's complete energy usage. In VLSI, multipliers of
different bit-widths are often needed from computers to particular embedded systems
for implementation. To be that much further energy than supplementary TTL, logic
type similarities relying on complete CMOS devices have currently been revealed.
The most significant but also commonly adopted metrics of evaluating delay, energy
dispersion and region of multiplier layout performance.

H. S. Bindra et al. [3], a latch-type comparator with a dynamic bias pre-amplifier is

implemented in a 65-nm CMOS process. The dynamic bias with a tail capacitor is
simple to implement and ensures that the pre-amplifier output nodes are only partially
discharged to reduce the energy consumption. The comparator is analyzed and
compared to its prior art in terms of energy consumption and input referred noise

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 5
 Design of a Low Volage Low Power and High Speed CMOS Comparator

voltage. First-order equations are presented that show how to optimize the pre-
amplifier for low noise and high gain. Both the dynamic bias comparator and the prior
art are implemented on the same die and measurements show that the dynamic bias
can reduce the average energy consumption by about a factor 2.5 for the same input-
equivalent noise at an input common-mode level of half the supply voltage.

Abozeid et al. [4], this paper presents a comparison in the consumed power between
different configurations of dynamic latched comparator used in low power Analog to
Digital (A/D) converters especially the successive approximation register (SAR)
which is used in many Electrical, Radio-frequency identification (RFID) and
biomedical applications. This comparison is in architecture, consumed power and
propagation time delay. The comparison is done under constant input referred offset.

Babayan-Mashhadi, et al. [5], the need for ultra-low power and area-efficient
analog-to-digital converters (ADCs) is pushing towards the use of low-voltage (LV)
dynamic clocked comparators to maximize power efficiency and speed. In this paper,
a delay analysis for a conventional body-driven LV dynamic comparator is presented.
Then based on the analysis results, the circuit of a conventional body-driven
comparator is modified for fast operation even in small supply voltages. Simulation
results in 90nm CMOS technology reveal that comparator delay time is remarkably
reduced. The maximum clock frequency of the proposed comparator can be increased
to 333 MHz and 50 MHz at supply voltages of 0.5V and 0.35V, while consuming
2.3μW and 184nW, respectively. The standard deviation of the input-referred offset
voltage is 5.1mV at 0.5V supply.

Bahmanyar, Parvin, et al. [6], this paper presents a new ultra-low power double-tail
latched comparator suited for biomedical applications. The proposed comparator
benefits from a positive feedback to achieve high resolution with low kickback noise.
It is shown by time analysis and simulation that the delay time is significantly reduced
compared to a conventional double-tail latched comparator. The presented circuit is
designed and simulated in 0.18-μm CMOS technology. The post-layout simulation
results show that the designed comparator consumes only 1.56 nW power, at 600 mV
supply voltage and 100 kHz clock frequency. This amount is 54.35 % of power
consumption of a conventional double-tail latched comparator with the same input

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 6
 Design of a Low Volage Low Power and High Speed CMOS Comparator

referred offset of 7.5 mV. Furthermore, the proposed circuit provides a self-
neutralization technique which results 8.8 % reduction of kick-back noise in
comparison to the conventional latched comparator. The maximum clock frequency
of this circuit is 200 MHz at 1 V supply voltage. The proposed circuit has a power-
delay product of 0.0172 fJ at 100 kHz clock frequency. The proposed comparator is
well designed to operate with supply voltages between 400 mV and 1 V.

Chan, Chi-Hang, et al. [7], this paper presents a reconfigurable, low offset, low
noise and high speed dynamic clocked-comparator for medium to high resolution
Analog to Digital Converters (ADCs). The proposed comparator reduces the input
referred noise by half and shows a better output driving capability when compared
with the previous work. The offset, noise and power consumption can be controlled
by a clock delay which allows simple reconfiguration. Moreover, the proposed offset
calibration technique improves the offset voltage from 11.6mV to 533μV at 1 sigma.
A prototype of the comparator is implemented in 90nm 1P8M CMOS with
experimental results showing 320μV input referred noise at 1.5GHz with 1.2V supply.

Halim et al. [8], this paper discusses the design and analysis of a latching comparator
using charge sharing circuit topology for low power and high speed. This topology
combines the good features of the resistive dividing comparator and the differential
current sensing comparator. This design will be focusing on the minimization of
propagation delay and the power dissipation of the comparator, which will improves
the comparator performance. Simulation results have been obtained using 0.18μm
technology, for a 100 MHz clocked comparator, considering 1.8V supply voltage and
1.8V input range. Design has been carried out in SILVACO EDA tool, the schematic
simulations are using Gateway SILVACO EDA tool and layout simulations are
verified using Expert SILVACO EDA tool.

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 7
 Design of a Low Volage Low Power and High Speed CMOS Comparator

CHAPTER 3
PROBLEM FORMULATION

Analog circuit design happens to be more complex to carry out the necessity of
reliability, where supply voltages need to be decreased according to the small
dimensions of the transistors. In ultra-deep sub-micron CMOS technology, the
threshold voltage of the devices are not scaled down at the same rate as the
technology, which in turn makes comparator design more difficult and challenging
with high speed and low power at low supply voltages due to limited input common-
mode range (Allen, et al., 2002) (Baker, et al., 2005) (Carusone, et al., 2011). To
compensate for this reduction in the rail voltage, larger size transistors are used in the
design, which in turn increases power and die size. Generally, there are two types of
solution to the problem are reported in the literature for the trade-off in the design of
low-voltage, low-power, and high-speed CMOS comparator. Firstly technological
(Providing a new technological solution) and secondly architectural (Providing new
circuit level modification or new architecture to fulfill the necessity in scaled
technology).

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 8
 Design of a Low Volage Low Power and High Speed CMOS Comparator

CHAPTER 4
PROPSOED METHODOLOGY

The proposed shared charge logic technique uses one pMOS pass transistor in
between cross-coupled inverter latch, i.e. between output terminals. This pass
transistor shares the charge and holds it approximately between supply and ground
during reset phase. This helps to reduce the delay and power. The simplified
schematic of shared charge transistor based set/reset technique is shown in Fig. 4.1.
The transient behavior of this technique is illustrated in Fig. 4.2.

Fig. 4.1: Block Diagram of Shared charge logic used in cross-coupled latch stage
using pass transistor

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 9
 Design of a Low Volage Low Power and High Speed CMOS Comparator

Fig. 4.2: Transient behavior of proposed shared charge logic during the reset phase

The functionality of the latch along with shared charge logic is as follows: Initially,
after the completion of evaluation phase (when CLK=Vdd) one of the output
terminals is at ground potential and other is at supply voltage level. Once the CLK
becomes LOW, reset/set phase starts. As the pMOS transistor is being used as a pass
transistor, it will be ON during this phase. In spite of charging or discharging, the
output terminals to supply voltage or ground level, this pass transistor shares the
charge of the output terminal. Due to the pMOS pass transistor, the output terminal
would be approximately at half of the supply voltage at the end of the reset/set phase,
which is not the case with the traditional techniques discussed so far. In the
subsequent evaluation phase the voltage level starts from the voltage level, which is
not ground level or supply voltage level, but approximately half of the supply level.
The addition of the pMOS pass transistor will not allow the output terminal to go
below the threshold voltage, which permits the latch to remain on at the start of the

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 10
 Design of a Low Volage Low Power and High Speed CMOS Comparator

evaluation phase. So, input signals can be compared faster during the regeneration
phase, which speeds up the operation of the latch and reduces the overall delay. Since
the pMOS pass transistor maintains the voltage approximately equal to the half of the
supply voltage at the output terminals, the output terminals need not discharged (to
ground) or charged (to the supply voltage). This phenomenon demands marginal
current and hence reduces the power consumption, which is not the case in the
traditional technique. In the traditional double tail dynamic latch comparators, pMOS
is used in the tail current of the latch, while the nMOS is used in the tail current of the
differential amplifier. To control the operation of such circuits, two separate control
signals CLK and CLK’ are required. The synchronization of the CLK and CLK’ is
mandatory to optimize the performance of the circuit. Use of nMOS transistor instead
of the pMOS transistor in the tail current of the latch stage in the proposed
architecture eliminates the requirement of two separate control signals i.e. CLK and
CLK’, which further nullifies the dependency of optimized performance of the circuit
on the control signal.

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 11
 Design of a Low Volage Low Power and High Speed CMOS Comparator

CHAPTER 5
SYSTEM COMPONENT

The proposed comparator is designed using Virtuoso tool, simulated and verified
using SPECTRE simulator (CADENCE) in 90nm CMOS process parameter at 27°C
temperature and with a clock frequency of 1 GHz. In order to have a fair comparison
and to show the improved performance of proposed comparator, the proposed
comparator1 along with reference comparators (referred comparator 2) is simulated in
a 90nm CMOS technology at 27°C temperature and 1 GHz of the clock frequency. In
all comparators, identical dimensions for transistors of the first (differential amplifier)
and the latch stage (cross-coupled inverter) are considered.

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 12
 Design of a Low Volage Low Power and High Speed CMOS Comparator

CHAPTER 6
EXPECT IMPLEMENTATION

The proposed comparator will inherited primarily from double tail current based
dynamic latch, so it retains all the advantages of the double tail current based
comparator. The proposed double tail current dynamic latch comparator uses the
concept of shared charge logic as a reset technique for the delay and power reduction
with use of a pMOS pass transistor. It possesses better performance than its
counterpart architecture. As there are two separate and independent tail currents,
optimization can be achieved independently for the performance in terms of delay and
power consumption. Moreover, there is no requirement of additional reset/set
transistor(s) as it is required in the other referred comparator architecture to reset/set
output terminals during reset/set phase, which ultimately reduces the power
consumption and die area. The equation for the delay is derived for the proposed
architecture and it is shown that the effective transconductance of the latch (Gm) is
increased, which in turn reduces overall delay. Finally, the APC technique for the
further reduction in the power is also explored for the future development of the
proposed architecture.

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 13
 Design of a Low Volage Low Power and High Speed CMOS Comparator

CHAPTER 7
CONCLUSION AND FUTURE SCOPE

7.1 Conclusion
Detailed analysis of performance parameters for the conventional dynamic latch
comparators (referred comparators), viz. Single tail current dynamic latch comparator
(STDLC), Double tail current dynamic latch comparator (DTDLC), Modified double
tail current dynamic latch comparator (MDTDLC), two-stage dynamic comparator
without an inverted clock (DTDLC-CLK), and Pre-amplifier with latch comparator
(Pre+Latch) is carried out in this thesis. Various reset techniques are also discussed
and analyzed for dynamic latch comparator and based on this study, a new reset
technique (shared charge logic) is proposed to improve the speed and power of
comparator. A new architecture of comparator with shared charge logic is proposed to
improve the performance parameter of the dynamic latch comparator. Analytical
expressions for the performance parameters are also derived. All these referred
comparators and proposed comparator have been simulated in Cadence Virtuoso
Analog Design Environment with 90 nm CMOS technology at 1 V of the supply
voltage.

7.2 Future Scope

In the course of this research and on consideration of the presented results, some
prospects for future work and some problems that may be the subject of further study
are marked. A few of the directions for future work are discussed below:
 Offset voltage optimization can be another topic of interest. It can be further
reduced by applying the offset minimizing technique e.g. auto zeroing
technique.
 Further power reduction can be achieved by applying a power reduction
technique e.g. adaptive power control.
 Other parameters like kick-back noise reduction and accuracy (dynamic and
static offset, noise, and resolution) can be one of the add-ons.

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 14
 Design of a Low Volage Low Power and High Speed CMOS Comparator

 The design of ADC can be carried out using presented high speed, low power,
and a low voltage dynamic comparator.

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 15
 Design of a Low Volage Low Power and High Speed CMOS Comparator

CHAPTER 8
REFERENCES

[1] Nagesh Mantravadia , S Roobanb , G Mani Shankarc , M Uday Suryad , N

Saikrishnae and A V Prabuf, “Design and Implementation of Low-Power
Dynamic Comparator”, Turkish Journal of Computer and Mathematics
Education, Vol.12 No.9 (2021), 538 – 544.
[2] N. Soumya, K. S. Kumar, K. R. Rao, S. Rooban, P. S. Kumar and G. S.
Kumar, “4-bit multiplier design using cmos gates in electric VLSI,”
International Journal of Recent Tehnology and Engineering, vol. 8(2), pp.
1172-1177, 2019.
[3] H. S. Bindra, C. E. Lokin, D. Schinkel, A.-J. Annema and B. Nauta, “A 1.2-V
Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input
Noise,” IEEE Journal of Solid-State Circuits, vol. 53, no. 7, pp. 1902-1912,
2018.
[4] Abozeid, K. M., M. M. Aboudina and A. H. Khalil. "Different configurations
for dynamic latched comparators used in ultra low power Analog to Digital
converters." 2014 International Conference on Engineering and Technology
(ICET). 2014. 1-6.
[5] Babayan-Mashhadi, Samaneh and Moein Sarvaghad-Moghaddam. "Analysis
and design of dynamic comparators in ultra-low supply voltages." 22nd
Iranian Conference on Electrical Engineering, ICEE, IEEE Proceeding. 2014.
255-258.
[6] Bahmanyar, Parvin, et al. "Design and analysis of an ultra-low-power double-
tail latched comparator for biomedical applications." Analog Integrated
Circuits and Signal Processing 86 (2016): 159-169.
[7] Chan, Chi-Hang, et al. "A reconfigurable low-noise dynamic comparator with
offset calibration in 90nm CMOS." IEEE Asian Solid State Circuits
Conference, A-SSCC. 2011. 233-236.
[8] Halim, Ili Shairah Abdul, Nurul Aisyah Nadiah Binti Zainal Abidin and
others. "Low power CMOS charge sharing dynamic latch comparator using
0.18μm technology." IEEE Regional Symposium on Micro and
Nanoelectronics, RSM, IEEE Proceeding. 2011. 156-160.

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 16
 Design of a Low Volage Low Power and High Speed CMOS Comparator

[9] Hill, J. M. and J. Lachman. "A 900MHz 2.25MB cache with on-chip CPU
now in Cu SOI." International Solid-State Circuits Conference, ISSCC, IEEE
Digest of Technical Papers. ISSCC. 2001. 176-177.
[10] Ho, Jeffrey and H. Cam Luong. "A 3-V, 1.47-mW, 120-MHz comparator for
use in a pipeline ADC." Asia Pacific Conference on Circuits and Systems,
IEEE Proceeding. 1996. 413-416.
[11] Hong, H. C. and G. M. Lee. "A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-
rail 8-bit Successive Approximation ADC." Journal of Solid-State Circuits,
IEEE 42 (2007): 2161-2168.
[12] Hsieh, Wei-Chih and Wei Hwang. "Adaptive power control technique on
power-gated circuitries." IEEE Transactions on Very Large Scale Integration
(VLSI) Systems 19 (2011): 1167-1180.
[13] Jeon, HeungJun, Yong-Bin Kim and Minsu Choi. "Offset voltage analysis of
dynamic latched comparator." 54th International Midwest Symposium on
Circuits and Systems, MWSCAS, IEEE Proceeding. 2011. 1-4.
[14] Jung, Y., et al. "Low-power and low-offset comparator using latch load."
Electronics Letters 47 (2011): 167-168. Johansson, Anders. "Investigation of
typical 0.13µm CMOS technology timing effects in a complex digital system
on chip." Institutionen för systemteknik, 2004.
[15] Kale, S. and R. S. Gamad. "Design of a CMOS comparator for low power and
high speed." International Journal of Electronic Engineering Research 2
(2010): 29-34.
[16] Kang, Sung-Mo and Yusuf Leblebici. CMOS Digital Integrated Circuits:
Analysis and Design. McGraw-Hill Higher Education, 2003.

Department of Electronics and Communication Engineering, Lakshmi Narain College of Technology, Bhopal (MP) 17