Low Power Sign-Off Checks and their

Efficient Engineering Change Order (ECO)

Implementation

Project Report

Submitted in Partial Fulfillment of the

Requirements for the Degree of

Master of Technology
in
Electronics and Communication Engineering
(VLSI Design)

Submitted By
Bhasha Shah
19MECV16

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING,
SCHOOL OF TECHNOLOGY, INSTITUTE OF TECHNOLOGY
NIRMA UNIVERSITY
AHMEDABAD-382481
May 2021
 Institute Certificate

This is to certify that the M.Tech thesis entitled ”Low Power Sign-Off Checks and
their Efficient Engineering Change Order (ECO) Implementation” submitted by
Bhasha Shah (Roll No: 19MECV16), towards the partial fulfillment of the require-
ments for the award of degree of Master of Technology in Electronics and Communication
(VLSI Design) of Nirma University, Ahmedabad, is the record of work carried out by her
under my supervision and guidance. In my opinion, the submitted work has reached a
level required for being accepted for examination. The results embodied in this M.Tech
thesis, to the best of my knowledge, haven’t been submitted to any other university or
institution for award of any degree or diploma.

Dr. Vijay Savani Dr. Usha S Mehta

Guide and Assistant Professor PG Coordinator M.Tech - VLSI
Institute of Technology, Institute of Technology,
Nirma University, Ahmedabad Nirma University, Ahmedabad

Dr. Dhaval Pujara Dr. Rajesh Patel

Professor and HOD Director
Institute of Technology, Institute of Technology,
Nirma University, Ahmedabad Nirma University, Ahmedabad

ii
 Company Certificate

This is to certify that the Major Project Report entitled ”Low Power Sign-Off Checks
and their Efficient Engineering Change Order (ECO) Implementation” submit-
ted by Bhasha Shah (Roll No. 19MECV16) as the partial fulfillment of the require-
ments for the award of the degree of Master of Technology in VLSI Design, Electronics
and Communication Engineering, Institute of Technology, Nirma University is the record
of work carried out by her under my supervision and guidance Intel Technology India
Pvt. Ltd.. The work submitted in our opinion has reached a level required for being
accepted for the examination.

Date: 13/05/2021
Place: Bangalore

External Guide
Mr. Asheer M Shaik
Engineering Manager
Intel Corporation

iii
 Undertaking for Originality of the Work

I, Bhasha Shah, Roll No. 19MECV16, give undertaking that the Major Project entitled
”Low-Power Sign-Off Checks and their Efficient Engineering Change Order
(ECO) Implementation” submitted by me, towards the partial fulfillment of the re-
quirements for the degree of Masters of Technology in Electronics and Communication
Engineering (VLSI Design), Nirma University, Ahmedabad 382 481, is the original work
carried out by me and I give assurance that no attempt of plagiarism has been made. I un-
derstand that in the event of any similarity found subsequently with any other published
work or any project report elsewhere; it will result in severe disciplinary action.

Date: 13/05/2021
Place: Ahmedabad

Bhasha Shah
M.Tech VLSI Student
Nirma University

iv
 Acknowledgement

It gives me immense pleasure in expressing gratitude to Dr. Vijay Savani, Assistant

Professor, EC Department, Institute of Technology, Nirma University for his valuable
guidance and continual encouragement throughout this work. I would like to thank Dr.
Usha Mehta, PG Coordinator of VLSI Design, EC Department, Institute of Technology,
Nirma university for providing this exhilarating opportunity and continual support in
reaching a higher goal.

The chain of my gratitude would be incomplete if I would forget to thank the first
cause of this chain, Dr. Dhaval Pujara, Hon’ble Head of EC Department, Institute
of Technology, Nirma University for his kind support and providing basic infrastructure
and healthy research environment.

It was a pleasure to be associated with the Intel Technology India Pvt. Ltd., and I would
like to thank the entire staff. I am grateful to Mr. Asheer Shaik, Engineering Manager,
Intel and Ms. Divya Suryadevara, Digital Design Engineer, for their valuable and
helpful guidance throughout the project.

I would also like to thank my Intel colleague Ms. Swathi Anumala (Digital Design
Engineer), Ms. Siri Chandana Kaveti (Digital Design Engineer) for their continuous
support and guidance throughout my M.Tech thesis project at Intel Corporation.

Bhasha Shah
19MECV16

v
 Abstract

The rapid demand of high performance and high-speed VLSI systems has shifted the fo-
cus of technocrats from traditional performance parameters like area and speed towards
the analysis of power consumption and optimization. Hence the power budget and man-
agement among the domains of the system is very much essential in ICs designed today.
Addressing dynamic leakage power requires new techniques and standards that fall out-
side the scope of traditional HDL-based flows. Implementing such low power techniques
at the RTL creates new design and verification challenges. Unified Power Format (UPF)
is an IEEE standard 1801-2009 that allows designers to describe low power design intent
and improve the way complex integrated circuits can be designed, verified and imple-
mented.

VC LP is a multi-voltage, static low power rule checker Synopsys Tool which will ver-
ify low power management techniques and UPF intended challenges like management
of power domains activity, control signals and supply rails availability and retention of
previous data for functional correctness in the design. Further, UPF is used to describe
the power intent with low power elements like Isolation Cell, Level Shifter Cell, Power
Switches and Retention Cell. Thus, VC LP will enable UPF to verify static low power
checks at early design cycle.

This thesis covers power management concepts of UPF and Static Low Power Checks
of the design. Sign-off Checks is done at the Synthesis and Place & Route stage of
physical implementation for further acceptance in the chip flow. The main aim of the
project is to simplify or develop an automated Engineering Change Order (ECO) for the
efficient analysis of the output reports and to reduce the runtime of the tool. The two
prominent scenarios of VCLP i.e., Wrong Domain Buffering and Level Shifter Insertion
has been taken care of, with the consideration of all corner cases. And finally, after
the identification of the intended instances the feedback ECO file will be provided as an
output of the TCL script.

vi
Contents

Institute Certificate ii

Company Certificate iii

Undertaking for Originality of the Work iv

Acknowledgement v

Abstract vi

List of Figures ix

List of Tables x

1 Introduction 1
1.1 Company Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.1 The Need of Low Power Design . . . . . . . . . . . . . . . . . . . 2
1.2.2 Power Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Power Management Concepts . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3.1 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.2 State Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.3 Isolation Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.4 Level Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Low Power Design Verification Flow . . . . . . . . . . . . . . . . . . . . . 8
1.5 Scope of The Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6 Timeline of the Training . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.7 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2 Literature Review 12
2.1 Previous Approaches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.2 Multi-supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.3 Multi Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.4 Power Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1.5 Speeding up power verification by merging RTL and UPF . . . . 15
2.1.6 Advanced UPF based voltage-aware verification for IOs . . . . . . 16
2.2 Details of Tools used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

vii
3 Power Management Architecture 18
3.1 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Supply Networks and Switching . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Supply Port States and Power State Table (PST) . . . . . . . . . . . . . 22
3.4 Isolation Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5 Level Shifter Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6 UPF Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4 Proposed Methodology 28
4.1 Static Low Power Checker Tool . . . . . . . . . . . . . . . . . . . . . . . 28
4.2 Wrong Domain Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2.1 Wrong Domain Buffering Architecture . . . . . . . . . . . . . . . 31
4.2.2 Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3 Level Shifter Instance Missing . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3.1 Level Shifter Instance Missing Error in VCLP . . . . . . . . . . . 34
4.3.2 Case I: When Source is Port . . . . . . . . . . . . . . . . . . . . . 34
4.3.3 Case II: When Source is Pin . . . . . . . . . . . . . . . . . . . . . 37

5 Results and Discussion 39

5.1 Wrong Domain Buffering Results . . . . . . . . . . . . . . . . . . . . . . 39
5.2 Level Shifter Instance Missing Results . . . . . . . . . . . . . . . . . . . . 41

6 Conclusion and Future Scope 42

Bibliography 43

viii
List of Figures

1.1 Power Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Active and Leakage Power at Lower Technology Node . . . . . . . . . . . 4
1.3 Power Management Concepts . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Retention Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Isolation Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6 Level Shifter Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.7 Normal Design and Verification Flow . . . . . . . . . . . . . . . . . . . . 9
1.8 Low Power Design and Verification Flow . . . . . . . . . . . . . . . . . . 10
1.9 Timeline of the Training . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1 Latch Based Clock Gating Schematic . . . . . . . . . . . . . . . . . . . . 13

2.2 Latch Free Clock Gating Schematic . . . . . . . . . . . . . . . . . . . . . 13
2.3 Voltage Aware RTL Code . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.1 Normal HDL Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.2 Different Power Domains in HDL Design . . . . . . . . . . . . . . . . . . 19
3.3 Supply Network in Different Power Domain . . . . . . . . . . . . . . . . 20
3.4 Power Switch in Domain P3 . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5 Power State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6 Isolation Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7 Level Shifter Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 VC LP Tool Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2 InstanceOffSinkOn Case in ISO BUFINV STATE Error . . . . . . . . . . 30
4.3 InstanceOffSinkOnIsolated Case in ISO BUFINV STATE Error . . . . . 30
4.4 SourceOffInstanceOn Case in ISO BUFINV STATE Error . . . . . . . . 30
4.5 Wrong Domain Buffering Architecture . . . . . . . . . . . . . . . . . . . 31
4.6 Wrong Domain Buffering Flow Chart . . . . . . . . . . . . . . . . . . . . 32
4.7 Schematic of High to Low Level Shifter . . . . . . . . . . . . . . . . . . . 33
4.8 Schematic of Low to High Level Shifter . . . . . . . . . . . . . . . . . . . 33
4.9 Level Shifter Instance Missing when Source is Port . . . . . . . . . . . . 34
4.10 Level Shifter Instance Missing when Source is Port . . . . . . . . . . . . 35
4.11 Level Shifter Insertion Function Flowchart . . . . . . . . . . . . . . . . . 36
4.12 Level Shifter Wrong Connection when Source is Pin . . . . . . . . . . . . 37
4.13 Level Shifter Wrong Connection Flowchart . . . . . . . . . . . . . . . . . 38

5.1 Single Wrong Domain Buffer Case . . . . . . . . . . . . . . . . . . . . . . 39

5.2 Chain Wrong Domain Buffer Case . . . . . . . . . . . . . . . . . . . . . . 40

ix
List of Tables

5.1 Output CSV file for Single Wrong Domain Buffer Case . . . . . . . . . . 39
5.2 Output CSV file for Chain Wrong Domain Buffer Case . . . . . . . . . . 40
5.3 Output CSV file for detailed cell information . . . . . . . . . . . . . . . . 41
5.4 Comparison table for LS INST MISSING . . . . . . . . . . . . . . . . . . 41

x
Chapter 1

Introduction

This is an introductory chapter of the thesis where we will discuss the need of low power
design and its early cycle low power verification. Also, ASIC design flow with power
intent specification is described with flowchart. Further, the scope, purpose and timeline
of the training at Intel India Pvt. Ltd. has been discussed.

1.1 Company Profile

1. History
Intel Corporation is an American multinational corporation and technology com-
pany headquartered in Santa Clara, California, in Silicon Valley. Intel was founded
on July 18, 1968, by semiconductor pioneers Robert Noyce and Gordon Moore, who
had left Fairchild Semiconductor. Originally called “NM Electronics” for Noyce and
Moore, the company purchased the rights to use the name “Intel,” short for Inte-
grated Electronics, from a company called Intelco.[1]

2. Mission and Vision

The mission of the company is to provide for customers’ greatest challenges with
reliable, cloud to edge computing, inspired by Moore’s Law. Its vision is to be the
trusted performance leader that unleashes the potential of data. Its values mainly
include Customer obsession, One Intel, Fearless, Truth, Transparency, Inclusion,
Quality, etc. They are a world pioneer in the design and manufacturing of essential
technologies that power the cloud and an increasingly smart, connected world.

1
 3. Products and Services
Intel has given so many products in the market like SRAMS and the microprocessor,
DRAM, x86 processors, the IBM PC, 386 microprocessors, Pentium, Itanium, Pen-
tium flaw, Solid-state drives, Supercomputers, Classmate PC, New mobile processor
technology, Ivy Bridge 22 nm processors, Car Security System, Haswell processors,
Self-driving cars, etc.

1.2 Motivation
With the advancement in Very Large-Scale Integration (VLSI) technology, there is a
constant reduction in the feature size of VLSI devices (i.e minimum transistor size). The
feature size decreased from about 0.25 µm in 1997 [1], to about 7 nm today [2]. Such
a continual miniaturization of devices has had a strong impact on VLSI technology in
several ways. One of those impacts is a drastic increase in power. The disadvantage of
increasing power and their consequences will be discussed in the following sections.

1.2.1 The Need of Low Power Design

A few years back, major challenges in the semiconductor design were area and perfor-
mance. Semiconductor industry were increasing speed as much as possible and reducing
the chip area to sustain in market. With increasing in the demand for high speed with less
area of portable electronics like Cell Phones, Smart Phones, Tablet, Laptops etc industry
started move towards the power performance as major concern. Every new generation is
expected to have more and more feature and longer battery life. To satisfy this require-
ments, we need active power management. As per the figure 1, active power management
is becoming important at 90 nm and it is necessary at below 65 nm.

1.2.2 Power Optimization

Physical design implementation in VLSI systems is the process of transforming logical
gates of the design into an equivalent layout representation considering all the design
constraints. The objective of automation in physical design is to carry out such trans-
formation efficiently using place & route tool so that the resulting layout satisfies the
topological, geometric, timing and power consumption constraints of the design. There
are many design variable inter-dependencies to be dealt with, perhaps the most important
is the trade-off between routability, timing, and power consumption. Optimizing for any

2
one may cause problems with the others. It is not possible to design and implement a
multi-million gate chip as an indivisible whole. The chip is partitioned into smaller blocks
known as partitions, implemented and integrated into full chip. Several implementation
level adaptations and power intent for these blocks are specified using industry standard
power format specification known as Unified Power Format (UPF).
As we all know that about the basics of power consumption and its types and we have
also shown it in figure 1.2. There are majorly two types of power and that is

Ptotal = Pstatic + Pdynamic

Figure 1.1: Power Calculation

The static power is because of leakage of current when the circuit is at steady state
and it depends on device technology node. The potential sources of leakage current
is majorly because of sub threshold current, gate leakage current and reversed biased
junction leakage. It is look up from the energy table in the library file. The basic
equation is shown below:
Pstatic = Ileakage ∗ VDD

The dynamic power comprised of two component: one is internal power and it is because
of short circuit current of device and second component is because of switching of device.
The switching power is the major part of power consumption. The basic switching power
equation is shown below:
2
Pswitching = α ∗ CL ∗ VDD ∗f

Here, in this the load capacitance is calculated from library file, Vdd is the supplied

3
voltage, f is the frequency at which the device is running and Alpha is the activity factor
which is calculated based on the activity of signals which will be less than 1.[2]

As per the figure 1.3, when we move towards the lower technology node, leakage power is
increased more and more compare to active power. It is become necessary below 65 nm
to require active power management.

Figure 1.2: Active and Leakage Power at Lower Technology Node

We need active power management so that it can control the power reduction techniques
to minimize the power consumption, especially leakage power. In the next section, we
will look more on power management concepts like power domains, isolation, retention
and level shifting in details.

1.3 Power Management Concepts

The power management scheme is built by the power architect of the SoC in order to
reduce the current power consumption of the chip. There are several common power
management techniques like multi-threshold design, Bus encoding, power gating, multi
Vdd approach and etc that are used in the design for power optimization. Also, some
basic buildings blocks in UPF power intent which are used by the power management
architect like power domains, isolation, retention, level shifting will be described here.[3]

4
1.3.1 Power Domains
In recent low power designs, some parts of the design works with a switchable supply
to reduce power consumption. Those parts are called switchable domains. The power-
management module is there which controls the power-up and power-down sequences and
it will enable the necessary power supply to that domain. These are the independently
powered regions. It toggles the control signals in the module to each of the analog switches
according to the power sequence and allows current to relevant power-domains by closing
that switches. The main idea of using power switches is to turn off heavily impacted
unused parts of the design and, as a result, gain low current consumption so eventually
reduction in power. Power domain enables the application of different power reduction
techniques in each regions.
In the following figure 1.3, total 4 power domains are present and power aware cells are
added for necessary power consumption. Here PD1 is the core unit which is always on
power domain and signals propagating from PD1 to PD2 requires level shifters while PD3
and PD4 have memory and retention cells so it works under gated power domain, hence
Isolation cells are required for the signals passing from PD3 to PD1.

Figure 1.3: Power Management Concepts

5
1.3.2 State Retention
State Retention cells as the name suggest it will retain the previous state of the block for
future use. Memories and other macros can be switched on and off in order to reduce their
current power consumption as they are being shut-down when their IP or power-domain
is in shutdown mode or when they are not in use. While some memories need to retain
or save their values for fast wake-up from the sleep mode. For these memories, only the
memory array stays powered on using a low power mode, and the peripheral interfaces
are powered off. The retention mode consumes a little more current than power-off mode
but allows fast recovery of the memory content after waking from sleep mode.

Figure 1.4: Retention Cell

In figure 1.4, we have shown the retention cell that are used in power intent specifications
where save and restore control signal will be given from power management unit and
retention voltage supply will also be connected to the block. A register’s power is turned
off when its power-domain/IP is turned off. Some registers also need to retain their values
after being turned off. These are called retention registers, which restore their previous
active value after being shut down which are important for fast wake-up.

1.3.3 Isolation Cell

Isolation is typically used to isolate signals propagating in a design power domain whose
power is shut off from a part of the design which still remains powered on and able to
read those signals. Because off domain gives unpredictable values at active domain so
that propagation needs to be isolated.

6
An isolation cell is needed when a signal comes from a switchable power domain, to any
other powered-on domain. This cell prevents a floating value from shut down domain to
come to powered on domain. When its control signal is enabled, the isolation cell outputs
a fixed logic value, 0 or 1. We have AND gate cell for clamp 0 and OR based cell for
clamp 1. When its input and output sides are both powered on, the isolation cell behaves
as a buffer. To define an isolation strategy, we need to specify the power domain where
this cell is inserted, its source and sink, its output value, its power supply, its control
signal and the elements impacted by this cell as shown in the figure 1.5.

Figure 1.5: Isolation Cell

Isolation strategies means adding the isolation cells either at the source, sink or both
power domain so that a particular power domain is isolated from the rest environment
of the design. Isolation cells are logic AND/OR gates that decide the values of a power
domain’s input or output port when the domain is powered down. These cells are impor-
tant because each power domain represents a silicon design area comprised of particular
features, and if we are getting floating value at the output then each feature corresponds
may not work properly. When one domain is turned OFF, the floating value coming
out of the shutdown domain shall be clamped to predefined logic, as it is still associated
electrically to other domains.

1.3.4 Level Shifter

A level shifter is needed in between when a signal crosses two power domains which have
different power supply voltage. For example, when signal passing from 0.8 V to 1.2 V
of power domain. This component converts a signal from one voltage to another and

7
avoid the mismatch. Thereby, a logic value is seen besides an unambiguous value by the
domains the related signal might cross. As per the shown in figure 1.6, there are two

Figure 1.6: Level Shifter Cell

power domains and level shifter is added in between these domains. There is a high to
low and a low to high Level Shifter at the cross over. To define a level shifter strategy,
we need to specify in which power domain the level shifter is inserted and which signals
are impacted by the level shifter.

1.4 Low Power Design Verification Flow

In this section, we will discuss about normal ASIC design flow and where we are consid-
ering power implementation in this flow. We will also see the low power design and veri-
fication flow by adding power intent specification using Unified Power Format (UPF).[4]
Logic Implementation is done using standard cell and macros. RTL design and standard
cell library is used for logic implementation and after synthesis we get the netlist. We
can also do logic equivalence checking of RTL design and generated netlist.

As per the figure 1.7, we have shown normal design flow. Here, RTL design captures the
design intent which can be described using hardware description language like Verilog,
System Verilog, etc. RTL design also drives the functional verification and it is the main
input for driving synthesis.

After the logic implementation, place and route completes the physical implementation
of the design. This step produces the manufacturing data. In Normal design flow, power
management is considered at this physical implementation stage but for low power design

8
 Figure 1.7: Normal Design and Verification Flow

flow it should be considered at earlier stage of the design flow.

Low power intent specification specified using Unified Power Format (UPF). UPF is IEEE
standard format use to define power management and to minimize power consumption,
especially leakage power. It is based upon TCL language and can be mixed with Non -
UPF TCL. UPF can be used for verification and implementation purpose like synthesis,
DFT, P& R etc.

As per the shown in figure 1.8, RTL is inserted with UPF to define power architecture
for a given implemented design. By doing RTL + UPF verification, we can ensure that
Power Architecture is complete and consistent with expected power states of the design.
We can also ensures that design will work correctly under power management with this
power architecture. At every stage we can update the UPF and we can implement it for
synthesis purpose.

9
 Figure 1.8: Low Power Design and Verification Flow

1.5 Scope of The Training

The main objective of the training programme is to gain practical knowledge and valuable
experience in the VLSI Industry, with the world-changing company - Intel Corporation.
The great outcome of this training is to gain the ability to analyse, recognize, frame and
model challenging problems and finding & executing the engineering solution. Following
are the objectives of the project:

1. To understand Low Power Techniques

2. To learn of UPF at block as well as chip level
3. To observe and analyse the static checks in VC LP Tool
4. To implement IEEE Standard Unified Power Format (UPF) methodology in Multi-
voltage driven chip
5. To diminish the manual effort of analysing power supply in wrong domain buffer
scenario
6. To automize the Level Shifter insertion in VC LP
7. To rewire the connection in the design to reduce VCLP error counts

10
1.6 Timeline of the Training

Figure 1.9: Timeline of the Training

The above figure 1.9 describes the timeline of the training at Intel(sign-off convergence
project) as well as Automation project to increase tool efficiency. Here the milestones
are shown by the vertical black strips and the brief work is described in left column.

1.7 Organization of the Thesis

Chapter 2 describes the literature survey of previous low power methodologies like lock
Gating (Both latch based and latch free based design), Multi-supply Voltage (SVS, MVS,
DVFS), Multiple Threshold (HVT, SVT, LVT) and Power Gating. One ITC paper of
Low Power Verification techniques incorporating RTL and UPF is discussed.

Chapter 3 consists of explanation of the Low Power elements and Power management
architecture that nowadays industry are implementing. It describes the UPF code of
isolation strategies, Level shifting strategies and retention strategies.

Chapter 4 consists of the automation approach involved in VC LP tool for efficient

analysis of the buffer and inverter cells which comes under the tag ISO BUFINV STATE.
One more approach of inserting level shifter is discussed here with rewiring of the design
which will reduce the error count of LS INST MISSING.

Chapter 5 consists of the exhaustive results of instance name, expected power supply,
type of instance and preferred solution in the output csv ECO file. It will also compare
the manual approach and automation efficiency.

At last we have also shown the conclusion and future scope followed by the references of
the thesis.

11
Chapter 2

Literature Review

One of the most important factors affecting power consumption in the design is the choice
of circuit technique for standard cells, logic, latches and flip-flops. So in this chapter we
will discuss the previous low power methodologies implemented in the circuits and how
verification is done by merging RTL and UPF.

2.1 Previous Approaches

Following are some of the low power techniques that has been implemented in previous
design circuits:

1. Clock Gating (Both latch based and latch free based design)
2. Multi-supply Voltage (SVS, MVS, DVFS)
3. Multiple Threshold (HVT, SVT, LVT)
4. Power Gating

2.1.1 Clock Gating

Clock gating is one of the key techniques in which switching activity of flops are reduced
by gating the clock input, viz. the clock pin of the register bank will be activated only
when a data movement is required, and it is implemented by gate-level power synthesis
tools. The critical design step is the placement of the gating circuit.[5]

1. Latch based Clock Gating The latch-based clock gating method inserts a level-
sensitive latch to the design to hold the enable signal from the active edge of the
clock until the inactive edge of the clock. Since the latch captures the state when
enable signal is on and holds it until the complete clock pulse has been generated.

12
 Figure 2.1: Latch Based Clock Gating Schematic

2. latch free based Clock Gating The latch-free clock gating style uses a simple
AND or OR gate which depends on the edge on which flip-flops are triggered.
So AND/OR gate can hold the unchanged clock signal till the enable pin is on.
Here if enable signal goes inactive in between then the clock output can terminate
prematurely which is a drawback of latch free method.

Figure 2.2: Latch Free Clock Gating Schematic

2.1.2 Multi-supply Voltage

Multi VDD approach is to partition the internal logic of the chip into multiple volt-
age regions or power domains, each with its own supply. It is based on the realization
that in a modern SoC design, different blocks have different performance objectives and
constraints. Level shifters are used to provide full rail-to-rail voltage required for the
destination power domain, so that there is no ambiguity seen by receiving logic when
signal is driven from the driver logic of different power domain.[6]
Multi voltage design techniques is useful when trade off between energy and speed is taken
into consideration. As shown in the figure 1.5 Level shifter are inserted to propagate the

13
correct signal from different range of supplies. The approaches to voltage scaling are:

1. Static Voltage Scaling (SVS): Different blocks or subsystems are given various or
permanent power supply voltages as per the need.
2. Multi-level Voltage Scaling (MVS): This method is an addition in SVS where a block
or subsystem is switched between two or more voltage levels or power domains. In
this case few, fixed, discrete levels are supported for different operating modes.
3. Dynamic Voltage and Frequency Scaling (DVFS): This method is an addition in
MVS where a larger number of voltage levels are dynamically switched between dif-
ferent blocks and partitions to follow changing workloads with dynamic frequencies.

2.1.3 Multi Threshold

In Multi Threshold Technique, the transistors are assigned different threshold voltages in
order to optimize power consumption and delay.[7] In order to achieve high speed with
low supply voltages, the threshold voltage must be reduced accordingly. To alleviate the
problem of subthreshold leakage currents, and also to reduce the delay in some parts of
the design. We need to have a variable threshold like LVT cells in timing critical paths,
and HVT cells where leakage prevention and power consumption is more required than
timing.
There is a trade off between leakage power and timing while using these cells, so eventually
that depends on the specification. Low-Vt cells have better timing but higher leakage
power while High-Vt cells have lower leakage but worse timing.

2.1.4 Power Gating

Power gating is used to turn off blocks that do not require power, it is used to reduce the
overall leakage of the chip. The basic strategy of power gating is to provide two modes
1. Low power mode
2. Active mode
The most challenging part in designing the power gating for a logic block is the design
of the switching network and power gating controller.[5] Power Switches based on switch
control signals are used to switch output power from it to different power states based
on the power modes specified in the design. The input and output supply port and the
power domain in which it operates can be passed as attributes to it. After creation of

14
the power domains, supply networks have to be designed which specifies the supply nets
which are connected to the design elements viz. lower order hierarchical blocks and also
to which supply ports these nets are getting the power form.
Power gating also requires power switches to generate gated supply form normal (primary)
power supply. It is also used to set the supply states of the output supply port of the
power switch. So the elements in these derived domains can have both the supplies and
hence can be used for AON Cells. Next Port states are used to specify different voltages
of the ports and their respective port state names. Further strategies have to be specified
for retaining a power state after the power down mode. For isolating the powered up and
powered down domains, and for level shifting in case of variable operating domains.

2.1.5 Speeding up power verification by merging RTL and UPF

In this paper[8], merging equivalent power domains by following types: inter-scope do-
main equivalence, intra-scope domain equivalence, behavior driven domain equivalence
for RTL designs with UPF was discussed. Some of the low power checks include: whether
the correct select signal is sent to the power switch, next to check whether there is any
missing isolation cell or level shifter cell present.
Similar to block wise design of the RTL, UPF is also designed in smaller blocks and
pieces, hence the power domains are enumerated after all the UPF sources are fetched,
due to this redundant power domains would be created which would be clubbed to form
one single domain. The three types of merging strategies are developed to explore:
(1) intra-scope domain equivalence, (2) inter-scope domain equivalence and
(3) behavior-driven domain equivalence.
The Intra-scope domain equivalence represents power domains located in the same de-
sign module connect to the same power supply example: pipeline register instances in the
CPU processor. The Inter-scope domain equivalence represents power domains present
in different design module but connect to the same power supply port. Behavior-driven
domain equivalence implies that supplies of different power domains but have the same
functional behavior such as encoder and decoder of a UART module. The Supply net-
work object include supply ports, supply sets, supply nets, supply switches. Two main
functions for power verification: draw flatten power map and report impacted signals.
Each power domain can have its own separate UPF file or can be grouped.

15
Grouping equivalent PDs must be done such that the number of cross-boundary ports
should decrease else no significant speed-up can be obtained for verification. At the first
intra-scope domain equivalence in each power design scopes, and then after updating
the domain database it checks for inter-scope domain equivalence and behavior driven
domain equivalence.

2.1.6 Advanced UPF based voltage-aware verification for IOs

In this paper[9], one recent verification approach i.e. Voltage Aware Verification has
been discussed. The main motivation behind this method is the IO supplies inside Power
Aware models are ‘reg’ type so does not completely represent the supply’s analog behav-
ior. So for full information and characteristics of the signal we are intended to use voltage
aware verification.

Voltage-Aware verification is a solution which uses ‘real’ voltage variable which keeps
watch on the actual analog values at each point. Complex features such as core-off,
IO-off and hibernate modes are represented only using actual analog voltage values. So
for making modes to function well, we need Voltage Aware Verification Model. Voltage
aware model access the real supply voltage variable to validate the design. RTL is made
power aware by writing get supply voltage declaration as shown in the figure 2.3. They
can access the voltage level of the supply net type by adding the suffix .voltage. Thus,

Figure 2.3: Voltage Aware RTL Code

16
Voltage Aware model can closely mimic silicon behavior at the early RTL stage and
reduces the risk for missed power-management issues. The proposed VA methodology
enables effective verification of advanced low power features such as core-off and IO-off
modes. As a result a more accurate verification is achieved at RTL stage.

2.2 Details of Tools used

SoC designs utilize low power design methods to enable support for cutting-edge power
management required in many of the present electronic products, from mobile devices to
servers and networking. Advanced low power techniques such as power gating, bus en-
coding, retention, low-VDD standby, and dynamic voltage scaling (DVS) employ voltage
control to enable fine-grained power management, and are seeing expanding selection.
Due to the notion of low power design architectures and behavior, verification and sign-
off for low power designs are dramatically more challenging than for always-on designs.

The VC LP™ static low power verification solution includes more than 400 checks
and gives full-chip sign-off capacity and performance for complete low power static sign-
off.[18]

The script for automation of VCLP Checks is written in Tool Command Language.
Tcl is a high-level, general-purpose, interpreted, dynamic programming language. It was
designed with the goal of being very simple but powerful. It is available across Unix,
Windows and Mac OS platforms.

Thus, the amalgamation of power intent to the RTL code is a very effective way for
early stage Power Verification. Thus, taking further the previous methodologies and
techniques into consideration, we finally will discuss which type of architecture we will
use for proposed methodologies. This architecture consists of multi level power supply
and power domains.

17
Chapter 3

Power Management Architecture

In this chapter [11], We have taken one simple design with main module as design and
inside this we have three different module P1, P2 and P3. This design figure is shown in
figure 3.1. We have applied the power management architecture on this design described
using Unified Power Format (UPF). The detailed PM block details are described in next
sections.

Figure 3.1: Normal HDL Design

3.1 Power Domains

A power domain is a collection of design elements that share a primary power and ground
supply net. The logic hierarchy level where a power domain is created is called the scope
of the power domain. Any design elements that belong to a power domain are said to be
in the extent of that power domain. A design element can be in the scope of a number
of power domains, it can only be in the extent of exactly one power domain.[10]
To help manage the complexity of the supply network specification, power domains are
defined to group elements from the logic hierarchy that share common supply needs. By
default, all logic elements in a power domain use the same primary supply. Additional

18
supplies may be defined to serve different uses in a power domain.

Figure 3.2: Different Power Domains in HDL Design

In this code snippet, we have created three power domain PD TOP, PD COMP and
PD MOD using create power domain UPF command. The visualization of code in design
is shown in figure 2.2.

3.2 Supply Networks and Switching

A Power Network consists of supply ports, supply nets, supply sets and power switches.
It represents the power supply of the design at a high abstraction level. A supply port is a
power supply connection. A supply net can be either a power or ground net connected to
a supply port. It crosses different levels of the design hierarchy. Each switchable domain
needs a power switch to be turned on and off. The output supply net of a power switch
must also be created.
In power supply network, upper shown snippets will create the power supply port, supply
net and connect this ports and nets. Using set domain supply net command, we can set

19
 Figure 3.3: Supply Network in Different Power Domain

the domain supply net to different modules. Here in module P1 we have set Pwr1 and
Gnd net supply. These power supply connections we can visualize in figure 3.3.
Power switch is like a controller from power management unit which provides the current
voltage and shut down power supply according to the control signal from PMU (Power

20
 Figure 3.4: Power Switch in Domain P3

Management Unit). During simulation, a power switch will react to the process which is
sensitive to changes in its input and control ports. Every time the signals on the control
ports change, their value is compared with the corresponding on-state Boolean functions.
If the value of the control signals match one of the on-state functions, the switch is closed,
which causes the on/off state, full/partial state, and voltage value at its input port to
propagate to the output port. If the control signals do not match any of the on-state
functions, the switch is opened turning off the output port. If any of the control signals is
X or Z, or the control signals match one of the error-state Boolean functions, the behavior
of the power switch is undefined, in this case implementations may issue a warning or an
error. Power switch code is shown in upper snippet and its visualization can be seen in
figure 3.4 domain P3.

21
 3.3 Supply Port States and Power State Table (PST)
A power state table is used for implementation specifically for synthesis, analysis, and
optimization. It defines the legal combinations of states, i.e., those combinations of states
that can exist at the same time during operation of the design.[12]

The power state table has no simulation semantics. It is tool dependent whether simu-
lation tools report an error if an illegal (unspecified) combination of states occurs. Each
port in the design can have one or more states but only one state at any given time. The
port-state and the related voltage value are specified in a Power State Table. The PST
also lists all the combinations of states of power switches in the design.

1 add_port_state VDD1 \
2 - state { ON_18 1.8}
3 create_pst DESIGN_PST \
4 - supplies { VDD1 VDD2 Vdd1_sw VSS }
5 add_pst_state - pst DESIGN_PST \
6 - state { ON_18 ON_10 ON_18 ON_00 }

Figure 3.5: Power State Table

As per the code snippet above, we can create the port state using add port state com-
mand. We have only shown one port state and like this we can create as many port state
we want. Now we have different port state for different ports. Using create pst command
we can create the power state table of all the ports and all the combinations are shown
in figure 3.5. Using PST, we can able to analyze where to add isolation strategies and
where to add level shifting strategies.

22
 3.4 Isolation Strategies
Isolation strategies means adding the isolation cells either at the input, output or both
so that a particular design is isolated from the rest of the design. Isolation cells are
logic gates that determine the values of a power domain’s input or output port when the
domain is powered down .

• set isolation

1 set_isolation ISO_COMP - domain PD_COMP \

2 - a pp li es _t o_ ou tp ut s - clamp_value 0 \
3 - is o l at i o n_ p o we r _ n et Pwr1 \
4 - isolation_ground_net Gnd

• set isolation control

1 s e t _ i s o l a t i o n _ c o n t r o l ISO_COMP \
2 - domain PD_COMP \
3 - isolation_signal iso_en \
4 - isolation_sense high \
5 - location self

Figure 3.6: Isolation Strategies

As per the code snippet above set isolation command will set the isolation strategies in
PD COMP domain. We have set the clamp value to 0. The control signal iso en is added
by set isolation control command.

23
3.5 Level Shifter Strategies
When a signal crosses two different power domains with different power supplies which do
not have the same supply voltage, a level shifter cell is necessary to be added between the
cross over. This cell converts a signal from one voltage to another and make an alignment
between the power domains. Thereby, a logic value is seen instead of an ambiguous value
by the receiver domain and the related signal might cross successfully.

Figure 3.7: Level Shifter Strategies

Level Shifter strategies can be analyzed by looking at the Power State Table in figure
3.5. When we look at the State 1, both the VDD2 and Vdd1 sw are n ON condition.
Both these domains are working at different power supply. When output signals from
goes from VDD2 domain to Vdd1 sw domain, we need Level Shifter to be placed and
it can be places using set level shifter command as per code snippet shown above. We
can also set which type of LS we want either Low to High or High to Low or Both. The
visualization of above code in power domain is shown in figure 3.7.

24
 These all the power domain commands, supply network - switching commands, PST,
isolation and level shifting commands are grouped together and made the power intent
specification in UPF file of our normal RTL design. The full UPF code of our design is
mentioned in the next section.

3.6 UPF Code

1 set_design_top design
2 c re a t e_ p o w er _ d om a i n PD_TOP -include_scope
3 c re a t e_ p o w er _ d om a i n PD_COMP -elements { comp }
4 c re a t e_ p o w er _ d om a i n PD_MOD -elements { m3 }
5

6 cr ea te _s up pl y_ po rt VDD1 -direction in
7 cr ea te _s up pl y_ po rt VSS -direction in
8 cr ea te _s up pl y_ po rt VDD2 -direction in -domain PD_COMP
9

10 cre ate_supply_n et Pwr1 -domain PD_TOP

11 cre ate_supply_n et Gnd -domain PD_TOP
12 cre ate_supply_n et Pwr2 -domain PD_COMP
13 cre ate_supply_n et Gnd -reuse -domain PD_COMP
14 cre ate_supply_n et Pwr1 -reuse -domain PD_COMP
15

16 co nn ec t_ su pp ly _n et Pwr1 -ports { VDD1 }

17 co nn ec t_ su pp ly _n et Pwr2 -ports { VDD2 }
18 co nn ec t_ su pp ly _n et Gnd -ports { VSS }
19

20 s e t _ d o m a i n _ s u p p l y _ n e t PD_TOP \
21 - pri ma ry _p ow er _n et Pwr1 \
22 - p ri m a ry _ g ro u n d_ n e t Gnd
23

24 s e t _ d o m a i n _ s u p p l y _ n e t PD_COMP \
25 - pri ma ry _p ow er _n et Pwr2 \
26 - p ri m a ry _ g ro u n d_ n e t Gnd
27

28 cre ate_supply_n et VDD1_sw -domain PD_MOD

29 cre ate_supply_n et Pwr1 -reuse -domain PD_MOD
30 cre ate_supply_n et Gnd -reuse -domain PD_MOD
31

25
32 cre ate_logic_po rt swCtl
33 create_logic_net swCtl
34 con nect_logic_n et swCtl -ports swCtl
35

36 c re a t e_ p o w er _ s wi t c h SW \
37 -domain PD_MOD \
38 - ou t p ut _ s up p l y _p o r t { swout VDD1_sw } \
39 -i np ut _s up pl y_ po rt { swin Pwr1 } \
40 -control_port { swctrl swCtl } \
41 -on_state { SWon swin swctrl } \
42 -off_state { SWoff ! swctrl }
43

44 s e t _ d o m a i n _ s u p p l y _ n e t PD_MOD \
45 - pri ma ry _p ow er _n et VDD1_sw \
46 - p ri m a ry _ g ro u n d_ n e t Gnd
47

48 add_port_state VDD1 -state { ON_18 1 .8 }

49 add_port_state SW / swout \
50 -state { ON_18 1 .8 } \
51 -state { OFF off }
52 add_port_state VDD2 \
53 -state { ON_10 1 .0 } \
54 -state { OFF off }
55 add_port_state VSS -state { ON_00 0 .0 }
56

57 create_pst DESIGN_PST -supplies { VDD1 VDD2 VDD1_sw VSS }

58

59 add_pst_state state_1 -pst DESIGN_PST \

60 -state { ON_18 ON_10 ON_18 ON_00 }
61 add_pst_state state_2 -pst DESIGN_PST \
62 -state { ON_18 OFF ON_18 ON_00 }
63 add_pst_state state_3 -pst DESIGN_PST \
64 -state { ON_18 ON_10 OFF ON_00 }
65 add_pst_state state_4 -pst DESIGN_PST \
66 -state { ON_18 OFF OFF ON_00 }
67

68 cre ate_logic_po rt iso_en

69 create_logic_net iso_en
70 con nect_logic_n et iso_en -ports iso_en

26
71

72 set_isolation ISO_COMP \
73 -domain PD_COMP \
74 -applies_to outputs \
75 -clamp_value 0 \
76 - i s o l a t i o n _ p o w e r _ n e t Pwr1 \
77 - i s o l a t i o n _ g r o u n d _ n e t Gnd \
78

79 s e t _ i s o l a t i o n _ c o n t r o l ISO_COMP \
80 -domain PD_COMP \
81 -is olatio n_sign al iso_en \
82 -isolation_sense high \
83 -location self
84

85 set _level_shift er LS_COMP -domain PD_COMP -applies_to outputs

86 -rule both -location self

Thus in this chapter, we discussed how to write UPF code with all low power management
concepts.This required power intent specification is described using UPF and the full UPF
code is shown above. We have added Isolation strategies, Level Shifting Strategies, Power
Switches in these specifications based on the Power State Table and different power ports
in power domain. In the next chapter we will look at the proposed low power UPF based
methodology implemented for Wrong Domain Buffering and Level Shifter Insertion. We
will see the tools required for simulation and synthesis of our design.

27
Chapter 4

Proposed Methodology

The increase in design complexities and shrinking technologies have brought in a new set
of challenges in System-on-Chip (SoC) verification. This brings in a need for a unified
and integrated verification environment with seamless flow and reuse of the information
across different domains/levels to achieve faster results. In this chapter, we will discuss
the tool that we are using and two automation i.e. Wrong Domain Buffering and Level
Shifter Insertion done at the VCLP level using TCL script.

4.1 Static Low Power Checker Tool

VC LP is a multi-voltage, static low power rule checker that allows verification of multi-
voltage designs for power optimization and management [13]. Key features of VC LP
includes:

1. Power Intent Consistency Checks

Performs syntax and semantic checks on the UPF file before confirming as Golden
reference.
2. Signal Corruption Checks
Detects the violating power architecture/RTL at the gate-level netlist.
3. Structural Checks
Validates insertion and connection of power switches, isolation cells, level shifters,
retention registers, and always-on cells through out the implementation flow from
synthesis to place & route.
4. Power and Ground (PG) Checks
Check the Power and Ground consistency against the UPF specification for power

28
 network routing on physical netlists.
5. Functional Checks
Validates the correct functionality of power aware cells in the design.

VC LP takes in an RTL (Verilog, VHDL, SVD), netlist (Verilog) or post-layout netlist of

the design. It reads the Liberty DB file for resolving, elaborating the design, recognizing
special cells and annotating power connections. It accepts the power intent specified in
the UPF.

As an output, VC LP creates a log file, an error and warnings report for all violations
related to low power static rule checks. VC LP provides a Tcl infrastructure that helps
in debugging these violations. You can also use the VC LP GUI to debug your design
violations. As shown in the figure 4.1 the input to VCLP tool is the upf power intent file
at both synthesis and Place and Route stage, the RTL netlist file, and library referencing
file and the output is logs, reports and GUI for detailed error debugging.

Figure 4.1: VC LP Tool Block Diagram

Further in this chapter, TCL script for the Sign-off tag ISO BUFINV STATE of VC LP
has been discussed in detail.The main aim is to reduce the report analysis time of the
VCLP.

29
4.2 Wrong Domain Buffering
The error ISO BUFINV STATE will pop up in VC LP tool while sign-off checking if
Electrical supply connection for buffer/inverter Instance doesn’t match between source
SourceInfo and sink SinkInfo. This will cause the design to consume excess leakage power,
function improperly or not function at all, as the intended signal is not properly received
by the sink. Following can be the cases while violation is reported:

1. InstanceOffSinkOn Both LogicSource and LogicSink are ON, and corruption

reaches to LogicSink due to Instance OFF. Schematic is shown in the figure 4.2.

Figure 4.2: InstanceOffSinkOn Case in ISO BUFINV STATE Error

2. InstanceOffSinkOnIsolated Both LogicSource and LogicSink are ON, and In-

stance is OFF but corruption do not reach LogicSink due to Isolation cell present.
Schematic is shown in the figure 4.3.

Figure 4.3: InstanceOffSinkOnIsolated Case in ISO BUFINV STATE Error

3. SourceOffInstanceOn Either LogicSource or LogicSink or both are OFF. Schematic

is shown in the figure 4.4.

Figure 4.4: SourceOffInstanceOn Case in ISO BUFINV STATE Error

30
4.2.1 Wrong Domain Buffering Architecture
Here an automated Engineering Change Order (ECO) Analysis file is developed here to
reduce the runtime of the tool and report analysing. The prime focus would be on the
design of the supply network and the type of cells from specified source and destination.
And finally, the following prominent bugs like Missing Expected Power Supply in the
Power Domain and Incorrect Supplies to Always ON Buffers will be identified, analysed
and updated in the feedback ECO File.
As shown in the figure 4.5, the source and sink are having 1.2 V power supply while
instances in between have 0.8 V power supply, so here there comes the range of voltage
where the source and sink will be ON and instances in between will be OFF, so the signal
will not propagate properly which results into bogus value and functionality mismatch.
So this kind of scenarios should be the utmost priority to resolve.

Figure 4.5: Wrong Domain Buffering Architecture

The scope of the developed script is to decrease the manual efforts in analysing the
buffers and inverts cells which are present between specified source to sink. As shown in
the figure below, in the scenarios for Wrong Domain Buffer, there might be possible that
chain of 50-60 buffers/inverters are there in between to fetch and check for power supply
for all.

4.2.2 Flow Chart

As shown in the figure 4.6, the input to this automation script will be the ISO BUFINV STATE
report generated by VC LP GUI where useful information like source and sink name,
source and sink power supply, chain length if any will be there. Further by applying
the automation solution we will get one csv file as an output which will indicate all the
buffers/inverters instances and there expected power supply to avoid this error.

31
There exist some cases when there is sub-branches in the intended path, there it becomes
challenging to get the correct chain of instances from source to sink.

Figure 4.6: Wrong Domain Buffering Flow Chart

Following corner cases has been also taken care of:

1. Net with more than one fan-outs

2. Physical Voltage layer is not present to make always on cells
3. All the buffers does not have same voltage supply

Following are the preferred feedback solutions given in the output file:

1. Make the BUFF/INV always on cells, give the top domain power as backup supply
2. Change the hierarchy of the chain
3. Remove the chain and connect source and supply with higher metal level

32
4.3 Level Shifter Instance Missing
Connecting power domains at different voltage domains can cause timing inaccuracy and
signal propagation design issues. Level Shifter cell are added to ensure correct commu-
nication between power domains, operating at different voltage levels. Level shifters are
inserted automatically by the tool during synthesis once the location and usage rules have
been defined in the UPF. Commonly, there are two types of level shifters.[11]

1. High to Low Level Shifter: A signal from higher to lower voltage supply does
not create any latch-up or breakdown issues as it is just a buffer structure which
is simply a “better”, faster edge compared to normal CMOS logic high or low level
switching levels. As shown in the figure 4.7, the high-to-low level shifter is a buffer,
so its impact on timing is small.

Figure 4.7: Schematic of High to Low Level Shifter

2. Low to High Level Shifter: A signal from lower to higher voltage supply degrades
the rise and fall times at the receiving inputs which leads to higher switching cur-
rents. A slow transition time means that the signal spends more time near threshold
voltage (VT ), causing more short circuit current. This design as shown in the figure
4.8 takes a buffered and an inverted form of the lower voltage signal and uses this
to drive a cross-coupled transistor structure running at the higher voltage.

Figure 4.8: Schematic of Low to High Level Shifter

33
4.3.1 Level Shifter Instance Missing Error in VCLP
The error LS INST MISSING will pop up in VC LP tool if any signal is propagating
in power domains which have different voltage area and Level Shifter Instance is not
present in the design. Level shifting protection is required for this crossover, based on
the power states defined for the supplies associated with the source and sink of this signal.
A missing level shifter can cause the design to function improperly or not function at all.
As a solution we have to ensure that all required level shifter instances have been properly
inserted, according to the specified level shifter strategy in UPF file. This error will cause
mismatch in the power intent of the design and tool will mistakenly connect the defined
pin to non-LS path. The automated TCL script will ensure the case of heterogeneous
nets too. The net with multiple fan-out from Logic Source to Logic Sink where sinks are
in more than one PD is known as heterogeneous net. These cases will be discussed in
further subsections.

4.3.2 Case I: When Source is Port

For the VCLP error LS INST MISSING when the source instance is a port, the algorithm
will check if the affected net is heterogeneous or non-heterogeneous. To provide the exact
schematic of the scenario following figure 4.9 explains the case where non-heterogeneous
and heterogeneous net is there from source to sink where LS is missing. In the hetro case
we can see source VA to Sink VA connection is also there, so LS shall not be inserted in
that case.

Figure 4.9: Level Shifter Instance Missing when Source is Port

34
Here in non-heterogeneous case, VA is the primary power supply of port while sink is in
VB Power Domain, so change in power rails will cause an insertion of Level Shifter in the
path. While in heterogeneous case, we can observe that sink power domains are more
than one which makes the analysis more critical.
Detailed implemented algorithm when source instance is a port in Level Shifter Missing
error is shown in the figure 4.10. Here error report from VCLP GUI is taken as an input to
the script and all sufficient data is fetched i.e., Source Name, Sink Name, Source Power
and Sink Power. Further check if the source is a port and heterogeneous connection
to that source is there by get ports and all connected ICC2 commands respectively. If
direct connection from source to sink is there, Level Shifter will be added by calling LS
insertion function. But in case of more than 1 sink connection the algorithm will fetch all
the destination pins and will remove the pins for which LS are already present to avoid
redundancy.

Figure 4.10: Level Shifter Instance Missing when Source is Port

So finally the algorithm will throw the source port, applicable sink pin, source power
and each sink power details into the LS insertion function which will eventually add the
LS in the design. Further as shown in the figure 4.11 LS insertion function will group
all the sink names which have same supplies through get related supply nets command
and eventually add 1 level shifter with high driving strength for that net. If the sink
power supply and source power supply is the same then script will not add LS to that

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net. While inserting the LS, the script take care of the LS library cell to be used and the
vcc in and vcc out pin power supply connection.

Figure 4.11: Level Shifter Insertion Function Flowchart

Final work done will be a developed Tcl Script of LS INST MISSING fix when source is
port, and which helps in reducing number of error counts in VCLP reports. After opening
the partition in ICC2 shell and sourcing the Tcl script in the shell the LS shifter will be
added in the design and further this design netlist and UPF can be saved for further
incremental runs. Following are the corner cases sufficed by the Tcl Script.

1. More than 1 power supplies in Destination Domain

2. One Level Shifter with high driving strength if more than one Sinks primary supply
is same
3. Level shifter already present in Sink PD
4. Heterogeneous nets from source to sink
5. Expected Power Supply not present in Destination Domain
6. Sink is port

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4.3.3 Case II: When Source is Pin
The scope of the algorithm where the source is a pin intends to have a case where Level
Shifter is already present in the path but wiring mismatch has happened from the tool
side which eventually popping up the error LS INST MISSING. Following figure 4.12
explains the before and after connection of the sourced script. As shown u=in the figure
the source and sink port are both on VA power supply which dons not require a Level
shifter but the hierarchical pin at VB Power domain requires a Level Shifter from VA
to VB signal propagation. Thus the script will identify the wrong connection if any and
change the wiring to that Sink where LS is actually needed.

Figure 4.12: Level Shifter Wrong Connection when Source is Pin

The scope of the script is to rewire the connection of LS input and output to get rid of
LS INST MISSING VCLP error. Detailed implemented algorithm when source instance
is a pin in Level Shifter wiring mismatch is shown in the below figure. Here error report
from VCLP GUI is taken as an input to the script and necessary information like source
name and source power is taken in the list.
Now through all fanout command of ICC2 fetch all the instance which are connected to
that source pin, and if any LS reference name is present then it will be obvious that the
wrong wiring scenario has happened here. If LS is not present check for any Isolation
cell, and convert them into Isolation + Level Shifter cell as sometimes tool just identify
the Off to On power domain. And if the LS is present then the algorithm will fetch
the LS cell name and the hierarchical pin of the source power domain. Once all the

37
connected sink to that hierarchical pin is fetched check all the power supply with that
source pin, and if same then no wiring of the nets is needed but if different then the ECO
connect nets and disconnect nets of ICC2 shell is performed. The detailed algorithm is
explained in the figure 4.13. Thus these two automation approaches of reducing the low-

Figure 4.13: Level Shifter Wrong Connection Flowchart

power verification check errors in VCLP tool is highly useful. The corner cases which are
included here can be increased as and when more errors will be seen in different projects.
In the next chapter, we will compare and discuss the results obtain by this Tcl script
when implemented in any partition.

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Chapter 5

Results and Discussion

5.1 Wrong Domain Buffering Results

The static low power checks helps to implement correct low power verification using UPF
power intent in VCLP tool. For the wrong domain buffering issue, the output ECO files
are provided in csv format for efficient analysis besides getting it manually with 50-60
buffer/inverter chain. The proper connection of power supply plays a vital role in VC LP
errros and reports.
As shown in the figure 5.1, in case where only single buffer is present between specified
source and sink, the output line in csv file will be like table 5.1. Here power supply PS B
is more ON than power supply PS A.

Figure 5.1: Single Wrong Domain Buffer Case

Table 5.1: Output CSV file for Single Wrong Domain Buffer Case

Instance Name Present Power Supply Expected Power Supply

buff cell 0 PS A PS B

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As shown in the figure 5.2, in case where chain of buffers is present between specified
source and sink, the output line in csv file will be like table 5.2. Here power supply PS B
is more ON than power supply PS A, PS A0, PS A1 and etc up to N number of cells.
The following cases w.r.t power supply of instances will be covered in the script.

1. All instances have same power supply (Highly Possible)

2. Some of them have same while others have different power supply (Might happen)
3. Every instances have different power supply (Rarely happen)

Figure 5.2: Chain Wrong Domain Buffer Case

Table 5.2: Output CSV file for Chain Wrong Domain Buffer Case

Instance Name Present Power Supply Expected Power Supply

buff cell 0 PS A PS B
buff cell 1 PS A0 PS B
buff cell 2 PS A1 PS B
buff cell n-2 PS A PS B
buff cell n-1 PS A PS B

Further, we will take these instances name as an input to another script where we can
find the type of the buffer or inverter with the reference name in library file. If it is
normal or always on buffer then we check if the expected power supply is present. If not
present then we recommend to change the hierarchy of the cell where physical layer of
that power supply is available. So following table 5.3 is the output of that file.

This script is highly efficient in terms of time required to do analysis of the schematic and
report of VCLP tool error. Here we will take one example to see how the process time
will decrease at the Owner’s end. Suppose we have a count of 30 ISO BUFINV STATE

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 Table 5.3: Output CSV file for detailed cell information

Instance Name Feedback

buff cell 0 Normal Buffer: Convert it to AON Buffer with PS B supply
buff cell 1 Normal Buffer: Change Hierarchy
buff cell 2 Normal Buffer: Change Hierarchy
buff cell n-2 AON Cell: Connect backup power rail with PS B
buff cell n-1 AON Cell: Change Hierarchy

out of which 20 are satisfying the case of wrong domain buffering. And in each count we
have approximately 10 buffer or inverter cells present to check for power supply and type
of cell, so overall 20 x 10 = 200 buffers to analyse, which will take approximately 15 - 20
minutes. So the project is eventually decreasing runtime and analysis time from 15 - 20
mins to 5 - 10 seconds.

5.2 Level Shifter Instance Missing Results

The VCLP error of Level Shifter is missing will pop up when the signal propagation is
happening between two different range of power supplies of Power Domain. It is one of
the most critical errors at Low Power Verification end which needs to be solved from the
sign-off team. As discussed in the Table 5.4 initially this error was solved manually by
the owner which takes a lot of time to debug for every count. And now as the steppings
of the design gets updated the owner was taking reference from the previous die but there
is a disadvantage if any new ports are added in the design. So this automated idea is
an apt solution for saving time as well as energy of the owner. Here, the error counts
reduced from 50’s to 0 within milliseconds which was taking hours if owners are doing
manually.

Table 5.4: Comparison table for LS INST MISSING

No Fix Involved Manual Approach Automation

Maximum Zero Zero *Error Counts
Maximum Average Zero Debug Time
Maximum Average Minimum Fix Time
Maximum Maximum Minimum Effort

*Error counts depends on the criticality of the partitions. (From 10s to 10,000s)

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Chapter 6

Conclusion and Future Scope

With the increase in consumer demands, features and longer battery life, the requirement
of low power design arises. Active power management is important at 90 nm and it be-
comes necessary below 65 nm technology as lower technology node will increase leakage
power. To reduce the leakage power in a design, power management concepts like power
domains, isolation, level shifter and retention registers are needed which is incorporated
in UPF and thus Low Power Verification is made efficient.
The VCLP Sign-off static checks have been done for Low Power Verification at early
design cycle. Prominent insertion of level shifter or Isolation cell and connection of the
dedicated power supply is being taken care of at runtime. Here the Engineering Change
Order feedback file is provided as an output of the wrong domain buffering script which
consists of affected instance name, its expected power supply and what solution is prefer-
able. So finally the analysis time will be reduced from 15 - 20 minutes to 5 - 10 seconds
which will reduce approximately 1/10,000th of total time which is an efficient approach
to analyze the affected instances. And another automation of LS insertion will add the
Level Shifter cell in the specific net where the LS INST MISSING error has popped up.
This automation will introduce the corrected wiring of the nets which will reduce the
error counts drastically from 50s to 0.
Further the most common errors can be fetched for automation as we are doing in Level
Shifter insertion in the scenarios where the tool is having limitations. We can also incor-
porate synthesis tool with the flow and give the required cells and automation. Innovation
from the customer end can be thought of by decreasing tool runtime and area optimization
by including less low-power elements.

42
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