ECE467: Introduction to VLSI Design

Lecture-8

Digital Logic Design:

Static Combinational Logic Design Techniques

Masud H. Chowdhury
Electrical and Computer Engineering
University of Illinois at Chicago
 Combinational vs. Sequential Logic
In Out
Combinational Combinational
In Logic Out Logic
Circuit Circuit

State

Combinational:Output = f( In ) Sequential:Output = f (In, Previous In )

Combinational logic or nonregenerative circuits:
• At any point in time, the output is some Boolean function of its current inputs
• No intentional connection from outputs back to input is present
Sequential or regenerative circuits:
• The output is not only a function of current inputs, but also of previous values of the
inputs
• This can be accomplished by connecting one or more outputs intentionally back to some
inputs, by providing a memory to remember past events
• A sequential circuit includes a combinational logic portion and module to store previous 2
logic states
 Static and Dynamic Circuits
Static Circuit:
• At every point in time (except during the switching transients) each gate output is
connected to either VDD or VSS via a low-resistive path
• The outputs of the gates assume at all times the value of the Boolean function,
implemented by the circuit (ignoring the transient effects during switching periods)
• An n-input gate requires 2n (n N-type + n P-type) devices
Dynamic Circuit:
• In dynamic circuit class, logic states rely on temporary storage of signal values on
the capacitance of high impedance circuit nodes
• An n-input gate requires on n + 2 (n+1 N-type + 1 P-type) transistors
• The resulting gate is simpler and faster
• This design is prone to failure due to increased sensitivity towards noise

Clk Mp
In1
PMOS only
In2 PUN
…

Out
InN In1 CL
Out
In2 PDN
In1
In3
In2 PDN
…

NMOS only Clk Me

InN 3
Static Gate Dynamic Gate
 Static Complementary CMOS Design
VDD
• A static CMOS gate is a combination of two
networks – the pull-down network (PDN) and
pull-up network (PUN) In1
PMOS only
• At every point in time (except during the In2 PUN

…
switching transients) each gate output is
connected to either VDD via PUN or VSS via PDN InN
• The PDN is constructed with NMOS transistors F(In1,In2,…InN)
to produce “strong zero”, and the PUN is In1
constructed with PMOS transistors to produce a In2 PDN

…
“strong ones” NMOS only
InN
Duality Principle:
•The PDN and PUN networks are constructed in
a mutually exclusive fashion so that one and only PUN and PDN are dual networks
one of the networks is conducting in steady state)
• NMOS devices connected in series corresponds to an AND function, while NMOS
devices connected in parallel represent an OR function
• The construction rules for PMOS network is exactly the opposite – parallel for AND
and series for OR
• Therefore, PDN and PUN are dual networks. This means that a parallel connection in
PDN corresponds to a series connection in PUN, and vice versa.
4
• Complementary CMOS gates are inverting, implementing only NAND, NOR, XNOR
 Digital Logic Circuits Classification
• Classification based on input-output relation:
– Combinational Logic Design
– Sequential Logic Design
• Classification based on logic style:
– Static Logic Design
– Dynamic Logic Design
• Classification based on implementation techniques:
– Complementary MOS (CMOS) circuit
– Ratioed logic circuit
• Resistive Load
• Active Load
– Pseudo NMOS
– Enhancement Type Active Load
– Depletion Type Active Load
– Differential Cascode Voltage Switch Logic (DCVSL)
– Pass-transistor logic circuit
– Transmission gate (TG)
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Static CMOS Combinational Circuits

6
 NMOS Transistors
in Series/Parallel Connection

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high
A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

7
 PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

8
 Complementary CMOS Logic Style

• PUN is the DUAL of PDN

• Duality can be shown by DeMorgan’s Theorem:

9
Example Gate: NAND

10
Example Gate: NOR

11
 Complex CMOS Gate

B
A
C

D
OUT = D + A • (B + C)
A
D
B C

12
 Constructing a Complex Gate

VDD VDD

C
SN1 F SN4 A
F
SN2 B
A A
D D SN3

B C B C D
F

(a) pull-down network (b) Deriving the pull-up network A

hierarchically by identifying
D
sub-nets
B C

(c) complete gate

13
Properties of Static CMOS Combinational Gates
• Full rail-to-rail swing: high noise margins
• Logic levels not dependent upon the relative device sizes: ratioless
• Always a path to Vdd or Gnd in steady state: low output impedance
• Extremely high input resistance: nearly zero steady-state input current
• No direct path steady state between power and ground: no static power
dissipation
• Propagation delay function of load capacitance and resistance of transistors
• Comparable rise and fall times: (under appropriate sizing conditions)

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 Switch Delay Model

A Req
A

Rp
Rp Rp
B
A B Rp
A Rp Cint
Rn CL A
B Rn CL
A Rn Rn CL
Rn
Cint
A B
A
NOR2
NAND2 INV

15
 Delay of RC Network
The propagation delay of an Inverter can be given by:
VDD

Rp

t pHL = 0.69τ n = 0.69Rn .CL t pLH = 0.69τ p = 0.69 R p .C L

CL
Rn
CL
V in= VDD

The propagation delay of any RC Network: Elmore Dealy

R1 R2 R3 R4
C1 C2 C3 C4

τ = R1C1+(R1+R2)C2+(R1+R2+R3)C3+(R1+R2+R3 +R4)C4

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 On Resistance Concept
• When a transistor is OFF it is considered an open
Rp Rp circuit, and can be considered an infinite
resistance
A B • When a transistor is ON it acts as a closed
switches with finite ON-resistance (Rn or Rp)
Rn CL • For a particular input pattern determine which
B transistors are ON and which are OFF
• Identify the continuous chains of ON transistors,
Rn that connect the output to either Vdd or GND
Cint • Use the resistance of those paths and load
A capacitance to calculate the delay

ON Resistance:
• Rno = Resistance of an NMOS transistor with size (W/L)n=1
• Rpo = Resistance of an PMOS transistor with size (W/L)p =1
Therefore,
• Rn = Rno/(W/L)n Normally Rpo = 2 or 3 times of Rno
• Rp = Rpo/(W/L)p 17
 Input Pattern Effects on Delay

• Delay is dependent on the pattern

of inputs
Rp Rp • Low to high transition
A B – both inputs go low
• delay is 0.69 Rp/2 CL
Rn CL
– one input goes low
B
• delay is 0.69 Rp CL
Rn
Cint
• High to low transition
A – both inputs go high
• delay is 0.69 2Rn CL

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 Delay Dependence on Input Patterns

3
Input Data Delay
2.5 A=B=1→0
Pattern (psec)
2 A=B=0→1 67
A=1 →0, B=1
A=1, B=0→1 64
Voltage [V]

1.5

1
A=1, B=1→0 A= 0→1, B=1 61

0.5 A=B=1→0 45

0 A=1, B=1→0 80
0 100 200 300 400 A= 1→0, B=1 81
-0.5
time [ps] NMOS = 0.5μm/0.25 μm
PMOS = 0.75μm/0.25 μm
CL = 100 fF 19
 Equivalent Inverter Concept
Steps to Calculate Delay:
– Find all inputs
– Calculate equivalent inverter sizes
– Use the equivalent inverter to calculate delay

(W/L)eq = (W/L)1 (W/L)eq = (W/L)2 (W/L)eq = (W/L)1 + (W/L)2

A (W/L)1 B
(W/L)2 Parallel equivalent

A=1 & B=0 A=0 & B=1 A=1 & B=1

A (W/L)1
1/(W/L)eq = 1/(W/L)1 + 1/(W/L)2 Or (L/W)eq = (L/W)1 + (L/W)2

B (W/L)2
Series equivalent

A=1 & B=1

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 Equivalent Inverter Concept
Consider following input combinations for the given circuit:

B B
A A (L/W)peq = (L/W)Bp+ (L/W)Cp+(L/W)Dp
C A=1 C
Rpeq = Rpo/(W/L)peq
B=0
D D tpLH = 0.69Rpeq.CL
C=0
&
A A
D=0
D D
CL
B C B C

B B
A A (W/L)BCn = (W/L)Bn+ (W/L)Cn
C C
A=1 CL (L/W)neq = (L/W)An+(L/W)BCn
D B=1 D Rneq = Rno/(W/L)neq
C=1
A & A tpHL = 0.69Rneq.CL
D D=0 D
B C B C
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 Worst Case Transistor Sizing Design
• Consider Rpo = 2Rno
• Worst-case tpLH will be for A=1, B=0, C=0 & D=0
• Worst-case tpHL will be for A=1,B=1, C=0 & D=0
• Our target is to make the circuit symmetrical with tpLH=tpHL = 0.69RnoCL=0.69(Rpo/2)CL
Sizing of PUN for worst-case tpLH:
B B 6
tpLH = 0.69Rpeq.CL A A 3
C C 6
Here Rpeq should be equal to Rpo/2
Now, D D 6

Rpeq = Rpo/(W/L)peq A A
Rpo/2 =Rpo/(W/L)peq D D
B C B C
(W/L)peq = 2 >> (L/W)peq =1/2
Now, (L/W)peq = (L/W)Bp+ (L/W)Cp+(L/W)Dp >> 1/2 = (L/W)Bp + (L/W)Cp +(L/W)Dp
Now for uniform transistor sizing we should select transistors of size
(L/W)Bp = (L/W)Cp = (L/W)Dp = 1/6 >> (W/L)Bp = (W/L)Cp = (W/L)Dp = 6
To maintain identical delay in all alternative signal paths we should select a size for transistor A, so
that it is equivalent to series combination of B and C.
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Here, (L/W)BCpeq = (L/W)Bp + (L/W)Cp = 1/6 + 1/6 = 1/3 >> (W/L)BCpeq = (W/L)Ap = 3
 Worst Case Transistor Sizing Design
• Consider Rpo = 2Rno
• Worst-case tpHL will be for A=1,B=1, C=0 & D=0
• Our target is to make the circuit symmetrical with tpLH=tpHL = 0.69RnoCL=0.69(Rpo/2)CL
Sizing of PDN for worst-case tpHL:
B B 6
tpHL = 0.69Rneq.CL A 3
A
C C 6
Here Rneq should be equal to Rno
Now, D D 6

Rneq = Rno/(W/L)neq A 2
A
Rno =Rno/(W/L)neq D D 1
B C B 2C 2
(W/L)neq = 1 >> (L/W)neq =1
Now, (L/W)neq = (L/W)An+ (L/W)Bn >> 1 = (L/W)An + (L/W)Bn
Now for uniform transistor sizing we should select transistors of size
(L/W)An = (L/W)Bn = 1/2 >> (W/L)An = (W/L)Bn = 2
Since transistor B and C hold identical positions in the PDN, (W/L)Cn = 2
For identical delay in all signal paths size for transistor D, should be equivalent of the series
combination of A and B or A and C.
Here, (L/W)ABneq = (L/W)An + (L/W)Bn = 1/2 + 1/2 = 1 >> (W/L)ABneq = (W/L)Dn = 1 23
 Fan-In Considerations

A B C D

A CL
B C3
Distributed RC model (Elmore delay)
C C2
D tpHL = 0.69 Rn(C1+2C2+3C3+4CL)
C1
Propagation delay deteriorates rapidly as a
function of fan-in – quadratically in the worst case.

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 tp as a Function of Fan-In

1250
quadratic
1000
Gates with a
750
fan-in greater
tp (psec)

tpHL tp than 4 should

500
be avoided.
250 tpLH
tpLH
linear
0
2 4 6 8 10 12 14 16
fan-in

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 tp as a Function of Fan-Out

All gates have

tpNOR2 tpNAND2 the same drive
current.
tpINV
tp (psec)

Slope is a
function of
“driving
strength”
2 4 6 8 10 12 14 16
eff. fan-out

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 tp as a Function of Fan-In and Fan-Out

• Fan-in: quadratic due to increasing resistance and capacitance

• Fan-out: each additional fan-out gate adds two gate capacitances
to CL

tp = a1FI + a2FI2 + a3FO

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 Fast Complex Gates: Design Technique 1
• Transistor sizing
– as long as fan-out capacitance dominates
• Progressive sizing
τ = R1C1+(R1+R2)C2+(R1+R2+R3)C3+(R1+R2+R3… +Rn)Cn

Distributed RC line
InN MN CL
M1 > M2 > M3 > … > MN
(the fet closest to the
output is the smallest)
In3 M3 C3
In2 M2 C2 Can reduce delay by more than
20%; decreasing gains as
In1 M1 C1 technology shrinks
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 Fast Complex Gates: Design Technique 2

• Transistor ordering
critical path critical path

charged 0→1
In3 1 M3 CL In1 M3 CLcharged
In2 1 M2 C2 charged In2 1 M2 C2 discharged
In1 M1 C1 charged In3 1 M1 C1 discharged
0→1
In1 is critical signal
delay determined by time to delay determined by time to
discharge CL, C1 and C2 discharge CL

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 Fast Complex Gates: Design Technique 3
• Logic Restructuring: Alternative logic structures
F = ABCDEFGH

Quadratic dependence of delay on Partitioning the NAND gate into two 4-input
fan-in makes this gate extremely slow NAND gates significantly reduce the delay

Further splitting of larger gates into

smaller gates reduce the delay even
more, which by far offsets the extra
delay incurred by additional smaller
gates.

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 Static Ratioed Logic Circuits
V DD V DD V DD V DD

Resistive Saturated Depletion PMOS

Load RL Load Load VT < 0 Load
V SS
F F F F
In 1 In 1 In 1 In 1
In 2 PDN In 2 PDN In 2 PDN In 2 PDN
In 3 In 3 In 3 In 3

V SS V SS V SS V SS
(a) resistive load (b) Enhancement-type (c) depletion load NMOS (d) pseudo-NMOS
saturated load MOS
Inverter
• The entire PUN is replaced by a single unconditional load device that pulls up the output.
• The PDN, which realizes the logic function, is same as complementary CMOS circuits
Goal: to reduce the number of devices over complementary CMOS
N+1 transistors versus 2N transistors for complementary CMOS
Disadvantages:
• Full voltage swing is not possible due to imperfect VOL
• Static power consumption
• Asymmetric VTC
• Reduced robustness due to reduced voltage swing 31
 Example of Ratioed Logic Circuit
VDD
VDD

F
D CL
F
CL
A B C D
C

B Pseudo NMOS NAND

Pseudo NMOS NOR

VOH = VDD (similar to complementary CMOS)

VOL > 0
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!

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 Differential Cascode Voltage Switch Logic
Design Goal:
– To create a ratioed logic that provides full rail-to-rail
voltage swing
– To ensures zero static power consumptions.
Concept:
• This type of gate combines two concepts:
– differential logic and positive feedback.
• A differential gate requires that each input be provided in complementary format,
and it produces complementary output in turn.
• The feedback mechanism ensures that the load device is turned off when not
needed.
• DCVSL is a ratioed logic design technique using the above mentioned concept.
Operating Principle:
• PDN1 and PDN2 are both of NMOS devices and mutually exclusive – that is, when
PDN1 conducts PDN2 is OFF, and vice versa.
• The logic function and its inverse are available simultaneously.
• Assume that initially Out and Out’ are high and low respectively.
• Now for a given set of inputs if PDN1 is turned ON while PDN2 is OFF, Out is
being pulled down, although there is still connection between M1 and PDN1.Out’ is
in high impedance state, as M2 and PDN2 are both turned OFF.
• PDN1 must be strong enough to bring Out below VDD - |VTp|, the point at which
M2 is turned ON and starts charging Out’ to VDD, eventually turning off M1. This33
in turn enables Out to be discharged all the way to GND.
 Differential Cascode Voltage Switch Logic
Advantages:
• The resulting circuit gives full rail-to-rail swing
• Static power dissipation is eliminated,
since none of the PDNs and load devices
are simultaneously conducting.
• It provides differential or complementary outputs.
It is a distinct advantage, because it eliminates the need
for an extra inverter to produce complementary signal.
• It prevents some of the time differential problems introduced by additional inverters
when both a function and its inverse are needed simultaneously
Disadvantages:
• The circuit is still ratioed since sizing of the PMOS device relative to the PDN
devices is critical to functionality and performance
• Circuit design complexity increases due to requirements of providing logic for a
function and its inverse
• The differential nature of this design virtually doubles the number of wires that
have to be routed, often leading to unwieldy designs on top of additional
implementation overhead in the individual gates.
• This circuit style has a power-dissipation problem due top cross-over currents.
• Short circuit power is still a problem. The dynamic power dissipation is also high.
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 Differential Cascode Voltage Switch Logic
Examples of DCVSL Gates:

Out
Out = AB Out = AB
Out

B A B B B B B

A A A

AND/NAND gate
XOR-NXOR gate

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 Pass Transistor Logic
Concept: In this logic style the primary input signals are used to drive gate terminals as well as
source and drain terminals of a transistor. In all other logic families only gate terminals of
MOSFET devices are allowed to be driven by primary inputs.
Advantage:
– Reduced number of transistor
– Lower Capacitance
– No static power
Example: 2-input AND gate

B
A B F
A 0 0 0
B
F = AB 0 1 0
0 1 1 1

• Total 4 transistors including the inverter needed to invert B.

• CMOS design requires 6 transistors for same function.
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 Pass Transistor Logic
Disadvantage:
C = 2.5V C = 2.5 V • Threshold voltage loss causes
static power consumption
M2
A = 2.5 V A = 2.5 V B • Reduced voltage level at node
B Mn B may be insufficient to turn
off the PMOS of the subsequent
CL M1 CMOS inverter

V does not pull up to 2.5V, but 2.5V - VTN NMOS has higher threshold than PMOS (body effect)
B
B C

Node x can charge up to VDD-Vtn1. Node Y can charge

A M1 M2 Out up to x-Vtn2, which works out to be VDD-Vtn1-Vtn2
x Y
B
• Using the concept of pass-transistor an AND function can be
implemented by the upper transistor only. When B=1, F=A, which
A
B gives the exact same result of an AND function.
F = AB
• But with B=0 the output node will be floating. To solve this
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0 floating node problem the second transistor is required.
 Pass Transistor Logic
Disadvantage:
• Reduced voltage swing due to threshold voltage drop: As discussed earlier the
NMOS device is effective at passing 0, but it is poor at pulling a node to VDD.
When an NMOS pass transistor is pulling a node high, the output only charges up
to VDD – VTn. Similarly when a PMOS pass-transistor is pulling a node down, the
output changes only down to VTp.
• Body effect: In MOSFET devices normally source and body terminals are kept at
same potential for proper operation. But in pass-transistor gates some source
terminals are connected to input signals, which are changing. Due to this source-to-
body bias the characteristics of the transistors vary widely.
• Floating output error: Some input combination may lead to floating output
situation, which is hard to identify for complex gate.
• Short Circuit Error: Since inputs drive source and drain terminals of pass transistor,
in some input combination there is chance of having short circuit between two
inputs
• Cascading problem: Multiple threshold drops prevents cascading of pass-transistor
gates

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 Pass Transistor Logic
Example: F = AB + B’C
A
For all but one input combinations this circuit works fine
For A=1 and C=1 there is short circuit between B and B’
B
A
Total transistors required: 10
F = AB+B’C

0
modification
C B

No floating node
B A
C B No short circuit
F = AB+B’C
4 transistors
0 C

A PMOS can be used

A in the lower path.
B
F = AB+B’C Only 2 transistors

C
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 Robust and Efficient Pass Transistor Logic
Level Restoration Transistor:
ƒ Using a PMOS level restoration transistor in a feedback path
ƒ Assume initially X=0, B=VDD and A=0 VDD
ƒ If A makes a 0 to VDD transition Level Restorer VDD
ƒ Mn charges X to VDD – Vtn Mr
ƒ The output of inverter is turned low B
ƒ The feedback device Mr is turned ON M2
ƒ X is pulled all the way to VDD X
A Mn Out
M1
Advantage:
• Full Swing
• No static power

Disadvantage:
• Restorer adds capacitance, takes away pull down current at X
• Additional capacitance slows down the gate
• Ratio problem: Mn must be stronger than the pull-up device Mr

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 Robust and Efficient Pass Transistor Logic
Multiple Threshold Transistors:
ƒ A technology solution to the voltage-drop problem associated with pass-
transistor logic is the use of multiple-threshold devices
ƒ Using zero threshold devices for the NMOS pass transistors eliminates most of
the threshold drop. All other devices are implemented using standard devices
VDD
Zero or low threshold transistor
VDD
0V 2.5V

VDD 0V Out

2.5V

WATCH OUT FOR LEAKAGE CURRENTS

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 Robust and Efficient Pass-Transistor Logic
Transmission Gate Logic:
ƒ To deal with the threshold voltage drop of the pass-transistor logic an approach
called transmission gate (TG) is utilized.
ƒ In this approach the complementary properties of NMOS and PMOS transistors
are used. NMOS devices pass a strong 0, but a weak 1, while PMOS devices
pass a strong 1, but a weak 0.
ƒ Transmission gate combines the best of both devices by placing an NMOS
device in parallel with a PMOS device as in figure below.
ƒ The control signal of the TG is complementary.
C
C

A B A B

C
C
TG circuit TG symbol

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 Transmission Gate Logic C
Operating Principle:
– TG acts as a bidirectional switch controlled by the gate signal C. A B
– When C=1, both MOSFETs are ON, allowing the signal to pass
– In short: A = B if C = 1
C
– While C = 0 both transistors are OFF, creating an open circuit between nodes A and B.
– Therefore the TG is enabled with C = 1 and disabled with C = 0
Example: Charging and discharging of node B

Advantages:
– No threshold voltage drop
– Can be used to build complex gates very effectively
• Example: Transmission Gate XOR gate
Disadvantage:
– Delay associated with chain of TG
– Delay is proportional to n2, and increases rapidly with the number of switches in the chain.
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