Systems Architecture

ARM Instruction Set

Data, Arithmetic and Memory Access

Notations

Rd Destination register d
d may be any register R0 – R15

hcc i Condition Code

Instruction executed under condition

hS i Set Condition Codes

Instruction sets condition for hcc i

hop1i Data-Processing Addressing Mode

Immediate / Register / Scaled

hop2 i Memory Access Addressing Mode

Offset / Pre-indexed / Post-Indexed
 Instruction Encoding

MOVS R0, R1
31 · · · 28 24 · · · 21 20 15 · · · 12 3···0

hcc i 000 hopcodei hS i 0000 Rd 00000000 Rm

hcc i Always = 1110 (0xE)

Ignore condition code – Always execute

hopcodei Move = 1101 (0xD)

This is a “Move” operation

hS i True (1)
Set the condition codes (N and Z)
N is true if value is Negative
Z is true if value is Zero

Rd R0 = 0000
Destination Register

Rm R1 = 0001
Source Register

Instruction Groups

1 Data Movement

2 Arithmetic

3 Memory Access

4 Logical

5 Flow Control

6 System Control
 Data Movement
• 50% to 70% of a program

• MOV Move value

MOVS Move value and set condition codes
• MOVhccihS i Rd, hop1i
hcc i: Rd ← hop1i
hcc ihS i: CPSR ← ALU(Flags)
• Rd is the destination (must be a register)

• hop1i is the source, may be any of the Data-

Processing addressing modes:
Immediate #nnn
Register Rn
Scaled Immediate Rn, hshift i #nnn
Scaled Register Rn, hshift i Rs

Arithmetic
• Addition
ADDhccihS i Rd, Rn, hop1i hcc i: Rd ← Rn + hop1i
hcc ihS i: CPSR ← ALU(Flags)

• Subtraction
SUBhccihS i Rd, Rn, hop1i hcc i: Rd ← Rn − hop1i
hcc ihS i: CSPR ← ALU(Flags)

• Multiplication
MULhccihS i Rd, Rn, Rs hcc i: Rd ← Rn × Rs
hcc ihS i: CSPR ← ALU(Flags)

Multiplying two 16-bit values (Rn and Rs), produces a 32-bit

result (Rd)

• Division
There is no division instruction
 Advanced Arithmetic
• Used to calculate values larger than 32-Bits

• Split value into 32-bit sections

Start with the least signification section and work up to the
most signification section, using the Carry to bridge sections

• Add with Carry

ADChccihS i Rd, Rn, hop1i
hcc i: Rd ← Rn + hop1i + CSPR(C)
hcc ihS i: CSPR ← ALU(Flags)

• Subtract with Carry

SBChccihS i Rd, Rn, hop1i
hcc i: Rd ← (Rn − hop1i) − CSPR(C)
hcc ihS i: CSPR ← ALU(Flags)

Memory Access

• Load Register from memory

LDRhcci Rd, hop2i hcc i: Rd ← M(hop2 i)

• Store Register in memory

STRhcci Rd, hop2i hcc i: M(hop2 i) ← Rd

• hop2 i is memory reference, may be any of

the Memory Access addressing modes:
Offset [Rn, hoffseti]
Pre-Index [Rn, hoffseti]!
Post-Index [Rn], hoffseti

• Memory Reference must be word aligned

 Load / Store Byte

• Load Register with unsigned Byte from memory

LDRhcciB Rd, hop2i hcc i: Rd(7:0) ← M(hop2 i)

hcc i: Rd(31:8) ← 0

• Load Register with Signed Byte from memory

LDRhcciSB Rd, hop2i hcc i: Rd(7:0) ← M(hop2 i)

hcc i: Rd(31:8) ← Rd(7)

• Store Register in a Byte of memory

STRhcciB Rd, hop2i hcc i: M(hop2 i) ← Rd(7:0)

Load / Store Halfword

• Does not work in the ARMulator

• An ARM word is 32-bits, so a Halfword is 16-bits

• Load Register with unsigned Halfword from memory

LDRhcciH Rd , hop2i hcc i: Rd(15:0) ← M(hop2 i)

hcc i: Rd(31:16) ← 0
• Load Register with Signed Halfword from memory

LDRhcciSH Rd , hop2i hcc i: Rd(15:0) ← M(hop2 i)

hcc i: Rd(31:16) ← Rd(15)
• Store Register in a Halfword of memory
STRhcciH Rd, hop2i hcc i: M(hop2 i) ← Rd(15:0)
• Memory Reference must be Halfword aligned
 Summary: Movement/Arithmetic

Data Movement

MOVhccihS i Rd, hop1i Move Data

Arithmetic

ADDhccihS i Rd, Rn, hop1i Add

SUBhccihS i Rd, Rn, hop1i Subtract

MULhccihS i Rd, Rm, Rs Multiply

ADChccihS i Rd, Rn, hop1i Add with Carry

SBChccihS i Rd, Rn, hop1i Subtract with Carry

Summary: Memory Access

LDRhcci Rd, hop2i Load Register

STRhcci Rd, hop2i Store Register

LDRhcciB Rd, hop2i Load Register unsigned Byte

LDRhcciSB Rd, hop2i Load Register Signed Byte

STRhcciB Rd, hop2i Store Register Byte

LDRhcciH Rd, hop2i Load Register unsigned Halfword

LDRhcciSH Rd, hop2i Load Register Signed Halfword

STRhcciH Rd, hop2i Store Register Halfword

 External Memory

MAR: Memory MBR: Memory

Address Register Buffer Register

Address
Incrementer
R15 / PC R11 R7 R3
R14 / LR R10 R6 R2
R13 / SP R9 R5 R1
R12 R8 R4 R0
User Registers
Booth's
Multiplier

Barrel IR
Shifter Control
Unit
CPSR

32-Bit ALU