UARTs on LPC2378

UM10211 – Ch.16, 17
UARTs
• 4 UARTs: UART 0/2/3 and UART1
– UART1 is identical to UART0/2/3, with the addition of a modem
interface.
• 16 byte Receive and Transmit FIFOs.
• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
• Built-in baud rate generator.
• Either software or hardware flow control can be
implemented.
• UART1: Standard modem interface signals included (CTS, DCD,
DTS, DTR, RI, RTS).
Pin Description (UART1)
RXD1 – [input] Serial Input. Serial receive data

TXD1 – [output] Serial Output. Serial transmit data.

CTS1 – [input] Clear To Send. Active low signal indicates if the

external modem is ready to accept transmitted data via TXD1 from
the UART1

DCD1 – [input] Data Carrier Detect. Active low signal indicates if

the external modem has established a communication link with
the UART1 and data may be exchanged.

DSR1 – [input] Data Set Ready. Active low signal indicates if the
external modem is ready to establish a communications link with
the UART1.
Pin Description (UART1) cont.
DTR1 – [output] Data Terminal Ready. Active low signal indicates
that the UART1 is ready to establish connection with external
modem.

RI1 – [input] Ring Indicator. Active low signal indicates that a

telephone ringing signal has been detected by the modem.

RTS1 – [output] Request To Send. Active low signal indicates that

the UART1 would like to transmit data to the external modem.
Pin function configuration

Source: UM10211 (Rev4.1) Ch. 9.5.1.2

Pin function configuration

Source: UM10211 (Rev4.1) Ch. 9.5.2.2

UART1 register map

Source: UM10211 (Rev4.1) Ch. 17.4

UART1 register map

Source: UM10211 (Rev4.1) Ch. 17.4

UART1 Line Control Register (U1LCR)

Source: UM10211 (Rev4.1) Ch. 17.4.7

UART1 Line Status Register (U1LSR)

Source: UM10211 (Rev4.1) Ch. 17.4.11

UART1 Line Status Register (U1LSR)

Source: UM10211 (Rev4.1) Ch. 17.4.11

UART1 Line Status Register (U1LSR)

Source: UM10211 (Rev4.1) Ch. 17.4.11

UART Interrupts
• UARTs generate interrupts for a number of
conditions
– Receive data ready
– Receive data error
• Framing, Parity, Overrun
– Modem signal status changes
– Transmitter buffer empty
• Issues using the transmit interrupt
UART1 Interrupt Enable Register (U1IER)

Source: UM10211 (Rev4.1) Ch. 17.4.11

UART1 Interrupt Enable Register (U1IER)

Source: UM10211 (Rev4.1) Ch. 17.4.11

UART1 Interrupt Enable Register (U1IIR)

Source: UM10211 (Rev4.1) Ch. 17.4.11

Example Code – UART init
/* initialize serial port */
void uart1_init() {

PINSEL0 |= 0x40000000; /* Enable TxD1 */

PINSEL1 |= 0x00000001; /* Enable RxD1 */

U1LCR = 0x83; /* 8-bits, no parity, 1 stop bit */

/* enable access to DLAB (DLL and DLM) */
U1DLL = 13; /* baud rate = 57600 */
U1DLM = 0; /* - */
U1LCR = 0x03; /* set to a normal operation */

/* Set the address of interrupt service routine */

VICVectAddr7 = (unsigned long) sio_irq;

VICIntEnable = 1 << 7; /* Enable UART1 Interrupt */

U1IER = 3; /* Enable UART1 RX and THRE Interrupts */

}
Example Code – Interrupt Handler
__irq void sio_irq (void) {
. . .
if ((U1IIR & 0x01) == 0) { /* There is at least one interrupt source */
switch (U1IIR & 0x0E) {
case 0x04: /* Receive Data Available */
/* get data available in U1RBR register */
/* process it */
break;
case 0x02: /* THRE Interrupt */
. . .
. . .
break;
default: break;
}
}
VICVectAddr = 0; /* Acknowledge Interrupt */
}
Data frame timing
• The data coming in at the receiving end of the data line in a
serial data transfer is all 0s and 1s.
To make of the data, the sender and receiver needs to agree
on a set of rules, a protocol, on how the data is packed, how
many bits constitute a character, and when the data begins
and ends.

• The time that a single data bit is valid is referred to as a bit

time. The bit time is reciprocal of a baud rate.
To successfully transfer data, the baud rate of transmitter and
receiver must be equal.
U1RBR & U1THR Registers
• UART1 Receiver Buffer Register (U1RBR)
– The U1RBR is the top byte of the UART1 RX FIFO. The
top byte of the RX FIFO contains the oldest character
received and can be read via the bus interface.

• UART1 Transmitter Holding Register (U1THR)

– The U1THR is the top byte of the UART1 TX FIFO. The
top byte is the newest character in the TX FIFO and
can be written via the bus interface.
– The LSB represents the first bit to transmit.
UART1 Divisor Latch LSB and MSB Registers (U1DLL and U1DLM)

• The UART1 Divisor Latch is part of the UART1 Baud Rate

Generator and holds the value used to divide the APB
clock (PCLK) in order to produce the baud rate clock,
which must be 16x the desired baud rate.

• The U1DLL and U1DLM registers together form a 16 bit

divisor where U1DLL contains the lower 8 bits of the
divisor and U1DLM contains the higher 8 bits of the
divisor
Example
• In order to set baud rate to 57600 with 12MHz pclk,
57600 = 12*106
16 * (256 * U1DLM + U1DLL)
16 * (256 * U1DLM + U1DLL) = 12*106 / 57600
256 * U1DLM + U1DLL = 13.021

Choose: U1DLM = 0 and U1DLL = 13

Fractional Value
• If fractional value is needed, then UART1
baudrate can be calculated as

• U1FDR[3:0] = DivAddVal (Reset value = 0)

– Note: If this field is 0, the fractional baud-rate
generator will not impact the UART1 baudrate.
• U1FDR[7:4] = MulVal (Reset value = 1)