Lecture 8

Exception Handling (Ch.11)

 time

user program
 time

user program user program

IRQ Interrupt handler

Interrupt
 time

user program user program

cpu context saved
cpu context restored
IRQ Interrupt handler

Interrupt latency

Interrupt response

Interrupt
 time

user program user program

cpu context saved
cpu context restored

FIQ Interrupt handler

Interrupt latency

Interrupt response

Interrupt
Second
Interrupt
Source: http://www.keil.com/support/man/docs/mcbstr7/mcbstr7_interrupt_func1.png
Exceptions

• Any event that breaks a program’s normal

flow could be considered an exception.
• Some can be readily handled and others are
unexpected and can cause a problem
Exceptions
Exceptions arise:
• as a direct effect of fetching or decoding an instruction:
– software interrupts
– undefined instructions
– prefetch aborts
• as a side-effect of an instruction:
– aborts on data transfers
• unrelated to the instruction flow (generated externally):
– Reset, IRQ, FIQ
Privileged modes and Exceptions
ARM has privileged operating modes:
• System mode for privileged operating system tasks
• SVC (supervisor) mode – a protected mode for the
operating system.
• Abort mode for handling memory faults
• Undef mode for undefined instruction – supports
software emulation of hardware coprocessors
• IRQ mode for interrupts
• FIQ mode for fast interrupts
ARM registers

ARM has a total of 37 registers

, all are 32-bit long
• 1 dedicated program counter (PC)
• 1 dedicated current program status register (CPSR)
• 5 dedicated saved program status registers (SPSR)
• 30 general purpose registers
Registers
Each privileged mode (excluding a system mode) has:
• its own r13, normally for a private stack pointer
• its own r14 for a return address
• its own Saved Program Status Register (SPSR) to preserve
the CPSR so it can be restored upon return.

FIQ mode has additional its own registers (r8 – r14) to

speed its operation.

Note: Exception handlers must save (restore) other registers on entry (exit)
Registers
• For all modes
– the same physical set of registers r0 to r7, r15 (pc) and CPSR are
used.
– have their own special stored program status registers,
SPSR_xxx, except the user the system modes
• For the mode _fiq
– all registers r8 to r14 are replaced by r8_fiq to r14_fiq
– r13 and r14 are replaced by alternatives, r13_xxx and r14_xxx,
except the system mode
CPSR register

Interrupt disable bits:

bit 7 disables IRQ when set
bit 6 disables FIQ when set
bit 5 controls the instruction set
ARM (T=0) or Thumb (T=1)
Mode - specifiy the processor mode

Unused - functions in later ARM versions

Processor Modes

Processor modes determine

• which registers are active, and
• access rights to CPSR register
Each processor mode is either
• Privileged: full read-write access to the CPSR
• Non-privileged: only read access to the control field of
CPSR but read-write access to the condition flags
Processor Modes

• The current processor mode governs which of several

banks is accessible. Each mode can access
– a particular set of r0-r12 registers
– a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
– the program counter, r15 (pc)
– the current program status register, CPSR
• Privileged modes (except System) can also access a
particular SPSR (saved program status register)
Processor Modes
Source: Table A2-2 (ARM Architecture Reference Manual)
Example

MOV r14, r1

• Source operand is r1
– There is only one r1 (physical) register.
– Therefore, the source operand refers to the same register in all
modes
• The destination register is r14
– Depending on the processor mode, the destination register can be
r14_fiq (in FIQ mode) or r14_svc (in supervisor mode)
– The postfix _xxx added to register name is only used to show which
(physical) register are set, it is not used in assembly language
Summary

• Register organization
• CPSR bits
• Processor mode
• Register under different modes
What’s Next

• Processor exception sequence

• Memory faults
• IRQ
• FIQ
• Exception handlers