ESD Merged Till CS6

Embedded System Design
BITS Pilani, Pilani Campus

Course Contents
• 9 Modules
• Recorded Lectures
• Books and reference material

Evaluation Scheme
No Name Type Durati Weig Day, Date, Session, Time
on ht
EC-1 Quiz-I Online - 5% February 1-15, 2021
Assignment-I Online 10% March 1-15, 2021
Assignment-II Online 15% April 1-15, 2021
EC-2 Mid-Semester Closed 2 30% Sunday, 07/03/2021 (AN)
Test Book hours 2 PM – 4 PM
EC-3 Comprehensiv Open 3 40% Sunday, 02/05/2021 (AN)
e Exam Book hours 2 PM – 5 PM

Summary of RL
• Introduction to embedded systems (ES)
• Description of ES
• Characteristics of ES
• Design procedure of ES
• Classification of ES
• Hardware and software components of ES
• Power supply for embedded system
• Separation of power lines
• Power and performance
• Power saving modes
• Clocking units

Characteristics
• Single functioned
• Complex Algorithms
• User Interface
• Tightly Constrained –Power, Cost, Memory
• Reactive and Real-Time
• Multi-rate
5
Performance Evaluation
• Response
• Throughput/(Speed of ES can process the input)
• Reliability – MTBF,MTTR
• Maintainability
• ISP & IAP
• Testability & Debug-ability
• Evolvability
• Portability
• Time-to-prototype and Market

Requirement Analysis
Specifications
System Architecture
Hardware Design Software Design
Hardware Implementation Software Implementation
Hardware Testing Software Testing
System Integration
System Validation
Operation & Maintenance

Example of Embedded Systems
• Washing machines
• Microwave ovens
• MP3 players
• Hand help electronic games
• Watches
• Vehicle displays and controls

Examples of Embedded Systems in Industry
• Sophisticated scientific instruments
• Systems in aircraft, missiles and satellites
• Robotic systems deployed in remote areas

Design Example: GPS moving map
• Requirements analysis
• Specification
• Architecture
• Component implementation
• System integration
• Testing

Requirements of GPS moving map

Specification
Name: GPS Moving Map
 Purpose: Consumer grade road navigation
 Inputs: Power button, 2 control buttons
Outputs: Back-lit LCD, 400x600 pixels
Functions: Uses GPS system, 3 user selectable resolutions,
displays current latitude and longitude.
Performance: Updates screen with 0.25s upon movement
Manufacturing cost: Rs. 1000
Power: 100 mW
Size and weight: 4cm x 8cm, 250 gm

Architecture Design
Hardware
• Display
• Frame buffer
• Memory
• CPU
• GPS receiver
• Panel i/o
 Software
• Database search
• Renderer
• User interface
• Position
• Timer
Designing Hardware and Software
• Ready made components: CPU, memory
• Specialized pre-designed component: GPS receiver
• Standard software modules: topographic database and access
routines
• PCB design
• Design with constraints

System Integration
• This phase uncovers bugs
• Integration in phases
• Correction of simple bugs
• Importance of debugging facilities
• Challenging

Classification of ES
Single 8/16 bit Microcontroller 16/32 bit

Less complex hardware and Microcontroller/RISC,DSP/ASS Multi-processor system
software P/IP Safety Critical applications
Board level design May involve use of RTOS H/w S/w Co-design
Battery-operated Distributed System – RTOS
bus/networks
Encryption/ Decryption/DCT
Real-Time Scheduling
Embedded System hardware

Embedded System Software
• Software
• Application Specific Software – series of tasks
• Constraints- available memory, available processing power, power dissipation
limit
• RTOS
• Supervise application s/w
• Allocate resources
• Context switching
• Latencies – meet the deadlines
• Scalable

From RL
• CPUs in embedded systems.
• RISC and CISC
• Microprocessor and Microcontroller

From RL
• Requirements for a GPP to qualify as an embedded systems CPU.
• Low Interrupt latency in the CPU architecture.
• Support for Atomic Operations.
• DSP Processors.
• Microprocessor + MAC unit
• Application Specific Processors / System on Chip
• Security needs
• Multimedia processing requirements
• Communication protocol requirements
• How to choose a suitable processor / SoC for your application?

From RL
• Memory types in Embedded Systems
• CPU registers
• Cache Memory
• Volatile / Nonvolatile memories
• RAM/ ROM/ Hybrid
• FRAM - for fast access non volatile storage
• Flash
• SD Card
• Dynamic Memory Allocation
• Programs larger than memory
• Multiple programs in memory
• Swapping

Difference between Harvard and Von Neumann Architecture

Memory
RAM Hybrid ROM
EEPROM NVRAM Flash
SRAM DRAM EPROM PROM

Cache memory

From RL
• Hit and Miss
• Cache Organization
• Direct Mapping
• Set Associative

From RL
• Power, Clock and Reset.
• Power
○ Voltage ranges in ES.
○ Power Saving Schemes. (Frequency, Idle and Sleep Modes)

• Clock Source
○ Crystal
○ Ceramic Resonators
○ External IC clock generator
• Reset
○ Power on Reset (H/W), External Reset
○ Invalid instructions
○ Clock Monitor
○ Watchdog Timer

From RL
Interrupt Handling, Timers, ADC, DAC, Communication
Interfaces
● Timer
○ Input Capture.
○ Output Compare
○ PWM
● Interrupt Handlers
○ Hardware External Interrupts
○ Internal event driven interrupts
○ Priority
○ Latency
● ADC
● DAC
● Serial and Parallel Communication Interfaces in ES.

From RL
Software Components of Embedded Systems
● Operating Systems
○ RTOS
○ Normal OS
● Compiler / Assembler / Linker
● Device Driver
● Scheduling Schemes in RTOS.

Embedded System Design
Class 2
From RL
Challenges in ESD
● Application Specific System on Chip
○ Network Connectivity
○ Encryption Requirements
○ Bluetooth / NFC requirements

Quiz
• Which one of the following offers CPUs as integrated memory or
peripheral interfaces?
a) Microcontroller
b) Microprocessor
c) Embedded system
d) Memory system

• It retains its content when power is removed. What type of memory
is this?
a) Volatile memory
b) Nonvolatile memory
c) RAM
d) SRAM
• What type of memory is suitable for high volume production?
a) RAM
b) ROM
c) EPROM
d) EEPROM

• Which is the first microcontroller?
a) 8051
b) Arm
c) TMS1000
d) Intel 4004
• . What is the performance of an accumulator?
a) Storing data and performing logical operation
b) Storing data and performing arithmetic operation
c) Storing address
d) Pointer

• How is memory accessed in RISC architecture?
a) load and store instruction
b) opcode instruction
c) memory instruction
d) bus instruction
• Which of the following statements are true for von Neumann architecture?
a) shared bus between the program memory and data memory
b) separate bus between the program memory and data memory
c) external bus for program memory and data memory
d) external bus for data memory only

Summary: ARM core
• ARM Characteristics
• Register windowing
• ARM Architecture
• ARM cores
• Flynn’s taxonomy
• ARMv7 core
• Comparison

ARM characteristics
• Soft Processor – IP core processors

• 32- bit RISC
• Load Store Architecture

• Fixed- Length 32-bit instructions
• 3-address instruction format
• Inst dst,src1,src2
• Register window
• Delayed branches
• Single cycle instructions
ARM characteristics
• Pipelined – 3 stage
• Fetch
• Decode
• Execute
• PC – points to instructions being fetched
• Von-Neumann Architecture
• Memory Access – only load/store/swap
• Data is aligned
• Two Instruction sets
• 32-bit ARM
• 16-bit THUMB – Instruction Compression

Flynn’s Taxonomy
• SISD: classical von Neumann architecture

• SIMD
• MISD: Non existent,just listed for
completeness
• MIMD: Most common and general
parallel machine

SISD
RL 3.1.1 Embedded System Design © K.R.Anupama &

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SIMD

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A: I1 A,B
SIMD
B: I1 C,D
Data Bus A
Data Bus A
ALU MAC Shifter ALU MAC Shifter
A B
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MISD

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MIMD
RL 3.1.1 Embedded System Design © K.R.Anupama & back 17

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ARM Programmer’s Model
• Bi-endian
• Operating states
• Operating modes
• Registers
• Register organization in different modes
• Program status register in different versions

For reference:
In computing, endianness is the order or sequence of bytes of a word of

digital data in computer memory. Endianness is primarily expressed as big-
endian (BE) or little-endian (LE). A big-endian system stores the most
significant byte of a word at the smallest memory address and the least
significant byte at the largest. A little-endian system, in contrast, stores the
least-significant byte at the smallest address. Endianness may also be used
to describe the order in which the bits are transmitted over a
communication channel, e.g., big-endian in a communications channel
transmits the most significant bits first. Bit-endianness is seldom used in
other contexts.
Bi-endianness is a feature supported by numerous computer architectures
that feature switchable endianness in data fetches and stores or for
instruction fetches.
Operating States and Modes
States: ARM
Thumb
Switching - BX
Most application programs execute in User mode. While the processor is in User
mode, the program being executed is unable to access some protected system
resources or to change mode, other than by causing an exception to occur.
This allows a suitably written operating system to control the use of system resources
Registers
• ARM has 37 registers
• 31 – GPRS, 6 SR
• Not all registers – available to programmers
• In ARM state – 16 GPR 1/2 SR are accessible
• In each of privileged modes – separate banks of
registers are accessible
• r0 - r15
• r15 – Program Counter –valid bits [31:2] –ARM state
• r14 – Link Register
• r13 – Stack Pointer
• CPSR – CCR/Flags
• In privileged modes – SPSR

Register 14
Register 14 is the Link Register (LR). This register holds

the address of the next instruction after a Branch and Link
(BL) instruction, which is the instruction used to make a
subroutine call.
At all other times, R14 can be used as a general-purpose
register.

R15 : Program Counter
• Register 15 is the Program Counter (PC). It can be

used in most instructions as a pointer to the instruction
which is two instructions after the instruction being
executed.
• All ARM instructions are four bytes long (one 32-bit
word) and are always aligned on a word boundary. This
means that the bottom two bits of the PC are always
zero, and therefore the PC contains only 30 non-
constant bits.
• The remaining 14 registers have no special hardware
purpose. Their uses are defined purely by software.
• Software normally uses R13 as a Stack Pointer (SP).

CPSR Register-Current Processor Status Register

Status Register Across Family

Exceptions
• An exception is any condition that needs to halt the normal sequential execution
of instructions.
• Reset, instruction fetch or memory access fails, undefined instruction, software
interrupt or external interrupts.

Exception Handling
The ARM architecture supports a range of interrupts, traps and

supervisor calls, all grouped under the general heading of exceptions.
They are all handled in similar way :
1. The current state is saved by copying the PC into R14_exc and the
CPSR into SPSR_exc (where exc stands for the exception type).
2. The processor operating mode is changed to the appropriate mode.
ARM processor mode can also be changed by changing the CPSR.
3. The PC is forced to a value between 0x00 to 0x1C, the particular value
depending on the type of exception. Usually the address of an
exception handler will be located into those values.
4. It disables IRQs by setting bit 7 of the CPSR and if it’s FIQ, disables
further FIQs by setting bit 6 of CPSR.
When an exception occurs the ARM processor always switches to ARM
state.
VECTOR TABLE
• A table of addresses that the ARM core branches to when an exception is

raised.
• These addresses commonly contain branch instructions to exception handler
routines.

Instructions at vector table addresses
Vector table addresses commonly contain branch instructions of one of

the following types:
❏ B <address> Branch relative to PC
❏ LDR PC, [PC, #offset] Loads the handler address from
memory to PC. Address is an absolute 32-bit value stored close
to the vector table. Delay in branching hence latency but can be
branched to any address in memory.
❏ LDR PC, [PC, #-0xff0] Loads ISR address from 0xFFFFF030.
❏ MOV PC, #immediate Copies an immediate value into PC.
But immediate value is limited by constraints.

Exception Return
Once the exception has been handled, the user task is normally
resumed. This requires the handler code to restore the user state exactly as it was
when the exception first arose:
❏ Any modified user registers must be restored from the handler’s stack.
❏ The CPSR must be restored from the appropriate SPSR.
❏ The PC must be changed back to relevant instruction address in the user instruction
stream.
If CPSR is restored first, the banked R14 holding the return address is no longer
accessible.
❏ If the PC is restored first, the exception handler loses control of the instruction
stream and can not cause the restoration of CPSR to take place.
❏ There is a need for an instruction that can perform both of these
tasks atomically as a single instruction.

• To return from a SWI or undefined instruction:
MOVS PC, R14
• To return from an IRQ, FIQ or prefetch abort
SUBS PC, R14, #4 ; PC = PC - 4
because there is an S at the end of SUB and PC is the
destination register, the cpsr is automatically stored from
the spsr register.
• To return from an data abort to retry the data access
SUBS PC, R14, #8 ; PC = PC - 8

Link Register Offsets

Exception Priorities

ESD class3

ARM Data Processing Instructions
• Perform arithmetic and logical operations in data values

stored in registers
• Typically require 2 operands and produce a single result,
with exceptions
• Operands are 32 bit wide
• Operands are present in registers or specified in the
instruction
• The result is 32 bit wide and is placed in the register
• Use 3-address format

Arithmetic Operations
• ADD r0, r1, r2;

r0 = r1 + r2
• ADC r0, r1, r2;
r0 = r1 + r2 + C
• SUB r0, r1, r2;
r0 = r1 − r2
• SBC r0, r1, r2;
r0 = r1 − r2 + C − 1
• RSB r0, r1, r2;
r0 = r2 − r1
• RSC r0, r1, r2;
r0 = r2 − r1 + C − 1
Bitwise Logical Operations
• AND r0, r1, r2;

r0 = r1 and r2
• ORR r0, r1, r2;
r0 = r1 or r2
• EOR r0, r1, r2;
r0 = r1 xor r2
• BIC r0, r1, r2;
r0 = r1 and not r2

Register Movement Operations
• The first operand is not present

• MOV r0, r2;
r0 = r2
• MVN r0, r2;
r0 = not r2

Comparison Operations
• Do not produce result

• Change N, Z, C and V bits in CPSR
• CMP r1, r2; Compare: set cc on r1 - r2
• CMN r1, r2; Compare negated: set cc on r1 + r2
• TST r1, r2; Bit test: set cc on r1 and r2
• TEQ r1, r2; Test equal: set cc on r1 xor r2

Shifted Register Operands
• ADD r3, r2, r1, LSL #3; r3 = r2 + 8r1

• LSL
Logical shift left by 0 to 31 places
• LSR
Logical shift right by 0 to 32 places
• ASL
Arithmetic shift left, same as LSL
• ASR Arithmetic shift right by 0 to 32 places.
Fills vacated bits with MSB
• ROR
Rotate right by 0 to 32 places
• RRX
Rotate right extended by 1 place

Condition Codes
• N, Z, C, V in CPSR
• Compare instructions change condition codes
• Data processing instructions can also change
condition codes if specified
• Example: 64 bit addition
• First number is stored in r0-r1
• Second number is stored in r2-r3
• ADDS r2, r2, r0; 32 bit carry out to C
• ADC r3, r3, r1;
• Used in conditional branch instructions

Multiplication
• MUL r4, r3, r2; r4 = r3 x r2

• Immediate second operands are not supported
• Result register must not be the same as the first
source Register
• Produces 64 bit result, the least significant 32 bits
are stored in the result register
• MLA r4, r3, r2, r1; r4 = (r3xr2 + r1)

In the ARM, PC is implemented using ___________
a) Caches
b) Heaps
c) General purpose register
d) Stack
Each instruction in ARM machines is encoded into __________

Word.
a) 2 byte
b) 3 byte
c) 4 byte
d) 8 byte

The address system supported by ARM systems is/are
___________
a) Little Endian
b) Big Endian
c) X-Little Endian
d) Both Little & Big Endian
The ARM processors don’t support Byte addressability.

a) True
b) False
Does the Load instruction do the following operation/s?

a) Loads the contents of a disc onto a memory location
b) Loads the contents of a location onto the accumulators
c) Load the contents of the PCB onto the register
d) None of the mentioned

In a vectored interrupt,
a) The branch address is assigned to a fixed location in memory.
b) The interrupting source supplies the branch information to the processor
through an interrupt vector.
c) The branch address is obtained from a register in the processor
d) None of the above
When CPU is executing a program that is part of the operating system, it is said to
be in
a) Interrupt mode
b) System mode
c) Half mode
d) Simplex mode

ASM Example Code

AMBA Bus
Advanced Micro-controller Bus Architecture

◮ Common bus terminologies
◮ Performance and cost of bus
◮ Speed of peripherals compared to CPU
◮ Architecture details

The advanced Microcontroller Bus Architecture(AMBA) specification defines an
On chip communication standard for designing high performance embedded
micro controllers.
Three distinct buses are defined within the AMBA specification:
• The advanced high Performance Bus(AHB)
• The advanced System Bus(ASB)
• The advanced Peripheral Bus(APB)
• The advanced trace Bus(ATB)
• The AMBA extensible Interface(AXI)

The AMBA specification has been derived to satisfy four key requirements:
To facilitate the right-first-time development of embedded micro controller
products with one or more CPUs or signal processors.
To be technology-independent and ensure that highly reusable peripheral
and system macro cells can be migrated across a diverse range of IC
processes and be appropriate for full-custom, standard cell and gate array
technologies
To encourage modular system design to improve processor independence,
providing a development road-map for advanced cached CPU cores and the
development of peripheral libraries.
To minimize the silicon infrastructure required to support efficient on-chip
and off-chip communication for both operation and manufacturing test.

ESD class 4

Difference between Preindexing and Postindexing
LDR R0, [R1, #4]! =>EA:R1 + 4 ; loads R0 with the word pointed LDR R0, [R1], #4=> EA:R1 ; loads R0 with the word pointed at
at by R1+4 ; then update the pointer by adding 4 to R1 by R1; then update the pointer by adding 4 to R1

Features - LPC23xx series - ARM-based
microcontrollers
• 10/100 Ethernet MAC
• USB 2.0 Full Speed interface
• 4 UARTs
• 2 CAN channels
• 1 SPI interface
• 2Synchronous Serial Ports (SSP)
• 3 I2C interfaces
• 1 I2S interface,
• 1 MiniBus
Introduction to LPC 23xx
Basic features of LPC 23xx series

◮ Members of series
◮ Memory features
◮ Clock sources and PLL output generation
◮ Power supply and low power modes of operation
◮ Brown out detection
◮ Memory map

Clk Generation
Main Osc
PLL cpu
Int RC mux mux clk div
RTC clksrcreg
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•Phase-locked loop (PLL)
A phase-locked loop (PLL) is a feedback circuit designed to allow one circuit board to
synchronize the phase of its on board clock with an external timing signal. PLL circuits operate
by comparing the phase of an external signal to the phase of a clock signal produced by a
voltage controlled crystal oscillator (VCXO). The circuit then adjusts the phase of the
oscillator’s clock signal to match the phase of the reference signal. Thus, the original reference
signal and the new signal are precisely in phase with each other.
Brown out Detection
3.3
2.9
2.65
Int
Reset
Enable - PCON

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ARM7TDMI –S stands for:
• ARM - Advanced RISC Machines
• 7 - Version number of the architecture
• T - THUMB: 32-bit wide instruction
words 16-bit wide memory
• D - Debug: 2 break points to stop the
CPU (both hardware and software)
• M - Multiplier: enhanced (relative to
earlier ARM cores) 32x8 Multiplier
• I:Interface: Embedded ICE macro cell.
JTAG-Joint test Action Group
• S-Synthesizable(ie., distributed as RTL
rather than a hardened layout)
LPC 23xx GPIO
Different ports of LPC 23xx

◮ General features of ports
◮ Use of ports for generating interrupts
◮ Useful and unaccessible pins of ports
◮ Functioning of port 0 and 1
◮ Mode selection and control registers for ports
◮ IOxPIN, IOxSET, IOxCLR, IOxDIR registers
◮ Fast GPIO ports and registers
◮ Input with interrupt registers

Features
• GPIO PORT0 & PORT1
• accessible
• group of reg providing enhanced features accelerated port access
• legacy group of reg
• PORT2/3/4 are accessed as fast ports only.
• Accelerated GPIO functions
• GPIO regs are relocated to the ARM local bus so that the fastest possible I/O
timing can be achieved

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• PORT0 & PORT2 provide an interrupt for each port pin
• Each int can be programmed to generate an int on a rising edge, a
falling edge, or both
• Asynchronous
• GPIO0 & GPIO2 ints share the same VIC slot with EI3
• Not all pins can be used for externally.
• Around 112 pins out of 150 can be used for externally, rest can be
accessed internally
• Every pin has alternate functions.
LPC 23xx Timer
System Clocks The LPC23xx has two main internal clocks.

The first is Cclk, the CPU clock, which is used to clock the ARM7
CPU and the AHB peripherals which include the USB controller,
Ethernet controller and the general purpose DMA.
The second internal clock is Pclk, the peripheral clock, which is
used to clock all the peripherals on the APB bus.Both of these
clocks may be derived from one of three oscillator sources, an
internal RC oscillator, an external main oscillator and an external
watch crystal.

Essentially a 32 bit binary counter which increments at the Pclk
frequency (or a sub multiple of)
For example if the Pclk is at 15MHz then the timer will

increment times per second which equates to once every 66.67
nS (The smallest resolution for a 15 MHz Pclk)Maximum time
duration 2^32×66.67 nS = 286 s
To increase this value a pre-scaler may be used

Generating a time period
Each timer has a match register

This value of this is set by the programmer
When the timer value = match register value a flag will be
set.
For example to generate a time period of 0.5s
Clock counts = Timer Frequency × time period
Clock counts = 15MHz× 0.5 =7500000

Each time an external event occurs detecting edge(s) of an input the
value in the counter is incremented. Source of the counter input is an
external pin not the clock!
Frequency counting
After a defined time period (nominally 1s) what is the value of the counter.
Event counting
After a set number of (events) edges have been detected perform some
action

PCLK is the peripheral clock which is
derived from the main processor clock.(
Pclk = CPUclk / x
where x is 1,2 or 4)

Input Capture Programming
Step 1: Port pins and alternate functions for input capture

◮ Step 2: Setting CPU clock input, PCLK0-1 registers
◮ Step 3: Prescaling, TxPR, TxPC, TxC registers
◮ Step 4: Selecting clock input for timer, CCxR register
◮ Step 5: Capture registers for timers: TxCCR
◮ Step 6: Starting the timer using TxCR register
◮ Step 7: Generating timer interrupt using TxIR register
◮ Step 8: TxCR0-3 capture registers

Output Compare
Four 32 bit match registers

◮ Flow diagram for output compare
◮ Output compare programming
◮ TxMR0-3, TxMCR, TxEMCR registers

LPC 23xx Watchdog
The purpose of the WatchDog is to reset the microcontroller within a reasonable amount
of time if it enters an erroneous state (crashed program).When enabled, the WatchDog
will generate a system reset if the user program fails to "feed" (or reload) the Watchdog
within a predetermined amount of time.The minimum watchdog period at 60MHz is us
and the maximum is just under 5 minutes.I need feeding every 5 Hours
• Watchdog features
• Block diagram
• Watchdog related registers
• Programming watchdog timer

Vector Interrupt Controller
32 Vector interrupts, 16 priority levels, sources

◮ FIQ and IRQ generation by VIC
◮ Interrupt priorities 0-31
◮ FIQ generation block diagram and related registers
◮ VIC programming
◮ External interrupts

LPC 23xx ADC-DAC
ADC features
◮ ADC function
◮ ADC programming
◮ ADC related interrupts sources
◮ DAC features and programming

Installing Keil MDK-ARM
◮ The latest version is 5.24a

◮ Download link https://www.keil.com/demo/eval/arm.htm
◮ File name: MDK524a.EXE
◮ File Size: 815 MB
◮ Operating system: Windows
◮ Note: This package itself does not have support for LPC
23xx
series

Installing Legacy Support for ARM7, ARM9 and Cortex-R
The latest version is 5.24

◮ Download link http://www2.keil.com/mdk5/legacy
◮ File name: MDK79524.EXE
◮ File size: 126.8 MB
◮ Note: This add-on package is required for NXP LPC
23xx
series

Function for initializing timer0
void initTimer0(void)
{
/*Assuming that PLL0 has been setup with CCLK = 50Mhz
and PCLK also = 50Mhz.*/
T0CTCR = 0x0; // Select timer
T0PR = 50000-1; //(Value in Decimal!) - Increment T0TC at
every 50000
clock cycle
//count begins from zero hence subtracting 1
//50000 clock cycles @50Mhz = 1 mS
T0TCR = 0x02; //Reset Timer
}

Function for generating delay
void delay(unsigned int milliseconds) // Using Timer0

{
T0TCR = 0x01; //Enable timer
while(T0TC < milliseconds); //wait until timer counter reaches
the desired delay
T0TCR = 0x00; //Disable timer
}

Program for PLL
void initClocks(void)
{
PLL0CON = 0x01; //Enable PLL
PLL0CFG = 0x24; //Multiplier and divider setup
PLL0FEED = 0xAA; //Feed sequence
PLL0FEED = 0x55;
while(!(PLL0STAT & 0x00000400)); //is locked?
PLL0CON = 0x03; //Connect PLL after PLL is locked
PLL0FEED = 0xAA; //Feed sequence
PLL0FEED = 0x55;
VPBDIV = 0x01; // PCLK is same as CCLK i.e.60
MHz
}

Using interrupt method generating delay
#include <LPC23xx.h>
#define MR0I (1<<0) //Interrupt When TC matches MR0
#define MR0R (1<<1) //Reset TC when TC matches MR0
#define DELAY_MS 500 //0.5 Seconds Delay
#define PRESCALE 50000 //50000 PCLK clock cycles to
increment TC by 1
void delayMS(unsigned int milliseconds);
void initClocks(void); // PLL Function
void initTimer0(void);
__irq void T0ISR(void); //Interrupt function ISR

int main(void)
{
initClocks(); //Initialize CPU and Peripheral Clocks @
50Mhz
initTimer0(); //Initialize Timer0
IO0DIR = 0xFFFFFFFF; //Configure all pins on Port 0 as
Output
IO0PIN = 0xF;
T0TCR = 0x01; //Enable timer
while(1); //Infinite Idle Loop //return 0; //normally this wont
execute ever :P
}

void initTimer0(void)
{
//----------Configure Timer0-------------
T0CTCR = 0x0;
T0PR =50000; //Fosc= 50 Mhz
T0MR0 = DELAY_MS-1;
//(Value in Decimal!) Zero Indexed Count - hence
subtracting 1
T0MCR = MR0I | MR0R; //Set bit0 & bit1 to High which is to :
Interrupt &
Reset TC on MR0
//----------Setup Timer0 Interrupt-------------
VICVectAddr4 = (unsigned )T0ISR; //Pointer Interrupt Function
(ISR)
VICVectCntl4 = 0x20 | 4; //0x20 (i.e bit5 = 1) -> to enable
Vectored IRQ slot
//0x4 (bit[4:0]) -> this the source number - here its timer0
which has VIC
channel mask # as
VICIntEnable = 0x10; //Enable timer0 int
}
__irq void T0ISR(void)
{
long int regVal;
regVal = T0IR; //Read current IR value
IO0PIN = ~IO0PIN; //Toggle the state of the Pins
T0IR = regVal; //Write back to IR to clear Interrupt Flag
VICVectAddr = 0x0; //This is to signal end of interrupt
execution
}

ESD contact session5
LPC23xx
peripherals
ADC in LPC23xx Series
On the LPC23XX, the number of ADC channels is dependent on the
part:
• LPC2361/62/64/65/66/67/68 and LPC2387: 6 channels
• LPC2377/78 and LPC2388: 8 channels
Registers for ADC channels 6 and 7 are reserved on the
LPC2361/62/64/65/66/67/68 and
LPC2387 parts.
The ADC is configured using the following registers:
1. Power: In the PCONP register* ,set bits PCADC.
Remark: On reset, the ADC is disabled. To enable the ADC, first set the
PCADC bit,and then enable the ADC in the AD0CR register (bit PDN) #. To
disable the ADC, first clear the PDN bit, and then clear the PCADC bit.
2. Clock: In the PCLK_SEL0 register , select PCLK_ADC (PCLK_ADC Peripheral
clock selection for ADC). To scale the clock for the ADC, bits CLKDIV.$
3. Pins: Select ADC pins and pin modes in registers PINSELn and PINMODEn
• 4. Interrupts: To enable interrupts in the ADC, see below table.
Interrupts are enabled in the VIC using the VICIntEnable register.
Features
• 10 bit successive approximation analog to digital converter.
• Input multiplexing among 6 pins or 8 pins.
• Power down mode.
• Measurement range 0 to 3 V.
• 10 bit conversion time 2.44 s.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition on input pin or Timer Match signal.
• Individual result registers for each A/D channel to reduce interrupt
overhead.
STEP-1 Enable ADC Pins using PINSEL
• Pin function Select register 0 (PINSEL0 - 0xE002 C000)
• PINSEL0= PINSEL0| (3<<8) ; // AD0_6
• PINSEL0= PINSEL0| (3<<10) ; // AD0_7
STEP-2 Configure ADC Peripheral Clock
• Related Register - ADCR A/D Control Register. The ADCR register must
be written to select the operating mode before A/D conversion can
occur
STEP-2 Configure ADC Peripheral Clock
• Related Register - ADCR A/D Control Register. The ADCR
• register must be written to select the operating mode before A/D
• conversion can occur
• #define CLKDIV 6
• // Dividing PCLK by CLKDIV
• AD0CR = AD0CR|(0x0000FF00&(CLKDIV<<8));
STEP-3 Enable ADC
• Related Register - ADCR 21st Bit PDN
#define PDN 1<<21
AD0CR = AD0CR|PDN; // ADC is operational

STEP-4 Select ADC Channel and its mode
STEP-5 Read Converted Data
STEP-5 Read Converted Data
#define DATA_MASK 0x0000FFC0;
// wait to finish conversion
while(!(AD0GDR&(0x80000000)));
val = AD0GDR;
val = val & DATA_MASK;
return(val>>6);
VIC in LPC2xxx Series
Pin connect Block
• All of the I/O pins on the LPC2300 are connected to a
number of internal functions via a multiplexer called the
pin select block.
• It allows the user to configure a pin as GPIO or select up
to three other functions.
• On reset all the I/O pins are configured as GPIO.
• The secondary functions are selected through the PINSEL
registers.
• The EINT0 interrupt line shares the same I/O pin as GPIO
2.10.
• If pin low during reset, forces the LPC2300 to enter the
bootloader command handler.
• To use the external interrupt , configure the Pin Select
register to switch from the GPIO function to EINT0
External Interrupts
• Controlled by 4 registers
• EXMODE register can select whether the interrupt is
level or edge sensitive.
• If edge sensitive, the EXPOL register is used to qualify
whether the interrupt is triggered on the rising edge
or falling edge.
• In the case of level sensitive triggering, the external
interrupts can only trigger on a logic zero level.
• If the Power Down Mode is being used, the EXWAKE
register can enable an interrupt to wake up the CPU.
• To set up a simple interrupt source program,
configure the EINT0 interrupt to be level sensitive and
then connect to the processor pin via the Pinsel 0
register.
FIQ Interrupt
FIQ Interrupt
Example Program: FIQ Interrupt
• This function sets up the external interrupts as an FIQ interrupt then
sits in a loop.
IRQ
IRQ
IRQ
IRQ
Same as FIQ
Difference in VIC table
ESD contact session 6
SPI and ARM assembly programming
Summary: SPI and SSP
◮ SPI features
◮ SPI master slave model
◮ SPI communication
◮ Block diagram
◮ SPI programming
◮ SSP features
◮ SSP master slave model
◮ TI and micro-wire formats
◮ SSP programming
SPI(Serial Peripheral Interface)
The SPI is configured using the following registers:
1. Power: In the PCONP register, set bit PCSPI.
Remark: On reset, the SPI is enabled (PCSPI = 1).
2. Clock: In PCLK_SEL0 select PCLK_SPI . In master mode, the
clock must be scaled down
3. Pins: Select SPI pins and their modes in PINSEL0 to PINSEL4 and
PINMODE0 to PINMODE4
4. Interrupts: Interrupts are enabled in the S0SPINT register. Interrupts are
enabled in the VIC using the VICIntEnable register .
Remark: In the VIC, the SPI shares its interrupts with the SSP0 interface.
Features
• Compliant with Serial Peripheral Interface (SPI) specification.
• Synchronous, Serial, Full Duplex Communication.
• SPI master or slave.
• Maximum data bit rate of one eighth of the input clock rate.
• 8 to 16 bits per transfer
Master operation
1. Set the SPI clock counter register to the desired clock rate.
2. Set the SPI control register to the desired settings.
3. Write the data to transmitted to the SPI data register. This write starts the SPI data
transfer.
4. Wait for the SPIF bit in the SPI status register to be set to 1. The SPIF bit will be set after
the last cycle of the SPI data transfer.
5. Read the SPI status register.
6. Read the received data from the SPI data register (optional).
7. Go to step 3 if more data is required to transmit.
Note: A read or write of the SPI data register is required in order to clear the SPIF status
bit. Therefore, if the optional read of the SPI data register does not take place, a write to
this register is required in order to clear the SPIF status bit.
Slave operation
1. Set the SPI control register to the desired settings.
2. Write the data to transmitted to the SPI data register (optional). Note that this can only
be done when a slave SPI transfer is not in progress.
3. Wait for the SPIF bit in the SPI status register to be set to 1. The SPIF bit will be set
after the last sampling clock edge of the SPI data transfer.
4. Read the SPI status register.
5. Read the received data from the SPI data register (optional).
6. Go to step 2 if more data is required to transmit.
Note: A read or write of the SPI data register is required in order to clear the SPIF status
bit. Therefore, at least one of the optional reads or writes of the SPI data register must
take place, in order to clear the SPIF status bit.
SPI block diagram
SPIx_IN VTREG
• The SPIx_IN VTREG (where x indicates the SPI port 0, 1, 2, and so on)
contains a byte which is received via the MCU SPI (Serial Peripheral
Interface) port on the next SPI transfer. You may use this VTREG in a
simulation script.
signal void spi_func (void) {
while (1) {
wwatch (SPI0_OUT);
printf ("SPI0_OUT: %2.2X\n", (unsigned) SPI0_OUT);
SPI0_IN = SPI0_OUT + 1;
}
}
This signal function returns the SPI byte send plus 1 on the
next SPI transfer.
SPIx_OUT VTREG
• The SPIx_OUT VTREG (where x indicates the SPI port 0, 1, 2, and so
on) contains a byte output via the MCU SPI (Serial Peripheral
Interface) port. When your simulated program sends a byte via SPI,
the SPIx_OUT VTREG is set with the value output.
signal void spi_watcher (void) {
while (1) {
wwatch (SPI1_OUT);
printf ("SPI1_OUT: %2.2X\n", (unsigned)
SPI1_OUT);
}
}
Program for SPI Master (include necessary
header files)
#include <lpc214x.h>
#include <stdint.h>
#include <string.h>
#include "LCD-16x2-8bit.h“
#include <stdio.h>
Initialization for Master
•Using pin select register (PINSEL),
void SPI_Init() configure P0.4, P0.5, P0.6 and P0.7
{ as SCK0, MISO0, MOSI0 and GPIO
respectively. SSEL (P0.7) is
PINSEL0 = PINSEL0 | 0x00001500;
/* Select P0.4, P0.5, P0.6, P0.7 as SCK0, configured as general purpose
MISO0, MOSI0 and GPIO */ output pin in order to select slave
device.
S0SPCR = 0x0020; /* SPI Master
mode, 8-bit data, SPI0 mode */ •Using S0SPCR, SPI master mode
is selected with 8-bit data and CPOL
S0SPCCR = 0x10; /* Even number,
minimum value 8, pre scalar for SPI Clock = CPHA =0. S0SPCR value will
*/ change according to configuration
required.
}
•Select clock pre-scalar using
S0SPCCR.
SPI0 Master Write Mode
void SPI_Write(char data) • Make SSEL pin low (we have configured
{ SSEL pin as GPIO to select slave) using
IOCLR to select slave.
char flush; • Load data to be written into the data
IO0CLR = (1<<7); /* SSEL = 0, register.
enable SPI communication with slave */ • Wait till transmission is completed, i.e. till
S0SPDR = data; /* Load data to be the SPIF bit becomes 1.
written into the data register */ • Make SSEL pin high using IOSET to
while ( (S0SPSR & 0x80) == 0 ); /* deselect the slave and to disable SPI
Wait till data transmission is completed */ transmission to that device.
flush = S0SPDR;
IO0SET = (1<<7); /* SSEL = 1,
disable SPI communication with slave */
}
SPI0 Master Read Mode
char SPI_Master_Read() { • Make SSEL pin low (we have
IO0CLR = (1<<7); /* SSEL = 0, enable SPI configured SSEL pin as GPIO to select
communication with slave */ slave) using IOCLR to select slave.
S0SPDR = 0xFF; /* Transmit Flush byte • Transmit Flush Byte.
*/ • Wait till data transmission is
while ( (S0SPSR & 0x80) == 0 ); /* Wait completed. When data transmission is
till data transmission is completed */ completed, data sent by slave will be
received.
IO0SET = (1<<7); /* SSEL = 1, disable SPI • Make SSEL pin high using IOSET to
communication with slave */ deselect the slave and to disable SPI
return S0SPDR; /* Return the data transmission to that device.
received */ } • Read the data in the data register. This
is the received data.
Main function
int main(void) {
int i,j;
i = 0; j = 0;
uint16_t rx1;
char receive, transmit[7];
memset(transmit,0,7);
LCD_Init();
SPI_Init();
LCD_String("Master send");
SPI_Write(0x01);
for(i=0;i<16;i++) {
sprintf(transmit,"i = %d",i);
while(transmit[j] != 0) {
SPI_Write(transmit[j]);
delay_ms(100);
j++;
}
SPI_Write('\0');
LCD_Command(0xC0);
LCD_String(transmit);
memset(transmit,0,7);
j = 0;
} //for loop end
return 0;
}//main end
Program for SPI Slave (include necessary
header files)
#define F_CPU 8000000UL #define LCD_PORT PORTD
#include <avr/io.h> #define LCD_DATA_PORT_DIRECTION
#include <util/delay.h> DDRD
#define LCD_COMMAND_PORT PORTC
#include <string.h> #define
#define MOSI PB5 LCD_COMMAND_PORT_DIRECTION
#define MISO PB6 DDRC
#define SCK PB7 #define RS PC0
#define SS PB4 #define RW PC1
#define EN PC2
void LCD_CMD(char command) {
LCD_PORT = command;
LCD_COMMAND_PORT = (0<<RS)|(0<<RW)|(1<<EN); /* EN = 1,
RS = 0, RW = 0 */
_delay_ms(2);
LCD_COMMAND_PORT = (0<<RS)|(0<<RW)|(0<<EN); /* EN = 0, RS = 0,
RW = 0 */
_delay_ms(5);
}
void LCD_INIT(void) {
LCD_DATA_PORT_DIRECTION = 0xFF; LCD_COMMAND_PORT_DIRECTION =
0xFF;
_delay_ms(20); LCD_CMD(0x38); /* Initialize lcd */
LCD_CMD(0x0C); /* Display on cursor off */
LCD_CMD(0x06); /* Auto increment cursor */
LCD_CMD(0x01); /* Display clear */
LCD_CMD(0x80); /* First line first position */
}
void LCD_STRING (char* msg) {
int i=0;
while(msg[i]!=0) {
LCD_PORT = msg[i];
LCD_COMMAND_PORT = (1<<RS)|(0<<RW)|(1<<EN); /* EN = 1, RS = 1, RW = 0 */
_delay_ms(2);
LCD_COMMAND_PORT = (1<<RS)|(0<<RW)|(0<<EN); /* EN = 0, RS = 1, RW = 0 */
_delay_ms(5);
i++;
}
}
void LCD_CHAR (char msg) {
LCD_PORT = msg;
RW = 0 */
_delay_ms(2);
RW = 0 */
_delay_ms(5);
}
Initialization for Slave
void SPI0_INIT( void ) { •PB4, PB5, PB6 and PB7 are
DDRB = DDRB | (1<<MISO); /* Make the SS, MOSI, MISO and SCK
MISO output */ pins respectively.
DDRB &= ~( (1<<MOSI) | (1<<SCK) | •Using data direction register,
(1<<SS) ); /* Make MOSI, SCK and SS configure the MISO pin as
pins as inputs. */ output. Also configure MOSI,
SPCR = (1<<SPE); /* Enable SPI */ } SS and SCK pins as input pins.
•Enable SPI using SPCR
register.
SPI Slave Write Mode
• Load data to be written into
void the data register.
SPI_SLAVE_WRITE_CHAR(char ch) • Wait till transmission is
{ completed, i.e. till the SPIF
char flush; bit becomes 1.
SPDR = ch; /* Load data to be
written into the data register */
while(!(SPSR & (1<<SPIF))); /* Wait
till data transmission is completed */
flush = SPDR; /* Return the data
received */ }
SPI Slave Read Mode
unsigned char
SPI_SLAVE_READ_CHAR() {
while(!(SPSR & (1<<SPIF))); /* Wait
till data reception is completed */
return SPDR;
}
•Wait till SPIF bit becomes 1, i.e. till
data reception is completed.
•Read the data in the data register.
This is the received data.
Main function for slave
int main(void) {
int i = 0;
int j = 0;
int k = 0;
unsigned char receive[7], rx;
SPI0_INIT();
LCD_INIT();
LCD_STRING("Slave receive");
memset(receive,0,7);
while(SPI_SLAVE_READ_CHAR() != 0x01);
do {
do {
receive[j] = SPI_SLAVE_READ_CHAR();
rx = receive[j];
j++;
}
while (rx != 0);
LCD_CMD(0xC0);
for(i=0;i<j-1;i++)
LCD_CHAR(receive[i]);
memset(receive,0,7);
j = 0;
} while (k != 16);
return 0;
}
Summary: I2C and I2S Interfaces
◮ I 2C features
◮ I 2C communication protocol
◮ Data transfer modes in I 2C
◮ Operating modes in I 2C
◮ Transmission data frames
◮ Arbitration loss
◮ Frequency of communication
◮ I 2C block diagram
◮ I 2S interface
The important difference between I2C and SPI
( I2C vs SPI ) communication protocol
I2C SPI
I2C can be multi-master and multi-slave, which means there SPI can be multi-slave but does not a multi-master serial
can be more than one master and slave attached to the I2C protocol, which means there can be only one master
bus. attached to the SPI bus.
I2C is a half-duplex communication protocol. SPI is a full-duplex commination protocol.
I2C has the feature of clock stretching, which means if the Clock stretching is not the feature of SPI.
slave cannot able to send fast data as fast enough then it
suppresses the clock to stop the communication.
I2C is used only two wire for the communication, one wire is SPI needs three or four-wire for communication ((depends on
used for the data and the second wire is used for the clock. requirement), MOSI, MISO, SCL, and Chip-select pin.
I2C is slower than SPI. In comparison to I2C, SPI is faster.
I2C draws more power than SPI. Draws less power as compared to I2C.
I2C is less susceptible to noise than SPI. SPI is more susceptible to noise than I2C.
I2C is cheaper to implement than the SPI Costly as compared to I2C.

communication protocol.
I2C work on wire and logic and it has a pull-up resistor. There is no requirement of a pull-up resistor in the
case of the SPI.
In I2C communication we get the acknowledgment bit Acknowledgment bit is not supported by the SPI
after each byte. communication protocol.
I2C ensures that the data sent is received by the slave SPI does not verify that data is received correctly or
device. not.
I2C support multi-master communication. SPI does not support multi-master communication.
I2C is a multi-master communication protocol that’s SPI is not a multi-master communication protocol, so it
why it has the feature of arbitration. does not consist of the properties of arbitration.
I2C is the address base bus protocol, you have to send In the case of the SPI, you have to select the slave using
the address of the slave for the communication. the slave select pin for the communication.
I2C has some extra overhead due to start and stop SPI does not have a start and stop bits.
bits.
I2C supports multiple devices on the same bus SPI requires additional signal (slave select lines) lines to
without any additional select lines (work on the basis manage multiple devices on the same bus.
of device address).
I2C is better for long-distance. SPI is better for a short distance.
I2C is developed by NXP. SPI is developed by Motorola.

ARM assembly Programming
ARM assembly Program
ARM Instruction Summary
ARM Instruction Summary
ARM instruction Summary
ARM instruction Summary
ARM Instruction Set format
Conditional Execution
• Each of the 16 values causes the instruction to be executed or skipped according
to the N,Z,C,V flags in the CPSR.
Data Processing Instructions
MULtiplication
• ADD r3,r2,r1,LSL #3
r3=r2+8*r1
• ADD r5,r5,r3,LSL r2
r5:=r5+r3*2^r2
• MOV r12,r4,ROR r3
R12:r4 rotated right by value of r3
• LSL: Logical shift left by 0 to 31 places, 0 filled at the lsb end
• LSR, ASL(arithmetic shift left), ASR, ROR(rotate right), RRX(rotate right
extended by 1 place)
Multiply Instructions
Base+Offset addressing
Multiple register data transfer
First assembly Program
ARM Control Flow Instructions
B LABEL
...
LABEL . . .
Conditional Branches
MOV r0, #0 ;initialize counter
LOOP . . .
ADD r0, r0, #1 ;increment loop counter
CMP r0, #10 ;compare with limit
BNE LOOP ;repeat if not equal
. . . ;else fall through
Branch Conditions
• B, BAL Always take branch
• BEQ Equal Comparison equal or result zero
• BNE Not equal Comparison not equal or result non-zero
• BPL Plus Result positive or zero
• BMI Minus Result negative
• BCC Carry clear Arithmetic operation did not give carry out
• BLO Lower Unsigned comparison gave lower
• BCS Carry set Arithmetic operation gave carry out
• BHS Higher, same Unsigned comparison gave higher or same
Branch Conditions
• BVC Overflow clear No overflow occurred; signed integer operation
• BVS Overflow set Overflow occurred; signed integer operation
• BGT Grater than Gave greater than; signed integer operation
• BGE Greater, equal Gave greater than or equal; signed integer
operation
• BLT Lower than Gave less than; signed integer operation
• BLE Less or equal Gave less than or equal; signed integer operation
• BHI Higher Unsigned comparison gave higher
• BLS Lower, same Unsigned comparison gave lower or same
Conditional Execution
◮ Method 1:
◮ Method 2:
CMP r0, #5
CMP r0, #5 ;if (r0 != 5) {
BEQ BYPASS ; ADDNE r1, r1, #0 ;
if (r0 != 5) { r1 = r1 + r0 - r2
ADD r1, r1, #0 ; SUBNE r1, r1, r2 ;}
r1 = r1 + r0 - r2 ...;
SUB r1, r1, r2 ;}
BYPASS . . . ;
Branch and Link Instructions
Subroutine Return Instructions
Jump Tables
IF statements
Switch statements
Do while
For loop
Example
Development Steps for MDK-ARM
◮ Create a new project
◮ Choose a target device
◮ Add a new file to project
◮ Write ALP in the added file
◮ Choose device options
◮ Assemble the ALP
◮ Debug
Choosing Options
◮ Target options
◮ Clock frequency: 12 MHz
◮ Code generation: ARM-mode, enable “use MicroLib”
◮ Memory layout: default
◮ Linker options
◮ Enable “Use memory layout from target dialog”
◮ Remove scatter file if any
◮ Debug options
◮ “Use simulator”
Program
Structure
Program
Define Input Data
Program
Define Output Data
Program
Get Address of Input Data
Program
Get Address of Output Data
Program
Branching to Subroutine
Program
Getting Values of Source Operands A and B
Program
Comparison of Operands and Conditional Branch
Program
If A > B, Perform Y = C - D

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Embedded System Design

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