ESD Merged CS 01-11

EEEZG512
Embedded Systems
Design Dept. of Electrical & Devesh Samaiya
BITS Pilani Electronics Engg
Pilani Campus Pilani Campus
BITS Pilani
Pilani Campus
EEE ZG512
Contact Session – I
Purpose of Contact Session
BITS Pilani, Pilani Campus

Pre Contact Hour Content

Overview of RL1.1
● Introduction & Definition of Embedded Systems.
● A system within a system.
● Difference between general purpose computing systems

and embedded computing systems.
● Characteristics of an Embedded System.
● Performance Evaluation.

Embedded System!
EMBEDDED = Placed Inside
Embedded Computing System !
A small computing system embedded inside a bigger electro-mechanical system, doing a specific
job, often with real time constraints.

Think of computer as a component or a machine part !
Just like a motor, bearing or gear….

Hard Real Time !!!!

Computing?

How do we embed?
We need a much smaller version of this!

Tiny Computers!
8- bit Microcontrollers
Intel 8051, Microchip PIC, Atmel AVR, STM8 etc.
16-bit Microcontrollers
MSP430 by Texas Instruments
32-bit Microcontrollers
AVR32, PIC32, ARM7, ARM Cortex M0, M4, M0+ etc.
System on Chip devices along with FPGA fabric interface
They comes in variety of packages and peripheral options...

Overview of RL1.2
● Development Cycle of an Embedded system.

● Hardware / Software Design.
● Small Scale Embedded Systems
○ COTS
○ Battery Operated
○ Board Level Design
○ ASM / C
● Medium Scale Embedded Systems
○ Computationally intensive
○ may involve peripheral library or OS abstraction to hardware
○ C or higher languages
○ Might require distributed computing
● Sophisticated Mission Critical Systems
○ Satisfy real time constraints
○ Safety critical systems
●
USER INPUTS
Requirement
Analysis
Requirement Definitions
Specifications
Functional Specifications
System
Hardware Design Hardware Architecture Architecture Software Architecture
Software Design
Hardware Software
Implementation Implementation
Hardware Testing Software Testing
System Integration
System Validation
Operation & Maintenance

Multidisciplinary Aspects

Firmware!
1. We usually do not write application software.
2. We write firmware and sometimes middleware.
3. We write it in C / ASM.
WHY?
● C Data structures resembles to those used in

Controllers and Processors.
● Efficient compiler, simple construct.
● Efficient Bit manipulation.
● Most widely supported higher level language.

Overview of RL1.2.1
● CPUs in embedded systems.

● RISC and CISC
● Pipeline in RISC and Pipeline Hazards
● Microprocessor and Microcontroller
Which one is more popular in embedded systems

design, why?

Overview of RL1.2.2
● Requirements for a GPP to qualify as an embedded

systems CPU.
○ Low Interrupt latency in the CPU architecture.
○ Support for Atomic Operations.
● DSP Processors.
○ Microprocessot + MAC unit
● Application Specific Processors / System on Chip
○ Security needs
○ Multimedia processing requirements (Cemara I/F, Video Codec)
○ Communication protocol requirements
● How to choose a suitable processor / SoC for your
application?

Cost Range of Embedded
Computing Devices?
Data Source - ST Microelectronics
Data Source - mouser.in

Overview of RL 1.2.3
● Memory types in Embedded Systems

● CPU registers
● Cache Memory (tav with and without multilevel cache)
● Volatile / Nonvolatile memories
● RAM/ ROM/ Hybrid
● FRAM - for fast access non volatile storage
● Flash
● SD Card
● Dynamic Memory Allocation

○ Programs larger than memory
○ Multiple programs in memory
○ Swapping

Overview of RL 1.2.4
● Hit and Miss

● Cache Organization
○ Direct Mapping
○ Set Associative

Design Thinking
Assignment
To Design a discharge capacity tester for Li-ion cells.

● Li-ion cells works in voltage range of 3.5 to 4.2 volts.
● A fully charged cell will be at around 4.2V and a

completely discharged cell would be at around 3.5.
● Depending on the chemistry of the cell, discharge

current can vary. Example, 3500mAH at 10A max
discharge rate.

Design Thinking
Assignment
● To test the discharge capacity of the cells, a constant,

known amount of current must be drawn continuously
from the cell. How to do that?
● At the same time monitor the voltage levels of the cell.
How to do that?
● Keep checking if the current is maintaining the levels or
not.
● Once the voltage drops to a threshold (say 3.5V)
withdraw the load from battery and measure the total
time of the process from fully charged cell to a fully
discharged cell.

Calculation of result?
Suppose you were drawing a current of 1A form the cell

and it took total time of 2 hours to fully discharge this cell.
What is the discharge capacity of cell under test?

Hardware Components!
● Display to show the set discharge current and show the

final result
● Human interface mechanism to set the discharge
current and cut off voltage.
● Microcontroller to drive the dummy electronic load, drive
display, take user inputs and measure current, voltage,
time and final result.
● Electronic Load
● Alarm to indicate end of testing.

EEEZG512
Embedded Systems
BITS Pilani
Pilani Campus
EEE ZG512
Contact Session – 2
Pre Contact Hour Content

Design Thinking Assignment
HW1 Discussion
To Design a discharge capacity tester for Li-ion cells.

● Li-ion cells works in voltage range of 3.5 to 4.2 volts.
● A fully charged cell will be at around 4.2V and a

completely discharged cell would be at around 3.5.
● Depending on the chemistry of the cell, discharge

current can vary. Example, 3500mAH at 10A max
discharge rate.

Design Thinking
Assignment
● To test the discharge capacity of the cells, a constant,

known amount of current must be drawn continuously
from the cell. How to do that?
● At the same time monitor the voltage levels of the cell.
How to do that?
● Keep checking if the current is maintaining the levels or
not.
● Once the voltage drops to a threshold (say 3.5V)
withdraw the load from battery and measure the total
time of the process from fully charged cell to a fully
discharged cell.

● Display to show the set discharge current and show the

final result
Most suitable would be a 4 digit seven segment display.
Small in size, easy to drive, visible from distance.
Scanning type Driving by MCU
Inbuilt Driver

● Human interface mechanism to set the discharge current

and cut off voltage.
Tactile switches are best suited for this application.
Cheap, Small, Easy to use. GPIO driven.
Minimum 3 switch required.
1. To increment the current / cutoff voltage
2. To decrement the current / cutoff voltage
3. To select the setting mode to current or cut off

● Dummy Load Design

We need to increment or decrement the discharge current
in steps of 100mA on press of a button. Max value can be
say 5A and minimum would be 100mA. Our dummy load
must satisfy the criteria.

Source - http://www.arachnidlabs.com/blog/2013/02/05/introducing-re-load/

● Microcontroller to drive the dummy electronic load, drive

display, take user inputs and measure current, voltage, time
and final result.
We need a controller which must have -
1. ADC at least 2 channels
2. At least 12 GPIO
3. PWM support
4. Low cost
5. 1x 8/16 Bit Timer preferably with prescaler
6. Cost and availability of development resources
(Software IDE, Library, Human Programmer) to
reduce time to market.
7. Device Package (DIP/ SMD type)
MCU choice!!!
● STM8S003F3P6
● N76E003AT20
● ATmega8A-PU
● and many more…

Overview of RL1.2.5
● Power, Clock and Reset.
● Power
○ Voltage ranges in ES.
○ Power Saving Schemes. (Frequency, Idle and Sleep Modes)
● Clock Source
○ Crystal
○ Ceramic Resonators
○ External IC clock generator
● Reset
○ Power on Reset (H/W), External Reset
○ Invalid instructions
○ Clock Monitor
○ Watchdog Timer

Overview of RL1.2.6
Interrupt Handling, Timers, ADC, DAC, Communication

Interfaces
● Timer
○ Input Capture.
○ Output Compare
○ PWM
● Interrupt Handlers
○ Hardware External Interrupts
○ Internal event driven interrupts
○ Priority
○ Latency
● ADC
● DAC
● Serial and Parallel Communication Interfaces in ES.

Overview of RL1.3.1
Software Components of Embedded Systems

● Operating Systems
○ RTOS
○ Normal OS
● Compiler / Assembler / Linker
● Device Driver
● Scheduling Schemes in RTOS.

user programs
libraries
User Level
Kernel Level
system call interface
file subsystem ipc

process
control
sub scheduler
Buffer cache
system
memory
management
character block
device driver
Kernel Level hardware control
Hardware Level
actual hardware
Block Diagram of the System Kernel

Source: The design of the unix operating system by Maurice J. Bach, figure 2.1
Overview of RL1.3.2
● Challenges in ESD
● Application Specific System on Chip
○ Network Connectivity
○ Encryption Requirements
○ Bluetooth / NFC requirements
○

EEEZG512
Embedded Systems
BITS Pilani
Pilani Campus
EEE ZG512
ARM Architecture

What makes a good processor?
• Fast!
• Support for high level language
• Support for Operating System
• Support for system development
• Efficient use of memory resources
• Legacy Support
• Low/ Efficient power consumption

What Processors Do!!!
If we wish to design a faster processor, we must first find out what
they spend their time on?
Instruction Type Dynamic Usage
Data movement 43%
Control flow 23%
Arithmetic operations 15%
Comparisons 13%
Logical operations 5%
Other 1%
Source - Section 1.5.3 ARM System on Chip Architecture by Steve Furber

Processor Design Trade-offs
• Prior to 1980, major focus was on increasing the instruction and
in turn hardware complexity in an attempt to reduce the
semantic gap that compiler has to bridge.
• Memories were much slower than processor.
• This approach lead to CISC.
• All the improvement was in terms of increasing the number of
transistors to incorporate more complex instructions in the
processor.
• Semiconductor industry was leading the development, no
serious attempts were made to increase the capabilities using
architectural aspects.

PIPELINES
Steps in executions of an instruction
1. Fetch in instruction from memory (fetch)
2. Decode it to see what kind of instruction it is (dec)
3. Access any operands required from register bank (reg)
4. Combine the operands to form the result or a memory address
(ALU)
5. Access memory for a data operand, if necessary (mem)
6. Write the result back to the register bank (res)

PIPELINES
An Ideal pipeline situation

READ AFTER WRITE SITUATION

Pipelined Branch Instruction
Behaviour

RISC
• Fixed instruction size with few formats.
• Load store architecture
• Large general purpose register bank
• Single Cycle execution
• Hard wired Instruction decode logic (no microcodes)
• Pipelined execution
Homework - Read paper “The Case for the

Reduced Instruction Set Computer” by
Patterson and Ditzel

Architecture
The ARM architecture has been designed to allow very small, yet
high-performance implementations.
The architectural simplicity of ARM processors leads to very small

implementations, and small implementations allow devices with
very low power consumption.

The ARM is a Reduced Instruction Set Computer (RISC), as it
incorporates these typical RISC architecture features:
➔ large uniform register file

➔ load/store architecture, where data-processing operations only
operate on register contents, not directly on memory contents
➔ simple addressing modes, with all load/store addresses being
determined from register contents and instruction fields only
➔ uniform and fixed-length instruction fields, to simplify
instruction decode.

ARM Instruction Set
➔ 3-address data processing instructions. (2 source operands
registers and result register are all independently specified)
➔ Conditional execution of every instruction
➔ Powerful Load and Store Multiple registers instructions.

ARM Instruction Set Features
➔ Ability to perform a general shift operation and a general ALU
operation in a single instruction that executes in a single clock
cycle.
➔ Open instruction set extension through coprocessor
➔ Dense 16-bit compressed representation of instruction set in the
Thumb architecture.

I/O system
➔ ARM handles I/O peripherals as memory mapped devices with

interrupt support.
➔ Internal registers in these devices appear as addressable
locations within ARM’s memory map and may be read and
written using same load store instructions.
➔ Peripheral can raise interrupt request to CPU via IRQ or FIQ
lines. Both IRQ and FIQ are level sensitive and maskable.
➔ Most peripheral shares IRQ line with only one or two very time
critical peripherals will be allowed to interrupt over FIQ.

3 Stage Pipeline Implementation in ARM
Source - Section 4.1 “ARM System on Chip Architecture” by Steve Furber

ARM7TDMI Core
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0210c/DDI0210B.pdf
Datapath Activities during Data Processing Instructions

ARM Registers
ARM has 31 general-purpose 32-bit registers. At any one time, 16
of these registers are visible. The other registers are used to speed
up exception processing.
All the register specifiers in ARM instructions can address any of

the 16 visible registers.

R14 : Link Register
Register 14 is the Link Register (LR). This register holds the

address of the next instruction after a Branch and Link (BL)
instruction, which is the instruction used to make a subroutine call.
At all other times, R14 can be used as a general-purpose register.

R15 : Program Counter
Register 15 is the Program Counter (PC). It can be used in most

instructions as a pointer to the instruction which is two instructions
after the instruction being executed.
All ARM instructions are four bytes long (one 32-bit word) and are
always aligned on a word boundary. This means that the bottom two
bits of the PC are always zero, and therefore the PC contains only
30 non-constant bits.
The remaining 14 registers have no special hardware purpose. Their

uses are defined purely by software.
Software normally uses R13 as a Stack Pointer (SP).
Processor Modes
Most application programs execute in User mode. While the processor is in User mode,
the program being executed is unable to access some protected system resources or to
change mode, other than by causing an exception to occur.
This allows a suitably written operating system to control the use of system resources

CPSR Register

Status Register Across Family

USER Mode
• When writing user level programs, only the 15 general purpose,
32 bit registers (R0-R14), the PC (R15) and the CPSR is
available to the programmer.
• Remaining registers are used only for system level programming
and for handling exceptions (for example, interrupts, system
calls)

EEEZG512
Embedded Systems
BITS Pilani
Pilani Campus
EEE ZG512
ARM assembly Language Programming
ARM instruction types
➔ Data processing instructions : They use and change only

register values.
➔ Data transfer instructions : They copy memory values into
register and vice versa.
➔ Control flow instructions : Causes execution to switch to a
different address, either permanently (branch) or by saving a
return address (branch with link) to resume the original
sequence. Supervisor calls are also falls under control flow
instructions.
Conditional Execution
Every ARM instruction can be executed conditionally.
Data Processing Instructions - Binary Encoding
ADD R2, R2,#1
ADD R4,R5, R5, LSL #2
ADD R10,R15,#8
ADDS R4,R5,R6, LSR R7
Note on Immediate Values
ADD R0, R0, #4
A valid immediate operand n satisfies the following equation
n = i ROR ( 2* r)
i = number between 0 and 255 (inclusive)
r = number between 0 and 15 (inclusive)

Arithmetic Operations
➔ Operand may be unsigned or 2’s complement signed numbers.

➔ Carry in, when used, is the current value of the C bit in CPSR.
Bitwise Logical Operations
AND r0, r1, r2 implies r0[i] = r1[i] AND r2[i] for i ranging from 0 to 31.
Register Movement Operations
Register Movement Operations
Comparison Operations
CMP r1,r2 ;set cc on r1-r2 ;compare

CMN r1,r2 ;set cc on r1+r2 ;compare negated
TST r1,r2 ;set cc on r1 and r2 ; (bit) test
TEQ r1,r2 ;set cc on r1 xor r2 ; test equal
Shifted Register Operands
ADD r3, r2,r1, LSL #3 ;r3 = r2 + 8 x r1
LSL - Logical Shift Left; fill the vacated bits with zeros
LSR - Logical Shift Right; fill the vacated bits with zeros
ASL - Arithmetic Shift Left; same as LSL
ASR - Arithmetic Shift Right; fill the vacated bits with 0 if operand was positive else with 1
ROR - Rotate Right by 0 to 32 places; the bit which falls off the LSB will fill the vacated bits
RRX - Rotate Right extended by 1 place; the vacated bit (bit 31) is filled with the old value of
the C flag and the operand is shifted one place to the right. With appropriate use of the
condition codes (see below) a 33-bit rotate of the operand and the C flag is performed.
Data Transfer Instructions
Single Register Load and Store

LDR R0, [R8] ;R0 := mem32 [R8]
LDR R0, [R1, -R2] ;R0 := mem32 [R1-R2]
LDR R0, [R1, +4] ;R0 := mem32 [R1+4]
LDR R0, [R1, +4]! ;R0 := mem32 [R1+4], R1 := R1+4
LDR R0, [R1], +16 ;R0 := mem32 [R1], R1 := R1+16
LDR R0, [R1, R2, LSR#0x4]!
;R0 := mem32 [R1+(R2 LSR 0x4)]
;R1 := R1+R2 LSR 0x4
Multiple Register Transfer Instruction
LDM/STM instructions allow between 1 to 16 registers to be

transferred to or from memory. Block transfer instructions have got
efficient utilization in
➔ implementing stack for saving and restoring context

➔ moving large blocks of data around memory
LDMIA r1, {r0, r2, r5} ; r0 := mem32 [r1]

; r2 := mem32 [r1+4]
; r5 := mem32 [r1+8]
Stack related LDM/STM instructions
Full Stack - SP points to last occupied address, thus needs

pre-decrementing/ pre-incrementing before the push.
Empty Stack - SP points to next to be occupied address, thus require

post-decrementing (descending) / pre-incrementing(ascending) after
the push.
STMFD / LDMFD ; Full descending stack

STMFA/ LDMFA ; Full ascending stack
STMED/ LDMED; Empty descending stack
STMEA/ LDMEA; Empty descending stack
Lowest register number is always transferred to/from the lowest memory location accessed
.
Binary encoding of multiple register transfer instructions
Saving context
STMFD r13!, {r0 - r2, r14}
Restoring context
LDMFD r13!, {r0 - r2, pc}
Block Data Transfer
Same function as stack instructions but different context.
● STMIA / LDMIA ; Increment after

● STMIB / LDMIB ; Increment Before
● STMDA / LDMDA ; Decrement after
● STMDB / LDMDB ; Decrement before
Example
; R12 points to the start of the source data

; R14 points to the end of the source data
; R13 points to the start of the destination data
loop LDMIA R12!, {R0-R11} ; load 48 bytes

STMIA R13!, {R0-R11} ; and store them
CMP R12, R14 ; check for an end
BNE loop ; and loop until done
SWAP Instruction
SWP Rd, Rm, [Rn] ; tmp = mem32[Rn]

; mem32[Rn] = Rm
; Rd = tmp
Rn tmp
2 3
Rm
Rd
Binary Semaphore Using SWP
spin
mov r1, =semaphore
mov r2, #1
swp r3, r2, [r1] ; hold the bus until complete
cmp r3, #1
beq spin
Exceptions
➔ An exception is any condition that needs to halt the normal

sequential execution of instructions.
➔ Reset, instruction fetch or memory access fails, undefined
instruction, software interrupt or external interrupts.
Exception Handling
The ARM architecture supports a range of interrupts, traps and supervisor calls,
all grouped under the general heading of exceptions. They are all handled in
similar way :
1. The current state is saved by copying the PC into R14_exc and the CPSR into
SPSR_exc (where exc stands for the exception type).
2. The processor operating mode is changed to the appropriate mode. ARM
processor mode can also be changed by changing the CPSR.
3. The PC is forced to a value between 0x00 to 0x1C, the particular value
depending on the type of exception. Usually the address of an exception
handler will be located into those values.
4. It disables IRQs by setting bit 7 of the CPSR and if it’s FIQ, disables further
FIQs by setting bit 6 of CPSR.
When an exception occurs the ARM processor always switches to ARM state.
VECTOR TABLE
➔ A table of addresses that the ARM core branches to when an

exception is raised.
➔ These addresses commonly contain branch instructions to
exception handler routines.
Instructions at vector table addresses
Vector table addresses commonly contain branch instructions of one
of the following types:
❏ B <address> Branch relative to PC

❏ LDR PC, [PC, #offset] Loads the handler address from
memory to PC. Address is an absolute 32-bit value stored close
to the vector table. Delay in branching hence latency but can be
branched to any address in memory.
❏ LDR PC, [PC, #-0xff0] Loads ISR address from
0xFFFFF030. Will be explained with Vectored Interrupt
Controller in next class.
❏ MOV PC, #immediate Copies an immediate value into PC.
But immediate value is limited by constraints discussed earlier.
Exception Return
Once the exception has been handled, the user task is normally
resumed. This requires the handler code to restore the user state
exactly as it was when the exception first arose:
❏ Any modified user registers must be restored from the handler’s

stack.
❏ The CPSR must be restored from the appropriate SPSR.
❏ The PC must be changed back to relevant instruction address in
the user instruction stream.
Exception Return Contd...
❏ If CPSR is restored first, the banked R14 holding the return

address is no longer accessible.
❏ If the PC is restored first, the exception handler loses control of
the instruction stream and can not cause the restoration of CPSR
to take place.
❏ There is a need for an instruction that can perform both of these
tasks atomically as a single instruction.
To return from a SWI or undefined instruction:
MOVS PC, R14
To return from an IRQ, FIQ or prefetch abort
SUBS PC, R14, #4 ; PC = PC - 4

because there is an S at the end of SUB and PC is the destination
register, the cpsr is automatically stored from the spsr register.
To return from an data abort to retry the data access
SUBS PC, R14, #8 ; PC = PC - 8

Link Register Offsets
Exception Priorities
ASM Example Code

EEEZG512
Embedded Systems
BITS Pilani
Pilani Campus
EEE ZG512
Keil ARM MDK Demo for ARM assembly
Language Programming
ASM Example Code

Exceptions
➔ An exception is any condition that needs to halt the normal
sequential execution of instructions.
➔ Reset, instruction fetch or memory access fails, undefined
instruction, software interrupt or external interrupts.

Exception Handling
The ARM architecture supports a range of interrupts, traps and supervisor calls,
all grouped under the general heading of exceptions. They are all handled in
similar way :
1. The current state is saved by copying the PC into R14_exc and the CPSR into
SPSR_exc (where exc stands for the exception type).
2. The processor operating mode is changed to the appropriate mode. ARM
processor mode can also be changed by changing the CPSR.
3. The PC is forced to a value between 0x00 to 0x1C, the particular value
depending on the type of exception. Usually the address of an exception
handler will be located into those values.
4. It disables IRQs by setting bit 7 of the CPSR and if it’s FIQ, disables further
FIQs by setting bit 6 of CPSR.
When an exception occurs the ARM processor always switches to ARM state.

VECTOR TABLE
➔ A table of addresses that the ARM core branches to when an
exception is raised.
➔ These addresses commonly contain branch instructions to
exception handler routines.

Instructions at vector table addresses
Vector table addresses commonly contain branch instructions of one
of the following types:
❏ B <address> Branch relative to PC
❏ LDR PC, [PC, #offset] Loads the handler address from
memory to PC. Address is an absolute 32-bit value stored close
to the vector table. Delay in branching hence latency but can be
branched to any address in memory.
❏ LDR PC, [PC, #-0xff0] Loads ISR address from
0xFFFFF030. Will be explained with Vectored Interrupt
Controller in next class.
❏ MOV PC, #immediate Copies an immediate value into PC.
But immediate value is limited by constraints discussed earlier.

Exception Return
Once the exception has been handled, the user task is normally
resumed. This requires the handler code to restore the user state
exactly as it was when the exception first arose:
❏ Any modified user registers must be restored from the handler’s
stack.
❏ The CPSR must be restored from the appropriate SPSR.
❏ The PC must be changed back to relevant instruction address in
the user instruction stream.

Exception Return Contd...
❏ If CPSR is restored first, the banked R14 holding the return
address is no longer accessible.
❏ If the PC is restored first, the exception handler loses control of
the instruction stream and can not cause the restoration of CPSR
to take place.
❏ There is a need for an instruction that can perform both of these
tasks atomically as a single instruction.

To return from a SWI or undefined instruction:
MOVS PC, R14
To return from an IRQ, FIQ or prefetch abort
SUBS PC, R14, #4 ; PC = PC - 4

because there is an S at the end of SUB and PC is the destination
register, the cpsr is automatically stored from the spsr register.
To return from an data abort to retry the data access
SUBS PC, R14, #8 ; PC = PC - 8

Link Register Offsets

Exception Priorities

Software Interrupt Instruction (SWI)
A software Interrupt instruction (SWI) causes a software
interrupt exception, which provides a mechanism for
applications to call operating system calls.

SWI Handler
; Store registers r0-r12 and the link register
STMFD sp!, {r0-r12, lr}
; Read the SWI instruction
LDR r10, [lr, #-4]
; Mask off top 8 bits
BIC r10, r10, #0xff000000
; r10 - contains the SWI number
BL service_routine
; return from SWI handler
LDMFD sp!, {r0-r12, pc}ˆ

Architectural Support for High Level
Languages
High level language?
Being an RISC architecture, it is tricky to design an efficient
compiler for ARM based SoCs.
Everything need to be done using a limited set of instructions,

operands has to be in CPU registers and take care of memory
alignment restrictions, immediate operand values etc.
C!
➔ Data types, Basic and Derived

➔ Floating point arithmetic
➔ Expressions
➔ Conditional Statements
➔ Functions
➔ Dynamic memory allocation
Support for Basic Data Types
ARMv4 based processors can efficiently load and store 8, 16 or 32

bit data. However, most of the ARM data processing operations are
32-bit only.
One should use 32-bit data type and avoid using char or short
wherever possible. If you requires modulo arithmetic of the form
255+1 = 0, then use the char type.
Compiler Output with ‘i’ as char
Compiler output with ‘i’ as integer
Expressions in C
➔ Basic ARM data processing instructions implements most of the

the C integer arithmetic, bit-wise and shift primitives directly.
➔ Key to efficient evaluation of a complex expression is to get the
required values into local registers in the right order and
efficient utilization of local registers.
➔ The 3 address instruction format allows the reuse of registers
and provides flexibility to the compiler in using them.
➔ Shifted operand in data processing instructions allows single
cycle execution of many complex expressions.
Compiler casts the return value to a short type, but does not case the input values.
It assumes that the caller has already ensured that the 32-bit values r0 and r1 are in
the range of short type.
ARM Procedure Call Standard (APCS)
Function Calls
Number of arguments (variables Vs structures)
Compiles to...
Same function using structure as argument
Compiles to...
EEEZG512
Embedded Systems
BITS Pilani
Pilani Campus
EEE ZG512
LPC2xxx
Analog to Digital Demo
ADC in LPC2xxx Series
➔ LPC2148 has two inbuilt ADC modules, ADC0 & ADC1.

➔ Each ADC is of 10 bit resolution, using Successive
approximation conversion technique.
➔ ADC0 has 6 channels and ADC1 has 8 channels. (14 analog
Channels)
➔ Supports maximum clock at 4.5 MHz.
➔ 10 bit conversion time >= 2.44 s
➔ The register we must know about is, ADC Control register
(AD0CR or AD1CR) & ADGDR (ADC Global data register)
ADC in LPC2xxx Series
➔ Optional conversion on transition on input pin or Timer Match

signal.
➔ Measurement range 0 V to VREF (3V typical)
➔ Basic clocking for the A/D converters is provided by the APB
clock. A programmable divider is included in each converter, to
scale this clock to the 4.5 MHz (max) clock needed by the
successive approximation process.
➔ A fully accurate conversion requires 11 of these clocks.
STEP-1 Enable ADC Pins using PINSEL
Pin function Select register 0 (PINSEL0 - 0xE002 C000)
PINSEL0= PINSEL0| (3<<8) ; // AD0_6
PINSEL0= PINSEL0| (3<<10) ; // AD0_7

STEP-2 Configure ADC Peripheral Clock
Related Register - ADCR A/D Control Register. The ADCR
register must be written to select the operating mode before A/D
conversion can occur
REF : UM10139 NXP

STEP-2 Configure ADC Peripheral Clock
Related Register - ADCR A/D Control Register. The ADCR

register must be written to select the operating mode before A/D
conversion can occur
#define CLKDIV 6
// Dividing PCLK by CLKDIV

AD0CR = AD0CR|(0x0000FF00&(CLKDIV<<8));
STEP-3 Enable ADC
Related Register - ADCR 21st Bit PDN
#define PDN 1<<21
AD0CR = AD0CR|PDN; // ADC is operational

STEP-4 Select ADC Channel and its mode
REF : UM10139 NXP

REF : UM10139 NXP

STEP-5 Read Converted Data
Related Register - (AD0GDR - 0xE003 4004 , AD1GDR - 0xE006 0004
REF : UM10139 NXP

STEP-5 Read Converted Data
#define DATA_MASK 0x0000FFC0;
// wait to finish conversion

while(!(AD0GDR&(0x80000000)));
val = AD0GDR;
val = val & DATA_MASK;
return(val>>6);
Timer Demo -1 Accurate Delay Function
● 32-bit Timer/Counter with a programmable 32-bit Prescaler.

● Counter or Timer operation
● Up to four 32-bit capture channels per timer, that can take a
snapshot of the timer value when an input signal transitions.
● A capture event may also optionally generate an interrupt.
● Four 32-bit match registers that allow:
○ Continuous operation with optional interrupt generation on match.
○ Stop timer on match with optional interrupt generation.
○ Reset timer on match with optional interrupt generation.
Timer Demo -1 Accurate Delay Function
➔ Up to four external outputs corresponding to match registers,

with the following capabilities:
◆ Set low on match.
◆ Set high on match.
◆ Toggle on match.
◆ Do nothing on match
STEP- 1 Understanding Timer Modes
REF : UM10139 NXP

STEP- 1 Understanding Timer Modes
REF : UM10139 NXP

STEP- 2 Deriving the Data for desired task
EEEZG512
Embedded Systems Design
Devesh Samaiya
Dept. of Electrical & Electronics Engg
BITS Pilani
BITS Pilani
Pilani Campus
EEE ZG512
Serial Peripheral Interface
LPC2xxx SoC
Introduction
SPI is a full duplex serial interface.
It can handle multiple masters and slaves being connected to a given bus.
Only a single master and a single slave can communicate on the interface during a given
data transfer.
During a data transfer the master always sends 8 to 16 bits of data to the slave, and the
slave always sends a byte of data to the master.
Ring Buffer
SPI data to CPOL, CPHA relationship
SPI CPOL, CPHA Significance (AT93C46 EEPROM)
http://ww1.microchip.com/downloads/en/DeviceDoc/doc5140.pdf
The Read (READ) instruction contains the address code for the memory location to be read.
After the instruction and address are decoded, data from the selected memory location is
available at the serial output pin DO. Output data changes are synchronized with the rising
edges of serial clock SK.
SPI CPOL, CPHA Significance (W25Q64 FLASH)
https://www.winbond.com/resource-files/w25q64fw_revk%2007012
READ instruction (03h) is initiated by driving the CS pin low and shifting out instruction (03h)
and 24-bit address (A23-A0) on DI pin.The instruction code and address bits are latched on the
rising edge of the CLK input. Data is shifted out on DO at falling edge of the CLK pin.
016%20sfdp.pdf
SPI0 Registers in LPC2148
MASTER OPERATION
The following sequence describes how one should process a data transfer with the SPI block when it
is set up to be the master. This process assumes that any prior data transfer has already completed
1. Set the SPI clock counter register to the desired clock rate.
2. Set the SPI control register to the desired settings.
3. Write the data to transmitted to the SPI data register. This write starts the SPI data
transfer.
4. Wait for the SPIF bit in the SPI status register to be set to 1. The SPIF bit will be set
after the last cycle of the SPI data transfer.
5. Read the SPI status register.
6. Read the received data from the SPI data register (optional).
7. Go to step 3 if more data is required to transmit.
SLAVE OPERATION
The following sequence describes how one should process a data transfer with the SPI block when it
is set up to be a slave. This process assumes that any prior data transfer has already completed. It is
required that the system clock driving the SPI logic be at least 8X faster than the SPI.
1. Set the SPI control register to the desired settings.

2. Write the data to transmitted to the SPI data register (optional). This can only be done
when a slave SPI transfer is not in progress.
3. Wait for the SPIF bit in the SPI status register to be set to 1. The SPIF bit will be set
after the last sampling clock edge of the SPI data transfer.
4. Read the SPI status register.
5. Read the received data from the SPI data register (optional).
6. Go to step 2 if more data is required to transmit.
Interfacing Example
Interfacing Example
Source - https://www.diodes.com/assets/Datasheets/74HC595.pdf
2
I C Protocol
devesh.samaiya@pilani.bits-pilani.ac.in
I2C
Developed by Philips Semiconductor (now NXP) as a simple bidirectional two wire bus
protocol for efficient inter-IC data communication. Originally, the I2 C bus was designed to
link a small number of devices on a single card, such as to manage the tuning of a car radio
or TV.
This bus is called the Inter IC or I2C-bus. All I2C-bus compatible devices incorporate an
on-chip interface which allows them to communicate directly with each other via the
I2C-bus.
Features
➔ Only two bus lines are required; a serial data line (SDA) and a serial clock line (SCL).
➔ Each device connected to the bus is software addressable by a unique address and
simple master/slave relationships exist at all times; masters can operate as
master-transmitters or as master-receivers.
➔ It is a true multi-master bus including collision detection and arbitration to prevent
data corruption if two or more masters simultaneously initiate data transfer.
➔ Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 kbit/s in
the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in Fast-mode
Plus, or up to 3.4 Mbit/s in the High-speed mode.
Pg. 4 https://www.nxp.com/docs/en/user-guide/UM10204.pdf
SDA & SCL Signals
Both SDA and SCL are bidirectional lines, connected to a positive supply voltage via a
current-source or pull-up resistor. When the bus is free, both lines are HIGH.
SDA & SCL Signal Levels
➔ Due to the variety of different technology devices (CMOS, NMOS, bipolar)
that can be connected to the I2C-bus, the levels of the logical ‘0’ (LOW) and
‘1’ (HIGH) are not fixed and depend on the associated level of VDD.
➔ Input reference levels are set as 30 % and 70 % of VDD; VIL is 0.3VDD and
VIH is 0.7VDD.
START & STOP conditions
➔ All transactions begin with a START (S) and are terminated by a STOP (P).
➔ A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START
condition.
➔ A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP
condition.
DATA Validity
➔ The data on the SDA line must be stable during the HIGH period of the clock.
➔ The HIGH or LOW state of the data line can only change when the clock signal on
the SCL line is LOW .
➔ One clock pulse is generated for each data bit transferred.
Byte format
➔ Every byte put on the SDA line must be eight bits long.
➔ The number of bytes that can be transmitted per transfer is unrestricted.
➔ Each byte must be followed by an Acknowledge bit.
➔ Data is transferred with the Most Significant Bit (MSB) first.
➔ If a slave cannot receive or transmit another complete byte of data until it has
performed some other function, for example servicing an internal interrupt, it can
hold the clock line SCL LOW to force the master into a wait state. Data transfer then
continues when the slave is ready for another byte of data and releases clock line
SCL.
ACK / NACK
➔ The acknowledge takes place after every byte. The acknowledge bit allows the
receiver to signal the transmitter that the byte was successfully received and another
byte may be sent. The master generates all clock pulses, including the acknowledge
ninth clock pulse.
➔ The transmitter releases the SDA line during the acknowledge clock pulse so the
receiver can pull the SDA line LOW and it remains stable LOW during the HIGH
period of this clock pulse.
➔ When SDA remains HIGH during this ninth clock pulse, this is defined as the Not
Acknowledge signal. The master can then generate either a STOP condition to abort
the transfer, or a repeated START condition to start a new transfer.
ACK / NACK
There are five conditions that lead to the generation of a NACK:
1. No receiver is present on the bus with the transmitted address so there is no device to
respond with an acknowledge.
2. The receiver is unable to receive or transmit because it is performing some real-time

function and is not ready to start communication with the master.
3. During the transfer, the receiver gets data or commands that it does not understand.
4. During the transfer, the receiver cannot receive any more data bytes.
5. A master-receiver must signal the end of the transfer to the slave transmitter.
Slave address and R/W’ bit
After the START condition (S), a slave address is sent. This address is seven bits long
followed by an eighth bit which is a data direction bit (R/W) — a ‘zero’ indicates a
transmission (WRITE), a ‘one’ indicates a request for data (READ).
Master Transmitter
Master Receiver
Master Transceiver
Arbitration
Arbitration, refers to a portion of the protocol required only if more than one master is
used in the system.
A master may start a transfer only if the bus is free. Two masters may generate a START
condition on the bus at the same time. Arbitration is then required to determine which
master will complete its transmission.
Arbitration
Arbitration proceeds bit by bit. During every bit, while SCL is HIGH, each master checks
to see if the SDA level matches what it has sent.
This process may take many bits. Two masters can actually complete an entire transaction
without error, as long as the transmissions are identical.
The first time a master tries to send a HIGH, but detects that the SDA level is LOW, the
master knows that it has lost the arbitration and turns off its SDA output driver. The other
master goes on to complete its transaction.
I2C Protocol Summary
I2C in LPC2xxx
➔ Standard I2C compliant bus interfaces that may be configured as Master or Slave.
➔ Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
➔ Programmable clock to allow adjustment of I2C transfer rates.
➔ Serial clock synchronization allows devices with different bit rates to communicate
via one serial bus.
I2C Bus configuration
I2C Operating Modes
➔ In a given application, the I2C block may operate as a master, a slave or both.
➔ If processor wishes to become the bus master, the hardware waits until the bus is free
before the master mode is entered so that a possible slave operation is not interrupted.
➔ If bus arbitration is lost in the master mode, the I2C block switches to the slave mode
immediately and can detect its own slave address or general call address in the same
serial transfer.
Master Transmitter Mode
➔ I2EN must be set to 1 to enable the I2C function.

➔ If AA bit is 0, the I2C interface will not acknowledge any address when another
device is master of the bus. It basically not the master itself but not a slave
either.
➔ STA, STO, SI bts must be 0. The SI bit is cleared by writing 1 to the SIC bit in
the I2CCONCLR register.
Master Transmitter Mode Contd.
➔ The I2C interface will enter the master transmitter mode when software sets the STA
bit. The I2C logic block will send the START condition as soon as the bus is free.
➔ After the START condition is transmitted, the SI bit is set, and the status code in the
I2CSTAT register is 0x08.
➔ This status code is used to vector to a state service routine which will load the slave
address and Write bit to the I2DAT register, and then clear the SI bit.
➔ After slave+r/w transmission and acknowledgement reception the SI bit is set again,
and the possible status codes now are 0x18, 0x20, or 0x38 for the master mode, or
0x68, 0x78, or 0xB0 if the slave mode was enabled.
Transfer Rate Calculation
LAB Experiment on I2C
Interfacing I2C EEPROM device, 24Cxx series.
24Cxx I2C EEPROM Interfacing
USB
devesh.samaiya@pilani.bits-pilani.ac.in
Universal Serial Bus
➔ Universal serial bus (USB) is a communication protocol for
connecting variety of peripheral devices to the host computer.
➔ The aim of the USB interface was to find a solution to the
mixture of connection methods to the PC, in use at the time.
➔ We had serial port, parallel port, keyboard, mouse, midi,
joystick ports and so on, none of these were plug and play.
Features
➔ Single standardized interface socket.
➔ Plug and play capabilities (hot swapping)
➔ Provides power to low consumption devices.
➔ Allows many devices to be used without requiring manufacturer specific, individual
device drivers to be installed.
➔ Allows all kind of peripheral devices to communicate with the computer using a
single standard protocol and connection method.
One connector to rule them all
So the USB was developed as a new means to connect a large
number of devices to the PC, and eventually to replace the 'legacy'
ports.
USB Connectors
USB Host & Devices
➔ USB is based on a so-called 'tiered star
topology' in which there is a single host
controller and up to 127 'slave' devices.
➔ A device can be plugged into a hub, and
that hub can be plugged into another
hub and so on. However the maximum
number of tiers permitted is six.
Device Classes
http://www.usb.org/developers/defined_class
Master Slave
➔ USB is a master slave protocol.
➔ Host is the master and all the communication on the bus is initiated by the Host.
➔ There can be no communication directly between 2 USB devices.
➔ A device cannot initiate a transfer, but must wait to be asked to transfer data by the
host. The only exception to this is when a device has been put into 'suspend' (a low
power state) by the host then the device can signal a 'remote wakeup'.
Bus enumeration
➔ The host regularly polls hubs for their status.
➔ When a new device is plugged into a hub, the hub advises the host of its
change of state.
➔ The host controller in turn issues a command to enable and reset the port.
➔ Device responds and host collects information about the device.
➔ Based on the retrieved information, the host operating system determines the
device driver to be used for the device.
➔ The process of detection and identification of USB devices by a host is called
bus enumeration.
Transactions
REF : http://www.usbmadesimple.co.uk/ums_3.htm
Packet Formats 1/4
Packet ID (PID) : The first byte in every
packet is a Packet Identifier (PID) byte.
This byte needs to be recognised quickly
by the USB engine and so is not included
in any CRC checks. It therefore has its
own validity check. The PID itself is 4
bits long, and the 4 bits are repeated in an
complimented form.
Packet Formats 2/4
Token Packet : Used for SETUP, OUT and IN packets. They are always the first packet in
a transaction, identifying the targeted endpoint, and the purpose of the transaction
SYNC PID ADDR ENDP CRC5 EOP
8 bits 7 bits 4 bits 5 bits
USB transaction token packet format

Packet Formats 3/4
Data Packet : Used for DATA0, DATA1, DATA2 and MDATA packets. If a transaction
has a data stage this is the packet format used.
SYNC PID DATA CRC16 EOP
8 bits (0-1024) x 8 16 bits

bits
USB transaction data packet format

Packet Formats 4/4
Handshake Packet : Used for ACK, NAK, STALL and NYET packets. This is the packet
format used in the status stage of a transaction, when required.
SYNC PID EOP
8 bits
USB transaction handshake packet format

Data Flow Types
Data flow type Description

Control Transfer Mandatory to use Endpoint 0 IN and OUT.
Bulk Transfer Error free high volume throughput when

bandwidth is available
Interrupt Transfer Error free, low throughput, regular opportunity

for status updates etc.
Isochronous Transfer No error check, fixed bandwidth guaranteed

Endpoints
➔ USB device communication is based on pipes (logical
channels).
➔ Pipes are connections from the host controller to a logical
entity on the device, known as Endpoint.
➔ USB device can have up to 32 active endpoints - 16 into
the host controller and 16 out of the host controller..
➔ Each endpoint can transfer data in one direction only.
An endpoint has characteristics that determine the type of transfer service required
between the endpoint and the client software. An endpoint describes itself by:
➔ Bus access frequency/latency requirement

➔ Bandwidth requirement
➔ Endpoint number
➔ Error handling behavior requirements
➔ Maximum packet size that the endpoint is capable of sending or receiving
➔ The direction in which data is transferred between the endpoint and the host
Types of USB Endpoints
A USB endpoint can be one of four different types that describe how the data is
transmitted on it: (Why do we need 4 different types of endpoints)
CONTROL
INTERRUPT
BULK
ISOCHRONOUS
CONTROL ENDPOINT
➔ Control endpoints are used to allow access to different parts of the USB
device.
➔ They are commonly used for configuring the device, retrieving information
about the device, sending commands to the device, or retrieving status reports
about the device.
➔ Every USB device has a control endpoint called "endpoint 0" that is used by
the USB core to configure the device at insertion time.
➔ These transfers are guaranteed by the USB protocol to always have enough
reserved bandwidth to make it through to the device.
CONTROL TRANSFER
It is divided into three stages.
1. The SETUP stage carries 8 bytes called the Setup packet. This defines the request,
and specifies whether and how much data should be transferred in the DATA stage.
2. The DATA stage is optional. If present, it always starts with a transaction containing a
DATA1. The type of transaction then alternates between DATA0 and DATA1 until all
the required data has been transferred.
3. The STATUS stage is a transaction containing a zero-length DATA1 packet. If the
DATA stage was IN then the STATUS stage is OUT, and vice versa.
Control transfers are used for initial configuration of the device by the host, using Endpoint 0 OUT and Endpoint 0
IN, which are reserved for this purpose. They may be used (on the same endpoints) after configuration as part of the
device-specific control protocol, if required.
CONTROL TRANSFER
REF : http://www.usbmadesimple.co.uk/ums_3.htm
SETUP PACKET
Possible bRequest types in control transaction
INTERRUPT ENDPOINT
➔ They have nothing to do with interrupts.
➔ Interrupt endpoints transfer small amounts of data at a fixed rate every time the
USB host asks the device for data.
➔ These endpoints are the primary transport method for USB keyboards and
mice.
➔ They are also commonly used to send data to USB devices to control the
device, but are not generally used to transfer large amounts of data.
➔ These transfers are guaranteed by the USB protocol to always have enough
reserved bandwidth to make it through.
BULK ENDPOINTS
➔ Bulk endpoints transfer large amounts of data.
➔ These endpoints are usually much larger (they can hold more characters at
once) than interrupt endpoints.
➔ They are common for devices that need to transfer any data that must get
through with no data loss. These transfers are not guaranteed by the USB
protocol to always make it through in a specific amount of time.
➔ If there is not enough room on the bus to send the whole BULK packet, it is
split up across multiple transfers to or from the device. These endpoints are
common on printers, storage, and network devices.
ISOCHRONOUS ENDPOINT
➔ Isochronous endpoints also transfer large amounts of data,

but the data is not always guaranteed to make it through.
➔ These endpoints are used in devices that can handle loss
of data, and rely more on keeping a constant stream of
data flowing.
➔ Real-time data collections, such as audio and video
devices, almost always use these endpoints.
Device, Config, Interface & Endpoints
Device, Interface & Endpoints
USB devices are quite complex and are made up of lots of
different logical units. The relationships among these units can
be simply described as follows:
➔ Devices usually have one or more configurations.

➔ Configurations often have one or more interfaces.
➔ Interfaces have zero or more endpoint
➔ Every device is identified using a Device Descriptor structure. Host will fetch
this descriptor from device to know about the nature of the device.
➔ Possible configurations of the device are identified using a configuration

descriptor and host will enquire this to gather more information about device.
➔ Interfaces usually have one or more settings which are specified in the
Interface descriptor.
➔ Finally Interfaces have zero or more endpoint and each endpoint is described
using Endpoint descriptor structure.
USB
DEVICE DESCRIPTOR
STRUCTURE
USB Configuration Descriptor Format
USB Interface Descriptor
USB
ENDPOINT
DESCRIPTOR
FORMAT
USB Frames and Microframes
➔ USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF)
packet each and every 1ms period.
➔ USB also defines a high-speed microframe with a 125 μs frame time
➔ SOF packets are generated (by the host controller) every 1ms for full-speed
links.
Image source: USB

2.0 Specifications
Summary
➔ USB is a 4 wire bus that supports communication between a host and a number of
(127 max) peripherals.
➔ The host controller allocates the USB bandwidth to the attached device through a
token based protocol.
➔ Bus supports hot plugging, un-plugging and dynamic configuration of the device.
➔ All transactions are initiated by the host.
➔ Each device can have maximum of 16 logical and 32 physical endpoints.
Summary
4 types of transfer are defined for the endpoints: control, interrupt, isochronous and bulk.
➔ Control transfers are used to configure the device.

➔ Interrupt transfers are used for periodic data transfer.
➔ Bulk transfer is used when rate of transfer is not critical but it has to be error free.
➔ Isochronous transfers have guaranteed delivery but no error check or correction.
USB is a host controlled protocol. Irrespective of whether the data transfer is from device
to host or host to device, transfer sequence is always initiated by the host.
During data transfer from device to the host, the host sends an IN token to the device,
following which the device responds with the data.
USB device peripheral in LPC2148
• Fully compliant with USB 2.0 Full Speed specification
• Supports 32 physical (16 logical) endpoints
• Supports Control, Bulk, Interrupt and Isochronous endpoints
• Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time
• RAM message buffer size based on endpoint realization and maximum packet size
• Supports Soft Connect feature and Good Link LED indicator
• Supports bus-powered capability with low suspend current
• Support DMA transfer with the DMA RAM of 8 kB on all non-control endpoints (LPC2146/8 only)
• One Duplex DMA channel serves all endpoints
• Allows dynamic switching between CPU controlled and DMA modes
• Double buffer implementation for Bulk & Isochronous endpoints
LPC2148: USB Device Controller
➔ The device controller enables 12 Mb/s data exchange with a USB host controller.
➔ It consists of register interface, serial interface engine, endpoint buffer memory and
DMA controller.
➔ The serial interface engine decodes the USB data stream and writes data to the
appropriate endpoint buffer memory.
➔ The status of a completed USB transfer or error condition is indicated via status
registers. An interrupt is also generated if enabled.
➔ The DMA controller when enabled transfers data between the endpoint buffer and the
USB RAM.
Pre-fixed Endpoint Configuration
Pre-fixed Endpoint Configuration
USB Peripheral Device Block
Data flow from Host to Device
➔ The USB device protocol engine receives the serial data from the USB analog
transceiver and converts it into a parallel data stream.
➔ The parallel data is sent to the RAM interface which in turn transfers the data to the
endpoint buffer.
➔ The endpoint buffer is implemented as an SRAM based FIFO. Each realized endpoint
will have a reserved space in the RAM.
➔ So the total RAM space required depends on the number of realized endpoints,
maximum packet size of the endpoint and whether the endpoint supports double
buffering.
Data Flow
➔ For non-isochronous endpoints, when a full data packet is received without any
errors, the endpoint generates a request for data transfer from its FIFO by generating
an interrupt to the system.
➔ Isochronous endpoint will have one packet of data to be transferred in every frame. So
the data transfer has to be synchronized to the USB frame rather than packet arrival.
So, for every 1 ms there will be an interrupt to the system.
➔ The data transfer follows the little endian format. The first byte received from the
USB bus will be available in the least significant byte of the receive data register.
Data Flow from Device to Host
➔ For data transfer from an endpoint to the host, the host will send an IN token to that
endpoint. If the FIFO corresponding to the endpoint is empty, the device will return a
NAK and will raise an interrupt to the system.
➔ On this interrupt the CPU fills a packet of data in the endpoint FIFO. The next IN
token that comes after filling this packet will transfer this packet to the host.
➔ The data transfer follows the little endian format. The first byte sent on the USB bus
will be the least significant byte of the transmit data register.
Software Interface
Software interface of the USB device block consists of a register view and the format
definitions for the endpoint descriptors.
A few important registers
USB Endpoint Interrupt Status register (USBEpIntSt - 0xE009 0030)
Each physical non-isochronous endpoint is represented by one bit in this register to
indicate that it has generated the interrupt.
USB Endpoint Interrupt Status register (USBEpIntSt - 0xE009 0030)
➔ All non-isochronous OUT endpoints give an interrupt when they receive a packet
without any error.
➔ All non-isochronous IN endpoints will give an interrupt when a packet is successfully
transmitted or a NAK handshake is sent on the bus provided that the interrupt on
NAK feature is enabled.
➔ Isochronous endpoint transfer takes place with respect to frame interrupt. The
USBEpIntSt is a read only register.
➔ All these interrupts can be enabled or disabled using USBEpIntEn and USBEpIntClr
registers respectively
USB Realize Endpoint register (USBReEp - 0xE009 0044)
➔ Though fixed-endpoint configuration implements 32 endpoints, it is not a must that all
have to be used. If the endpoint has to be used, it should have buffer space in the
EP_RAM.
➔ The EP_RAM space can be optimized by realizing a subset of endpoints.
➔ This is done through programming the Realize Endpoint register. Each physical
endpoint has one bit as shown below. The USBReEp is a read/write register
Virtual COM Port Device (Vendor Specific)
Virtual COM port driver allows your PC to recognize and communicate with the remote
target as a COM port regardless the under-layer hardware connection between the PC and
target system.
For example, if the LPC2148 is programmed as a COM port device, actual connection is
through USB but it will appear to the PC as a COM port. When the USB cable is
connected, the target looks like a real serial port communicating with the PC Hyper
Terminal Software on the Windows platform.
Also called USB to serial converter. (Remember CH340, CP2102 ?)

USB Operation on the device side
The operation of the USB device driver can be simply defined in three phases:
1. Reset,
2. Enumeration, and
3. Operation phase.
USB reset phase
➔ The USB device will be in the reset phase after power-on reset.
➔ When the USB device is attached to the PC USB host, the host will issue a reset
signal.
➔ When a USB reset signal is detected on the bus, on the device side, the DEV_STAT
bit in the Device Interrupt Register is set and a USB interrupt will be generated.
➔ The USB device will process the RESET interrupt and set itself to the default
configuration state. The initial address of the USB device is set to zero at reset phase.
➔ After the reset signal is released and RESET interrupt has been processed, the device
will enter the enumeration phase.
USB enumeration and standard requests
➔ During the enumeration phase, the host performs a bus enumeration to identify the
attached devices by sending a series of requests on the control pipe (endpoint 0 OUT)
using standard device request to get the device information and configuration, and
then, assign a unique address to it.
➔ Based on the information it gets, if necessary, send SET_FEATURE,
SET_CONFIGURATION, and/or SET_INTERFACE requests to reconfigure the
device.
➔ The device responds to the host requests on its default control pipe (endpoint 0 IN).
Endpoint configuration for virtual COM port
In the virtual COM port device driver implementation, more than one interface descriptors
can be created to accommodate multiple virtual COM ports.
Under each interface descriptor, vendor specific class code (0xFF) has been chosen.
Endpoint configuration for virtual COM port
Interface number EP Number (Physical Description
Endpoint, type)
0 EP1 IN (3, Interrupt) Report modem status of the device

in UART0 or virtual COM port 0
0 EP2 OUT (4, Bulk) Data transfer from host to the

device on UART0 or virtual COM
port 0
0 EP2 IN (5, Bulk) Data transfer from device to the

host on UART0 or virtual COM port
0
1 EP4 IN (9, Interrupt) Report modem status of the device

in UART1 or virtual COM port 1
1 EP5 OUT (10, Bulk) Data transfer from host to the

device on UART1 or virtual COM
port 1
1 EP5 IN (11, Bulk) Data transfer from device to the

host on UART1 or virtual COM port
1
Virtual COM Port protocol
In order to establish the COM port communication, after the USB Reset phase and entering
the enumeration phase, the USB host is responsible for sending the COM port information
such as COM port baud rate, data bits, stop bits, hardware handshaking to the USB device.
To do so, USB host uses the vendor specific request to set up the virtual COM port on the
USB device.
Virtual COM Port Setup
Based on the vendor specific request from the host, the USB device will configure the
on-chip COM port accordingly. Once the configuration is accomplished, the data from the
USB host can be transmitted or received to/from the on-chip COM port seamlessly via the
virtual COM port.
SETUP PACKET
The first byte of the setup packet represents “Request Type”. The Request Type identifies
the characteristics of the request shown as follows:
In the second byte, “Request” field specifies the particular request for configuring the
UART device followed with a value shown as follows:
UART Channel Selection
Bit 7, 6, and 5 of the “Request” is used to represent the channel number of UART as
shown on the following table.
Vendor Specific Device Request Example
As seen in the second column of above table, 0x41 indicates the direction of the setup
request is from host to device (bit 7 is 0), the type is “vendor” (bit 6 and 5 is 10b), and the
recipient is “interface” (bit 4 through 0 is 00001b). Finally, the SETUP request is to set the
baud rate of the COM port 0 at 9600.
The index and length fields in the vendor specific interface request table are defined but not
used. They are reserved for future expansion.
Initialization
➔ After the power up, the USB initialization should include below steps:
➔ Turn on USB PCLK
➔ Configure 48Mhz PLL1 for USB clock
➔ Setup Vectored Interrupt Controller (VIC) for USB
➔ Set up minimum numbers of USB registers including index and packet size register
for Control OUT (0) and Control IN (1) endpoints.
➔ Set USB Device Interrupt Enable register
➔ Use protocol engine commands SET_ADDRESS to reset device address to zero, and
SET_DEVICE_STATUS to make a soft connection
LPC2148 USB Command Code register (USBCmdCode - 0xE009 0010)
➔ This register is used for writing the commands.

➔ The commands written here will get propagated to the Protocol Engine and will be
executed there.
➔ After executing the command, the register will be empty, and the “CCEMTY” bit of
the Interrupt Status register is set high.
LPC2148 USB Command Data register (USBCmdData - 0xE009 0014)
➔ This is a read-only register which will carry the data retrieved after executing a
command.
➔ When this register is ready, the “CD_FULL” bit of the Device Interrupt Status register
is set. The CPU can poll this bit or enable an interrupt corresponding to this to sense
the arrival of the data.The data is always one-byte wide
LPC2148 Protocol Engine Commands
➔ The protocol engine operates based on the commands issued from the CPU.
➔ These commands have to be written into the Command Code register
➔ The read data when present will be available in the Command Data register after the
successful execution of the command.
When the CPU has written data into an IN buffer, it should set the buffer full flag by
the Validate Buffer command. This indicates that the data in the buffer is valid and
can be sent to the host when the next IN token is received
Set Address (Command: 0xD0, Data: write 1 byte)
➔ The Set Address command is used to set the USB assigned address and enable the
(embedded) function.
➔ The address set in the device will take effect after the status phase of the setup token.
(Alternately, issuing the Set Address command twice will set the address in the
device).
➔ At power on reset, the DEV_EN is set to 0. After bus reset, the address is reset to
0x00. The enable bit is set to 1. The device will respond on packets for function
address 0x00, endpoint 0 (default endpoint).
Configure Device (Command: 0xD8, Data: write 1 byte)
A value of 1 written to the register indicates that the device is configured and all the
enabled non-control endpoints will respond. Control endpoints are always enabled and
respond even if the device is not configured, in the default state.
Refer to section 14.9 in UM10139 document for all the different command codes and their purposes.
LPC2148 USB LAB Demo :Class Specific Drivers
➔ To implement a CDC (Communication Device Class) with subclass 0x02
device.
➔ Windows has inbuilt USB Serial driver called USBSer.sys.
➔ USBSer.sys enumerates with the attached device as per the USB CDC
subclass 2 protocol.
➔ Our device must be programmed to respond to those requests.
So, for class specific device drivers, our device must respond to both standard requests and
class specific requests. It must provide class specific descriptors when asked to and
respond to class specific request coming via setup packet.
USB CDC Class
The Communication Device Class (CDC) supports a wide range
of devices that can perform telecommunications and networking
functions. Examples for communications equipment are:
● Telecommunications devices, such as analog phones and
modems, ISDN terminal adapters, digital phones, as well as
COM-port devices
● Networking devices, such as ADSL and cable modems, as well
as Ethernet adapters and hubs
CDC Subclasses
Class Specific Descriptors
Class-Specific Device Descriptor
This descriptor contains information applying to the entire communication device. The
Communication Device Class does not currently use any class-specific descriptor
information at the Device level.
Class-Specific Configuration Descriptor

The Communication Device Class currently does not use any class-specific descriptor
information at the Configuration level
Functional Descriptors
Functional descriptors describe the content of the class-specific information within an
Interface descriptor. Functional descriptors all start with a common header descriptor,
which allows host software to easily parse the contents of class specific descriptors. Each
class-specific descriptor consists of one or more functional descriptors.
Functional Descriptors Contd.
ACM Functional Descriptor : bmCapabilities
Class Specific Requests
REF: USB CDC SPECIFICATION

VCOM Init function
Descriptors in Demo Code
Human Interface Devices
Class
USB - HID Class
➔ All data exchanged resides in structures called reports.
➔ The host sends and receives data by sending and requesting reports in control or
interrupt transfers. The report format is flexible and can handle just about any type of
data.
➔ A HID must have an interrupt IN endpoint for sending Input reports.
➔ A HID can have at most one interrupt IN endpoint and one interrupt OUT endpoint. A
device that requires more interrupt endpoints can be a composite device with multiple
HID interfaces. An application obtains separate handles for each HID in the device
➔ The interrupt IN endpoint enables the HID to send information to the host at
unpredictable times. For example, there’s no way for the host computer to
know when a user will press a key on the keyboard, so the host’s driver uses
interrupt transactions to poll the device periodically to obtain new data.
HID Class Descriptor
HID Report Descriptor 1/3
A report descriptor is a class-specific descriptor. The host
retrieves the descriptor by sending a Get Descriptor request
to the interface with the wValue field containing 22h in the
high byte.
The Usage Page item (06h) specifies the general function of

the device, such as generic desktop control, game control,
or alphanumeric display. In the example,descriptor, the
Usage Page is the vendor-defined value FFA0h.
The Usage item (09h) specifies the function of an individual

report in a Usage Page. For example, Usages available for
generic desktop controls include mouse, joystick, and
keyboard.
● The Collection (Application) item (A1h) begins a group of
items that together perform a single function, such as
keyboard or mouse. Each report descriptor must have an
application collection
● The Collection contains three reports. Each report has

these items: A vendor-defined Usage applies to the data
in the report. A Logical Minimum and Logical Maximum
specify the range of values that the report can contain.
● The Report Size item indicates how many bits are in each
reported data item. In the example, each data item is eight
bits. The Report Count item indicates how many data
items the report contains. In the example, each report
contains two data items
● In the final item, the first byte specifies whether the report
is an Input report (81h), Output report (91h), or Feature
report (B1h). The second byte contains additional
information about the report data, such as whether the
values are relative or absolute.
An End Collection item (C0h) closes the Application Collection.

The main item type
A Main item defines or groups data items within a report descriptor.
Table below shows supported values for Input, Output, and Feature items. Each
item has a 1-byte prefix followed by 1 or 2 bytes that describe the report data.
Similar tables
are there for
output and
feature report
data.
Data | Constant. Data means that the contents of the item are modifiable (read/write).
Constant means the contents are not modifiable (read-only).
Array | Variable. This bit specifies whether the data reports the state of every control
(Variable) or just reports the states of controls that are asserted, or active (Array).
Reporting only the asserted controls results in a more compact report for devices such as
keyboards that have many controls (keys) but where only one or a few controls are
asserted at the same time.
Absolute | Relative. Absolute means that the value is based on a fixed origin. Relative
means that the data indicates the change from the last reading. A joystick normally reports
absolute data (the joystick’s current position), while a mouse reports relative data (how far
the mouse has moved since the last report).
Example from USB Lab
HID Specific Requests
That’s all !
Motion, Mechanisms &
Interfacing Motion Related Devices
➔ Linear
➔ Rotational
Linear motion can be generated using rotational motion using arrangement of gears.
Solenoid based magnetic devices can also be used to generate short range linear motion.
Linear Motor
Kind of Motors usually found in electronic systems
DC Motors
Useful when continuous rotation at high torque, high RPM is required.
Stepper Motors
Useful for applications where precise angular motion is required in equal size steps.
Comes in variety of torque and step angles.
Servo Motors
Feedback based motor control, used to design highly accurate movements.
DC Motor Interfacing
➔ Works on DC voltages with RPM proportional to applied voltage.
➔ Direction can be controlled by changing the polarity of applied voltage.
➔ Require high current to drive and act as inductive load.
DC Motor Interfacing
➔ Microcontroller pins can not supply current required to drive different variety of DC
motors. Depending on the RPM and torque of the motor it may require current of up
to 10s of Amps to drive.
➔ Special motor driver circuits are required to drive these motors.
➔ Driver can control direction and speed of the motor.
➔ How to design motor drivers?
Direction Control
Speed control using PWM
Stepper Motor
Translates electrical pulses into mechanical movement. Provides precise motion control
but no awareness of shaft position. Open loop control. You can control how many step you
want to rotate but you can not control the absolute angle of the shaft from where the
rotation will begin.
Servo Motor
➔ DC motor with shaft position feedback.
➔ Closed loop control.
Typical Servo control PWM pulse
Touch Panels
● Single touch (resistive) or multitouch (capacitive)
● Resistive touch screen are easy to interface. Can be driven using 2 or more
ADC channels.
● Capacitive touch panels are more complex to interface and often required
specialized driver ICs for integration into the system.
Proximity Touch Buttons

Numeric Keypad
Alphanumeric LCD Interfacing
Design Example - 1
Currency Note Acceptor +
Validator for vending machines
Design Example - 1
Design Breakdown
● Mechanical System Control

● Validation Algorithm
● Validation Hardware (Sensor + Computing)
● Communication
● Mechanical Enclosure Design
Design Example - 1
➔ Mechanical System Control
◆ To pull the notes into the detector
◆ Rotatory mechanism with friction wheels
◆ Pull out unacceptable / non validated notes.
◆ Store the notes into cash box.
Design Example - 1
Design Breakdown
How to identify the bank note?
How to ensure future compatibility?

Design Example - 1
Design Breakdown

Length, Width, Color?
What else?
How to ensure future compatibility?

Support end user Programmability!!!
Design Example - 1
Design Breakdown

Length, Width, Color?
What else?
Optical Profile !!!

Each currency note has security points on
it. Some are UV visible, IR visible or visible
to a certain frequency of light ray.
Design Example - 1
Design Breakdown

➔ How to obtain the optical profile?
➔ Put a pair of UV. IR, Visible light

sensors on top and bottom of acceptor
opening.
➔ Light Emitter on top and photosensitive

receiver on bottom.
Design Example - 1
Design Breakdown

User can do the optical profiling for a new type of
note and store it in the device memory as a
template. A user software interface is required
for that. And must be done a few times for
accuracy.
User will define the denomination in the software

and that value will be assigned to that optical
profile.
Now every time a currency note is inserted,

denomination with exact match to stored profile
will be communicated to the rest of the system.
Design Example - 1
Design Breakdown
● Communication
Device need to communicate to the host computer for programming

and configuration. PC supported protocols like Ethernet, USB, Wifi ,
Bluetooth should be used for that.
It also need to send the denomination value or rejection or notes to

the host microcontroller or embedded computer internal to the
machine. Board to board or IC to IC communication protocols should
be used for that. Example, RS232, SPI, IRDA, I2C etc.
Design Example - 2
SaReGaMa Carvaan like Music
Players
Design Example - 2 Customized MP3 players
Design Breakdown
● Human Interface Mechanisms

● Music Selection
● Tone Control and Audio Drive
Human Interface Mechanisms
● LCD display
● User Buttons
● Dial Wheel
● Remote Control IR
● Bluetooth App control
● LCD display - GPIO / I2C / SPI

● User Buttons - GPIO / EXINT
● Dial Wheel - Rotary Encoder / EXTINT
● Remote Control IR - EXTINT / TIMER
● Bluetooth App control - Bluetooth Audio Receiver
● Dial Wheel - Rotary Encoder / EXTINT

● Remote Control IR - EXTINT / TIMER

● Variety of standard IR remote protocols are there.
● RC5, NEC etc. (https://www.vishay.com/docs/80071/dataform.pdf)
● They rely on accurate timing measurement to
detect a particular input.
Design Breakdown
● Music Selection
There are MP3 playback ICs

that supports song seek via
title, folder etc.
Can also perform tone control,

EQ, Bass, Volume etc.
Design Breakdown
● Music Selection
Example - JQ6500
WTV020-SD etc.
Can store mp3 files into SD card /

flash and seek files via folder
names. Can provide play time,
number of files etc.
Design Breakdown
Example - JQ6500
SPK+ SPK- Can

provide direct drive
to small speakers.
For larger speakers

ADCL ADCR along
with external
amplifier is needed
Example - JQ6500
More design thinking projects?
Look around you!

Thank you!
Wish you all the best

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EEEZG512

BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus

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