Assignment1 MELZG632 2019HT80542 PDF

Analog IC Design Assignment I
Name : MOHAMMAD RAHAMTULLA
BITS ID : 2019HT80542
Course : Analog IC Design (MEL- ZG632)
Note:
I have used 180nm node for simulator and LT Spice IV tool.
Title:
Extract the model parameters of NMOS and PMOS devices and find the analog FOM
(intrinsic gain and frequency). Use minimum device dimensions.
1. Use 0.18um/180nm technology

2. Use minimum dimension
Circuit Diagram
NMOS :
1
PMOS:
Design:
Ultimate bandwidth of single stage MOSFET amplifier is determined by speed

limitations of the transistor itself. In simple terms, this means that it takes certain time
for charge carriers to move from source to drain and device cannot work faster than
that. Of course it is only qualitative statement and a lot of details are needed to be able
to predict the frequency response of the particular transistor. Often the unity-gain
frequency (fT) is introduced. This is the frequency at which short-circuit current gain
of the common-source configuration becomes unity. The value of unity-gain
frequency can be estimated in the framework of the simplistic lumped capacitor
model:
f= gm
2(Cgs + Cgd) 
where gm is gate transconductance and CGS and CGD are net equivalent MOSFET
capacitances. The MOSFET capacitances have both internal and external
contributions. Of course, much more detailed modeling is required to predict the
unity-gain bandwidth accurately but the equation (1) is OK as an estimate in many
cases. The bandwidth (BW) of MOSFET amplifiers rarely can approach fT due to
additional limitations caused by particular circuit layout. Usually, BW << fT. Figure
below (taken from recommended book) shows the generic form of the CS amplifier
with resistive load
2
NMOS:
Do DC sweep of Vds and plot Id Vs Vds for different values of Vgs
For this, W/L = 2.33 Vds = 0 to 1.8 V Vgs = 1, 1.1, 1.2, 1.3, 1.4 and 1.5 V
 W = 420nm
 L = 180nm
 Vgs = 0.7v
 Vds = 0.9V,
3
 μn = 327
 tox = 41*10^-8 cm
 Vth = 0.5V (From simulation)
 λ = 0.25 (From simulation)
Hand Calculations:
Id = 1/2 unCox (W/L) (Vgs - VTh)2 [ 1 + λ Vds]
= 1/2 × 327 × 8.854 × 10-14 × 3.9 × (420/180) (0.7-0.5)2 (1+0.25×0.9)

41 × 10-8
= 1.57 × 10-5 A
gm = 2Id/Vov
= 2 × 1.57 × 10-5
(0.7-0.5)
= 1.57×10-4
Value of gm and Id through simulators:
Id = 1.54 × 10-5
gm = 1.57 × 10-4
Now for intrinsic gain and frequency calculation
ro = 1/gds = 1/(3.9 × 10-6)
= 256.41 kΩ
Av = gm ro = 1.57 × 10-4 × 256.41 × 103
= 40.132
4
Intrinsic frequency:
f= gm
2(Cgs + Cgd) 
= 1.57 × 10-4
2 × 3.14 (3.23 × 10-16 + 3.23 × 10-16 )
= 3.868 x 1010
= 38.68 GHz
PMOS:
5
 W = 420nm,
 L = 180nm
 Vgs = -0.7v,
 Vds = - 0.9V,
 μp = 128
 tox = 41*10^-8 cm
 Vth = -0.4V (From simulation)
 λ = 0.19 (From simulation)
Hand Calculations for PMOS
Id = - 1/2 upCox (W/L) (Vgs - VTh)2 [ 1 + λ Vds]
= - 1/2 × 128 × 8.854 × 10-14 × 3.9 × (420/180) (0.7-0.4)2 (1+0.19×0.9)

41 × 10-8
= - 13.25×10-6 A
gm = 2Id/Vov
= 2 × 13.25 × 10-5
(0.7-0.4)
= 8.833×10-5
Value of gm and Id through simulators:
gm = 8.833 × 10-5
Now for intrinsic gain and frequency calculation
ro = 1/gds = 1/(2.72 × 10-6)
= 367.64 kΩ
Av = gm ro = 8.833 × 10-5 × 367.64 × 103
6
= 32.47
Intrinsic frequency:
f= gm
2(Cgs + Cgd) 
= 8.833 × 10-5 / 2 × 3.14 (1.27 × 10-16 + 1.27 × 10-16 )
= 5.537 x 1010
= 55.37 GHz
Results and Observations:
NMOS:
Simulator results :
7
Data Simulator Hand

Calculation
Id 15.4 uA 15.7 uA
gm 1.57 x 10 -4 1.57 x 10 -4
Figure of Merit:
 Intrsinc Gain Av = 32.47

 Instrinsic frequency = 55.37 GHz
PMOS:
8
Data Simulator Hand

Calculation
Id 13.2 uA 10.2 uA
gm 8.833×10-5 7.47 ×10-5
Figure of Merit:
 Intrsinc Gain Av = 32.47

 Instrinsic frequency = 55.37 GHz
Observations:
1. There is a substantial difference between hand calculation (expected) and

simulated results.
2. Value of Cox is also different, we consider 3.9 as a relative permittivity of Silicon

Dioxide but this is a Static dielectric constant value which is subject to change in the
simulation.
Conclusion:
1. For same size and overdrive, NMOS can drive much higher current than PMOS as
mobility of electrons is greater than mobility of holes.
2. Since hand calculation uses square law formulae and simulation uses advanced
model files, therefore hand calculations will never meet simulation results. We might
need to explore other methods like gm over ID techniques.
9
Question 2:
Title:
Design a resistive load common source amplifier, which shall give the maximum
voltage gain with minimum device dimension.
Use 0.18um/180nm technology
Use minimum dimension
Therefore, W/L = 180/420 = 2.33 and Vdd = 1.8 V 3. It should have maximum gain
Circuit Diagram:
10
Design:
GATE DRAIN REGION FIRST ORDER BEHAVIOR
VDS > VGS - VTH SATURATI DRAIN "LOOKS LIKE" CURRENT

ON SOURCE;
ID DEPENDS ONLY ON VGS - VTH
D-S CHANNEL "LOOKS" RESISTIVE
ID = VDS / Ron Ron DEPENDS ON VGS - VTH
VGS > VDS < VGS - VTH TRIODE SWITCH "OFF" ID = 0
VTH
VGS < |VDS| < Vbkd CUTOFF

VTH
Maximum gain of a CS amplifier is = 2 (Vdd - Vov)/Vov
Vdd = 1.8V, Vth = 0.5V, Vgs =0.7V,
W = 360nm, L =180nm
μn = 327.37, tox = 41*10^-8 cm, Cox = 0.86uF
11
Theoretical Max Gain = 2(1.8-0.2)/(0.2)
= 16
Id = 1/2 unCox (W/L) (Vgs - VTh)2
= 0.5 × 327.37 × 0.86 × 10-6 × (360/180) × (0.7-0.5)2

=
11.2սA
gm = 2Id/Vov
=2 × 11.2 × 10-6 /0.2
= 1.12 × 10-4
Av = gm Rd
Rd = Av/gm
= 142.85kΩ
Results and Observation:
Through Simulations:
12
gm = 1.17 × 10-4
Av = gm Rd = 16.71
R0 = 1/Gds
= 1/(5.66 × 10-6) = 176kΩ
Req = Ro || Rd
= 78.59kΩ
13
Conclusion:
The CS amplifiers has infinite input impedance (draws no current at DC), and a
moderately high output resistance (easier to match for maximum power transfer), and
a high voltage gain (a desirable feature of an amplifier).
1. Reducing RD reduces the output resistance of a CS amplifier, but unfortunately,

the voltage gain is also reduced. .
2. A CS amplifier suffers from poor high frequency performance, as most transistor
amplifiers do.
14
Question 3:
Title:
Design a common gate amplifier with an active load (i.e., current mirror) for a voltage
gain of 25 V/V and input impedance should be 50 Ω.
Circuit:
Design:
Given Av = 50, Rin = 50
Ignoring rds1 and rds2
Rin = 2/gm
Therefore gm = 2/Rin
= 2/50 = 40mA/V
15
Id = gmVov/2
= 40/2(0.6-04)
Id1 = Id2 = Id3 = Id4 = 4mA
Id = kn/2 (W/L) (Vgs - Vth)2
4 × 10-3 = 350/2 × (0.865 × 10-6) × (W/L) × 0.04
Therefore W/L = 660.61
Considering L = 0.2um
(W/L)1 = (W/L)2 = (W/L)3 = 132u/20
Vbias = Vgs + IdRs = 0.6 + (4 × 10-3 × 50) = 0.8V
Results and observation
Through Simulation:
rds1 = rds2 = 1/Gds
= 1/(5.12×10 ) = 1.953kΩ
-4
gm = 3.07 × 10-2
Av = 1+ gm (rds1 || rds2)
= 30.98
Rin = (rds1 + rds2)/(1+gm*rds1) = 72Ω
16
Conclusion:
1. The CG amplifier has a low input resistance 1/gm. This is undesirable as it will
draw large current when driven by a voltage input.
2. The voltage gain of the CG amplifier can be made similar in magnitude to that of
the CS amplifier if RD||RL can be made large compared to Rsig + 1/gm.
3 The output resistance can be made large since Ro = RD. 4. The CG amplifier has
good high frequency performance
4 Output is in-phase with input
5 Body effect of NMOS (driving MOSFET) increases gain and decreases Rin.
17
Library file used for Simulation:
* PSPICE TSMC180nm.lib file RWN 04/18/2010
* library file for transistor parameters for TMSC 0.18 micron process
* uses BIM parameters added 01/15/98
* can configure and attach to Nbreak and Pbreak transistors in PSpice
****
****************** 180nm TSMC parameters *************
*T14B SPICE BSIM3 VERSION 3.1 PARAMETERS
* downloaded from MOSIS 04/18/10
*http://www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/
* tsmc-018/t92y_mm_non_epi_thk_mtl_params.txt
*SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8
* DATE: Jun 8/01
* LOT: T14B WAF: 06
* Temperature_parameters=Default
*$
.MODEL TSMC180nmN NMOS ( LEVEL =7
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.354505
+K1 = 0.5733393 K2 = 3.177172E-3 K3 = 27.3563303
+K3B = -10 W0 = 2.341477E-5 NLX = 1.906617E-7
+DVT0W =0 DVT1W =0 DVT2W =0
+DVT0 = 1.6751718 DVT1 = 0.4282625 DVT2 = 0.036004
+U0 = 327.3736992 UA = -4.52726E-11 UB = 4.46532E-19
+UC = -4.74051E-11 VSAT = 8.785346E4 A0 = 1.6897405
18
+AGS = 0.2908676 B0 = -8.224961E-9 B1 = -1E-7
+KETA = 0.021238 A1 = 8.00349E-4 A2 =1
+RDSW = 105 PRWG = 0.5 PRWB = -0.2
+WR =1 WINT =0 LINT = 1.351737E-8
*+XL = -2E-8 XW = -1E-8
+ DWG = 1.610448E-9
+DWB = -5.108595E-9 VOFF = -0.0652968 NFACTOR = 2.4901845
+CIT =0 CDSC = 2.4E-4 CDSCD =0
+CDSCB =0 ETA0 = 0.0231564 ETAB = -0.058499
+DSUB = 0.9467118 PCLM = 0.8512348 PDIBLC1 = 0.0929526
+PDIBLC2 = 0.01 PDIBLCB = -0.1 DROUT = 0.5224026
+PSCBE1 = 7.979323E10 PSCBE2 = 1.522921E-9 PVAG = 0.01
+DELTA = 0.01 RSH = 6.8 MOBMOD = 1
+PRT =0 UTE = -1.5 KT1 = -0.11
+KT1L =0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL =0 WLN =1 WW =0
+WWN =1 WWL =0 LL =0
+LLN =1 LW =0 LWN =1
+LWL =0 CAPMOD = 2 XPART = 0.5
+CGDO = 7.7E-10 CGSO = 7.7E-10 CGBO = 1E-12
+CJ = 1.010083E-3 PB = 0.7344298 MJ = 0.3565066
+CJSW = 2.441707E-10 PBSW = 0.8005503 MJSW = 0.1327842
+CJSWG = 3.3E-10 PBSWG = 0.8005503 MJSWG = 0.1327842
+CF =0 PVTH0 = 1.307195E-3 PRDSW = -5
19
+PK2 = -1.022757E-3 WKETA = -4.466285E-4 LKETA = -9.715157E-3
+PU0 = 12.2704847 PUA = 4.421816E-11 PUB =0
+PVSAT = 1.707461E3 PETA0 = 1E-4 PKETA = 2.348777E-3 )
*$
.MODEL TSMC180nmP PMOS ( LEVEL =7
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.4120614
+K1 = 0.5590154 K2 = 0.0353896 K3 =0
+K3B = 7.3774572 W0 = 1E-6 NLX = 1.103367E-7
+DVT0W =0 DVT1W =0 DVT2W =0
+DVT0 = 0.4301522 DVT1 = 0.2156888 DVT2 = 0.1
+U0 = 128.7704538 UA = 1.908676E-9 UB = 1.686179E-21
+UC = -9.31329E-11 VSAT = 1.658944E5 A0 = 1.6076505
+AGS = 0.3740519 B0 = 1.711294E-6 B1 = 4.946873E-6
+KETA = 0.0210951 A1 = 0.0244939 A2 =1
+RDSW = 127.0442882 PRWG = 0.5 PRWB = -0.5
+WR =1 WINT = 5.428484E-10 LINT = 2.468805E-8
*+XL = -2E-8 XW = -1E-8
+DWG = -2.453074E-8
+DWB = 6.408778E-9 VOFF = -0.0974174 NFACTOR = 1.9740447
+CIT =0 CDSC = 2.4E-4 CDSCD =0
+CDSCB =0 ETA0 = 0.1847491 ETAB = -0.2531172
+DSUB = 1.5 PCLM = 4.8842961 PDIBLC1 = 0.0156227
+PDIBLC2 = 0.1 PDIBLCB = -1E-3 DROUT =0
20
+PSCBE1 = 1.733878E9 PSCBE2 = 5.002842E-10 PVAG = 15
+DELTA = 0.01 RSH = 7.7 MOBMOD = 1
+PRT =0 UTE = -1.5 KT1 = -0.11
+KT1L =0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL =0 WLN =1 WW =0
+WWN =1 WWL =0 LL =0
+LLN =1 LW =0 LWN =1
+LWL =0 CAPMOD = 2 XPART = 0.5
+CGDO = 7.11E-10 CGSO = 7.11E-10 CGBO = 1E-12
+CJ = 1.179334E-3 PB = 0.8545261 MJ = 0.4117753
+CJSW = 2.215877E-10 PBSW = 0.6162997 MJSW = 0.2678074
+CJSWG = 4.22E-10 PBSWG = 0.6162997 MJSWG = 0.2678074
+CF =0 PVTH0 = 2.283319E-3 PRDSW = 5.6431992
+PK2 = 2.813503E-3 WKETA = 2.438158E-3 LKETA = -0.0116078
+PU0 = -2.2514581 PUA = -7.62392E-11 PUB = 4.502298E-24
+PVSAT = -50 PETA0 = 1E-4 PKETA = -1.047892E-4 )
.ENDS
*$
21

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Analog IC Design Assignment I

Name : MOHAMMAD RAHAMTULLA

Course : Analog IC Design (MEL- ZG632)

I have used 180nm node for simulator and LT Spice IV tool.

1. Use 0.18um/180nm technology

Ultimate bandwidth of single stage MOSFET amplifier is determined by speed

Do DC sweep of Vds and plot Id Vs Vds for different values of Vgs

 Vth = 0.5V (From simulation)

 λ = 0.25 (From simulation)

Id = 1/2 unCox (W/L) (Vgs - VTh)2 [ 1 + λ Vds]

= 1/2 × 327 × 8.854 × 10-14 × 3.9 × (420/180) (0.7-0.5)2 (1+0.25×0.9)

Value of gm and Id through simulators:

Now for intrinsic gain and frequency calculation

ro = 1/gds = 1/(3.9 × 10-6)

Av = gm ro = 1.57 × 10-4 × 256.41 × 103

 Vth = -0.4V (From simulation)

 λ = 0.19 (From simulation)

Hand Calculations for PMOS

Id = - 1/2 upCox (W/L) (Vgs - VTh)2 [ 1 + λ Vds]

= - 1/2 × 128 × 8.854 × 10-14 × 3.9 × (420/180) (0.7-0.4)2 (1+0.19×0.9)

Value of gm and Id through simulators:

Now for intrinsic gain and frequency calculation

ro = 1/gds = 1/(2.72 × 10-6)

Av = gm ro = 8.833 × 10-5 × 367.64 × 103

= 8.833 × 10-5 / 2 × 3.14 (1.27 × 10-16 + 1.27 × 10-16 )

Results and Observations:

Data Simulator Hand

 Intrsinc Gain Av = 32.47

Data Simulator Hand

 Intrsinc Gain Av = 32.47

1. There is a substantial difference between hand calculation (expected) and

2. Value of Cox is also different, we consider 3.9 as a relative permittivity of Silicon

Use 0.18um/180nm technology

Use minimum dimension

GATE DRAIN REGION FIRST ORDER BEHAVIOR

VDS > VGS - VTH SATURATI DRAIN "LOOKS LIKE" CURRENT

VGS < |VDS| < Vbkd CUTOFF

Maximum gain of a CS amplifier is = 2 (Vdd - Vov)/Vov

Vdd = 1.8V, Vth = 0.5V, Vgs =0.7V,

μn = 327.37, tox = 41*10^-8 cm, Cox = 0.86uF

Theoretical Max Gain = 2(1.8-0.2)/(0.2)

Id = 1/2 unCox (W/L) (Vgs - VTh)2

= 0.5 × 327.37 × 0.86 × 10-6 × (360/180) × (0.7-0.5)2

=2 × 11.2 × 10-6 /0.2

Results and Observation:

= 1/(5.66 × 10-6) = 176kΩ

1. Reducing RD reduces the output resistance of a CS amplifier, but unfortunately,

Given Av = 50, Rin = 50

Ignoring rds1 and rds2

Id1 = Id2 = Id3 = Id4 = 4mA

Id = kn/2 (W/L) (Vgs - Vth)2

4 × 10-3 = 350/2 × (0.865 × 10-6) × (W/L) × 0.04

Therefore W/L = 660.61

(W/L)1 = (W/L)2 = (W/L)3 = 132u/20

Vbias = Vgs + IdRs = 0.6 + (4 × 10-3 × 50) = 0.8V

Results and observation

rds1 = rds2 = 1/Gds

Rin = (rds1 + rds2)/(1+gm*rds1) = 72Ω

4 Output is in-phase with input

Library file used for Simulation:

* PSPICE TSMC180nm.lib file RWN 04/18/2010

* uses BIM parameters added 01/15/98

****** 180nm TSMC parameters *