Chapter 6

Functional Organization

Parallel Processing
Instead of processing each instruction sequentially as in a conventional computer, a parallel
processing system is able to perform concurrent data processing to achieve faster execution time.

Example: while an instruction is being executed in the ALU, the next instruction can be read from memory.
The system may have two or more ALU’s or processors operating concurrently.

The purpose of parallel processing is to speed up the computer processing capability and increase it’s
throughput, that is, the amount of processing that can be accomplished during a given interval of time.

Multiple Functional units: Parallel processing is established by distributing the data among multiple
functional units.

Example: The arithmetic, logic, and shift operations can be separated into three units and the operands
diverted to each unit under the supervision of a control unit.

All units are independent of each other, so operations can be performed concurrently on different data.

There are a variety of ways that parallel processing can be classified:

1. It can be considered from internal organization of the processors,

2. From the inter connection structure between processors,
3. From the flow of information through the system.

M.J Flynn considers the organization of a computer system by the number of instruction and data items that
are manipulated simultaneously.
Instruction stream: The sequence of instructions read from memory constitutes an instruction stream.
Data Stream: The operations performed on the data in the processor constitute a data stream.

Parallel processing may occur in the instruction stream, in the data stream, or on both.

Flynn’s classification divides computers into four major groups as follows:

1. Single instruction stream, single data stream (SISD)
2. Single instruction stream, multiple data stream (SIMD)
3. Multiple instruction stream, single data stream (MISD)
4. Multiple instruction stream, multiple data stream (MIMD)- Most multiprocessor and multi
computing systems can be classified in this category.

Applications of parallel processing computers:

 Numerical weather forecasting
 Computational aerodynamics
 Finite-sensing applications
 Remote-sensing applications
 Genetic engineering
 Computer-assisted tomography
 Weapon research and defense

Pipelining is a technique of decomposing a sequential process into sub-operations, with each sub-process
being executed in a special dedicated segment that operates concurrently with all other segments.

A pipeline can be visualized as a collection of processing segments through which binary information flows.

Each segment performs partial processing dictated by the way the task is partitioned. The result obtained
from the computation in each segment is transferred to the next segment in the pipeline.

The final result is obtained after the data have passed through all segments. The registers provide isolation
between each segment so that each can operate on distinct data simultaneously.

Example: Suppose that we want to perform the combined multiply and add operations with a stream of
numbers.
Ai * Bi + Ci , for i=1,2,3……7

The sub operations performed in each segment of the pipeline are as follows:

R1←Ai, R2←Bi – segment 1 – in clock pulse 1

R2←R1*R2, R4←Ci – segment 2 – in clock pulse 2
R5←R3+R4 - segment 3 – in clock pulse 3
The five registers are loaded with new data every clock pulse. The first clock pulse transfers A i and Bi into
R1 and R2. The second clock pulse transfers the product of R1 and R2 into R3 and Ci into R4.

The same clock pulse transfers A2 and B2 into R1 and R2. The third clock pulse operates on all three
segments simultaneously.

There are two areas of computer design where the pipeline organization is applicable.

An arithmetic pipeline divides an arithmetic operation into sub operations for execution in the
pipeline segments.

An instruction pipeline operates on a stream of instructions by overlapping the fetch, decode and
execute phases of instruction cycle.

Instruction Pipeline
An instruction pipeline reads consecutive instruction from memory while previous instructions are
being executed in other segments.

Four-segment Instruction Pipeline:

The following flow chart shows how the instruction cycle in the CPU can be processed with a four-
segment pipeline. Four sub operations in the instructions cycle can overlap and up to four different
instructions can be in progress of being processed at the same time.

Instruction Cycle:
Segment (1) Fetch instruction (FI)
Segment (2) Decode Instruction (DI)
Segment (3) Read Operand (RO)
Segment (4) Execute (EX)

Once in a while, an instruction in the sequence may be a program control type that causes a branch out of
normal sequence. In that case the pending operations in the last two segments are completed and all
information stored in the instruction buffer is deleted. The pipeline can restarts from the new address stored
in the program counter.
Similarly, an interrupt request, when acknowledged will cause the pipeline to empty and start again from a
new address value.

The following diagram shows the operation of the instruction pipeline. The time in the horizontal axis is
divided into steps of equal duration.

It is assumed that the processor has separate instruction and data memories so that the operation in FI and
RO can be proceed at the same time.

In the absence of branch instruction, each segment operates on different instruction. Thus, in step 4,
instruction 1 is being executed in segment EX; the operand for instruction 2 is being read in segment RO;
instruction 3 is being decoded is segment DI; and instruction 4 is being fetched from memory in segment FI.

Assume now the instruction 3 is branch instruction. As soon as the instruction is decoded in segment DI in
step 4, the transfer from FI to DI of other instruction is halted until the branch instruction is executed in step
6.

If the branch is taken, a new instruction is fetched in step 7, if the branch is not taken, the instruction fetched
previously in step 4 can be used.

In general, there are three major difficulties that cause the instruction pipeline to deviate from its normal
operation.

1. Resource conflicts: caused by access to memory by the segments at the same time. Most of these
conflicts can be resolved by using separate instruction and data memories.

2. Data dependency: conflicts arise when an instruction depends on the result of a previous
instruction, but this result is not yet available.

3. Branch difficulties: arise from branch and other instructions that change the value of PC.
Microprogrammed Control Unit
The function of the control unit in a digital computer is to initiate sequences of microoperations.
Two methods of implementing control unit are hardwired control and microprogrammed control.

The design of hardwired control involves the use of fixed instructions, fixed logic blocks of arrays,
encoders, decoders etc.

The key characteristics of hardwired control logic are high-speed operation, expensive, relatively complex,
and no flexibility of adding new instructions.

Example: Intel 8085, Motorola 6802, Zilog 80, and any RISC (Reduced Instruction Set Computer)
CPUs.

Microprogramming is a second alternative for designing the control unit of a digital computer. The principle
of microprogramming is an elegant and systematic method for controlling the microoperation sequences in a
digital computer.

Example: Intel 8080, Motorola 68000, and any CISC (Complex Instruction Set Computer) CPUs.

The control function that specifies a microoperation is a binary variable. When it is in one binary state, the
corresponding microoperation is executed, if it is in the opposite binary state, it does not change the state of
the registers in the system.

In a bus-organized system, the control signals that specify microoperations are groups of bits that select the
paths in multiplexers, decoders, and arithmetic logic units.

Control word: The control variables at any given time can be represented by a string of 1’s and 0’s called a
control word. As such, control words can be programmed to perform various operations on the components
of the system.

A control unit whose binary control variables are stored in memory is called a microprogrammed control
unit.

Microinstruction: Each word in control memory contains within it is called microinstruction. The
microinstruction specifies one or more microoperations for the system.

Micro program: A sequence of micro instructions constitutes a micro program.

Control memory: A memory that contains control unit is referred to as a control memory.

Since alterations of the microprogram are not needed once the control unit is in operation, the control
memory can be a read-only memory (ROM).

Control units that use dynamic micro programming employ a writable control memory.

A computer that employs a micro programmed control unit will have two separate memories; a main
memory and a control memory.

The main memory is available to the user for storing the programs. The contents of main memory
may alter when the data are manipulated and every time that the program is changed.

In contrast, the control memory holds a fixed microprogram that cannot be altered by the occasional
user. These microinstructions generate the micro operations to fetch the instruction from main memory; to
evaluate the effective address, to execute the operation specified by the instruction, and to return control to
the fetch phase in order to repeat the cycle for the next instruction.
Microprogrammed Control organization:

The control memory is assumed to be ROM, within which all control information is permanently stored.

The control address register specifies the address of the microinstruction, and the control data registers holds
the micro instruction read from memory.

The micro instruction contains a control word that specifies one or more micro operations for the data
processor.

While the micro operations are being executed, the next address is computed in the next address generator
circuit and then transferred into the control address register to read the next micro instruction.

Thus a microinstruction contains bits for initiating micro operations in the data processor part and
bits that determine the address sequence for the control memory.

Microprogram sequencer: The next address generator is sometimes called a microprogram sequences, as
it determines the address sequences that is read from control memory.

Typical functions of a microprogram sequences are incrementing the control address register by one, loading
into the control address register an address from control memory, transferring external address, or loading an
initial address to start the control operations.

Pipeline register: The control data register is sometimes called a pipeline register. It allows the execution of
the microoperations specified by the control word simultaneously with the generation of the next
microinstruction.

Advantage:
The main advantage of the microprogrammed control is that the hardware configuration should not
be changed for different operations; the only thing that must changed is the microprogram residing in control
memory.