Computer Organization

& Architecture
BITS Pilani Chandan Ranvandur n
Pilani Campus
Input /Output

• I/O system provides interface to the outside

world
• I/O operations are accomplished through wide
variety of external devices
• Used to transfer the data between computer
and external world
• e.g. Keyboard, Monitor, Disk Drive, Printer
• An external device attached to the computer by
an Interface Circuit called as I/O module
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Why I/O Module?
• Wide variety of peripherals
– Impractical to incorporate the necessary logic within
processor
• Delivering different amounts of data
– At different speeds, different formats and word length
• Speed mismatch between processor/memory
and I/O devices
– Some I/O devices are slower than processor and
memory while some are faster than processor and
memory
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Generic Model of I/O Module

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I/O Module Functions-1

• Control & Timing

– To coordinate the flow of traffic between internal
resources and external devices
– Control Signals: Read, Write, Ready, Busy, Error etc.
• Processor and Device Communication
– It must communicate with the processor and the
external device before transferring the data
– Processor communication involves
• Command decoding, Data, Status reporting, Address
recognition
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I/O Module Functions-2

• Data Buffering
– To overcome the speed mismatch between CPU or
memory and device

• Error Detection
– Mechanical, electrical malfunctioning and
transmission
– e.g. paper jam, disk bad sector

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EXTERNAL DEVICES

classify external devices into

three categories
1. Human readable
Eg.keyboard/monitor
2. Machine readable
Eg.Disk Drive
3. Communication

Block Diagram of an External Device

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General I/O Module Structure
• CPU checks I/O module device status
• I/O module returns status
• If ready, CPU requests data transfer
• I/O module gets data from device
• I/O module transfers data to CPU

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I/O Methods

• Programmed
• Interrupt driven
• Direct Memory Access (DMA)

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 Programmed I/O

• CPU has direct control over I/O

– Sensing status
– Read/write commands
– Transferring data
• CPU waits for I/O module to
complete operation
• Commands
• Control - telling module what to do
• Test - check status
• Read/Write
• Wastes CPU time!!! Why?
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Addressing I/O Devices

• Memory mapped I/O

– Devices and memory share an address space
– I/O looks just like memory read/write
– No special commands for I/O
• Large selection of memory access commands available

• Isolated I/O
– Separate address spaces
– Need I/O or memory select lines
– Special commands for I/O
– 210= 1024 lines

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Memory Mapped and Isolated
I/O

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Interrupts

• Interrupts, what the processor is doing

• Program
– e.g. overflow, division by zero, segmentation fault
• Timer
– Generated by internal processor timer
– Used in pre-emptive multi-tasking
• I/O
– from I/O controller
• Hardware failure
– e.g. memory parity error
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Interrupt Driven I/O

• CPU issues read command

• I/O module gets data from
peripheral whilst CPU does other
work
• I/O module interrupts CPU once
data ready
• If interrupted:-
– Save context (registers values)
– Process interrupt
• Fetch data & store

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Simple Interrupt Processing

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Changes in Memory and Registers for an
Interrupt

a. Interrupt occurs after instruction at

location N
b. Return from interrupt
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Device Identification-1
• How does processor determine which device
issued the interrupt?
– Multiple Interrupt Lines
• Impractical to provide one line to each I/O device as
number of devices increase
– Software Poll
• Processor branches to ISR
• ISR poll each I/O module to identify which module
caused the interrupt
• Time consuming process

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Device Identification-2
• Hardware Poll
– All I/O modules share a common interrupt request line
– Interrupt ACK line is Daisy changed through the modules
– Requesting module places address of the I/O module on data
bus which is called as a vector
– Technique is called as vectored Interrupt

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A common interrupt request line

INTR= INTR1 + INTR2 +…………….+ INTRn

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Enabling & Disabling interrupts

 Interrupt request for printing

 Interrupt request line high results in multiple interrupts;
May lead to infinite loop
 Remedy
 Interrupt disable instruction as the 1st instruction in
subroutine
 Processor automatically disables interrupts ; can be
achieved through changing the IE(interrupt enable)
pin in PS (Program status register)

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Sequence of events involved in handling
interrupt

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Simultaneous requests

A multiple Priority Scheme implemented by using individual

interrupt request and acknowledge line

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Simultaneous requests

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Simultaneous requests Example

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Simultaneous requests Example

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Simultaneous requests Example 2

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Simultaneous requests Example 2

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Multiple Interrupts - Sequential
Processor will ignore further interrupts whilst processing one interrupt
Interrupts remain pending and are checked after first interrupt has been
processed

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Multiple Interrupts: Priority
Low priority interrupts can be interrupted by higher priority interrupts
When higher priority interrupt has been processed, processor returns
to previous interrupt

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Use of the 82C59A Interrupt Controller

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Review Questions

• When a device interrupt occurs, how does the

processor determine which device issued the
interrupt?
• What is context switching?
• How programmed I/O is different from
Interrupt Driven I/O?
• How software polling is different from Daisy
chain method to handle multiple interrupts?
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Summary

• I/O modules: Functions and Structure

• I/O methods
– Programmed I/O
• Device addressing methods
– Interrupt Driven I/O
• Interrupt handling and processing
• Device Identification

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 The Cache Coherence Problem

 As multiple processors operate in parallel, and

independently multiple caches may possess different
copies of the same memory block, this creates cache
coherence problem. Cache coherence schemes help to
avoid this problem by maintaining a uniform state for each
cached block of data.
 write-through policy: the same copy will be written
immediately into the shared memory.
 & write-back policy: the main memory will be updated
when the modified data in the cache is replaced or
invalidated.
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 The Cache Coherence Problem

In general, there are three sources of inconsistency problem

•Sharing of writable data
•Process migration
•I/O activity
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 Snoopy Bus Protocols
 Snoopy protocols achieve data consistency between the cache
memory and the shared memory through a bus-based memory
system. 
 Write-invalidate and write-update policies are used for
maintaining cache consistency.  In this case, we have
three processors P1, P2,
and P3 having a
consistent copy of data
element ‘X’ in their local
cache memory and in the
shared memory
 Processor P1 writes X1
in its cache memory
using write-invalidate
protocol. So, all other
copies are invalidated via
the bus
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 Snoopy Bus Protocols

It is denoted by ‘I’ .Invalidated blocks are also known as dirty, i.e. they
should not be used.
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 Snoopy Bus Protocols

The write-update protocol updates all the cache copies via the bus. By

using write back cache, the memory copy is also updated
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 Cache Coherency in Shared Memory Machines

Maintaining cache coherency is a problem in multiprocessor system

when the processors contain local cache memory. Data inconsistency
between different caches easily occurs in this system.
The major concern areas are −
•Sharing of writable data
•Process migration
•I/O activity

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 Sharing of writable data

When two processors (P1 and P2) have same data element (X) in their
local caches and one process (P1) writes to the data element (X), as
the caches are write-through local cache of P1, the main memory is
also updated. Now when P2 tries to read data element (X), it does not
find X because the data element in the cache of P2 has become
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Process migration

In the first stage, cache of P1 has data element X, whereas P2 does not have
anything. A process on P2 first writes on X and then migrates to P1. Now, the
process starts reading data element X, but as the processor P1 has outdated data
the process cannot read it. So, a process on P1 writes to the data element X and
then migrates to P2. After migration, a process on P2 starts reading the data
element X but it finds an outdated version of X in the main memory.
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I/O activity

As illustrated in the figure, an I/O device is added to the bus in a two-processor

multiprocessor architecture. In the beginning, both the caches contain the data
element X. When the I/O device receives a new element X, it stores the new
element directly in the main memory. Now, when either P1 or P2 (assume P1)
tries to read element X it gets an outdated copy. So, P1 writes to element X.
Now, if I/O device tries to transmit X it gets an outdated copy.
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Thank You!

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