Serial communication

Parallel communication requires More lines ,costly, generally used for short distance

Serial communication requires single line, so suitable for long distances, and cheap. Data passes through a parallel to
serial converter at transmitter, and receiver has s/p converter.

With help of modem converts data to signal and transmitted through communication line.

Simplex – data transmission in one direction only= printers

Duplex- data transmission in both direction

– One direction at a time- half duplex

– Simultaneous bidirectional transfer – full duplex

Protocol –rules of data packing and transmission

UART stands for Universal Asynchronous Receiver/Transmitter. The data bits are not synchronized with the clock pulses,
transfers a byte of data at a time

USART stands for Universal Synchronous Asynchronous Receiver/Transmitter. The data bits are synchronized with the clock
pulses, transfers a block of data at a time
 – AVR has built in USART

Framing- arranging data bites between start and stop bits

 Every frame will have at least

 1 start bit
 data bits (5,6,7,8 or 9)
 1-2 stop bit
 Parity is optional

Serial frame format

Data transmission rate

The rate of data transfer is measured in Bits per second or Baud rate. In wired communication these two are the same.In
USART speed is generally limited to 100000b/s

In practice, serial communication with no handshaking uses 3 wires (TX, RX and GND). Serial communications with basic
hardware handshaking uses 5 wires (TX, RX, RTS, CTS and GND).

The USART of the AVR occupies three hardware pins:

1. RxD: USART Receiver Pin (ATMega8 Pin 2; ATMega16/32 Pin 14)

2. TxD: USART Transmit Pin (ATMega8 Pin 3; ATMega16/32 Pin 15)\
3. XCK: USART Clock Pin (ATMega8 Pin 6; ATMega16/32 Pin 1)

Modes of Operation

The USART of the AVR can be operated in three modes, namely-

1. Asynchronous Normal Mode

2. Asynchronous Double Speed Mode
3. Synchronous Mode

Asynchronous Normal Mode

In this mode of communication, the data is transmitted/received asynchronously, i.e. we do not need (and use) the clock pulses,
as well as the XCK pin. The data is transferred at the BAUD rate we set in the UBBR register. This is similar to the UART
operation.
Asynchronous Double Speed Mode

This is higher speed mode for asynchronous communication. The difference is that data is transferred at double the baud we set
in the UBBR Register. Setting the U2X bit in UCSRA register can double the transfer rate.

Synchronous Mode

This is the USART operation of AVR. When Synchronous Mode is used (UMSEL = 1 in UCSRC register), the XCK pin will
be used as either clock input (Slave) or clock output (Master).

Register Description

The USART of AVR has five registers, namely UDR, UCSRA, UCSRB, UCSRC and UBBR.

UDR: USART Data Register (16-bit)

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to
as USART Data Register or UDR. The Transmit Data Buffer Register (TXB) will be the destination for data written to the
UDR Register location. Reading the UDR Register location will return the contents of the Receive Data Buffer Register
(RXB).

USART Baud Rate Register (UBRR)

The baud rate of UART/USART is set using the 16-bit wide UBRR register. The register is as follows:

16-bit UBRR register is comprised of two 8-bit registers – UBRRH (high) and UBRRL (low).

Baud rate = (FOSC/(UBRR+1)).

UCSRA: USART Control and Status Register A

Error and status bits

UCSRB: USART Control and Status Register B

Control/ enable bits

UCSRC: USART Control and Status Register C

The UCSRC register can be used as either UCSRC, or as UBRRH register. This is done using the URSEL bit.

Initializing UART

1. Setting the Baud Rate

2. Setting Data Size (5/6/7/8/9 bits)
3. Enabling Reception/ Transmission (In the TXEN and RXEN bits in UCSRB)
4. Setting parity, and number of Stop Bits.

Procedure to transmit

Program to transmit ‘G’ serially at 9600 baud rate continuously. System clock 8MHz.

.INCLUDE "M32DEF.INC"
LDI R16,(1<<TXE ; enable transmit
OUT UCSRB, R16
LDI R16,(1<<UCSZ1)|(1<<UCSZ0)|(1<<URSEL) ; 8 bit, no parity, 1 stop bit
OUT UCSRC, R16
LDI R16,0x33 ; @8 MHz for 9600
OUT UBRRL,R16
AGAIN:
SBIS UCSRA,UDRE
RJMP AGAIN
LDI R16,'G'
OUT UDR,R16
RJMP AGAIN
Program to transmit “YES” continuously , serially at 9600baud, 8 bit data, and one stop bit.

.INCLUDE "M32DEF.INC"

LDI R21,HIGH(RAMEND)
OUT SPH,R21
LDI R21,LOW(RAMEND)
OUT SPL,R21

LDI R16,(1<<TXEN)
OUT UCSRB, R16
LDI R16,(1<<UCSZ1)|(1<<UCSZ0)|(1<<URSEL)
OUT UCSRC, R16
LDI R16,0x33
OUT UBRRL,R16

AGAIN:
LDI R17,'Y'
CALL TRNSMT
LDI R17,'E'
CALL TRNSMT
LDI R17,'S'
CALL TRNSMT
LDI R17,' '
CALL TRNSMT
RJMP AGAIN

TRNSMT:
SBIS UCSRA,UDRE
RJMP TRNSMT
OUT UDR,R17
RET

Procedure to receive

Program to receive data serially, @9600 baud rate, 8 bit data, one stop bit, and out received data on port b.
.INCLUDE "M32DEF.INC"

LDI R21,HIGH(RAMEND)
OUT SPH,R21
LDI R21,LOW(RAMEND)
OUT SPL,R21
LDI R16,(1<<RXEN)
OUT UCSRB, R16
LDI R16,(1<<UCSZ1)|(1<<UCSZ0)|(1<<URSEL)
OUT UCSRC, R16
LDI R16,0x33
OUT UBRRL,R16
LDI R16,0xFF
OUT DDRB,R16
RCVE: SBIS UCSRA,RXC
RJMP RCVE
IN R17,UDR
OUT PORTB,R17
RJMP RCVE
RS-232

RS-232 (Recommended Standard – 232) is a standard, describes the physical interface and protocol for relatively low-speed
serial data communication between computers and related devices

• Widely used serial i/o standard

• Not TTL compatible
• Logic 1 -3 to -25v
• Logic 0 3 to 25v
• -3 to -3v undefined
• The connection must be no longer than 50 feet
• Needs voltage converters/line drivers like MAX 232 ics
• Used to convert TTL voltage to RS232 and vice versa
• Original RS232 has 25 pin D connector
• Later it is modified to 9 pin D connector
In practice, serial communication with no handshaking uses 3 wires (TX, RX and GND)

When we want to interconnect two devices, one of which works over TTL and the other over RS232, we need to convert the
HIGH of TTL (which is 3.3v~5v) into the HIGH of RS232 (which is -3v ~ -25v) and similarly, the LOW of TTL (0v~0.8v)
into the low of RS232 (which is +3v ~ +25v).

IC MAX232

MAX232 ICs were invented by Maxim. Used to convert TTL/CMOS logics to RS232 logic . Need some passive components
only.
Limitations

The two devices must have same rate, for proper asynchronous transfer.

Complex h/w.

Minimum one start and stop pulse for every byte of data transfer.

Suitable for only two devices.

Speed limit.

Serial Peripheral Interface (SPI)

Serial Peripheral Interface (SPI) is a series interface protocol, commonly used to send data between microcontrollers and small
peripherals such as shift registers, sensors, and SD cards. It is a synchronous mode, uses separate clock and data lines, along
with a select line to choose the device. The side that generates the clock is called the “master”, and the other side is called the
“slave”. There is always only one master, but multiple slaves. The master sends a bit on the line and the slave reads it, while
the slave sends a bit on its line and the master reads it. Data transmission is full duplex.

Master places data byte(A) in its shift register, and the Slave places its data (B) in its shift register. Master generates 8 clock
pulses, and the contents of the Master's shift register are transferred to the Slave's shift register and vice versa. So, at the end of
the clock pulses, the Master has completely received B, and the Slave has received A.

 The interface can send data with the most-significant bit (MSB) first, or least-significant bit (LSB) first..
 The slave will read the data on either the rising edge or the falling edge of the clock pulse
 SPI can operate at extremely high speeds (millions of bytes per second
In an AVR, four signals (pins) are used for the SPI: MISO, MOSI, SCK and SS'

MISO (Master In Slave Out): the input of the Master's shift register, and the output of the Slave's shift register.

MOSI (Master Out Slave In): the output of the Master's shift register, and the input of the Slave's shift register.

SCK (Serial Clock): In the Master, this is the output of the clock generator. In the Slave, it is the input clock signal.

SS' (Slave Select): This tells the slave that it should wake up and receive / send data and is also used when multiple slaves are
present to select one.

SPI Registers

SPCR(SPI Control Register)

Control bits to select spi, enable spi interrupt, data flow order, master or slave mode selection, clock edge selection, idle clock
status, and frequency pre-scalar.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0

SPIE (SPI Interrupt Enable) bit: Set SPIE to one if you want the SPI interrupt to be executed when a serial transfer is
completed.

SPE (SPI Enable) bit: If you want to use the SPI, you must set this bit.

DORD (Data Order) bit: You can choose in which order the data will be transmitted. Set DORD to one to send the least
significant bit (LSB) first. Set DORD to zero to send the most significant bit (MSB) first.

MSTR (Master/Slave Select) bit: Set MSTR to configure the AVR as a Master SPI device. Clear MSTR to configure it as a
Slave.

CPOL (Clock Polarity) and CPHA (Clock Phase) bits:.'SPI modes'.

SPI Mode CPOL CPHA Sample

0 0 0 Leading (Rising) Edge

1 0 1 Trailing (Falling) Edge

2 1 0 Leading (Falling) Edge

3 1 1 Trailing (Rising) Edge

The following image shows figure 76 and 77 from the mega128 datasheet:

SPR1 and SPR2 (SPI Clock Rate Select) bits: The SPR bits configure the frequency of the clock signal.

SPR1 SPR0 SCK frequency

0 0 fosc/4

0 1 fosc/16

1 0 fosc/64

1 1 fosc/128

SPSR (SPI Status Register)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SPIF WCOL --- --- --- --- --- (SPI2x)

SPIF (SPI Interrupt Flag) bit: It is set by hardware when a serial transfer is complete

WCOL (Write Colision Flag) bit: The WCOL bit is set if the SPDR register is written to during a data transfer.

SPI2x (Double SPI Speed) bit: When this bit is set to one, the SPI speed will be doubled when the SPI is in Master mode.

SPDR (SPI Data Register)

The SPI Data Register used for data transfer between the Register File and the SPI Shift Register. Writing to the register
initiates data transmission. Reading the register causes the Shift Register receive buffer to be read.

Advantages of SPI:

 It’s faster than asynchronous serial

 Full duplex communication in the default version of this protocol
 The receive hardware can be a simple shift register
 It supports multiple slaves

Disadvantages of SPI:

 It requires more signal lines (wires) than other communications methods

 The communications must be well-defined in advance (you can’t send random amounts of data whenever you want)
 The master must control all communications (slaves can’t talk directly to each other)
 It usually requires separate SS lines to each slave, which can be problematic if numerous slaves are needed.
I²C (Inter-Integrated Circuit)

I²C (Inter-Integrated Circuit), is a multi-master, multi-slave, packet switched, single-ended, serial protocol, used for
attaching lower-speed peripheral ICs to processors and microcontrollers in short-distance, intra-board communication.

Basics of I2C

The I²C (Inter-Integrated Circuit) protocol, referred to as I-squared-C, I-two-C, or IIC) is two wire serial communication
protocol for connecting low speed peripherals to a micrcontroller or computer motherboard.

I²C require two wires for communication.,Serial Data (SDA) and Serial Clock (SCL) .The Master generates the clock for
serial communication(SCL). A stream of data bits(B1 to BN) is transferred between the start and the stop bits. I2C bus drivers
are open drain, each line has a pull up resister, so no bus over loading and damage. Up to 120 devices (nodes) can be
connected.

I2C Timings and Conditions.

Data transfer is initiated with the Start(S) ,ieSDA goes from high to low when SCL is high .

A data bit is transmitted at every low level of the clock (SCL) after the start condition.

To stop the data transfer, the clock(SCL) is held high, while data(SDA) goes from low to high.

Message has two frames ; one address frame and one or more data frames.

Information ( address/data) is transferred as a packet of 9 bits. 7-bit address, the address is clocked out most significant bit
(MSB) first, followed by a R/W bit indicating whether this is a read (1) or write (0) operation. The 9th bit is the NACK/ACK
bit, from the slave to acknowledge-low/ not acknowledge –high, the receipt of data. Address is used to select a slave, and if it
is ready ACK is generated in 9th clock, else NACK. In this case master may send a stop signal to abrt operation or a repeated
start to initiate a new transmission,

After the address, any number of frames of data transfer initiated, from master or slave depends on the R/W bit.

After data frames stop bit is send by the master.

Clock stretching
Some slow slaves keeps the SCL line low until it is ready and refrain master from generating further clocks. It is called clock
stretching.
In AVR,I2C is referred as TWI- two wire serial interface. TWI module of atmega 32 consists of rate generator-control clock
frequency when operating as master , address match unit- receives address when operating as slave, interface unit-generating
start, stop and receive ACK and related signals, and control unit.

TWBR ( TWI Bit Rate Register )

Controls SCL rate by along with prescaler value in master mode

SCL= CPU_clock/(16 + 2*TWBR*(4^prescaler))

TWCR ( TWI Control Register )

Bits to Controls TWI interface, like generation of start, stop etc, interrupt flag, enable bit etc.

TWSR ( TWI Status Register )

Contains twi status bits(5bits), and SCL prescaler bits(2bits)

TWDR ( TWI Data Register )

In Transmit mode, contains the next byte to be transmitted, last byte received, in receiving mode.