Professional Documents
Culture Documents
ON
Submitted by:
NAME
ROLL NO. OF THE CANDIDATE
BACHELOR OF TECHNOLOGY
IN
Computer Science & Engineering
.
Acknowledgement to SUPERVISOR (INTERNAL SUPERVISOR FROM MRIIRS)
Acknowledgement to TRAINING COORDINATOR….(DR NITASHA SONI & MS MONIKA
GARG)
Acknowledgement to HOD….(DR TAPAS KUMAR)
Acknowledgement to ASSOCIATE DEAN….(DR GEETA NIJHAWAN)
I (We) hereby declare that this project report entitled “TITLE OF PROJECT WORK” by NAME
OF STUDENT (ROLL NUMBER), being submitted in partial fulfillment of the requirements for the
degree of Bachelor of Technology in Computer Science and Engineering under Faculty of
Engineering & Technology of Manav Rachna International Institute of Research and Studies,
Faridabad, during the academic year December,2020, is a bonafide record of our original work carried
out under guidance and supervision of NAME OF MENTOR/TRAINING GUIDE,
DESIGNATION , DEPARTMENT and has not been presented elsewhere.
December, 2020
Certificate
This is to certify that this project report entitled “TITLE OF PROJECT WORK” by NAME OF
STUDENT (ROLL NUMBER), submitted in partial fulfillment of the requirements for the degree of
Bachelor of Technology in Computer Science and Engineering under Faculty of Engineering &
Technology of Manav Rachna International Institute of Research and Studies Faridabad, during the
academic year December 2020, is a bonafide record of work carried out under my guidance and
supervision.
Acknowledgement i
Declaration ii
Certificate iii
Table of Contents v
List of Figures vi
Abstract viii
Chapter Page No
I. Introduction
II.1Introduction
II.2Survey
II.3Conclusion
IV.1 Introduction
IV.2 Functional Decompositions
IV.3 Different Design Options
IV.4 Proposed Flow Model
IV.5 Circuit Design
IV.6 Simulation Platform (wherever required)
IV.7 PCB Design (wherever required)
IV.8 Assembly of Hardware and Components
V.1Verification
V.2Validation
V.3Evaluation
References/Bibliography
LIST OF TABLES
Table Page No
………….
…………
ABSTRACT
REFERENCES
[1] J. Cong, C. Wu, and Y. Ding, “Cut ranking and pruning: Enabling a general and efficient FPGA
mapping solution," in Proc. of ACM Intl. Symp. on Field Programmable Gate Arrays, 1999, pp. 29-
35.
[2] A. Ling, D. P. Singh, and S. D. Brown, “FPGA technology mapping: A study of optimality," in
Proc. of IEEE/ACM Design Automation Conf., 2005, pp. 427-432.