IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 33, NO.
1, MARCH 2010 3
Development of 3-D Silicon Module With TSV
for System in Packaging
Navas Khan, Vempati Srinivasa Rao, Samuel Lim, Ho Soon We, Vincent Lee, Xiaowu Zhang, E. B. Liao,
Ranganathan Nagarajan, T. C. Chai, V. Kripesh, and John H. Lau, Fellow, IEEE
Abstract—Portable electronic products demand multifunc-
tional module comprising of digital, radio frequency and memory
functions. Through silicon via (TSV) technology provides a
means of implementing complex, multifunctional integration
with a higher packing density for a system in package. A
3-D silicon module with TSV has been developed in this pa-
per. Thermo-mechanical analysis has been performed and TSV
interconnect design is optimized. Multiple chips representing
different functional circuits are assembled using wirebond and
flip chip interconnection methods. Silicon carrier is fabricated
using via-first approach, the barrier copper via is exposed by the
backgrinding process. A two-stack silicon module is developed
and module fabrication details are given in this paper. The
module reliability has been evaluated under temperature cycling
(−40/125 °C) and drop test.
Index Terms—3-D packaging, system in packaging, through
silicon via.
I. Introduction
M ICROELECTRONICS packaging is driven by the con-
tinuous increase in demands for smaller form fac-
tor, faster, high-density interconnection at cheaper cost. Also
portable product design requires integration of heterogeneous
semiconductor technologies in a module for minimum system
board area. High level of silicon integration for baseband
functions is achieved with the advances in complementary
metal-oxide semiconductor technologies. But radio frequency
(RF) and memory functions integration for cell phones is
currently being accomplished by system in package (SiP)
design. Traditional substrate and packaging technologies may
not support the high density and heterogeneous integration
needed for such applications. Newer packaging approaches,
such as through silicon via (TSV) and 3-D SiP, complement
or replace the wire-bond chip stack package and multichip
package [1], [2]. The TSV provides electrical connectiv-
ity between different functional blocks through the silicon
chip/carrier. TSV technology has other potential benefits such
Manuscript received March 26, 2008; revised March 23, 2009. First version
published February 22, 2010; current version published March 10, 2010. Rec-
ommended for publication by Associate Editor R. Chanchani upon evaluation
of reviewers’ comments.
The authors are with the Microsystems, Modules and Components
Laboratory, Institute of Microelectronics, Singapore 117685 (e-mail:
oknavas@ime. a-star.edu.sg; vempati@ime.a-star.edu.sg; limyl@ime.a-
star.edu.sg; hosw@ime.a-star.edu.sg; leews@ime.a-star.edu.sg; xiaowu@
ime.a-star.edu.sg; nathan@ime.a-star.edu.sg; taichong@ime.a-star.edu.sg;
kripesh@ime.a-star. edu.sg; lauhs@ime.a-star.edu.sg).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCAPT.2009.2037608
1521-3331/$26.00

c 2010 IEEE
as reduced wire length between block-to-block, high-density
interconnection. The TSV allows integrating multiple chips
with a physical packing density many times better than the
multichip module.
The conventional substrate technologies have a large via
size and wider line width/line spacing. It may not meet the
future requirements of line width <10 µm and thousands of
input—output (I/O) pads per square centimeter [3]. Silicon
carrier based substrate technology provides dense wiring using
back-end of-line processing. Matched thermal expansion of
the carrier and the chip allows the use of micro bumps and
improves solder interconnects reliability [4]. The 3-D package
construction results in a large thermal resistance, which makes
difficult to cool the chip mounted in the inner layers of the
package. But the silicon carrier has better thermal conductivity
compared to conventional substrate material, which helps to
reduce the 3-D package thermal resistance [5]. Development of
a 3-D-SiP using silicon carrier with TSV for the integration of
RF, baseband, memory chips have been presented in this paper.
The silicon carrier allows further integration of passive devices
using thin film technology. We integrated resistor, capacitor,
and inductors on the silicon carrier wafer. We demonstrated
high Q inductors and a band-pass filter for wireless local area
network application on this platform technology [6].
II. Module Construction
A 3-D module consists of two stacks assembled one over
other with three chips. The module size is 12 mm × 12 mm
and 1.3 mm thickness. The silicon carrier is 12 mm ×
12 mm × 0.2 mm with 168 peripherally populated via. The
bottom carrier (Carrier 1) is assembled with a 5 mm × 5 mm
flip-chip. The top carrier (Carrier 2) is assembled with a
5 mm × 5 mm flip-chip and two numbers of 3 mm × 6 mm
wirebond chip. Carrier 2 is overmolded to protect the wire
bond chip. The silicon carrier has been fabricated with two
metal layers with SiO2 as dielectric/passivation layer. Elec-
trical connections through the carrier are formed by TSV. A
schematic of the two stack module and chip arrangement on
Carriers 1 and 2 are shown in Fig. 1.
III. Thermo-Mechanical Design
Thermo-mechanical design of the 3-D silicon module is im-
portant for the reliable package structure. Structural parameters
like via size, via shape, and solder joint are analyzed for the
4 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 33, NO. 1, MARCH 2010

Fig. 2. Thermo-mechanical analysis of via shape.

Fig. 1. Schematic of 3-D silicon module and carrier layout.

TABLE I
Material Properties for Thermo-Mechanical Analysis

Young Modulus Poisson Common

(GPa) Ratio Table
Expression Fig. 3. Via arrange on the carrier.
(ppm/°C)
Benzocyclobutene 2.9 0.34 52
(BCB)
8% higher shear stress than the cylindrical shape. The tapered
SiO2 70 0.16 0.6 via is preferred for TSV fabrication processes like conformal
Ti 116 0.34 8.9 deposition of dielectric/barrier/seed layer and void free copper
Silicon 129.617 (25 °C) 0.28 2.813 filling. Small via size allows high density routing in the carrier.
128.425 (150 °C) (25 °C) In this project, we chose via size of 100 µm tapering to
3.107
(150 °C) 50 µm. The interfacial stress of tapered via and cylindrical
SnAgCu 44.4 (25 °C) 0.4 21 via is shown in Fig. 2.
30.7 (75 °C) The location of the solder joint with respect to the TSV
18.8 (125 °C)
is critical for interconnect reliability and redistribution layer
Printed Ex,y = 22.4 vx = 0.2 αx, y = 16
circuit board (30 °C), vy,z = 0.1425 αz = 65 (RDL) design. Pad-on via and off-set via designs have been
(PCB) 19.3 (125 °C) evaluated. The pad-on design, where the solder ball is directly
Ez = 16 (30 °C), on the copper plug (TSV), but the copper plug is much smaller
1 (125 °C)
Cu E = 130.0 0.34 18
compared to the solder pad area as shown in Fig. 3. The pad-
εp = 0, on via design has advantages in terms of shorter electrical path
σ = 0.1379 from chip to the board and un-broken power/ground plane de-
εp = 0.098982,
σ = 0.2715
sign. Both the designs show comparable stress condition in the
solder joint. The simulation results show maximum stress con-
minimum thermo-mechanical stress. The finite element (FE) centration at the smaller section of the via. Therefore, the pad-
analysis is carried using ABAQUS [7]. 2-D eight node solid on via design has been selected for the module construction.
element is used for the FE model. The stress free temperature
state is taken as 125 °C for thermo-mechanical analysis. IV. Carrier Fabrication
Material properties used for the thermo-mechanical analysis An eight-inch silicon wafer is used for the TSV carrier
are given in Table I. fabrication. Main processes steps are via etching, deposition
The TSV can be designed in cylindrical shape and tapered of dielectric/barrier/seed layer, via filling, chemical mechanical
shape, thermo-mechanical stresses of the TSV has been studied polishing (CMP) of copper overburden, RDL formation, wafer
using FE analysis. The tapered TSV structure of size 50 µm thinning, via exposure, and dielectric/under bump metalliza-
and 100 µm diameter has been analyzed. The interfacial stress tion (UBM) deposition. The TSV fabrication processes can be
between the copper and the surrounding silicon carrier is broadly classified as the via-first or via-last approach. In via
comparable for both via sizes. But the tapered shape showed first approach, the TSV is fabricated before the circuit/RDL
KHAN et al.: DEVELOPMENT OF 3-D SILICON MODULE WITH TSV FOR SYSTEM IN PACKAGING
Fig. 4. Carrier fabrication process flow and images.
formation. In the via-last approach, the TSV is formed after
the circuit/RDL formation on the wafer. The via–first approach
is preferred for the silicon carrier technology, because most
of TSV fabrication processes are carried out with the full
wafer thickness, then the wafer is thinned to required thickness
for via exposure. The thinned wafer is processed further to
form the necessary back side metallization/UBM. The carrier
fabrication process flow is shown in Fig. 4. The silicon wafer
is etched using the deep reactive ion etch process forming
blind via of 50 µm diameter and 200 µm deep. Via tapering
is accomplished by a controlled isotropic etch chemistry
consisting of SF6 , Argon (Ar), and O2 plasma after the straight
etch process. The via formation process is split into three steps
viz.: 1) straight via formation; 2) via tapering process by a
controlled isotropic etch; and 3) corner rounding by a global
isotropic etch process. Tapered via of size 50 µm at the base
and 100 µm at the top is achieved after via tapering steps.
A dielectric layer of 1 µm SiO2 has been deposited by
the plasma enhanced chemical vapor deposition (PECVD)
process. Barrier and seed layers of Ti and Cu are deposited
using the physical vapor deposition process. The sidewall
deposition uniformity is characterized by cross section
analysis. The oxide thickness varied from 0.8 µm at the top
of the via to 0.4 µm at the bottom of the via as shown in
Fig. 5. Damascene copper plating is used for the via filling.
Typical composition of copper plating electrolyte includes
CuSO4 , H2 SO4 , Cl− , with additives such as Suppressor,
Accelerator, and Leveler. The plating solution used is
Everplate-Cu200 from Atotech. We developed the pulse
reverse plating process recipe and demonstrated void free via
filling. The plating current has been optimized and complete
via plating is achieved in three steps viz.: 1) step 1—low
forward current plating; 2) step 2—medium forward current
plating; and 3) step 3—high forward current plating.
5
Fig. 5. Coverage of SiO2 in deep silicon via.
Fig. 6. Wafer images after TSV formation.
A thick layer of copper overburden (30–40 µm) was ob-
served on the TSV wafer surface because of the long plating
time required for filling the 200 µm deep via. The wafer
warpage/bow observed to be lager (>500 µm) due to the thick
copper overburden, it was measured using an optical probe.
Different methods were considered for the removal of the
copper overburden. Chemical etching took long time to remove
the thick copper overburden and observed non-uniform etch
rate across the wafer. CMP was evaluated using aggressive
Cu polishing slurry from Rohm and Hass. We developed two-
step polishing to remove the thick copper: step 1 to remove
the bulk of the copper with high down force (320 g/cm2 ), and
step 2 to remove a thin layer of copper with lower down force
(100 g/cm2 ). The wafer images before and after the CMP are
shown in Fig. 6. After CMP, an RDL has been deposited for
electrical re-distribution on the carrier wafer. We evaluated
BCB and SiO2 as dielectric layer and both the materials were
found suitable for our application. A low-temperature (250 °C)
PECVD process was used for the SiO2 dielectric deposition.
Exposing the buried copper via in the carrier TSV wafer
is a challenge, because it requires grinding brittle silicon
and ductile copper simultaneously. Conventional backgrinding
wheel is found not suitable for the ductile copper and observed
wheel clogging. We used a rough grinding step followed by a
fine grinding step and CMP to relieve the stress. The carrier
wafer was thinned to 250 µm thickness by course grinding,
remaining 50 µm was removed with the vitrified bond wheel.
Then the wafer was polished by the wet method to remove
the sub-surface damages. The wafer surface roughness (Ra)
is 17 nm and 0.45 nm after grinding and wet polishing,
respectively. The wafer surface was analyzed by energy-
dispersive X-ray spectroscopy and AUGERE and found no
6 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 33, NO. 1, MARCH 2010

Fig. 9. Images of stud bump interconnection.

Fig. 7. Wafer images after TSV formation.

Fig. 10. Images of stacked wire bond chips.

Fig. 8. Images of carrier wafer after debonding. (a) Polymer residue without
sacrificial layer. (b) No residue with sacrificial layer.

copper contamination on the wafer. The carrier wafer showing

exposed Cu via is given in Fig. 7.

V. Thin Wafer Handling

Handling TSV wafer of 200 µm thickness through multiple
process steps like oxide deposition, lithography, copper RDL
plating is difficult. It is not allowed to process such a thin
wafer in most of the wafer processing tools. We developed a
thin wafer handler process using a perforated support wafer
and temporary adhesive. The temporary adhesive used in the
project is spin on polymer from Brewer Science. The polymer
is spin coated on the TSV carrier wafer and bonded with the
perforated support wafer using EV Group wafer bonder. The
wafer bonding was done at 1.2 kN force, 150 °C for 5 min.
The bonded wafer was processed for the backside metalliza-
tion/UBM and passivation layers. After all the processes, the
carrier wafer was debonded by wet stripping the temporary
adhesive through the perforated support wafer. This method
is found suitable for our project, but observed some polymer
residues on the wafer surface. A sacrificial layer of Titanium
was deposited on the TSV carrier wafer before attaching with
the support wafer. The sacrificial layer was etched by wet
process after debonding from the support wafer. This sacrificial
layer helped to protect the carrier wafer surface and polymer
residue was etched away along with the sacrificial layer. Fig. 8
shows images of wirebond and flip-chip pads after debonding.
VI. Module Assembly
We evaluated gold stud bump and solder interconnect for
chip 1 and chip 2, respectively. Chip 1 has been designed with
72 peripheral I/O. Chip 1 is stud bumped using stud bump
bonder. The stud bumping parameters have been optimized
and achieved 45 µm bump height with 4 kgf coining force.
The stud bump shear and failure mode have been evaluated
for high temperature storage up to 1000 h. The bumps showed
Fig. 11. Images of 3-D silicon module. (a) Cross section of the 3-D module.
(b) 3-D module without over. (c) 3-D module with over molding.
good shear value of >60 g. Three NCP materials have been
evaluated and the interconnect reliability has been assessed
up to 1000 thermal cycles (TC). All the three materials with
bonding force >10 kgf showed no failure. Fig. 9 shows the
stud profile and cross section of the chip attachment. Chip 2
has been designed with 252 I/O at 200 µm bump pitch. Chip 2
was bumped using SAC305 type 6 solder paste and achieved
bump height of 55 µm. The bump shear has been evaluated
for Pb free reflow condition (five times) and found the bump
shear value >60 g with bulk solder failure mode.
Chip 3 represents memory die in our module design. Stack-
ing of two chips has been demonstrated using dicing die attach
film (DDAF) and wire embedding film. Three DDAF materials
have been evaluated and all the materials showed no void after
the Moisture Sensitivity Level 3 condition test. The materials
have also been evaluated in hot shear test at 260 °C. One of
the materials has been selected based on minimum bleeding.
Wire embedding film is an emerging technique to stack wire
bond chips. The film is soft enough to flow over the wires
KHAN et al.: DEVELOPMENT OF 3-D SILICON MODULE WITH TSV FOR SYSTEM IN PACKAGING
Fig. 12. Drop test setup and results.
and there is no need for a spacer die. This method gives small
stand-off for the stacked wire bond chips. The bond parameters
like top/bottom heater temperature and bond speed have been
optimized. Carrier 2 is assembled with flip-chip and wire bond
chip. Therefore, the pad finish should be suitable for both the
chip attachment methods. Pads on the carrier top and bottom
side are plated with electroless NiPdAu. Wire bondability and
wire pull strength are found good on the NiPdAu pads. Two
chips have been stacked and demonstrated low loop height
(<50 µm) for the chip stacking. Fig. 10 show the stacked
wire bond die assembled for this paper.
Carrier 1 is mounted on a FR4 PCB using SAC305 solder
of 250 µm diameter. Carrier 1 assembly is underfilled and
cured at 165 °C for 3 h. Carrier 2 is over molded using the
transfer molding process. Then Carrier 2 is assembled on the
Carrier 1 and underfilled. Fig. 11 shows the images of the 3-D
silicon module. We prepared samples having Carrier 2 with
and without overmold for reliability assessment.
VII. Module Reliability Assessment
The 3-D silicon module is assembled onto a two-layer PCB.
The PCB design is based on JESD22-B111 in terms of package
layout, metal traces, and pad opening design. Separate daisy
chain for the three chip interconnections, Carrier 1 to PCB
and Carrier 1 to Carrier 2 has been designed. The 3-D silicon
module was tested for drop and thermal cycle reliability test
condition. Preliminary drop test of the 3-D module without
underfill showed complete detachment of the carrier from the
PCB. Samples with underfill and overmold passed the 30 drops
at 1500 G, 0.5 ms pulse duration. The drop test setup and
results are shown in Fig. 12.
The reliability of the 3-D silicon module has been assessed
for thermal cycle reliability conditions (−40 °C to 125 °C,
ramp 15 C/min, dwell 15 min). Fig. 13 shows the cross section
of solder and TSV of Carrier 1 and Carrier 2. Electrical con-
tinuity of the TSV and solder joint was monitored by separate
daisy chains. The daisy chain resistance was monitored every
250 cycles. The solder interconnects and TSV joints showed
no crack or detachment at time zero. However some of TSV
chains showed open, when we measured the resistance after
500 cycles.
7
Fig. 13. Cross section of solder and TSV.
Fig. 14. SEM micro graph failed sample for TC test.
TABLE II
Chip Solder Interconnect TC Results
Daisy Chain Resistance ()
Time 0 500 1000 2000
cycles cycles cycles
Chip 1 24.3 24.3 24.3 34.3
Chip 2 17.3 18 18.9 20.5
The failed samples were cross-sectioned and failure anal-
ysis was performed. The failed samples show detachment
of RDL/UBM metal layer form the copper via as shown in
Fig. 14. During the carrier fabrication, the 1 µm thick SiO2
layer was used as the dielectric layer after the via exposure and
the contact opening on the via was patterned. Then the barrier
layer of 1 KA Ti and the seed layer of 2 KA Cu were sputtered
for copper RDL formation. Poor adhesion of the sputtered
metal layers on the TSV and stress due to thermal expansion
of TSV are potential cause for the above failure.
Chip 1 and chip 2 are assembled with the carrier using
solder. The solder height is ∼50 µm, which helps to reduce
the stack height. The carrier and chip are silicon, therefore no
thermal mismatch between them. Both the chips showed good
interconnect reliability, no failure in solder interconnection
was observed even after 2000 TC cycles. The chip 1 and 2
solder joint reliability is measured by electrical continuity of
the daisy chain and electrical resistances are given Table II.
VIII. Conclusion
A 3-D silicon module platform technology using silicon
carrier technology has been developed and demonstrated for
system in packaging application. Silicon carrier (substrate)
with TSV interconnection is developed for chip attachment
and embedded passives integrations. The module thermo-
mechanical and reliability performances have been reported
in the paper. Chip interconnection methods, such as flip-
chip, wirebond, and gold stud bump have been evaluated and
interconnections reliability is reported. Some important results
and recommendations are summarized as follows.
1) A tapered via structure has been designed and void free
filling has been achieved using damascene pulse-reverse
plating.
8 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 33, NO. 1, MARCH 2010
2) Silicon carrier fabrication process based on the via-first
approach is established and developed 200 µm thick
carrier with TSV for 3-D module assembly.
3) Thin wafer handling technique using spin-on temporary
adhesive is evaluated and found suitable for the silicon
carrier fabrication.
Acknowledgment
This paper is the result of a project initiated by the Micro-
System Packaging Initiative Electronic Packaging Research
Consortium, EPRC VIII Project 2: stacked silicon module
with embedded passives for SiP application. The authors
would like to thank the consortium members and project
team for their support and guidance. The consortium members
are ASM Technology Singapore Pte Ltd., Freescale Semi-
conductor Malaysia Sdn Bhd., Ltd., Infineon Technologies
Asia Pacific Pte Ltd., Microcircuit Technology (2002) Pte
Ltd., STATSChipPAC, Ltd., Ibiden Singapore Pte Ltd., Surface
Technology Systems Pte Ltd., United Test and Assembly
Center Ltd., Institute of Microelectronics, Institute of Ma-
terials Research and Engineering, Institute of High Perfor-
mance Computing, and Singapore Institute of Manufacturing
Technology.
References
[1] S. F. Al-Sarawi, D. Abbott, and P. Franzon, “A review of 3-D-packaging
technology,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 21,
no. 1, pp. 2–14, 1998.
[2] Y. Yano, T. Sugiyama, S. Ishihara, Y. Fukui, H. Juso, K. Miyata,
Y. Sota, and K. Fujita, “Three-dimensional thin stacked packaging
technology for SiP,” in Proc. Electron. Compon. Technol. Conf., 2002,
pp. 1329–1334.
[3] J. U. Knickerbocker, P. S. Andry, L. P. Buchwalter, A. Deutsch, R. R.
Horton, K. A. Jenkins, Y. H. Kwark, G. McVicker, C. S. Patel, R. J.
Polastre, C. Schuster, A. Sharma, S. M. Sri-Jayantha, C. W. Surovic,
C. K. Tsang, B. C. Webb, S. L. Wright, S. R. McKnight, E. J. Sprogis,
and B. Dang, “Development of next-generation system-on-package (SOP)
technology based on silicon carriers with fine-pitch chip interconnection,”
IBM J. Res. Dev., vol. 49, nos. 4–5, pp. 725–753, Jul. 2005.
[4] S. W. Yoon, D. Witarsa, S. Y. L. Lim, V. Ganesh, A. G. K. Viswanath,
T. C. Chai, K. O. Navas, and K. Vaidyanathan, “Reliability studies of a
through via silicon stacked module for 3-D microsystem packaging,” in
Proc. Electron. Compon. Technol. Conf., 2006, pp. 1449–1453.
[5] N. Khan, S. W. Yoon, A. G. K. Viswanath, V. P. Ganesh, D. W.
Ranganathan, S. Lim, and K. Vaidyanathan, “Development of 3-D stack
package using silicon interposer for high power application,” in Proc.
Electron. Compon. Technol. Conf., 2006, pp. 756–760.
[6] H. Y. Li, Y. M. Khoo, N. Khan, K. W. Teoh, V. S. Rao, H. B. Li, E.
B. Liao, S. Mohanraj, V. Kripesh, and K. Rakesh, “High performance
embedded RF passive device process integration,” in Proc. Electron.
Compon. Technol. Conf., 2008, pp. 1709–1713.
[7] Hibbitt, Karlsson and Sorensen, Inc., Pawtucket, RI, ABAQUS 6.41.
Navas Khan received the B.E. degree in mechanical
engineering from Bangalore University, Bangalore,
India, in 1993, and the M.E. degree in mechanical
engineering from Nanyang Technological University,
Singapore, in 2006.
He is a Member of the Technical Staff at the
Microsystems, Modules and Components Labora-
tory, Institute of Microelectronics, Singapore. He has
many years of experience in the area of advanced
packaging. He was with C-Dot, India, from 1994
to 2009 in the area of system level packaging of
telecommunication electronics. Currently, he is working on through silicon
via and silicon interposer technology.
Vempati Srinivasa Rao received the B.Tech. degree
in metallurgical engineering from the National In-
stitute of Technology, Warangal, India, in 2002, and
the M.E. degree in mechanical engineering from the
National University of Singapore, Singapore.
Since 2006, he has been a Research Engineer
with the Microsystems, Modules and Components
Laboratory, Institute of Microelectronics, Singapore.
His research interests include wafer level packag-
ing, fine pitch interconnects, Cu/low-k packaging,
through silicon via technology, 3-D stacked module,
wafer level integration, and package reliability.
Samuel Lim received the B.E. degree in mechanical
and manufacturing engineering from the University
of South Australia, Adelaide, Australia, in 2006.
He has been involved in the process integration of
3-D stacked silicon modules in the Microsystems,
Modules and Components Laboratory, Institute of
Microelectronics, Singapore, as a Lab Officer.
Ho Soon We received the B.E. degree in materials
engineering from Nanyang Technological University,
Singapore, in 2006.
He is currently a Research Officer with the Mi-
crosystems, Modules and Components Laboratory,
Institute of Microelectronics, Singapore. His re-
search interests include wafer level packaging, sil-
icon based 3-D system in packages, through silicon
via process integration, and thin wafer handling.
Vincent Lee received Diploma in chemical engi-
neering from SP, in 2006.
He has been working as a Lab Officer with the Mi-
crosystems, Modules and Components Laboratory,
Institute of Microelectronics, Singapore, in the area
of advanced packaging. His fields of expertise are
wafer thinning and dicing.
Xiaowu Zhang received the B.S. degree in physics
from the National University of Defense Technol-
ogy, Changsha, China, in 1986, the M.E. degree
in mechanics from the University of Science and
Technology of China, Hefei, China, in 1989, and
the Ph.D. degree in mechanical engineering from the
Hong Kong University of Science and Technology,
Clear Water Bay, Kowloon, Hong Kong, in 1999.
He was a Lecturer with the East China Institute of
Technology, Fuzhou City, China, from 1989 to 1994.
He has been with the Institute of Microelectronics
(IME), Singapore, since 1999. Currently, he is a Member of the Technical Staff
at the Microsystems, Modules and Components Laboratory, IME, Singapore.
His research activities include advanced packaging development and 3-D
integrated circuit integration. He has authored or co-authored more than 90
technical papers in refereed journals and conference proceedings.
Dr. Zhang is the recipient of the 2001 JEP Best Paper Award conferred by
the ASME Transactions Journal of Electronic Packaging.
KHAN et al.: DEVELOPMENT OF 3-D SILICON MODULE WITH TSV FOR SYSTEM IN PACKAGING
E. B. Liao received the B.E. degree in metallurgical
engineering from the Central South University of
Technology, Changsha, China, the M.E. degree in
materials engineering from the Institute of Metal Re-
search of the Chinese Academy of Sciences, China,
and the M.E. and Ph.D. degrees in mechanical engi-
neering from the National University of Singapore,
Singapore.
In 2005, he joined the Microsystems, Modules and
Components Laboratory, Institute of Microelectron-
ics, Singapore, and is currently a Senior Research
Engineer. His research interests include advanced packaging technologies,
microfabrication techniques, and radio frequency passive devices.
Ranganathan Nagarajan received the B.E. de-
gree in electronics and telecommunications from
Osmania University, Hyderabad, India, in 1982, and
the M.Tech degree in integrated electronics and
circuits from the Indian Institute of Technology, New
Delhi, India, in 1984.
He has over 24 years of diverse techni-
cal experience in complementary metal–oxide–
semiconductors, micro-electro-mechanical systems,
and wafer level packaging technologies. He is cur-
rently with the Microsystems, Modules and Com-
ponents Laboratory, Institute of Microelectronics, Singapore, as a Mem-
ber of the Technical Staff. His areas of expertise and interest include
high aspect ratio silicon micro-machining, nano electromechanical systems,
bio-micro-fluidics, and 3-D wafer level stacking technology.
T. C. Chai received the Bachelor degree in me-
chanical engineering from Heriot-Watt University,
Edinburgh, U.K.
Previously, he was with Texas Instruments,
Singapore, as a Packaging Development Engineer.
He is currently a Member of the Technical Staff at
the Microsystems, Modules and Components Labo-
ratory, Institute of Microelectronics, Singapore. He
has worked on areas of packaging development, re-
liability, and failure analysis for 18 years. Recently,
his focus has been on flip chip packaging for Cu
low-K chip and through silicon via technology.
9
V. Kripesh received the Bachelor degree in physics
from the University of Madras, Chennai, India, in
1985, the M.S. degree in physics from the University
of Madras in 1987, and the Ph.D. degree in 1995.
He carried out his doctoral work at the Max-Planck
Institute for Metalforschung, Stuttgart, Germany, in
the area of thick and thin film passives for micro-
electronics modules.
He has 16 years of research experience in the area
of advanced packaging, and he has worked as a Vis-
iting Scientist at Infineon Technologies, Corporate
Research, Munich, Germany, in the area of 3-D-integrated circuits. Since
March 2000, he has been with the Microsystems, Modules and Components
Laboratory, Institute of Microelectronics, Singapore. He has authored more
than 40 journal and conference publications. His research interests include 3-
D-silicon stacked modules, Cu/low-k packaging, and wafer level packaging.
John H. Lau (F’94) received three M.S. degrees
in structural engineering, engineering physics, and
management science, and the Ph.D. degree in the-
oretical and applied mechanics from the University
of Illinois, Chicago.
He is the Director of the Microsystems, Modules
and Components Laboratory, Institute of Micro-
electronics, Singapore. Prior to this, he was with
HP/Agilent for more than 20 years. With more than
30 years of research and development and manufac-
turing experience in the electronics and photonics
industries, he has authored and co-authored over 250 peer-reviewed technical
publications, authored more than 100 book chapters, and given over 250
workshops and invited presentations.
Dr. Lau is one of the elected Fellows of the American Society of Mechanical
Engineers.