SSE Chap-17 Doping59 - 4p

doping
固態工程
Solid State Engineering
Chapter 17
Doping Processes
Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda © 2001by Prentice Hall by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang 2
Objectives Objectives
After studying the material in this chapter, you will be able to:
After studying the material in this chapter, you will be able to:
1. Explain the purpose and applications for doping in wafer
fabrication.解釋晶圓製作中，摻雜的目的與應用。 5. List and describe the five major subsystems for an ion
2. Discuss the principles and process of dopant diffusion. implanter.列出並描述離子植入所需之5項主要次系統。
討論摻質擴散的原理與製程。
6. Explain annealing and channeling in ion implantation.
3. Provide an overview of ion implantation, including its 解釋何謂離子植入之回火及通道效應。
advantages and disadvantages.
提供有關離子植入之概要說明，包括它的優缺點。 7. Describe different applications of ion implantation.
描述出離子植入的不同應用。
4. Discuss the importance of dose and range in ion implant.
討論離子植入時，有關劑量與範圍的重要性。

by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang 3 by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang 4
Common Dopants Used Video files of Ion Implantation
in Semiconductor Manufacturing
• http://www.youtube.com/watch?v=vK-geBYygXo at
Acceptor Dopant Donor Dopant
3:50
Semiconductor
Group IIIA
(P-Type)
Group IVA
Group VA
(N-Type)
• (1) Ion Implantation (Simple Animation) – YouTube
Atomic Atomic Atomic
Element Element Element
Number Number Number
Boron (B) 5 Carbon 6 Nitrogen 7
Aluminum 13 Silicon (Si) 14 Phosphorus (P) 15
Gallium 31 Germanium 32 Arsenic (As) 33 • http://www.matec.org/animations/
Indium 49 Tin 50 Antimony (Sb) 51
Group VIA : Oxygen (O)
Table 17.1
CMOS Structure with Doped Regions CMOS Structure with Doped Regions
Process Step Dopant Method Process Step Dopant Method
A. p+ Silicon Substrate B Diffusion I. n-Channel Lightly Doped Drain (LDD) As Ion Implant
- In-situ doping
B. p Epitaxial Layer B Diffusion J. n-Channel Source/Drain (S/D) As Ion Implant
C. Retrograde n-Well P Ion Implant K. p-Channel LDD BF2 Ion Implant
D. Retrograde p-well B Ion Implant
L. p-Channel S/D BF2 Ion Implant
E. p-Channel Punchthrough P Ion Implant
M. Silicon Si Ion Implant
F. p-Channel Threshold Voltage (VT) Adjust P Ion Implant
Ion Implant or
G. p-Channel Punchthrough B Ion Implant N. Doped Polysilicon P or B
Diffusion
H. p-Channel VT Adjust B Ion Implant Ion Implant or
O. Doped SiO2 P or B
Diffusion
p-channel Transistor n-channel Transistor
N
O p-channel Transistor n-channel Transistor
M K L I J O
p+ LI oxide n+ N
M K L I J
p+ LI oxide n+
p– p– n– n– p+
n+ STI p+ p+ STI n+ n+ STI
n p p– p– n– n– p+
n+
F H p+
n+ STI p+ p+ STI n+ n+ STI
n-well E G p-well n
F
p
n++
D p++ n+ H p+
C n++
n-well E G p-well
p++
C D
B p– epitaxial layer p– 磊晶層
B
p– epitaxial layer
A p+ silicon substrate p+ 矽基板
A p+ silicon substrate
Semiconductor Manufacturing Technology Figure 17.1 Semiconductor Manufacturing Technology
by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang 7 by Michael Quirk and Julian Serda © 2001by Prentice Hall Figure 17.1 NCHU / EE / Prof. Fang-Hsing Wang 8
Ion Implant in Process Flow Diffusion
Wafer fabrication (front-end) • Diffusion Principles
Wafer start
– Three Steps
Dopant gas
Thin Films Polish
• Predeposition
• Drive-in
Unpatterned
wafer
• Activation
Completed wafer Diffusion Photo Etch – Dopant Movement Diffused
Photoresist mask
– Solid Solubility Oxide region Oxide
Test/Sort Ion – Lateral Diffusion N

Implant
Anneal after implant
• Diffusion Process p+ Silicon substrate
Hard mask (oxide or nitride)
– Wafer Cleaning
Used with permission from Lance Kinney, AMD – Dopant Sources Doped region in a silicon wafer
Figure 17.2
Dopant Diffusion in Silicon Solid Solubility Limits in Silicon at 1100˚C

Si Si 摻質
Dopant
Si Si Si
Si Si
Si Si
Si Si
Si
Vacancy空位
Vacancy Dopant Solubility Limit (atoms/cm3)
Si
Si Si
Si Si
Si Si
Si Si
Si
Arsenic (As) 1.7 x 1021
Si
Si Si
Si Si
Si Si
Si Si
Si Si
Si
Phosphorus (P) 1.1 x 1021
b) Substitutional diffusion
a) a)矽晶格結構
Silicon lattice structure b)取代擴散
Substitutional diffusion
Boron (B) 2.2 x 1020
Dopant
間隙位置中之摻質 in
interstitial site Antimony (Sb) 5.0 x 1019
Si
Si Si
Si Si
Si Si Si
Si Si Si Si
Aluminum (Al) 1.8 x 1019
Si
Si Si
Si Displaced
位於間隙位置之 Si
Si Si
Si Si
Si
Si
Si silicon
被取代的矽原子 atom in
Si
Si Si
Si Si
Si interstitial site Si
Si Si
Si Si
Si
c) Mechanical
c) Mechanical interstitial displacement d)d)
interstitial Interstitial diffusion
Interstitial diffusion
displacement 間隙擴散
Table 17.3
Figure 17.4
Diffusion Process Typical Dopant Sources for Diffusion
正確執行擴散所需的8道步驟 Dopant Formula of Source Chemical Name
Eight Steps for Successful Diffusion:
1.程序鑑定測試以確保設備符合產品品質標準。 Arsenic (As) AsH3 Arsine (gas)
1. Run qualification test to ensure the tool meets production
quality criteria.
2.利用批次控制系統驗證晶圓特性。 Phosphorus (P) PH3 Phosphine (gas)
2. Verify wafer properties with a lot control system.
3.下載所需擴散參數的製程處方(recipe)。 Phosphorus (P) POCl3 Phosphorus oxychloride (liquid)
3. Download the process recipe with the desired diffusion Boron (B) B2H6 Diborane (gas)
4.設定爐管，包括溫度輪廓。
parameters. Boron (B) BF3 Boron tri-fluoride (gas)
4. Set up the furnace, including a temperature profile.
5.清潔晶圓並將晶圓浸入稀釋氫氟酸(HF)以移除原生氧化物。 Boron (B) BBr3 Boron tri-bromide (liquid)
5. Clean the wafers and dip in HF to remove native oxide.
6.執行預沉積(pre-deposition)：裝載晶圓於沉積爐管中並進行 Antimony (Sb) SbCl5 Antimony pentachloride (solid)
6. Perform predeposition: load wafers into the deposition furnace
摻質氧化物的沉積與擴散。
and diffuse the dopant.
7.執行驅入(drive-in)：增加(or維持)爐管溫度以進行驅入及活
7. Perform drive-in: increase furnace temperature to drive-in and 1st B2H6(gas)+3O2  B2O3(solid)+3H2O
化(activation)摻質(與Si鍵結)，繼之降溫與卸載出晶圓。
activate the dopant bonds, then unload the wafers.
2nd 2B2O3(solid)+3Si(solid)  4B(solid)+2SiO2(solid)
8. Measure, evaluate and record junction depth
8.測量、評估及記錄接面深度(junction and sheet
depth)與片電阻值。
resistivity.
SEMATECH “Diffusion Processes,” Furnace Processes and Related Topics, (Austin, TX: SEMATECH, 1994), P. 7.
Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology Table 17.4
Ion Implantation Controlling Dopant Concentration and

Depth
• Overview
High energy
– Controlling Dopant Concentration Low energy
High dose
Ion implanter Low dose Ion implanter
– Advantages of Ion Implant Fast scan speed Slow scan
speed
– Disadvantages of Ion Implant Dopant ions
• Ion Implant Parameters Beam scan Beam scan
– Dose xj
Mask Mask Mask Mask
Junction xj
– Range
depth
Silicon substrate Silicon substrate
http://courses.ee.psu.edu/ruzyllo/ionimplant/index.html a) Low dopant concentration (n–, p–) b) High dopant concentration (n+, p+)
and shallow junction (xj) and deep junction (xj)
Figure 17.5
by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang 15 by Michael Quirk and Julian Serda © 2001by Prentice Hall
NCHU / EE / Prof. Fang-Hsing Wang 16
General Schematic of an Ion Implanter Advantages of Ion Implantation
http://www.youtube.com/watch?v
(from Table 17.5)
=crLDt7KQuxc (Ion implanter)
1. Precise Control of Dopant Concentration
Ion source 2. Good Dopant Uniformity
Plasma 3. Good Control of Dopant Penetration Depth
Extraction assembly
Analyzing magnet 4. Produces a Pure Beam of Ions
Acceleration
Ion beam column
Process 5. Low Temperature Processing
chamber
Scanning 6. Ability to Implant Dopants Through Films
disk
7. No Solid Solubility Limit
F=qvB
Photograph courtesy of Varian Semiconductor, VIISion 80 Source/Terminal side

Semiconductor Manufacturing Technology Figure 17.6 Semiconductor Manufacturing Technology Table 17.5
Disadvantages of Ion Implantation Classes of Implanters

Class of Implanter
Description and Applications
System

• Ion bombardment damage Medium Current

Highly pure beam currents <10 mA.
Beam energy is usually < 180 keV.
 Most often the ion beam is stationary and the wafer is scanned.
 Specialized applications of punchthrough stops.
• Complex equipment (expensive)  Generate beam currents > 10 mA and up to 25 mA for high dose
implants.
 Beam energy is usually <120 keV.
• Radiation hazard (dangerous) High Current  Most often the wafer is stationary and the ion beam does the
scanning.
 Ultralow-energy beams (<4keV down to 200 eV) for implanting
ultrashallow source/drain junctions.
 Beam energy exceeds 200 keV up to several MeV.
High Energy  Place dopants beneath a trench or thick oxide layer.
 Able to form retrograde wells and buried layers.
Oxygen Ion Implanters  Class of high current systems used to implant oxygen in silicon-
on-insulator (SOI) applications.
Table 17.6
Ion Implant Parameters Range and Projected Range of Dopant
Ion
• Dose (Q) • Range Incident ion beam
– ions/cm2 – Distance an ion travels in Si
It – Depending on ion mass and
Q Range
enA energy
– I : beam current (A) KE  nV Silicon substrate
Rp
– t : time (s) – KE : energy (eV) Stopping point for a Rp dopant
– n : charge/ion – n : charge/ion single ion distribution
– A : implant area (cm2) – V : voltage (V)
R┴
Figure 17.7
Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology NCHU / EE / Prof. Fang-Hsing Wang
by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang 21 by Michael Quirk and Julian Serda © 2001by Prentice Hall 22
Projected Range Chart Energy Loss of an Implanted Dopant Atom

1.0 Electronic stopping vs. Nuclear stopping
Implanting
Projected Range, Rp (m)
into Silicon
~0.3 m Energetic dopant ion
B P Lighter ion,
~0.12 m As Deeper Rp. Electronic collision Silicon crystal lattice
0.1 Si Si Si Si Si Si
Sb
~0.05 m X-rays
Si Si Si Si Si Si
Atomic collision
Si Si Si Si Si
0.01 Displaced Si atom
10 100 1,000 Si
Si Si Si Si Si Si
Implantation Energy (keV)
Redrawn from B.El-Kareh, Fundamentals of Semiconductor Processing Technologies,
(Boston: Kluwer, 1995), p. 388 Figure 17.9
Crystal Damage Due to Light and Heavy Ion Implanters
Ions
• Ion Source
Light ion impact Heavy ion impact • Extraction and Ion Analyzer
• Acceleration Column
shallow • Scanning System
• Process Chamber
deep c-Si c-Si • Annealing
• Channeling
• Particles
https://www.gns.cri.nz/Home/Our-Science/Environment-and-
Materials/Advanced-Materials/Ion-Implantation-Equipment
Interaction of ion Source and Extraction Assemblies Mass Analyzing Magnet

Ion Source Extraction Assembly
N Grounded electrode
S
Suppression electrode
-
+ +
Arc chamber - Ion source
-
+ +
- Extraction
+ + -
Source
magnet + +Ion beam
-
To PA
assembly
+ -
supply -
+
+
+
-
- Analyzing magnet
+ -
+ + - Ion beam
N
Lighter ions
S 2.5 kV Mass/charge
Suppression
F=qvB
5V
Filament
120 V
Arc
60 kV
Extraction Terminal reference
Neutrals
(PA voltage) Heavy Graphite
ions
Used with permission from Applied Materials Technology, Precision Implanter 9500 Photograph courtesy of Varian Semiconductor, VIISion 80 analyzer side
Figure 17.13
Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology Figure 17.14
Acceleration Column Dose Versus Energy Map
1016 Present applications
Evolving applications Poly doping
Proximity
1017 gettering
Dose (atoms/cm2)
Electrode
+100 kV +80 kV +60 kV +40 kV +20 kV 0 kV Source/drain Damage
engineering
Ion beam 1015
Ion beam Buried
1014 Channel and drain layers
From To
analyzing process engineering
chamber 1013
magnet Vt adjust Retrograde
12 wells
+100 kV 10
100 M 100 M 100 M 100 M 100 M
Triple wells
1011
0.1 1 10 100 1000 10,000
Energy (keV)
Figure 17.15
Used with permission from Varian Semiconductor Equipment
Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology Figure 17.16
Linear Accelerator for High-Energy Space Charge Neutralization

Implanters
摻質離子 Secondary
Atomic mass 200 KeV ~ a few MeV electron
Dopant ion
analysis Linear accelerator Final energy +
magnet analysis magnet +
+
+
+
+
+
+
+
+
+
+
+
+
+
Wafer
+
Source Beam with space charge
neutralization具空間電荷中性化之
Scan disk beam blow-up because 離子束的橫切面
positively charged ions are Secondary electrons are generated when high-
unstable energy dopant ions strike a surface (aperture plates
束膨大之橫切面 or beam guide assembly)
Figure 17.17
Figure 17.18
Neutral Beam Trap Scanning System
Neutral ions are formed in the beam when a dopant ion gains an electron • Focused ion beam is small on the order of 1 cm2 for
by colliding with a residual gas molecular (because only 10-6 torr). medium implanter and 3 cm2 for high-current one. It must
be scanned to cover entire wafers.
Focussing Beam Neutral • Low- to medium-current implanters keep wafers stationary,
anode bending beam Grounded
electrode while high-current one keep the ion beam stationary.
Analyzing path collector
Magnet plate
1. Electrostatic scanning
Accelerator Ion beam Y-axis
deflection X-axis 2. Mechanical scanning
Source deflection Wafer
Neutral beam trap 3. Hybrid scanning
4. Parallel scanning
Used with permission from Varian Semiconductor Equipment
Figure 17.19
Electrostatic Ion Beam Scanning of Implant Shadowing

Wafer
High frequency Ion beam

Low frequency
Y-axis deflection X-axis deflection
Y-axis Resist Resist
deflection
Wafer
a) Mechanical scanning with b) Electrostatic scanning
no tilt with normal tilt
a)無傾斜之機械式掃描 b)具正常傾斜之靜電式掃描
X-axis • Disadv: particulate • Adv: no channeling, no
deflection Twist Tilt
contamination due to contamination, electrons and
mechanical assembly neutrals are eliminated.
• Disadv: shadowing effect
Figure 17.20 Figure 17.21
Mechanical Scanning of Implanted Wafers Hybrid scanning
Spillover cup • Wafers on disk are rotated to scan in y axis.
Ion beam Outer scan radius • Beam is electrostatic scanned in x axis.
掃描外徑 • For low- to medium-current system with a single wafer.
Implant area
(calculated) Inner scan radius Wafer cooling
掃描內徑 • Ion beam strikes wafers causing heating.
• For high-current implant • Wafer temperature should be less than 50 oC.
• Ion beam is fixed. • Gas cooling: helium on backside.
• Beam size: 1 x 3 cm2 • Elastomeric cooling: using elastomeric material on backside to
• Disk move and rotate transfer heat to metal platen.
• Disk >= 5 feet
•
•
Disk can be tilted
1000~1500 rpm
Wafer charging
• 8” wafers up to 25 • As ion beam strike wafers, positive ions accumulate in the
masking layer, causing wafer charging.
Used with permission from Varian Semiconductor Equipment, VIISion 80 Ion Implanter • Wafer charging lead to beam blow-up and surface oxide damage.
Figure 17.22
Electron Shower for Wafer Charging Control Plasma Flood to Control Wafer
Secondary electron target Charging
Neutralized
-Biased aperture Secondary atoms
electrons Ion beam
(<20eV) Wafer
+ +
++
+
+
+
+
+
+
Electron
+
Wafer scan
+ + emission
+
direction
+
+ + Chamber wall
+
Current
N N
+
+
+
+
-Biased (dose)
monitor
+
aperture
+
+Ion - electron Plasma
Primary electron flood
+
electrons recombination
Electron gun chamber
(>100eV) S S
Adapted from Eaton NV10 ion implanter, circa 1983
Argon gas inlet
Semiconductor Manufacturing Technology Figure 17.23 Semiconductor Manufacturing Technology Figure 17.24
End Station for Ion Implanter Wafer Handler for an Implant
Process Chamber
Implant Subsystem Wall
Source Subsystem
Operator
VIISion
interface
Video monitor
End Station
Wafer
cassette
loadlocks
Terminal Subsystem
Process Wafer handler
Chamber Scan disk
Photograph provided courtesy of International SEMATECH
Used with permission from Varian Semiconductor Equipment, VIISion 200 Ion Implanter
Photo 17.3 Figure 17.25
Faraday Cup Beam Current Annealing of Silicon Crystal

Measurement for Dose Control
Scanning disk with wafers
Before Annealing After Annealing
Sampling slit in Suppressor aperture
disk Faraday cup Ion Beam
Repaired Si lattice structure and
Ion beam activated dopant-silicon bonds
Current
integrator
Scanning a) Damaged Si lattice during b) Si lattice after annealing

direction implant
Redraawn from S. Ghandhi, VLSI Fabricaton Principles: Silicon and Gallium Arsenide, 2d ed.,
(New York: Wiley, 1994), p. 417
Silicon Lattice Viewed Along <110> Axis Ion Entrance Angle and Channeling
channel
<100> <110> <111>
Used with permission from Edgard Torres Designs
http://courses.ee.psu.edu/ruzyllo/ionimplant/index.html
Used with permission from Edgard Torres Designs
Figure 17.29
Implantation Damage from Ion Implant Trends in Process

Particulate Contamination Integration
Examples of Different Implant Processes
• Deep buried layers
Ion implanter • Retrograde wells
• Punchthrough stoppers
• Threshold voltage adjustment
Beam scan • Lightly doped drain (LDD)
• Source/drain implants
Mask Mask • Polysilicon gate
Particle creates a void • Trench capacitor
in implanted area Silicon Substrate • Ultra-shallow junctions
• Silicon on Insulator (SOI)

Buried Implanted Layer Retrograde Well
n-type dopant p-type dopant
n-well p-well
n-well p-well
n++ p++
p Epi layer Retrograde Well
p+ Buried layer p+ Buried layer
p+ Silicon substrate p+ Silicon substrate
Punchthrough Stop Implant for Threshold Voltage

Adjustment
n-type dopant p-type dopant n-type dopant p-type dopant
n-well p-well
n-well p-well
n+ p+ n- n p- p
n++ p++ n+ p+
n++ p++
Punchthrough Stop
p+ Silicon substrate p+ Silicon substrate
Source-Drain Formations Dopant Implant on Vertical Sidewalls
of Trench Capacitor
p-channel transistor n-channel transistor p+ S/D implant n+ S/D implant
p– LDD implant n– LDD implant
Poly gate
Spacer
oxide
Trench for
++++ ++++ ----- ----- ++++
++++
++++
++++
-----
- -- -- -- -
-----
-------- forming capacitor Tilted implant
Source Drain Source Drain ++++ ++++
Source Drain Source Drain
n-well p-well n-well p-well

p+ Silicon substrate p+ Silicon substrate n+
p+
1) p– and n– lightly-doped drain 2) p+ and n+ Source/drain
implants (performed in two implants (performed in two
separate operations) separate operations)
Ultra-Shallow Junctions CMOS Transistors with and without

SIMOX Buried Oxide Layer
Poly gate
n-well p-well n-well p-well

Epi layer Silicon substrate
Implanted silicon dioxide
Silicon substrate Silicon substrate
180 nm
a) Common CMOS wafer b) CMOS wafer with SIMOX
construction buried layer
54 nm arsenic implanted layer 20 Å gate oxide SIMOX: Separation by IMplanted OXygen)
Chapter 17 Review Review Questions
1. List the four common dopants and state
• Quality Measures 508 whether each is a p-type or n-type dopant.
• Troubleshooting 509 2. List and explain the three steps of diffusion.
• Summary 510 3. Describe projected range.
• Key Terms 511 4. Describe dose.
• Review Questions 512 5. Why do dopants need to be activate?
• Equipment Suppliers’ Web Sites 513
• References 513


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doping

Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology

Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology

Group VIA : Oxygen (O)

Test/Sort Ion – Lateral Diffusion N

Dopant Diffusion in Silicon Solid Solubility Limits in Silicon at 1100˚C

Ion Implantation Controlling Dopant Concentration and

• Ion Implant Parameters Beam scan Beam scan

Photograph courtesy of Varian Semiconductor, VIISion 80 Source/Terminal side

Disadvantages of Ion Implantation Classes of Implanters

Projected Range Chart Energy Loss of an Implanted Dopant Atom

Interaction of ion Source and Extraction Assemblies Mass Analyzing Magnet

Linear Accelerator for High-Energy Space Charge Neutralization

Electrostatic Ion Beam Scanning of Implant Shadowing

High frequency Ion beam

Faraday Cup Beam Current Annealing of Silicon Crystal

Scanning a) Damaged Si lattice during b) Si lattice after annealing

<100> <110> <111>

Used with permission from Edgard Torres Designs

Implantation Damage from Ion Implant Trends in Process

Semiconductor Manufacturing Technology Figure 17.30 Semiconductor Manufacturing Technology

n-type dopant p-type dopant

p+ Silicon substrate p+ Silicon substrate

Punchthrough Stop Implant for Threshold Voltage

p+ Buried layer p+ Buried layer

Ultra-Shallow Junctions CMOS Transistors with and without

n-well p-well n-well p-well

54 nm arsenic implanted layer 20 Å gate oxide SIMOX: Separation by IMplanted OXygen)

Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology

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