SSE Chap-15 Photo-Advanced Lithography50 - 4p

Objectives
固態工程 After studying the material in this chapter, you will be able to:
Solid State Engineering 1. Explain why and how a post exposure bake is done for conventional and
Chemically amplified DUV resist.
• 解釋傳統與化學倍增式DUV光阻為何與如何執行曝光後烘烤。
Chapter 15 2. Describe the negative and positive resist development process for
conventional and chemically amplified DUV resist.
Photolithography: Resist • 分別針對傳統與化學倍增式DUV光阻，描述其負與正光阻顯影製程。
Development and Advanced 3. List and discuss the two most common resist development methods and the
critical development parameters.
Lithography • 列出並討論兩種最常用到的光阻顯影方法及關鍵性顯影參數。
4. State why a hard bake is done after resist development.
• 說明為何光阻顯影後，需進行硬烤處理。
Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology

by Michael Quirk and Julian Serda © 2001by Prentice Hall by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang 2
Objectives Eight Basic Steps of Photolithography

Chapter
After studying the material in this chapter, you will be able to: Step
Covered
5. Explain the benefits of a post-develop inspection. 1. Vapor prime 13
• 解釋顯影後檢查所具有之優點。 2. Spin coat 13
6. List and describe the four different alternatives for advanced lithography, 3. Soft bake 13
including the challenges for introducing each alternative into production. 4. Alignment and exposure 14
• 敘述4種不同的先進微影替代技術，包含簡述每一技術在考量量產時所 5. Post-exposure bake 15
可能面對之挑戰。
6. Develop 15
7. Describe and give the benefit for the advanced resist process of top surface
7. Hard bake 15
imaging.
8. Develop inspect 15
• 描述有關頂層顯像術之先進光阻製程並舉出其優點所在。
Table 15.1
by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang 3 by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang 4
Post Exposure Bake
• Deep UV Exposure Bake Chemically Amplified Photoresist
– Temperature Uniformity
• 90~130℃ for 1~2 min.(PEB usually requires a higher temperature
than soft bake) Before PEB After PEB
• CD variation 5 nm/ ℃; 130℃ ± 0.1 ℃
– Thermal movement of photoresist molecules Exposed PR Exposed PR
Heat
– Rearrangement of the overexposed and underexposed PR + H+ + + H+
molecules
– Over-baking will cause polymerization and affects Protecting Groups Protecting Groups
photoresist development
– PEB Delay  T-top issue
• Conventional I-Line PEB
固態工程/NCHU,EE,F.H.Wang/Source:蕭宏的半導體製程技術投影片 6
by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang 5 by Michael Quirk and Julian Serda © 2001by Prentice Hall
Amine Contamination of DUV Resist Reduction of Standing Wave Effect

leading to “T-top” Formation Unexposed Exposed
Standing
A delay time ( from exposure to PEB) grater than a few minutes waves photoresist photoresist
permitted acid to neutralize due to amine contamination from air. PAC
PAC
PAC
PAC
PAC PAC
PAC
PAC
PAC
PAC PAC
Region of Neutralized PAC
PAC
PAC
PAC
PAC
PAC PAC
unexposed photoresist PAC
PAC PAC PAC
photoresist Resist T-topping PAC PAC

PAC PAC

PAC PAC PAC PAC PAC
PAC PAC PAC
PAC
PAC PAC PAC
PAC PAC
H+ PAG H+ (a) Exposure to UV light (b) Striations in resist

PAG
PAC PAC
H+ PAG H+ PAC
PAC
PAG Development PAC PAC

H+ PAC
PAG H+ PAC PAC
PAC
PAC
PAG PAC
H+
PAG
H+
amine PAC
PAC
PAC
PAC
PAC
H+ PAG H+
(c) PEB causes PAC diffusion (d) Result of PEB
Acid-catalyzed • For DUV CA photoresist, PEB provides the heat needed for acid
reaction of exposed diffusion and amplification
resist (post PEB)
• PEB smooth PR sidewall and improve resolution
Semiconductor Manufacturing Technology Figure 15.1 Semiconductor Manufacturing Technology Figure 15.2
Develop Photoresist Development Problems
• Negative Resist Resist Substrate
• Positive Resist
• Development Methods
X X X
• Resist Development Parameters 
Correct Severe
Under Incomplete
develop develop develop overdevelop
Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology Figure 15.3

Negative Resist Crosslinking Development of Positive Resist

Resist exposed to
UV light dissolves in the Unexposed
develop chemical. positive resist
Exposed resist
TMAH
Crosslinks Crosslinked
Unexposed resist resist
• Early developer solutions are an alkaline-water mixture of sodium hydroxide (NaOH) or

N-PR : Swelling and distortion of crosslinked exposed potassium hydroxide (KOH).
• The most common developer today for P-PR is TMAH (N(CH3)4+ OH−)(四甲基氫氧化銨).
resist due to absorption of developer solution. • 目前大部分的半導體製造廠都使用正型光阻劑。
Figure 15.4
Development Methods Continuous Spray Development
Spray
Vapor Resist Develop Edge-bead
Load Station Prime Coat -Rinse Removal Transfer Station
• Continuous Spray Development
• Puddle Development Wafer Transfer System
Vacuum chuck
To vacuum
pump Spindle
connected to
spin motor
Soft Cool Cool Hard
Bake Plate Plate Bake
(a) Wafer track system (b) Developer spray dispenser

Spin at 100-500 rpm

Puddle Resist Development Resist Development Parameters

Puddle
formation Developer
dispenser • Developer Temperature :15~25 ± 1 ℃
水坑形成
• Developer Time
• Developer Volume
(a) Puddle dispense (b) Spin-off excess developer • Normality : developer concentration
• Rinse : DI water
• Exhaust Flow
• Wafer Chuck
(c) DI H2O rinse (d) Spin dry
Semiconductor Manufacturing Technology Figure 15.7 Semiconductor Manufacturing Technology

Hard Bake Softened Resist Flow at High Temperature
• Characteristics of Hard Bake:
–Post-Development Exposure Photoresist
–Evaporates Residual Solvent in PR
–Hardens the Resist
–Improves Resist-to-Wafer Adhesion
–Prepares Resist for Subsequent Processing
–Higher Temperature (130 ℃ for P-PR and 150 ℃ for
N-PR) than Soft Bake, but not to Point Where Resist
Softens and Flows
• Resist Hardening with Deep UV : for DNQ-
Novolak resist)
Figure 15.8
Develop Inspect Automated Inspection Tool for Develop Inspect
‧目的在找尋是否有缺陷存在
• Post-Develop Inspection to Find Defects
‧在持續進行後續蝕刻或植入製程之前
• Find Defects before Etching or Implanting
‧有光阻圖案缺陷之晶圓被進行蝕刻或植入後即
• Prevents
成廢料 Scrap
• Characterizes the Photo Process by
‧顯影後檢查即用以來表示光處理後之特徵，進
而提供資料給微影生產部門以進行動作修正
Providing Feedback Regarding Quality of
the Lithography Process
‧顯影重作(rework)
• Develop Inspect Rework Flow
Photograph courtesy of Advanced Micro Devices, Leica Auto Inspection station

Photo 15.1
Develop Inspect Rework Flow I-line and DUV
• SiO2 strongly absorbs UV when  < 180 nm

UV light
Resist Mask
HMDS
• Silica lenses and masks can’t be used

1. Vapor prime 2. Spin coat 3. Soft bake 4. Align and expose 5. Post-exposure bake
• 157 nm F2 laser photolithography
O2 – Fused silica with low OH concentration, fluorine
doped silica, and calcium fluoride (CaF2),
Rejected wafers
Plasma – With phase-shift mask, even 35 nm is possible
Strip and clean 8. Develop inspect 7. Hard bake 6. Develop
• Further delay next generation lithography
Rework
Ion implant Passed wafers Etch
Figure 15.9 22
by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang 21 by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang
Advanced Photolithography Advanced Lithography

Photolithography Improvements
• Possible Next Generation Lithography
1. Reduction in wavelength of the UV light source.
1. Extreme UV (EUV)
2. Increase in numerical aperture.
2. SCALPEL (SCattering with Angular Limitation
3. Chemically amplified DUV resists Projection Electron beam Lithography)
4. Resolution enhancement techniques (e.g., phase-shift 3. Ion Projection Lithography (IPL)
masks and optical proximity correction).
4. X-Ray
5. Wafer planarization (chemical mechanical
planarization, or CMP) to reduce surface topography. • Below 70 10 nm
6. Advances in photolithography equipment (e.g., stepper
and step-and-scan).
• EUV and SCALPEL EUV+ are preferred
Semiconductor Manufacturing Technology Table 15.2 Semiconductor Manufacturing Technology

X-ray Spectrum Concept for Extreme Ultraviolet Lithography
It uses a laser-produced plasma source to produce ~13 nm UV light and print
<30 nm images. The source and equipment are in vacuum environment.
Step-and-scan 4×
Hard X-rays Soft X-rays UV Spectrum High power reflection reticle Multilayer
laser
coated
EUV DUV MUV
mirrors
EUV
0.1 nm 1 nm 10 nm 100 nm
¼ image
of reticle
Synchrotron Excimer laser Hg Plasma
source 準分子雷射 lamp
同步加速器汞 Target Step-and-scan
material Vacuum chamber wafer stage
Redrawn from International SEMATECH's Next Generation Lithography Workshop Brochure

Figure 15.13
Challenges of EUV Photolithography ASML的EUV曝光機

ASML的EUV光刻機使用40對蔡司鏡面構成光路，每個鏡面的反光率為70%。這也就
1. Precision optics will be difficult to achieve. 是說，EUV光束通過該系統中的每一對鏡面時都會減半，在經過40對鏡面反射後，只
有不到2%的光線能投射到晶元上。到達晶圓的光線越少，光刻所需的曝光時間就越長
2. Mirror reflectivities will be optimized. ，相應的生產成本也就越高。且EUV光源的光束必須足夠強，EUV光刻機價格超過1
億歐元，是DUV光刻機價格的二倍有餘，且使用EUV光刻機時會消耗1.5兆瓦的電力。
3. The short wavelength and penetration depths will require 原文網址：https://kknews.cc/digital/pgxzax2.html
top surface imaging resist or bi-layer resist with a very thin

top layer.
4. For alignment, total overlay budget is about 35 nm for 0.1
um design rules.
5. All equipment will be in a vacuum environment.

台積電EUV曝光技術 Concept of SCALPEL
(SCattering with Angular Limitation Projection Electron beam Lithography)
• 台積電在7nm上選擇求穩路線，沒有急於進入EUV。台積電先繼
續使用DUV光刻，利用沉浸式光刻和多重曝光等技術平滑進入 • Electron beam Lithography
(instead of light source) Electron beam
7nm時代，然後再轉換到EUV光刻。
• Multilayer membrane mask
• 台積電使用DUV光刻的第一代7nm FinFET已經在2017年Q2進入
試產。與10nm FinFET製程相比，7nm FinFET使晶片尺寸降低37
that absorbs few electrons. Step-and-scan
％，或在電路複雜度相同的情況下降低40％的功耗。
• E-beam passes through a high reticle stage
atomic number layer in the
• 在第二代7nm FinFET+製程上， 2017Q2開始用EUV光刻。針對 mask that scatters electrons for
EUV優化的布線密度帶來約10~20％的面積減少，在電路複雜度 a high contrast image at wafer Electrostatic
相同的情況下，相比7nm FinFET再降低10％的功耗。 plane. lens system
• 根據後藤弘茂分析，台積電7nm DUV的特徵尺寸
• Beam blur by space charge at (4:1 reduction)
high beam current.
介於台積電10nm FinFET和三星7nm EUV之間，
• Several exposure stripes need
Metal Pitch特徵尺寸40nm，Gate Pitch特徵尺寸不 stitched together per chip.
Step-and-scan
明確，但必定小於10nm時的66nm。 (need accurate overlay) wafer stage
• 原文網址：https://kknews.cc/digital/pgxzax2.html • 2002 ready Vacuum chamber
Ion Projection Lithography (IPL) Concept of X-ray Photomask

Gold plated chrome pattern X-
Ion source ray absorbers
• Using a mask (need Silicon wafer
鍍鉻金層之X射線吸收體
stitching image) or serially H or He ion beam Glass frame Window etched into
writing on PR with a finely Mask lower membrane
focused beam. 蝕刻到較底薄膜之窗口
• Using H or He ions
• Enhanced efficiency due to Electrostatic • for 10~100 nm Membrane 薄膜
large mass than electron lens system • Using soft X-ray
(4:1 reduction) • 1:1 mask
• Secondary electron Reference
backscattering limits the plate • Expensive (vs. Scanning X-rays are directed toward a
min. feature size. optical lithography) production wafer through a photomask
Step-and-
similar to this one.
• 50 nm ready scan wafer
X射線係透過類似如圖的光罩而直接掃向晶圓
stage
Vacuum chamber Redrawn from C. Y. Chang and S. M. Sze, ULSI Technology, edited by C. Y.
Chang and S. M. Sze (New York: McGraw-Hill 1996) p.314
Semiconductor Manufacturing Technology Figure 15.12 Semiconductor Manufacturing Technology Figure 15.14
Development Trends of Photoresist and Lithography
Next Generation Lithography
Negative photoresist 1970s 10 m Contact Printer
• Advanced Resist Processing (先進光阻製程)
Positive photoresist 1.2 m Scanning Aligner
1980s – Top-surface imaging (頂層顯像術)
(DNQ-Novolak) 1.0 m G-line Stepper
0.40 m I-line Stepper • PR is imaged only at its top surface.
PSM, OAI • DESIRE (Diffusion-Enhanced Silylated Resist, 擴散
Chemical amplification 1990s 0.35 m
DUV Stepper 增強的甲矽烷基化的光阻) Process
0.18 m DUV Step and Scan • Using silylation to selectively place a thin Si layer on
Improve Resolution a resist.
2000s 0. 13 m EUV Step and Scan
Advanced photoresist
top surface imaging 2010 90 nm
SCALPEL
IPL, X-ray
Semiconductor Manufacturing Technology Figure 15.15 Semiconductor Manufacturing Technology
Top Surface Imaging Recent Development to Improve Resolution

UV • Below the 157nm wavelength, the optical exposure systems
Exposed resist Exposed Crosslinked must change to all reflecting optics due to high levels of
absorption in refractive lens at shorter wavelengths.
Unexposed
resist K
R 1
(a) Normal exposure process (b) Post exposure bake NA
O2 plasma
develop
HMDS Silylated
exposed resist
Si Si
矽化後之已
曝光光阻
(c) Vapor phase silyation (d) Final developed pattern
氣相矽化
NCHU / EE / Prof. Fang-Hsing Wang
Semiconductor Manufacturing Technology Figure 15.16 Semiconductor Manufacturing Technology 36
by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang 35 by Michael Quirk and Julian Serda © 2001by Prentice Hall
To Improve Resolution Optical lithography reaching a limit
• K1 is a complex factor of several variables in the photo- K 1
lithography process such as the quality of the photoresist and R
the use of resolution enhancement techniques such as phase
NA
shift masks, off-axis illumination and optical proximity
K1=0.25, =193nm, NA=1 (air)  R = 48.3 nm
correction.
 While exposure wavelengths
have been falling and NA rising, K1=0.25, =193nm, NA=1.35 (water)  R = 35.7 nm
k1 has been falling as well, see
figure .
The practical lower limit for k1
is thought to be >0.25.
37
by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang 38
Immersion Lithography 台積電浸潤式曝光顯影技術邁入量產

• 鉅亨網記者葉文義／台北‧2006年2月22日
• Insert the “n>1” medium between the lens and the wafer • 台積電 (2330-TW) 表示，該公司浸潤式曝光顯影技術所產出的測
• Water has an index of refraction n =1.47 , absorption of <5% 試晶片，已符合量產所要求，已成功產出多批測試晶片，晶片缺
at working distances of up to 6 mm, is compatible with P.R. 陷最低的僅有 3個。此一結果超越目前世界上其他已發表的產出
and lens and in it’s ultrapure form is non-contaminating. 結果。浸潤式曝光顯影技術突破了目前這個世代 (193奈米)曝光
顯影機台的限制。
• 浸潤式曝光顯影技術係使用水或類似的清澈液體當作成像的介質
。在曝光機的鏡頭與晶片間加入水作為介質，能夠得到更高解析
度的光源，以便製造面積更小、密度更高的元件。使用液體介質
不免會產生一些挑戰，例如氣泡、水印、微粒子掉入、由微粒子
掉入引起成像缺陷或光阻液殘留等狀況。這些挑戰，透過台積電
研發的專有技術，已經獲得解決。測試結果顯示，許多12吋晶片
上的晶片缺陷數目少於 7個，缺陷密度為每平方公分 0.014。台積
電計劃於45奈米製程採用浸潤式曝光顯影技術。
39 40
by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang by Michael Quirk and Julian Serda © 2001by Prentice Hall NCHU / EE / Prof. Fang-Hsing Wang
雙重曝光技術護航 ArF浸潤式微影穩居主流雙重曝光技術
2008/9 王智弘
• 在雙重曝光技術與相關設備漸趨成熟的加持下，原本面臨物理極限的193
奈米浸潤式微影因而得以延伸應用至32奈米與22奈米製程節點，成為下一
世代微影製程的主流技術。
• http://www.mem.com.tw/article_content.asp?sn=0809010005
• https://www.youtube.com/watch?v=XI5Ypy77fVE
Multiple Patterning Enables Feature Shrink
Ref: http://www.mem.com.tw/article_content.asp?sn=0809010005

TSMC 2015年研究發展成果 TSMC 2015年研究發展成果

● 微影技術
● 10奈米製程技術民國一百零四年微影技術研發的重點在於10奈米及7奈米技術的開發。在10奈米方
相較於前幾世代製程技術，10奈米製程將顯著地降低功耗並維持相同的晶面，主要的重點是持續改善疊對控制與顯像穩健性來為10奈米技術的驗證做準備
片效能。民國一百零四年的研發著重於基礎製程制定、設計法則定樁、良。針對7奈米技術的開發，新的光阻材料及先進光罩技術已完成最佳化，進一步強
率提升、電晶體效能改善以及製程與產品之可靠性評估。主要客戶與矽智化浸潤式製程的顯影與設計準則微縮。除此之外，台積公司將引進最新世代的浸
財廠商已完成10奈米矽智財的驗證。10奈米FinFET製程技術，已於民國一潤式掃描曝光機，以滿足7奈米及更先進製程對於更緊密疊對控制與影像品質的要
求。
百零五年第一季開始客戶產品設計定案。
民國一百零四年，極紫外光（EUV）專案在雷射功率及穩定度上取得大幅的進展
。光源功率的穩定與改善得以加快先進技術的學習速度與製程開發。此外，極紫
● 7奈米製程技術外光光阻製程、光罩保護膜及相關的光罩基板也都展現顯著的進步，極紫外光技
相較於10奈米製程技術，7奈米製程顯著地改善晶片密度及降低功耗並維持術正逐步邁向全面研發及量產就緒以支援先進的製程技術。
相同的晶片效能。民國一百零四年的研發著重於基礎製程制定、良率提升 ● 光罩技術
、電晶體及導線效能改善以及可靠性評估。7奈米製程技術預計於民國一百光罩技術是先進微影技術中極為重要的一環．民國一百零四年，研發組織成功地
零五年持續進行全面開發，並於民國一百零六年進入試產。完成了10奈米光罩技術的開發，並正將此技術移轉至光罩生產部門。同時，研發
組織在極紫外光的光罩技術上亦取得了實質的進展，包括光罩基板缺陷的降低以
及次10奈米世代微影使用的EUV光罩製作。
Ref: http://www.tsmc.com.tw/download/ir/annualReports/2015/chinese/c_5_2.html
Ref: http://www.tsmc.com.tw/download/ir/annualReports/2015/chinese/c_5_2.html
Multiple Patterning Future IC Trend: 小晶片(Chiplet)
• Multiple patterning (or multi-patterning) is a class of • 傳統晶圓製造如今已走到7奈米以下先進製程，投片的成本至少5億美元，
technologies for manufacturing ICs, developed 出片時間長達4~5個月，代表晶片業者至少需要賣20億美元金額，賣到終
for photolithography to enhance the feature density. It is 端市場4億顆晶片以上，才有可能回收高昂的設計成本。
expected to be necessary for the upcoming 10 nm and 7 nm node • 放眼當下，除了智慧手機晶片此一巨量市場，並非所有玩家都能進入門檻
semiconductor processes and beyond. ，反觀IoT市場百花齊放，不必盲目追求摩爾定律微縮，靠著小晶片Die
Bank選取需要的晶片組合與IP矽智財。
• Chiplet會是後摩爾定律解方，透過先進封裝將小晶片整合在一起，透過一
個介面標準以較低的功耗與功率進行晶片單元間的傳輸溝通，形成一個系
統小宇宙。這或許可以解決當前分散在電路板上各晶片單元各自為政，也
特別適用在物聯網等多元與低功耗的應用領域，
• 半導體業者就說，由於先進製程已逼近物理極限，摩爾定律發展面臨諸多
瓶頸，Chiplet、先進封裝戰役將會是晶圓代工另一牽動勝負與提升獲利的
關鍵戰場，因此三星、台積電、英特爾(Intel)多年前就積極搶進布局。
Ref: https://en.wikipedia.org/wiki/Multiple_patterning

摩爾定律趨緩的好解方：小晶片 AMD全面採用chiplet小晶片技術而獲得了技術優勢
 這字是Intel和AMD在其2017年合作計劃中提出來的，2018隨即被納入DARPA的ERI
議題中，而現在已有產品依此概念設計出來了。 AMD從2019年起全面採用小晶片技術而獲得了技術優勢，也就是Zen2體系結構中採用的小晶片
 做chiplet的動機很簡單，是要在逐漸趨緩摩爾定律的大環境下，持續提升產品的性技術稱為Core Complex Die（CCD），使用7nm製程製造與CPU內核相對應的CCD，並以14nm製
能和價值。如果為了整合新功能模組入晶片而加大晶片面積，於最先進製程上製造外圍管芯。Chiplet這種方法降低了製造晶片所支援的零組件生產成本，而不僅僅針對7nm支援
造大晶片是很不划算的。而且晶片面積大了，由缺陷密度導致的良率損失也跟著的零組件。AMD通過將管芯與一種稱為Infinity Fabric On-Package（IFOP）的技術連接來解決管
增長。芯到管芯連接的性能損失。
 解決方法是讓最需要講求效能的部份在最先進製程製造，其它對效能要求沒這麼
高（譬如I/O）的模組、或者有專屬製程的產品如DRAM等則另外製造。因為個別 AMD 的 Zen2 架構處理器，在原來 MCM（Multi-Chip Module）多晶片模組設計再進一步，改
晶片變小了，因此以chiplet為名。這還有額外的好處，因為功能模組化，有些用 chiplets 小晶片設計。簡單來說就是將 CPU 核心與 I/O 核心分離，分別使用不同的製程技術
chiplet可以一用再用，甚至變成公共矽智權，大幅減少設計的時間和成本。，CPU使用的是台積電 7 奈米製程技術，I/O是格芯 14 / 12 奈米。
 實際的做法是多個chiplet安置於中介板(interposer)上，以封裝方式將數個chiplet做成未來可見的chiplet設
一個高效能的終端產品，重點是chiplet與chiplet間的聯線間不能犧牲太多性能。這計會整合進更多的功根據 AMD 在ISSCC公布成本分析，對比7奈米 Zen2 在不同核心配置下的成本狀況。在桌上型處
其實是異質整合的一種實施方式。能晶片，而其中介板理器的部分，如果將 16 核心 32 執行序的 Ryzen 3 代做為 100% 標準，那麼採用原生核心的 16
 Intel將這種多chiplet的平面封裝叫做EMIB（Embedded Multi-die Interconnected Bridge
的矽晶面積更大，包核心處理器的成本將超過 2，也就是至少是兩倍的成本。而如果是 EPYC 伺服器處理器，則核心
）。Intel還另外有花樣，叫Foveros，基本上是向上、下方向堆疊晶片。而將兩種含許多互連和路由，數越多，成本優勢就越明顯。其中以 64 核心的 7 奈米製程 Ryzen 為標準，則 48 核心的成本就
概念合併的—就是上下晶片堆疊、左右晶片交互聯通—的叫co-EMIB，當然圖的是是為主動式中介板。是 0.9，而原生 48 核設計的成本至少是 1.9，也就是同樣幾乎為兩倍的成本。
兼二者之利。如果要將之想像成實境，可以用吉隆坡的Petronas Towers：聳立的高 Intel
塔之間，還有聯絡的空橋。垂直的連繫靠矽穿孔（Through Silicon Via；TSV），就小晶片技術的主要用於邏輯晶片製程轉移放緩下來，降低每一次製程縮減所需要的成本和開發
是在堆疊的晶片上垂直蝕刻穿孔相連接。Intel的做法還稍有不同，矽穿孔特別大時間。它僅在最新製程中引入必要的零組件，而在舊式製程製造時對不必要的零件則藉由小晶
，電阻小，讓各層晶片有充足的電流可用。
片技術進行連接，從而實現高效能。由此可見，展望未來，在架構設計、後端和封裝流程的重
 AMD第一個用chiplet概念設計的產品，叫Zen2(又名Ryzen3000)。這是一個用3個要性，將比前端流程的開發更為重要。
chiplet封裝的產品，兩個用7nm製作、8核的CPU，共用一個14nm製作的I/O。而未
來EPYC則將包含多個Zen2模組，理論上它還可以支持8個DDR DRAM的介面。看
，這就是每個大廠魂牽夢縈的高效能計算（HPC）晶片！
https://www.digitimes.com.tw/col/article.asp?id=1068
Chapter 15 Review Review Questions
1. Why is a PEB done for CA DUV resist?
• Quality Measures 429
• Troubleshooting 431
2. Why is Positive resist the most
commonly used resist?
• Summary 432
• Key Terms 433 3. Why is hard bake done?
• Review Questions 433 4. Explain EUV?
• Equipment Suppliers’ Web Sites 433
• References 434


SSE Chap-15 Photo-Advanced Lithography50 - 4p

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Objectives

Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology

Objectives Eight Basic Steps of Photolithography

Amine Contamination of DUV Resist Reduction of Standing Wave Effect

photoresist Resist T-topping PAC PAC

H+ PAG H+ (a) Exposure to UV light (b) Striations in resist

PAG Development PAC PAC

• Negative Resist Resist Substrate

Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology Figure 15.3

Negative Resist Crosslinking Development of Positive Resist

• Early developer solutions are an alkaline-water mixture of sodium hydroxide (NaOH) or

• Puddle Development Wafer Transfer System

(a) Wafer track system (b) Developer spray dispenser

Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology Figure 15.6

Puddle Resist Development Resist Development Parameters

Semiconductor Manufacturing Technology Figure 15.7 Semiconductor Manufacturing Technology

Develop Inspect Automated Inspection Tool for Develop Inspect

Photograph courtesy of Advanced Micro Devices, Leica Auto Inspection station

• SiO2 strongly absorbs UV when  < 180 nm

• Silica lenses and masks can’t be used

Advanced Photolithography Advanced Lithography

Semiconductor Manufacturing Technology Table 15.2 Semiconductor Manufacturing Technology

Redrawn from International SEMATECH's Next Generation Lithography Workshop Brochure

Challenges of EUV Photolithography ASML的EUV曝光機

top surface imaging resist or bi-layer resist with a very thin

Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology

Ion Projection Lithography (IPL) Concept of X-ray Photomask

Top Surface Imaging Recent Development to Improve Resolution

Immersion Lithography 台積電浸潤式曝光顯影技術邁入量產

Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology

TSMC 2015年研究發展成果 TSMC 2015年研究發展成果

Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology

Semiconductor Manufacturing Technology Semiconductor Manufacturing Technology

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