TUTORIAL SCHEDULE (11.02.

2021)

Session-1 Session-2
09.00 AM – 09.25
Joining the Meeting Hall Joining the Meeting Hall
AM
Surviving the electronics revolution requires a digital strategy - Mr.Pavan
Fundamentals of RF/Analog Device Modelling – RLC by Mr. Praveen Paul, RF &
Kumar Nanduri, Senior Application Engineer,Mentor Graphics
Analog Mixed Signal Compact Modeling Engineer, GLOBALFOUNDRIES.
Session Incharges: Dr. Jagannadha Naidu & Dr.Rajeev Pankaj
https://vit-ac-in.zoom.us/j/98789954771?
https://vit-ac-in.zoom.us/j/92284598268?
09.30 AM –11.00 pwd=SjcrVTcrNzRhdFREYlE0RXRMdnRSdz09
pwd=ZDhQZnpNV0RSNHR0ZUJLVzFWRzFQQT09
AM Meeting ID: 987 8995 4771
Meeting ID: 922 8459 8268
Passcode: 531156
Passcode: 352514
Shorten URL: https://tinyurl.com/icmdcstut01
Shorten URL: https://tinyurl.com/icmdcstut02

11.00 AM – 11.30 Break

AM
Fundamentals of RF/Analog Device Modelling – RLC - Mr. Varuna AB, Design Surviving the electronics revolution requires a digital strategy - Mr.Pavan
Enablement group, GLOBALFOUNDRIES Kumar Nanduri, Senior Application Engineer,Mentor Graphics
Session Incharges Dr.P.Jayakrishnan and Dr Dhanabal R Session Incharges: Dr. Jagannadha Naidu & Dr.Rajeev Pankaj
https://vit-ac-in.zoom.us/j/98789954771?
pwd=SjcrVTcrNzRhdFREYlE0RXRMdnRSdz09 https://vit-ac-in.zoom.us/j/92284598268?
11.30 AM – 1.00 PM
Meeting ID: 987 8995 4771 pwd=ZDhQZnpNV0RSNHR0ZUJLVzFWRzFQQT09
Passcode: 531156 Meeting ID: 922 8459 8268
Shorten URL: https://tinyurl.com/icmdcstut01 Passcode: 352514
Shorten URL: https://tinyurl.com/icmdcstut02

01.00 PM – 2.00 PM
LUNCH

Industry Partner
 Testing of electronic circuits and chips using DFT Methodologies with
Introduction to Intel FPGAs and FPGA Accelerators - Mr. Padmanaban
Tessent DFT solution – Mr. Jai Sehgal, Corporate Application Engineer,
Kalyanaraman,FPGA University Outreach Program Specialist , Intel’s
Siemens EDA
Programmable Solutions Group
business
Session Incharges: Dr.P.Jayakrishnan and Dr Dhanabal R
Session Incharges: Dr. Jagannadha Naidu & Dr.Rajeev Pankaj
https://vit-ac-in.zoom.us/j/98789954771?
2.00 PM – 3.30 PM https://vit-ac-in.zoom.us/j/92284598268?
pwd=SjcrVTcrNzRhdFREYlE0RXRMdnRSdz09
pwd=ZDhQZnpNV0RSNHR0ZUJLVzFWRzFQQT09
Meeting ID: 987 8995 4771
Meeting ID: 922 8459 8268
Passcode: 531156
Passcode: 352514
Shorten URL: https://tinyurl.com/icmdcstut01
Shorten URL: https://tinyurl.com/icmdcstut02

3.30 PM – 4.00 PM Break

Testing of electronic circuits and chips using DFT Methodologies with
Introduction to Intel FPGAs and FPGA Accelerators - Mr. Padmanaban Tessent DFT solution – Mr. Jai Sehgal, Corporate Application Engineer,
Kalyanaraman,FPGA University Outreach Program Specialist , Intel’s Siemens EDA business
Programmable Solutions Group Session Incharges: Dr. Jagannadha Naidu & Dr.Rajeev Pankaj
https://vit-ac-in.zoom.us/j/98789954771?
4.00 PM – 5.30 PM pwd=SjcrVTcrNzRhdFREYlE0RXRMdnRSdz09 https://vit-ac-in.zoom.us/j/92284598268?
Meeting ID: 987 8995 4771 pwd=ZDhQZnpNV0RSNHR0ZUJLVzFWRzFQQT09
Passcode: 531156 Meeting ID: 922 8459 8268
Shorten URL: https://tinyurl.com/icmdcstut01 Passcode: 352514
Shorten URL: https://tinyurl.com/icmdcstut02

Technical Query Contact:

For Session -1 : Dr. M. Aarthy (9952501667) / Dr.R.Sanjay (9487202626)
For Sesssion -2 : Dr.Payaline (7200577872) / Dr.Antony Glittas (9894260869)

Industry Partner