UNIVERSITY OF LIMERICK

OLLSCOIL LUIMNIGH

COLLEGE OF INFORMATICS & ELECTRONICS

DEPARTMENT OF ELECTRONIC & COMPUTER

ENGINEERING

MODULE CODE: ET4508/ED5532

MODULE TITLE: Computer Systems Architecture

SEMESTER: Autumn 2001

DURATION OF EXAM: 2 ½ Hours

LECTURER: Ciaran MacNamee

INSTRUCTIONS TO CANDIDATES:
Answer 4 questions. All questions carry equal marks.
This exam represents 70% of the total module assessment.
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1.
(a) What are the main differences between CISC and RISC approaches to microprocessor design?
What factors make RISC approaches more suitable for modern designs?

The following code fragment is to be run on a 5-stage pipelined RISC microprocessor.

Mov reg1, reg2

Add reg3, reg1

i. Show the problems that could be expected when this code is being executed.
ii. How can these problems be resolved?
iii. If similar code were to be executed on a Pentium, what factors would influence the choice
of ways of solving the problem? (15 Marks)

(b) The programmer’s model of Intel IA-32 architecture microprocessors is shown below:

Instruction Pointer EFLAG Register

31 16 15 0 31 16 15 E0

EIP IP EFLAG FLAG

General-Purpose Registers Segment Registers

15 0
31 16 15 8 7 0

Figure 1: IA-32 Registers

(Programmers Model)

Fill in the Names of the missing registers and explain how the use of the segment registers differs in
Real and Protected Modes. (10 Marks)

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2. Answer either Part I or Part II.

Q2, Part I

(a) Draw a block diagram to show the structure of either an Intel D815BN or D810E2CB Desktop
Board (Motherboard). (10 Marks)

(b) Describe the Intel Hub Architecture used in this system. (10 Marks)

(c) Describe how you would upgrade the BIOS in this system. Which Chipset Component contains
the BIOS code? (5 Marks)

Q2, Part II

(a) Describe the technology used in the Transmeta Crusoe VLIW processor. (10 Marks)

(b) Show how the code morphing technique used in Crusoe processor result in reduced microprocessor
die-size and lower power consumption. What are the effects of code morphing on the processor’s
performance? (8 Marks)

(d) How does the Transmeta Crusoe processor handle exceptions? Why is this important?
(7 Marks)

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3.
(a) Under what circumstances can a Pentium’s superscalar pipeline meet its performance objective of
completing execution of two instructions per clock cycle? (5 Marks)

(b) Show how the Pentium’s Integer and floating point pipelines interact and outline any restrictions
on the pipeline operation arising from the integer/floating point pipeline structure. Use sketches to
illustrate your answer. (5 Marks)

(c) Explain why the Pentium retains a microcode ROM. (5 Marks)

(d) Compare the instruction decode mechanism used in Pentium and P6 Family processors. How does
the P6 Family achieve faster instruction throughput? (5 Marks)

(e) P6 Family processors have 40 internal registers. Show how these registers are used to support
Dynamic Instruction Execution. (5 Marks)

4.
(a) Describe the function of a cache memory in a high performance computer system.
(5 Marks)
(b) Explain the difference between a write-through strategy and a write-back strategy. Which strategy
offers the better performance?
(5 Marks)
(c) What is the function of the MESI protocol? Explain the meaning of each of the 4 states used in the
MESI protocol. (5 Marks)
(d) Two processors, A and B, each have an on-chip cache, and share access to a common main
memory. A cache line in Processor A is in the M state as shown in the diagram below. What will
happen if processor B attempts to read from an address in main memory that is corresponds to an
address in the M-state cache line? Use sketches to illustrate the sequence of events that follows.
(10 Marks)

Processor A with a
Modified Cache Line

A B

CPU + CPU +
Registers 3 Registers

Cache 2 3 Cache

Modified Invalid

Fig. 2: Modified Cache

Line in a 2 processor Main
environment Memory

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5

(a) What are the advantages that the PCI bus has over earlier PC bus systems? (5 Marks)

(b) Draw a block diagram of a PCI-bus based Personal Computer Motherboard. Assume that the
board supports AGP. (5 Marks)

(c) Using the diagram below, explain how a 33MHz PCI bus can achieve a maximum bandwidth of
133Mbyte/s. (5 Marks)

(d) Explain the functions of the C/BEX# signals in Fig 3 below. (5 Marks)

(e) How would a target PCI device cause wait states to be inserted in the data transfer.
(5 Marks)

T0 T1 T2 T3 T4 T5 T6

PCICLK

FRAME#

AD Bus Address Data0 Data1 Data2 Data3

C/BEx# Command BEX# BEX# BEX# BEX#

IRDY#

TRDY#

DEVSEL#

Fig. 3. PCI Burst Mode Data Transfer: No waits

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(a) Distinguish between asynchronous and isochronous methods of data transfer. (3 Marks)

(b) What data rates are supported by USB Ver 2.0? (3 Marks)

(c) What types of data transfer are supported by USB? Give examples of applications for which each
of type of data transfer is best suited. (4 Marks)

(d) Consider the following system: a PC with one USB port, a Keyboard hub with one upstream and
two downstream USB ports, mouse with one USB port, a scanner with one upstream USB port, a
still camera with a single USB port and a USB hub with one upstream and two downstream USB
ports. Use a diagram to show how the peripherals can be connected in a tiered star configuration.
(5 Marks)

(e) Sketch the three layers of the USB model, showing how layers from the host and device side
communicate with each other. (5 Marks)

(f) What is meant by a USB endpoint and a USB pipe? Show how these abstractions relate to the
layers of the USB model. (5 Marks)

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