Experiment-1

Aim: To write VHDL code for basics logic Gate circuits AND, OR, NOT and its test bench for
verification, observe the waveforms and synthesize the code with technological library with given
Constraints.
Apparatus: Modelsim PE Student Edition 10.4 Software.
Theory: Logic gates are the basic components in digital electronics. They are used to create digital
circuits and even complex integrated circuits. For example, complex integrated circuits may bring
already a complete circuit ready to be used – microprocessors and microcontrollers are the best
example – but inside them they were projected using several logic gates.
AND Logic Gate:
The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high.
A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted
i.e. AB.

Figure 1.1: Symbol of AND gate.

Table-1: 2 input AND gate truth table

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VHDL Code for AND Logic:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY AND_LOGIC IS
PORT(X: IN STD_LOGIC; Y: IN STD_LOGIC; Z: OUT STD_LOGIC);
END AND_LOGIC;
ARCHITECTURE BEHAVIORAL OF AND_LOGIC IS
BEGIN
PROCESS(X,Y)
BEGIN
IF(X = '1' AND Y = '1')
THEN
Z <= '1';
ELSE
Z <= '0';
END IF;
END PROCESS;
END BEHAVIORAL;

Snapshots of VHDL code of AND gate:

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OR Logic Gate:
The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high.
A plus (+) is used to show the AND operation i.e. A+B.

Figure 1.2. Symbol of AND gate.

Table 1.2. 2 input OR gate truth table

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VHDL Code for OR Logic:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY OR_LOGIC IS
PORT(X: IN STD_LOGIC; Y: IN STD_LOGIC; Z: OUT STD_LOGIC);
END OR_LOGIC;
ARCHITECTURE BEHAVIORAL OF OR_LOGIC IS
BEGIN
PROCESS(X,Y)
BEGIN
IF(X = '0' AND Y = '0')
THEN
Z <= '0';
ELSE
Z <= '1';
END IF;
END PROCESS;
END BEHAVIORAL;
Snapshots of VHDL code of OR gate:

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NOT Logic Gate:
The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is
also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is
also shown as A', or A with a bar over the top, as shown at the outputs.

Figure 1.3. Symbol of AND gate.

Table 1.3. NOT gate truth table

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VHDL Code for NOT Gate:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NOT_LOGIC IS
PORT(X: IN STD_LOGIC; Z: OUT STD_LOGIC);
END NOT_LOGIC;
ARCHITECTURE BEHAVIORAL OF NOT_LOGIC IS
BEGIN
PROCESS(X)
BEGIN
IF(X = '1')
THEN
Z <= '0';
ELSE
Z <= '1';
END IF;
END PROCESS;
END BEHAVIORAL;

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Results: VHDL code for the AND, OR, NOT gate circuits has written, observed the waveforms and
the codes synthesized with the technological libraries and verified.