Standard Cell based Memory Compiler for
Near/Sub-threshold Operation
Jinbo Zhou Kamlesh Singh
Innatera Nanosystems BV Department of Electrical Engineering,
Delft, The Netherlands Electronic Systems
Email: jinbo.zhou@innatera.com Eindhoven University of Technology
Eindhoven, The Netherlands
Email: k.k.singh@tue.nl
Abstract—Voltage scaling to near/sub-threshold region is com-
monly used to achieve energy-efficient operation in digital cir-
cuits. However, the voltage-scaling potential of traditional 6T
SRAM memories is limited by reliability problems. For small size
memories, designers tend to a use latch/flip-flop based register file
which brings relatively high area overhead, high delay penalty,
and power overhead. In this work, a standard-cell based memory
(SCM) compiler is presented to automatically generate a 12T
OAI based SCM for multiple CMOS technologies operating in
near/sub-threshold region. The SCM compiler utilizes Python-
MyHDL for RTL and constraint generation. The timing and
floor-plan constraints are generated based on user specified
technology, memory size, and memory shape inputs. The power,
area, energy per access, read delay, and write delays are evaluated
for the generated memories of different sizes and shapes. The
proposed 12T OAI based SCM achieves average speed-up of
28%/39% in write delay and average speed-up of 25%/19% in
read delay when compared to D-latch/flip-flop based memories
in a 28-nm FDSOI technology. Furthermore, 41% reduction in
energy per access and 33% area saving are obtained, compared to
a recently published SCM design in 40-nm CMOS technology [1].
Keywords:– RAM, memory compiler, standard cell, syn-
thesis, CMOS.
I. INTRODUCTION
Voltages scaling to near/sub-threshold region is a prevalent
approach to achieve ultra-low power/energy for portable de-
vices. The conventional 6T SRAM bitcells do not operate
reliably at low voltages due to static noise margin (SNM)
degradation [2]. To deal with the bitcell reliability issue,
various special designs with 8T, 9T or 10T bitcell for SRAMs
are proposed for near/sub-threshold voltages [2]–[4].
The larger on-chip memories (> 8kb) are generally designed
by using SRAM macrocells [1], which require extensive modi-
fications to operate reliably in the sub-threshold voltage range.
However, the peripheral circuitry in SRAMs typically cause
area overhead especially for smaller memories. The small on-
chip memories, such as registers and register files, are typically
based on latches or flip-flops [5] for which the area and delay
overhead is relatively high. Therefore, there is a shift towards
This work was performed at Eindhoven University of Technology, prior to
Jinbo Zhou’s affiliation with Innatera Nanosystems BV.
978-1-7281-6044-3/20/$31.00 ©2020 IEEE
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Jos Huisken
Department of Electrical Engineering,
Electronic Systems
Eindhoven University of Technology
Eindhoven, The Netherlands
Email: j.a.huisken@tue.nl
standard cell based memories (SCMs) for small size memory
(< 8kb) blocks [1], [6], [7].
The advantage of SCMs over foundry-provided SRAMs
macrocell is the ease of portability over different technologies.
The SRAM macrocells must be recreated for new technologies
as opposed to the SCMs which are described in technol-
ogy independent hardware description languages. For smaller
memories the SCMs are relatively more efficiency as compared
to SRAMs in terms of area, delay, and power [1]. In literature,
several representative SCM designs for sub-threshold opera-
tion are already developed [1], [8], [9]. In [9], a D-latch based
SCM using clock-gates for writing and glitch-free multiplexers
for reading is implemented and compared to 6T SRAMs in 65-
nm CMOS technology for sub-threshold operations. In [1], an
Or-And-Invert (OAI) and And-Or-Invert (AOI) based SCM is
presented. However, the placement and routing of the bitcell
array is done manually in order to avoid timing issues in
physical design. This approach results in relatively slow read
circuitry and high design effort.
In this paper, an OAI based standard cell memory is
proposed. To the best of our knowledge, this is the first work
proposing a complete automated flow to generate different size
and shape of OAI based SCMs. The main contributions of this
work are as follows:
• Design of a technology-independent SCM compiler with
a fully integrated automatic EDA design tool flow to
generate different size and shape of OAI based SCMs.
• Automatic synthesis of memory array along with pre-
placement strategy for bitcells, results in improved read
access delay, write delay and power consumption.
• Comprehensive performances analysis of read delay,
write delay, power consumption, and area for the pro-
posed SCMs, latch and flip-flop based SCMs.
The paper is organized as follows. In Section II, the structure
of the bitcell and memory array are illustrated. Section III
describes the architecture of the SCM compiler. Comparisons
and analysis of our proposed SCM and latch/flip-flop based
SCMs are presented in Section IV, followed by a conclusion
in Section V.
 data per word. At any time only a single WWL should be
active low. In this example, for write operation two groups of
WBR and WBL are set inverse of each other, the rest of WWL
kept high. This ensures one word of 2 bits can be written.
In the case of read only one RWL is activated, in this case
RWL1 = 1 in order to read bit positions 1 and 5.

Fig. 1: Original structure of bitcells.

II. P ROPOSED 12T OAI BASED SCM

The proposed SCM consists of OAI based bitcell. The
original structure of the bitcell at design stage of RTL netlist
is shown in Fig. 1. Each bitcell consists of a pair of cross-
coupled OAI gates for write operation and followed by either
an AOI (even bitcell) or an OAI (odd bitcell) gate for read
logic. The daisy-chained read decoder is used with one gate
Fig. 2: Architecture of SCM array.
delay per bit to obtain minimal delay for the read operation
and to save area. This results in even and odd bitcells. III. A RCHITECTURE OF THE SCM COMPILER
In the write mode, the write is possible when write word A. SCM compiler
line (WWLi ) is active low. The pair of cross-coupled OAI In the proposed SCM compiler the memory generator is
based bitcell is written with a value corresponding to write written in Python/MyHDL for generating the RTL description
bit lines WBLi and WBRi . In the data retention mode, either of the memory. As shown in Fig. 3, a variety of technologies
WWLi or both WBLi and WBRi must be active high. The with their PVT corners, parameters including address bits, data
active low value on WWLi and WBLi /WBRi at the same bits, and shape (aspect ratio) are taken as user inputs. As first
time must be avoided. In this case, glitches on the WWLi step the generator produces RTL netlist, timing constraints,
and WBLi /WBRi signals may cause parasitic writes, hence I/O pins placement and a YML file with various kinds of
this case needs special attention by setting appropriate timing technology information. In second step, a templates-driven
constraints. In the read mode, the state of the daisy-chain script generator produces scripts for synthesis and physical
input (RB0 ) is initialized to 0, so the consecutive states of design procedures and tools.
RB from RB0 to RBi is 0, 1, 0, 1, ... 0, 1. While reading The proposed SCM compiler also generates testbench
out bitcelli , the read word line (RWLi ) becomes active high, scripts for design validation at different stages of design
and the inverted read is achieved via alternating AOI and OAI flow. Any type of memory march test can be executed after
gates in the daisy-chain. As shown in Fig. 1, in original bitcell synthesis and physical design with sdf back-annotation to
each alternate OAI/AOI gate contains 6 transistors making a verify correctness.
bitcell of 18 transistors. After these preparation steps, using unix ”make”, all steps
In contrast to [1], in this proposed SCM design the alternate from synthsis up to physical design including functional
OAI/AOI gate for read decoder is typically optimized by validation using the march tests are executed.
logic synthesis. This turns the long daisy-chained read decoder
typically into a tree structure in gate level netlist. Since the
RTL synthesis tool is free to use different gates from the
standard cell library, the read decoder circuitry is optimized
to less number of gates as well as faster read access time.
The cross-coupled OAI gates comprising the 12T bitcell are
not touched by synthesis and place & route tools, constituting
the proposed 12T OAI based SCM. Furthermore, without any
customized design in the SCM, the logic gate-based bitcell
is flexible and portable to different technologies, sizes and
shapes.
The architecture of a 8-bit (2x4) memory array is shown in
Fig. 3: Design flow of SCM compiler.
Fig. 2. The SCM contains 4 words (2-bit address) with 2 bits

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 B. Synthesis
The proposed SCM compiler flow is verified for 28-nm
FDSOI technology and 40-nm bulk CMOS technology. For the
cross-coupled OAI gates, the combinational timing loop is cut
to enable a standard logic synthesis flow. The logic synthesis
of the SCM optimizes the daisy-chained read decoder of the
memory array to meet the timing requirements. In the SCM
proposed in [1], the OAI/AOI based bitcell array is designed
manually and only the periphery is synthesized, using 40-
nm CMOS technology. In order to compare with [1], a 64kb
(2048x32) SCM based memory is generated and synthesized
in 40-nm CMOS technology using LVT cells. Initial post-
synthesis comparison of total area and access energy per bit
for write operation is shown in Table I. The analysis shows Fig. 4: Layouts of SCMs with pre-placement and different aspect
that the proposed SCM achieves 41% lower energy per bit for ratios.
write access when compared to the SCM proposed in [1]. TABLE II. Comparison between with (W) and without (WO) pre-
placement at typical corner. VDD=0.4 V, T=25◦ C.
TABLE I. Post-synthesis comparison using 40-nm CMOS technology.
SCM 256 bits 256 bits 512 bits 512 bits
SCM 40-nm CMOS Area (mm2 ) Access 28-nm FDSOI A=5 D=8 A=3 D=32 A=5 D=16 A=4 D=32
energy per Write W 5.5 6.8 7.3 7.4
bit (pJ/bit) delay(ns) WO 6.7 7.7 8.2 7.6
Proposed OAI based SCM 0.2 92 Read W 13.7 15.8 17.5 14.9
delay(ns) WO 14.4 19.6 18.8 15.0
OAI/AOI based SCM in [1] 0.3 157
Consumed W 1.1 2.4 2.1 3.5
power (µW) WO 1.2 2.7 2.2 3.6
C. Place & Route
In this work, standard physical design flow with customized impacts especially on read delay and power consumption are
floor-planning using relative placement of the bitcell is used. observed when aspect ratios deviate from one. Therefore, it is
During floor-planning, all pairs of cross-coupled OAI gates advised to keep aspect ratio close to one.
are pre-placed relatively using the generated script. This pre- TABLE III. Comparison between different aspect ratio W/L at typical
placement is especially beneficial to maintain timing correct- corner. VDD=0.4 V, T=25◦ C.
ness for the broken timing path in the cross-coupled OAI gates.
SCM Aspect Write Read Power
Each pair of OAI gates are placed tightly together without 28-nm FDSOI ratio(W/L) delay(ns) delay(ns) (µW)
any space to keep the wire short. Several OAI gates form a 512 bits (32x16) 1.0 7.3 17.5 2.1
cluster, then all OAI cell clusters are distributed in rows and 2.0 8.7 19.0 2.1
0.5 9.0 21.0 2.2
columns. Small spaces are kept in between the clusters for the 2048 bits (64x32) 1.0 14.2 26.2 4.0
memory read and write decoder logic cells as shown in Fig. 4. 2.0 14.4 32.5 4.1
Main challenge is the density of bitcells in the memory array 0.5 13.5 30.7 4.1
increases with the sizes of SCM memory. The pre-placement
algorithm is flexible to adjust the size of bitcell clusters and IV. P ERFORMANCE EVALUATION
the spacing between the clusters. The floor-planning with pre- In this work, the Foundry-provided 8-track, low-threshold
placement for different aspect ratios are shown in Fig. 4. (LVT) standard cell library in a 28-nm FDSOI technology
1) Performances of SCMs with and without pre-placement: is used. The LVT standard-cell library can operate reliably
Comparison for power consumption, write, and read delay and efficiently at 0.4 V across all PVT corners. The Foundry-
are performed for SCMs with and without pre-placement for provided standard cell library is characterized for near/sub-
different address width (A) and word width (D) as shown in threshold operation at 0.4 V±10%, different corners and tem-
table II. The SCMs with pre-placement achieve up to 18% peratures. A comprehensive performance evaluation of the
speed-up for write delay and up to 19% speed-up for read proposed SCM compared to latch based and a flip-flop (FF)
delay as compared to non pre-placed SCMs. This indicates that based SCM is performed. Cadence RTL Compiler is used for
pre-placement is beneficial in providing better performance. logic synthesis while Cadence Innovus Digital Implementation
Additionally, for the same memory size, different address and System is used for the back-end physical design (placement
word widths also influence the performances. Wider memories and routing). The sign-off is performed at slow-slow (SS)
provide overall better energy efficiency, as expected. corner, 0.36 V and 0◦ C.
2) Performances of SCMs with different shapes (aspect For read-address, write-address and write-data, normal reg-
ratios): Some layouts with different aspect ratios are shown in ister setup and hold constraints are applied. The WWL decoder
Fig. 4. The read delays, write delays, and power consumption and WB DEMUX determine the write-access delay. Write-
for different aspect ratios are compared in Table III. Negative access timing arc starts at the write-address and write-data

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 TABLE IV. Comparison of OAI/LATCH/FF based SCMs at typical corner. VDD=0.4 V, T=25◦ C.
SCM Write delay (ns) Read delay (ns) Power consumption (µW) Area (µm2 )
size (bits) OAI LATCH FF OAI LATCH FF OAI LATCH FF OAI LATCH FF
16 3.3 5.6 5.7 6.6 19.6 13.3 0.2 0.2 0.1 97 89 108
32 3.4 5.8 6.6 8.6 21.3 12.7 0.3 0.2 0.3 162 136 162
64 3.6 6.0 7.7 10.9 22.5 14.0 0.4 0.3 0.5 280 238 305
128 4.8 7.6 7.9 12.6 27.9 16.2 0.9 0.8 1.1 517 396 538
256 5.5 7.8 8.7 13.7 29.4 18.3 1.1 1.1 2.4 843 739 1040
512 7.3 10.6 11.4 17.5 30.6 21.2 2.1 2.0 4.2 1612 1299 1937
1024 10.5 15.6 18.2 23.1 32.4 26.9 2.8 2.5 6.6 3477 2505 5244
2048 13.5 16.3 20.7 30.7 37.9 39.6 4.1 4.4 12.8 6067 4900 10366
4096 14.8 17.9 24.6 40.8 39.6 42.0 8.0 8.3 25.6 11937 9205 20572

(a) (b) (c)

Fig. 5: (a) Write delay, (b) read delay, and (c) power consumption of OAI/LATCH/FF based SCMs.

registers and endpoints are the cross-coupled OAI gates in
memory array. Read-access time is determined by the read
decoder, consequently read delay is defined from the read-
address through the output of bitcells to the register output.
Power consumption of the SCM is measured by running
memory march test. The post-layout netlist simulation with
sdf back-annotation is performed for power analysis.
Comparison of write delay, read delay, power consumption
and area for SCMs from size 16-bit to 4096-bit are listed
in Table IV. To observe the trends of delays and power
consumption, the results at typical corner, 0.4V, and 25◦ C
are plotted in Fig. 5a, 5b and 5c. The OAI based SCMs
are superior as compared to latch and flip-flop based SCMs
in most situations. The proposed OAI based SCM achieves
average 28% and 39% speed-up in write delay as compared
to latch and flip-flop based SCMs respectively. The speed-up in
read delay is 25% and 19% on average as compared to latch
and flip-flop based SCMs, respectively. Power consumption
for OAI and latch based SCM are almost equal. The flip-
flop standard cell consists of two latches, hence flip-flop based
SCMs consumes higher power.
V. C ONCLUSION
For a variety of SCMs with different sizes and aspect
ratios, a technology-independent SCM compiler is proposed
to support fully automatic design flow. Experimental results
show that the proposed OAI based SCMs are more area
and energy efficient due to automatic optimization during
synthesis. OAI based SCMs outperforms the latch/flip-flop
based SCM for write and read delay. The evaluation also shows
the superiority for power consumption and area compared
to flip-flop based SCMs. This essentially indicates that the
proposed SCM design is competitive for near/sub-threshold
operation. Furthermore, the SCM design still has potential to
become more area and energy efficient with proper transistor
sizing in the bitcell, while being supported by a full automatic
design flow.
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