Time

Dependent Dielectric Breakdown of SiN, SiBCN and SiOCN spacer dielectrics

A Q&A with Jim Stathis about “spacers” breakthrough presented at the 2017 IEEE International
Reliability Physics Symposium

Members of the IBM Research Semiconductor Technology team, based in Albany, NY,
presented five papers at IEEE’s International Reliability Physics Symposium that demonstrate
clear architecture and material progress toward 7nm semiconductors, and beyond. One such
paper, Time Dependent Dielectric Breakdown of SiN, SiBCN and SiOCN spacer dielectric,
presents a comprehensive comparison of several materials that are used for the insulator in the
space between the electrical contacts at the transistor level. These spacer dielectrics are some
of the thinnest insulators in the chips – tested at 10nm for a 22nm chip, and at about 6nm in a
7nm chip. Understanding how the lifetime of these materials depend on the chip operation
voltage is crucial.

James Stathis, Manager, Electrical Characterization and Reliability, IBM Research, stated in the
related announcement:

“At the 7nm node, parasitic capacitance is projected to increase to 85 percent of device
capacitance for the traditional Silicon Nitride (SiN) spacer. We need to find a material that has
lower dielectric constant than SiN and is compatible with CMOS integration. [Our paper
demonstrates that] Silicon-Boron-Carbon-Nitride (SiBCN) and Silicon-Oxygen-Carbon-Nitride
(SiOCN) meet these requirements.”

IBM has implemented SiBCN in 14nm node technology, and is testing it at 10nm and 7nm node
technology. SiBCN is a balanced approach to improving circuit performance and improving
yield. SiOCN is also being implemented in 7nm.

What past study of spacer dielectrics led to the paper?

James Stathis: We have worked for three years on spacer dielectrics, from tool and material
optimization, integration and device and reliability studies. For more about this earlier work, I
recommend reading “A Novel ALD SiBCN Low-k Spacer for Parasitic Capacitance Reduction in
FinFETs”, T.Yamashita et al., (34 authors), VLSI Technology Symposium 2015. p. T154 - T155,
DOI: 10.1109/VLSIT.2015.7223659.

What do you think stood out about ‘Time Dependent Dielectric Breakdown of SiN, SiBCN and
SiOCN spacer dielectric’ to the IEEE IRPS review board?

JS: MOL reliability (MOL = Middle-of-Line, industry-speak for the contacts part of the chip) is
currently an area of interest in the industry. There is not yet a consensus on the correct voltage
acceleration model to use for this spacer breakdown. This paper specifically addresses this
question of the voltage model, in addition to giving fundamental data on the material reliability
which the industry can use as a benchmark.

What spacer material did you find performed best with a 7nm chip? What, about the material’s
lifetime, did you find – and in terms of “lifetime” what does this mean, compared to, say, a chip
in a computer or mobile device?

JS: The best spacer material is air which has the lowest dielectric constant. But there are many
process challenges to implement “air” spacer. Before “air” spacer will be implemented, we
need to find a material which has lower dielectric constant than SiN and compatible with the
CMOS integration. SiBCN and SiOCN are two materials meet these requirements.

In terms of lifetime, I would phrase the question differently: The lifetime is a required target
(failure rate less than target rate, over target lifetime). The goal of this research is to determine
what combination of operation voltage and spacer material and thickness can meet this
requirement.

Before we reach 7nm chips, can this work apply to other chips – 14nm, 10nm?

JS: Yes, SiBCN will be in 14nm technology node (developed at IBM, and now in manufacturing
with our foundry partner GlobalFoundries). SiOCN is being implemented in 7nm. To get to the
5nm node, we want to implement air-spacer.

Can you talk more about “air spacers”?

JS: An “air spacer” is the ultimate solution to improve chip performance that we’re targeting to
implement at the 5nm node and beyond.

Bear in mind, however, the “air” gap is just a part of the spacer. It is a small gap in another
material (presumably one of the materials we describe in our spacer dielectric paper). So the
work on the spacer material remains relevant and necessary to bridge the reliability
measurements to air gap technology.

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