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RF, DC, and Reliability Performance of MIM Capacitors Embedded in Organic

Substrates by Wafer-Transfer Technology (WTT) for System-on-Package
Applications

Article  in  IEEE Transactions on Electron Devices · April 2007

DOI: 10.1109/TED.2006.890233 · Source: IEEE Xplore

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Copyright © 2007 Year IEEE. Reprinted from IEEE TRANSACTIONS ON
ELECTRON DEVICES, VOL. 54, NO. 3, MARCH 2007. Such permission of the IEEE
does not in any way imply IEEE endorsement of any of Institute of Microelectronics’
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 3, MARCH 2007
RF, DC, and Reliability Performance of MIM
Capacitors Embedded in Organic Substrates by
Wafer-Transfer Technology (WTT) for
System-on-Package Applications
E. B. Liao, Hongyu Li, L. H. Guo, Guo-Qiang (Patrick) Lo, Member, IEEE, Rakesh Kumar,
N. Balasubramanian, Member, IEEE, and Dim-Lee Kwong, Senior Member, IEEE
Abstract—In this paper, radio frequency (RF), dc, and relia-
bility performance have been studied on metal–insulator–metal
(MIM) capacitors embedded in organic substrates. The MIM
structure including ∼74-nm SiN dielectric was prefabricated on
Si and then transferred onto organic substrates (FR-4) by wafer-
transfer technology (WTT). The RF characteristics up to 30 GHz
were investigated by equivalent lumped circuit modeling, showing
that the parameters associated with the MIM layers including
the main capacitance, parasitic inductance, and resistance were
only slightly changed by the WTT process. The substrate-related
parasitics were reduced as a result of the replacement of lossy Si
with insulating FR-4 substrates. Excellent capacitance linearity,
low voltage coefficient (∼2.2 ppm/V2 ), and temperature coef-
ficient (∼38 ppm/◦ C) were obtained for capacitors on FR-4
substrates. Current–voltage and time-dependent dielectric break-
down tests verified that, after the harsh processes of WTT, the
MIM structures maintained the intrinsic reliability as those orig-
inally fabricated on Si. This paper, along with earlier reports,
proved that WTT presented a new dimension to realize embedded
capacitors for high-density circuit board and system-on-package
applications.
Index Terms—Embedded capacitor, leakage, radio frequency
(RF), reliability, system on package (SoP), temperature coefficient
of capacitance (TCC), voltage coefficient of capacitance (VCC).
I. INTRODUCTION
A S THE CMOS technology advances toward the 45-nm
generation node, the majority of passive devices still
manifest themselves in a bulky and discrete form. Among
various passives, capacitors play a very important role since,
for example, the capacitors may account for 70% of the total
passive devices on the circuit board of a cell phone [1], [2], and
capacitors are required for various applications such as tuning,
blocking, and decoupling. For discrete capacitor components
in a surface mountable package, the solder interconnect results
in electrical parasitics and thermomechanical reliability [3] and
environmental concerns. To overcome these issues and also to
achieve design flexibility, capacitors are preferably embedded
in the packaging substrate. Embedding capacitors and other
Manuscript received September 25, 2006; revised November 22, 2006. The
review of this paper was arranged by Editor J. Kanicki.
The authors are with the Institute of Microelectronics, Singapore 117685
(e-mail: liaoeb@ime.a-star.edu.sg).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2006.890233
0018-9383/$25.00 © 2007 IEEE
425
passive devices in packaging substrates has been considered as
the core technology for the realization of system-on-package
(SoP), which is particularly critical for next-generation radio-
frequency (RF) systems [2], [4].
Embedding capacitors into organic packaging substrates
has been frequently realized by thick-film technology [5], [6]
because of the incompatibility of organic substrates with high-
temperature processes. Typically, the capacitor electrodes and
dielectric layer are directly defined on the organic substrates by
screen printing and curing in sequence. The dielectric thickness
is usually at mil level, and hence, the capacitance density is
lower compared to those fabricated by thin-film technology.
The precision control of the dimension and roughness of
the dielectric layer is also poor, resulting in high deviation
from specifications and inferior dielectric reliability. On the
other hand, the capacitor electrode is often made of printable
conductive paste or ink, which demonstrates > 4 times higher
electrical resistivity than pure metals [7]. As a result, the thick-
film capacitors suffer from higher parasitic resistance and lower
Q-factor, and hence, their application in RF systems is limited.
To overcome the above described drawbacks, wafer-transfer
technology (WTT) [8], [9] has been recently developed to
achieve high-performance metal–insulator–metal (MIM) ca-
pacitors embedded on packaging substrates. As shown in Fig. 1,
the capacitors are first fabricated on Si substrates by thin-film
technology and then transferred to organic substrates such as
FR-4 by sequential processes including thermo-compression
wafer bonding, back-grinding, and bulk Si etching. In contrast,
WTT-based capacitors feature several advantages over thick-
film capacitors.
1) Precise control of capacitor dimension which enables
capacitor of any values ranging from pico- to micro-
Faraday level.
2) Higher thermal budget due to Si substrate in compari-
son to the low glass transition temperature (∼200 ◦ C)
of organic substrates. This is particularly beneficial to
high-κ dielectrics which necessitate high-temperature
postdeposition annealing to improve the dielectric perfor-
mance [10].
3) Thinner, smoother dielectric, and thus higher capaci-
tance density and higher reliability. The smaller distance
between two capacitor plates (i.e., the dielectric thick-
ness) also leads to less parasitic inductance [11].
426
Fig. 1. Schematic of WTT for MIM capacitors embedded on organic sub-
strate, including: 1) MIM capacitor fabrication on Si substrate; 2) wafer
bonding by thermo-compression; 3) backside grinding; and 4) Si removal by
wet etching.
4) Electrode materials with superior conductivity which re-
sults in higher Q-factors. Clearly, the last two features
make WTT particularly useful for fabrication of embed-
ded capacitors for RF applications.
Despite the above advantages due to thin-film processes on
Si, however, it is still unknown that whether the RF and reli-
ability performance of the MIM capacitors is degraded by the
wafer-level transfer process. Potential degradation mechanisms
may include the following: 1) Cu diffusion into dielectric (i.e.,
plasma-enhanced chemical vapor deposition (PECVD)-SiN in
this paper) and 2) defect initiation in dielectrics. Previous study
[12] has shown that Cu may significantly diffuse into PECVD-
SiN after annealing at 450 ◦ C for 1 h. If annealing is conducted
at 550 ◦ C, the Cu diffusion is further enhanced by the ammonia
pretreatment process on the PECVD-SiN film [13]. Although
the thermo-compression bonding of WTT process occurs at a
much lower temperature (160 ◦ C), it is still in question that
whether the high compression (∼60 KPa) would significantly
assist the Cu diffusion through the dielectric layer. For defect in
dielectrics, it has been reported [14] that microvoids may appear
across the dielectric layer in an MIM structure as a result of
residual stress. For WTT-based capacitors, the residual stress
may come from not only the thermal mismatch between the
organic substrate and the inorganic stack layers of the MIM
structure but also the back-grinding process. Furthermore, the
residual stress may also introduce crystallographic defects like
dislocation into dielectrics [15], which are preferred transporta-
tion path for electrons or holes and hence lower the capacitor
reliability.
In this paper, we investigate and compare the RF and reliabil-
ity performance of on-Si MIM capacitors with those transferred
to FR-4 substrate. Together with the results [8], [9] reported
earlier, this paper completes the evaluation of WTT process as
an efficient alternative to realize embedded capacitors on or-
ganic substrates and also as a promising method for fabrication
of low-profile and high-performance integrated passive devices,
high-density circuit boards, and SoP.
II. EXPERIMENTALS
The MIM capacitors are initially fabricated on an 8-in Si (i.e.,
device wafer) with 2-µm-thick damascene Cu as electrodes and
∼74-nm PECVD-SiN as the dielectric layer. By the wafer-
transfer process, as indicated by Fig. 1, the MIM capacitors
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 3, MARCH 2007
Fig. 2. MIM capacitor embedded on organic substrate: (a) TEM cross section
and (b) plan view.
were transferred onto a 0.4-mm-thick FR-4 substrate with a
60-µm-thick prepreg sheet as glue layer. The thermo-
compression bonding takes place in an EVG520 bonding cham-
ber with a vacuum ambient of ∼10−3 mBar. The vacuum
is applied in order to eliminate the air trapped in the wafer
stack or the gas released from the organic materials during
heating. The wafer-level bonding was accomplished at 160 ◦ C
for 50 min with a compressive force of 2000 N. Owing to the
existence of sacrificial wafer, the bonded wafer stack remains
flat after cooling down to room temperature despite the thermal
mismatch of Si and FR-4. The flatness of bonded stack is
important to the subsequent double-sided grinding process,
which ends up with ∼200-µm thickness for both device and
sacrificial wafers. A tetramethylammonium hydroxide etching
was then applied to completely remove the Si, and finally,
the SiO2 /SiN passivation was removed by CHF3 /O2 dry-etch
process to expose the Al pads. Fig. 2(a) shows the cross-
sectional view of the MIM capacitors on FR-4 substrate. No
void can be seen at the MIM-FR4 interface. Fig. 2(b) shows
the plain view of the capacitor, which includes a coplanar
waveguide (CPW) structure for RF measurement up to 30 GHz.
Open CPW structures are also measured for de-embedding
purpose; hence, the RF characteristics associated with only the
MIM structures can be obtained.
RF characteristics were measured by HP8510 Network Ana-
lyzer, and reliability testing was conducted by Agilent 4156C
precision semiconductor parameter analyzer. Because of the
unsymmetric characteristic of the MIM structure, as shown in
Fig. 2(a), it is important to keep the polarity of stress field
consistent for capacitors on Si and FR-4 substrates. In this
paper, the top (or bottom) electrode of the capacitor on Si (or
FR-4) substrate was always applied with positive field during
reliability testing. All the measurements were conducted at
room temperature (24 ◦ C) unless specified particularly.
LIAO et al.: RF, DC, AND RELIABILITY PERFORMANCE OF MIM CAPACITORS EMBEDDED IN SUBSTRATES 427

Fig. 4. Equivalent circuit model representing MIM capacitors on Si and FR-4

substrates [18].

Ls and the parallel resistance Rp do not show significant

change by the wafer-transfer process. However, the main ca-
Fig. 3. Effective capacitance comparison between capacitors on Si and trans- pacitance Cs slightly increases after wafer transfer, which is
ferred to FR-4 substrate.
consistent with the capacitance density increase obtained at
low frequency measurement [9]. Both the Cs and Rs changes
III. RESULTS AND DISCUSSION
are tentatively attributed to the slight deformation of the MIM
A. RF Performance layers (particularly the Cu electrodes which possesses excellent
plasticity) as a result of significant residual stress/strain induced
Fig. 3 shows the effective capacitance as a function of
by the wafer-transfer process. On the other hand, the substrate-
frequency for different capacitors on Si and FR-4 substrate.
associated parameters Rsub and Cox result in higher insulation
The resonant frequency, at which the capacitors actually turn
impedance after the wafer-transfer process, which is obviously
into inductors, moves toward the lower end with increase of
related to the replacement of lossy Si substrate with FR-4.
capacitor value. The resonant frequency is also slightly reduced
Fig. 5 illustrates that Rsub and Cox possess opposite scaling
after the wafer-transfer process, and the difference becomes
relationship with the capacitor area (i.e., the capacitor value).
more obvious for capacitors with lower values. This shift of
The scalability of Rsub is enhanced by the transfer process
resonant frequency may be attributed to the minute change
while the contrary trend is observed on Cox .
of main capacitance and parasitic inductance, which will be
The validity of the equivalent circuit model in wideband
extracted and shown in the following section.
range was proved by the excellent agreement between the
For the purpose of evaluating the effects of WTT process on
measurement and equivalent circuit modeling until 30 GHz, as
RF performance, it is very important to know the variation of
shown in Fig. 6. One should note that all elements in equiv-
main capacitance, parasitic inductance, and resistance. These
alent circuit are frequency-independent. Furthermore, Fig. 7
values are also desired for time-domain simulation like SPICE.
illustrates that the RF performance of before- and after-transfer
Hence, lumped circuit models are usually used to extract the
capacitor demonstrated minor difference through the frequency
equivalent element values for a particular range of frequency.
range. The Q-factor is also not affected after wafer transfer, as
For RF capacitors, traditional equivalent circuit models [16]
shown in Fig. 8. The similarity of transmission coefficient S12
consist of main capacitor, parasitic inductor and resistor in
and Q-factor is consistent with the stability of Zseries through
series, a resistor parallel to the main capacitor representing the
transfer process, as shown in Table I, which again verifies the
dielectric loss, and sometimes also includes parasitic capacitor
validity of the equivalent circuit model. It should be noted
and conductance as indicator of substrate effects [17]. The
that the WTT-based embedded capacitor demonstrates a high
disadvantage of the traditional model is that the increase of
Q-factor of over 100 at 1 GHz, which is much higher than those
resistive impedance with frequency due to skin effect is not
fabricated by lamination [19] or LTCC technology [2].
taken into account, and hence, the Q-factor is overestimated
particularly in high frequency range. The skin effect was ad-
B. Linearity, Voltage, and Temperature
dressed in a recent model [18], which features fully frequency-
Dependence of Capacitance
independent lumped circuit elements representing the capacitor
behavior within a wide band. As such, this model makes it Fig. 9 shows that the capacitance values increase linearly
easy to compare the comprehensive capacitor characteristics with the plate area, and also no degradation of capacitance and
before and after wafer-transfer process. As shown in Fig. 4, its linearity is observed from the WTT process. The capacitance
the model consists of two parts: the series impedance Zseries density was quite high as ∼85 nF/cm2 , and the capacitance
and the substrate-related conductance Ysub . In particular, Cs uniformity is within ±0.7% (1σ) across the wafer. It should
represents the main capacitance while others indicate parasitics be emphasized that, since the capacitors were fabricated on
associated with the MIM layers or the substrate. Si substrates first, the dielectric thickness would be allowed
With the method described in [18], the lumped element to be further reduced. Combining with integrated high-κ di-
values of equivalent circuit model for several capacitors were electrics (e.g., HfO2 /Al2 O3 [16]), a much higher capacitance
extracted and summarized in Table I. It could be seen that, density can be obtained for embedded capacitors on organic
for the series impedance part Zseries , the parasitic inductance substrate. Another interesting observation from Fig. 9 is that
428
TABLE I
EQUIVALENT CIRCUIT PARAMETER COMPARISON FOR CAPACITORS BEFORE AND AFTER WTT PROCESS
Fig. 5. Parasitic capacitance (Cox ) and substrate resistance (Rsub ) as a
function of the capacitor dimension for before- and after-transfer capacitors.
Fig. 6. S-parameter comparison until 30 GHz between measurement and
equivalent circuit modeling.
the capacitance value is slightly enhanced by the WTT, which
is consistent with the calculated value of equivalent circuit
elements, as shown in Table I. This is presumably attributed
to the compressive force loaded on the MIM structure during
the WTT process.
A system-level capacitor between functional blocks may
subject to high voltage, and thus, the capacitance stability with
voltage is very important. The variation of the quadratic voltage
coefficient of capacitance (VCC) and the loss tangent with the
frequency (10 k–1 MHz) for capacitors embedded on FR-4 was
plotted in Fig. 10. It was reported [20] that, to reduce the disper-
sive effect, either nitride/oxide (NO) or oxide/nitride (ON), or
oxide/nitride/oxide (ONO) dielectric stacks have been used as
a replacement of pure silicon nitride for on-Si MIM capacitors.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 3, MARCH 2007
Fig. 7. S-parameter comparison until 30 GHz between capacitors embedded
on Si and FR-4.
Fig. 8. Q-factor comparison between capacitors fabricated on Si and trans-
ferred to FR-4.
Furthermore, nitride passivation and sintering process were also
required for these dielectric stacks to enhance the capacitance
stability with respect to bias voltage. In contrast, our measure-
ments showed very low capacitance dispersion (∼2.2 ppm/V2
at 1 MHz) close to that of ONO stacks (∼1.2 ppm/V2 at 1 MHz)
despite the fact that no additional layers or processes were in-
volved. According to [20], the charge relaxation time associated
with dielectric traps may become longer than the excitation
wave period. This explains the appearance of a plateau region
in VCC when the frequency increases beyond 100 kHz. The
dispersive effect on loss tangent was similar to the previous
report [21].
LIAO et al.: RF, DC, AND RELIABILITY PERFORMANCE OF MIM CAPACITORS EMBEDDED IN SUBSTRATES
Fig. 9. Capacitances as a function of plate area on Si and FR-4 substrates.
Fig. 10. Quadratic VCC and loss tangent as a function of frequency for
capacitors on FR-4 (T = 24 ◦ C).
On the other hand, the embedded capacitors on FR-4 demon-
strated a linear capacitance dependence on the temperature, as
shown in Fig. 11, which is much lower than the previously
reported on pure silicon nitride but quite close to the ON
and NO dielectrics [20]. The inset table indicated no obvious
correlation between the temperature coefficient of capacitance
(TCC) and either bias voltage or applied frequency. Once again,
the low values of TCC as well as its stability are particularly
advantageous for SoP applications where a system-level capac-
itor typically works within a wide range of conditions including
temperature, voltage, and frequency range.
C. Dielectric Leakage and Reliability Characteristics
The leakage current has been characterized under different
temperatures, as shown in Fig. 12. The leakage current was
erratic at low field range and increased with temperature at
high field. For the case of 297 K, there was no discernable
difference in the leakage before and after transferring to FR-4
substrate. For capacitors embedded on FR-4, the perfectly fitted
curves indicated that, with the increased temperatures, the
leakage characteristics still followed the Poole–Frenkel (P–F)
conduction mechanism [22], and no excess leakage was found.
With current–voltage measurement, the breakdown-voltage
distribution for MIM capacitors on Si and transferred to
FR-4 was obtained as Fig. 13. The capacitor plate area is
429
Fig. 11. Normalized capacitance change as a function of temperature mea-
sured at 100 kHz with zero bias. Capacitance changes are normalized to the
capacitance obtained at 297 K. The inset table shows that no clear trend exists
between TCC and bias voltage and sweeping frequency.
Fig. 12. Leakage characteristics as a function of electric field measured at
different temperatures. The perfect P–F fitting of measurement results is clear
since they are quite parallel to one of the dotted straight lines, which were drawn
as references.
126.7 × 126.7 µm2 . In the case of 50% probability of failure,
the breakdown voltage is reduced from ∼50 to ∼48 V as a
result of increased defects originating from the wafer-transfer
process. Like the case of gate oxide, the dielectric may be
degraded from a number of mechanisms including impact ion-
ization, anode hole injection, or trap creation, in which the hot
electrons and holes can be thermally activated with or without
assistance of electrical field to overcome the energy barrier,
for example, ∼5 eV for SiN bandgap. It is therefore assumed
that the wafer-transfer processes, including mechanical grind-
ing, thermo-compression bonding, and consequently the wafer
deformation, are possible sources for providing the threshold
energy.
The time-dependent dielectric breakdown (TDDB) test was
conducted on capacitors with an area of 109.5 × 109.5 µm2 .
Fig. 14 shows the results in terms of Weibull probability as a
function of time to failure. A tail was noticeable at low failure
time region, which could be attributed to extrinsic breakdown
[23] due to latent defects. Hence, to describe the intrinsic
breakdown behavior of the dielectric, the Weibull slope was
extracted by linear fitting of the segment with higher failure
time. It was found that the Weibull slope decreased from
430
Fig. 13. Comparison of cumulative failure probability as a function of break-
down voltage.
Fig. 14. Comparison of Weibull probability as a function of lifetime to
breakdown.
2.67 to 2.25, signifying a mild degradation of the dielectric by
the wafer-transfer process. The failure time data were translated
into critical charge to failure (QBD ) by multiplying the time
to leakage current during TDDB test, and the results were
illustrated in Fig. 15. Interestingly, a much longer tail was
observed at low-to-intermediate range of QBD . In fact, the
Weibull failure probability as a function of QBD can be divided
into two segments: one with lower QBD and extending over
magnitude of two orders and the other one with higher QBD
but with a much narrower distribution. The long tail was also
observed on capacitors fabricated on Si, probably revealing
presence of latent defects before the wafer-transfer process.
One can actually note from Fig. 15 that, in higher QBD region,
the capacitors on Si and transferred to FR-4 almost demonstrate
the same statistical breakdown behavior. Therefore, the intrinsic
insulating performance of the MIM dielectric probably may not
be degraded as much as the Weibull slope reduction manifested
in Fig. 14.
Finally, the typical leakage-current variation with stress time
during TDDB test (Voltage: 48 V) was also shown in Fig. 16,
which was measured on samples with time to failure corre-
sponding to 63.2% Weibull probability. A very close leakage
current was obtained on capacitors fabricated on Si and trans-
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 3, MARCH 2007
Fig. 15. Comparison of Weibull probability as a function of critical charge to
dielectric breakdown.
Fig. 16. Leakage-current variation with stress time during TDDB test
(Voltage: 48 V).
ferred to FR-4. However, a short period of current increase was
recorded at the beginning stage of TDDB test. After reaching
a peak value by ∼70 s, the leakage current decreases with the
stress time as reported in [24]. The initial current increase may
be induced by hole trapping in the dielectric close to the cathode
electrode and, hence, the effectively higher electrical field.
IV. CONCLUSION
Embedded MIM capacitors have been realized on organic
substrates (FR-4) by a novel process platform, so-called WTT.
No significant degradation has been observed through the WTT
process in terms of the RF, dc, and reliability characteristics
associated with the MIM layers. This approach opens up a new
way of embedding capacitors for high-density circuit board and
SoP applications.
ACKNOWLEDGMENT
The authors would like to thank the staffs of Semiconductor-
Process-Technology laboratory of Institute of Microelectronics
in Singapore, particularly J. Y. K. Woo for her efforts on TEM
and C. H. M. Chua for his assistance on reliability testing.
LIAO et al.: RF, DC, AND RELIABILITY PERFORMANCE OF MIM CAPACITORS EMBEDDED IN SUBSTRATES
R EFERENCES
[1] R. K. Ulrich, Integrated Passive Component Technology, R. K. Ulrich
and L. W. Schaper, Eds. Hoboken, NJ: Wiley, 2003, ch. 1: Introduction,
pp. 3–7.
[2] J. Wu, M. J. Anderson, D. Coller, and G. Guth, “RF SIP technology
innovation through integration,” in Proc. 5th Int. Conf. Electron. Packag.
Technol., Oct. 28–30, 2003, pp. 484–490.
[3] D. Scheider, D. Hopkins, P. Zucco, E. Moszczynski, M. Griffin, and
M. Takacs, “Reliability and characterization of MLC decoupling capaci-
tors with C4 interconnections,” in Proc. 46th Electron. Compon. Technol.
Conf., Orlando, FL, May 1996, pp. 365–374.
[4] R. R. Tummala and J. Laskar, “Gigabit wireless: System-on-a-package
technology,” Proc. IEEE, vol. 92, no. 2, pp. 376–387, Feb. 2004.
[5] W. Jillek and W. K. C. Yung, “Embedded components in printed circuit
boards: A processing technology review,” Int. J. Adv. Manuf. Technol.,
vol. 25, no. 3/4, pp. 350–360, Feb. 2005.
[6] W. J. Borland and S. Ferguson, “Embedded passive components in printed
wiring boards, a technology review,” Circuitree, pp. 94–106, Mar. 2001.
[7] T. Kaydanava, M. F. A. M van Hest, A. Miedaner, C. J. Curtis,
J. L. Alleman, M. S. Dabney, E. Gamett, S. Shaheen, L. Smith, R. Collins,
J. I. Hanoka, A. M. Gabor, and D. S. Ginley, “Direct write contacts for
solar cells,” in Proc. 31st IEEE Photovolt. Spec. Conf., Jan. 3–7, 2005,
pp. 1305–1308.
[8] L. H. Guo, Q. X. Zhang, H. Y. Li, E. B. Liao, L. K. Bera, W. Y. Loh,
C. C. Kuo, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, “Successful
transferring of active transistors, RF-passive components and high density
interconnect from bulk Si to organic substrates,” in IEDM Tech. Dig.,
2005, pp. 675–678.
[9] E. B. Liao, L. H. Guo, R. Kumar, G. Q. Lo, N. Balasubramanian, and
D. L. Kwong, “High-density MIM capacitors (∼85 nF/cm2 ) on organic
substrates,” IEEE Electron Device Lett., vol. 26, no. 12, pp. 885–887,
Dec. 2005.
[10] X. Zhu, J. Zhu, S. Zhou, Z. Liu, N. Ming, S. Lu, H. L.-W. Chan, and
C.-L. Choy, “Recent progress of (Ba, Sr) TiO3 thin films for tunable
microwave devices,” J. Electron. Mater., vol. 32, no. 10, pp. 1125–1134,
Oct. 2003.
[11] R. Ulrich, “Embedded resistors and capacitors for organic-based SOP,”
IEEE Trans. Adv. Packag., vol. 27, no. 2, pp. 326–331, May 2004.
[12] H. Miyazaki, H. Kojima, and K. Hinode, “Passivation effect of
silicon nitride against copper diffusion,” J. Appl. Phys., vol. 81, no. 12,
pp. 7746–7750, Jun. 15, 1997.
[13] W. Qin, Z. Q. Mo, L. J. Tang, B. Yu, S. R. Wang, and J. Xie, “Effect of
ammonia plasma pretreatment on silicon-nitride barriers for Cu metalliza-
tion systems,” J. Vac. Sci. Technol. B, Microelectron. Process. Phenom.,
vol. 19, no. 5, pp. 1942–1947, Sep./Oct. 2001.
[14] D. Suh and J.-Y. Kang, “Stress-induced failure of Si3N4 metal–
insulator–metal capacitors fabricated by plasma enhanced chemical vapor
deposition,” J. Vac. Sci. Technol. B, Microelectron. Process. Phenom.,
vol. 20, no. 2, pp. 717–720, Mar./Apr. 2002.
[15] Y. Gogotsi, C. Baek, and F. Kirscht, “Raman microspectroscopy study of
processing-induced phase transformations and residual stress in silicon,”
Semicond. Sci. Technol., vol. 14, no. 10, pp. 936–944, Oct. 1999.
[16] S.-J. Ding, H. Hu, C. Zhu, S. J. Kim, X. Yu, M.-F. Li, B. J. Cho,
H. Chan, M. B. Yu, S. C. Rustagi, A. Chin, and D.-L. Kwong, “RF,
DC, and reliability characteristics of ALD HfO2 −Al2 O3 laminate MIM
capacitors for Si RF IC applications,” IEEE Trans. Electron Devices,
vol. 51, no. 6, pp. 886–894, Jun. 2004.
[17] M. Y. Yang, D. S. Yu, and A. Chin, “High-density RF MIM capacitors
using high-κ La2 O3 dielectrics,” J. Electrochem. Soc., vol. 151, no. 7,
pp. 162–165, 2004.
[18] S.-S. Song, S.-W. Lee, J. Gil, and H. Shin, “Simple wide-band
metal–insulator–metal (MIM) capacitor model for RF applications and
effect of substrate grounded shields,” Jpn. J. Appl. Phys., vol. 43, no. 4B,
pp. 1746–1751, 2004.
[19] S. Dalmia, J. M. Hobbs, V. Sundaram, M. Swaminathan, S. H. Lee,
F. Ayazi, G. White, and S. Bhattacharya, “Design and optimization of high
Q RF passives on SOP-based organic substrates,” in Proc. 52nd Electron.
Compon. and Technol. Conf., 2002, pp. 495–503.
[20] S. V. Huylenbroeck, S. Decoutere, R. Venegas, S. Jenei, and
G. Winderickx, “Investigation of PECVD dielectrics for nondispersive
metal–insulator–metal capacitors,” IEEE Electron Device Lett., vol. 23,
no. 4, pp. 191–193, Apr. 2002.
[21] C. H. Ng, K. W. Chew, and S. F. Chu, “Characterization and compari-
son of PECVD silicon nitride and silicon oxynitride dielectric for MIM
capacitors,” IEEE Electron Device Lett., vol. 24, no. 8, pp. 506–508,
Aug. 2003.
431
[22] S. M. Sze, “Current transport and maximum dielectric strength of silicon
nitride films,” J. Appl. Phys., vol. 38, no. 7, pp. 2951–2956, Jun. 1967.
[23] J. Scarpulla, D. C. Eng, S. R. Olson, and C.-S. Wu, “A TDDB model of
Si3 N4 -based capacitors in GaAs MMICs,” in Proc. 37th Ann. Int. Reliab.
Phys. Symp., San Diego, CA, 1999, pp. 128–137.
[24] K.-H. Allers, “Prediction of dielectric reliability from I-V√ characteris-
tics: Poole–Frenkel conduction mechanism leading to E model for
silicon nitride MIM capacitor,” Microelectron. Reliab., vol. 44, no. 3,
pp. 411–423, Mar. 2004.
E. B. Liao received the B.Eng. degree in metal-
lurgical engineering from Central South University
of Technology, Changsha, China, and the M.Eng.
degrees in materials engineering and mechanical en-
gineering, both from Institute of Metal Research of
the Chinese Academy of Sciences, Shenyang, China
and National University of Singapore, Singapore,
respectively. Since 2002, he has been working to-
ward the Ph.D. degree at the National University of
Singapore.
In 2004, he joined the Institute of Microelec-
tronics, Singapore, as a Research Engineer. His research interests are radio-
frequency passive devices, microfabrication techniques, wafer-level bonding,
and packaging technologies.
Hongyu Li received the Ph.D. degree from
Changchun Institute of Physics, Chinese Academy
of Science, Changchun, China in 1999, with a major
in semiconductor physics and devices.
She was a Yield Improvement Engineer in Char-
tered Silicon Partner Pte Ltd. from October 2000 to
October 2002. She has been working on the integra-
tion and reliability improvement for Cu/Low-κ in-
terconnects and RF passive devices in the Institute of
Microelectronics, Singapore, since November 2002.
She has published 35 research papers.
L. H. Guo, photograph and biography not available at the time of publication.
Guo-Qiang (Patrick) Lo (S’86–M’92) received the
B.S. degree from California State University, Chico,
in 1987, and the M.S. and Ph.D. degrees in electrical
and computer engineering, both from the University
of Texas at Austin, 1989, and 1992, respectively.
He was with the Integrated Device Technology,
Inc., both in San Jose, CA, and Hillsboro, OR, work-
ing in Si semiconductor areas in process and integra-
tion module research and development. Since 2004,
he has been with the Institute of Microelectronics,
Singapore. His research interests are in novel semi-
conductor device and integration technology. He has authored or coauthored
more than 50 articles and more than ten granted patents.
Rakesh Kumar received the B.S. (Hons.) degree in
electronics and electrical communication engineer-
ing from Punjab University, Chandigarh, India and
the MBA degree from Indira Gandhi National Open
University (IGNOU), Delhi, India. He is currently
working toward the Ph.D. degree at Nanyang Tech-
nological University, Singapore.
He is currently a Deputy Lab Head at Semicon-
ductor Process Technology, Institute of Microelec-
tronics, Singapore. He has been working in the area
of CMOS process technology for the last 24 years.
His areas of interest are Cu interconnects, CMOS, and MEMS technologies.
432
N. Balasubramanian (M’96) received the Ph.D.
degree in physics from the Indian Institute of Tech-
nology, Madras, India, in 1990.
Since 1998, he has been with the Institute of
Microelectronics (IME), Singapore, where he cur-
rently heads the Semiconductor Process Technology
Laboratory. Prior to joining IME, he was with Char-
tered Semiconductor Manufacturing, Singapore, as
a Section Manager of the diffusion/implant process
modules. He has broad experience in Si process tech-
nology through different roles in CMOS front-end
process development, R&D, manufacturing, technology transfer, and program
management. His current research interests are in Si nanowire technology, and
application of Si devices and technology in bioelectronics and photonics.
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 3, MARCH 2007
Dim-Lee Kwong (A’84–SM’90) received the B.S.
degree in physics and the M.S. degree in nuclear
engineering from the National Tsing Hua University,
Taipei, Taiwan, R.O.C., in 1977 and 1979, respec-
tively, and the Ph.D. degree in electrical engineering
from Rice University, Houston, TX.
He is the Executive Director and a Professor of
electrical and computer engineering with the Insti-
tute of Microelectronics, Singapore. He also holds
the Earl N. and Margaret Brasfield Endowed Profes-
sorship at the University of Texas at Austin. Under
his supervision, 50 students have received their Ph.D. degrees. He is the author
of more than 410 referred archival journals and 350 referred archival conference
proceedings publications and the holder of more than 25 U.S. patents. He has
also presented more than 60 invited talks at international conferences. His
current research interests include Si narrow-wire-based CMOS nanodevices
and its applications, Si-based ultrasensitive biosensors and lab-on-chip, and Si
micro- and nanophotonics technology.