CALIFORNIA STATE UNIVERSITY, NORTHRIDGE

Simulation of GaAs Schottky diode using Synopsys Sentaurus TCAD Tools

A graduate project submitted in partial fulfillment of the requirements

For the degree of Master of Science

In Electrical Engineering

By

Srinivasa Kmihik Chakkirala

May 2011
The graduate project of Srinivasa Karthik Chakkirala is approved:

Dr. Ali Amini, Ph.D. Date

Dr. Ramin Roosta, Ph.D. Date

Dr. Somnath Chattopadhyay, Ph.D, Chair. Date

California State University, Northridge

11
 ACKNOWLEDGEMENT

I would like to thank my professor Dr. Somnath Chattopadhayay for being my

advisor and guide. I am grateful to him for his continuous support and invaluable inputs
he has been providing me through the development of the project. This work would not
have been possible without his support and encouragement. I also would like to thank
him for showing me some examples that related to the topic of my project.

Besides, I would like to thank the Department Chair Dr. Ali Amini of Electrical
and Computer Engineering for providing me with a good enviromnent and facilities to
complete this project. It gave me an oppmtunity to participate and leam about the
software Synopsys. I also would like to thank Dr.Ramin +Roosta as participant in the
review process ofthis project as my committee member.

This project is dedicated to my parents both my mother and father without whom i
would not be here today, they have supported me anyway they could, whether financially
or emotionally, and my friend Chih-yuan cheng who has altemately stood by and helped
me to see fruits of this work. There have been many challenges and struggles and they
have always been there when I needed support.

111
 TABLE OF CONTENTS

Signature Page 11

ACKNOWLEDGMENT 11I

ABSTRACT VI

Chapter 1: Introduction 1

1.1 Electro Static Discharge 2

1.2 Microwave GaAs Schottky diode 8

1.3 Gallium Arsenide wafer and its Interconnections 9

1.4 Graphene Nanoribbon (GNR) Schottky diode 15

1.5 Ideality Factor and Barrier height for GaAs 22

Chapter 2: Physics of Schottky diode 25

2.1 Benefits of Schottky Diode 26

2.2 Images-Force Lowering 28

2.3 Barrier-Height Adjustment 31

2.4 Current Transport Process 33

2.5 Tunneling Current 35

2.5.1 Thermionic-Emission-Diffusion Theory 36

2.6 Minority-Carrier Injection 38

Chapter 3: Device Physics Of Gallium Arsenide 44

3 .1 Gallium Arsenide Advantages 44

3.2 Applications of Gallium Arsenide 45

IV
 3 .2.1 Solar cells and detectors 45

3.2.2 Light Emission Devices 46

3.2.3 Band Gap 46

3 .2.4 Carrier Density 47

3.2.5 Electron Mobility 47

3.2.6 Crystal Growth 47

3.2.7 Crystal Stress 48

3.2.8 Physical Strength 48

3.2.9 Native Oxide 48

Chapter 4: Synopsys Sentaurus TCAD Device Modeling 49

4.1 Creating Layers and shape with Sprolyt Mask Layer editor 50

4.2 Creating a process flow with Ligedit 52

4.3 Running Sprocess and viewing results in tecplot 58

Chapter 5: Results and discussions 62

REFRENCES 68

Appendix A: Input File for Sprocess 75

Appendix B: Input File for Sdevice Forward Bias 77

Appendix C: Input File for Sdevice Reverse Bias 80

v
 ABSTRACT

GaAs Based Schottky Diode Using Synopsys Sentaums TCAD

By

Srinivasa Karthik Chakkirala

Master of Science in Electrical Engineering

Today, being the dawn of a new RF technology wave, the requirement of making
semiconductor devices which have greater speed in performance, Gallium Arsenide
(GaAs) based schottky diodes have superior RF performance with a low forward voltage
drop and a very fast switching action compared to silicon based diodes due to its high
speed operation. Perhaps the primary benefit of GaAs comes from its electron-dynamic
properties. In this project, the Synopsys Sentaurus TCAD is used to simulate the GaAs
based schottky diode to generate the device stmcture and model the device electrical
characteristics. The objective of this project is to design GaAs-based schottky diode with
the software called Synopsys.

The Sentaurus TCAD simulator project provides a template setup for the
simulation of Gallium-Arsenide devices. A special attention is given to the changes in the
numeric accuracy settings required to simulate large band-gap materials such as Gallium
Arsenide for the example of a schottky diode, TCAD has the capability to develop and
simulate the fabrication and electrical outcome of semiconductor devices. It takes layout,
process steps with parameters and electrical outcome of semiconductor devices. It then
incorporates the data to produce simulated data (i.e., device structure, I-V curves). From
the simulation experience with TCAD, it is understood that the software has many
"powerful" options that can lead to deeper analysis. In this project a general electrical
characteristic of an GaAs Schottky diode is achieved.

Vl
 Chapter 1

Introduction

The emergence of new circuit topologies in power electronics and the high cost of
various components used in such circuits make it absolutely essential for good models to
be developed for various circuit elements which can behave correctly under different
operating conditions and at various temperatures [1]. Bipolar rectifiers such as P-i-N
diodes have been used extensively to facilitate high current-handling capabilities.
However, these devices are prone to reverse recovery problems due to minority carrier
charge storage consequently, their switching speed is limited. To improve the switching
speed and to perfonn efficient high-power conversion, majority carrier rectifiers are in
demand [2]. The GaAs Schottky diode reverse recovery mechanism greatly differs from
that of the silicon P-i-N diode. A systematic approach is described to extract accurate
device parameters from simple measurements that can be used to construct a 2-D
simulation grid. In all cases, the simulation results are in good agreement with the
measured data [3]. Ti based multilayer contacts on n-GaAs have been tested in respect to
their short time annealing characteristics up to 800°C. As shown in figure 1, the Schottky
diode is very similar to a standard pn diode, instead of having an implanted p-layer, the
action occurs at the interface between the barrier metal and the silicon. The guard rings
are used to make the device's reverse breakdown characteristics more rugged. Since both
metal and the silicon are n-type materials, the conduction occurs through majority
carriers only, with no minority catTier injection, storage, or recombination. This explains
the Schottky diode's lack of reverse recove1y, making it ideal for high frequency
applications [4].

I
 Schottky Barrier 1\ietal Front 1\letal

N- epilayer Guard Rings

N+Substrate

Figure 1: Basic Structure of Schottky Diode

1.1 Electro Static Discharge (ESD):

Greatest reliability threat to semiconductor devices:

GaAs schottky diodes varying in size from 40J..Lm to 400J..Lm anode periphery have
been tested to assess their effectiveness as ESD protection devices in FET-based MMICs.
ESD failure voltage is seen to increase linearly with diode size. A plot of ESD failure
voltage as a function of discrete diode periphery is shown in figure 2. Notice that the
failure threshold increases linearly with diode size. This result can be used to consider
trade-offs between failure voltage threshold and circuit area. HBM ESD tests have been
perfonned on diodes of various sizes and configurations. The ESD failure threshold for
these diodes increases monotonically with diode size as shown in tablel [5].

2
 ~ 1200~~~~~~~~~~~~~~~~~
G
~ 1000~~~~~~~~~~~~~~~~~~~4
(1;1

-a> 800
~ 600 ~~~~~~~~~~--~~~~~~~~~
~
~
VJ
400 ~§~~~~~~~~~~~~~~
r.LJ
200
0
0 100 200 300 400 500
Size Gate Periphery (urn)

Figure 2: Failure voltage as a function of diode size for discrete diodes.

--- --- ---···- -----. -----·-. ----

Structure Size Failure Vohages

1 :finge-r interdigitated 40m 150V

2 finger interdigitated 80m 300\l
2 finges (1 gap) interdigitated ..
80m --
250V
------. . ---·--·

2 :finger (2 gap) interdigitated - 80m 250V

6 :finger interdigitated 240m 600V
10 :finger interdigitated 400111 1000V
1 x 40 edge diode 40m lOOV
1 x 80 edge diode 80m 225V
·- ----
2 finger interdigitated cham 80m--·- 400V
------- _1 }t ~q edg~ c~£iin --
80m 400V

Table 1: Minimum ESD failure voltages

3
 100000
") ,-\r·.0.54e\r,
,?- -....
'"'I 0\7 0 46 \r
,-
_;o*".T ·• ~· e ·
......... _ ·_, _

.~··•/,...~ ~L5V. OAleV

11¥'- ~,.~..... ~LOV.0.39eV
· ·/,..;./
-~·~">· -~--·· ·•
~·- /" -0 ...-\ir 0 36eV
j '•··' .......
··.P~~~
..
.·~-·J-
_,.-11 -.J-;J ..

-..3- 10,000 - .
·····.~·~:;:tr~: ~r<
,-J'..,.,....... ···
rx: ';
A
:;.~

'
-

1000 I 1 J
3A 3.6 3.8 4.0
lOOOT (1/K)

Figure 3: Resistance versus 1000/T obtained by the high-frequency inflexion

frequency from the sample with 1000 A 0 thick InGaAs.

Figure 3 shows that the R increases monotonously with increasing reverse

voltages at low temperature while the R remains almost a constant at high temperature.
This effect leads to an increase of activation energy from 0.36 to 0.54eV as reverse
voltage increases from 0.5 to 2.5V. Therefore, we should take 0.36eV for the activation
energy of R. It is shown that at low voltages, the low-frequency capacitance is equal to
the Schottky depletion capacitance; at high voltages, it approaches the high-fi:equency
capacitance [6]. The dependence on temperature of the Schottky barrier height ofPt on n-
GaAs is reported. Two different behaviors are observed. The Schottky contacts of one
group have a mean batTier height of 1.018ev and a temperature coefficient of
20.23meV/K while the contacts of the other group have a significantly lower barrier
height of 0.922eV which is almost independent of the temperature. These results are
interpreted on the basis of recent models of fermi level pinning. While the fermi level in
the diodes of the first group is pinned to a charge neutrality level, it is pinned by defects
in the diodes of the second group [8]. Reverse current-temperature (IG/T) characteristics
of Al-GaAs Schottky diodes with oxidized interfaces are measured in the temperature
region of250-400 Kat various reverse bias voltages in order to elucidate a mechanism of
carrier transport through the barrier. The IG/T dependencies are explained on the basis of

4
phonon-assisted electrons tunneling from interface states to the semiconductor model. It
is shown that these dependencies are due to the above-mentioned cmTier transport
through the Schottky barrier mechanism [9]. An ensemble MC simulator self-consistently
coupled with a one-dimensional PS has been used to investigate the high-frequency noise
properties of GaAs SBDs. This method, by intrinsically incorporating the processes
causing the fluctuations, allows for a deep microscopic interpretation of the noise
behavior of these devices. By using cun·ent-noise operation, our microscopic model
naturally detects the presence of shot, thermal and excess noise and reproduces their main
features without invoking phenomenological noise sources [10].

... "'---- Padlel Plate

Our theory

2 measured

~
.-t::
u
Ill
~
u 1

0
0.2 0.4 0.6 0.8 LO

Figure 4: Measured and calculated dependences of the round-dot GaAs Schottky

barrier diode capacitance on the dot diameter.

The C-V characteristics of round-dot GaAs schottky barrier diodes by registering

the capacitance between a metal whisker and the wafer with schottky diodes and
determining the capacitance jump when the whisker touches the schottky contact. The
experimental data are compared with the theory as can be seen from the figure 4; the
agreement with the experimental data is quite reasonable [11].

5
 20
Rsc = 10-5 llcm2
18 R sc = 10 -6 Qcm2·

R sc =10-7Qcm 2
16

14

12

10
0 1 2 3 4 5
Substrate Thiclrness (11m)

Figure 5: Resistance versus chip thickness for various contact resistivities

at 1 THz.
The series impedance as a function of chip thickness is shown in figure 5 for
various specific contact resistances. The figure 5 also shows that at terahertz :fi·equencies
(3THz to 20THz), there is a gradual increase in the series resistance,and a much sharper
rise in the series inducatance. This is due to both the skin effect and the electron inertia.
The graph indicates that in device of thickness less than about 2[1m, the value of the
specific contact resistivity has a significant effect on the overall series resistance, whereas
in thicker chips, the value of the specific contact resistivity of 1o· 8ncm2 , show the
greatest decrease in total series resistance as the chip thickness is reduced below one
skin-depth. [12]. So, the proposed membrane diode will substantially reduce the series
impedance by making the cunent path much shorter than in diodes of greater thickness
diodes with epitaxial materials other than GaAs, such as InGaAs, are also being
investigated. The new diodes developed from guidelines presented in this analysis will
increase both the sensitivity and maximum operating frequency of sub millimeter wave
heterodyne receivers [13]. Most of the GaAs MESFET models cunently in use for
circuit simulation are more or less nonphysical curve fitting models, which complicates
the task of extracting simulation parameters from the measurement data. Therefore, in

6
response to the problems connected with GaAs device characterization and modeling, a
method for extracting model parameters simultaneously for the channel and gate diode of
GaAs MESFET was developed. The procedure has been applied to the extraction of
model parameters for gamma and neutron irradiated MESFETs, and the results have been
compared through circuit simulation [14]. The existing models ofthe current flow across
planar-doped-barrier (PDB) diodes are based on thennionic emission over the triangular
barriers and have successfully predicted the Characteristics of diodes with low barriers
[15].

1Q1
1Ql

109

·f
Q
w-1
w-2
~ w-3
~ 10-4
lQ-5

w-6
lQ-7
0 1 2 3
Bias Voltage (V)

Figure 6: Experimental temperature dependent 1-V characteristics of a PDB diode.

Figure 6 shows a measured temperature dependent I-V characteristics of a PDB

diode. The temperature is varied from 300 to 50 K with step of 25K as shown from the
top to bottom. A culTent limit of 10 mA was set during the measurement. The I-V
characteristics shown in figure 6 can be divided into three regions: (a) a low bias region
which has small temperature dependence, (b) a medium bias region which has strong
temperature dependence, and (c) a resistive region at high injection levels. The different
temperature dependencies n regions (a) and (b) suggests that the fonner is likely a
tunneling current and the latter a thennionic emission current [16]. A general method is
presented to design microwave schottky diodes for detection and mixing, based on
colTelations between imposed microwave electrical parameters and stmctural elements in
various polarization and frequency regimes. The results allow that the optimization of

7
some of the design parameters and, on the other hand, the choice of suitable technological
solutions [17].

Time-resolved measurements of the current output of OaAs MSM detectors with

finger spacing's between 0.5 and 1.2pm illuminated with 70-fs pulses at 620nm have
been carried out utilizing photoconductive and electro-optic sampling with a
synchronized 70-fs pulse from the same laser system. These techniques allow recording
of the photocurrent pulse shape with sub picoseconds resolution. All in all the Monte
Carlo simulation provides a very satisfying description of the experimental data [ 18].

1.2 Microwave GaAs Schottky diode:

20

Schottky metal
100

schottky
contact

Figure 7: Layout of the prepared Schottky diode

The figure 7 shows the layout of the prepared Schottky diode, where one of the
dimensions of the Schottky contact is given by the thickness of the epitaxial layer on
which the structure is fabricated. The value of cut-off frequency is 130Hz; this is in
discrepancy with the theoretically predicted parameters. This contribution points to the
thickness of the suggested theory and describes the technological improvements, which
should lead to increase limiting frequency [19]. Integrated InP-based mixers can benefit
millimeter and sub millimeter-wave receivers by their potential for LO power
requirements (Pw) and low noise performance. A quasi-optical, InOaAs integrated
antenna-mixer was demonstrated at 900Hz and obtained intrinsic noise and conversion
loss perfonnance on par with state-of-the-art planar OaAs mixer diodes [20].

8
 400 -
.......... PBWO,max= 2.6 m'V
~
1 m\V
! 300
.,... .... PB,VO,nu..;: =

0.5 m\V
.
-~' <M- PB,VO,max=
-
:.fa
~ :zoo
l(
•

..... -
~
~
;II{
J{
,/
II)
.... ...............
-
if.
,_ 'W: ,.
......... ....
~ ......
J:J,;.-"" .t~
:>
~~
.:!:I
0
100 !It ' .... ;&...-"" fll"--
l:r'- -_
-- - -- ~~ .......-
i'-'
- ...
--- ----- -- --------
0
575 580 585 590 595 600 605 610 615 620 625
Frequency (Ghz)

Figure 8: Measured voltage responsivity of the mixer at high RF power levels

Figure 8 shows the voltage responsivities of the flip-chip diode rrrixer for different
LO power levels. The results show voltage responsivities of up to 350 mV/mW. The
increasing responsivity for lower RE power levels clearly demonstrates the effect of
compression of the diode in detector operation. The 1dB compression point of the
implemented Schottky diode is typically at a power level of approximately -10 dBm [21].

1.3 Gallium Arsenide wafer and its Interconnections:

Planar GaAs IC
First-Second
Second-level Second-level
Insulator Insulator
Substrate

~:J

SEMI-INSD'"LATING GaAs

Ohmic Contact First Level Interconnect

Metal

Figure 9: Cut-way view of GaAs wafer and its interconnections

9
 The high speed digital integrated circuits are fabricated using a planar process
which features multiple localized ion implantations directly into semi-insulating GaAs
substrates. The figure 9 depicts this process, as it is used to implement Schottky diode
FET Logic (SDFL) circuitry. The NOR gate is the primary SDFL building block,
designed with Schottky diodes perfonning the OR function, and a common source
depletion mode MESFET performing the inversion mode [22]. A level shifting diode and
pull down transistor provide the proper gate bias to the common source switching
transistor. Radiation upset, caused by charge trapping in the substrate, is very similar to
the back gating effect. Therefore, steps taken to reduce back gating are also effective in
reducing radiation effects, as is exemplified by the fact that an implanted p region
reduces both back gating and radiation transients [23].

- - simulated
******calculated

(1'1)-
p::
0
E-<
2.0 - ..,,3
1 0~0.3 \/
0 . 04 v
0.05 v
u 4 0.06 v
~ 1.8 .. 5 () 07 v

b
~
~
1.6 -
8 1.4

1.2 .•

1.0
50 100 150 200 250 300
TEMPERATURE (K)

Figure 10: Ideality factor as a function of temperature

The value of ideality factor is depicted in figure 10 as a function of temperature

for various standard deviations. Clearly, the ideality factor increases slowly in the
beginning but quite rapidly afterward with a decrease in temperature [24]. A more
systematic, computer-fitting approach is suggested for extracting the values of the

10
ideality factor n and the series resistance R, from the I-V characteristics of schottky
diodes. Consistent results have been obtained for both commercial and homemade
schottky diodes in the regime where the series resistance is low [25]. Limitations of
conventional drift-diffusion models for schottky diodes under fiat band conditions and
their influence on the design of schottky mixers have been analyzed. Monte Carlo
simulations have been employed to get a better of the physics inside the Schottky diodes
and to extend the validity of drift-diffusion based models in flat band regime [26]. Data
of the electron mobility from the magneto transport investigation of structures with the
modulation-doped barrier nearest to the surface are unprecise because of a high mobility
conductive bypass in the bulk GainAs(P) layers used in typical structures [27]. The upper
and lower interfaces of InP/GainAs(P)/InP QWs may be conveniently studied in such
structures. These have a very low conductive bypass. This pennits study of the scattering
processes at the two interfaces which become particularly evident when decreasing the
width [28].

The barrier height found by C/V measurements increased as the temperature

decreased and was consistent with the pinning of the Fermi level at the valence band. The
barrier height found by JN measurements decreased as the temperature decreased; and
this is due to the impmiance of generation recombination at lower temperatures. From
DLTS measurements, a trap is found at 219 mev with a density of 7.18Xl0 13 cm-3 . The
origin of this trap is not known with any certainity, and more tests should be done [29].
The well-rectifying schottky diodes are made on highly doped thiophene thin films, using
the eutectic Ga, In alloy as the schottky metal contact. Studies show that an interaction
between the in-diffusing metal and the oligo well-rectifying schottky diodes are made on
highly doped thiophene thin films, using the eutectic Ga, in alloy as the schottky metal
contact. Studies show that an interaction between the in-diffusing metal and the oligomer
occurs, which causes an effective (pmiial) undoping of the highly doped semiconductor
at the Schottky metal interface (formation of a p-layer on a bulk semiconductor p+layer)
[30]. The decrease of the number of ionizable acceptors at the surface is correlated with
the contact time and is probably due to the in diffusion of the Schottky metals and the
ongoing chemical reaction between the Schottky metal and the film. Simultaneously with
the undoping an eventually well rectifying barrier on the p- layer is formed. The full

11
Schottky barrier height stays constant with time [31]. The assumption of an ideal
absorbing boundary may not be correct for very high forward bias condition where the
injection probability cannot be negligible. A proper boundary condition which includes
the probability from the Schottky contact back into semiconductor may be necessary for
the accurate prediction of current density [32]. The application of the MBE grown device
may be in areas as high frequency detectors and microwave mixers. These devices are
usually operated at very low bias conditions in order to reduce power consumption. The
MC results show that such devices can be operated at high forward biases to take
advantage of higher speed perfonnance in spite of a minor increase in power
consumption [33].

A complete analysis of dopants diffusions was presented including both

interstitial and vacancy contributions. The understanding of the enhancement or
retardation of arsenic diffusion in the presence of both high and low concentrations of
point defects are presented. It was demonstrated that point-defects concentrations cannot
be deduced systematically from phosphorus and antimony diffusivities, in contrast with
previous approaches [34]. The donor impurities in AlGaAs and other alloys exhibit a
bistable behavior between the ordinary substitutional configuration and a lattice distorted
one that results in two distinct spectra of electronic states. The ground state of the
distorted configuration is known as the DX center. Forwardly biased Schottky diodes
made on Te-doped AIGaSb are very attractive to investigate hole capture at DX centers.
A significant modifications of the space charge distribution can be easily obtained at low-
temperature under steady state forward bias using cunent densities at least one order of
magnitude lower than those needed for similar experiments in Si-doped AlGaAs. Using
forward-bias filling pulses, a positive deep level transient spectroscopy (DLTS) signal has
been systematically detected in all the samples studied. This positive peak can be
ascribed to electron capture that follows the hole capture at the DX centers during the
filling pulse [3 5].

12
 I
(a) (b) ,-(c)
8

zb~
6

H
(/) 4 ~

(/)
(-i
2
~
~·
0

-2
0.50 0.60 0.70 0.80 0.90
BARRIER HEIGHT (eV)

Figure 11: The peak intensity ofDLTS signal vs. the Schottky barrier height

The figure 11 describes that there are basically three regions described as follows:
(a) Saturation region: the signal reaches its maximum for barrier heights higher than
0.83eV (b) Transition region: the signal decreases along with the batTier heights
decreasing from 0.83 to 0.62 eV and (c) Disappearance region: the signal is not observed
for barrier heights lower than 0.62 eV [36]. SBDs with moderately high barrier heights
(0.83 eV) on low doped (1 X 10 14/ cm3) n-Si can be used to detect minority-carrier traps
in the substrate, provided the SBDs are forward biased during the DLTS filling pulse.
The use of a forward-bias pulse to assist minority-carrier injection eases the requirement
of using ultrahigh barrier height SBD's, as was previously used to detect minority-carrier
defects in Si [3 7]. The long time constant of the aging process, the ability of the barrier
height to recover after aging, the long time constant of the recovery process, and the
acceleration of the recovery process suggest that the changes in the barrier height which
occur upon electrical aging are due to the creation and/or am1ihilation of deep level traps
near the interface [38]. The diffusion equation for an illuminated schottky batTier is
solved for a finite lifetime of photo injected minority carriers within the barrier. The
general solutions are related to parabolic cylinder functions when diffusivity and mobility
are constant [39].

13
 I~:::'"":-.--. :. -,:•-•-,-,-.-:-~:,..._-,-:-I...,_....}-..~'1 "'!"' : -~:-.:.~; .. .•i·-:.• -,_......
::-,.-.-.-: -:-,-~-;~ - -~-~,. . _._~- -~-
....
[-. .....-_---"!-

:::: ::::::- ~' ' . :::::: ~:::: ;~ ~: --x:b.1Ji3

.....-.'-~>2
100
~.
_.. 1fb2D:il212
'j : <· : : - Me!lsured •
' I ,
10 .. -.---.----.·:· ~ ·-. ·:- ---~----r---~--7-. ----:-~. -~~-
- - - -·- - - - ..... - - . -
• - - - •• ~ - •• ..! • ~ ~ --
. - . -
- - -.
'
--- - -
•

.
~ -' ~

' ·-- --~-,·: :·-_. •., ..-:-· . . . ..

.' . - _.-.-- ~-~--::.-,.. - ---·.:. }-~-;
1 ----- -?'~--:: - :·--:··:. ·--------:--!: :·- ··::·:·--:--·--r --_:.._··:---_.- ---~- ,- . . .:-
.T·.----~-- ~---- :~

- ~ - -·- - - - - - - - ~ . - - .. - ·- - .
·- .. l - . -
....

0 500 1000 1500 2000 2500

Frequency (GHz)

Figure 12: Predicted and measured output power for a variety of chain
configuration at an operating temperature of 120 K.

The figure 12 shows predicted output power for a variety of chain configurations.
The assumed chain input power decreases linearly from 200 m W at 70 GHz to 60 m W at
150 GHz [40]. The chain input power for the measurements was 150 mW in the 92-106
GHz band. Note that different configurations with the same output frequency may have
different input frequencies [41]. A planar grid of 100 Schottky diodes suitable for use as a
quasi-optically coupled mixer. A simple transmission line model for predicting the
reflection coefficient of the grid to a normally incident plane wave has been developed.
[42]. A novel technique for monolithically integration of trench power JFET and schottky
diode is proposed in order to achieve higher cell density, comparable on-resistance and
blocking capability with the trench MOSFET. Two approaches for the integrated schottky
diode structure are analyzed and compared to their p-n counterpart. Both schottky
structures show a lower forward voltage drop and smaller stored charge than their p-n
counterpart. [43].

14
1.4 Graphene Nanoribbon (GNR) Schottky diode:

20

~ Up-Conversion {dB)
~ IP3(dBm)

6 7 8 9 10
IF Frequency (GHz)

Figure 13: Up-conversion loss and Performance

The figure 13 describes two different Schottky contacts fonn two ends of the p-
type Graphene Nanoribbon (GNR). Al metal at the source contact makes a large Schottky
barrier while Ag metal at the drain contact creates a small Schottky barrier [44]. (GNR), a
narrow band of graphene, is particularly favorable for FET applications. This is based on
width-tunable bandgap of GNR, and near ballistic transport along the GNR channel. Such
ballistic transport comes from very high mobility in the GNR. A model of double gate
GNR Schottky diode has been performed with p-type semiconducting GNR and
asymmetric contacts as shown in figure 14. This kind of Schottky diode shows a good
rectification performance. A rectification ratio of 2x10 7 is obtained for anN (Ribbon
Index)= 1OGNR at a low gate bias voltage of 0.2 V. Such presented GNR Schottky diode
has potential to be applied in some applications such as high frequency applications [45].

15
 F onvard Bias +
+ Reverse Bias

I~
TopGatt

Insulator

Insulator
Bottom Gate

Figure 14: Schematic representation of double gate GNR Schottky diode.

-40 Au-nGaAs ./-

_¥
y
-30 / n;;:;L0026
.a·v yi
::t:
to
-~
~
-20
y
~10 image force

0 -1 1 -3 -4 -5 -6 -7 -8 -9 -10
Re'\·erse Bias (v)

Figure 15: Comparisons between the experimental data and the theoretical results
of the Au-nGaAs Schottky diode.

As figure 15 shows that the applied voltage across the interfacial layer is
proportional to the applied reverse bias and the proportionality constant is dependent on
the interfacial layer properties. Comparisons between the developed model and the
experimental results of the fabricated AI -nGaAs Schottky diodes arc made, and general
agreements are obtained. Moreover, it has been demonstrated that the measurements of
the bias-dependent photoelectric barrier height can be used to predict the ideality factor

16
ofthe Schottky diodes operated in the forward bias [47]. In figure 16, the changes of the
Schottky barrier height energy q~B, the conduction band edge Ec in the bulk
semiconductor, and the interface fermi-level EFi with the applied voltage are
schematically shown, where the metal fermi energy is taken as a zero of energy. The
increase of q~B is nearly the same order of magnitude as that in EFi. and EFi hardly moves
relative to the conduction band edge at the interface. This is considered to be the first
direct observation of the Penni level pinning behavior under applied voltage [48].

1
GaAs

0.8

Efi
0
0 0.1 0.2 0.3 0.4
Bias Voltage (V)

Figure 16: Variations of the EFi' the in bulk semiconductor, and the q(f)B, i.e., the
conduction band minimum at the interface with the applied voltage.

Where,

Intrinsic Fermi level = EFi

Top of Schottky barrier= q<.pB

Conduction band minimum= Ec at K (wave vector)= 0

The results of a non-linear analysis have been used in determining the level of
distortion generated by the MESFET in RF and microwave control applications. The
results, applied to series connected MESFET switches and attenuators, show good

17
agreement with experimental measurements and indicate that those parameters that
improve power handling and MESFET switch also give improved distortion
performance. The results were also used in comparsion of the MESFET and the PIN
diode as switching elements [49].

10

8 ........ . - ~

DC
~
tj,

19 6
84
·~
r!5 ;
2 /
l
''
0
0 1 2 3 4 5
Drain Voltage (Vds)

Figure 17: Typical 1- V characteristics of GaAs MESFET

The figure 17 shows the I-V data for GaAs MESFET' s with parameters that can
be related to the physics of the diode. The improved fit to I-V curves results in a better fit
of small signal parameters over bias. Results on the aging of surface baniers have been
obtained by combining electrical measurements and surface analysis techniques using ion
beams. In contrast to the theories of rectification at the metal-semiconductor contact
(Schottky theory or Bardeen theory), they demonstrate the large influence of oxygen and
of its reaction with contacting metal [50].

18
 100000

10000

~
~

k;·
-~ 1000
0
11
j
100

10
0.5 0.6 0.7 0.8 0.9 1.0 1.1

Applied Voltage (V)

Figure 18: Current voltage characteristics of the Schottky barrier diode

The curr-ent voltage characteristics of the schottky barr-ier diode under forward
bias condition are shown in figure 18. The solid line represents the I-V characteristics
where no traps are considered. Due to the presence of barr-ier, only voltages higher than
0.5V can be reliably simulated. In each curve, two main transport regimes that
characterize the SBD behavior can be distinguished. An ensemble Monte Carlo
simulation has been used to investigate the static characteristics and noise spectra of a
GaAs Schottky barr-ier diode where Generation Recombination (GR) processes of
electron with traps are included in the active n region of the diode. Two main behaviors
are distinguished depending on the Operating point. In the exponential region of the I-V
characteristics, no influence of GR processes on the noise are observed at low frequency,
but an important noise reduction at higher frequencies around the returning-carr-iers peak
takes place [51]. The Re/GaAs Schottky diode, even annealed at 800°C for 20s, exhibits a
good ideality factor of ~1.14, a barr-ier height of about 0.65-0.71eV, and a low sheet
resistance of less than IOn. With the Re/GaAs annealed at 900°C or higher, an apparent
degradation of the rectifying behavior can be observed [52].

19
 240K
300K
340K

-1.0 -0.0 -0.2 0.2 0.6 1.0

Reverse Bias (V)

Figure 19: Plot of C 2 vs. V for n-type AJJGaAs diodes

Diodes are made using both n-type and p-type GaAs, with Nd = lAx 10 16 cm-3 and
Na = 3.0xl0 16 cm·3 . The figure 19 describes the C-V characteristics which were measured
over a range from 200 to 400K, the capacitance measurements being made at a frequency
of lMHz. The ideality factors for the I-V characteristics were not greater than 1.03 over
2
the entire temperature range and the C vs. V plots were indistinguishable :fi·om straight
lines. The quality of both the n-type and p-type diodes are demonstrated by the electrical
characteristics shown in figure 18 [53]. The reason for the temperature dependence
barrier height of planar doped barriers diode (PDBD) is investigated. It has been found,
that the electron spill-over effect plays an impmiant role in the functioning of PDBDs,
especially in the case of low barrier PDBDs. This effect is a sensitive function of the
temperature, which changes the electric field distribution in the undoped layer and
therefore the barrier height [54].

20
 w-3

104
J (Aicm)

10-6

•
lQ-7 1..........-....L..--"---~~~...J-----1'------1

0 0.1 0.2 03

Figure 20: Theoretical and experimental values of current-voltage

characteristics for Au-Si Schottky barriers.

Theoretical and experimental values of typical current-voltage characteristics for

Au-Si Schottky barriers are shown in figure 20. We note that the cmrent density can be
expressed as

J = Js [exp (qV/17kT) -1] (1.1)

Where,

Js =saturation current density

11 = ideality factor
K = Holtzman Constant
T =Ambient Temperature= 300 K

21
1.5 Ideality Factor and Barrier height for GaAs:

11 = ideality factor

(a)

Au-si
10·3

-~'
104

~ I0-5
~
~ 10·6 . 300K
8
·-ra
~
(.1)
10·~

to-s

lQ·lO '---..L....---'~............................~...---
1014 1015 1016 1017 tOlS JQl9

1.6

L4

1.2

LO .e:::~-~~~::......~:............J
1014 10 :5 10 16 10n 10 rs 10 19
(b)

Doping Concentration (cm-3)

Figure 21: (a) Saturation current density versus doping concentration for Au-Si
barriers at three temperatures

(b) Ideality factor 11 versus doping concentration

22
 The saturation current density and n are plotted in figure 21 for Au-Si diodes as a
function of doping concentration with temperature as a parameter. The ideality factor 11 is
very close to unity at low doping and high temperature. However, it can depart
substantially from unity when the doping is increased or temperature is lowered.

- --· - -·-·

pt-si
0.9 0.9
I
::<:',\
Q
"
ptsi-si
/ \
~ -../
I

~ pt-GaAs
0
0
r<i 0.8 0.8
"ta
i"ID
::t:: Al-si
[l
-~ 0.7 0.7
P=l
\V-S!

0.6 L-_........___ __.__--~. _ __._ _,__.....__..J. 0.6

0 200 400 600 800 1000 1200
Annealing Tempemture ('C)

Figure 22: Barrier heights on n-type Si and GaAs measured at room temperature
after annealing at various temperatures.

The figure 22 shows the barrier heights on n-type Si and GaAs measured at room
temperature after annealing at various temperatures. The barrier height of a pt-Si diode is
0.9V. After annealing at 300°C or higher temperatures, pt-Si is fonned at the interface
and Cf>bn decreases to 0.85V. For pt-GaAs contact the barrier height increases from 0.84V
to 0.87V when PtAs2 is formed at the interface. When an Al-Si diode is annealed above
450°C, the barrier begins to increase presumably due to diffusion of Si in Al. For a W-Si
diode the barrier height remains constant until the annealing temperature is above
1000°C, where WSh is fonned.

23
 /
0.4 . //
/
/ ///
/
i
·~
/ / 0.4
IJ:: 0.5 // / /
/ /
~ / /
·~ / /
~ / 0.5
iU 0.6 I
·.Eiu / /
~ / /
r..tl
..... / GaAs {0.7) / 0.6
1./).
// /
I
/
L '0.7
0.8

1 2 3 4 5 6 7 8 9 10
sm
GaA.s Effective Barriet· Height

Figure 23: Calculated effective barrier height for si and GaAs metal semiconductor
contacts
The calculated effective barrier height as a function of <f>hn is shown in figure 23
for Si and GaAs baniers. By increasing the maximum field from 10 5 V/cm to 106 V/cm,
one generally can reduce the effective banier by 0.2V in Si and 0.3V in GaAs.

24
 Chapter 2

Physics of Schottky diode

The schottky diode (named after Gennan physicist Walter H. Schottky also
known as hot canier diode) is a semiconductor diode with a low forward voltage drop
and a very fast switching action. The cat's-whisker detectors used in the early days
of wireless can be considered as primitive Schottky diodes.

A schottky diode is a special type of diode with a very low forward-voltage drop.
When cunent flows through a diode there is a small voltage drop across the diode
terminals. A normal silicon diode has a voltage drop between 0.6-1.7V, while a schottky
diode voltage drop is between approximately 0.15-0.45V. This lower voltage drop can
provide higher switching speed and better system efficiency

Schematic Symbol:

A schottky diode uses a metal-semiconductor junction as a schottky

banier (instead of a semiconductor-semiconductor junction as in conventional diodes).
This schottky banier results in both very fast switching and low forward voltage drop.
The schottky diode is a "majority canier" semiconductor device. The majority caniers are
quickly injected into the conduction band of the metal contact on the other side of the
diode to become free moving electrons. Therefore no slow, random recombination of n-
and p- type caniers is involved, so that this diode can cease conduction faster than an
ordinary p-n rectifier diode. This property in turn allows a smaller device area, which also
makes for a faster transition. This is another reason why schottky diodes are useful in
switch-mode power converters; the high speed of the diode means that the circuit can
operate at frequencies in the range 200kHz to 2MHz, allowing the use of
small inductors and capacitors with greater efficiency than would be possible with other
diode types. Small-area Schottky diodes are the heart of RF detectors and mixers, which
often operate up to 500Hz. A Schottky diode is a special type of diode with a very low

25
forward-voltage drop, approximately between 0.15-0.45V; this lower voltage drop
translates into higher system efficiency [55-57].

2.1 Benefits of Schottky Diode:

The incorporation of a SiC schottky-type rectifier in typical power-electronic

systems, such as motor drive circuits The prime benefit of the Sic schottky diode lies in
its ability to switch fast (<50 ns) and with almost no reverse and switching power
supplies, will virtually eliminate the switching losses. In the forward bias,
Ti schottky diode provides a forward cunent density of 100 A/cm2 at a forward drop of
1.15V, at room temperature. However, the low banier height of Ti Schottky diode results
in a very high room temperature leakage cunent density of 300~cm2 at 500V.
Fmihermore, the leakage cunent becomes unacceptable at temperatures higher than
100°C. A 4H-SiC merged PiN Schottky (MPS) diode uses interdigitated p +regions
between Schottky contacts to limit the electric field at the Schottky interface during the
off-state operation of the device. It has a low on-state voltage drop and fast switching of
a Schottky diode and offers a low off-state leakage current like the PiN diode. The on-
state and off-state perfonnance was optimized by analyzing the effect of adjacent
p +region width and spacing by 2D device simulations [58-59].

Where,

<rm Work function of metal

=

<j)Bn = Banier height (without image-force lowering)

<p 0 = N eutrallevel (above E) of interface states

1:1= Potential across interfacial layer

X= Electron affinity of semiconductor

\j/bi =Built-in potential

8 = Thickness of interfacial layer

26
 q/1

qz
!
f
q 'l'bi

~---...l.._--Ev

Figure 24: Detailed energy-band diagram of a metal-n-semiconductor contact with

an interfacial layer (vacuum) of the order of atomic distance.

Qsc = Space-charge density in semiconductor

Qss = Interface-trap charge

QM = Surface-charge density on metal

Dit = Interface-trap density

Es = Permittivity of semiconductor

£1= Permittivity of interfacial layer

The various parameters used in derivation that follows are defined in this figure
24. The first quantity of interest is the energy level qcp 0 above E, at the semiconductor
surface. It is called the neutral level above which the states are of acceptor type (neutral
when empty, negatively charged when full) and below which the states are of donor type
(neutral when full of electrons, positively charged when empty). Consequently, when the
Fermi level at the surface coincides with this neutral level, the net interface-trap charge is
zero. This energy level also tends to pin the semiconductor Fenni level at the surface
before the metal contact was formed. The second quantity is qcpBn, the banier height of

27
the metal-semiconductor contact; it is this bmrier that must be surmounted by electrons
flowing from the metal into the semiconductor. The interfacial layer will be assumed to
have a thickness of a few angstroms and will therefore be essentially transparent to
electrons.

2.2 Image-Force Lowering:

The image-force lowering, also known as the schottky effect or schottky-barrier lowering
is the image-force-induced lowering of the barrier energy for charge carrier emission, in
the presence of an electric field. Consider a metal-vacuum system first. The figure 25
shows the minimum energy necessary for an electron to escape into vacuum from an
initial energy at the fenni level is the work. When an electron is at a distance x from the
metal, a positive charge will be induced function q<pm as shown. The effective barrier is
lowered when an electric field is applied to the surface. The lowering is due to the
combined effects of the field and the image force on the metal surface. The force of
attraction between the electron and the induced positive charge is equivalent to the force
that would exist between the electron and an equal positive charge located at 'x'.

E
Metal Vacuum
0 Xm
TT
q!11/J
~~-----.--------------------------~-------~.~-~~x
~.....
..... .....
----- \
/ '>""' , Image potential energy
I '"'-

Figure 25: Energy-band diagram between a metal surface and a vacuum. The metal
work function is qlfJm·

28
 This positive charge is referred to as the image charge. The attractive force toward
the metal, called the image force, is given by

(2.1)

Where,

Eo= Permittivity of free space

q =Electron Charge (1.602 x 10-19) coulombs

The work done to an electron in the course of its transfer from infinity to the
point x is given by

E (x) = fx Fdx = -q2/16rrE

00 0X (2.2)

..,._:::.;....---=·Ec (V> 0)
- - - - -- Ef

-----Ec<V < 0)
Metal Semiconductor ~ .. - - ·e,..
~·

Figure 26: Energy diagram incorporating the Schottky effect for a metal on n-type
semiconductor under different biasing conditions.

The figure 26 shows the energy diagram incorporating the Schottky effect for a
metal on n-type semiconductor under different biasing conditions. The intrinsic barrier
height is q<pBno· The barrier height at thennal equilibrium is q<pBn· The barrier lowerings
under forward and reverse bias are Ll<pp & and Ll<pR respectively. Note that for forward
bias (V > 0), the field and the image force are smaller and the barrier height q<pBno- qLl<pp
is slightly larger than the batTier height at zero bias of

29
 (2.3)

For reverse bias (V > 0), the banier height q<pBn0 -qLlq:>R.. is slightly smaller. In
effect, the banier height becomes bias dependant [60-64].

Reducing ¢8 Increasing ¢8

0 a w X 0 a w X

Pt
(a)

X X

lg'ml
(b)

qf..¢s
~
qf..¢81!
-t
q¢B
r Ec
Ec
EF EF
X X

Metal Semiconductor Metal Semiconductor

(c)

Figure 27: Idealized controlled barrier contacts with a thin n +-layer or a thin p +_
layer on an n-type substrate for barrier reduction (left) or barrier increase (right),
respectively.

30
2.3 Barrier-Height Adjustment:

For an ideal Schottky barrier, the barrier height is determined primarily by the
characters of the metal and the metal-semiconductor interface properties and is nearly
independent of the doping. Usual Schottky barriers on a given semiconductor (e.g., nor p-
type Si) therefore give a fmite number of choices for barrier height. However, by
introducing a thin layer (=10 nm or less) of controllable number of dopants on a
semiconductor surface (e.g., by ion implantation), the effective barrier height for a given
metal-semiconductor contact can be varied. This approach is particularly useful in order
to select a metal having the most desirable metallurgical properties required for reliable
device operation and at the same time to be able to adjust the effective batTier height
between this metal and the semiconductor in a controlled manner.

The dashed lines in figure 27 indicate original barrier with unifonn doping. The
figure 27(a) shows the idealized controlled barrier contacts with a thin n+-layer or a thin
p+-layer on an n-type substrate for barrier reduction or barrier increase, respectively.
Consider the reduction of barrier first. The field distribution in figure 27(b) is given by

E =1-Eml + qn1xlcs, for 0 < x <a (2.4a)

= -qnziEs(W- x), for a<x<w (2.4b)

(2.5)

Although the image force lowering contributes to the barrier reduction, generally
the tunneling effect is more significant as shown in figure 27(c). The increased saturation
current due to tunneling for schottky batTier diode is about 10-3 A/cm2, corresponding to
an effective barrier height of 0.6V. The calculated effective barrier height as a function of
Em is shown in figure 28 for Si and GaAs barriers. By increasing the maximum field from
10 5 V/cm to 106 V/cm, one generally can reduce the effective barrier by 0.2V in Si and
over 0.3V in GaAs. The figure 29 shows the measured results of Ni-Si diodes with
shallow antimony implantation on the surface. As the implant dose increases, the
effective barrier height decreases for n-type substrates and increases for p-type substrates
[65-69].

31
 - - - GaAs
0.8 --Si

,-...
(:_ 0.7
.1: '
·-
on
C1)
..c:
''
.....
C1)
0.6
''
'Ed
.0
'
C1) 0.5
.B>
~ '
p..:j 0.4
'
''
0.3
''
.. ' '
1 8 10

Figure 28: Calculated reduced effective barrier height from tunneling for Si and
GaAs metal-semiconductor contacts.
0.8 . - - - - - - - - - - - - - - - - - - ,

,--.
> 0.7
--
-~
G)

c;:,.. 0.6
+->
..0

·-co
( !)
..c: 0.5
.....
G)

·~
..D 0.4
(!)

·-~
.....>
u
0.3
Ni-Si contacts
5 keY, 750°C anneal
i:LI

12
Antimony atoms implanted (10 12 cm-2)

Figure 29: Effective barrier height for holes in p-type substrates and for electrons in
n-type substrates as a function of the implanted antimony dose.

32
 .. •1

1
q¢Bn 4 E
-~FIJ... q¢!!
I
-- -tqv 1
n-semioonductor

Figure 30: Five basic transport processes under forward bias. (1) Thermionic
emission. (2) Tunneling. (3) Recombination. (4) Diffusion of electrons. (5) Diffusion
of holes.

2.4 Current Transport Process:

The current transport in metal-semiconductor contacts is due mainly to majority

carriers, in contrast to p-n junctions where the minority carriers are responsible. The
figure 30 shows five basic transport processes under forward bias (the inverse processes
occur under reverse bias). These five processes are (1) emission of electrons from the
semiconductor over the potential barrier into the metal [the dominant process for
Schottky diodes with moderately doped semiconductors (e.g., Si with ND :S 10 17cm-3)
operated at moderate temperatures (e.g., 300K), (2) quantum mechanical tunneling of
electrons through the barrier (impmiant for heavily doped semiconductors and
responsible for most ohmic contacts), (3) recombination in the space-charge region
[identical to the recombination process in a p-n junction (4) diffusion of electrons in the
depletion region, and (5) holes injected from the metal that diffuse into the semiconductor
(equivalent to recombination in the neutral region) [70-72].

Thermionic-Emission Theory:

The thermionic-emission theory by Bethe is derived from the assumptions that (1)
the barrier height q<pBn is much larger than kT, (2) thermal equilibrium is established at

33
the plane that detennines emission, and (3) the existence of a net current flow does not
affect this equilibrium so that one can superimpose two current fluxes-ne from metal to
semiconductor, the other from semiconductor to metal, each with a different quasi Fermi
level. If thennionic emission is the limiting mechanism, then EFn is flat throughout the
deletion region (figure 31 ). Because of these assumptions, the shape of the barrier profile
is immaterial and the current flow depends solely on the barrier height.

2 3 2
Js->m= (4rrqm*k /h ) T exp (- q(/)Bn/kT) exp (qV/kT)

A*T2 exp (- qcpBnlkT) exp (qV/kT) (2.6)

and (2.7)

Where,

A* = effective Richardson constant for thermionic emission

The Richardson constant has been determined by neglecting the effects of optical-
photon scattering and quantum mechanical reflection. For free electrons (m* = mo) the
Richardson constant A is 120 A/cm2-K2 . Note that when the image-force lowering is
considered, the barrier height C/)Bn in equation 2.6 will be reduced by Llcp.

Metal n-semiconductor

Figure 31: Energy-band diagram incorporating the Schottky effect to show the
derivations of thermionic-emission-diffusion theory and tunneling
current.

34
 The diffusion of carriers is strongly affected by the potential configuration in the
region through which the diffusion occurs, so we consider the electron potential energy
[Ec(x)] versus distance incorporating the schottky lowering effect as shown in figure 31.
Since the barrier height for electrons moving fi·om the metal into the semiconductor
remains the same under bias, the current flowing into the semiconductor is thus
unaffected by the applied voltage. It must therefore be equal to the current flowing from
the semiconductor into the metal when thennal equilibrium prevails (i.e., when V = 0).
This corresponding current density is obtained from equation 2.6 by setting V = 0,

(2.8)

The total current density is given by the sum of equations 2.6 and 2.8.

Jn =(A *T2exp (-qcpBnlkT)) (exp (qV/kT)- 1)

= hE(exp (qV/kT)- 1) (2.9)

2
Where hE= (A *T exp (-qcpBJkT)

2.5 Tunneling Current:

For more heavily doped semiconductors and/or for operation at low temperatures, the
tunneling current may become more significant. In the extreme of an ohmic contact,
Which is a metal contact on degenerate semiconductor, the tunneling current is the
dominant transport process [73].

35
 140~--------------------------------~
ND or NA = 1016 cm-3
Si
T=300K

~ lOOr-~------------------------------------~
Nl

s
~ Holes
**~

~(V/cm)

Figure 32: Calculated effective Richardson constant A** versus electric field for
metal-silicon barriers.

2.5.1 Thermionic-Emission-Diffusion Theory:

The electron potential energy [or Ec(x)] versus distance(x) incorporating the
Schottky lowering effect is shown in figure 32. Consider the case where the barrier height
is large enough that the charge density between the metal surface and x = W is essentially
that of the ionized donors (i.e., depletion approximation). As drawn, the applied voltage
V between the metal and the semiconductor bulk would give rise to a flow of electrons
toward the metal. The electron quasi-fenni level EFn in the ban·ier is also shown
schematically as a function of distance. Throughout the region between Xm and W.

Where,

W =Edge of the electron depletion layer

Xm = Electron density at point x

The current density can be expressed as

J = nJl11 dEp11/dx (2.10)

Where the electron density at any point x is given by

36
 n = Nc exp (- Ec- EF/kT) (2.11)

Where,

Ec = Conduction Band

Nc =Effective density of states in the conduction band

T =Ambient Temperature= 300 K

The region between x and Wn is considered to be isothermal and that the electron
temperature T is equal to the lattice temperature as shown in figure 31 [7 4].

Figure 33 shows the ratio of the tunneling cunent to the thermionic cunent of a
Au-Si banier diode. Note that for Nn:::; 10 17cm-3 and T 2: 300 K, the ratio is much less
than unity and the tunneling component can be neglected. However, for higher doping
and lower temperatures, the ratio can become much larger than unity, indicating that the
tu1meling cunent becomes dominant. Alternatively, the tunneling cunent can be
expressed analytically and will give more physical insight.

1~~------------------------~

150 200 250 300 350

T(K)

Figure 33: Ratio of Tunneling-current component to the thermionic-current

component of a Au-Si barrier.

37
 Refen·ing to the energy band diagrams in figure 34, we can roughly categorize the
components into three types: (1) thermionic emission (TE) over the barrier, (2) field
emission (FE) near the Fenni level, and (3) thermionic-field emission (TFE) at energy
between TE and FE. While FE is a pure tunneling process, TFE is tunneling of thennally
excited carriers which see a thinner barrier than FE. The relative contributions of these
components depend on both temperature and doping level.

==:>TE

FE

(a) (b)

Figure 34: Energy-band diagrams showing qualitatively tunneling currents in a

Schottky diode under (a) forward bias and (b) reverse bias.

Where,

TE = Thermionic emission

TFE = Thermionic-field emission

FE = Field emission.

2.6 Minority-Carrier Injection:

The Schottky-barrier diode is mainly a majority-carrier device. The minority-

carrier injection ratio y, which is the ratio of minority-cmTier current to total current, is
small because the minority-carrier diffusion is much smaller than the majority-cmTier
thermionic-emission current. However, at sufficiently large forward bias, the drift
component of the minority carriers cannot be ignored anymore and the increased drift
component will increase the overall injection efficiency.

38
 We consider the energy-band diagram shown in figure 35 where x 1 is the
boundary of the depletion layer, and x2 marks the interface between the n-type epitaxial
layer and the n+ highly doped substrate.

L---.-.,
Depletion 1 1
Quasi~neutral
layer t.---t reg1on
I I I
Metall· 1 n-type epitaxial layer - 1 n+-substrate
I I I
0 XI x2
Figure 35: Energy band diagram of a epitaxial Schottky barrier under forwar bias.

It is evident that to reduce the minority-carrier injection ratio (to reduce the
charge storage time to be discussed below) one must use a metal-semiconductor system
with large Nu (Donor concentration) corresponding to low resistivity material, large Ino
(Saturation current density) corresponding to small barrier height, and small ni
(corresponding to large bandgap). Fmihermore, high level bias is to be avoided. As an
example, a gold-n-silicon diode with Nu = 10 15 em -3 and I no = 5 x 1o-7 A/cm2 would give
a low-bias injection Yo of= 5 x 104 . But it would be expected to have an injection ratio of
about 5% at a current density of 350 A/cm 2 [75-78].

39
 H 10.3
z
~
u
10.5 .

1.8 2.4 3.0

VOLTAGE

Figure 36: Temperature dependent forward 1-V characteristics ofPd/n-GaAs

{n=S.lXl0-16 cm-3) Schottky barrier diode.

Section No 1: Equations involved for calculating the current, ideality factor, barrier
heights:

The I-V characteristics of Pd/n-GaAs SBD are shown in figure 36 and can be
described by the thermionic emission model, which can be expressed as

In=Io exp (qvqkT), V;::::3kT/q (2.12)

(2.13)

Where,

In = forward diode current

Io = reverse saturation cmrent

V = applied voltage

k = Boltzmann constant

T = absolute temperature

(flb = Schottky barrier height

40
 A = diode area

A* = effective Richardson constant.

The theoretical value of A*= 120(m*/mo) Acm-2 K-2 and for n-GaAs it comes out to be
8.04A cm-2 K-2 .

The ideality factor can be determined from equation 2.12 and is given by

fJ = q/k:T (dv/dln I) (2.14)

The barrier potential for zero bias and at any bias voltage V can be determined by
equations (2.12) and (2.13) and can be expressed as

Qb = kT In(AA * T2 flo) (2.15a)

Qb (V) = kT In(AA * T 2 flo)+ qV (2.15b)

5 ----- ------~ --- --- - - - - - - - - - - -

0.91
......... Ideality factor

t§
- -Zero-bias barrier
/
\
0.90
b
~
4
/ ffi
m
•><:
I-Ll

b
~
8
3
I .
0.89

0.88
I
t:Q

2 -· - ---- ·----
• 0.87
150 200 250 300
TE:MPER.i\.TURE

Figure 37: Plot of ideality factor and barrier height as a function of temperature for
Pd/n-GaAs SBD.
The ideality factor and the effective barrier height has been evaluated using the
equations 2.14 and 2.15 and the above plot in figure 37 has been are achieved, where the
ideality factor decreases and the barrier height increases with temperature increment [75].

41
 The ideality factor is found to increase with the decrease in temperature, whereas
the batTier height increases with temperature. The variation in the ideality factor with the
temperature has been explained by Chand and Kumar, using Wemer-Gutler's potential
fluctuation model [76]. Accordingly ideality factor can be written a

1!17 = 1-y+ (q£CJs/k:T) (2.16)

Where,

y and £ = voltage coefficients of the barrier height

CJs= conductivity ofthe semiconductor

The variation in the ideality factor with temperature is found to be loosely

exponential in nature and can be described by equation 2.16. As the temperature
increases, more and more electrons gain sufficient energy to surmount the higher barrier.
As a result, the apparent barrier height will increase with the temperature and bias
voltage. An apparent increase in the ideality factor and a decrease in the barrier height at
low temperatures are caused possibly by other effects such as in homogeneities of
thickness and no uniformity of the interfacial charges [77-78]. In order to find the
effective barrier height, the band diagram of Pdln-GaAs Schottky diode is presented in
the figure 38.

- Vacuum energy
~--

Zs=4.07eV
<l>M = 5.12 eV

Figure 38: Band diagram of Pd/n-GaAs Schottky diode.

42
Where,

(j)m = Metal work function

(j)Bo =barrier potential when applied voltage is zero

(j)bi =Built-in potential

W = Depletion Region

43
 Chapter 3

Device Physics of Gallium Arsenide

Gallium arsenide (GaAs) is a compound of the elements gallium and arsenic. It

is IIIN semiconductor. However, the Gallium Arsenide is used in the manufacturing of
devices such as microwave fi·equency integrated circuits (IC's), monolithic microwave
integrated circuits (MMIC's), infi·ared light-emitting diodes, laser diodes, solar cells, and
optical windows.

3.1 Gallium Arsenide Advantages:

GaAs has some electronic properties which are superior to those of silicon. It has
a higher saturated electron velocity and higher electron mobility, allowing transistors
made from it to function at fi·equencies in excess of 250 GHz. Unlike silicon junctions,
GaAs devices are relatively insensitive to heat due to their higher bandgap. Also, GaAs
devices tend to have less noise than silicon devices especially at high fi·equencies which
are a result of higher canier mobility's and lower resistive device parasitics. These
properties recommend GaAs circuitry in mobile phones, satellite communications,
microwave point-to-point links, and higher frequency radar systems. It is used in the
manufacture of Gunn diodes for generation of microwaves.

Another advantage of GaAs is that it has a direct band gap, which means that it
can be used to emit light efficiently. Due to its lower bandgap though, Si LEDs cannot
emit visible light and rather work in IR range while GaAs LEDs function in visible red
light. As a wide direct band gap material and resulting resistance to radiation damage,
GaAs is an excellent material for space electronics and optical windows in high power
applications. Because of its wide bandgap, pure GaAs is highly resistive. Combined with
the high dielectric constant, this property makes GaAs a very good electrical substrate
and unlike Si provides natural isolation between devices and circuits. This has made it an
ideal material for microwave and millimeter wave integrated circuits, MMICs, where
active and essential passive components can readily be produced on a single slice of
GaAs.

44
 One of the first GaAs microprocessors was developed in the early 1980s by
the RCA corporation and was considered for the Star Wars program of the United States
Department of Defense. Those processors were several times faster and several orders of
magnitude more radiation hard than silicon counterpmis, but they were rather
expensive. [S] Other GaAs processors were implemented by the supercomputer vendors Cray
Computer Corporation, Convex, and Alliant in an attempt to stay ahead of the ever-
improving CMOS microprocessor. Cray eventually built one GaAs-based machine in the
early 1990s, the Cray-3, but the effort was not adequately capitalized, and the company
filed for bankruptcy in 1995. Complex layered structures of gallium arsenide in
combination with aluminum arsenide (AlAs) or the alloy AlxGa 1_xAs can be grown
using molecular beam epitaxy (MBE) or usmg metal orgamc vapor phase
epitaxy (MOVPE). Because GaAs and AlAs have almost the same lattice constant, the
layers have very little induced strain, which allows them to be grown almost arbitrarily
thick [79].

3.2 APPLICATIONS OF GALLIUM ARSENIDE:

3.2.1 Solar cells and detectors:

Another important application of GaAs is for high efficiency solar cells. Gallium
arsenide (GaAs) is also known as single-crystalline thin film and are high cost high
efficiency solar cells.

In 1970, the first GaAs heterostructure solar cells were created by the team led
by Zhores Alferov in the USSR. In the early 1980s, the efficiency of the best GaAs solar
cells surpassed that of silicon solar cells, and in the 1990s GaAs solar cells took over
from silicon as the cell type most commonly used for Photovoltaic arrays for satellite
applications.GaAs with germanium and indium gallium phosphide layers were developed
as the basis of a triple junction solar cell which held a record efficiency of over 32% and
can operate also with light as concentrated as 2,000 suns. This kind of solar cell powers
the rovers spirit and oppmiunity, which are exploring Mars surface. Also many solar
cars utilize GaAs in solar arrays. Complex designs of AlxGa 1_xAs-GaAs devices can be

45
sensitive to infrared radiation (QWIP). GaAs diodes can be used for the detection of X-
rays.

3.2.2 Light Emission Devices:

GaAs has been used to produce (near-infrared) laser diodes since 1962. Single
crystals of gallium arsenide can be manufactured by the Bridgeman technique, as
the Czochralski process is difficult for this material due to its mechanical properties.
However, an encapsulated Czochralski method is used to produce ultra-high purity GaAs
for semi-insulators. GaAs is often used a substrate material for the epitaxial growth of
other III-V semiconductors including: InGaAs and GainNAs.

The toxicological propetiies of gallium arsenide have not been thoroughly

investigated. On one hand, due to its arsemc content, it is considered
highly toxic and carcinogenic. On the other hand, the crystal is stable enough that
ingested pieces may be passed with negligible absorption by the body. When ground into
very fine particles, such as in wafer-polishing processes, the high surface area enables
more reaction with water releasing some arsine and/or dissolved arsenic. California lists
gallium arsenide as a carcinogen.

3.2.3 Band Gap:

The band gap of GaAs is 1.42 eV; resulting in photon emission in the infra-red
range. Alloying GaAs with Al to give AlxGar-x.As can extend the band gap into the
visible red range. Unlike Si, the band gap of GaAs is direct, i.e., the transition between
the valence band maximum and conduction band minimum involves no momentum
change and hence does not require a collaborative particle interaction to occur. Photon
generation by inter-band radiative recombination is therefore possible in GaAs. Whereas
in Si, with an indirect band-gap, this process is too inefficient to be of use. The ability to
convert electrical energy into light forms the basis of the use of GaAs, and its alloys, in
optoelectronics; for example in light emitting diodes (LEDs), solid state lasers (light
amplification by the stimulated emission of radiation). A significant drawback of small
band gap semiconductors, such as Si, is that electrons may be thennally promoted from
the valence band to the conduction band. Thus, with increasing temperature the thermal

46
generation of carriers eventually becomes dominant over the intentionally doped level of
carriers. The wider band gap of GaAs gives it the ability to remain 'intentionally'
semiconducting at higher temperatures; GaAs devices are generally more stable to high
temperatures than a similar Si device.

3.2.4 Carrier Density:

The low intrinsic carrier density of GaAs in a pure (undoped) form indicates that
GaAs is intrinsically a very poor conductor and is commonly referred to as being semi-
insulating. This property is usually altered by adding dopants of either the p- (positive) or
n- (negative) type. This semi-insulating property allows many active devices to be grown
on a single substrate, where the semi-insulating GaAs provides the electrical isolation of
each device; an important feature in the miniaturization of electronic circuitry, i.e., VLSI
(very-large-scale-integration) involving over 100,000 components per chip (one chip is
typically between 1 and 10 mm square).

3.2.5 Electron Mobility:

The higher electron mobility in GaAs than in Si potentially means that in devices
where electron transit time is the critical performance parameter, GaAs devices will
operate with higher response times than equivalent Si devices. However, the fact that
hole mobility is similar for both GaAs and Si means that devices relying on cooperative
electron and hole movement, or hole movement alone, show no improvement in response
time when GaAs based.

3.2.6 Crystal Growth:

The bulk crystal growth of GaAs presents a problem of stoichiometric control due
the loss, by evaporation, of arsenic both in the melt and the growing crystal (>ca
(concentration of the crystal growth) 600 °C). Melt growth techniques are, therefore,
designed to enable an overpressure of arsenic above the melt to be maintained, thus
preventing evaporative losses. The loss of arsenic also negates diffusion techniques
commonly used for wafer doping in Si technology; since the diffusion temperatures
required exceed that of arsenic loss.

47
3.2. 7 Crystal Stress:

The thermal gradient and, hence, stress generated in melt grown crystals have
limited the maximum diameter of GaAs wafers (currently 6" diameter compared to over
12" for Si), because with increased wafer diameters the thennal stress generated
dislocation (crystal imperfections) densities eventually becomes unacceptable for device
applications.

3.2.8 Physical Strength:

Gallium arsenide single crystals are very brittle, requiring that considerably
thicker substrates than those employed for Si devices.

3.2.9 Native Oxide:

Gallium arsenide's native oxide is found to be a mixture of non-stoichiometric

gallium and arsenic oxides and elemental arsenic. Thus, the electronic band structure is
found to be severely disrupted causing a breakdown in 'normal' semiconductor behavior
on the GaAs surface. As a consequence, the GaAs MISFET (metal-insulator-
semiconductor-field-effect-transistor) equivalent to the technologically important Si
based MOSFET (metal-oxide-semiconductor-field-effect-transistor) 1s, therefore,
presently unavailable. The passivation of the surface of GaAs is therefore a key issue
when endeavoring to utilize the FET technology using GaAs. Passivation in this
discussion means the reduction in mid-gap band states which destroy the semiconducting
properties of the material [80].

48
 Chapter 4

Synopsys Sentaurus TCAD Device Modeling

Sentaurus Device is an advanced lD, 2D and 3D device-level simulator capable

of simulating the electrical, thermal, and optical characteristics of silicon and compound
semiconductor devices and presents several benefits which include:

Exploration of new device concepts for which fabrication processes are not yet
defined. Characterization of electrical, thennal, and optical behaviour of semiconductor
devices for fast prototyping, development, and optimization of their perfonnance.

Shorten development time by supplementing experimental data with deep

physical insight fi·om simulation. Study of the sensitivity of device characteristics to
process variations for optimizing parametric yields. Generation of electrical data for
SPICE modeling and early-silicon circuit evaluation.

Overview

Introduction to Sentaurus TCAD software:

1. Building the device structure

2. Running the simulation
3. Viewing results
4. Other software

49
Example of Simulation Flow :

Files avail able in SENTAURU S/Seminar/1 ntroducti on

;l"msh.bnd-
bou ndary file Graphs (images
or exported data)
;l"msh.cmd- ;l"des.cmd-
command file commandfile i
l l ;l"des.plt- current file
Mesh
;l"msh .grd - grid file ;\"des .dat- plot files
(structure of mesh)
;l"msh .dat- doping file
(doping at each point)
1
Image files
(E-field etc.)

Figure 39: List of files in Sentaurus TCAD

4.1 Creating Layers and shape with Sprolyt Mask Layer editor:

;.:; xterm
$ prolyt &
[1] 25650
$
****************************************************************************
*** Ligament Layout Editor ***
*** Version C-2009.06 ***
*** (1.0, ia32, linux_gnu) ***
*** ***
*** Copyright (C) 1994-2009 ***
*** Synopsys, Inc. ***
This software and the associated documentation are confidential
***
***
and proprietary to Synopsys, Inc. Your use or disclosure of this ***
software is subject to the terms and conditions of a written ***
license agreement between you, or your company, and Synopsys, Inc. ***

Figure 40: Terminal window command used to draw the mask view of a diode

The figure 40 shows the prolyt & command used to draw the mask view of a diode.

50
1. Type prolyt & at the command line.
2. Click ok on the layout dimensions pop-up that is in the front of the layout editor.
3. Double click on the layer INIT on the left hand side or the editor.
4. In the Edit Layers pop-up change the name of INIT to STRUCT and the color of
STRUCT to red. Click on Modify to update your changes.
5. In the Edit Layers pop-up change the name of STRUCT to PDIFF, and the color
of red to orange. Click on new to update your changes. Repeat this for the Ml
layer to blue.

/home/users8/skc64750/pn/schottky_layout.lyt- Ligament Layout Editor@dcd155.ecs.csun.edu vC-2009.06

Eile £dit Ylew .layer _g_IM Regions CQntacts B.egions Iransformation .!:!elp
-----
Cl ~ ~ l db ~ ~ on Ilit r ' ' ... r t:r. a l• !IJ. r ~ ..f;~ I T + _.!. ,... + -.f [It ++_
1 Mode - - - - -1 ~ 1• 1• 1 • 1 • I· 1 • 1• 1 • 1. • 1 • 1 • .I • 1 • lsel~clline for 2D simulali?nl1 • 1 • 1 • I • 1 • 1 • 1 • 1 • 1

Figure 41: Setting a 2-D cross section for simulation

IE.lkl
Edit Ylow Layer ~IM Ae1J10n• C.~tnlatls Beglon• I•an•formalion tlelp
1Cl ~~.lie, 1i!, ....,Jf~ I_ e.. e. im,. i 1Ef tz.l !l! ~ !lll i ~"" ~_IL_..I._+.!. fi- +_ -J!: It ;:;
1
~---Mode------J Plltlf'''1 1 1"1"1 ~1'1'1'1 '1'1'•'51 1 'I' f'l • t~ 1'1 'I'IIJ •t't'f'l' PI 1 P lq •t•t•l•.f'l't 'PI' Jlt' PI'
;+ ~ [~

I I
Layout :.

!..:-,~-~~- ;. I1: ·,
;~~~~ert----· ~
i Li.J M1
! 1!1 PDIFF
:
~ II I

I
II

~
10
""'" It I .1! I
If I I ! !
It I -~ I
:, I ' I

I I
I '
I
I

II r-1
________
[ ----·----------------' I
.I
: F~J- I.

Figure 42: Prolyt CAD Tool For Mask Pattern Rendering

51
The figure 42 shows the view of the layout editor with all the three layers (M1, PDIFF,
STRUCT).

1. To add an area of STRUCT click on STRUCT in the selection area and click on
the add a new rectangle icon.
2. Draw a Rectangle of any shape or size in the editor window.
3. To edit the coordinates click on the select an existing object icon and then double
click on the rectangle you wish to edit.
4. Double click the upper left hand corner of the rectangle and edit its value to 0, 4.
5. Edit all the coordinates with the values you take.
6. Save the file as diode.lyt. After saving you will notice all your shapes will
disappear. Just click on where the shapes should be and they will re-appeaL
7. Now we would like to simulate a 2-D cross section of the device. We only want
to process half of the device to save simulation time. Click on TCAD in the upper
left comer ofthe editor and the select line for 2-D cross section icon as shown in
figure 41
8. Draw the line according to figure 42 and save your work!

4.2 Creating a process flow with Ligedit:

In the previous section 4.1 we defined the masks for three layers STRUCT,
PDIFF and MI. Here, we will use that mask information in the process run deck and we
will simulate the 2-D cross section area we choose SIM2D.

52
 isedit 8.
25674

*****************'******************************************'***************
*** Ligament Flow Editor
Version C-2009.06
***
***
(1.0, ia32, linux_snu) ***
Cop~risht (C) 1994-2009
***
***
S~nops~s, Inc. ***
This software and the associated documentation are conf:dential
***
and proprietlr~ to S~nops~s, Inc. Your use or disclosure of this ***
***
software is !Ubject to the tet'nls and conditions of a wr:tten ***
license asreeooent between ~ou, or ~our cooopan~, and S~nops~s, Inc. ***

Figure 43: Starting Ligedit

Elle _!idit !:references El:lfensions Help

Variables & Macros

.-----------------------------------rT ._ _:N~a:::m.:.:e______, ___T02y'-"p..::.e_._l __ ~ :.i
1 ~~~-----------N~a=m~e~s______________~-~
J~L~:~--

Process
~ Implant
·Ro li'elif anneal
·Ro #else pattern
PPii' pattern2d
PPii'split epitaxy
PP #header deposit
-j _ _ _ _ _,_ _ _ _ _ _,_ _ _ __j, PP li'endheader etch

Figure 44: Ligedit GUI

53
Start the Ligedit editor by typing Ligedit & at the command line as shown in figure 43.
The editor should start as shown in figure 44.

1. Add a Process Header by going to Edit, Add Process Header.

2. Double Click on environment and the title and set the title to schottky diode.
3. Double Click on simulator and set it to sprocess.
4. Double Click on Graphics and set it to false. This makes sure plots do not pop-up
during simulation.
5. Click on Substrate and double click on dopant type and set it to Boron.
6. Double click on concentration and set it to le16 with a unit of /cm3.
7. Read in the mask data by going to file, and Open Layout. Select the file
schottky_layout.lyt as shown in figure 45.

s Open ···.:j~i~·ln
,; '/:1,. l~r

Qirectory:
- /home/users8/skc64 750/pn ~I g
~ NEW.Iyt
~ PN_Iayout .lyt
~~.

:,
,<;
... ~
r-.J J ... ,··

File name: rschottky_layout.lyt [Epe~ ~

~

Files oftype: Layout files (".lyt) ~I £,ancel

I
Figure 45: Selecting the proper layout file.

To assign the region click on environment, and then double click on region, select
SIM2D3 fi·om the pop-up shown in figure 46.

54
 S Set Actual Argument

Macro Call: environment

Argument: region

Type: r :3irinq
" :J
Can Be Array: ....1

Value Array Size: r

Value: ~'-[s.....
rM-.2D;.;_;3;J_I_ _ _ _ _ _ _Fi.~_'""l

Un~ r ~
String Editor: _____o_pen Text Area _ _j
~----------------------------------------------1

Figure 46: Selecting the proper 2-d cross section

Click on the translate current flow icon. You should see the run deck that has been
created by the GUI. Check to see if the syntax is acceptable for sprocess by clicking on
check translated flow as shown in figure 47.

Save this sprocess run deck by going to file, save translated flow. Save the file as
schottky_diode_fps.cmd as shown in figure 48.

Click on the Go back to editor icon as shown in figure 49.

Save this GUI-Run deck by going to File, Save as shown in figure 50. Call the file
schottky_diode_lig.cmd.

55
S ./firstfinaUig.cmd- Ligam~ent Row Editor@dcdl55.ecs.csu~.edu .A:-2009.06 K.\..M~~~~t
·-'-'-"-'----

Eile §.dit .ereferences El:llensions .!:J.elp

Variables & Macros Flow ] Unfolded Flow ]

---,--------!':James _______ _jf~ Name I Type ___j_ Valu _;

8--..,-~ Flow _f........ <··~ title .. ' String . qua,rter~di I
--T. ::~~·HlQIN!mimmm _

Ji~=t m~~r: ~- ·- · · J~-:~:'f,::}~~~e _ ..

f..~
debug
j....:..{ ..)
. =H- diecld d·
··
j Boolean : true
!.·-~s~o ci11 :e:an n
1 1
:t;a1
1s::e.•
, 1
t""""illll paJtern
.. L·::"'l:l._e!ch_ ... l.:.~.r:J ~~~a~f!~f 1
..• ~~~~~~r •~~i~cess I
t"'"'~~!l!C.~ ;
i"'"":-11..., depOSit_ j~.::t:;{ie~i}~: -_ . . . ~~riij SIM2b3 -~
)----~2 pttem j.........(...)coordinate_shitt Boolean true
E!.
j......... etch F::. {{output · - · ·string unknown
_ ~Iring . @node@ I"'
l:,::.::t ~~~~~a! j.........(..·) node
r~:-::Ifslde__ -·- - - 'Side front' . .
· ··-·· ~insert --
,J ____L·
lrisert ·
--
' msert"
~-~~::.:··-~:~-9~~~-nf - - --~ ---------- -_j--

SWB Generic Process

1 .fit il'lf ----._'C"1- -g) comment-- ,J:.. Implant
·Ro il'elif J ~ remark .!).. anneal

J
·flo il'else ~J insert iii pattern
~il'
PP il'split
PP il'header
~~~
'-, ~ save _lin iilp~ernW
epitaxy
..;, deposit
____ __j,.,• PP il'endheader / £1 etch
-..J ~- ____ j ~~.:::--.-..._-~-.
-.....--~
..•

Figure 47: Translated flow into sprocess.

S SaveAs

.Qirectory: ____lh_o_m_el_u_se_r_sB_Is_k_c6_4_7_so_l_pn_ _ _ _...J.--'I £!1

~ PN_diode_fps.cmd ~ SCHOTTKY_diode_li.cl
~ PN_fps.cmd ~ semifinal_des.cmd
es.cmd ~ prof_fps.cmd ~ semis_diode_lig.cmd
g.cmd ~ quarter_diode_lig.cmd ~ semis_fps.cmd
~ quarter_fps.cmd ~ testi ;cmd
~ reverse_des.cmd ~ worldcu_des.cmd
~-BfDJI ~ worldcup_des.cmd

File name: lschottky_diode_fps.cmd

Files of type: Ligament files (".cmd)

Figure 48: File name for Sprocess flow

56
 S ./firstfinal_lig.cmd- Ligament Flow Edito~@dcd155.ecs.csun.edu ~.~~()()9.~6 .f~6\~'*N:.·;j')t,j~i

file ,Edit f_references El:ltensions t[elp

-----·-------~--------------------------------

D ~ ~ -~l j~ ~~ ~ __:·) I {~-- $ -/ I ·~ '?jJ :-=--~=;'=======:;-

Variables & Macros Flow ] Unfolded Flow j ~ ArguijBack to_ Edit Model
1

Figure 49: Going back to Gill editor.

S ./firstfinal_lig.cmd - Ligamen! Flow E

•J" ,.,._,,,, .UII

~ ,Edit f_references El:ltension

,New Ctri+N
Open ... Ctri+O

Save fls ...

- ----
Reload All Ctri+H

Figure 50: Saving the GUI run deck.

Main Flow of Ligament Editor:

file ftlit frererences ~ens!ons .J:!elp

Variables & Macros Flow I Unfolded Flow ·: , ~ Arguments }

Names __j:S I! Name ___j~_j~_l__l!"~-- ~

-~Ill ·II I=Frs_M_ H-lB
L..(-) save
_ _s_lri_n_ _g_ .
Boolean
.q. ·~rler_diode
!rue
I
· · ·Boolean raise
I H-> debu-g BOoiean ratse
j !
-, ,+) H-l chec~l d
an·81Ytical
B·ool~an..
Boolean
iaJse
false
I
i

I! £3:~ ~~iJal'' _
, !j

H-l region
~~i'Ja!"
SIJing
ip_roce!•
iiiMZD3
i
1·

.._-) ~-~~.~~!!1-~~=s~~
H_ ~~o)ei3.!1 tru·e
i H-) ouljlut §lri~9 unmown ·
1
'H-1 no_de Siring @node@
I.I H-l g.~iph(cs
I
I H-l side 'side
Boolean
ironl .
false
I
H-l. deplh_ DJsJance '5 um J
; H··l user_gnd Gnd deiaun
-H-l
I Qrld:fefiiiement GrldRef m9o-afs on norm'
I, J<-)
'I
H-)
H-[t~uJJ:re::m(~d~J!i.,..v~~i:_al
t~upre~~~~l!a=~~ri~~n~?J
!~uprem4~'!'.in,ver!lc~l
Dfst~ce
Dlslanc~
plst~~e
0.5
0:5
0:1
-- um
um
urn
J
,·
1

I II -J..:.:=:.:..:::·,···-:-________·________. _____.J_;.
: 1

1 ::-
11
1
~- -~--~~i:.enl- Ii~;C~~=l,~,;:;.;;;;;,;:;'T"''=
, ·A- telif ~ remart. ; .2, anneal
! ,':j. teiSe
I" ~ Insert I ;a panem
1
1

.
1 I 1 PPt
pp tspiH
! PP theader
111J load
save
1iillpanemld
1 ii epilaxy
: ~ deposit
.
I
.
I
I
J PP tendheader
1 : PP tposlheader
j l! etch
I
I
~
I I
\
L '
PP tendpostheader i
I !,I
1 J 1
PPtset I ,
PPtverbalim I 1 , J
1 ! PPtem I 1

;:_,---------------------=---===.::_--=-.-.::::::-_:r bl1i L J
_j__ i
I j_I __ ..
(Mode: flow: 1irstfinaJ_IIg.cmd

FIGURE 51: Ligament Editor Flow Gill Model

57
 The ligament Flow editor is the graphical representation of a Ligament file. Its
function is to assemble a process flow from macros (predefined language steps and #-
preprocessor directives), local macros and, optionally, library macros. The ligament Flow
editor provides a convenient graphical user interface to edit the process flow as shown in
figure 51.

4.3 Running sprocess and viewing results in Tecplot:

1. In your diode directory type: sprocess diode_fps.cmd as shown in figure 52.

[2] + Done 1iaedi t &

$ sprocess schottky_diode_fps+cmdl

Figure 52: Running the process deck.

2. The simulator should stmi and eventually end with a successful message.

~~I~L~~i
.!::f.!liP

Figure 53: Tecplot

3. Tecplot is a visualization tool that lets you to see the structure of the diode you have
designed as shown in figure 53.

58
 . '\} T'.!<:plot
_f.ile I Edit View
ad...
Data Update

Figure 54: Loading the files to be plotted

4. After Tecplot the files should be loaded as shown in figure 54 to be plotted.

Inspect:

Inspect can be used to display and analyze curves. It features a graphical user
interface (GUI), a script language, and an interactive language for computations with
curves. An Inspect curve is a sequence of points defined an array ofx-coordinates andy-
coordinates.

(';il Read Synopsys File

Filter (Name Search)

/home/users8/skc64750/pn/".[bgtdpi)[dnrealiv][rdntfxl)l

PN_dlode_des.tdr
PN_doping.plx
out_fps.dat
out_fps.dat.gz
out_fps.grd
out_fps.grd.gz
nknown_bnd.tdr

File to be Added
jf'PN_diode_des.plt"
Selected File(s)

-- Remove I

Figure 55: Inspect Plot

59
1. Creates graphs from* .plt files created by sentaurus device as shown in figure 55
2. Contains electrode voltages, currents etc, and "time".
3. Contains data produced by Current Plot (e.g. max electric field).
4. Can graph any pair of data sets.
5. Use inspect to view your electrical results
6. Start inspect by typing inspect & at t command line
7. Go to file, Load dataset and select PN_diode_des.plt as shown in figure 56.
F -·-- -~ ·- · .
-~--~,_..Y>,,~,,7 ,.,~

S Inspect@dcdlSS.ecs.csun,edu vC-2009.06
"'" 1iri'·---"
_.,_ \.;'<''• ..

Eile! £dit .c_urve ~cript E!Stensions

b.oad Dataset... Ctri+L

Jlpdate Datasets Ctri+U
,8utomatically Update Datasets ...
Qelete Datasets

.L.oad Setup ...

~ave Setup ...

B.estore All. ..
Saye All. ..

gxport ·""
Write Bitmap ... Ctri+W
--
Write EPS ...
Write PS ...
Print... Ctri+P

Preferences ...
--- --
E2:5it Ctri+Q

Figure 56: Loading the file to see electrical results.

60
 S inspect@dcdl55.ecs.esun S 1nspect@dcdl55.ecs.csu
:~:~- i$

Eile £dit ~urve ~cri~ Eile £dit ~urve ~cr

---·· .
~~zr~rore.. ~~zr/'i1ror•
.-- Datasets------ -Datasets-------
~~~-:'""""'"'-
PN_diode_des

time time
p::_Sid~-~:_ _ _ _ _'].
r~siae -~---···_ ._]
n_side n_side

buterV:oltage · ' [S QuasiFermiPotential '\

lnnerVoltage
QuasiFermiPotential
J Displacementcurren _·.
eCurrent
Displacementcurren hCurrent
eCurrent -- ,:cifaiClifrent.
hCurrent Charge
r--.----,----''
.·...... l
~j _ _ _ j ~~~L-==.=__J~-~

--·~~~_j To X-Axis

To L~fl- ::.:- Axi~.J

-~ightY-~ J To Right Y- Axis

Figure 57: Assigning X-axis andY-axis

Click on p-side, Outer voltage assign to x axis and p-side, Total Current to left y-axis as
shown in figure 57 we see a forward biased diode's characteristics.

Click on n-side, Outer Voltage x axis. Click on n-side Total Current and assign to left y-
axis, similarly we should see a reverse biased diode's characteristics.

61
 Chapter 5

Results and discussions

The project on GaAs based schottky diode simulation has been found using the synopsys
sentarus TCAD and the results has been discussed below.

Dopu>JConcenlrallon(NeiAciiVe) [crrr'-3]
II LOE~19 0.001
1.4E~18

1.9E~17

Figure 58: 1-V Characteristics of Forward Sdevice.

The figure 58 shows the GaAs based diode current versus diode under forward
bias. The diode starts conducting at the built-in voltage of 2.7V, evaluated by using
indicating the built-in voltages evaluated by using Synopsys Sentaurus TCAD. The
forward resistance has been estimated from the slope and found to be 6K. At the forward
voltage of 50V, the current is obtained in the form of 4mA. The pattern of the plot and
the built in voltage obtained from Matlab agrees well with the Synopsys Sentaurus
TCAD.

62
 0.006

0.005

0,004

0.003

DopiflJConcenlrallon(NeiAclive) [cm'-3] 0.002

• I.OE<I9
1.4E<18
0,001
1.9E<17

Figure 59: 1- V Characteristics of Reverse Sdevice.

The figure 59 shows the diode cun-ent versus diode voltage under reverse biased.
The break down voltage was obtained in the order of 30V, where the cun-ent reaches to
0.6rnA due to avalanche breakdown. The reverse cun-ent estimated from Matlab agrees
well with the result of Synopsys Sentaurus TCAD, where the breakdown voltages are
matching to 30v and the cun-ents are also matching 0.6mA shown in figure 60.

63
 • 0- ~-----·-----------------------·---·--·----------·------------

~: -;/
-

CURRENT '.:i
. I

·-~..---------f._2.~=---------;;_2.,_0------..,-1:';-5--..,.----_+.:10------!-_5--------!

VOLTAGE(\')

Figure 60: Reverse Current estimated in Matlab

The figure 60 shows the diode current versus diode voltage under reverse biased.
The reverse current reaches to 0.6mA estimated from Matlab, which has been conduced
for my independent study. The I-V characteristics under reverse bias extracted from
Matlab, agrees well with the result of Synopsys Sentaurus TCAD.

64
 Figure 61: Doping Concentration

The figure 61 shows the channel doping concentration in the terms of ion dose of
10 15 cm-2 which reflected as blue color representing of 4xl0 15 cm-3 . The N-epi layer
concentration is found to be in the range of 10 19 cm-3 with the color of green. TheN-
substrate concentration is found to be 3.5x10 15 cm-3 . The Aluminum Layer is added by
depositing as a last step for ohmic contact and the color shows dark green.

65
 f,i;o t~ ~ ~,t {~· ~

II ··"~~~ ''-'!~==~

Figure 62: Space Charge

The figure 62 shows the plot of space charge. The plot shows the space charge by
the light blue color representing of 3.1 x 10 12 where, N -substrate shows in the range of-
2.3 x 106 cm-3 with the color of dark blue. The N-epilayer is found to be in the range of
2.1 x 10 15 cm-3 with the green color.

66
 . ···---- ·----·-·-----·-·-"------·-··--------------·--·····--··-··----·-;-···-

Figure 63: Electric Field

The figure 63 shows the plot of electric field versus GaAs bulk space. The plot
shows the maximum electric field at the junction present by the light blue color. For the
electric field of 4.6x 105 V/cm. At the edge of the depletion region the color becomes light
blue to prevent the same electric field. It means that the electric field does not terminate
at the edge of space charge behaving as punch-through diode.

67
 References

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68
13. M. Prevedelli, F. L. Walls, S. P. Beaton, "High-order hannonic mixing with GaAs
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69
25. T. C. Lee, S. Fung, C. D. Beling, "A systematic approach to the measurement of
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26. J. V. Siles, J. Grajal, A.Di Carlo, "Design of Submillimeter Schottky Mixers
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27. G. Gomila, L. Reggiani, "Shot-noise suppression in Schottky barrier diodes",
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29. V. A. Joshkin, V. N. Pavlenko, A. V. Kvit, "High quantum efficiency Schottky
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30. Mason, Whitney Waterman, "Electrical properties of extremely low doped GaSb
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32. E. Roca, Larsen, K. Kyllesbech, "Influence of grain boundary scattering in the
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33. C.G. Hwang, R. W Dutton, "Hot Carrier Transport Effect in Schottky-Barrier
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70
36. Q. Y. Schmidt, M. T. Wu, X.Evans "Effect of Schottky barrier height on EL2
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48. Ikoma, Hideaki Ishida, Toshiki Sato, "Analysis of GaAs Schottky/tunnel metal-
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73
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74
 Appendix A

Input File for Sprocess

set sim_right 4

set sim bottom 5

set sim_top 0

set intersections_STRUCT { {0.0 4.0} }

set intersections_PDIFF { {1.0 3.0} }

set intersections_M1 { {0.5 3.5} }

line y loc=O spa=0.8 tag=left

line y loc=4 spa=0.8 tag=right

line x loc=O spa=0.25 tag=top

line x loc=5 tag=bottom

region GaAs xlo=top xhi=bottom ylo=left yhi=right

init concentration=1e19 field=Phosphorus wafer.orient=100 slice.angle=[CutLine2D 0 0

4 OJ

mgoals on normal.growth.ratio= 1.3 min.nonnal.size=20<nm> max.lateral.size=0.2<um>

deposit material= {GaAs} type= isotropic Phosphorus conc=1e15 rate= {1.0} time=1

deposit material= {Oxide} type= isotropic rate= {1.0} time=0.3

mask name=mask_1_2 segments = {-0.1 0. 5 3. 5 4.1 } negative

photo mask=mask_1_2 thickness= 1

75
etch material= {Oxide} type=anisotropic rate= {10.0} time=l.l

strip Photoresist

deposit material= {Aluminum} type= isotropic rate= {1.0} time=0.25

temp_ramp name=tempramp_1_2 time=1 temp=950

diffuse temp_ramp=tempramp_1_2

grid remesh

contact name=p_side point X=-1.15 y=2.0

contact name=n_side box GaAs xlo=5 xhi=4.5 ylo=O yhi=4

struct dfise=tpsout

SetPlxList {BActive P Active}

WritePlx PN_doping. pix y=2.0 GaAs

## ---- Added process flow header -----

struct smesh=unknown

exit

76
 AppendixB

Input file for Sdevice Forward Bias

File {

* Input Files

Grid= "fpsout_fps.grd"

Doping = "fpsout_fps.dat"

*Output Files

Current = "PN_diode_des.plt"

Plot= "PN- diode- des.tdr"

Output = "PN_diode_des .log"

Electrode {

{ Name="n_side" Voltage=O.O}

{ Name="p_side" Voltage=O.O}

Physics {

eQCvanDmi

EffectivelntrinsicDensity( OldSlotboom)

Mobility(

DopingDep

77
eHighFieldsaturation( GradQuasiFermi)

hHighFieldsaturation( GradQuasiFermi)

Enormal

Recombination(

SRH( DopingDep )

Plot {

eDensity hDensity eCunent hCurrent

Potential SpaceCharge ElectricField

eMobility hMobility eVelocity hVelocity

Doping DonorConcentration AcceptorConcentration

ElectricFieldNector

Math {

Extrapolate *offby default

RelEnControl *on by default

Iterations=20 *default= 50

Notdamped=lOO *default= 1000

78
Solve {

*- Build-up of initial solution:

Coupled(Iterations=lOO){ Poisson}

Coupled { Poisson Electron Hole }

Quasistationary(

InitialStep=O.Ol Increment=1.35

MinStep=le-5 MaxStep=0.2

Goal { Name="n_side" Voltage= 5 }

) { Coupled { Poisson Electron Hole } }

*Forward Bias Sweep

Quasistationary(

InitialStep= 1e-3 Increment= 1. 35

MinStep=le-5 MaxStep=0.05

Goal{ Name="p_side" Voltage= 50}

) { Coupled { Poisson Electron Hole } }

79
 APPENDIXC

INPUT FILE FOR SDEVICE REVERSE BIAS

File {

* Input Files
Grid = "fpsout_fps.grd"

Doping = "fpsout_fps.dat"

* Output Files
Current = "PN_diode_des.plt"

Plot= "PN- diode- des.tdr"

Output = "PN_diode_des.log"

Electrode {

{ Name="n_side" Voltage=O.O}

{ Name="p_side" Voltage=O.O}

Physics {

eQCvanDmi

EffectiveintrinsicDensity( OldSlotboom)

Mobility(

DopingDep

80
eHighFieldsaturation( GradQuasiFenni)

hHighFieldsaturation( GradQuasiFenni )

Enonnal

Recombination(

SRH( DopingDep )

Plot {

eDensity hDensity eCurrent hCurrent

Potential SpaceCharge ElectricField

eMobility hMobility eVelocity hVelocity

Doping DonorConcentration AcceptorConcentration

ElectricField!Vector

Math {

Extrapolate *offby default

RelErrControl *on by default

Iterations=20 *default= 50

Notdamped=lOO *default= 1000

81
Solve {

*-Build-up of initial solution:

Coupled(Iterations= 100) { Poisson }

Coupled { Poisson Electron Hole }

Quasistationary(

Initia1Step=0.01 Increment=1.35

MinStep=le-5 MaxStep=0.2

Goal{ Name="n_side" Voltage= 5}

) { Coupled { Poisson Electron Hole } }

*Reverse Bias Sweep

Quasistationary(

InitialStep=O. 01 Increment= 1. 3 5

Min Step= 1e-5 MaxStep=O .2

Goal{ Name="n_side" Voltage= 5}

) { Coupled { Poisson Electron Hole } }

82