Professional Documents
Culture Documents
-Place
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Lienig
1.2 VLSI Design Flow
© KLMH
System Specification
Partitioning
Architectural Design
ENTITY test is
port a: in bit;
end ENTITY test;
Functional Design Chip Planning
and Logic Design
Physical Design
Clock Tree Synthesis
Physical Verification
DRC and Signoff
LVS Signal Routing
ERC
Fabrication
Timing Closure
Chip
Lienig
VLI Design Styles
© KLMH
Layout editor
Menu Bar Toolbar
Drawing Tools
Layer Palette
Locator
Cell Browser
Layout Windows
Status Bar
© 2011 Springer
3
Lienig
1.3 VLSI Design Styles Vdd Contact
Metal layer
© KLMH
Vdd IN2 Poly layer
IN2
IN1 OUT Diffusion layer
OUT
IN1 p-type
transistor
n-type
GND
transistor
GND
IN1
OUT
IN2
Lienig
1.3 VLSI Design Styles Vdd Contact
Metal layer
© KLMH
Vdd IN2 Poly layer
IN2
IN1 OUT Diffusion layer
OUT
IN1 p-type
transistor
n-type
GND
transistor
GND
IN1
OUT
IN2
Power (Vdd)-Rail
Ground (GND)-Rail
5
Lienig
VLSI Design Styles
© KLMH
Standard cell layout with Standard cell layout using
a feedthrough cell over-the-cell (OTC routing
A A
VDD VDD
GND
A’ GND
A’
Lienig
VLSI Design Styles
© KLMH
Layout with macro cells
RAM
PLA
VDD
RAM
Standard Cell GND
Block
PLA
Lienig
Common EDA Terminology
© KLMH
Connectivity graph
a x a x
N3 N5
N1 N2 z c z c
N4
y
b b y
Lienig
Graph Theory Terminology
© KLMH
Undirected graph with maximum node degree 3 Directed tree
b a
a
f b c d
c
e g e f g h i j k
d
Lienig
Graph Theory Terminology
© KLMH
Rectilinear minimum spanning Rectilinear Steiner minimum
tree (RMST) tree (RSMT)
b (2,6) b (2,6)
Steiner point
c (6,4) c (6,4)
a (2,1) a (2,1)
Lienig
Common EDA Terminology
© KLMH
Connectivity matrix
a b x y z c
a 0 0 1 1 0 0
a b 0 0 1 1 0 0
x
x 1 1 0 2 1 0
N3 N5
N1 N2 z c y 1 1 2 0 1 0
N4
z 0 0 1 1 0 1
y
b c 0 0 0 0 1 0
Lienig
Common EDA Terminology
© KLMH
Distance metric between two points P1 (x1,y1) and P2 (x2,y2)
n n
d x2 x1 y2 y1
n
n = 1: Manhattan distance d M ( P1 , P2 ) x2 x1 y 2 y1
P1 (2,4) dM = 7
dE = 5
dM = 7 P2 (6,1)
12
Lienig
Netlist and System Partitioning
© KLMH
Partitioning Algorithms
13
Lienig
Introduction
© KLMH
Circuit: 1 Cut cb
3
2
7 8
4
6
5
Cut ca
8 3 4 1 8 5 4 1
7 6 5 2 7 6 3 2
Cut ca: four external connections Cut cb: two external connections
14
Lienig
Kernighan-Lin (KL) Algorithm – Example
© KLMH
1 5
2 6
3 7
4 8
Cut cost: 9
Not fixed:
1,2,3,4,5,6,7,8
15
Lienig
Kernighan-Lin (KL) Algorithm – Example
© KLMH
1 5
2 6
3 7
4 8
Cut cost: 9
Not fixed:
1,2,3,4,5,6,7,8
16
Lienig
Kernighan-Lin (KL) Algorithm – Example
© KLMH
1 5
2 6
3 7
4 8
Cut cost: 9
Not fixed:
1,2,3,4,5,6,7,8
17
Lienig
Kernighan-Lin (KL) Algorithm – Example
© KLMH
1 5 1 5
2 6 2 6
3 7 3 7
4 8 4 8
Cut cost: 9
Not fixed:
1,2,3,4,5,6,7,8
18
Lienig
Kernighan-Lin (KL) Algorithm – Example
© KLMH
1 5 1 5
2 6 2 6
3 7 3 7
4 8 4 8
19
Lienig
Kernighan-Lin (KL) Algorithm – Example
© KLMH
1 5 1 5
2 6 2 6
3 7 3 7
4 8 4 8
20
Lienig
Kernighan-Lin (KL) Algorithm – Example
© KLMH
1 5 1 5 1 5
2 6 2 6 2 6
3 7 3 7 3 7
4 8 4 8 4 8
21
Lienig
Kernighan-Lin (KL) Algorithm – Example
© KLMH
1 5 1 5 1 5 1 5
2 6 2 6 2 6 2 6
3 7 3 7 3 7 3 7
4 8 4 8 4 8 4 8
22
Lienig
Kernighan-Lin (KL) Algorithm – Example
© KLMH
1 5 1 5 1 5 1 5 1 5
2 6 2 6 2 6 2 6 2 6
3 7 3 7 3 7 3 7 3 7
4 8 4 8 4 8 4 8 4 8
Cut cost: 9 Cut cost: 6 Cut cost: 1 Cut cost: 7 Cut cost: 9
Not fixed: Not fixed: Not fixed: Not fixed: Not fixed:
1,2,3,4,5,6,7,8 1,2,4,6,7,8 1,2,7,8 2,8 –
Lienig