Assignement 1- Simulation Test Benches in

Cadence
Rafid Adnan Khan
Department of Electrical and Computer
Engineering
McGill University
Montreal, Canada
rafid.khan@mail.mcgill.ca

Abstract—This report presents simulation of an Op-amp in

Cadence. Transistor level design of a given Op-amp is
implemented in Cadence 65nm platform. Simulations are
performed on the op-amp to obtain its DC, AC and transient
behavior. Test bench setup and results for respective
simulations are demonstrated.

Keywords—Analog Microelectronics, Cadence, Op-amp

I. INTRODUCTION

Op-amp is one the most common building block in

contemporary analog and mixed signal ICs. They can have
multitude of applications encompassing amplification,
buffering, filtering [1].The objective of this work is to 
simulate and demonstrate the required characteristics of a Fig. 2. The plot of drain current of M5 against RB
given op-amp implementation in cadence using 65nm
technology. III. DC ANANLYSIS
The report includes implementation of a two-stage op-
amp design as depicted in figure 1, in the Cadence schematic A. Large Signal, Common Mode (CM), Transfer
composer platform. The schematic implementation is Charactaristics:
converted to a symbol with input, output and power supply A Common mode DC voltage is swept from 0 to Vdd =1V
pins. Then test benches are constructed using the implemented across input with the test bench configuration as shown in
symbol to simulate the DC, AC and transient behavior of the figure 3. The output is plotted against the common mode DC
given op-amp circuit. voltage to obtain the common mode transfer function as
shown in figure 4.
II. DESIGN CHOICES
The transistor sizes of for the circuit implementation of
figure 1 are illustrated in table I. The Cc and CL are chosen to
be 0.5pF and 2pF respectively.

Fig. 3. Test bench setup for common mode transfer characteristics

Fig. 1. The schematic of the CMOS amplifier design

TABLE I. TRANSITOR SIZES FOR THE CMOS AMPLIFIER

The value of RB needs to be selected so that drain current

of transistor M5 is between 85uA to 115uA. Figure 2 shows
the plot of drain current of M5 against RB. From figure 2, RB
is chosen to be 60KΩ where drain current of M5=110uA. Fig. 4. Large signal Common mode transfer characteristics

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B. Large Signal Differentail Mode Transfer
Characteristics:
To obtain differential mode transfer characteristics a common
mode DC Bias of 0.55V, which is approximately at the middle
of linear region of CM transfer characteristics, is applied at the
inputs and a differential mode voltage between the inputs of
the op-amp is applied. Figure 5 illustrates the test bench for
differential mode transfer characteristics. In the figure VDM
is swept from 0 to 1V to obtain the differential mode transfer
characteristics.

Fig. 7. Plot of common mode gain vs frequency

Fig. 5. Test bench to obtain differential mode transfer characteristics

Fig. 8. Plot of differential mode gain vs frequency pointing Differential

Mode Low Frequency gain

Fig. 6. Plot of differential mode transfer characteristics

C. Voltage Offset, Input and Output Voltage Range

From the common mode transfer characteristics, we find,
when the input voltage is at 0V, output is 0.61V as depicted
in figure 4. Thus, the offset for the given amplifier design is
0.61V. The input voltage range for linear amplification is
from 500.77mV to 610.23mV, and corresponding output
voltage range for linear amplification is from 743.7mV to
904mV as depicted from figure 4. Fig. 9. Plot of differential mode gain vs frequency pointing Unity Gain
Band Width and Phase Margin

IV. AC ANALYSIS Figure 7 shows common mode low frequency gain is

A. Common Mode Gain, DM LF GAIN, Unity Bandwidth
Gain and Phase Margin
For Common mode gain, test setup of figure 3 is used,
where VCM=0.55V(DC)+10mV (AC) is applied. For
obtaining differential mode frequency response and phase vs
frequency plot, test bench setup of figure 5 have been used,
where VCM=0.55V (DC) and VDM=10 mV(AC).
5.046dB. From Figure 8, Differential mode low frequency
gain is 49.625dB, and 3dB frequency is at 727.64KHz. From
figure 9, at Differential Mode, Unity Gain Band Width is
222.92MHz and phase at 0dB frequency is -104.9°, hence the
phase margin is the difference between -104.9° and -180°,
which is 75.1°.
B. Open Loop Poles and Zeros:
Open loop poles and zeros obtained with cadence simulation
are shown in Figure 10.
 Figure 12: Finding rms thermal noise level

V. TRANSIENT ANALYSIS
A. Slew Rate, Rise time, Settling Time
Test bench setup for determining slew rate, rise time and
settling time is showed in figure 13. A negative unity
feedback from the output is provided in the setup.

Figure 10. Open Loop Poles and Zeros

C. Spectral Noise Density and RMS thermal noise level
Figure 11 shows the spectral noise of the output signal. It is
observed that the spectral noise decreases exponentially as
the frequency increase, this is due to the effect of the flicker
noise, which is inversely proportional to the frequency.
Fig. 13. Test bench for determining slew rate, rise time, settling time
For determining slew rate V_pulse is set from -1V to 1V and
for rise time and settling time V_pulse is set from -1mV to
1mV with a pulse width of 5ms in both cases. VCM is set to
0.55V

Fig. 11. Spectral noise of the output signal Fig, 14: Plot for determining the slew rate

At low frequency flicker noise dominates the spectral noise,

at very high frequency flicker approaches to very small value,
so at high frequency the spectral noise is essentially
dominated by thermal noise. From cadence noise summary
we obtain the r.m.s level of noise (input referred) at 100GHz
(high frequency) to be 1.43538*10-8 V/Hz, as shown in figure
12. So, rms thermal noise level (input referred) ≈ 1.43538*10-
8
V/Hz

Fig. 15 Plot for determining the rise time

 From figure 17 and 18, maximum input swing is 16mV peak
to peak, and the corresponding maximum output swing is
982.979mV peak to peak.

C. THD for the common mode and differential mode

sinusoidal signals
For finding THD of common mode and differential mode
sinusoidal signals, test bench setup of figure 3 and 5 for
common mode and differential mode operations respectively
are employed. DC bias is set 0.55V, a sinusoid of 1mV
amplitude and 1 KHz frequency is applied. The THDs are
calculated employing Calculator in Cadence as shown in
figure 19 and 20.
Fig. 16. Plot for determining the settling time

From figure 14, 15, and 16 we obtain slew rate as 7.0921*104

V/s, rise time (from 10% to 90% of output) as 1.033us, and
settling time is 3.328us (up to 99% of steady state value of
output) for the particular bias and input.

B. Maximum input/output swing

Figure 5 shows the test setup for determining maximum input
and output swing. The DM input sinusoid starting from 2 mV
(peak to peak) is kept increasing until the output gets distorted
and clipped. For input swing up-to 16mV (peak to peak)/8mV
(peak), undistorted and unclipped output sinusoid is obtained
as depicted figure 17. When the input swing exceeded 16mV,
output sinusoid starts to get distorted gradually as shown in
figure 18.

Fig 17. Plot for maximum input and output swing

Fig 19. THD calculated for differential mode operation

Fig. 18. Plot of slightly distorted output near 1V for input swing 20mV
peak to peak for exceeding the maximum input swing 16mV peak to peak.
 TABLE II. SUMMARY OF SIMULATION RESULTS

Analysis type Parameter Value

DC Rb 60 KΩ
Bias voltage 0.55 V
Input range 500mV- 610mV
Output range 743.7mV- 904mV
AC UGBW 222.92 MHz
DM LF gain 49.625 dB
DM 3dB 727.64 KHz
frequency
Phase Margin 75.1 degree
CM gain 5.046dB
RMS thermal 1.43538*10-8 V/Hz
noise (input
referred)
Transient Slew rate 7.0921*104 V/s
Rise time 1.033us
Settling time 3.328us
CM THD 1.06%
DM THD 24.73%

REFERENCES

[1] Behzad Razavi: ‘Design of Analog CMOS Integrated Circuits’,

(McGraw-Hill Publisher, New York, 2001), p.p. 291. J. Clerk
Maxwell, A Treatise on Electricity and Magnetism, 3rd ed., vol. 2.
Fig 20. THD calculated for common mode operation Oxford: Clarendon, 1892, pp.68–73.
[2] G. W. Roberts, ECSE 534 Analog Microelectronics Course Notes,
From figure 19 and 20, THD calculated for differential mode McGill University
operation and common mode operation are 24.73% and
1.06% respectively.
VI. CONCLUSION
A two stage op-amp implemented 65nm technology in
Cadence platform is simulated to obtain its DC, AC and
Transient characteristics as shown in table II.
 VII. APPENDIX:

Fig. A.1: Schematic of the CMOS amplifier

Fig. A.2: Symbolic Representation of the schematic