ECSE 534

Project (Final Phase)

A First-Order, Single-bit, Lowpass ΔΣ A/D Converter: System
and Circuit Level Implementation

Rafid Adnan Khan

ID: 260837941
Department Electrical and Computer Engineering
McGill University
 A First-Order, Single-bit, Lowpass ΔΣ A/D
Converter: System and Circuit Level
Implementation (Final Phase)
Rafid Adnan Khan
Department of Electrical and Computer
Engineering
McGill University
Montreal, Canada
rafid.khan@mail.mcgill.ca

Abstract— This report includes implementation of a first
order, single bit, low pass ΔΣ A/D Converter. First, the design
is implemented at the system level in Matlab Simulink and
simulated to verify the performance. Then the system level
design is mapped onto a circuit level design employing switched
capacitor. The pre-layout architecture of the circuit is
implemented and then the implemented architecture is laid out
in 65nm CMOS technology using Cadence virtuoso platform.
The simulation results of system level, pre-layout circuit level
and post-layout circuit level are compared. The major causes for
the variation of performance of the A/D converter at different
levels are addressed. Finally, the scopes for optimization and
further improvement are discussed.
Keywords— ΔΣ A/D Converter, 65nm technology, CMOS,
Analog Microelectronics
I. INTRODUCTION
The ΔΣ A/D modulator topology exploits error feedback
of the previous conversion to predict and pre-compensate the
error for the current signal sample [1]. A first order ΔΣ A/D
Converter is depicted in figure 1.
Fig. 1: A first order ΔΣ A/D Converter [1]
The depicted topology can be used to shape the noise in
order to get an exponentially increasing noise curve with
respect to frequency as shown in figure 2 [1]. In the figure, for
an input signal with a frequency of f0, which is oversampled
with frequency fs, noise shaping obtains exponentially
decaying low noise with lowering frequency. The higher noise
introduced at high frequency due to noise shaping can be
filtered out using H(z). Thus, armed with oversampling the
noise shaping topology can potentially reduce the noise within
a lower frequency bandwidth.
In this Project, a first order, single bit, low pass ΔΣ
(Sigma-Delta) A/D Converter is implemented. First, the
design is implemented at the system level in Matlab Simulink
and simulated to verify the system performance. Then the
system level design is mapped onto a circuit level design
employing switched capacitor. The circuit is laid out in
Cadence platform employing 65nm technology. The
simulation results at different stages of the implementation are
compared and the potential reasons causing the discrepancy at
different stages are addressed. Finally, the Further scopes for
improvement are discussed.
II. THEORETICAL CALCULATION
The given bandwidth for the project is found using
equation (1) where α=941/1000
𝑓𝑏𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ = (1 + 𝛼) × 10𝐾𝐻𝑧 = 19.41𝐾𝐻𝑧 (1)
The Target SNDR (peak) is 50dB. The OSR to achieve
required SNRmax can be approximated by equation 2 and the
corresponding Fs can be calculated using equation 3
𝑆𝑁𝑅𝑚𝑎𝑥 −2.61
𝑂𝑆𝑅 = 10( 30
)
(2)
𝐹𝑠 = 𝑂𝑆𝑅 × 2 × 𝑓𝑏𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ (3)
From the above calculation to satisfy the SNRmax of 50dB
(equivalent resolution of 8 bits), minimum OSR of 38 and the
corresponding minimum Fs of 1.48MHz is required.
The circuit level implementation can introduce non-
ideality, nonlinearity and parasitic, which are unaccounted in
the calculations. To ensure the required performance at the
physical implementation level, the system is overdesigned to
get a calculated SNRMAX of 75dB for Fs at 10MHz
(OSR≈258).
III. SYSTEM LEVEL IMPLEMENTION
A first order ΔΣ A/D Converter is implemented in
MATLAB Simulink as shown in figure 3.

Figure 3: Simulink Model for first order ΔΣ A/D Converter

Figure 2: Noise Shaping [1]

A sinusoid of 0.2V amplitude (DC biased at 0.5V) at
12.20703125 KHz is provided as input. The sampling
frequency Fs is 10MHz. The discrete transfer function block
acts as ideal integrator. The relay in forward path acts as a
comparator for analog to digital conversion, switching at
0.5V. The relay in feedback path is acting as DAC (Digital to
Analog converter). Figure 4 shows the signals at different
stages of the ΔΣ A/D Converter Simulink Model.
Figure 4: The input, output, integrator input, integrator output and DAC
output of the ΔΣ A/D Converter Simulink Model
The power from the A/D Converter output is calculated and
the PSD plot is obtained as shown in Figure 5. The frequency
of the input sinusoid, FT=12.20703125KHz=(M/N)*FS
corresponds to M=5 for Fs of 10MHz and N=4096 samples.
It is to be noted that MATLAB starts indexing the frequency
bins from 1 instead of 0. As a result DC is obtained at
Frequency bin number 1 and likewise all other frequency bins
are shifted by 1 bin in the MATLAB plot. Thus the coherent
input signal corresponds to bin number 6 in MATLAB PSD
plot for the given choice of Fs and N.
Figure 5: PSD plot for the Simulink Model
The SNDR can be calculated as follows:
𝑘
𝑃𝑜𝑤𝑒𝑟𝑖=𝑛
SNDR= ∑ (4)
𝑖=2,𝑖≠𝑛 𝑃𝑜𝑤𝑒𝑟𝑖
In equation 4, n represents the frequency bin of the input
sinusoid and k corresponds to frequency bin of the 𝑓𝑏𝑎𝑛𝑑𝑤𝑖𝑑𝑡ℎ
for obtained MATLAB plot (n=6 and k=9 in the depicted
PSD plot for the mentioned choice of Fs and N). As i=1
correspond to the DC in MATLAB, it is neglected.
For setting DAC (Digital to Analog Converter) most positive
and most negative voltages at Vref+=0.5 + A Volts and Vref-
= 0.5 – A Volts respectively, peak SNDR is calculated for
different levels of A using Equation 4. The plot of peak
SNDR as a function of DAC output level is shown in Figure
6. From the figure, peak SNDR of 62.64dB is obtained at
A=0.21V for the given input sinuosid of 0.2V amplitude at
12.20703125 KHz frequency. Thus for the DAC,
Vref+=0.71V and Vref-=0.29V is chosen for
implementation.
Figure 6: SNDR (dB) as function of DAC output level, A (Volts) for
Vref+=0.5 + A Volts and Vref-= 0.5 – A Volts
IV. CIRCUIT LEVEL IMPLEMENTAION (PRE-LAYOUT)
The system level design at Simulink in mapped onto a circuit
level implementation employing switched capacitor as shown
in figure 7. The ΔΣ A/D Converter pre-layout implementation
in Cadence is shown in appendix, Fig. A1.
Figure 7: Circuit level design of the ΔΣ A/D Converter
In figure 7, the major building blocks: switched capacitor,
integrator, comparator, D-Latch, 1 bit DAC are highlighted.
In the next subsections discussions about the mentioned
circuit blocks are elaborated.

A. Switched Capacitor:

Switched capacitor provides an effective way of realizing the

active RC filters in monolithic form. In switched capacitors,
charge transferred during a clock phase is taken out during
another nonoverlapping clock phase, where the two clock
phases are almost at 180° with each other. The equivalent
resistor, Rc of a capacitor, C1 periodically switched at a
frequency of fc can be found with equation (5)
1
𝑅𝐶 = (5)
𝑓𝑐 ∗𝐶1
Here the switched capacitor C1 is chosen as 0.1pF and the
switching frequency, fc is at 10MHz. Figure 8 shows the
switched capacitor implementation.
Figure 9: Transmission Gate
B. Clock
In switched capacitors, charge transferred during a clock
phase is taken out during another nonoverlapping clock
phase. Thus, switched capacitor operation can be achieved
with 2 non overlapping clocks. However, for a 2-phase clock,
charge stored in the channel region of switch can get trapped
in C1. A 4-phase sampling can eliminate amplitude dependent
charge injected by switches [1]. Therefore a 4-phase clock is
preferred. A 4-phase clock implemented with NOR gates and
series of inverters is depicted in Figure 10.

Figure 10: four phase clock

Figure 8: switched capacitor
The 4 phase clock is controlled with the help of a clock signal
which is set at frequency of 10MHz. Figure 11 shows the
The switching is obtained with transmission gates. High clock signal coming at 4 phases from the implemented design
switch resistance is seen for only PMOS switch during low
input voltage or only NMOS switch during high input
voltage. Using both PMOS and NMOS in complementary
manner, transmission gate can resolve the high switching
resistance problem during both low and high input voltage. A
transmission gate can improve the switch transfer
characteristics over full supply range, and it can partially
solve the charge injection problem. Figure 9 shows the
implementation of transmission gate. The implementation of
transmission gate and inverter in Cadence is shown in
appendix, Fig. A4. As the mobility of electrons is almost
twice the mobility of holes, in the transmission gate and the
inverter PMOS width is twice of NMOS width to have a
symmetrical performance. For Transmission gate and
inverter PMOS W/L is 10.4um/0.13um and NMOS W/L is
5.2um/0.13um. Larger the switch, lower the on resistance but
greater the parasitic capacitance. The transmission gate can
be controlled with the help of a clock, which is discussed in
the next subsection Figure 11: Timing Diagram of CLK1, CLK1D, CLK2, CLK2D
C. Integrator is greater than 0.5V, the output produced is at 1V. The same
OTA design of figure 13 with Cc and Rc disconnected is
The integrator together with switched capacitor realizes a employed for the comparator design. Disconnecting the
monolithic active RC filter with transfer function described compensation capacitor Cc can increase the maximum
by equation (6) operating frequency of the comparator by approximately 100
times [1].
Vout 1
= 1 (6)
Vin s( )C
C1 fc 2 E. D-Latch

Here, C1=switched capacitor=0.1pF and C2=integrator D-Latch takes the output signal sample of the comparator and
feedback capacitor=0.1pF and fc=switching frequency stores the sample until the next CLK. Figure 15 depicts the
=10MHz. The time constant of the active RC filter is 0.1us. implemented D-Latch using inverters and transmission gates.
The Latch has two outputs Q and Q_not (inverted form of Q).
The integrator is implemented with an OTA. Figure 12 The D-Latch implementation in Cadence is shown in
depicts the implementation of the integrator. Figure 13 appendix, Fig. A5.
depicts the OTA design. The OTA implementation in
Cadence is shown in appendix, Fig. A3. The OTA has
63.57dB gain and about 10KHz bandwidth. Further details of
design and specification of the OTA is included in
Assignment 2.

Figure 15: Implemented D-Latch

F. 1 Bit Digital to Analog Converter (DAC):

The DAC converts the digital values at the output of ΔΣ A/D

Figure 12: Integrator Implementation
Converter to predefined analog values for negative feedback
at the input in order to pre-compensate for the error
introduced by A/D conversion. The 1bit DAC is
implemented using two transmission gates as depicted in
figure 16.

M1 M2 M3 M4 M5 M6 M7 M8 Figure 16: Implemented 1-bit DAC

L 390 390 390 390 390 390 390 390 From the results obtained in the system level simulation
(nm)
W .91 .91 1.04 1.04 11.18 .39 1.04 4.03
discussed in previous section the most positive and most
(um) negative voltage of the 1 bit DAC is set at Vref+=0.71V and
Component RB RC Cc Vref-=0.29V respectively. The transmission gate that
Value 200KΩ 700Ω 1pF transmits Vref+ is connected to output, Q of the latch and the
transmission gate that transmits Vref- is connected to output
Figure 13: OTA Design
Q̅ (inverted Q) of the latch.

G. Simulated Results of the pre-layout circuit implementation

D. Comparator in the Cadence Analog Environment

The comparator converts the analog input value into digital. The implemented ΔΣ A/D Converter is simulated in cadence
Analog ground, 0.5V is set to be the threshold for the analog analog environment using transient simulation. The sinusoid
to digital conversion. If the comparator input is smaller than of 0.2V amplitude (DC biased at 0.5V) at 12.20703125 KHz
0.5 V the output is produced at 0V and if the comparator input (same as system level) is provided as input and the switching
frequency is at 10MHz (same as system level sampling
frequency). The signal seen at different stages of the
implemented ΔΣ A/D Converter is depicted in Figure 17.
Figure 17: The input, output, DAC output, integrator input and integrator
output (from top to bottom) of the ΔΣ A/D Converter for cadence pre-
layout circuit implementation
Simulation can take too long to converge. Implementing each
clock phase with individual voltage pulse sources instead of
the clock designed, can make the simulation run faster.
Besides, Cadence transient simulation does not produce
uniformly sampled signals. Using the calculator tool in
Cadence the output data is resampled at Fs=10MHz from
time TD to TD + (N-1)/Fs to generate N samples. The start
time TD ensures that the initial transient response diminishes
to a steady state. (Here, TD=409.7us, N=4096 and
Fs=10MHz) The sampled output data is imported to
MATLAB and the power at each frequency bin is computed.
The obtained PSD plot is shown in figure 18.
Figure 18: PSD plot for Cadence prelayout circuit level simulation
The peak SNDR is calculated in the same manner as
described in system level implementation usig equation (4).
The peak SNDR calculated in the prelayout circuit
implementation is computed to be 61.5dB.
V. LAYOUT IMPLEMENTATION OF THE CIRCUIT
The layout of the circuit is implemented at Cadence Virtuoso
in 65nm technology. The resistances and capacitances are
implemented with ‘rnwod’ and ‘mimcap’. All the
components are positioned in the layout so that the length of
the traces for routing is minimized specially along the signal
path to minimize trace parasitic. The implemented layout is
shown in Fig. 20 (Fig. A2 in appendix shows larger and
marked depiction of the Fig. 20).
The layout is checked for DRC errors so that design rules for
manufacturability are satisfied. The layout is simulated
without DRC errors. Also the LVS check demonstrate that
the layout and schematic match. Then the layout is parasitic
extracted using QRC run and finally the parasitic extracted
implementation is simulated to determine the performance.
In the layout level the Analog GND is established at 0.41V
and Vref+ and Vref- at 0.62V and 0.2V respectively. The
reason for modifying these DC values at layout level is
discussed in the next section. The implemented ΔΣ A/D
Converter is simulated in cadence analog environment using
transient simulation. The sinusoid of 0.2V amplitude (DC
biased at 0.41V) at 12.20703125KHz is provided as input.
The simulated input and output signal is illustrated in figure
21. The simulated output data is imported into MATLAB
following the process discussed in the subsection (IV.G).
Power at each frequency bin is computed and the obtained
PSD plot is shown in figure 22. The peak SNDR is calculated
with equation (4). The peak SNDR calculated in the
postlayout circuit implementation is computed to be 58.19dB.
Figure 20: Implemented layout in Cadence of the ΔΣ A/D Converter
 TABLE I. RESULTS SUMMARY OF THE A/D CONVERTER
SYSTEM CADENCE CADENCE REQUIRED
LEVEL PRE- POST-
(SIMULINK) LAYOUT LAYOUT
Power 1V 1V 1V 1V
Supply
Bandwidth 19.410KHz 19.410KHz 19.410KHz 19.41KHz

Sampling 10MHz 10MHz 10MHz >1.48MHz

Frequency
Input 12.207031 12.207031 12.207031 <19.41KHz
Frequency KHz KHz KHz
Figure 21: The output and input of the ΔΣ A/D Converter for cadence post-
layout circuit implementation Input 0.2V 0.2V 0.2V <0.2V
Amplitude
Analog 0.5V, 0.5V, 0.41V, -
GND, 0.71V, 0.71V, 0.62V,
Vref+,Vref 0.29V 0.29V 0.20V
-
SNDR 62.64dB 61.5dB 58.19dB 50dB
Static - - 620uW -
Power
Dissipation

The system level realization does not account for the

Figure 22: PSD plot for Cadence post-layout circuit level simulation
The static power dissipation at layout level of implementation
is calculated to be approximately 620uW, which is
comparable to static power dissipation reported for a similar
ΔΣ A/D modulator implemented in 65nm technology using
1V supply [3]. There is scope for optimizing the static power
dissipation by minimizing the connection parasitics.
nonlinearity of the circuit components, transistors in
particular. However in the circuit level implementations
(both in pre-layout and post layout) the nonlinearity gives rise
to harmonics in frequency domain as observed in figure 23
for the ΔΣ A/D Converter implementation. If the harmonics
fall within the bandwidth of interest this can reduce the
SNDR from its expected value at system level. For the choice
for input frequency greater than 10 KHz for a bandwidth of
19.410 KHz the 2nd, 3rd and rest of the harmonics will fall
outside the bandwidth of interest and so they can be filtered
out. Therefore, for better SNDR, at the implementation level
an input frequency greater than 10 KHz is recommended for
the given bandwidth. The SNDR degrades for lower input
frequency due to presence of harmonics inside the bandwidth
of interest. Still, at lower frequencies SNDRs achieved for the
implementation satisfy the specification requirement.

VI. RESULTS AND DISCUSSIONS 0

Fundamental
Tone system-level
-10
post-layout
Table I shows the comparison of the system level (Simulink), -20
pre-layout

pre-layout level and post-layout level implementation. The

-30 2nd
discrepancy in SNDR in system level, pre-layout level and Harmonic
post-layout level implementation is due to the non-idealities -40
PSD (dB)

3rd Harmonic
introduced by the operation of circuit components. Some of -50
major non-idealities causing the SNDR to differ between
-60
different levels of implementation are discussed elaborately
in this section -70

-80

-90

-100
0 10 20 30 40 50 60
Frequency Bin Number
Figure 23: PSD at different levels of implementation
The parasitic introduced in the layout level implementation
can affect the SNDR. The parasitic can slightly shift the DC
operating points in the circuit, affect the OTA gain and
increase overall static power dissipation. In the post-layout
level the Analog GND is established at 0.41V instead of 0.5V
at pre-layout level to account for op-amp input voltage offset
introduced in post-layout level. Along with the mentioned
shift of Analog GND, modifying the DC voltages of Vref+
and Vref- of the DAC to 0.62V and 0.2 V in layout level
shows improvement of SNDR.

Based on these discussions regarding non-linearity and

parasitic introduced by circuit components, some
improvements are addressed in the next section.

VII. SCOPES FOR IMPROVEMENT

There are several scopes for improving the implemented

designs, which are discussed below:

From the discussion of previous section, the non-linearity,

which appears as harmonics in the frequency domain, is an
important concern in the circuit level implementation. A fully
differential topology can mitigate the even order harmonics
and thereby can improve the overall SNDR [2], if the even
order harmonics for a given input frequency fall within the
bandwidth of interest. For the fully differential topology,
interdigitated transistors with common centroid geometry
would aid the matching of transistors and thereby suppression
of even order harmonics.

There is scope for sharing the diffusion area of transistors for

D-Latch implementation. Sharing the diffusion area of the
transistors would reduce the parasitic capacitance. Also, there
is scope for further optimization of trace length, which would
reduce the trace parasitic resistance.

VIII. CONCLUSION

A first order, single bit, low pass ΔΣ A/D converter is

implemented. First, the design is implemented at the system
level in Matlab Simulink platform and simulated to verify the
performance. Then the system level design is mapped onto a
circuit level design employing switched capacitor. The circuit
level design is laid out and simulated. The simulation results
of system level, pre-layout circuit level and post-layout circuit
level are compared. The major causes for the variation of
addressed. Finally, further provisions for the improvement in
the implementation of the A/D converter is delineated.

REFERENCES

[1] G. W. Roberts, ECSE 534 Analog Microelectronics Notes, McGill

University, McGill University Bookstore.
[2] Yan, Dong, et al. “Analysis of Harmonic Distortion of Sigma-Delta
Modulator.” Key Engineering Materials, vol. 645–646, Trans Tech
Publications, 2015
[3] L. Liu, D. Li, et al. “A 95dB SNDR audio ΔΣ modulator in 65nm
CMOS” IEEE Custom Integrated Circuits Conference, 2011
 APPENDIX

File paths to the design: /home/rkhan37/tsmc65/assignment3

TABLE II: FILE NAMES

Content File name

ΔΣ A/D converter S_D_Mod/schematic
(schematic)
ΔΣ A/D converter (layout) S_D_Mod/layout
ΔΣ A/D converter (parasitic S_D_Mod/av_extracted
extraction)
ΔΣ A/D converter worked_simu
(Simulink Model)
ΔΣ A/D converter (matlab working_cad
file for PSD plot and SNDR
calculation)
Data files for A/D aaa5 (for post-layout
converter output extracted simulation)
from cadence transient w2f (for pre-layout
simulation simulation
Integrator OTA integrator
Comparator comparator
D-Latch D_Latch
Transmission Gate Pass_Gate
Inverter InverterCMOS
Nor Gate Nor_gate
4 phase clock 4_phase_clock

Fig. A1: Pre layout implementation of the ΔΣ A/D Converter

Fig. A2: Implemented layout in Cadence of the ΔΣ A/D Converter
 (a) Pre-layout circuit level

(b) Layout

Fig A3: Implementation of OTA

(a) inverter pre-layout (b) transmission gate pre-layout

(c) Inverter layout (d) transmission gate layout

Fig. A4: Implementation of inverter and transmission gate

 (a) Pre-layout circuit level

(b) layout

Fig. A5: Implementation of D-Latch