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  • Chapter 4-My First Program in Verilog

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    Danh ZEUS49
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    This document discusses a basic "Hello World" program in Verilog and a 4-bit synchronous up counter design. It introduces some key concepts in Verilog including always blocks, modules, initial and endmodule keywords. The counter design is specified to be 4 bits, synchronous, with active high reset and enable. A testbench is created to simulate the counter design and verify its functionality.

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    This document discusses a basic "Hello World" program in Verilog and a 4-bit synchronous up counter design. It introduces some key concepts in Verilog including always blocks, modules, initial and endmodule keywords. The counter design is specified to be 4 bits, synchronous, with active high reset and enable. A testbench is created to simulate the counter design and verify its functionality.

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    © All Rights Reserved
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    18 views6 pages

    Chapter 4-My First Program in Verilog

    Uploaded by

    Danh ZEUS49
    This document discusses a basic "Hello World" program in Verilog and a 4-bit synchronous up counter design. It introduces some key concepts in Verilog including always blocks, modules, initial and endmodule keywords. The counter design is specified to be 4 bits, synchronous, with active high reset and enable. A testbench is created to simulate the counter design and verify its functionality.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 6

    VERILOG HDL

    Chapter 4

    My First Program in Verilog

    Trương Phong Tuyên


    Hello World Program

    • hello_world.v
     Words in green are comments, blue are
    reserved words.
     Any program in Verilog starts with
    reserved word module <module_name>.
     We can have compiler pre-processor
    statements like `include, `define before
    module declaration
     The initial block: this block gets executed
    only once after the simulation starts, at
    time=0 (0ns).
     If you have multiple lines within a block, you need to use begin and end.
     Module ends with `endmodule reserved word.

    2
    Counter Design

    • Counter Design Specs


     4-bit synchronous up counter.
     Active high, synchronous reset.
     Active high enable.

    • Counter Block

    3
    Counter Design

    4
    Simulation

    5
    The End

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