LAB NO: 1

Introduction to Verilog (gate-level modeling, data-flow

modeling and Behavioral modeling)

Objective:

This lab is an introduction to logic design using Verilog-HDL .There will be 2 hours Pre Lab
explanation by the instructor on Verilog and RTL Verilog. Design concepts using HDL are
presented in this lab. The goal of this lab is for you to become familiar with the Verilog HDL and
its different ways to code your Hardware.

Introduction:

HDL (Hardware Description Language) is any language from a class of computer languages,
specification languages, or modeling languages for formal description and design of electronic
circuits, and most-commonly, digital logic. It can describe the circuit's operation, its design and
organization, and tests to verify its operation by means of simulation. The two most popular
HDLs are Verilog and VHDL. Verilog due to its similarity to C language is easier to understand so
has become most widely used HDL in educational institutions. In this lab we have come to know
about modules and operators and also about level abstraction which include Behavioral ,Data
flow ,Gate level modeling.

Discussion:

In gate level modeling a circuit can be defined by use of logic gates. These gates predefined in
verilog library. In dataflow Continuous assignment statement is used. Keyword assign is used
followed by = Most common operator. In behavioural there are procedural blocks that consists
of two blocks (i)initial block (ii) always block .An always block contain list of expressions which
are usually evaluated sequentially and initial block execute only once and start at time 0.also in
behavioural the $sign is used to finish code. Operators used are e.g uniry ,binary, tri and
conditional etc.

Working:

A module is the basic building block in Verilog. A module can be an element or a collection of
lower-level design blocks. In Verilog, a module is declared by the keyword module. A
corresponding keyword endmodule must appear at the end of the module definition. Each
module must have a module_name, which is the identifier for the module, and a
module_terminal_list, which describes the input and output terminals of the module .
In gate level modeling the basic gates and their syntax is as follows:

module ha(a, b, sum, carry);

input a;

input b;

output sum;

output carry;

xor o1(sum,a,b);

and o2(carry,a,b);

endmodule

In dataflow modeling its as follows:

module lab3a(a, b, c, sum);

input a;

input b;

output c;

output sum;

assign sum=a^b;

assign c=a&b;

endmodule

In behavioural modeling syntax is as follows:

Initial

clock = 1'b0; //Toggle clock every half-cycle (time period = 20)

always @(clk)

#10 clock = ~clock;

Initial
#1000 $finish;

Conclusion:

In this lab we have learned about basics of FPGA lab. The languages we are going to use and
operators and about modeling of circuits. Also we have learned how to implement code in gate
level, dataflow and behavioural modeling. Also about timing delays in behavioural modeling
and now able to do coding.