VERILOG HDL

Chapter 6

Gate Level Modeling

Trương Phong Tuyên

 Introduction

• Verilog has built in primitives like gates,

transmission gates, and switches. These are rarely
used in design (RTL Coding), but are used in post
synthesis world for modeling the ASIC/FPGA cells;
these cells are then used for gate level simulation,
or what is called as SDF simulation. Also the output
netlist format from the synthesis tool, which is
imported into the place and route tool, is also in
Verilog gate level primitives.
• Note: RTL engineers still may use gate level
primitives or ASIC library cells in RTL when using IO
CELLS, Cross domain sync cells.
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 Gate Primitives

• The gates have one scalar output and

multiple scalar inputs. The 1st terminal in the
list of gate terminals is an output and the
other terminals are inputs.

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 Gate Primitives

• Example

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 Transmission Gate Primitives

• Transmission gates are bi-directional and can be

resistive or non-resistive.
• Syntax: keyword unique_name (inout1, inout2, control);

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 Transmission Gate Primitives
• Example

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bufif0 U1(data_bus,in, data_enable_low);
buf U2(out1,in);
not U3(out2,in);

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 Switch Primitives
• There are six different switch primitives (transistor models)
used in Verilog, nmos, pmos and cmos and the
corresponding three resistive versions rnmos, rpmos and
rcmos. The cmos type of switches have two gates and so
have two control signals.
• Syntax: keyword unique_name (drain, source, gate)

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 Switch Primitives
• Transmission gates are
bi-directional and can be
resistive or non-resistive.
• Resistive devices reduce
the signal strength which
appears on the output by
one level.
• All the switches only
pass signals from source
to drain, incorrect wiring
of the devices will result
in high impedance
outputs.

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 Switch Primitives

• Examples

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 Logic Values and Signal Strengths

• The Verilog HDL has got four logic values

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 Logic Values and Signal Strengths

• Verilog Strength Levels

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 Logic Values and Signal Strengths

• Verilog Strength Levels (cont.)

• Two buffers that has output • Two buffers that has output
• A : Pull 1 • A : Supply 1
• B : Supply 0 • B : Large 1
• Since supply 0 is stronger • Since Supply 1 is stronger
then pull 1, Output C takes then Large 1, Output C takes
value of B. the value of A
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 Designing Using Primitives
• Designing using primitives is used only in library
development, where the ASIC vendor provides
the ASIC library Verilog description, using
Verilog primitives and User Defined Primitives
(UDP).
• Example

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 Designing Using Primitives
• Example

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 Designing Using Primitives
• D-Flip Flop from NAND Gate

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Multiplexer 4 - > 1

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18
 Gate and Switch Delays
• In real circuits, logic gates have delays associated with them.
Verilog provides the mechanism to associate delays with
gates.
 Rise, Fall and Turn-off delays.
 Minimal, Typical, and Maximum delays.
• In Verilog delays can be introduced with #'num' as in the
examples below, where # is a special character to introduce
delay, and 'num' is the number of ticks simulator should delay
current statement execution.
 #1 a = b : Delay by 1, i.e. execute after 1 tick
 #2 not (a,b) : Delay by 2 all assignments made to a.
• Real transistors have resolution delays between the input and
output. This is modeled in Verilog by specifying one or more
delays for the rise, fall, turn-on and turn off time separated by
commas. 19
 Gate and Switch Delays
• Syntax:
keyword #(delay{s}) unique_name (node specifications);

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 Gate and Switch Delays
• Rise Delay
 The rise delay is associated with a gate output transition to 1
from another value (0, x, z).

• Fall Delay
 The fall delay is associated with a gate output transition to 0
from another value (1, x, z).

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 Gate and Switch Delays

• Turn-off Delay: The Turn-off delay is

associated with a gate output transition to z
from another value (0, 1, x).
• Min Value: The min value is the minimum delay
value that the gate is expected to have.
• Typ Value: The typ value is the typical delay
value that the gate is expected to have.
• Max Value: The max value is the maximum
delay value that the gate is expected to have.
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 Gate and Switch Delays

• Example - Single Delay

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 Gate and Switch Delays

• Example - Two Delays

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 Gate and Switch Delays
• Example - All Delays

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 Gate and Switch Delays
• Example – Complex Example

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 N-Input Primitives

• The and, nand, or, nor, xor, and xnor

primitives have one output and any
number of inputs.
 The single output is the first terminal.
 All other terminals are inputs.

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 N-Input Primitives
• Example

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 N-Output Primitives

• The buf and not primitives have any number of

outputs and one input .
 The outputs are the first terminals listed.
 The last terminal is the single input.

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 N-Output Primitives

• Example

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The End