IEEE TRANSACTIONS ON REHABILITATION ENGINEERING, VOL. 6, NO.
1, MARCH 1998
A Programmable Sound Processor
for Advanced Hearing Aid Research
Hugh McDermott
Abstract— A portable sound processor has been developed
to facilitate research on advanced hearing aids. Because it is
based on a digital signal processing integrated circuit (Motorola
DSP56001), it can readily be programmed to execute novel
algorithms. Furthermore, the parameters of these algorithms
can be adjusted quickly and easily to suit the specific hearing
characteristics of users. In the processor, microphone signals
are digitized to a precision of 12 bits at a sampling rate of
approximately 12 kHz for input to the DSP device. Subsequently,
processed samples are delivered to the earphone by a novel, fully-
digital class-D driver. This driver provides the advantages of a
conventional class-D amplifier (high maximum output, low power
consumption, low distortion) without some of the disadvantages
(such as the need for precise analog circuitry). In addition,
a cochlear implant driver is provided so that the processor
is suitable for hearing-impaired people who use an implant
and an acoustic hearing aid together. To reduce the compu-
tational demands on the DSP device, and therefore the power
consumption, a running spectral analysis of incoming signals
is provided by a custom-designed switched-capacitor integrated
circuit incorporating 20 bandpass filters. The complete processor
is pocket-sized and powered by batteries. An example is described
of its use in providing frequency-shaped amplification for aid
users with severe hearing impairment. Speech perception tests
confirmed that the processor performed significantly better than
the subjects’ own hearing aids, probably because the digital filter
provided a frequency response generally closer to the optimum
for each user than the simpler analog aids.
Index Terms— Digital signal processing, hearing aids, speech
perception.
I. INTRODUCTION
A variety of devices are now available to assist people with
a hearing impairment, ranging from simple amplifiers
for those with a mild loss, to sophisticated cochlear implant
(CI) and auditory brainstem implant systems for those with
a profound or total loss. Although these devices provide
satisfactory performance for many of their users, few, if any,
can restore all the characteristics of hearing to normal. Much
of the current research in this field is focused on developing
advanced sound processing techniques that are designed to
compensate for the perceptual deficiencies that are commonly
associated with a loss of hearing sensitivity.
In this work, digital signal processing (DSP) is preferred
over analog processing for one predominant reason: flexi-
bility. Because the functional specification of a DSP device
Manuscript received June 30, 1997; revised December 1, 1997.
The author is with the Co-operative Research Center for Cochlear Implant,
Speech, and Hearing Research, Department of Otolaryngology, The University
of Melbourne, East Melbourne 3002 Australia.
Publisher Item Identifier S 1063-6528(98)01984-3.
1063–6528/98$10.00  1998 IEEE
53
is determined almost entirely by software, new processing
schemes can be developed, evaluated, and modified rapidly
and relatively easily [1]. In contrast, major changes to the func-
tion of an analog signal processor require electronic circuitry
to be designed and constructed, which can be particularly
demanding if the device must be small enough to be carried
or worn by the user.
The ease of programming general-purpose digital processors
comes at the cost of high power consumption, and relatively
large physical size and weight [2], [3]. Although DSP chips are
beginning to appear in hearing aids packaged in conventional
behind-the-ear (BTE) and in-the-ear (ITE) enclosures, so far
these devices are custom-designed and lack the flexibility
required in research. While they are programmable in the sense
that a set of parameters can be adjusted to suit the individual
user, the processing algorithm is to a large extent embedded
in the circuitry, so that major changes are not possible.
Therefore, there is still a need for a sound processor based
on a general-purpose DSP chip. The processor must be no
larger than pocket-sized, so that users can gain experience
with new processing schemes in everyday situations away
from the laboratory. The power consumption must be low
enough to ensure that neither the size of the battery pack nor
the frequency of battery changes will inconvenience the user.
The ease of programming and the computational performance
must be adequate for the implementation of inventive schemes
that could feasibly be incorporated into digital BTE or ITE
instruments by a manufacturer within the next few years. This
article describes such a processor. In the following paragraphs,
details of the hardware design are described. Subsequently, an
example is presented of how the device is fitted to hearing-
impaired people, and finally the results of some recent speech
perception tests are reported.
II. HARDWARE DESIGN
Previously we have described a portable digital sound
processor, called the P-DSP, that was designed specifically
for cochlear implant research [4]. It has enabled a range
of experimental processing schemes to be evaluated by CI
users. Some of these schemes, especially those that atten-
uate interfering noise, are potentially beneficial to users of
other devices, including conventional acoustic hearing aids.
Furthermore, improvements in CI performance have led to a
gradual relaxation of the criteria for patient selection. There
are now people with some usable hearing receiving CI’s, and
many of them obtain benefit from wearing a hearing aid and
a CI simultaneously in opposite ears [5]. These developments
54 IEEE TRANSACTIONS ON REHABILITATION ENGINEERING, VOL. 6, NO. 1, MARCH 1998
Fig. 1. Functional block diagram of the P-DSP/HA.
provided an incentive for extending the design of the P-DSP.
The new device, known as the P-DSP/HA, incorporates two
new features: 1) a novel, fully digital earphone driver, and 2)
a real-time spectrum analyzer based on a bank of bandpass
filters. These capabilities have been provided in addition to
the CI driver, so that the P-DSP/HA is appropriate for users
of both hearing aids and cochlear implants, either separately
or together.
A. Analog Inputs
The analog circuitry and DSP chip are outlined only briefly
here, as full details were presented in the previous report [4].
As shown in the block diagram of Fig. 1, input signals are
amplified with gain set by the front-panel sensitivity control,
pass through an anti-aliasing low-pass filter with a cut-off
frequency of approximately 6 kHz, and are delivered to one
of four inputs of the analog-to-digital converter (ADC). Two
types of input transducer may be accommodated. One is a
directional two-port microphone mounted in a BTE case.
The frequency response of this microphone has a high-pass
characteristic with a slope of 6 dB/oct below 4 kHz. The other
type of input is suitable for devices with a flat frequency re-
sponse, including omnidirectional microphones, telephone and
television adapters, etc. The P-DSP/HA automatically detects
which input is in use, and applies an appropriate compensating
frequency response in the preamplifier. Although the ADC
digitizes input signals to a precision of only 12 bits, the
sensitivity control enables an optimum overall gain to be
selected for each signal source. Measurements have shown
that the dynamic range at the microphone input is close to 60
dB over most of the available bandwidth.
The other three inputs to the ADC are: 1) a voltage derived
from a potentiometer mounted on the front panel, which may
be used as a volume control or for other purposes, 2) the main
battery voltage, which enables the central processor to detect
when the battery is becoming exhausted, so that operations
may be shut down smoothly, and 3) signals from the filterbank
chip, which is described below.
B. Filterbank
In sound-processing research, the need arises so often for a
running estimate of the input spectrum that it was considered
worthwhile to include a chip in the P-DSP/HA specifically for
this purpose. The chip was developed originally for another
cochlear implant sound processor [6]. It is a programmable
device employing switched-capacitor technology, and is out-
lined in the block diagram of Fig. 2. A preamplifier with
automatic gain control (AGC) delivers signals originating from
the microphone in parallel to a bank of 20 bandpass filters.
The filters are fourth-order with frequency responses designed
to intersect at the 3 dB points, such that the sum of their
magnitudes is nearly constant across frequency. The output of
each filter passes to an amplitude detector which generates a
signal approximating the envelope of the filtered waveform.
An output multiplexer enables selection of any of the 20
envelope amplitudes or the output of a reference channel. The
reference output may be subtracted from each of the other
outputs by the external DSP unit to compensate partially for
any dc offsets inherent in the circuitry.
In the P-DSP/HA, the filterbank chip receives programming
data directly from the DSP unit, and provides analog signals
to the ADC. Many functions in the chip are programmable,
including the operation of the AGC amplifier, the gains of the
bandpass filters, and the range of frequencies encompassed by
the bank of filters. Typically the 20 center frequencies cover
the range from 240 to 9600 Hz, with the first eight separated
by a constant frequency increment, and the remaining 12 sepa-
rated by a constant frequency ratio. This chip not only relieves
the DSP unit of a considerable amount of computation in many
applications, but also reduces the total power consumption of
the P-DSP/HA. The filterbank chip’s power requirement is
less than 10 mW. Measurements have also shown the dynamic
range of each filter band to be greater than 40 dB.
C. Central Processor
The ADC delivers 12-bit digital samples to the central DSP
chip, which is a Motorola DSP56001. This chip controls both
MCDERMOTT: SOUND PROCESSOR FOR ADVANCED HEARING AID RESEARCH
Fig. 2. Simplified block diagram of the custom-designed spectrum analyzer chip incorporating 20 band-pass filters.
the ADC sampling rate and the selection of the analog input
signal to be digitized. Typically it is programmed to provide
an overall sampling rate of 23 438 Hz, with alternate samples
being obtained from the microphone input. The remaining
samples are obtained from each of the other ADC inputs
in a cyclical sequence. There are 23 of these inputs in
total (amplitudes from 20 filters, dc level from the reference
channel, setting of the volume potentiometer, and the battery
voltage). In this way, estimates of the input spectrum are
acquired at intervals of about 2 ms, which provides sufficient
temporal detail of changing spectra for most speech-processing
applications.
The DSP56001 has limited amounts of random-access mem-
ory (RAM) on-chip. In the P-DSP/HA, the memory size is
extended by provision of 32 768 words of 24-bit static RAM.
This RAM maintains the program code and associated data
(much of which is specific to the individual user). Because
all this information must be retained even when the main
power supply is switched off, the external RAM receives
an uninterrupted supply from a miniature lithium cell when
necessary. The external RAM is loaded from an IBM PC-
compatible computer via a simple parallel interface. The
interface also allows the host computer to execute programs
in the P-DSP/HA, and to examine and modify RAM contents,
thus facilitating software development. Once the program and
data are loaded into the portable unit, it may be disconnected
from the computer and taken away by the user.
A front-panel switch allows one of up to three stored
programs to be selected by the user (see Fig. 1). Simple visual
indications are provided when appropriate by a light-emitting
diode (LED) on the front panel which is controlled directly by
the DSP program. A second LED is provided to warn the user
when the battery is nearly depleted, and is illuminated even
when the battery is too flat for normal DSP operation.
D. Output Drivers
In the original version of the P-DSP, provision was made
for two programmable logic devices (PLD’s) so that two
55
cochlear implants could be driven simultaneously [4]. In that
situation, each implanted receiver-stimulator obtained data and
a power supply through independent inductive links operating
at a frequency of 2.5 MHz. Thus there were two radio
frequency (RF) amplitude-modulated transmitters in the P-
DSP. However, at present there are very few people with
bilateral cochlear implants. To provide an acoustic output
from the P-DSP/HA, one of the CI transmitters was replaced
with an earphone driver, while the other was retained. As
described below, the associated PLD (Xilinx XC3000 series)
was reconfigured to create a novel type of digital-to-analog
converter (DAC) without the need for extensive modifications
to the hardware.
Many recently developed hearing aids produced by com-
mercial manufacturers drive the earphone (often called the
receiver) with a class-D amplifier [7]. The principle of the
class-D circuit is that an analog waveform is sampled at a
regular time interval, and the instantaneous amplitude mod-
ulates the pulse duration (or duty cycle) of a constant-rate
pulse train. The modulated pulse train simply controls the
switching of a steady voltage onto the earphone. Because
earphones generally exhibit a low-pass frequency response
with an abrupt slope at a cut-off frequency of typically 4
kHz, they will effectively demodulate the pulse train to recover
the original analog waveform. This depends on the pulse rate
being much higher than any signal frequency, and in many
class-D amplifiers, a pulse rate of about 50–100 kHz is used.
The advantages of this technique include 1) very high power
efficiency, because the earphone is driven through low-loss
switches rather than by a linear amplifier and 2) effectively
linear operation with little distortion up to the output limits
imposed by the power supply. These features are particularly
valuable in hearing aids, which require long battery lifetime
and power amplification with minimal distortion.
Previous class-D amplifiers are mostly analog circuits, but in
a fully digital hearing aid, the opportunity exists for converting
digital sample values directly into the modulated pulse train
that drives the earphone. In the P-DSP/HA, this conversion
56 IEEE TRANSACTIONS ON REHABILITATION ENGINEERING, VOL. 6, NO. 1, MARCH 1998

Fig. 3. Functional block diagram of the fully digital class-D earphone driver.

is performed by one of the PLD’s. As shown in the block

diagram of Fig. 3, the 12-bit samples generated by the DSP
unit are first stored in a register. They are then partitioned
(a)
into a most-significant portion (MSP) of 9 bits and a least-
significant portion (LSP) of 3 bits. The MSP is compared
for equality with the current value of a 9-bit counter by a
digital comparator. As shown in the timing diagram of Fig. 4,
the output of the comparator can be delayed in time under (b)
the control of the LSP of the input data value. The most-
significant bit (MSB) of the LSP conditionally adds a one-half
clock period delay, while the remaining 2 bits add 0–3 unit
delays, produced using the propagation time of elementary (c)
logic gates on the chip. The counter is clocked at a rate of
24 MHz by a crystal oscillator. One-half the clock period is
20.8 ns, and the propagation delay for logic gates in this PLD
is close to 5 ns. Therefore, the increments in overall delay (d)
controlled by the LSP of the data subdivide the master clock
period (of 41.6 ns) into eight approximately equal intervals.
Larger increments in the delay are controlled by the 9-bit
counter and the comparator using the MSP of the data. (e)
In the output waveform, each pulse is started when the
MSB of the counter is set, and this results in 5 V being
applied to the earphone. The pulse is terminated by the
conditionally delayed signal from the comparator, and this (f)
results in 5 V being applied to the earphone (by reversing Fig. 4. Timing diagram for the most important signals shown in Fig. 3. (a)
its connections). Thus the period of the waveform delivered 24 MHz clock input. (b) SET signal from MSB of the counter to the flip-flop.
to the earphone is 21.3 s, and the pulse duration within this (c) EQUAL signal from the comparator, showing the effect of the half-cycle
delay (dashed). (d) delayed EQUAL signal, showing the combined effects of
period is controlled by the 12-bit sample data. For example, the half-cycle delay (solid), and the selectable propagation delays (dashed). (e)
a sample value of zero results in a 50% duty cycle in RESET signal to the flip-flop (shown with the maximum delay). (f) OUTPUT
the output pulse train, and therefore an average voltage of signal to the earphone driver.
zero at the earphone. Positive samples produce larger duty
cycles, and proportionately positive average output voltages. regulated voltage reference, to convert digital samples into
Conversely, negative samples (which have the MSB set) the analog waveform required by the earphone. Furthermore,
produce smaller duty cycles, and proportionately negative it reduces the possibility of heterodyne interference that can
average output voltages. The effective digital to analog voltage occur when multiple clock frequencies coexist in a sound pro-
conversion is linear, and measurements made on the PLD cessor. For example, some systems containing a conventional
confirmed that the relation between output pulse duration and DAC employ a class-D amplifier incorporating an independent
input sample value was monotonic, right down to changes in oscillator (such as the Knowles CL-series integrated receivers),
the least-significant bits. which could interfere with the oscillator controlling the digital
The main advantage of this digital design is that it re- processor. However, in the P-DSP/HA, the 24 MHz clock from
quires no high-performance analog circuitry, nor a tightly the master crystal oscillator is divided by two in the PLD to
MCDERMOTT: SOUND PROCESSOR FOR ADVANCED HEARING AID RESEARCH
provide a 12 MHz clock for the DSP56001. The DSP unit
internally divides this clock by 1024 to set the sampling rate
to 11 719 Hz for both the microphone and earphone signals.
Thus all clocks are synchronized and related by integer ratios,
resulting in minimum mutual interference. Another feature
of the design is that it does not require any change to the
format of the data processed by the DSP unit: a conventional
12-bit two’s-complement data representation is used at both
input and output of the DSP. In this respect the design may
have advantages over techniques based on, e.g., sigma–delta
principles, which require parallel data to be converted to and
from serial bit-streams at a rate much higher than the sampling
rate.
III. HEARING-AID FITTING
The flexibility of the P-DSP/HA facilitates its use in the
development of a wide range of sound processing techniques.
Examples of some types of processing that might benefit
people with severe hearing impairment include: attenuation
of interfering noise; enhancement of speech signals; improved
automatic control of loudness; transposition of inaudible fre-
quency bands; and reduction of feedback oscillations. How-
ever, it is an essential requirement of all hearing aids to provide
amplification at each frequency that is appropriate for the
individual listener. How this basic requirement is attained in
the P-DSP/HA is described below.
A desirable frequency response for a hearing aid is one that
optimizes the audibility of information-bearing components
of speech. The response must account for the characteristics
of the aid user’s residual hearing, because hearing threshold
levels, in particular, can vary greatly among individuals. It
must also account for some important characteristics of the
speech signal, such as the shape of the long-term average
spectrum, which is approximately flat from 100 to 500 Hz,
and declines at a rate of about 9 dB/oct from 500 Hz to 4
kHz [8]. Furthermore, the dynamic range of speech signals is
at least 30 dB [8]. The frequency response of the aid should
be designed to amplify that range to a range of comfortable
loudness levels at each frequency for the user. Failure to
achieve these requirements will usually result in less than
optimum intelligibility or quality of amplified sounds, and
possibly rejection of the aid by the user.
Various techniques have been proposed for specifying the
frequency response for each aid user. One of the most widely
used currently was developed by the National Acoustic Lab-
oratories of Australia, and is known as the NAL-RP formula
[9], [10]. This formula specifies the frequency response using
only the hearing thresholds measured in the individual at each
frequency. The thresholds are normally measured with pure
tones using a standard audiometer and supra-aural headphones.
However, the advent of digital technology has facilitated
the measurement of thresholds through the user’s hearing
aid itself, perhaps resulting in a more accurately specified
frequency response. This is because several potential sources
of error in computing the required frequency response from
the headphone-measured thresholds are eliminated when the
57
identical earphone and earmold are used for both the threshold
measurements and the fitted hearing aid.
With the P-DSP/HA, thresholds are measured under the
control of a program running on the host computer, to which
the portable processor is attached. The host downloads a
program into the DSP which generates controlled bursts of
sine waves with rise/fall times of 30 ms. The host program
specifies the frequencies, levels, and durations of these tone
bursts in real-time. In practice, an audiologist can operate the
system in essentially the same way as she or he would use
a standard audiometer. Typically, hearing threshold levels are
obtained at half-octave frequencies between 125 Hz and 4
kHz, with tone durations of about 500 ms. The levels are
calibrated in standard units of dB HL by converting from level
measurements made with a 2-cm3 coupler [11]. Thus they may
be compared directly with thresholds measured conventionally
using an audiometer and headphones.
The host program computes the required frequency response
of the aid based on the set of measured thresholds. It then
subtracts (in dB terms) the frequency responses associated
with the microphone and earphone of the aid to obtain the
response that needs to be provided by the processor itself.
A simple example of a suitable DSP program is illustrated in
flow-chart form in Fig. 5. Samples of the digitized microphone
signal are first processed by a 127-point finite impulse response
(FIR) filter. They are then multiplied by a value that depends
on the setting of the front-panel volume control. Finally,
they are limited to a range of values that is chosen to
prevent the production of uncomfortably loud sounds, and are
conveyed to the earphone driver. The coefficients for the FIR
filter are calculated in the host computer by application of
the inverse discrete Fourier transform to the derived target
frequency response. These coefficients and the DSP program
are downloaded by the host into the P-DSP/HA. Subsequently,
the P-DSP/HA can be disconnected from the host computer
and operated on battery power by the aid user away from
the laboratory. The power consumption of the P-DSP/HA
running this relatively simple program is about 450 mW, which
translates into a battery lifetime of about 24 h.
IV. P-DSP/HA PERFORMANCE
Recently five experienced users of monaural hearing aids
were fitted with the P-DSP/HA using the above procedure.
Their performance in understanding speech was assessed with
both the P-DSP/HA and their own hearing aids. In the tests,
speech material was presented at an average level of 60 dBA
(based on peak levels measured on a sound-level meter with
the fast time constant). The volume control of the P-DSP/HA
was adjusted to produce the nominal overall gain specified
by the NAL-RP formula. For tests using their own aids,
each subject was instructed to set the volume control to its
usual position for listening to speech at conversational levels.
However, the speech level in the tests was approximately 5
dB below typical conversational levels, and was chosen to
emphasize the effects of the frequency response of each aid.
At low speech levels, a nonoptimum frequency response would
be expected to have a greater effect on intelligibility than
at high levels, because more of the speech signal would be
58 IEEE TRANSACTIONS ON REHABILITATION ENGINEERING, VOL. 6, NO. 1, MARCH 1998
Fig. 5. Diagrammatic representation of the signal processing implemented
in the P-DSP/HA for the performance assessment by aid users with severe
hearing impairment.
inaudible to the listener. This is consistent with the findings of
a recent study [12], which showed that the frequency response
generally had little effect on intelligibility provided that most
of the dynamic range of speech across frequency was amplified
to audible levels.
The speech test material comprised recordings of mono-
syllabic words having a consonant-vowel-consonant structure.
There were 50 words per list, and the same distribution of
phonemes within each list [13]. The subjects were tested
individually, and their responses were recorded as the number
of phonemes correct (out of 150) on each list. Two lists were
used to assess each subject’s performance with each aid. For
the subjects’ own aids, one list was tested before, and one
after, the two lists tested with the P-DSP/HA. This sequence
was intended to reduce the possibly confounding effects of
practice on the task. In addition, the subjects had a limited
amount of listening experience with the P-DSP/HA, including
presentation of word lists different from those used when the
responses were scored. An equal number of practice lists were
also presented with the subjects listening through their own
aids. However, no take-home experience with the P-DSP/HA
was provided.
The results for each subject are shown in Fig. 6. Four of
the five subjects recorded an increased mean score for the P-
DSP/HA compared with their own aids. A two-factor analysis
of variance on the group scores revealed a significant effect
of aid type (mean score difference: 8.2 percentage points, P-
DSP/HA higher; ), but not for the aid subject
interaction . of the aids, such as levels of distortion, might have affected
Fig. 6. Speech perception results for five subjects using the P-DSP/HA (solid
columns) and their own hearing aids (hatched columns). The ordinate shows
the percent correct of phonemes in monosyllabic words. Error bars indicate
plus one standard deviation of the mean.
Fig. 7. Average frequency responses, relative to the response specified by
the NAL-RP formula, for the P-DSP/HA (open circles) and the subjects’ own
aids (filled squares). Error bars indicate plus and minus one standard deviation
of the mean across subjects. Symbols for the P-DSP/HA data are offset to the
right for clarity.
The frequency response of each aid was measured using
a standard 2 cm3 coupler (Rastronics Porta-REM 20). To
facilitate comparison, the response prescribed by the NAL-
RP formula was subtracted from the two measured responses
at each frequency. The results, averaged across subjects, are
shown in Fig. 7. They confirm that the overall response
provided by the P-DSP/HA was much closer to the NAL-RP
specification than those of the subjects’ own aids. In addition,
there was less variability in the response of the P-DSP/HA
when fitted to each subject, as indicated by the generally
smaller standard deviations.
The above results should be interpreted with caution, for
several reasons. In the course of the experiment, no adjust-
ments were made to the subjects’ own aids. Those aids were
of various types, and it is unknown whether they were all
fitted originally in accordance with the NAL-RP formula.
Furthermore, other differences in the technical performance
MCDERMOTT: SOUND PROCESSOR FOR ADVANCED HEARING AID RESEARCH
the results. Nevertheless, it is encouraging that significant
improvements in intelligibility were observed with the P-
DSP/HA in spite of the much greater listening experience all
subjects had with their own aids.
V. CONCLUSION
A portable, digital sound processor, originally developed for
cochlear implant research [4], has been modified and extended.
The new version, called the P-DSP/HA, can be used with
an acoustic output transducer and a cochlear implant simul-
taneously. The acoustic output is produced by a conventional
hearing-aid earphone driven by a novel, fully-digital circuit
based on the principles of the class-D amplifier. In addition,
the P-DSP/HA includes a custom-designed bandpass filterbank
integrated circuit that can relieve the central DSP processor of
some common operations involving estimation of the incoming
spectrum. The P-DSP/HA can easily be programmed to pro-
vide frequency-shaped amplification appropriate for hearing-
impaired individuals, and a speech intelligibility test with five
subjects indicated that it could provide better performance
than the subjects’ own aids. Research is now underway to
develop more sophisticated sound processing schemes that
address particularly the problems experienced by aid users
with severe to profound hearing loss. These schemes in-
clude loudness compensation, dynamic enhancement of the
speech spectrum, and transposition to lower frequencies of
inaudible high-frequency regions of the speech spectrum. The
P-DSP/HA is a valuable tool for this research, as it allows
users to gain experience with complex sound processing in
everyday situations. Ultimately, processing techniques that
show consistent and worthwhile benefit in these studies will be
transferred to custom-designed digital integrated circuits that
are small enough, and have power requirements low enough,
for use in miniature BTE or ITE hearing instruments.
ACKNOWLEDGMENT
The author would like to thank B.-D. Lu who contributed
to the design and construction of the portable processors and
M. Dean who carried out the speech perception tests. The
contributions of the research subjects, and of many colleagues,
including Dr. H. Dillon, Dr. C. McKay, and Prof. G. M. Clark
are also gratefully acknowledged.
59
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Hugh McDermott received the degree in applied
science (electronics) with honors in 1981. He re-
ceived the Ph.D. degree from the University of
Melbourne, Melbourne, Australia, in 1988 for a dis-
sertation describing the development of an advanced
multiple channel cochlear implant.
He has contributed to various aspects of cochlear
implant design, including development of improved
sound processing schemes. He holds several patents
in this field for work which has resulted in suc-
cessful commercial outcomes. Since 1992, he has
led a small group conducting research into advanced hearing aids as part of
the Co-operative Research Centre for Cochlear Implant, Speech and Hearing
Research, East Melbourne, Australia.