THE VERILOG® HARDWARE

DESCRIPTION LANGUAGE

THIRD EDITION
THE VERILOG® HARDWARE
DESCRIPTION LANGUAGE

THIRD EDITION

by

Donald E. Thomas
Carnegie Mellon University

and

Philip R. Moorby
Avid Technology, Inc.

"
~.

Springer Science+Business Media, LLC

 Additional material to this book can be downloaded from http://extras.springer.com

ISBN 978-1-4757-2466-0 ISBN 978-1-4757-2464-6 (eBook)

DOI 10.1007/978-1-4757-2464-6

Consulting Editor: Jonathan Allen, Massachusetts Institute of Technology

Library of Congress Cataloging-in-Publication Data

A C.I.P. Catalogue record for this book is available from the Library of
Congress.

(Reference) Reprinted from IEEE Std 1364-1995 IEEE Standard Verilog

Hardware Description Language Reference Manual (LRM), Copyright ~ 1995
by the Institute of Electrical and Electronics Engineers, Inc. The IEEE
disclaims any responsibility or liability resulting from placement and use in this
publication. Information is reprinted with the permission of the IEEE.

is a registered trademark of Cadence Design Systems, Inc.

Verilog~
Synopsys~is a registered trademark of Synopsys, Inc.
DASYS is a trademark of DASYS, Inc.
Copyright ~ 1996 by Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 1996.
Softcover reprint of the hardcover 3rdedition 1996

All rights reserved. No part of this publication may be reproduced, stored in

a retrieval system or transmitted in any form or by any means, mechanical,
photo-copying, recording, or otherwise, without the prior written permission of
the publisher, Springer Science+Business Media, LLC

Printed on acid-free paper.

 To Sandie,
and John and Holland,
and Jill.
 Preface xv
••
Acknowledgments XVII

CHAPTER 1 Verilog - A Tutorial Introduction 1

Getting Started 2
A Structural Description 2
Simulating the NAND Latch 4
Module Hleral'Chy 6
The Counter 7
Components of the Counter 9
A Clock for the System 10
Tying the Whole Circuit Together 11
Using An Alternate Description of the Flip Flop 13
Behavioral Modeling 1S
A Behavioral Model of the m16 Counter 16
Mixing Structure and Behavior 18
Assignment Statements 22
Summary on Mixing Behavioral and Structural
Descriptions 23
Creating a Testbench For a Module 24
Summary 2S
Tutorial Guide to Formal Syntax
Specification 26
Exercises 30

CHAPTER 2 Behavioral Modeling 33

Process Model 33
If- Then-Else 3S
Where Does The ELSE Belong? 39
The Conditional Operator 41
Loops 41
Four Basic Loop Statements 42
Exiting Loops on Exceptional Conditions 45
Multi-way branching 46
If-Else-If 46
Case 46
Comparison of Case and If-Else-If 48
viii The Verilog Hardware Description Language

Casez and Casex 49

Functions and Tasks SO
Tasks 52
Functions 55
A Structural View 57
Rules of Scope and Hierarchical Names S9
Rules of Scope 60
Hierarchical Names 62
Summary 63
Exerdses 63

CHAPTER 3 Concurrent Processes 6S

Concu"ent Processes 6S
Events 67
Event Control Statement 67
Named Events 69
The Walt Statement 72
A Complete Producer-Consumer Handshake 74
Comparison of the Wait and While Statements 77
Comparison of Wait and Event Control
Statements 78
A Concu"ent Process Example 78
Disabling Named Blocks 84
Intra-Assignment Control and Timing
Events 87
Procedural Continuous Assignment 90
Sequential and Parallel Blocks 92
Exercises 94

CHAPTER 4 Logic Level Modeling 97

Introduction 97
Logic Gates and Nets 99
Modeling Using Primitive Logic Gates 99
Four-Level Logic Values 102
Nets 103
Module Instantiation and Port Specifications 106
A Logic Level Example 108
A"ays of Instances 113
 ix

Continuous Assignment 116

Behavioral Modeling of Combinational Circuits 118
Net and Continuous Assign Declarations 119
Parameterized Definitions 121
A Mixed Behavioral/Structural Example 125
Logic Delay Modeling 129
A Gate Level Modeling Example 130
Gate and Net Delays 131
Specifying Time Units 134
Minimum, Typical, and Maximum Delays 135
Delay Paths Across a Module 136
Summary 138
Exercises 138

CHAPTER 5 Advanced Timing 141

Verilog Timing Models 141
Basic Model of a Simulator 145
Gate Level Simulation 145
Towards a More General Model 145
Scheduling Behavioral Models 148
Non-Deterministic Behavior of the Simulation
Algorithm 151
Near a Black Hole 152
It's a Parallel Language 154
Non-Blocking Procedural Assignments 157
Contrasting Blocking and Non-Blocking
Assignments 157
Extending the Event-Driven Scheduling
Algorithm 159
Illustrating Non-Blocking Assignments 162
Summary 164
Exercises 165

CHAPTER 6 Synthesis 169

Overview of Synthesis 169
Register-Transfer Level Systems 170
Disclaimer 171
Combinational Logic Using Cates and
Continuous Assign 171
x The Verllog Hardware Description Language

Using Procedural Statements to Spedfy

Combinational Logic 173
The Basics 174
Complications - Inferred Latches 175
Specifying Don't Care Situations 177
Procedural Loop Constructs 179
Infemng Sequential Elements 180
Latch Inferences 180
Flip Flop Inferences 181
Summary 183
Infemng Trl-State Devices 184
Describing Finite State Machines 184
An Example of a Finite State Machine 185
An Alternate Approach to FSM Specification 186
Summary on Logic Synthesis 189
Behavioral Synthesis 190
Overview of Behavioral Synthesis and
Disclaimer 190
Specifying Input/Output Relationships 191
Trade-Ofts With Behavioral Synthesis Tools 193
Specification for Behavioral Synthesis 195
Summary 197
Exercises 197

CHAPTER 7 User-Defined Primitives 199

Combinational PrImitives 200
Basic Features of User-Defined Primitives 200
Describing Combinational Logic Circuits 202
Sequential PrImitives 203
Level-Sensitive Primitives 204
Edge-Sensitive Primitives 205
Shorthand Notation 207
Mixed Level- and Edge-Sensitive
PrImitives 208
Summary 210
Exercises 21 1
 xl

CHAPTER 8 Switch Level Modeling 213

A DynamIc MOS ShIft RegIster Example 273
SwItch Level Modeling 278
Strength Modeling 218
Strength Definitions 221
An Example Using Strengths 222
Resistive MOS Gates 224
AmbIguous Strengths 225
Illustrations of Ambiguous Strengths 226
The Underlying Calculations 227
The mlnlSlm Example 237
Overview 231
The miniSim Source 233
Simulation Results 242
Summary 243
ExercIses 243

CHAPTER 9 Projects 245

Modeling Power DIssIpatIon 245
Modeling Power Dissipation 246
What to do 246
Steps 247
A Floppy DIsk Controller 248
Introduction 248
Disk Format 249
Function Descriptions 250
Reality Sets In... 253
Everything You Always Wanted to Know about
CRC's 253
Supporting Verilog Modules 254

APPENDIX A Lexical Conventions 255

WhIte Space and Comments 255
Operators 256
Numbers 256
Strings 257
Identifiers, System Names, and Keywords 258
xii The Verllog Hardware Description Language

APPENDIX B Verilog Operators 261

Table of Operators 26 J
Operator Precedence 265
Operator Troth Tables 266
Expression Bit Lengths 267

APPENDIX C Verilog Gate Types 269

Logic Cates 269
BUF and NOT Cates 27J
BUFIF and NOTIF Cates 272
MOS Cates 273
Bidirectional Cates 274
CMOS Cates 275
Pullup and Pulldown Cates 275

APPENDIX D Registers, Memories, Integers, and

Time 277
Registers 277
Memories 278
Integers and Times 279

APPENDIX E System Tasks and Functions 281

Display and Write Tasks 28J
Continuous Monitoring 283
Strobed Monitoring 283
File Output 283
Simulation Time 284
Stop and Finish 284
Random 285
Reading data from disk files 285
 xiii

APPENDIX F Formal Syntax Definition 287

Source Text 288
Dedaratlons 289
PrImitive Instances 291
Module Instantiation 292
UDP Dedaratlon and Instantiation 292
Behavioral Statements 293
Spedfy Section 295
Expressions 298
General 300
 Preface

The Verilog language is a hardware description language that provides a means of

specifying a digital system at a wide range of levels of abstraction. The language sup-
ports the early conceptual stages of design with its behavioral level of abstraction, and
the later implementation stages with its structural level of abstraction. The language
provides hierarchical constructs, allowing the designer to control the complexity of a
description.

Verilog was originally designed in the winter of 1983/84 as a proprietary verifica-

tion/simulation product. Later, several other proprietary analysis tools were developed
around the language, including a fault simulator and a timing analyzer. More recently,
Verilog has also provided the input specification for logic and behavioral synthesis
tools. The Verilog language has been instrumental in providing consistency across
these tools. Now, the language has been standardized as IEEE standard #1364-1995
and is openly available for any tool to read and write. This book presents the lan-
guage, providing material for the beginning student and advanced user of the lan-
guage.

It is sometimes difficult to separate the language from the simulator tool because
the dynamic aspects of the language are defined by the way the simulator works. Fur-
ther, it is difficult to separate it from a synthesis tool because the semantics of the lan-
guage become limited by what a synthesis tool allows in its input specification and
produces as an implementation. Where possible, we have stayed away from simula-
xvi The Verllog Hardware Description Language

tor- and synthesis-specific details and concentrated on design specification. But, we

have included enough infonnation to be able to write working executable models.

The book takes a tutorial approach to presenting the language. Indeed, we start
with a tutorial introduction that presents, via examples, the major features of the lan-
guage. We then continue with a more complete discussion of the language constructs.
Numerous examples are provided to allow the reader to learn (and re-Iearn!) easily by
example. Finally, in the appendix we provide a fonnal description of the language.
Overall, our approach is to provide a means of learning by observing the examples,
and doing the exercises.

We have provided a set of exercises to stimulate thought while reading the book.
It is strongly recommended that you try the exercises as early as possible with the aid
of a Verilog simulator. Or, if you have your own designs, or some from a data book,
try them out too. The examples shown in the book are available in electronic fonn.
For access, refer to http://www.ece.cmu.edulfaculty/thomas.html. Alternatively, send
e-mail to thomas+verilogbookexamples@ece.cmu.edu. The examples will automati-
cally be sent back in return e-mail.

The book assumes a knowledge of introductory logic design and software pro-
gramming. As such, the book is of use to practicing integrated circuit design engi-
neers, and undergraduate and graduate electrical or computer engineering students.
The tutorial introduction provides enough infonnation for students in an introductory
logic design course to make simple use of logic simulation as part of their laboratory
experience. The rest of the book could then be used in upper level logic design and
architecture courses as it provides more in-depth coverage of the language and exam-
ples of its usage.

The book is organized into nine chapters and six appendices. We start with the
tutorial introduction to the language in chapter 1. Chapters 2 and 3 present the lan-
guage's behavioral modeling constructs, while chapter 4 presents logic level model-
ing. Chapter 5 covers advanced topics in timing and event driven simulation. Use of
the language for synthesis is presented in chapter 6. Chapters 7 and 8 then present the
more advanced topics of user-defined primitives, and switch level modeling. Chapter
9 suggests two major Verilog projects for use in a university course. The appendices
are reserved for the dryer topics typically found in a language manual; read them at
your own risk.

Have fun designing great systems ...

Always,
Donald E. Thomas
Philip R. Moorby
 Acknowledgments

The authors would like to acknowledge Open Verilog International, whose role it is to
maintain and promote the Verilog standard, and the many CAD tool developers and
system designers who have contributed to the continuing development of the Verilog
language. In particular, the authors would like to thank Leigh Brady for her help in
reviewing earlier manuscripts, and Elliot Mednick for organizing the information on
the CD-ROM that comes with the book. The authors would also like to thank C. Gor-
don Bell, Giovanni De Micheli, Peter Eichenberger, Tom Fu~an, John Hagerman,
Beth Lagnese, Tom Martin, Trevor Mudge, Karem Sakallah, John Sanguinetti, Her-
man Schmit, Dave Springer, and Clovis L. Tondo for their help and suggestions. H.
Fatih Ugurdag provided us with Example 6.17.
THE VERILOG® HARDWARE
DESCRIPTION LANGUAGE

THIRD EDITION