ECE 124 – Digital Circuits and Systems

Dept. of ECE, Univ. of Waterloo

Lecture Slides: Set 7 - Part 5

Contents:
• Flip-flop choices in synchronous sequential circuits

©2014-2020 M. A. Hasan. These slides and notes are for the exclusive use of the students registered
in the course. Reproduction in any form or use for any other purposes is prohibited.

Set 7 - Part 5 1
 Use of different types of flip-flops

• So far, we have only used DFFs to realize current states

• DFF is an obvious choice because the FF input equations are
the next state equations
• Other types of flip-flops (e.g., TFF and JKFF) may be used
(and may lead to less expensive circuits)
• For TFF and JKFF, the flip-flop input equations are not the
next state equations and need to be derived as follows:
- Based on the FF excitation table, determine how the FF
input must be set to get the next state from the current
state
• An excitation table for a FF is just an expanded form of its
characteristic table showing current inputs and outputs that
excite the next outputs

Set 7 - Part 5 2
 FF excitation tables

𝐷𝐷 𝑄𝑄(𝑡𝑡 + 1) 𝑇𝑇 𝑄𝑄(𝑡𝑡 + 1)

0 0 0 𝑄𝑄(𝑡𝑡)
1 1 1 𝑄𝑄𝑄(𝑡𝑡)

1) DFF characteristic table 3) TFF characteristic table

𝐷𝐷 𝑄𝑄(𝑡𝑡) 𝑄𝑄(𝑡𝑡 + 1) 𝑇𝑇 𝑄𝑄(𝑡𝑡) 𝑄𝑄(𝑡𝑡 + 1)

0 0 0 0 0 0
1 0 1 1 0 1
0 1 0 0 1 1
1 1 1 1 1 0

2) DFF excitation table 4) TFF excitation table

[Clearly, 𝑄𝑄 𝑡𝑡 + 1 = 𝐷𝐷] [Note that 𝑄𝑄 𝑡𝑡 + 1 = 𝑇𝑇𝑄𝑄′(𝑡𝑡) + 𝑇𝑇𝑇𝑄𝑄(𝑡𝑡),
i.e., if 𝑄𝑄(𝑡𝑡)=0, then 𝑄𝑄 𝑡𝑡 + 1 = 𝑇𝑇, else
Set 7 - Part 5 𝑄𝑄 𝑡𝑡 + 1 = 𝑇𝑇′] 3
 FF excitation tables (contd.)

𝐽𝐽 𝐾𝐾 𝑄𝑄(𝑡𝑡) 𝑄𝑄(𝑡𝑡 + 1)
𝐽𝐽 𝐾𝐾 𝑄𝑄(𝑡𝑡 + 1)
0 0 0 0
0 0 𝑄𝑄(𝑡𝑡)
0 0 1 1
0 1 0
0 1 0 0
1 0 1
0 1 1 0
1 1 𝑄𝑄𝑄(𝑡𝑡)
1 0 0 1
5) JKFF characteristic table
1 0 1 1
1 1 0 1
𝐽𝐽 𝐾𝐾 𝑄𝑄(𝑡𝑡) 𝑄𝑄(𝑡𝑡 + 1)
1 1 1 0
0 X 0 0
6) JKFF excitation table
1 X 0 1
Note that:
X 0 1 1
• 𝑄𝑄(𝑡𝑡 + 1)=𝐽𝐽 𝑄𝑄𝑄(𝑡𝑡) + 𝐾𝐾𝐾 𝑄𝑄(𝑡𝑡)
X 1 1 0 • I.e.,
- if 𝑄𝑄(𝑡𝑡)=0, then 𝑄𝑄(𝑡𝑡 + 1)=𝐽𝐽 and
7) JKFF excitation table (short form) - if 𝑄𝑄(𝑡𝑡)=1, then 𝑄𝑄(𝑡𝑡 + 1)=𝐾𝐾𝐾
Set 7 - Part 5 4
 Excitation tables for an example circuit
• Consider the following state-assignment table for a sequential
circuit
Next state
Present
w = 0 w = 1 Output
state
z
𝑦𝑦2 𝑦𝑦1 𝑌𝑌2 𝑌𝑌1 𝑌𝑌2 𝑌𝑌1
A 00 00 01 0
B 01 00 10 0
C 10 00 10 1
11 dd dd d

• The corresponding excitation tables using D, T and JK flip-flops

follow

Set 7 - Part 5 5
 Excitation tables for an example circuit (contd.)
• Excitation table using DFFs

Present Next state (𝑌𝑌2 𝑌𝑌1 ) & flip-flop input (𝐷𝐷2 𝐷𝐷1 )
Output
state w=0 w=1
z
𝑦𝑦2 𝑦𝑦1 𝑌𝑌2 𝑌𝑌1 𝐷𝐷2 𝐷𝐷1 𝑌𝑌2 𝑌𝑌1 𝐷𝐷2 𝐷𝐷1
00 00 00 01 01 0
01 00 00 10 10 0
10 00 00 10 10 1
11 dd dd dd dd d

• Note that 𝑦𝑦1 and 𝑦𝑦2 can be viewed as 𝑄𝑄1 (𝑡𝑡) and 𝑄𝑄2 𝑡𝑡 ,
respectively. Similarly, 𝑌𝑌1 and 𝑌𝑌2 can be viewed as 𝑄𝑄1 (𝑡𝑡 + 1)
and 𝑄𝑄2 𝑡𝑡 + 1 , respectively.
• Using K-maps with don’t cares, we can write
𝐷𝐷1 = 𝑤𝑤𝑤𝑤1′ 𝑦𝑦2′ , 𝐷𝐷2 =𝑤𝑤(𝑦𝑦1 + 𝑦𝑦2 )
Set 7 - Part 5 6
 Excitation tables for an example circuit (contd.)
• Excitation table using TFFs
Present Next state (𝑌𝑌2 𝑌𝑌1 ) & flip-flop input (𝑇𝑇2 𝑇𝑇1 )
state Output
w=0 w=1
z
𝑦𝑦2 𝑦𝑦1 𝑌𝑌2 𝑌𝑌1 𝑇𝑇2 𝑇𝑇1 𝑌𝑌2 𝑌𝑌1 𝑇𝑇2 𝑇𝑇1
00 00 00 01 01 0
01 00 01 10 11 0
10 00 10 10 00 1
11 dd dd dd dd d

• Recall that for TFF, 𝑄𝑄 𝑡𝑡 + 1 = 𝑇𝑇𝑇𝑇𝑇(𝑡𝑡) + 𝑇𝑇𝑇𝑇𝑇(𝑡𝑡), i.e., if

𝑄𝑄(𝑡𝑡)=0, then 𝑄𝑄 𝑡𝑡 + 1 = 𝑇𝑇, else 𝑄𝑄 𝑡𝑡 + 1 = 𝑇𝑇𝑇. This is used in
completing the columns with titled 𝑇𝑇2 𝑇𝑇1
• We can write
𝑇𝑇1 = 𝑤𝑤 ′ 𝑦𝑦1 + 𝑤𝑤𝑦𝑦2′ , 𝑇𝑇2 =𝑤𝑤 ′ 𝑦𝑦2 +𝑤𝑤𝑤𝑤1

Set 7 - Part 5 7
 Excitation tables for an example circuit (contd.)
• Excitation table using JKFFs

Present Next state (𝑌𝑌2 𝑌𝑌1 ) & flip-flop input (𝐽𝐽𝑖𝑖 𝐾𝐾𝑖𝑖 )
state Output
w=0 w=1
z
𝑦𝑦2 𝑦𝑦1 𝑌𝑌2 𝑌𝑌1 𝐽𝐽2 𝐾𝐾2 𝐽𝐽1 𝐾𝐾1 𝑌𝑌2 𝑌𝑌1 𝐽𝐽2 𝐾𝐾2 𝐽𝐽1 𝐾𝐾1
00 00 0d 0d 01 0d 1d 0
01 00 0d d1 10 1d d1 0
10 00 d1 0d 10 d0 0d 1
11 dd dd dd dd dd dd d
• Recall that for JKFF, if 𝑄𝑄 𝑡𝑡 = 0, then 𝑄𝑄 𝑡𝑡 + 1 = 𝐽𝐽 and if
𝑄𝑄(𝑡𝑡) = 1, then 𝑄𝑄(𝑡𝑡 + 1) = 𝐾𝐾𝐾. This is used in completing the
columns with titled (𝐽𝐽𝑖𝑖 𝐾𝐾𝑖𝑖 )
• We can write (assuming that the above table is correct)
𝐽𝐽1 = 𝑤𝑤𝑦𝑦2′ , 𝐾𝐾1 =1, 𝐽𝐽2 = 𝑤𝑤𝑦𝑦1 , 𝐾𝐾2 =𝑤𝑤’
which cost less than the designs based on DFF and TFF
Set 7 - Part 5 8
 ECE 124 – Digital Circuits and Systems
Dept. of ECE, Univ. of Waterloo

Lecture Slides: Set 7 - Part 6

Contents:
• Analysis of synchronous sequential circuits

©2014-2020 M. A. Hasan. These slides and notes are for the exclusive use of the students registered
in the course. Reproduction in any form or use for any other purposes is prohibited.

Set 7 - Part 6 1
 Analysis of synchronous sequential circuits

• Given a synchronous sequential circuit, analysis involves

figuring out the circuit behavior, i.e., a state table or diagram
for the circuit
• Analysis is the reserve task of synthesis or design
• Basic steps are the following
1. Write down the logic expressions for the circuit outputs
and the flip-flop inputs
2. Use the logic expressions to derive a state table which
describe the next state and circuit outputs

Set 7 - Part 6 2
Analysis of synchronous sequential circuits (contd.)
Consider the following circuit
J1 y1
w J Q
z

K Q
K1

J2 y2
J Q
Clock
K Q
K2

Resetn

We can easily write

output 𝑧𝑧 = 𝑦𝑦1 𝑦𝑦2 , and FF input 𝐽𝐽1 = 𝑤𝑤, 𝐾𝐾1 = 𝑤𝑤 ′ + 𝑦𝑦2′ , 𝐽𝐽2 = 𝑤𝑤𝑦𝑦1 , and 𝐾𝐾2 = 𝑤𝑤′
Set 7 - Part 6 3
 Analysis of synchronous sequential circuits (contd.)
The excitation table for the circuit is given below

Present Flip-flop inputs

state w= 0 w= 1 Output
y2 y1 z
J 2K 2 J 1K 1 J 2K 2 J 1K 1

00 01 01 00 11 0
01 01 01 10 11 0
10 01 01 00 10 0
11 01 01 10 10 1

From the excitation table for JKFF,

• 𝑦𝑦𝑖𝑖 = 0 means the corresponding 𝑌𝑌𝑖𝑖 = 𝐽𝐽𝑖𝑖
• 𝑦𝑦𝑖𝑖 = 1 means the corresponding 𝑌𝑌𝑖𝑖 = 𝐾𝐾𝑖𝑖′
Thus we have the following state table
Set 7 - Part 6 4
Analysis of synchronous sequential circuits (contd.)

Next state
Present
w = 0 w = 1 Output
state
z
𝑦𝑦2 𝑦𝑦1 𝑌𝑌2 𝑌𝑌1 𝑌𝑌2 𝑌𝑌1
00 00 01 0
01 00 10 0
10 00 11 0
11 00 11 1

Set 7 - Part 6 5