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Lecture 200 - Clock and Data Recovery Circuits: (References (6) ) Objective
Lecture 200 - Clock and Data Recovery Circuits: (References (6) ) Objective
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-2
Recovered
Clock
t
Fig. 4.2-01
Most all clock recovery circuits employ some form of a PLL.
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-4
ω
0 2π 4π 6π 8π
Tb Tb Tb Tb
Fig. 4.2-04
†
S.K.Shanmugam, Digital and Analog Communication Systems, New York: Wiley &Sons, 1979.
ECE 6440 - Frequency Synthesizers © P.E. Allen - 2003
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-6
Edge Detection
CRC circuits require the ability to detect both the positive and negative transitions of the
incoming data as illustrated below,
NRZ
Data
Edge
Detection
Fig. 4.2-05
Methods of edge detection:
1.) EXOR gate with a delay on one input.
Din
Dout
∆
Fig. 4.2-06
2.) A differentiator followed by a full-wave rectifier.
Out
Din d
Dout
dt
In Fig. 4.2-07
Fig. 4.2-09
XVCO
D
CLK Q
D Latch
Fig. 4.2-10
ECE 6440 - Frequency Synthesizers © P.E. Allen - 2003
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-8
In essence, the high-Q oscillator is “synchronized” with the input transitions and
oscillates freely in their absence. Synchronization is achieved by means of phase locking.
Fig. 4.2-11
Operation:
1.) Assume the input data is periodic with a frequency of 1/Tb (Hz).
2.) The edge detector doubles the frequency causing the PLL to lock to 2/Tb (Hz).
3.) If a number of transitions are absent, the output of the multiplier is zero and the
control voltage applied to the VCO begins to decay causing the oscillator to drift from
1/Tb (Hz).
4.) To minimize the drift due to the lack of transitions,
τLPF >> Maximum allowable interval between consecutive transitions.
5.) The result is a small loop bandwidth and a narrow capture range. Fortunately, most
communication systems guarantee an upper bound of the allowable interval between
consecutive transitions by encoding the data.
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-10
I_clk
Loop data Loop
VCO VCO
Filter Filter
Q_clk
N
If no reference clock is available, a frequency detector has to be used which requires I and
Q clocks and for typical implementations, the VCO frequency cannot be off more that
about 25% of the data rate.
data
D Q D Q
A B
clk
Clock rising edge is at data center: Clock is 0.5 period ahead of data center.
data data
clk
clk
A A
B B
up up
down down
†
C. R. Hogge, IEEE J. Lightwave Technology, pp. 1312-1314, 1985.
ECE 6440 - Frequency Synthesizers © P.E. Allen - 2003
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-12
-π 0 +π Phase
11001100
error
data density
-0.5
101010
data density
-1.0
clk
A B C A B C
down
D Q
B
D Q Binary Phase Detector Truth-Table
ABC Decision Output
Normalized 000 Tri-state -------
average
up/down output
+1 001 Clock is ahead Down
010 Error -------
Phase 011 Clock is behind Up
0 error
100 Clock is behind Up
101 Error -------
110 Clock is ahead Down
-1
111 Tri-state -------
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-14
clk Phase
0 error
up/down
A
D Q D Q -1
clk clk
retimed retimed
data data
A A
up / up /
down down
†
M. Meghelli, et. al. ISSCC’2000, pp. 56-57.
ECE 6440 - Frequency Synthesizers © P.E. Allen - 2003
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-15
up Normalized frequncy
DE-FF DE-FF
A C +1 detector gain
I-clk D Q D Q
data
fdata fdata 3fdata fdata frequency
2 4 8 8 error
0 f data f data 3fdata f data
B D down 8 4 8 2
Q-clk D Q D Q
DE-FF DE-FF
-1
Timing diagram example: (VCO clock is faster than the data rate)
data
I_clk
Q_clk
A
B
up 10 11 01 00 10 10 11 00 10 11 01 01 10 01 00 10 11 01 01 10 11 11 01 00 10
down
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-16
01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11
00 10
I
00 10
I
00 10
I
00 10
I
00 10
I
00 10
I
00 10
I
00 10
I
00 10
I
fVCO = 1.125 x data rate
Q Q Q Q Q Q Q Q Q
01 11
I
01 11
I
01 11
I
01 11
I
01 11
I
01 11
I
01 11
I
01 11
I
01 11
I fVCO = 1.250 x data rate
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
Q Q Q Q Q Q Q Q Q
01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11
I I I I I I I I I
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
fVCO = 1.375 x data rate
Q Q Q Q Q Q Q Q Q
01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11
I I I I I I I I I
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10
fVCO = 1.500 x data rate
Q Q Q Q Q Q Q Q Q
01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11 01 11
I I I I I I I I I
00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 00 10 fVCO = 1.625 x data rate
Normalized frequncy
+1 detector gain
If the VCO frequency is off more than 50%,
fc 3fc fc fc
the frequency is in the wrong direction. 4 2 4 frequency
0 fc fc 3f c fc error
4 2 4
-1
ECE 6440 - Frequency Synthesizers © P.E. Allen - 2003
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-17
DE-FF
Q1 up /
I-clk D Q
down Logic Table of Pottbacker’s Frequency Detector
Q1 Q2 Q3
data X 1 0
Rising 0 -1
Q2 Q3 Falling 0 +1
Q-clk D Q D Q
DE-FF FD
†
A. Pottbacker, et. al., IEEE JSSC, pp. 1747-1751, Dec. 1992.
ECE 6440 - Frequency Synthesizers © P.E. Allen - 2003
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-18
CDR ARCHITECTURES
Clock Recovery – Spectral Line, Early-Late
Enam, Abidi 1992
Interleaved decision circuit
Interleaved VDD
Decision Circuit
Din Dout
D Q Output- Output+
Loop II
cos (ω1-ω2)t d
Fig 4.2-13 LPF dt
Edge detector plus three loops-
Loops I and II perform frequency detection
Loop III performs phase detection
Operation:
The signal at P is (ω1-ω2) cos2(ω1-ω2) ⇒ VCO is driven by sin(ω1-ω2)t + (ω1-ω2)
Loops I and II drive the VCO to lock when ω1≠ω2. As |ω1-ω2| approaches zero,
Loop III begins to generate an asymmetrical signal at node M assisting the lock
process. Finally, when ω1≈ω2, the dc feedback signal produced by Loops I and II
approaches zero and Loop III dominates, locking the VCO output to the input data.
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-20
Quadricorrelator – Continued
The use of frequency detection in the quadricorrelator makes the capture range
independent of the locked loop bandwidth, allowing a small cutoff frequency in the LPF of
Loop III so as to minimize the VCO drift between data transitions.
Because Loops I and II can respond to noise and spurious components, it is desirable to
disable these loops once phase lock has been attained.
Since the combination of an edge detector and a mixer can be replaced with a double-
edge triggered flipflop, the quadricorrelator can be implemented in a digital form as
shown below.
CLK Q
NRZ D
Data Edge 0° D
Detector VCO LPF Q CLK
90°
D
Fig. 4.2-14 CLK Q
All flipflops are double-edge-triggered
Oscillator
Output
∆T Fig. 4.2-17
- Diverges for a free-runnng oscillator
- Meaningful only in a phase-locked system
- Depends on PLL dynamics
• Cycle-to-cycle jitter
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-22
(Razavi: IEEE Trans. on Circuits and Systems, Part II, Jan. 99)
Sources of Jitter
• Input jitter Din fosc
PD LPF VCO
Fig. 4.2-19
Din fosc
PD LPF VCO
Fig. 4.2-20
Fig. 4.2-21
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-24
Present Solution:
Keep circuit separate by using multiple substrates and put the multiple substrates in the
same package.
;; ;
RL Substrate Noise
vin vout vout
VGS vin
vin VDD(Analog)
;;;
;;;;;
;;; ;;;
vin vout RL
VDD(Digital) VGS
Digital Ground
n+ channel vout Analog Ground
stop (1 Ω-cm)
;;;
;;;;;
;;; ;;;
p+ n+ n+ p+ p+ n+ n+ n+ p+
p+ channel stop (1Ω-cm)
n- well "AC ground"
Hot Back-gating due to a
iD
Carrier momentary change in
Put substrate connections reverse bias
as close to the noise source
as possible ∆iD
ID
"AC ground" ∆iD
vGS
p- substrate (10 Ω-cm) VGS
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-26
;; ;
RL Substrate Noise
vin vout vout
VGS vin
vin VDD(Analog)
;;;
;;;;;
;;; ;;;
vin vout RL
VDD(Digital) VGS
Digital Ground vout Analog Ground
;;;
;;;;;
;;; ;;;
p+ n+ n+ p+ p+ n+ n+ n+ p+
n- well "AC ground" p-epitaxial Reduced back
Put substrate Hot layer (15 Ω-cm) gating due to
connections Carrier smaller resistance
as close to the
noise source
as possible
"AC ground"
;;
VDD
vin vout
L1
Cs1
n- well
Digital Ground VDD(Digital)
;;; ;;;
;;;;;
vin vout
Cs3 Cs2
vin vout Rs1 Substrate
;;;;;;;;
;;;
Rs2
Rs3
p+ n+ n+ p+ p+ n+
n- well Cs4
;;;;;
Hot Cs5
Carrier Coupling
Hot
L2 L3
Carrier Coupling
Coupling
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-28
;
RL Substrate Noise
vin vout
VGS VDD
VDD(Analog)
vin RL RL
vout
vout
;;;
VGS Analog Ground L4 CL
;;;
L6
n+ n+ p+
VGS
Cs6 Rs4 Cs7
Substrate
Cs5
L5
Inductor
Substrate BJT
;;;;;;;;
Collector Base Emitter Collector
n+ p+ n+ n+
p- well
Fig. SI-04
Heavily Lightly Intrinsic Lightly Heavily Metal
Doped p Doped p Doping Doped n Doped n
Also, there is coupling from power supplies and clock lines to other adjacent signal lines.
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-30
Fig. SI-05
ECE 6440 - Frequency Synthesizers © P.E. Allen - 2003
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-31
Lecture 200 – Clock and Data Recovery Circuits - I (6/26/03) Page 200-32
(To be continued)