K6X1008C2D Family CMOS SRAM

Document Title
128Kx8 bit Low Power CMOS Static RAM

Revision History
Revision No. History Draft Data Remark
0.0 Initial draft July 15, 2002 Preliminary

0.1 Revised December 4, 2002 Preliminary

- Deleted 32-TSOP1-0820R Package Type.
- Added Commercial product.

0.2 Revised May 13, 2003 Preliminary

- Added Lead Free 32-SOP-525 Product

0.3 Revised June 21, 2003 Preliminary

- Added Lead Free 32-TSOP1-0820F Product

1.0 Finalized September 16, 2003 Final

- Changed ICC from 10mA to 5mA
- Changed ICC2 from 35mA to 25mA
- Changed ISB from 3mA to 0.4mA
- Changed IDR(industrial) from 15µA to 10µA
- Changed IDR(Automotive) from 25µA to 20µA

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.

1 Revision 1.0
September 2003
 K6X1008C2D Family CMOS SRAM
128Kx8 bit Low Power full CMOS Static RAM
FEATURES GENERAL DESCRIPTION
• Process Technology: Full CMOS The K6X1008C2D families are fabricated by SAMSUNG′s
• Organization: 128K x 8 advanced CMOS process technology. The families support
• Power Supply Voltage: 4.5~5.5V verious operating temperature ranges and have various pack-
• Low Data Retention Voltage: 2V(Min)
age types for user flexibility of system design. The families
• Three state output and TTL Compatible
also support low data retention voltage for battery back-up
• Package Type: 32-DIP-600, 32-SOP-525,
operation with low data retention current.
32-SOP-525, 32-TSOP1-0820F

PRODUCT FAMILY
Power Dissipation
Operating
Product Family Vcc Range Speed PKG Type
Temperature Standby Operating
(ISB1, Max) (ICC2, Max)
K6X1008C2D-B Commercial(0~70°C) 10µA 32-DIP-600, 32-SOP-525,
32-SOP-525
K6X1008C2D-F Industrial(-40~85°C) 4.5~5.5V 551)/70ns 15µA 25mA 32-TSOP1-0820F

K6X1008C2D-Q Automotive(-40~125°C) 25µA 32-SOP-525, 32-TSOP1-0820F

1. The parameters are tested with 50pF test load

PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM

Clk gen. Precharge circuit.

NC 1 32 VCC
A16 2 31 A15
A14 3 30 CS2
A12 4 29 WE A11 1 32 OE
A9 2 31 A10
A7 5 28 A13 A8 3 30
Row Row
CS1 Memory array
A13 4 29 I/O8 addresses select
A6 6 32-SOP 27 A8
WE 5 28 I/O7
A5 7 26 A9 CS2 6 27 I/O6
32-DIP A15 7 26 I/O5
A4 8 25 A11 VCC 8 32-TSOP 25 I/O4
NC 9 24 VSS
A3 9 24 OE
A16 10
Type1-Forward 23 I/O3
A2 10 23 A10 A14 11 22 I/O2
A12 12 21 I/O1
A1 11 22 CS1 A7 13 20 A0
A0 12 21 I/O8 A6 14 19 A1
A5 15 18 A2
I/O1 13 20 I/O7 A4 16 17
I/O1 Data I/O Circuit
A3
19
cont Column select
I/O2 14 I/O6 I/O8
I/O3 15 18 I/O5
VSS 16 17 I/O4
Data
cont

Column Addresses
Name Function
CS1, CS2 Chip Select Input
CS1
OE Output Enable Input
CS2 Control
WE Write Enable Input logic
WE

OE
I/O1~I/O8 Data Inputs/Outputs
A0~A16 Address Inputs
Vcc Power
Vss Ground
NC No Connection

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

2 Revision 1.0
September 2003
K6X1008C2D Family CMOS SRAM

PRODUCT LIST
Commercial Products(0~70°C) Industrial Products(-40~85°C) Automotive Products(-40~125°C)
Part Name Function Part Name Function Part Name Function
K6X1008C2D-DB55 32-DIP, 55ns, LL K6X1008C2D-DF55 32-DIP, 55ns, LL K6X1008C2D-GQ55 32-SOP, 55ns, L
K6X1008C2D-DB70 32-DIP, 70ns, LL K6X1008C2D-DF70 32-DIP, 70ns, LL K6X1008C2D-GQ70 32-SOP, 70ns, L
K6X1008C2D-GB55 32-SOP, 55ns, LL K6X1008C2D-GF55 32-SOP, 55ns, LL K6X1008C2D-TQ55 32-TSOP-F, 55ns, L
K6X1008C2D-GB70 32-SOP, 70ns, LL K6X1008C2D-GF70 32-SOP, 70ns, LL K6X1008C2D-TQ70 32-TSOP-F, 70ns, L
K6X1008C2D-BB551) 32-SOP, 55ns, LL K6X1008C2D-BF551) 32-SOP, 55ns, LL
K6X1008C2D-BB701) 32-SOP, 70ns, LL K6X1008C2D-BF701) 32-SOP, 70ns, LL
K6X1008C2D-TB55 32-TSOP-F, 55ns, LL K6X1008C2D-TF55 32-TSOP-F, 55ns, LL
K6X1008C2D-TB70 32-TSOP-F, 70ns, LL K6X1008C2D-TF70 32-TSOP-F, 70ns, LL
K6X1008C2D-PB551) 32-TSOP-F, 55ns, LL K6X1008C2D-PF551) 32-TSOP-F, 55ns, LL
K6X1008C2D-PB701) 32-TSOP-F, 70ns, LL K6X1008C2D-PF701) 32-TSOP-F, 70ns, LL

1. Lead Free Product

FUNCTIONAL DESCRIPTION
CS1 CS2 OE WE I/O Mode Power
H X1) X1) X1) High-Z Deselected Standby
X1) L X1) X1) High-Z Deselected Standby
L H H H High-Z Output Disabled Active
L H L H Dout Read Active
L H X1) L Din Write Active
1. X means don′t care (Must be in high or low states)

ABSOLUTE MAXIMUM RATINGS1)

Item Symbol Ratings Unit Remark
Voltage on any pin relative to Vss VIN,VOUT -0.5 to VCC+0.5V(Max. 7.0V) V -
Voltage on Vcc supply relative to Vss VCC -0.3 to 7.0 V -
Power Dissipation PD 1.0 W -
Storage temperature TSTG -65 to 150 °C -
0 to 70 °C K6X1008C2D-B
Operating Temperature TA -40 to 85 °C K6X1008C2D-F
-40 to 125 °C K6X1008C2D-Q
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

3 Revision 1.0
September 2003
K6X1008C2D Family CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS1)

Item Symbol Min Typ Max Unit
Supply voltage Vcc 4.5 5.0 5.5 V
Ground Vss 0 0 0 V
Input high voltage VIH 2.2 - Vcc+0.5 2) V
Input low voltage VIL -0.5 3) - 0.8 V
Note:
1. Commercial Product: TA=0 to 70°C, Otherwise specified
Industrial Product: TA=-40 to 85°C, Otherwise specified
Automotive Product: TA=-40 to 125°C, Otherwise specified
2. Overshoot: Vcc+3.0V in case of pulse width≤30ns.
3. Undershoot: -3.0V in case of pulse width≤30ns.
4. Overshoot and undershoot are sampled, not 100% tested.

CAPACITANCE1) (f=1MHz, TA=25°C)

Item Symbol Test Condition Min Max Unit
Input capacitance CIN VIN=0V - 8 pF
Input/Output capacitance CIO VIO=0V - 10 pF
1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item Symbol Test Conditions Min Typ Max Unit
Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA
Output leakage current ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA
Operating power supply current ICC IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read - - 5 mA

ICC1 Cycle time=1µs, 100%duty, IIO=0mA, CS1≤0.2V, CS2≥Vcc-0.2V, - - 7 mA

VIN≤0.2V or VIN≥VCC-0.2V
Average operating current
ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, - - 25 mA
VIN=VIH or VIL
Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.4 - - V
Standby Current(TTL) ISB CS1=VIH, CS2=VIL, Other inputs=VIH or VIL - - 0.4 mA
K6X1008C2D-B - - 10 µA
CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or
Standby Current(CMOS) ISB1
CS2≤0.2V, Other inputs=0~Vcc K6X1008C2D-F - - 15 µA
K6X1008C2D-Q - - 25 µA

4 Revision 1.0
September 2003
K6X1008C2D Family CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS( Test Load and Input/Output Reference)
Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns CL1)
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL 1. Including scope and jig capacitance
CL=50pF+1TTL

AC CHARACTERISTICS
(VCC=4.5~5.5V, Commercial product: TA=0 to 70°C, Industrial product: TA=-40 to 85°C, Automotive product: TA=-40~125°C)

Speed Bins
Parameter List Symbol 55ns 70ns Units

Min Max Min Max

Read Cycle Time tRC 55 - 70 - ns
Address Access Time tAA - 55 - 70 ns
Chip Select to Output tCO - 55 - 70 ns
Output Enable to Valid Output tOE - 25 - 35 ns
Read Chip Select to Low-Z Output tLZ 10 - 10 - ns
Output Enable to Low-Z Output tOLZ 5 - 5 - ns
Chip Disable to High-Z Output tHZ 0 20 0 25 ns
Output Disable to High-Z Output tOHZ 0 20 0 25 ns
Output Hold from Address Change tOH 10 - 10 - ns
Write Cycle Time tWC 55 - 70 - ns
Chip Select to End of Write tCW 45 - 60 - ns
Address Set-up Time tAS 0 - 0 - ns
Address Valid to End of Write tAW 45 - 60 - ns
Write Pulse Width tWP 40 - 50 - ns
Write
Write Recovery Time tWR 0 - 0 - ns
Write to Output High-Z tWHZ 0 20 0 25 ns
Data to Write Time Overlap tDW 20 - 25 - ns
Data Hold from Write Time tDH 0 - 0 - ns
End Write to Output Low-Z tOW 5 - 5 - ns

DATA RETENTION CHARACTERISTICS

Item Symbol Test Condition Min Typ Max Unit
Vcc for data retention VDR CS1≥Vcc-0.2V1) 2.0 - 5.5 V
K6X1008C2D-B - - 10 µA
Data retention current IDR Vcc=3.0V, CS1≥Vcc-0.2V1) K6X1008C2D-F - - 10 µA
K6X1008C2D-Q - - 20 µA
Data retention set-up time tSDR 0 - -
See data retention waveform ms
Recovery time tRDR 5 - -

1. CS1≥Vcc-0.2V, CS2≥VCC-0.2V, or CS2≤0.2V

5 Revision 1.0
September 2003
K6X1008C2D Family CMOS SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
tRC
Address
tAA
tOH
Data Out Previous Data Valid Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC
Address
tOH
tAA
tCO1
CS1

tHZ(1,2)

CS2
tCO2
tOE

OE

tOLZ tOHZ
tLZ
Data out High-Z Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.

6 Revision 1.0
September 2003
K6X1008C2D Family CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

tWC
Address
tWR(4)
tCW(2)
CS1

tAW

CS2
tCW(2)

tWP(1)
WE
tAS(3)
tDW tDH

Data in Data Valid

tWHZ
tOW
Data out Data Undefined

TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)

tWC
Address

tAS(3) tCW(2)
tWR(4)
CS1

tAW

CS2

tWP(1)

WE

tDW tDH

Data in Data Valid

Data out High-Z High-Z

7 Revision 1.0
September 2003
K6X1008C2D Family CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)

tWC
Address

tAS(3) tCW(2)
tWR(4)
CS1

tAW

CS2

tCW(2)
tWP(1)
WE

tDW tDH

Data in Data Valid

Data out High-Z High-Z

NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS1 going low or CS2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1 or WE going high tWR2 applied
in case a write ends as CS2 going to low.

DATA RETENTION WAVE FORM

CS1 controlled
tSDR Data Retention Mode tRDR
VCC
4.5V

2.2V

VDR

CS≥VCC - 0.2V
CS1
GND

CS2 controlled
Data Retention Mode
VCC
4.5V
CS2
tSDR tRDR

VDR

0.4V CS2≤0.2V

GND

8 Revision 1.0
September 2003
K6X1008C2D Family CMOS SRAM
PACKAGE DIMENSIONS Units: millimeters(inches)
32 DUAL INLINE PACKAGE (600mil)
+0.10
0.25 -0.05
0.010+0.004
-0.002

#32 #17

15.24
0.600
13.60±0.20
0.535±0.008

#1 #16 0~15°
42.31 MAX 3.81±0.20
1.666 0.150±0.008
5.08
41.91±0.20 0.200 MAX
1.650±0.008

0.46±0.10 3.30±0.30
0.018±0.004 0.130±0.012
0.38
( 1.91 ) 1.52±0.10 2.54
0.015 MIN
0.075 0.060±0.004 0.100

32 PLASTIC SMALL OUTLINE PACKAGE (525mil)

0~8°

#32 #17

13.34
0.525

14.12±0.30 11.43±0.20
0.556±0.012 0.450±0.008

#1 #16 0.80±0.20
20.87 MAX 2.74±0.20 0.20 +0.10
-0.05 0.031±0.008
0.822 0.108±0.008 0.008+0.004
-0.002
3.00
20.47±0.20 0.118 MAX
0.806±0.008

0.10 MAX
0.004 MAX

+0.100
0.41 -0.050
( 0.71 ) +0.004
0.016 -0.002
1.27
0.05
0.028 0.050 0.002 MIN

9 Revision 1.0
September 2003
K6X1008C2D Family CMOS SRAM
PACKAGE DIMENSIONS Units: millimeters(inches)
32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)

0.20 +0.10 20.00±0.20

-0.05
0.787±0.008
0.008+0.004
-0.002

#1 #32

0.25
( )
0.010

0.315
8.00
8.40
0.331 MAX

0.50
0.0197 #16 #17
1.00±0.10 0.05
0.039±0.004 0.002 MIN
1.20
0.25 18.40±0.10 0.047 MAX
0.010 TYP 0.724±0.004
+0.10
0.15 -0.05
0.006+0.004
-0.002

0.004 MAX
0.10 MAX
0~8°

0.45 ~0.75 0.50

( )
0.018 ~0.030 0.020

10 Revision 1.0
September 2003