FPGA Based Fault Distance Detection and
Positioning of Underground Energy Cable by Using
GSM/GPRS
Güner Tatar Osman Kılıç
Electrical and Electronic Engineering Electrical and Electronics Engineering
Fatih Sultan Mehmet Vakıf University Marmara University
Istanbul, Turkey Istanbul, Turkey
gtatar@fsm.edu.tr osman.kilic@marmara.edu.tr
Abstract—This paper proposes the usage of Field Pro-
grammable Gate Arrays (FPGA) for fault distance detection and
positioning of an underground cable by using GSM/GPRS. This
task was produced using Very High Speed Integrated Circuit
Hardware Description Languages (VHDL) and implemented
on Basys-3 FPGA board by using Xilinx Vivado Design Suite
18.1. Deciding the separation of underground power line fault
from the base station was done by using FPGA and Global
System for Mobile Communication/General Packet Radio Service
(GSM/GPRS) module. The main fault types are three phase
symmetrical short circuit fault, two phase-to-earth short-circuit
fault, phase-to-phase short circuit fault, phase-to-earth short-
circuit fault and open-circuit fault. In this study, only two types
of faults were taken into consideration. The first of them is phase-
to-earth short-circuit fault, while the other one is open circuit
fault with broken in transmission line and both simulated by
using LTspice.
Index Terms—FPGA, VHDL, Basys-3 board, SIM900
GPRS/GSM Module, Smart phone, LTspice, FSM (Finite State
Machine).
I. I NTRODUCTION
Previously, power transmission lines were above ground,
but recently they were changed to underground [1]. Although
the underground lines are not affected by any natural con-
ditions such as storm, rain, snow, it is difficult to detect
and eliminate the faults in the lines [1]. So, growing and
developing technology makes this problem easier. Because
the world is moved toward becoming digitalized so the task
is expected to distinguish the area of the fault carefully.
Some electronic devices and embedded systems are used for
finding and localizing the fault of underground cables. An
embedded system is regularly a plan that utilizes the intensity
of a little micro-controller, similar to the Re-configurable
Computing FPGA, Microchip PIC micro-controller (MCU) or
dsPIC computerized flag controller (DSC) [2] [3]. A micro-
controller is formed by adding several peripheral interfaces
to the microprocessor. An FPGA is a semiconductor gadget
that is based around a framework of configurable rationale
978-1-7281-3729-2/19/$31.00 ©2019 IEEE
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Salih Bayar
Electrical and Electronics Engineering
Marmara University
Istanbul, Turkey
salih.bayar@marmara.edu.tr
squares (CLBs) associated by means of programmable in-
terconnects. FPGAs can be reconstructed to the desired ap-
plication or usefulness necessities subsequent to assembling.
This component perceives FPGAs from Application-Specific
Integrated Circuits (ASICs), which are exceptionally created
for express arrangement assignments. This single device would
then have the option to be embedded into other electronic and
mechanical contraptions for simplicity automated control [2]
[3] [6].
In this study, Basys-3 FPGA board was used for controller
and VHDL was preferred as software language and SIM900
GSM/GPRS module was used for transferring data. Universal
Asynchronous Receiver Transmitter (UART) serial commu-
nication is used as the communication protocol which uses
GSM/GPRS module for transferring the location information
of the fault to the user. Communication by the UART protocol
is used between different baud rates changing from 1200
to 115200 bauds depends on the oscillator frequency. And,
this structure consists of many blocks which are main part
as a control unit, transmitter part and receiver part [3]. A
network structure of underground energy transmission lines is
established at the specified intervals. This structure consists of
ohm’s law and voltage dividers [4] [5]. In Figure1 shows that
the block diagram with communication parts of the project.
II. W ORKING PRINCIPLE
In the second era, remote correspondence arranges, for
example, GSM is a remote area innovation, handset-based area
innovation, and system based area innovation [7]. In handset-
based area innovation, a portable terminal computes its situ-
ation with the associate help of GPS system. Handset-based
area innovation can decide a portable terminal position when
it gets flagging information from no less than four satellites
in GPS or three Base Transceiver Stations(BTS) [7]. Handset-
based area innovations may require extra changes for a remote
correspondence organize. Also, the protection issue of portable
terminals should be considered. Obviously, a few anonymiza-
tion methods are utilized [8]. Also, information concealment
strategies can help anticipate information mining calculations
 1
User
Z= 1 (4)
R+JwL + JwC
Phone
In this study, 1k ohm resistors structure was utilized to
represent transmission lines [4] [12]. Figure 2 indicates that
the representation of 3 phases transmission line network. The
PC for distance between each resistance was taken in meters and the
Basys-3 FPGA GSM Module more voltage divider resistance is used in the structure, the
Programming
Development Board with SIM Card
and Power more precise a structure is formed. In this study, the sensitivity
was made at 500 meters intervals and for a total length of "n"
km. If there is a long transmission line distance, the number
of voltage divider resistor values can be increased and the
ADC
required long distance can be obtained according to the ADC
resolution used. The difference of this structure from the [4],
Fault data
Fault
from
Sensing
structure

Fig. 1. Overall block diagram of the project

from remaking private data from mysterious database tests as

in [8]. System based area innovation is helped by additional
equipment or programming by estimating flagging information
between a versatile terminal and encompassing base stations
to ascertain the situation by the system [7].
Fig. 2. 3 phase transmission line network with representative resistors [4]
In Figure 1 shows that the basic GSM/GPRS commu-
nication system with Basys-3 FPGA board and peripheral it is aimed to realize the "n" km length of the transmission
interfaces. Basys-3 FPGA board is an embedded system that it lines considering certain distances. User can define length of
has internal environmental interfaces. An inserted framework the line by using "Generic value" given in the code block. Of
is normally a structure that utilizes the intensity of a little course, FPGA capabilities and capacity were also taken into
micro controller, similar to the PIC micro controller (MCU) account. The fault at the desired distance is calculated with
or Re-configurable Computing (FPGA). FPGA is the main the help of the following code block. Figure 3 has two inputs
part of this project. Overall software used in the project was
programmed to the FPGA. Compare to other micro-controllers
FPGA has so many advantages like parallel processing, re-
configurable capabilities, easy set up to use, hardware de- "m"
scription languages feature and so on. In order to represent Pn
Sum = k=0 x[k] Point Volt.
the 3-phase underground energy transmission line, a physical
structure consisting of voltage divider resistors was formed [4]. "n"
Because resistance is an important parameter because it causes
power loss in transmission lines. Although this resistance value
differs in direct current (DC) and alternating current (AC), it Fig. 3. A transmission line with a representative m array is nth voltage drop
was taken in this study according to AC. In AC current, in line
with the frequency and the characteristics of the cable, even the variables "m" and "n" under the Generic. The "m" represents
inductance and capacitance effect is formed in the alternating array length as a transmission line and "n" represents the fault
current transmission lines. In the study, the parameters of the points. For example, in case of fault R9 resistance, "n" is
energy transmission line were used and certain values were considered to be an index of resistance R9. The variables
calculated for a certain length. Some useful formulas in (1),(2), allow for the calculation of the length of the underground
(3) and (4) were given follows that used for lines’ resistance cables and the current flowing through the voltage divider
value. resistance depending on these lengths. Since the transmission
l line is divided into specific meter ranges, we can think of it as
RDC = ρ (1)
A an array. The variable "n" is used to calculate the number of
1 indices of this series and the voltage falling on the resistance
XC = (2) at the fault point. In this study, the value of "m" is 12 and "n"
2πf C
is 8. These values can be changed in the Generic code block
XL = 2πf L (3) for the desired length and distance.

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 Another important part of the project is the SIM900
GSM/GPRS module. 4 Frequency GPRS/GSM Module is an Start
ultra-minimal and solid remote module. It is a breakout board
and least arrangement of SIM900 Quad-band GSM/GPRS
module [9]. Figure 4 indicates that the SIM900 GSM/GPRS
module that was used in this project. Communication between
Character Get a Character
Received ? Set Rx reception flag
Yes

No

Loop
Transmitter Get a Character
Ready ? Set Tx done flag
Yes

No

Sleep
(context
switch)

Fig. 4. SIM900 GSM/GPRS Module [9]

the receiver and the transmitter is provided to determine the
coordinate location of the region of the fault location and send
it to the user.
A. Universal Asynchronous Receiver Transmitter (UART)
UART gets and transmits information in sequential to
parallel and parallel to sequential with various Baud Rates
every second, with begin stop and equality bits. FPGA board
comprises of constrained I/O’s N-Bit tasks can be performed
through RS-232 sequential correspondence. In the UART cor-
respondence, the information transmission speed is estimated
by Baud Rate. It incorporates Start bit, Data byte, a Parity
bit and Stop bit. Transmitter and collector should be kept up
in the baud rate. Figure 5 shows the block diagram of the
project contained a UART communication interface. And the
flowchart was given in fig 9. The flowchart shows how the
program steps are processed and the communication states
between the transmitter and receiver.
Fig. 6. Algorithm Flowchart of the UART [11]
B. FSM of UART Receiver
What should be considered in any asynchronous communi-
cation is when the data is sampled. If the data is not sampled
in time, the wrong data can be received or sent. The receiver
and transmitter stage must be at the same baud rates for a
correct communication. Figure 7 shows the FSM of UART
receiver part. The receiver part has 5 states. 16 clock cycles
or 16 prescaler pulses are required for each state change. In the
case RxIdle, the state machine is waiting for the start bit to
be detected. In case RxStart, the state machine waits for 16
clock cycles to pass next state. RxData, this state consists
of an 8-bit internal register. When all 8 bits are received,
the state machine will proceed to the next step.RxP arity,
it chooses whether the got information is the location byte or
the information byte. and the last state is RxStop, in this state
the FSM checks the all data received or transmitted and then
it stops the FSM operation [10].

C. FSM of UART Transmitter

When Tx mode is activated, UART will switch to transmis-
sion mode. The controller will send the destination address
and determine the data and other transmission settings [10].
The data and address to be sent are converted to serial bits.
Like the receiver, the UART transmission consists of 5 states
and 16 clock cycles are also required for each state transition.
For a known UART communication, the baud rate and clock
frequency are determined by the equation 5 of the prescaler
division rate.
Fig. 5. UART Communication Interface
SerialClockF requency
DivideRatio = (5)
16 ∗ BaudRate

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 line. The transmission line mentioned in the project is much
longer than the transmission line in figure 9 and 10 has a
a

en
er characteristic impedance at each km. Reflection wave and

th
1
f St 6 cloc

1
RX-Idle

=
voltage standing wave ratio (VSWR) were shown in (6), (7)

it
art kc

tb
bit ycl

ar
=1 e

St
respectively. VSWR indicates that mismatch between Z0 and
ZL .

RX_Stop RX_Start V0− VL − IL Z0

A er 16 clock cycle Γ= + = (6)
f Start bit =1 then V0 VL + ILZ0

cles
16 clo

ck cy
|V |max 1 + |Γ|
S= = (7)

16 clo
ck cy

|V |min 1 − |Γ|
cle

IV. -

8
it <
R_Parity RX_Data

ab
a er 16 clock cycle

dat
Rx data bit =8 Rx

Fig. 7. Finite State Machine of Receiver [10]

Tx_
=1

TX-Idle de
y

tec
pt

t
m

=1
e
f_
Tx

Fig. 9. LTspice model for open circuit fault detection

TX_Stop TX_Start
After 16 clock cycle
cles

Txf_empty=1
16 clo

ck cy
16 clo
ck cy
cle

Tx_Parity TX_Data
<8

after 16 clock cycle

d ata

Tx data bit =8
Rx

Fig. 8. Finite State Machine of Transmitter [10]

III. LT SPICE MODEL OF THE PROJECT

The simulated results of a phase model of the transmis- Fig. 10. LTspice model for short circuit fault detection
sion line in the LTspice environment were given below. The
impedance is connected to the end of the transmission line
for the detection of short circuit and open circuit fault. A
short-circuit fault is connected to the transmission line with
an impedance close to 0, and for the open-circuit fault, a
resistance corresponding to the characteristic impedance of
the air (377 ohms) is connected. The law of reflection was
used to find the fault. As is known, transmission lines are
composed of reflection and standing wave. If there is a short
circuit in the transmission line, the amplitude of the reflected
signal is low and if there is an open circuit, the amplitude
of the reflected signal will be large. With these methods
mentioned above, faults at certain distances can be determined.
Figure 9 and 10 indicate the LTspice model of a phase
transmission line, and their simulation results were given on
figure11 and 12. This model is used to show the reflection Fig. 11. LTspice simulation result of open-circuit fault detection
and standing wave formation occurring in the transmission

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 data at a rate of 16 times the baud rate [13]. For this reason, we
need to send 1/16 bits of the speed of the produced pulses. As
a result, the generated pulses are counted and one bit of data is
sent every 16 pulses. There are also code blocks for the project
and the UART protocol. The transmission and reception of the
data of the UART communication was given in the simulation
results section. We utilized studies given [13] and [14] in the
preparation of VHDL codes of UART communication.

reset
DataIn TxDone

Fig. 12. LTspice simulation result of short-circuit fault detection

sTick UART Tx Module
clk in Tx
TxStart
A. VHDL Source Code Blocks
Fig. 15. Entity of UART Transmitter FIFO

reset
WData full

WriteD FIFO ReadData

clk in empty
ReadD

Fig. 13. Entity of UART Transmitter FIFO Fig. 16. Usage of Basys-3 Board Capacity of UART Transmitter Part

clk in
UARTBauGen tick cnt
reset

Fig. 17. Usage of Basys-3 Board Capacity of ADC Part

Fig. 14. Entity of Baud Rate Generator

The code blocks representing the important parts of the

software used in the project are given in figure 13, 14 and 15.
Figure 13 is used to store the data sent over serial line and
to prevent swelling of the registers. FIFO is used in all serial
communication protocols to prevent data loss. Since UART
communication is 8 bit data, 8 bit FIFO structure is used.
Figure 14 was used for Baud-Rate generator. Tick must be
produced at appropriate speeds for UART communication. In Fig. 18. UART Implementation of RTL Schematic Zoom In
UART communication, the signal is sampled at 16 times the
set baud rate [13]. Considering the crystal clock frequency 100
MHz of the basys-3 board used in the project, the baud-rate V. A PPLICATION AND S IMULATION R ESULTS
generator should be 27 according to 5. This means that our In this study, how to use GSM / GPRS module which is one
baud-rate generator will produce one pulse every 27 cycles. of the wireless communication units in FPGA environment and
Figure 15, the data from FIFO is adapted to the UART how it is written in VHDL language was shown with simu-
protocol according to the baud rate of the baud-rate generator. lation programs. Firstly, the effect of an energy transmission
As mentioned earlier, UART takes samples from the incoming line in LTspice program when it has short circuit and open

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Fig. 19. UART Transmitter Simulation Result
Fig. 20. UART Receiver Simulation Result
circuit failure, and then the behavior of UART communication
in data sending and receiving part are shown in Vivado 2018.1
environment. In the case of an open circuit (R = 377 ohms)
in the energy transmission line, the standing wave due to
reflection, and in the case of short circuit (R = 0.01ohms), no
reflection and no standing wave are shown in fig.11 and fig.12,
respectively. In Figure 2, when any of these two faults occur,
it is considered to make a position determination considering
the reflection and no reflection in the system. The simulation
results of the project were given in figures; 16, 17 18, 19 and
20.
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VI. C ONCLUSION AND F UTURE W ORKS

When the results are taken into consideration, FPGA is
used in this study, unlike the existing projects. The use
of FPGAs in such projects seems to be feasible since it
is easily reconfigurable. As it is known, FPGAs can be
programmed with VHDL or Verilog HDL from hardware
description languages since they are hardware based struc-
tures. Two important (short-circuit and open-circuit) failures
of the power transmission lines were considered. In future
studies, unlike these fault types, the detection of other faults
of the transmission lines (3-phase symmetrical short-circuit,
two-phase ground short-circuit, phase-phase short-circuit and
phase-earth short-circuit) will be performed by using different
algorithms and different structures.

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