Schem, MLB, Kepler, 2phase, D2: Schematic / PCB #'S

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2012-05-09
SCHEM,MLB,KEPLER,2PHASE,D2
苹果笔记本维修交流群群号：325742634
FSB, 5/9/2012
D (.csa) Date (.csa) Date (.csa) Date

D
Page Contents Sync Page Contents Sync Page Contents Sync
TABLE_TABLEOFCONTENTS_HEAD
1 01/13/2012 TABLE_TABLEOFCONTENTS_HEAD
54 03/05/2012 TABLE_TABLEOFCONTENTS_HEAD
102 01/13/2012
1 Table of Contents D2_KEPLER 46 High Side and CPU/AXG Current Sensing D2_SEAN 91 PCH Constraints 1 D2_KEPLER
2 01/13/2012 55 03/05/2012 103 01/13/2012
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
2 System Block Diagram D2_KEPLER 47 Thermal Sensors D2_SEAN 92 PCH Constraints 2 D2_KEPLER
3 01/13/2012 56 01/13/2012 105 01/13/2012
3 Power Block Diagram D2_KEPLER 48 Fan Connectors D2_KEPLER 93 Thunderbolt Constraints D2_KEPLER
TABLE_TABLEOFCONTENTS_ITEM
4 01/13/2012 TABLE_TABLEOFCONTENTS_ITEM
106 01/13/2012
4 Revision History D2_KEPLER 49 KEYBOARD/TRACKPAD (1 OF 2) D2_KEPLER 94 SMC Constraints D2_KEPLER
107 01/13/2012
5 BOM Configuration D2_KEPLER 50 KEYBOARD/TRACKPAD (2 OF 2) D2_KEPLER 95 GPU (Kepler) CONSTRAINTS D2_KEPLER
6 01/13/2012 59 01/13/2012 108 03/15/2012
6 BOM Variants D2_KEPLER 51 DIGITAL ACCELEROMETER & GYRO D2_KEPLER 96 Project Specific Constraints D2_CLEAN
109 01/13/2012
7 Functional / ICT Test D2_KEPLER 52 SPI ROM D2_KEPLER 97 PCB Rule Definitions D2_KEPLER
8 01/13/2012 62 03/16/2012 130 03/05/2012
8 Power Aliases D2_KEPLER 53 AUDIO: CODEC/REGULATOR D2_CARA 98 DEBUG SENSORS AND ADC D2_SEAN
9 01/13/2012 63 03/16/2012 132 01/13/2012
9 Signal Aliases D2_KEPLER 54 AUDIO: HEADPHONE FILTER D2_CARA 99 SMC12 SENSORS EXTENDED D2_KEPLER
10 01/13/2012 64 03/16/2012
10 CPU DMI/PEG/FDI/RSVD D2_KEPLER 55 AUDIO: IV SENSE D2_CARA

65 03/16/2012
11 CPU CLOCK/MISC/JTAG D2_KEPLER 56 AUDIO: IV SENSE FILTER D2_CARA
66 03/16/2012
12 CPU DDR3 INTERFACES D2_KEPLER 57 AUDIO: SPEAKER AMP D2_CARA
13 01/13/2012 67 03/16/2012
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
13 CPU POWER D2_KEPLER 58 AUDIO: JACK D2_CARA

68 03/16/2012
14 CPU POWER AND GND D2_KEPLER 59 AUDIO: JACK TRANSLATORS D2_CARA
16 03/05/2012 69 01/13/2012
15 CPU DECOUPLING-I D2_SEAN 60 DC-In & Battery Connectors D2_KEPLER

70 01/13/2012
16 CPU DECOUPLING-II D2_SEAN 61 PBus Supply & Battery Charger D2_KEPLER
C
17
18
19
PCH SATA/PCIe/CLK/LPC/SPI D2_KEPLER
01/13/2012
01/13/2012
62
71
72
System Agent Supply D2_KEPLER
01/13/2012
01/13/2012
C
18 PCH DMI/FDI/PM/Graphics D2_KEPLER 63 5V / 3.3V Power Supply D2_KEPLER
73 01/13/2012
19 PCH PCI/USB/TP/RSVD D2_KEPLER 64 1V5R1V35V DDR3 SUPPLY D2_KEPLER
21 01/13/2012 74 03/05/2012
20 PCH GPIO/MISC/NCTF D2_KEPLER 65 CPU IMVP7 & AXG VCore Regulator D2_SEAN
22 03/19/2012 75 03/05/2012
21 PCH POWER D2_CLEAN 66 CPU IMVP7 & AXG VCore Output D2_SEAN
23 01/13/2012 76 01/13/2012
22 PCH GROUNDS D2_KEPLER 67 CPU VCCIO (1V0R1V05 S0) POWER SUPPLY D2_KEPLER
24 03/19/2012 77 01/13/2012
23 PCH DECOUPLING D2_CLEAN 68 Misc Power Supplies D2_KEPLER

78 01/13/2012
24 CPU & PCH XDP D2_KEPLER 69 Power FETs D2_KEPLER
26 01/13/2012 79 01/13/2012
25 Chipset Support D2_KEPLER 70 Power Control 1/ENABLE D2_KEPLER

27 01/13/2012 80 01/13/2012
26 USB HUB & MUX D2_KEPLER 71 KEPLER PCI-E D2_KEPLER

28 01/13/2012 81 03/05/2012
27 CPU Memory S3 Support D2_KEPLER 72 KEPLER CORE/FB POWER D2_SEAN

29 01/13/2012 82 03/05/2012
28 DDR3 SDRAM Bank A (1 OF 2) D2_KEPLER 73 KEPLER FRAME BUFFER I/F D2_SEAN

30 01/13/2012 83 03/05/2012
29 DDR3 SDRAM Bank A (2 OF 2) D2_KEPLER 74 1V05 GPU / 1V35 FB POWER SUPPLY D2_SEAN
31 01/13/2012 84 03/05/2012
30 DDR3 SDRAM Bank B (1 OF 2) D2_KEPLER 75 GDDR5 Frame Buffer A D2_SEAN

32 01/13/2012 85 03/05/2012
31 DDR3 SDRAM Bank B (2 OF 2) D2_KEPLER 76 GDDR5 Frame Buffer B D2_SEAN

33 01/13/2012 86 03/05/2012
32 DDR3 Termination D2_KEPLER 77 KEPLER EDP/DP/GPIO D2_SEAN

34 01/13/2012 87 03/05/2012
33 DDR3/FRAMEBUF VREF MARGINING D2_KEPLER 78 KEPLER GPIOS,CLK & STRAPS D2_SEAN

35 01/13/2012 88 03/05/2012
34 79
B TABLE_TABLEOFCONTENTS_ITEM
35
36
X29/ALS/CAMERA CONNECTOR
Thunderbolt Host (1 of 2)
D2_KEPLER
D2_KEPLER
01/13/2012
80
89
KEPLER PEX PWR/GNDS
GFX IMVP VCore Regulator
D2_SEAN
D2_SEAN
03/05/2012 B
37 01/13/2012 90 01/13/2012
36 Thunderbolt Host (2 of 2) D2_KEPLER 81 eDP Display Connector D2_KEPLER

91 03/05/2012
37 Thunderbolt Power Support D2_KEPLER 82 eDP Mux D2_SEAN
44 01/13/2012 92 03/05/2012
38 RIO CONNECTOR D2_KEPLER 83 eDP Muxed Graphics Support D2_SEAN

45 01/13/2012 94 01/13/2012
39 SSD CONNECTOR D2_KEPLER 84 Thunderbolt Connector A D2_KEPLER

46 01/13/2012 96 01/13/2012
40 USB 3.0 CONNECTORS D2_KEPLER 85 Thunderbolt Connector B D2_KEPLER

97 01/13/2012
41 SMC D2_KEPLER 86 LCD Backlight Driver (LP8545) D2_KEPLER
50 01/13/2012 98 01/13/2012
42 SMC Support D2_KEPLER 87 PCH VCCIO (1.05V) POWER SUPPLY D2_KEPLER

99 01/13/2012
43 LPC+SPI Debug Connector D2_KEPLER 88 Power Sequencing EG/PCH S0 D2_KEPLER
100 01/13/2012
44 SMBus Connections D2_KEPLER 89 CPU Constraints D2_KEPLER
53 03/05/2012 101 01/13/2012
45 Voltage & Load Side Current Sensing D2_SEAN
90 Memory Constraints D2_KEPLER
A A
DRAWING TITLE
SCHEM,MLB,KEPLER,2PHASE,D2
DRAWING NUMBER SIZE
Schematic / PCB #’s Apple Inc. 051-9589 D
REVISION
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION R
4.18.0
051-9589 1 SCHEM,MLB,KEPLER_2PHASE,D2 SCH CRITICAL NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
820-3332 1 PCBF,MLB,KEPLER_2PHASE,D2 PCB CRITICAL PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
DRAWING I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 132
TITLE=MLB III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
ABBREV=ABBREV
LAST_MODIFIED=Wed May 9 13:50:52 2012 IV ALL RIGHTS RESERVED 1 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J2500,J2550
U8000 INTEL CPU 苹果笔记本维修交流群群号：325742634

GRAPHICS XDP CONN
2.X GHZ
PG 23
AMD WHISTLER IVY BRIDGE
J2900
PG 9
PG 73 J3100
2 DIMMS
DDR3-1067/1333MHZ
DIMM
D PG 26,28
J6950
D
DC/BATT POWER SUPPLY
PG 63
GPIO FDI DMI RTC
PG 19 PG 17 PG 17 PG 16 U4900
U6100
SPI
Boot ROM TEMP SENSOR
U2700 CLOCK
Misc PG 55
CK5G05 CLK
PG 44
PG 19
PG 24
BUFFER POWER SENSE
PG 44
PG 16
J5650,5660
SPI FAN CONN AND CONTROL

J4501
PG 51
5
SATA2.0/3(GB/S)
PG 16
ODD SATA
CONN
4
SATA2.0/3(GB/S)
PG 41
SATA INTEL J5100 Ser
B,0 BSB ADC Fan
LPC + SPI CONN
3
SATA2.0/3(GB/S) Prt
PANTHER-POINT SMC
J4500
PG 16 Port80,serial
LPC PG 46 PG 44
MOBILE U4900
2
SATA2.0/3(GB/S)
C HDD SATA
CONN PG 16
C
1
SATA3.0/6(GB/S)
PG 41
U1800
0 SATA3.0/6(GB/S)
U3600 J3402
PWR CAMERA
PG 31
CTRL
DP OUT
J4501
PG 17 USB IR
U9320 PG 41
RGB OUT
DP MUX HUB 2 J4610

EXTERNAL B
9 10 11 12 13
HDMI OUT PG 33
XP25-5G
PG 83
DVI OUT PG 33 EXTERNAL C
(RESERVATION) PG 33
LVDS OUT
(UP TO 14 DEVICES)
8
J9400 TMDS OUT
7
U3700 J5713
PG 18
USB
PG 18 TRACKPAD/KEYBOARD
6
PG 53
MINI DP PORT
5
4
PG 84 USB J3401
PCI BLUETOOTH
3
PG 31
HUB 1
2
PG 18
1
J4600
0
EXTERNAL A
U9370 PG 34 PG 34
B DDC MUX
JTAG
SMB
B
PG 16 SMBUS
PG 16
PG 83
CONNECTION
PCI-E HDA PG 47
PEG
(UP TO 16 LINES)
PG 16
PG 16 PG 16
DIMM
LCD PANEL PG 26,28
U9600
U6201
AUDIO
GMUX
CODEC
PG 86 PG 56
U4100
U6610,6620,6630
U3900
GB
A J3401
FW643
E-NET
LINE TIN
FILTER
HEADPHONE
FILTER
SPEATKER
AMP SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
BCM57765 PAGE TITLE
PG 38
PG 36
PG 57 PG 58 PG 59
System Block Diagram
AirPort DRAWING NUMBER SIZE
PG 31 J4310 Apple Inc. 051-9589 D

J4000 J3500
REVISION
FIREWIRE E-NET SDCARD READER J6700,J6750
R
4.18.0
CONN AUDIO NOTICE OF PROPRIETARY PROPERTY: BRANCH
CONN CONN
CONN SPEATKER THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
PG 40 PG 37 PG 37 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PG 60 PG 63
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
2 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 2 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D6990
D2 POWER SYSTEM ARCHITECTURE SMC PWRGD
NCP303LSN SMC_RESET_L
PP18V5_DCIN_CONN
R6990 U5000
(PAGE 45)
ENABLE
PPBUS_G3H SMC AVREF SUPPLY
3.425V G3HOT
PM6640 PP3V42_G3H PP3V3_S5_AVREF_SMC
SMC_PBUS_VSENSE VIN VOUT
U6990
REF3333 PP3V3_S5_SMC
J6900 F7040 V Q5315

(PAGE 62) (PAGE 45)
SMC_TPAD_RST_L
D F6905
6A FUSE R7020
PPBUS_G3H
SMC_ONOFF_L D
U5001
AC
ADAPTER
DCIN(16.5V)
A VIN
U7000
PPVBAT_G3H
8A FUSE
VIN
V SMC_GPU_VSENSE R7640
IN
SMC_DCIN_ISENSE
ISL6259HRTZ
VOUT PP5V_S3_GFXIMVP6_VDD VDD VOUT A PPVCORE_GPU PP5V_S0_CPUVTTS0
VIN
1.05V
VOUT
A PPCPUVTT_S0
GPU VCORE SMC_CPU_FSB_ISENSE

U5410 ISL95870 TPS22924
PBUS SUPPLY/ ISL6263C U7600 U4202 PP1V0_FW_FWPHY
SMC_GPU_ISENSE
SMC_RESET_L
BATTERY CHARGER
R7050 A U8900
CPUVTTS0_EN
EN
PGOOD
CPUVTTS0_PGOOD (PAGE 39)
EN
VR_ON PGOOD
SMC_BATT_ISENSE GPUVCORE_EN GPUVCORE_PGOOD (PAGE 70)
FW_PWR_EN
(PAGE 64) (PAGE 82)
SMC_CPU_VSENSE
J6950
Q7055
R5388/U5388
V
PPVBATT_G3H_CONN PPVBAT_G3H_CHGR_R SMC_CPU_HI_ISENSE
A
CPU VCORE
VOUT
A PPVCORE_S0_CPU
PANTHER_POINT PM_PWRBTN_L
(9 TO 12.6V)
VIN PWRBTN#
ISL95831
3S2P
SMC_CPU_ISENSE
SYS_RERST#
CPUIMVP7_VR_ON U7400
CHGR_BGATE VR_ON RSMRST#
PGOOD CPUIMVP7_AXG_PGOOD
(PAGE 67) ACPRESENT
www.qdzbwx.com PM_PCH_PWRGD
PS_PWRGD PLTRST#
PLT_RERST_L
U1800 CPU_PWRGD
C
PROCPWRGD
C GMUX
PB16B
EG_RAIL1_EN P1V1GPU_EN
U5440
DRAMPWROK
PM_MEM_PWRGD
EG_RAIL2_EN P3V3GPU_EN U2850 (PAGE 16~21)

PB17A PP5V_S3_DDRREG SMC_CPU_DDR_VSENSE
U9600
PB17B
EG_RAIL3_EN GPUVCORE_EN
R7350
XP25-5 PB18A
EG_RAIL4_EN
VIN VLDOIN
SMC_DDR_ISENSE
V
PM_ALL_GPU_PGOOD DDRREG_EN 1.5V
(PAGE 86)
PL32A
P1V0GPU_EN
EN1 VIN
VOUT1
PP1V0_S0GPU_REG
DDRVTT_EN
S5 VOUT1
PPDDR_S3_REG
A PP1V5_S3
S3 0.75V PPVTT_S0_DDR_LDO
1.003V(L/H) R5413 VOUT2 SM_DRAMPWROK
CPU
SMC
P1V5FB_EN
EN2
1.503V(R/H)
VOUT2
A PP1V5_GPU_REG
SMC_GPU_1V8_ISENSE
TPS51116
U7300 PGOOD
DDRREG_PGOOD 4.5V PP4V5_AUDIO_ANALOG U1000 VCCCPUPWRGD
VIN MAX8840
(PAGE 66) VOUT
EN U6200
U4900 ISL6236 POK1
P1V0GPU_PGOOD
RESET*
PP3V3_S0 (PAGE 9~14)
RC P3V3S5_EN U9500
P1V5FB_PGOOD PP1V5_S3
P60 POK2 Q7860
DELAY (PAGE 85) Q7801
SMC_PM_G2_EN P1V5CPU_EN PP5V_S0
(PAGE 44) VIN PP1V5_S3RS0
ON G
SLG5AP020
U7801
VIN VREG5 P5VS0_EN
P5VS3_EN PP5V_S3 P1V5S0FET_GATE
VOUT1
PANTHER-POINT EN1
5V
PM_ALL_GPU_PGOOD
(L/H)
MOBILE PP3V3_S5 PP3V3_S5
PM_SLP_S5_L
P3V3S5_EN VOUT2 U7980
SLP_S5#(E4) EN2 3.3V PP1V8_S0 SMC
Q9806 (R/H) ALL_SYS_PWRGD
Q7880
B RC P5VS3_EN TPS51125
U7201
Q7870
PP3V3_S0GPU
P1V8FB_EN
ON
VIN
G
PP1V8_GPUIFPX PWRGD(P12)
(P64)
SMC_ADAPTER_EN B
DELAY SLG5AP020
(PAGE 65) RSMRST_PWRGD
U7880 RSMRST_IN(P13) PM_RSMRST_L
RSMRST_OUT(P15)
PGOOD
RC DDRREG_EN BKLT_PLT_RST_L P1V8GPUIFPXFET_GATE SMC_ONOFF_L 99ms DLY
PWR_BUTTON(P90) CPUIMVP_VR_ON
DELAY
&& VIN P3V3GPU_EN IMVP_VR_ON(P16)
U1800 LCD_BKLT_NO LP8550

P5V3V3_PGOOD Q7810 PM_SYSRST_L
SYSRST(PA2)
P3V3S3_EN BKLT_EN U9701 PP3V3_S3
PPVOUT_S0_LCDBKLT Q7922 PP3V3_ENET
ENA VOUT PP3V3_S0_PWRCTL
PM_PWRBTN_L
P17(BTN_OUT)
PM_SLP_S4_L (PAGE 87) P1V8S0_PGOOD
SLP_S4#(H7) PM_SLP_S5_L
P3V3S3_EN SLP_S5_L(P95)
PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN P5V3V3_PGOOD SMC_RESET_L
Q4260 Q7830 PM_SLP_S4_L RES*
SLP_S4_L(P94)
PM_SLP_S3_L TPS22924
PFWBOOST S0PGOOD_PWROK PM_SLP_S3_L
SLP_S3#(P12) PP3V3_S0_FET U4201 PP3V3_FW_FWPHY SLP_S3_L(P93)
(PAGE 39) H8S2117
(PAGE 16~21) U4900

EN
PP3V3_S0 (PAGE 45)
P3V3S0_EN
FW_PWR_EN
SMC_ADAPTER_EN&&PM_SLP_S3_L
VCC
PP3V3_S0
R7978 V2MON
U7971
PP1V5_S0 ISL88042IRTJJZ
VIN PP1V8_S0
VOUT V3MON RST*
PM_SLP_S3_L_R P1V8_S0_EN
ISL8014A
EN
U7720 P1V8S0_PGOOD PP1V05_S0
PGOOD V4MON (PAGE
(PAGE 70) Q7850 72)
A RC
DELAY
P1V8S0_EN
P5VS0_EN
PP1V2_S0 TRST = 200mS SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
RC P1V2S0_EN Power Block Diagram
DELAY VIN P1V2S0_EN DRAWING NUMBER SIZE
P3V3S0_EN P1V2ENET_EN ISL8014A PP1V2_ENET
EN
U7760
VOUT
Apple Inc. 051-9589 D
RC CPUVTTS0_EN P1V2ENET_PGOOD REVISION
(PAGE 70) PGOOD
DELAY
PBUSVSENS_EN
R
4.18.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
RC P1V5CPU_EN THE INFORMATION CONTAINED HEREIN IS THE
DELAY THE POSESSOR AGREES TO THE FOLLOWING: PAGE
3 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
B B
A SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
Revision History
DRAWING NUMBER SIZE

REVISION
R
4.18.0
4 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOM Variants (continued on CSA 6) TABLE_BOMGROUP_HEAD
Bar Code Labels / EEEE #’s (continued on CSA 6) Alternate Parts TABLE_ALT_HEAD
BOM NUMBER BOM NAME BOM OPTIONS PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_BOMGROUP_ITEM
PART NUMBER
085-3726 D2,MLB,KEPLER,DEV D2_DEVEL:ENG 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY3V] CRITICAL EEEE:DY3V TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
128S0257 128S0264 ALL Kemet alt to Sanyo
085-4776 D2,MLB,KEPLER,FSB DEV D2_DEVEL:FSB 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY3W] CRITICAL EEEE:DY3W TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
353S3527 353S3528 ALL Pericom eDP MUX
607-9546 D2,MLB,KEPLER_2PHASE,COMMON D2_COMMON,POSCAP_MYLAR_PAIR 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY3Y] CRITICAL EEEE:DY3Y TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
353S3526 353S3528 ALL TI eDP MUX
685-0016 PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2 PBUS_CAP:KEMET 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY40] CRITICAL EEEE:DY40 TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
376S0855 376S0613 ALL Diodes alt to Toshiba
685-0017 PBUS PAIR,SANYO POSCAP,SHORT MYLAR,D2 PBUS_CAP:SANYO 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY43] CRITICAL EEEE:DY43 TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
376S0855 376S0613 VREFDQ:M1_M3 ALL Diodes alt to Toshiba
639-3378 PCBA,2.3G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY3V BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3V,DEVEL_BOM,RAM_2G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY44] CRITICAL EEEE:DY44 TABLE_ALT_ITEM
D 639-3379 PCBA,2.3G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY3W BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY3W,DEVEL_BOM,RAM_2G_HYNIX_1600

TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY45] CRITICAL EEEE:DY45
376S1076
376S0903
376S0634
376S0796
ALL
ALL
Diodes alt to On Semi
Fairchild alt to Siliconix

TABLE_ALT_ITEM
D
639-3380 PCBA,2.3G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY3Y BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3Y,DEVEL_BOM,RAM_2G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY4C] CRITICAL EEEE:DY4C TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
376S0977 376S0859 ALL Diodes alt to Toshiba
639-3381 PCBA,2.3G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY40 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY40,DEVEL_BOM,RAM_2G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DRF1] CRITICAL EEEE:DRF1 TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
376S1053 376S0604 ALL Diodes alt to Fairchild
639-3384 PCBA,2.3G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY43 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY43,DEVEL_BOM,RAM_4G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DRF4] CRITICAL EEEE:DRF4 TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
128S0311 128S0329 ALL NEC alt to Sanyo
639-3385 PCBA,2.3G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY44 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY44,DEVEL_BOM,RAM_4G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DRDN] CRITICAL EEEE:DRDN TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
138S0739 138S0706 ALL Samsung alt to Murata
639-3386 PCBA,2.3G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY45 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY45,DEVEL_BOM,RAM_4G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DRDW] CRITICAL EEEE:DRDW TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
197S0434 197S0343 ALL Epson Alt to TXC
639-3387 PCBA,2.3G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY4C BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY4C,DEVEL_BOM,RAM_4G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DT9H] CRITICAL EEEE:DT9H TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
197S0435 197S0343 ALL NDK Alt to TXC
639-2821 PCBA,2.6G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DRF1 BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF1,DEVEL_BOM,RAM_2G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DT9D] CRITICAL EEEE:DT9D TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
197S0432 197S0431 ALL NDK Alt to Epson
639-2825 PCBA,2.6G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DRF4 BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRF4,DEVEL_BOM,RAM_2G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DT9F] CRITICAL EEEE:DT9F TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
197S0452 197S0181 ALL Epson Alt to TXC
639-2817 PCBA,2.6G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DRDN BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDN,DEVEL_BOM,RAM_2G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DT9G] CRITICAL EEEE:DT9G TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
197S0453 197S0181 ALL NDK Alt to TXC
639-2815 PCBA,2.6G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DRDW BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDW,DEVEL_BOM,RAM_2G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0HN] CRITICAL EEEE:F0HN TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
685-0017 685-0016 ALL Sanyo POSCAP/Mylar alt to Kemet
639-2979 PCBA,2.6G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DT9H BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9H,DEVEL_BOM,RAM_4G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0HR] CRITICAL EEEE:F0HR TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
376S0975 376S1081 ALL Toshiba alt to diodes
639-2980 PCBA,2.6G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DT9D BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9D,DEVEL_BOM,RAM_4G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DYW4] CRITICAL EEEE:DYW4 TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
371S0709 371S0652 ALL NXP alt to infineon
639-2981 PCBA,2.6G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DT9F BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9F,DEVEL_BOM,RAM_4G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0HV] CRITICAL EEEE:F0HV TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
371S0713 371S0558 ALL DDS alt to ST
639-2982 PCBA,2.6G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DT9G BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9G,DEVEL_BOM,RAM_4G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0HM] CRITICAL EEEE:F0HM TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
377S0126 377S0066 ALL New Semtech package
639-3618 PCBA,2.7G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HN BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HN,DEVEL_BOM,RAM_2G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DYW5] CRITICAL EEEE:DYW5 TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
377S0147 377S0066 ALL On Semi alt to Semtech
639-3619 PCBA,2.7G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,F0HR BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HR,DEVEL_BOM,RAM_2G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0HY] CRITICAL EEEE:F0HY TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
152S0461 152S1645 ALL Cyntec alt to Vishay
639-3561 PCBA,2.7G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DYW4 BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:DYW4,DEVEL_BOM,RAM_2G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0HT] CRITICAL EEEE:F0HT

C
TABLE_ALT_ITEM
C 639-3620 PCBA,2.7G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HV BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HV,DEVEL_BOM,RAM_2G_SAMSUNG_1600

TABLE_BOMGROUP_ITEM
Programmables
376S1080
155S0667
376S0820
155S0583
ALL
ALL
Diodes alt to On Semi
Panasonic alt to TDK

TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
639-3627 PCBA,2.7G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HM BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HM,DEVEL_BOM,RAM_4G_HYNIX_1600 TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
341S3584 1 IC,TRKPD/KYBD CNTRLR,DVB,D2 U5701 CRITICAL TPAD_PSOC:PROG 107S0232 107S0129 ALL Cyntec alt to TFT
639-3562 PCBA,2.7G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DYW5 BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:DYW5,DEVEL_BOM,RAM_4G_HYNIX_1600 TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
337S2983 1 IC,TP PSOC,QFN,BLANK U5701 CRITICAL TPAD_PSOC:BLANK 197S0466 197S0464 ALL Epson alt to NDK
639-3628 PCBA,2.7G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,F0HY BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HY,DEVEL_BOM,RAM_4G_SAMSUNG_1600 TABLE_ALT_ITEM
TABLE_BOMGROUP_ITEM
341S3597 1 IC,EEPROM,CACTUS RIDGE (8.1) FSB,D2 U3690 CRITICAL TBTROM:PROG 341S3564 341S3565 ALL Avnet eDP MUX alt to Renesas
639-3629 PCBA,2.7G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HT BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HT,DEVEL_BOM,RAM_4G_SAMSUNG_1600

335S0865 1 EEPROM,256KBIT,SPI,5MHZ,1.8V,2X3QFN U3690 CRITICAL TBTROM:BLANK
BOM Groups TABLE_BOMGROUP_HEAD

335S0852 1 IC,GPU ROM,D2,BLANK U8701 CRITICAL GPUROM:BLANK
BOM GROUP BOM OPTIONS 341S3565 1 IC,EDP MUX-95C, (RENESAS) V3.2.8,DVB,D2 U9100 CRITICAL DPMUXMCU:PROG
TABLE_BOMGROUP_ITEM
D2_COMMON ALTERNATE,COMMON,D2_COMMON1,D2_COMMON2,D2_PROGPARTS,D2_PVB 337S4313 1 IC,MCU,H8S/2113,9X9MM,TLP-145V U9100 CRITICAL DPMUXMCU:BLANK

TABLE_BOMGROUP_ITEM
D2_COMMON1 CPUMEM_S0,SMC_DEBUG_YES,DPMUX:HOCO,TBTRTR:PRQ,TBTBST:Y,TBTHV:P15V,HUB_2NONREM,USBHUB2512B,SPEAKERID,SMC_PACKAGE:PROD,SKIP_5V3V3:AUDIBLE,CHGR_5V:LDO,P1V5S0:LDO
TABLE_BOMGROUP_ITEM
DRAM VREF Configs
D2_COMMON2 EDP:YES,MIKEY,PPCPUVCCIO:IVB,PPDDR:1V35,LPCPLUS_CONN:YES,LPCPLUS_R:YES,KBD_BL:SANDWICH,CAPS:INT,BTPWR:S4,XDP,XDP_CPU:BPM,GPU:2P,TPAD_5V:LDO_S5
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
BOM GROUP BOM OPTIONS
D2_PVB VREF:PROD,D_BKL:PROD,SENSOR_NONPROD:N TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
VREF:PROD VREFDQ:M1_M3,VREFCA:LDO
D2_PROGPARTS SMC_PROG:FSB,BOOTROM_PROG:FSB,DPMUXMCU:PROG,TPAD_PSOC:PROG,TBTROM:PROG TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
VREF:ENG_M3 VREFDQ:M1_M3,VREFCA:LDO_DAC
D2_DEVEL:ENG ALTERNATE,IVB_PPT_XDP,S0PGOOD_ISL,DPMUX_DEBUG,DDRVREF_DAC,VREF:ENG_M3,SENSOR_NONPROD:Y,D_BKL:DEV
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
VREF:ENG_LDO VREFDQ:M1_DAC,VREFCA:LDO_DAC
D2_DEVEL:FSB ALTERNATE,IVB_PPT_XDP
IVB_PPT_XDP XDP_CONN,XDP_PCH
TABLE_BOMGROUP_ITEM
DRAM SPD Straps TABLE_BOMGROUP_HEAD

Module Parts RAM_4G_HYNIX_1600_S RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L
TABLE_BOMGROUP_ITEM
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION

B B
TABLE_BOMGROUP_ITEM
RAM_1G_SAMSUNG_1600 RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H
337S4266 1 U1000 CRITICAL
TABLE_BOMGROUP_ITEM
IVB,S R0MP,PRQ,E1,2.3,45W,4+2,1.2,6M,BGA CPU_IVY:2_3GHZ

RAM_4G_SAMSUNG_1600_S RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L
337S4267 1 IVB,S R0MM,PRQ,E1,2.6,45W,4+2,1.25,6M,BGA U1000 CRITICAL CPU_IVY:2_6GHZ
TABLE_BOMGROUP_ITEM
RAM_1G_HYNIX_1600 RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H
TABLE_BOMGROUP_ITEM
IVB,S R0MK,PRQ,E1,2.7,45W,4+2,1.25,8M,BGA CPU_IVY:2_7GHZ

RAM_4G_ELPIDA_1600_S RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L
TABLE_BOMGROUP_ITEM
PANTHER POINT,C1,SLJ8C,PRQ,BD82HM77
RAM_2G_SAMSUNG_1600 2G_SAMSUNG_1600,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H
TABLE_BOMGROUP_ITEM
IC,GPU,NV GK107-GTX-PS-A2
RAM_2G_SAMSUNG_1333 RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L
TABLE_BOMGROUP_ITEM
IC,TBT,CR-4C,B1,PRQ,CIO,228 12X12 FC-CSP TBTRTR:PRQ

RAM_2G_HYNIX_1600 2G_HYNIX_1600,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
333S0622 32 IC,SDRAM,DDR3-1600,256MX8,78FBGA,HYNIX,C-DIE,38NM U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270 CRITICAL 2G_HYNIX_1600
TABLE_BOMGROUP_ITEM
RAM_4G_SAMSUNG_1600 4G_SAMSUNG_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L
333S0623 32 CRITICAL
TABLE_BOMGROUP_ITEM
IC,SDRAM,DDR3-1600,256MX8,78FBGA,SAMSUNG U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270 2G_SAMSUNG_1600

RAM_4G_HYNIX_1600 4G_HYNIX_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H
333S0628 32 IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270 CRITICAL 2G_ELPIDA_1600
TABLE_BOMGROUP_ITEM
RAM_2G_ELPIDA_1600_S RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L
333S0625 32 CRITICAL
TABLE_BOMGROUP_ITEM
IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270 4G_HYNIX_1600

RAM_2G_ELPIDA_1600 2G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H
333S0624 32 IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270 CRITICAL 4G_SAMSUNG_1600
TABLE_BOMGROUP_ITEM
RAM_4G_ELPIDA_1600 4G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L
333S0629 32 IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3000,U3010,U3020,U3030,U3040,U3050,U3060,U3070,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170,U3200,U3210,U3220,U3230,U3240,U3250,U3260,U3270 CRITICAL 4G_ELPIDA_1600
TABLE_BOMGROUP_ITEM
RAM_2G_SAMSUNG_1600_S RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H
333S0630 4 CRITICAL
TABLE_BOMGROUP_ITEM
IC,SDRAM,GDDR5,64MX32,A-DIE,HYNIX U8400,U8450,U8500,U8550 FB_2G_HYNIX_A_DIE

RAM_2G_HYNIX_1600_S RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L
333S0631 4 IC,SDRAM,GDDR5,64MX32,D-DIE,SAMSUNG U8400,U8450,U8500,U8550 CRITICAL FB_2G_SAMSUNG
128S0264 30 CAP,TANT,POLY,68UF,20%,16V,50MOHM,D2E C8921,C8922,C8920,C8926,C7554,C7560,C7561,C7513,C7514,C7523,C7524,C7533,C7534,C7570,C7571,C7572,C7040,C7240,C7242,C7280,C7282,C7330,C7331,C7575,C7620,C7621,C8307,C8356,C9820,C9821 CRITICAL PBUS_CAP:SANYO

DEVELOPMENT/BASE BOM
128S0257 30 CAP,TANT,POLY,68UF,20%,16V,50MOHM,D,LF C8921,C8922,C8920,C8926,C7554,C7560,C7561,C7513,C7514,C7523,C7524,C7533,C7534,C7570,C7571,C7572,C7040,C7240,C7242,C7280,C7282,C7330,C7331,C7575,C7620,C7621,C8307,C8356,C9820,C9821 CRITICAL PBUS_CAP:KEMET
085-3726 1 D2 MLB KEPLER DEVEL BOM DEVEL CRITICAL DEVEL_BOM
725-1614 1 INSULATOR,SHORT,REAR,MLB,D2 REAR_INSULATOR CRITICAL PBUS_CAP:SANYO
A 725-1648 1 INSULATOR,TALL,REAR,MLB,D2 REAR_INSULATOR CRITICAL PBUS_CAP:KEMET
085-4776 1 D2 MLB KEPLER FSB DEVEL BOM DEVEL_FSB CRITICAL DEVEL_FSB_BOM
SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
607-9546 1 D2 MLB KEPLER 2PHASE BASE BOM BASE CRITICAL BASE_BOM PAGE TITLE
725-1568 1 CPU_INSULATOR CRITICAL PD Parts
INSULATOR,CPU,D2
685-0016 1 PBUS PAIR,KEMET POSCAP,TALL MYLAR,D2 POSCAP_MYLAR CRITICAL POSCAP_MYLAR_PAIR
BOM Configuration
725-1569 1 INSULATOR,GPU,D2 GPU_INSULATOR CRITICAL DRAWING NUMBER SIZE
725-1621 1 INSULATOR,PCH,D2 PCH_INSULATOR CRITICAL SMC Apple Inc. 051-9589 D

REVISION
806-2897 2 CAN,COVER,2,J5 CAN_COVER1,CAN_COVER2 CRITICAL 341S3308 1 IC,SMC,DEVELOPMENT-FSB,A3,D2 U4900 CRITICAL SMC_PROG:FSB
R
4.18.0
825-7697 1 TEXT,LABEL,MLB,D2 TEXT_LABEL CRITICAL 341S3309 1 IC,SMC,PVB,A3,2.2F36,D2 U4900 CRITICAL SMC_PROG:PVB
946-3819 1 D2 MLB DYMAX ADHESIVE SEE-CURE 29993-SC EDGE_BOND CRITICAL
EFI ROM THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
5 OF 132
825-7841 1 LBL,PART CONFIG,BOARDS,D2 CONFIG_LABEL CRITICAL II NOT TO REPRODUCE OR COPY IT
341S3595 1 IC,EFI,ROM,FSB, D2 U6100 CRITICAL BOOTROM_PROG:FSB
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOM Variants (continued from CSA 5) TABLE_BOMGROUP_HEAD
Bar Code Labels / EEEE #’s (continued from CSA 5)
BOM NUMBER BOM NAME BOM OPTIONS PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
TABLE_BOMGROUP_ITEM
639-3382 PCBA,2.3G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,DY41 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY41,DEVEL_BOM,RAM_2G_ELPIDA_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY41] CRITICAL EEEE:DY41

TABLE_BOMGROUP_ITEM
639-3383 PCBA,2.3G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,DY42 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY42,DEVEL_BOM,RAM_2G_ELPIDA_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY42] CRITICAL EEEE:DY42

TABLE_BOMGROUP_ITEM
639-3445 PCBA,2.3G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,DYJ5 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DYJ5,DEVEL_BOM,RAM_4G_ELPIDA_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DYJ5] CRITICAL EEEE:DYJ5

TABLE_BOMGROUP_ITEM
639-3446 PCBA,2.3G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,DYJ6 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DYJ6,DEVEL_BOM,RAM_4G_ELPIDA_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DYJ6] CRITICAL EEEE:DYJ6
Elipda DQ’d
TABLE_BOMGROUP_ITEM
639-2818 PCBA,2.6G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRF0 BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF0,DEVEL_BOM,RAM_2G_ELPIDA_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DRF0] CRITICAL EEEE:DRF0
Keeping for PRQ

TABLE_BOMGROUP_ITEM
639-2820 PCBA,2.6G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,DRDP 825-7563 1 [EEEE:DRDP] CRITICAL EEEE:DRDP

D 639-2823 PCBA,2.6G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,DRDT
BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDP,DEVEL_BOM,RAM_2G_ELPIDA_1600
BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDT,DEVEL_BOM,RAM_4G_ELPIDA_1600
TABLE_BOMGROUP_ITEM
825-7563 1
LABEL,MLB/LIO,MBA
LABEL,MLB/LIO,MBA [EEEE:DRDT] CRITICAL EEEE:DRDT

D
TABLE_BOMGROUP_ITEM
639-2819 PCBA,2.6G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,DRDQ BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDQ,DEVEL_BOM,RAM_4G_ELPIDA_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DRDQ] CRITICAL EEEE:DRDQ

TABLE_BOMGROUP_ITEM
639-3632 PCBA,2.7G,8G_ELP,VRAM_HYN,MLB_KEPLER,D2,F0JD BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0JD,DEVEL_BOM,RAM_2G_ELPIDA_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0JD] CRITICAL EEEE:F0JD

TABLE_BOMGROUP_ITEM
639-3633 PCBA,2.7G,8G_ELP,VRAM_SAM,MLB_KEPLER,D2,F0J3 BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0J3,DEVEL_BOM,RAM_2G_ELPIDA_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0J3] CRITICAL EEEE:F0J3

TABLE_BOMGROUP_ITEM
639-3630 PCBA,2.7G,16G_ELP,VRAM_HYN,MLB_KEPLER,D2,F0J4 BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0J4,DEVEL_BOM,RAM_4G_ELPIDA_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0J4] CRITICAL EEEE:F0J4

TABLE_BOMGROUP_ITEM
639-3631 PCBA,2.7G,16G_ELP,VRAM_SAM,MLB_KEPLER,D2,F0JC BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0JC,DEVEL_BOM,RAM_4G_ELPIDA_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0JC] CRITICAL EEEE:F0JC
C C
B B
PAGE TITLE
BOM Variants
DRAWING NUMBER SIZE

REVISION
R
4.18.0
6 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J6701 - audio flex FUNC_TEST J6950 - battery ICT Test Points NC NO_TESTs
Functional Test Points I1731
FUNC_TEST
TRUE AUD_HP_PORT_L 53 54 58 I1759 TRUE PPVBAT_G3H_CONN 8X 60 61
NO_TEST
TRUE NC_SMC_FAN_3_TACH
FUNC_TEST TRUE AUD_HP_PORT_R 53 54 58 TRUE SMBUS_SMC_5_G3_SCL 41 44 CPU NO_TESTs
J3501 - airport FUNC_TEST J5100 - lpc + spi I1733
TRUE AUD_SPDIF_OUT_JACK 53 58
I1760
TRUE SMBUS_SMC_5_G3_SDA 41 44 NO_TEST
TRUE NC_SMC_FAN_3_CTL
AP_CLKREQ_Q_L LPCPLUS_GPIO I1735 I1761 TP_CPU_RSVD<65..62> NC_TP_CPU_RSVD<65..62> NC_SMC_FAN_2_TACH
I1596 TRUE 34 I1652 TRUE 20 43 TRUE TRUE
I1734 TRUE AUD_TIPDET_INV 59 I1763 TRUE SYS_DETECT_L 60 MAKE_BASE=TRUE
I1597 TRUE AP_RESET_CONN_L 34 I1655 TRUE LPCPLUS_RESET_L 25 43 TP_CPU_RSVD<58..45> TRUE NC_TP_CPU_RSVD<58..45> TRUE NC_SMC_FAN_2_CTL
I1736 TRUE AUD_TYPEDET 58 59 TRUE GND 8X GND MAKE_BASE=TRUE
I1599 TRUE PCIE_AP_D2R_PI_N 34 92 I1656 TRUE LPC_AD<0> 17 41 43 82 TP_CPU_RSVD<43..32> TRUE NC_TP_CPU_RSVD<43..32> TRUE NC_FW2_TPBP
92
I1738 TRUE CH_HS_GND 4X 58 MAKE_BASE=TRUE
I1600 TRUE PCIE_AP_D2R_PI_P 34 92 I1658 TRUE LPC_AD<1> 17 41 43 82 TP_CPU_RSVD<27..26> TRUE NC_TP_CPU_RSVD<27..26> TRUE NC_FW2_TPBN
92
I1737 TRUE CH_HS_MIC 58 MAKE_BASE=TRUE
TRUE PCIE_AP_R2D_N TRUE LPC_AD<2> TP_CPU_RSVD<24..15> TRUE NC_TP_CPU_RSVD<24..15> TRUE NC_FW2_TPBIAS
I1601
TRUE PCIE_AP_R2D_P
34 92
34 92
I1659
TRUE LPC_AD<3>
17 41 43 82
92
17 41 43 82
I1740 TRUE PP3V3_S0 7 8 96 J9000 - eDP TP_CPU_RSVD<2..1>
MAKE_BASE=TRUE
TRUE NC_TP_CPU_RSVD<2..1> TRUE NC_FW2_TPAP
I1602 I1657 US_HS_GND DP_INT_AUX_N
92
I1739 TRUE 4X 58 I1762 TRUE 81 95 MAKE_BASE=TRUE
I1603 TRUE PCIE_CLK100M_AP_CONN_N 34 96 I1661 TRUE LPC_CLK33M_LPCPLUS 25 43 92 TP_CPU_RSVD_NCTF<8..5> TRUE NC_TP_CPU_RSVD_NCTF<8..5> TRUE NC_FW2_TPAN
I1741 TRUE US_HS_MIC 58 I1764 TRUE DP_INT_AUX_P 81 95 MAKE_BASE=TRUE
I1604 TRUE PCIE_CLK100M_AP_CONN_P 34 96 I1660 TRUE LPC_FRAME_L 17 41 43 82 TRUE NC_FW0_TPBP
GND 2X GND DP_INT_ML_N<0>
D
92 TRUE TRUE 81 95
I1766
PCIE_WAKE_L LPC_PWRDWN_L NC NO_TESTs NC_FW0_TPBN
D I1605
I1606
TRUE
TRUE PP3V3_S3RS4_BT_F
18 34
34
I1663
I1664
TRUE
TRUE LPC_SERIRQ
18 25 41 43
17 41 43
J6801 - 3-mic
I1765
I1768
TRUE
TRUE
DP_INT_ML_N<1>
DP_INT_ML_N<2>
81 95
81 95 18 TP_CRT_IG_BLUE
NO_TEST
TRUE NC_CRT_IG_BLUE
TRUE
TRUE NC_FW0_TPAP
I1608 TRUE PP3V3_WLAN 34 42 I1662 TRUE PM_CLKRUN_L 18 41 43 MAKE_BASE=TRUE TRUE NC_ESTARLDO_EN
I1743 TRUE CON_DMIC_CLK 59 I1767 TRUE DP_INT_ML_N<3> 81 95 18 TP_CRT_IG_GREEN TRUE NC_CRT_IG_GREEN
I1609 TRUE USB_BT_CONN_N 34 91 I1665 TRUE PP5V_S0 7 8 MAKE_BASE=TRUE TRUE NC_ALS_GAIN
I1742 TRUE CON_DMIC_PWR 59 I1769 TRUE DP_INT_ML_P<0> 81 95 18 TP_CRT_IG_RED TRUE NC_CRT_IG_RED
I1607 TRUE USB_BT_CONN_P 34 91 I1666 TRUE SMC_RESET_L 41 42 43 61 MAKE_BASE=TRUE TRUE NC_USB_HUB_PRTPWR2 26
I1745 TRUE CON_DMIC_SDA1 59 I1770 TRUE DP_INT_ML_P<1> 81 95 18 TP_CRT_IG_DDC_CLK TRUE NC_CRT_IG_DDC_CLK
I1611 TRUE WIFI_EVENT_L 34 41 42 I1668 TRUE SMC_ROMBOOT 42 43 MAKE_BASE=TRUE TRUE NC_USB_HUB_PRTPWR3 26
I1744 TRUE CON_DMIC_SDA2 59 I1771 TRUE DP_INT_ML_P<2> 81 95 18 TP_CRT_IG_DDC_DATA TRUE NC_CRT_IG_DDC_DATA
TRUE GND 4X GND I1669 TRUE SMC_RX_L 41 42 43 MAKE_BASE=TRUE TRUE NC_USB_HUB_PRTPWR4 26
TRUE GND I1773 TRUE DP_INT_ML_P<3> 81 95 18 TP_CRT_IG_HSYNC TRUE NC_CRT_IG_HSYNC
I1667 TRUE SMC_TCK 41 42 43 MAKE_BASE=TRUE TRUE NC_USB_HUB_OCS2 26
TRUE LCD_FSS TP_CRT_IG_VSYNC TRUE NC_CRT_IG_VSYNC
J3502 - ALS camera I1671 TRUE SMC_TDI 41 42 43
J6802 - L speaker
I1772
TRUE LCD_HPD_CONN
81 82
81
18
18 TP_LVDS_IG_CTRL_CLK
MAKE_BASE=TRUE
TRUE NC_LVDS_IG_CTRL_CLK
TRUE NC_USB_HUB_OCS3 26
PP5V_S3_ALSCAMERA_F SMC_TDO I1774 NC_USB_HUB_OCS4

I1610 TRUE 34 I1670 TRUE 41 42 43 MAKE_BASE=TRUE TRUE 26
I1746 TRUE SPKRCONN_L_ID 59 I1775 TRUE LED_RETURN_1 81 86 18 TP_LVDS_IG_CTRL_DATA TRUE NC_LVDS_IG_CTRL_DATA
I1613 TRUE SMBUS_SMC_2_S3_SCL 7 41 44 94 I1673 TRUE SMC_TMS 41 42 43 MAKE_BASE=TRUE TRUE NC_SMC_XOSC1 41
I1748 TRUE SPKRCONN_L_OUT_N 57 59 96 I1776 TRUE LED_RETURN_2 81 86 18 TP_PCH_LVDS_VBG TRUE NC_PCH_LVDS_VBG
I1614 TRUE SMBUS_SMC_2_S3_SDA 7 41 44 94 I1674 TRUE SMC_TX_L 41 42 43 MAKE_BASE=TRUE TRUE NC_SMC_ODD_DETECT 42
I1747 TRUE SPKRCONN_L_OUT_P 57 59 96 I1777 TRUE LED_RETURN_3 81 86
I1612 TRUE USB_CAMERA_CONN_N 34 91 I1672 TRUE SPIROM_USE_MLB 20 43 52 TRUE NC_SMC_SYS_LED 42
I1750 TRUE SPKRCONN_SL_OUT_N 57 59 96 I1779 TRUE LED_RETURN_4 81 86 17 TP_HDA_SDIN1 TRUE NC_HDA_SDIN1
I1615 TRUE USB_CAMERA_CONN_P 34 91 I1675 TRUE SPI_ALT_CLK 43 MAKE_BASE=TRUE TRUE NC_SMC_HIB_L 41
I1749 TRUE SPKRCONN_SL_OUT_P 57 59 96 I1778 TRUE LED_RETURN_5 81 86 17 TP_HDA_SDIN2 TRUE NC_HDA_SDIN2
TRUE GND I1676 TRUE SPI_ALT_CS_L 43 MAKE_BASE=TRUE TRUE NC_SMBUS_SMC_4_ASF_SDA 42
TRUE GND I1780 TRUE LED_RETURN_6 81 86 17 TP_HDA_SDIN3 TRUE NC_HDA_SDIN3
I1678 TRUE SPI_ALT_MISO 43 MAKE_BASE=TRUE TRUE NC_SMBUS_SMC_4_ASF_SCL 42
TRUE PP5VR3V3_SW_LCD 3X 81 TP_PCI_AD<31..0> TRUE NC_PCI_AD<31..0>
J4400 - rio coax I1679 TRUE SPI_ALT_MOSI 43
I1781
TRUE PPVOUT_S0_LCDBKLT TP_PCI_C_BE_L<3..0>
MAKE_BASE=TRUE
TRUE NC_PCI_C_BE_L<3..0>
TRUE NC_SMC_T25_EN_L 8
I1616 TRUE HDMI_EG_CLK_C_N 38 77 95 I1677 TRUE TP_SMC_MD1 43 J6803 - R speaker I1782

TRUE GND
81 86 99
16X GND TP_PCI_GNT3_L

MAKE_BASE=TRUE
TRUE NC_PCI_GNT3_L
TRUE NC_SMC_T25_ISENSE
I1618 TRUE HDMI_EG_CLK_C_P 38 77 95 I1681 TRUE TP_SMC_TRST_L 43 I1751 TRUE SPKRCONN_R_ID 59 MAKE_BASE=TRUE TRUE NC_ISNS_P1V5R1V35_CPUDDRP 69 98
TP_PCI_GNT2_L TRUE NC_PCI_GNT2_L
I1619 TRUE HDMI_EG_DATA_C_N<0> 38 77 95 TRUE GND 2X GND I1753 TRUE SPKRCONN_R_OUT_N 57 59 96 MAKE_BASE=TRUE TRUE NC_ISNS_P1V5R1V35_CPUDDRN 69 98
NO_TEST=TRUE TP_PCI_GNT1_L TRUE NC_PCI_GNT1_L
I1617 TRUE HDMI_EG_DATA_C_N<1> 38 77 95 J5700 - ipd flex I1752 TRUE SPKRCONN_R_OUT_P 57 59 96
TP_PCI_GNT0_L
MAKE_BASE=TRUE
TRUE NC_PCI_GNT0_L
TRUE NC_ISNS_LCDBKLTP 99
I1621 TRUE HDMI_EG_DATA_C_N<2> 38 77 95 I1685 TRUE Z2_CS_L 49 I1755 TRUE SPKRCONN_SR_OUT_N 57 59 96 TRUE TBT_A_D2R_C_P<1..0> 84 93 MAKE_BASE=TRUE TRUE NC_ISNS_LCDBKLTN 99
TP_PCI_PAR TRUE NC_PCI_PAR
I1620 TRUE HDMI_EG_DATA_C_P<0> 38 77 95 I1686 TRUE Z2_DEBUG3 I1754 TRUE SPKRCONN_SR_OUT_P 57 59 96 TRUE TBT_A_D2R_C_N<1..0> 84 93 MAKE_BASE=TRUE TRUE NC_ISNS_LCD_PANELP 81 98
TP_PCI_RESET_L TRUE NC_PCI_RESET_L
I1623 TRUE HDMI_EG_DATA_C_P<1> 38 77 95 I1687 TRUE Z2_MOSI 49 TRUE GND TRUE TBT_A_D2R_P<1..0> 7 35 84 93 MAKE_BASE=TRUE TRUE NC_ISNS_LCD_PANELN 81 98
19 TP_PCI_PME_L TRUE NC_PCI_PME_L
I1624 TRUE HDMI_EG_DATA_C_P<2> 38 77 95 I1689 TRUE Z2_MISO 49 TRUE TBT_A_D2R_N<1..0> 7 35 84 93 MAKE_BASE=TRUE TRUE NC_ISNS_AIRPORTP 99
TP_PCI_CLK33M_OUT3 TRUE NC_PCI_CLK33M_OUT3
I1622 TRUE PCIE_CLK100M_ENET_N 17 38 92 I1688 TRUE Z2_SCLK 49 J6900 - DC PWR TRUE TBT_A_R2D_C_P<1..0>
19
7 35 84 93
TP_PCH_NV_RCOMP
MAKE_BASE=TRUE
TRUE NC_PCH_NV_RCOMP
TRUE NC_ISNS_AIRPORTN 99
TRUE PCIE_CLK100M_ENET_P 17 38 92 TRUE Z2_HOST_INTN 49 TRUE ADAPTER_SENSE 60 TRUE TBT_A_R2D_C_N<1..0> 35 84 93 MAKE_BASE=TRUE
C
I1625 I1691 I1756
C I1626 TRUE
TRUE
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
17 38 92
17 38 92
I1690 TRUE
TRUE
Z2_CLKIN
Z2_KEY_ACT_L
49
49
I1758 TRUE
TRUE
PP18V5_DCIN_FUSE
TDM_ONEWIRE_MPM
2X 60
60
TRUE
TRUE
TBT_A_R2D_P<1..0>
TBT_A_R2D_N<1..0>
84 93
84 93
TP_NV_DQ<15..0>
TP_NV_DQS<1..0>
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_NV_DQ<15..0>
NC_NV_DQS<1..0> TP_HDMI_CEC TRUE
MAKE_BASE=TRUE
NC_HDMI_CEC
I1628 I1692 I1757
TP_NV_CE_L<3..0> TRUE NC_NV_CE_L<3..0>
I1629 TRUE PCIE_ENET_R2D_C_N 17 38 92 I1694 TRUE Z2_RESET TRUE GND 2X GND TRUE TBT_B_D2R_C_P<1..0> 85 93 MAKE_BASE=TRUE
TP_NV_ALE TRUE NC_NV_ALE
I1627 TRUE PCIE_ENET_R2D_C_P 17 38 92 I1693 TRUE PSOC_F_CS_L 49 TRUE TBT_B_D2R_C_N<1..0> 85 93 MAKE_BASE=TRUE TP_DP_IG_C_HPD TRUE NC_DP_IG_C_HPD
TP_NV_CLE TRUE NC_NV_CLE MAKE_BASE=TRUE
I1631 TRUE USB3_EXTB_RX_N 19 38 91 I1695 TRUE PICKB_L 49 POWER RAILS TRUE TBT_B_D2R_P<1..0> 35 85 93
TP_NV_RB_L
MAKE_BASE=TRUE
NC_NV_RB_L
TP_DP_IG_C_CTRL_CLK TRUE NC_DP_IG_C_CTRL_CLK
TRUE MAKE_BASE=TRUE
I1630 TRUE USB3_EXTB_RX_P 19 38 91 I1799 TRUE PP3V3_S4 7 8 FUNC_TEST TRUE TBT_B_D2R_N<1..0> 35 85 93 MAKE_BASE=TRUE TP_DP_IG_C_CTRL_DATA TRUE NC_DP_IG_C_CTRL_DATA
TP_NV_WR_RE_L<1..0> TRUE NC_NV_WR_RE_L<1..0> MAKE_BASE=TRUE
I1633 TRUE USB3_EXTB_TX_C_N 38 97 I1800 TRUE PP5V_S5 7 8 TRUE TBT_B_R2D_C_P<1..0> 7 35 85 93 MAKE_BASE=TRUE 18 TP_DP_IG_C_MLP<3..0> TRUE NC_DP_IG_C_MLP<3..0>
TRUE PM_SLP_S3_L 7 18 27 38 41 70 TP_NV_WE_CK_L<1..0> TRUE NC_NV_WE_CK_L<1..0> MAKE_BASE=TRUE
I1634 TRUE USB3_EXTB_TX_C_P 38 97 I1697 TRUE PSOC_MISO 49 TRUE TBT_B_R2D_C_N<1..0> 35 85 93 MAKE_BASE=TRUE 18 TP_DP_IG_C_MLN<3..0> TRUE NC_DP_IG_C_MLN<3..0>
TRUE PP0V75_S0_DDRVTT 8 17 TP_PCIE_CLK100M_PE4N TRUE NC_PCIE_CLK100M_PE4N MAKE_BASE=TRUE
I1632 TRUE USB_EXTB_N 26 38 91 I1797 TRUE PSOC_MOSI 49 TRUE TBT_B_R2D_P<1..0> 85 93 MAKE_BASE=TRUE TP_DP_IG_C_AUXP TRUE NC_DP_IG_C_AUXP
TRUE PP1V05_S0 8 17 TP_PCIE_CLK100M_PE4P TRUE NC_PCIE_CLK100M_PE4P MAKE_BASE=TRUE
I1635 TRUE USB_EXTB_P 26 38 91 I1798 TRUE PSOC_SCLK 49 TRUE TBT_B_R2D_N<1..0> 85 93 MAKE_BASE=TRUE TP_DP_IG_C_AUXN TRUE NC_DP_IG_C_AUXN
TP_PCIE_CLK100M_PE5N TRUE NC_PCIE_CLK100M_PE5N MAKE_BASE=TRUE
TRUE GND 19X GND I1817 TRUE SMBUS_SMC_2_S3_SCL 7 41 44 94 TRUE DP_TBTSNK0_ML_C_P<3..0> 35 77 95 MAKE_BASE=TRUE
TRUE PP1V8_S0 8 TP_PCIE_CLK100M_PE5P TRUE NC_PCIE_CLK100M_PE5P 18 TP_DP_IG_D_HPD TRUE NC_DP_IG_D_HPD
I1818 TRUE SMBUS_SMC_2_S3_SDA 7 41 44 94 TRUE DP_TBTSNK0_ML_C_N<3..0> 35 77 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
TRUE PP3V3_S0 7 8 96 TP_PCIE_CLK100M_PE6N TRUE NC_PCIE_CLK100M_PE6N 18 TP_DP_IG_D_CTRL_CLK TRUE NC_DP_IG_D_CTRL_CLK
TRUE GND 2X GND TRUE DP_TBTSNK0_ML_P<3..0> MAKE_BASE=TRUE MAKE_BASE=TRUE
J4410 - rio flex TRUE PP3V3_S0GPU 8
TRUE DP_TBTSNK0_ML_N<3..0>
35 95
TP_PCIE_CLK100M_PE6P TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE6P 18 TP_DP_IG_D_CTRL_DATA TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_CTRL_DATA
I1636 TRUE ENET_CLKREQ_L 17 38 J5713 - keyboard TRUE
PP3V3_S3 7 8
TRUE DP_TBTSNK0_AUXCH_C_P
35 95
35 83 95
TP_PCIE_CLK100M_PE7N TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PE7N 18 TP_DP_IG_D_MLP<3..0> TRUE
MAKE_BASE=TRUE
NC_DP_IG_D_MLP<3..0>
TRUE ENET_RESET_L 25 TRUE PP3V3_S4 7 8 TRUE
PP3V3_S5 8 96 TP_PCIE_CLK100M_PE7P TRUE NC_PCIE_CLK100M_PE7P 18 TP_DP_IG_D_MLN<3..0> TRUE NC_DP_IG_D_MLN<3..0>
I1638 I1802 DP_TBTSNK0_AUXCH_C_N
TRUE 35 83 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1639 TRUE HDMI_EG_DDC_CLK 38 77 I1803 TRUE PP3V42_G3H 7 8 TRUE PP3V3_S5_AVREF_SMC 41 42 49 TP_PSOC_P1_3 TRUE NC_PSOC_P1_3 18 TP_DP_IG_D_AUXP TRUE NC_DP_IG_D_AUXP
TRUE DP_TBTSNK0_AUXCH_P 35 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1637 TRUE HDMI_EG_DDC_DATA 38 77 I1696 TRUE WS_CONTROL_KBD 49 TRUE PP3V42_G3H 7 8 TP_SATA_B_D2RN TRUE NC_SATA_B_D2RN 18 TP_DP_IG_D_AUXN TRUE NC_DP_IG_D_AUXN
TRUE DP_TBTSNK0_AUXCH_N 35 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1641 TRUE HDMI_HPD_L 38 42 82 I1698 TRUE WS_KBD1 49 TRUE PP5V_S0 7 8 TP_SATA_B_D2RP TRUE NC_SATA_B_D2RP
TRUE DP_TBTSNK1_ML_C_P<3..0> 35 77 95 MAKE_BASE=TRUE
I1640 TRUE I2C_DPMUX_A_SCL 44 I1699 TRUE WS_KBD10 49 TRUE PP5V_S3 8 TP_SATA_B_R2D_CN TRUE NC_SATA_B_R2D_CN 18 TP_SDVO_TVCLKINN TRUE NC_SDVO_TVCLKINN
TRUE DP_TBTSNK1_ML_C_N<3..0> 35 77 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1643 TRUE I2C_DPMUX_A_SDA 44 I1700 TRUE WS_KBD11 49 TRUE PP5V_S5 7 8 TP_SATA_B_R2D_CP TRUE NC_SATA_B_R2D_CP 18 TP_SDVO_TVCLKINP TRUE NC_SDVO_TVCLKINP
TRUE DP_TBTSNK1_ML_P<3..0> 35 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1644 TRUE PM_SLP_S3_L 7 18 27 38 41 70 I1702 TRUE WS_KBD12 49 TRUE PPBUS_G3H 8 17 TP_SATA_D_D2RN TRUE NC_SATA_D_D2RN
TRUE DP_TBTSNK1_ML_N<3..0> 35 95 MAKE_BASE=TRUE 18 TP_SDVO_STALLN TRUE NC_SDVO_STALLN
I1642 TRUE PM_SLP_S4_L 18 27 34 38 40 41 70 I1701 TRUE WS_KBD13 49 TRUE PPDCIN_G3H 8 17 TP_SATA_D_D2RP TRUE NC_SATA_D_D2RP MAKE_BASE=TRUE
TRUE DP_TBTSNK1_AUXCH_C_P 35 83 95 MAKE_BASE=TRUE 18 TP_SDVO_STALLP TRUE NC_SDVO_STALLP
I1645 TRUE PP1V5_S0_RIO 8 I1703 TRUE WS_KBD14 49 TRUE PPVCORE_GPU 8 17 TP_SATA_D_R2D_CN TRUE NC_SATA_D_R2D_CN MAKE_BASE=TRUE
TRUE DP_TBTSNK1_AUXCH_C_N 35 83 95 MAKE_BASE=TRUE
I1646 TRUE PP3V3_S3 7 3X P3V3_S3 I1704 TRUE WS_KBD15_CAP 49 TRUE PPVCORE_S0_CPU 8 17 TP_SATA_D_R2D_CP TRUE NC_SATA_D_R2D_CP 18 TP_SDVO_INTN TRUE NC_SDVO_INTN
8 TRUE DP_TBTSNK1_AUXCH_P 35 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
I1648 TRUE PP3V3_S4 7 8 I1705 TRUE WS_KBD16_NUM 49 TRUE PPVTTDDR_S3 8 17 TP_SATA_E_D2RN TRUE NC_SATA_E_D2RN 18 TP_SDVO_INTP TRUE NC_SDVO_INTP
TRUE DP_TBTSNK1_AUXCH_N 35 95 MAKE_BASE=TRUE MAKE_BASE=TRUE
PP5V_S4 8 5X P5V_S4 WS_KBD17 TP_SATA_E_D2RP NC_SATA_E_D2RP
B I1649
I1647
TRUE
TRUE SDCONN_STATE_CHANGE_RIO 25 38
I1707
I1706
TRUE
TRUE WS_KBD18
49
49 NC NO_TESTs
17
17 TP_SATA_E_R2D_CN
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SATA_E_R2D_CN TP_GPU_BUFRST_L TRUE
MAKE_BASE=TRUE
NC_GPU_BUFRST_L B
I1651 TRUE SD_PWR_EN 9 38 I1708 TRUE WS_KBD19 49 NO_TEST 17 TP_SATA_E_R2D_CP TRUE NC_SATA_E_R2D_CP TP_GPU_GSTATE<0> TRUE NC_GPU_GSTATE<0>
MAKE_BASE=TRUE MAKE_BASE=TRUE
I1650 TRUE USB_EXTB_OC_L 24 38 I1709 TRUE WS_KBD2 49 17 TP_PCIE_5_D2RN TRUE NC_PCIE_5_D2RN 17 TP_SATA_F_D2RN TRUE NC_SATA_F_D2RN TP_GPU_GSTATE<1> TRUE NC_GPU_GSTATE<1>
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
I1785 TRUE GND 10X GND I1710 TRUE WS_KBD20 49 17 TP_PCIE_5_D2RP TRUE NC_PCIE_5_D2RP 17 TP_SATA_F_D2RP TRUE NC_SATA_F_D2RP TP_GPU_MIOA_D<9..0> TRUE NC_GPU_MIOA_D<9..0>
I1712 TRUE WS_KBD21 49 17 TP_PCIE_5_R2D_CN TRUE NC_PCIE_5_R2D_CN 17 TP_SATA_F_R2D_CN TRUE NC_SATA_F_R2D_CN TP_GPU_MIOA_DE TRUE NC_GPU_MIOA_DE
TRUE WS_KBD22 TP_PCIE_5_R2D_CP TRUE NC_PCIE_5_R2D_CP TP_SATA_F_R2D_CP TRUE NC_SATA_F_R2D_CP
J5050 - hall effect I1711
TRUE WS_KBD23
49
49
17
MAKE_BASE=TRUE
17
TP_SMC_P41
MAKE_BASE=TRUE
TRUE NC_SMC_P41
PP3V42_G3H I1713 TP_PCIE_6_D2RN NC_PCIE_6_D2RN MAKE_BASE=TRUE
I1653 TRUE 7 8 17 TRUE
I1715 TRUE WS_KBD3 49 MAKE_BASE=TRUE
I1654 TRUE SMC_LID_R 42
WS_KBD4
17 TP_PCIE_6_D2RP TRUE NC_PCIE_6_D2RP GPU NO_TESTs TP_LVDS_EG_BKL_PWM TRUE NC_LVDS_EG_BKL_PWM
I1714 TRUE 49 MAKE_BASE=TRUE NO_TEST MAKE_BASE=TRUE
TRUE GND 17 TP_PCIE_6_R2D_CN TRUE NC_PCIE_6_R2D_CN TP_DVPDATA<21..4> TRUE NC_DVPDATA<21..4> 18 LVDS_IG_B_CLK_N TRUE NC_LVDS_IG_B_CLKN
I1717 TRUE WS_KBD5 49 MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
17 TP_PCIE_6_R2D_CP TRUE NC_PCIE_6_R2D_CP TP_DVPCNTL_M<1..0> TRUE NC_DVPCNTL_M<1..0> 18 LVDS_IG_B_CLK_P TRUE NC_LVDS_IG_B_CLKP
I1716 TRUE WS_KBD6 49 MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE NC_LVDS_IG_BKL_PWM
TP_DVPCNTL<2..0> TRUE NC_DVPDATA<2..0> LVDS_IG_BKL_PWM TRUE
J5650 - left fan I1718 TRUE WS_KBD7 49 17 TP_PCIE_7_D2RN TRUE
MAKE_BASE=TRUE
NC_PCIE_7_D2RN
7
7 TP_DVPCNTL<2..0>
MAKE_BASE=TRUE
TRUE NC_DVPDATA<2..0>
7
7
18
MAKE_BASE=TRUE
I1680 TRUE FAN_LT_PWM 48 I1720 TRUE WS_KBD8 49 17 TP_PCIE_7_D2RP TRUE NC_PCIE_7_D2RP MAKE_BASE=TRUE
MAKE_BASE=TRUE SMC_BS_ALRT_L TRUE NC_SMC_BS_ALRT_L
I1683 TRUE FAN_LT_TACH 48 I1719 TRUE WS_KBD9 49 17 TP_PCIE_7_R2D_CN TRUE NC_PCIE_7_R2D_CN MAKE_BASE=TRUE
MAKE_BASE=TRUE
I1793 TRUE PP5V_S0 7 3X P5V_S0 I1722 TRUE WS_KBD_ONOFF_L 49 17 TP_PCIE_7_R2D_CP TRUE NC_PCIE_7_R2D_CP
8 MAKE_BASE=TRUE
TRUE GND 5X GND I1721 TRUE WS_LEFT_OPTION_KBD 49
WS_LEFT_SHIFT_KBD
17 TP_PCIE_8_D2RN TRUE NC_PCIE_8_D2RN Thunderbolt NO_TESTs
I1723 TRUE 49 MAKE_BASE=TRUE NO_TEST
TP_PCIE_8_D2RP TRUE NC_PCIE_8_D2RP TP_TBT_XTAL25OUT TRUE NC_TBT_XTAL25OUT TRUE PCH_VSS_NCTF<15>
J5660 - right fan TRUE GND 2X GND
17
17 TP_PCIE_8_R2D_CN TRUE
MAKE_BASE=TRUE
NC_PCIE_8_R2D_CN
35
35 TP_TBT_PCIE_RESET0_L
MAKE_BASE=TRUE
TRUE NC_TBT_PCIE_RESET0_L
TRUE PCH_VSS_NCTF<1>
TRUE PCH_VSS_NCTF<17>
I1684 TRUE FAN_RT_PWM 48 MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<2>
17 TP_PCIE_8_R2D_CP TRUE NC_PCIE_8_R2D_CP 35 TP_TBT_PCIE_RESET1_L TRUE NC_TBT_PCIE_RESET1_L TRUE PCH_VSS_NCTF<19> 7
I1682 TRUE FAN_RT_TACH 48 MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<5>
35 TP_TBT_PCIE_RESET2_L TRUE NC_TBT_PCIE_RESET2_L TRUE PCH_VSS_NCTF<19> 7
I1795 TRUE PP5V_S0 3X P5V_S0 TP_PCIE_PE5_D2RN TRUE NC_PCIE_PE5_D2RN MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<7>
MAKE_BASE=TRUE 35 TP_TBT_PCIE_RESET3_L TRUE NC_TBT_PCIE_RESET3_L TRUE PCH_VSS_NCTF<21>
TRUE GND 5X GND TP_PCIE_PE5_D2RP TRUE NC_PCIE_PE5_D2RP MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<9>
MAKE_BASE=TRUE 35 TP_DP_TBTSRC_ML_CP<3..0> TRUE NC_DP_TBTSRC_ML_CP<3..0> TRUE PCH_VSS_NCTF<25>
TP_PCIE_PE5_R2D_CN TRUE NC_PCIE_PE5_R2D_CN MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<11>
MAKE_BASE=TRUE 35 TP_DP_TBTSRC_ML_CN<3..0> TRUE NC_DP_TBTSRC_ML_CN<3..0> TRUE PCH_VSS_NCTF<27>
TP_PCIE_PE5_R2D_CP TRUE NC_PCIE_PE5_R2D_CP MAKE_BASE=TRUE TRUE PCH_VSS_NCTF<12>
J5815 - kbd backlight MAKE_BASE=TRUE 35 TP_DP_TBTSRC_AUXCH_CP TRUE
MAKE_BASE=TRUE
NC_DP_TBTSRC_AUXCH_CP TRUE PCH_VSS_NCTF<29>
I1728 TRUE KBDLED_ANODE1 2X 50 TP_PCIE_PE6_D2RN TRUE NC_PCIE_PE6_D2RN 35 TP_DP_TBTSRC_AUXCH_CN TRUE NC_DP_TBTSRC_AUXCH_CN
A I1730 TRUE
TRUE
KBDLED_ANODE2
SMC_KBDLED_PRESENT_L
2X 50
50
TP_PCIE_PE6_D2RP
TP_PCIE_PE6_R2D_CN
TRUE
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCIE_PE6_D2RP
NC_PCIE_PE6_R2D_CN
MAKE_BASE=TRUE
I1729
MAKE_BASE=TRUE
PAGE TITLE
GND 4X GND TP_PCIE_PE6_R2D_CP NC_PCIE_PE6_R2D_CP PCH ALIASES
TRUE TRUE
MAKE_BASE=TRUE Functional / ICT Test
TP_PCIE_PE7_D2RN TRUE NC_PCIE_PE7_D2RN NC_LPC_DREQ0_L TP_LPC_DREQ0_L 17 DRAWING NUMBER SIZE
PLACEABLE BEAD-PROBES FOR TBT

TP_PCIE_PE7_D2RP TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCIE_PE7_D2RP
MAKE_BASE=TRUE TRUE

TP_PCIE_PE7_R2D_CN TRUE NC_PCIE_PE7_R2D_CN REVISION
TP_CLINK_CLK NC_CLINK_CLK
93 85 35 7 TBT_B_R2D_C_P<1> 1 TP
SM BEAD-PROBE BP0733 SIGNAL_MODEL=EMPTY
TP_PCIE_PE7_R2D_CP TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCIE_PE7_R2D_CP
17
17 TP_CLINK_DATA
TRUE
MAKE_BASE=TRUE
TRUE NC_CLINK_DATA
R
4.18.0
93 85 35 7 TBT_B_R2D_C_P<0> 1 TP
SM BEAD-PROBE
MAKE_BASE=TRUE NOTICE OF PROPRIETARY PROPERTY: BRANCH
BP0734 SIGNAL_MODEL=EMPTY TP_PCIE_PE8_D2RN TRUE NC_PCIE_PE8_D2RN 17 TP_CLINK_RESET_L TRUE NC_CLINK_RESET_L
93 84 35 7 TBT_A_R2D_C_P<1> 1 TP
SM BEAD-PROBE
MAKE_BASE=TRUE MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE
BP0735 SIGNAL_MODEL=EMPTY TP_PCIE_PE8_D2RP TRUE NC_PCIE_PE8_D2RP PROPRIETARY PROPERTY OF APPLE INC.
93 84 35 7 TBT_A_D2R_P<1> 1 TP
SM BEAD-PROBE
MAKE_BASE=TRUE 17 TP_PCIE_CLK100M_PEBN TRUE NC_PCIE_CLK100M_PEBN THE POSESSOR AGREES TO THE FOLLOWING: PAGE
BP0731 SIGNAL_MODEL=EMPTY TP_PCIE_PE8_R2D_CN NC_PCIE_PE8_R2D_CN
93 84 35 7 TBT_A_D2R_N<1> 1 TP
SM BEAD-PROBE BP0732 SIGNAL_MODEL=EMPTY TP_PCIE_PE8_R2D_CP
TRUE
TRUE
MAKE_BASE=TRUE
NC_PCIE_PE8_R2D_CP
17 TP_PCIE_CLK100M_PEBP
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_PCIE_CLK100M_PEBP I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
7 OF 132
MAKE_BASE=TRUE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
61 60 =PPBUS_G3H PPBUS_G3H 7 63 =PP3V3_S5_REG PP3V3_S5 7 96 1.8V/1.5V/1.2V/1.05V Rails
MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.8V MIN_LINE_WIDTH=0.6 MM VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE 68 =PP1V8_S0_REG PP1V8_S0 7 "GPU" Rails
G3H Rails =PPBUS_S0_LCDBKLT =PP3V3_GPU_P3V3GPUFET
MIN_LINE_WIDTH=0.6 MM
=PP3V3_S0GPU_FET PP3V3_S0GPU
86 69 4A max supply MIN_NECK_WIDTH=0.2 MM 88 69 7
VOLTAGE=1.5V MIN_LINE_WIDTH=0.3 MM
=PPVIN_S5_HS_OTHER_ISNS_R 46 =PP3V3_GPU_MISC_P3V3GPUMISCFET 69 MAKE_BASE=TRUE MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
=PPVIN_S5_HS_COMPUTING_ISNS_R 46 =PP3V3_S0_P3V3S0FET 69 MAKE_BASE=TRUE
=PP1V8R1V5_S0_PCH_VCCVRM 21
=PPVIN_S5_HS_GPU_ISNS_R 46 =PP3V3_S3_P3V3S3FET 69 =PP3V3_GPU_IFPX_PLLVDD 77
=PP1V8_S0_AUDIO
=PPVIN_SW_TBTBST 9 37 =PP3V3_S4_DPAPWRSW =PP3V3_S0_GFX3V3BIAS 80
=PP1V8_S0_CPU_VCCPLL 15
=PPBUS_S0_VSENSE 45 =PP3V3_S4_DPBPWRSW =PP3V3_GPU_VDD33 71 77 78 79
=PP1V8_S0_GPUFET
=PPBUS_G3H_T25_R =PP3V3_S4_P3V3S4FET 69
=PP1V8_S0_PCH_VCCTX_LVDS 23
46 =PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS =PP3V3_S5_CPU_VCCDDR 27
MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.8V =PP1V8_S0_PCH_VCC_DFTERM 20 21 23
MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE =PP3V3_S5_P1V2P1V8 68
=PPVDDIO_S0_SBCLK 25
=PPVIN_S0_CPUIMVP 65 66 =PP3V3_S5_P1V5S0 68 69 =PP3V3_S0GPU_MISC_FET PP3V3_S0GPU_MISC
=PP1V8_S0_P1V5_LDO
D
=PPVIN_S3_DDRREG
=PPVIN_S0_CPUVCCIOS0
64
67
=PP3V3_S5_P3V3SUSFET
=PP3V3_S5_PCH
69
18
15 13 =PP1V8_S0_CPU_VCCPLL_R PP1V8_S0_CPU_VCCPLL_R
MIN_LINE_WIDTH=0.5 MM VOLTAGE=1.8V
68 MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
D
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
=PPVIN_S0_CPUAXG 66 =PP3V3_S5_PCHPWRGD 70 =PP3V3_GPU_MISC 77
64 =PPDDR_S3_REG PP1V5R1V35_S3
=PPVIN_S0_VCCSAS0 62 =PP3V3_S5_PCH_GPIO 20 MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm
=PPVIN_S0_PCHVCCIOS0 87 =PP3V3_S5_PCH_VCCDSW 21 23 VOLTAGE=1.5V
MAKE_BASE=TRUE
46 =PPVIN_S5_HS_GPU_ISNS PPVIN_S5_HS_GPU_ISNS =PP3V3_S5_PWRCTL 70
MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.8V =PP1V5_S3_MEMRESET 27
MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE =PP3V3_S5_SMCBATLOW 42
=PPDDR_S3_MEMVREF 33
=PPVIN_S0_GFXIMVP 80 =PP3V3_S5_SYSCLK 25
=PPVIN_S3_P1V5S3RS0_FET 69
=PPVIN_S0GPU_P1V5P1V0 74 =PP3V3_S5_VMON 70
=PPVIN_S0_DDRREG_LDO 64
=PP3V3_S5_XDP 24
46 =PPVIN_S5_HS_OTHER_ISNS PPVIN_S5_HS_OTHER_ISNS =PPVIN_S3_MEM_ISNS_R 45
MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.8V =PP3V3_S4_TBTAPWRSW 84
MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE
=PP3V3_S4_TBTBPWRSW 85 45 =PPVIN_S3_MEM_ISNS PP1V5R1V35_MEM
=PPVIN_S5_P5VP3V3 63 MIN_LINE_WIDTH=0.2 mm
69 =PP3V3_S3_FET PP3V3_S3 7 MIN_NECK_WIDTH=0.17 mm
60 =PP18V5_DCIN_CONN PPDCIN_G3H 7 MIN_LINE_WIDTH=0.50MM VOLTAGE=3.3V VOLTAGE=1.5V
MIN_LINE_WIDTH=0.6 MM VOLTAGE=18.5V MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE MAKE_BASE=TRUE
=PP3V3_S3_BT 34 =PP1V5R1V35_S3_MEM_A 28 29
=PPDCIN_S5_CHGR 61
=PP3V3_S3_DPMUX_UC 82 =PP1V5R1V35_S3_MEM_B 30 31
60 =PP18V5_DCIN_ISOL PPDCIN_G3H_ISOL
MIN_LINE_WIDTH=0.6 MM VOLTAGE=18.5V =PP3V3_S3_ISNS 99
=PP3V3_S3_MEMRESET 27 69 =PP1V5_S3RS0_FET_ISNS PP1V5_S3RS0_CPUDDR 96
=PPDCIN_S5_CHGR_ISOL 61 MIN_LINE_WIDTH=0.6 MM
=PP3V3_S3_PCH_GPIO 19 25 MIN_NECK_WIDTH=0.2 MM
=PPDCIN_S5_VSENSE 45 VOLTAGE=1.5V
=PP3V3_S3_RIO 38 MAKE_BASE=TRUE
60 =PP3V42_G3H_REG PP3V42_G3H 7 =PP3V3_S3_SMBUS_SMC_2_S3 44 =PP1V5_S3RS0_VMON 70

MIN_LINE_WIDTH=0.3 MM VOLTAGE=3.42V TP_P1V8GPU_EN =P1V8GPU_EN
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE =PP3V3_S3_SMBUS_SMC_3 44 =PP1V5_S3_CPU_VCCDDR 11 14 16 27 88
=PP3V3_S5_LPCPLUS 43 =PP3V3_S3_TPAD
68 =PP1V5_S0_REG PP1V5_S0
=PP3V3_S5_SMC 41 42 78 =PP3V3_S3_USBMUX 26 MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
=PP3V42_G3H_CHGR 61 70 =PP3V3_S3_USB_HUB 26 VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP3V42_G3H_ONEWIREPROT 60 =PP3V3_S3_USB_RESET 26 74 =PP1V5R1V35_GPU_REG PP1V5R1V35_S0GPU
=PP3V42_G3H_PWRCTL 70 =PP3V3_S3_VREFMRGN 33 =PP1V5_S0_AUDIO 53 MIN_NECK_WIDTH=0.2 MM
C 58 =PP3V42_G3H_AUDIO
=PP3V42_G3H_SMBUS_SMC_5
=PP3V42_G3H_SMCUSBMUX
44
40
=PP3V3_S3_WLAN
=PP3V3_S3_GYRO
34
51
=PP3V3R1V5_S0_PCH_VCCSUSHDA 21 23 25
VOLTAGE=1.5V
MAKE_BASE=TRUE
=PP1V35_GPU_FBVDDQ 72 75 76
C
60 =PP3V42_G3H_TDM 68 =PP1V5_S0_RIO_LDO PP1V5_S0_RIO 7
=PP3V42_G3H_TPAD 49 =PP3V3_S3_SMS 51 MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.5V =PP1V35_GPU_S0_FB 73
42 =PP3V42_S3_HALL MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
=PPVIN_S5_SMCVREF 42 =PP3V3_S3_SDBUF 25
For PCH RTC Power =PP1V5_S0_RIO 38
=PPVBAT_G3_SYSCLK 25 69 =PP3V3_S0_FET PP3V3_S0 7 96
MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V 64 33 =PPVTT_S3_DDR_BUF PPVTTDDR_S3 7
25 =PPVRTC_G3_OUT PPVRTC_G3H MIN_NECK_WIDTH=0.075 mm MAKE_BASE=TRUE MIN_LINE_WIDTH=0.3 MM
MIN_LINE_WIDTH=0.3 MM VOLTAGE=3.42V MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE =PP3V3_S0_AUDIO 59 VOLTAGE=0.75V
MAKE_BASE=TRUE
5V Rails =PPVRTC_G3_PCH 17 18 21 =PP3V3_S0_AUDIO_DIG 53 58
=PPVTT_S0_DDR_LDO PP0V75_S0_DDRVTT =PP1V8_GPU_FET TP_GPU_PGOOD2
64 7 88
63 =PP5V_S5_LDO PP5V_S5 7 =PP3V3_S0_BKL_VDDIO 86 MIN_LINE_WIDTH=2 mm
MIN_LINE_WIDTH=0.5 MM VOLTAGE=5V MIN_NECK_WIDTH=0.17 mm MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.1 MM MAKE_BASE=TRUE =PP3V3_S0_CPUTHMSNS 47 VOLTAGE=0.75V
MAKE_BASE=TRUE
=PP5V_S5_P1V5S3RS0FET 69 =PP3V3_S0_CPU_VCCIO_SEL 13
=PP0V75_S0_MEM_VTT_A 32
=PP5V_S5_P5VSUSFET 69 =PP3V3_S0_DPMUX 82 83
=PP0V75_S0_MEM_VTT_B 32
=PP5V_S5_TPAD 49 =PP3V3_S0_DPMUXI2C 44 74 =PP1V05_S0GPU_REG PP1V0_S0GPU_ISNS
=PPVTT_S0_VTTCLAMP 27 MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.05V
69 =PP5V_SUS_FET PP5V_SUS =PP3V3_S0_DPMUX_UC 35 78 82 MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM VOLTAGE=5V 68 =PP1V05_SUS_LDO PP1V05_SUS
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE =PP3V3_S0_FAN_LT 48 MIN_LINE_WIDTH=0.4 MM =PP1V0_GPU_DPLL
=PP5V_SUS_PCH 23 =PP3V3_S0_FAN_RT 48 VOLTAGE=1.05V =PP1V0_GPU_DP_AB
MAKE_BASE=TRUE
63 =PP5V_S4_REG PP5V_S4 7 =PP3V3_S0_GPUTHMSNS 47 =PP1V0_GPU_DP_CD
MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V =PP1V05_SUS_PCH_JTAG 24
MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE =PP3V3_S0_HS_ISNS 46 =PP1V05_GPU_IFPCD_IOVDD 77
67 =PPCPUVCCIO_S0_REG PP1V05_S0 7
=PP5V_S4_RIO 38 =PP3V3_S0_IMVPISNS 46 MIN_LINE_WIDTH=0.6 MM =PP1V05_GPU_IFPEF_IOVDD 77
=PP5V_S4_P5VS0FET 69 =PP3V3_S0_ISNS 45 98 99 VOLTAGE=1.05V =PP1V05_GPU_PEX_IOVDD 73 79
MAKE_BASE=TRUE
=PP5V_S4_P5VS3FET 69 =PP3V3_S0_LCD 81 =PP1V05_GPU_PEX_PLLVDD 77 79
=PP1V05_S0_CPU_VCCIO 10 11 13 14 15
=PP5V_S0_LCD 81 =PP3V3_S0_P1V8GPUFET
=PPVCCIO_S0_XDP 24 45 =PPVCORE_GPU_REG PPVCORE_GPU 7
=PP5V_S3_LTUSB 40 =PP3V3_S0_P3V3TBTFET 37 MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.0V
=PPVCCIO_S0_CPUIMVP 65 MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
=PP5V_S4_ISNS =PP3V3_S0_PCH 17 23
=PPVCCIO_S0_SMC 42 =PPVCORE_GPU 72 79
=PP5V_S4_TPAD 49 =PP3V3_S0_PCH_GPIO 17 18 19 20 25 37
=PP1V05_S0_VMON 70
=PP5V_S4_AUDIO 53 59 =PP3V3_S0_PCH_VCC3_3_CLK 23
=PP1V05_S0_RMC =PPVCORE_S0_GFX_REG
B 69 =PP5V_S3_FET PP5V_S3
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5V
MAKE_BASE=TRUE
7 =PP3V3_S0_PCH_VCC3_3_GPIO
=PP3V3_S0_PCH_VCC3_3_HVCMOS
21 23
21 23 87 =PPPCHVCCIO_S0_REG PP1V05_PCHVCCIO_S0
98 80
B
=PP5V_S3_ISNS 99 =PP3V3_S0_PCH_VCC3_3_PCI 21 23 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
=PP5V_S3_ALSCAMERA 34 =PP3V3_S0_PCH_VCC3_3_SATA 21 23 MAKE_BASE=TRUE
=PP5V_S3_DDRREG 64 =PP3V3_S0_PCH_VCCADAC 23 =PP1V05_S0_PCH_VCCIO_PLLPCIE 21 GND =LVDS_VCCA 21
MIN_LINE_WIDTH=0.6MM
=PP5V_S3_DEBUG_ADC_AVDD 98 =PP3V3_S0_PWRCTL 70 88 =PP1V05_S0_PCH_VCCADPLL 23 MIN_NECK_WIDTH=0.085MM
VOLTAGE=0V
=PP5V_S3_DEBUG_ADC_DVDD 98 =PP3V3_S0_RSTBUF 25 =PP1V05_S0_PCH_VCCIO 21 23 MAKE_BASE=TRUE
=PP5V_S3_DEBUG_ISNS 98 =PP3V3_S0_SATAMUX 39 =PP1V05_S0_PCH_VCCIO_PCIE 18
=PP5V_S3_MEMRESET 27 =PP3V3_S0_SB_PM 25 70 =PP1V05_S0_PCH_VCCIO_SATA 17 21 23
69 =PP5V_S0_FET PP5V_S0 7 =PP3V3_S0_SMBUS_PCH 44 =PP1V05_S0_PCH_VCCIO_CLK 8 21 23 Chipset "VCore" Rails

MIN_LINE_WIDTH=0.4 MM VOLTAGE=5V
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE =PP3V3_S0_SMBUS_SMC_0_S0 44 =PP1V05_S0_PCH_VCCIO_USB 21 23 66 =PPVCORE_S0_CPU_REG PPVCORE_S0_CPU 7
MIN_LINE_WIDTH=0.6 MM MAKE_BASE=TRUE
=PP5V_S0GPU_P1V0P1V35_GPU 74 =PP3V3_S0_SMBUS_SMC_1_S0 44 =PP1V05_S0_PCH_VCC_CORE 21 23 MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V
68 =PP5V_S0_P1V5_LDO
=PP5V_S0_AUDIO_XW 9 =PP3V3_S0_SSD 39 =PP1V05_S0_PCH_VCCASW 21 23 =PPVCORE_S0_CPU 13 15 45 98
=PP5V_S0_BKL 86 =PP3V3_S0_SYSCLK 25 =PP1V05_S0_PCH_VCCIO_CLK 8 21 23

66 45 =PPVCORE_S0_AXG_REG PPVCORE_S0_AXG
=PP5V_S0_CPUIMVP 65 66 =PP3V3_S0_TBTI2C =PP1V05_S0_PCH_VCCDIFFCLK 17 21 23 MIN_LINE_WIDTH=0.6 MM MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
=PP5V_S0_CPUVCCIOS0 67 =PP3V3_S0_TBTPWRCTL 37 =PP1V05_S0_PCH 17 23
=PPVCORE_S0_CPU_VCCAXG 13 14 16
=PP5V_S0_FAN_LT 48 =PP3V3_S0_TPAD 50 =PP1V05_S0_PCH_VCCSSC 21 23
=PP5V_S0_FAN_RT 48 =PP3V3_S0_VMON 70 =PP1V05_S0_PCH_V_PROC_IO 21 23 16 13 =PP1V5_S3_CPU_VCCDQ PP1V5_S3_CPU_VCCDQ

=PP5V_S0_GFXIMVP 80 =PP3V3_S0_X29THMSNS 47 =PP1V05_S0_PCH_VCCIO_PLLUSB 21 MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V
=PP5V_S0_KBDLED 50 =PP3V3_S0_XDP 24 =PP1V05_S0_PCH_VCC_DMI 21 23

15 13 =PP1V05_S0_CPU_VCCPQE PP1V05_S0_CPU_VCCPQE
=PP5V_S0_LPCPLUS 43 =PP3V3_S0_DDR3THMSNS =PP1V05_S0_PCH_VCCIO_PLLFDI 21 MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.05V
=PP5V_S0_PCH 23 25 =PP3V3_S0_SPKRTHMSNS =PP1V05_S0_PCH_VCCDMI_FDI 21
TBT RAILS 99 62 =PPVCCSA_S0_REG PPVCCSA_S0_REG
=PP5V_S0_PCHVCCIOS0 87 =PP1V05_S0_P1V05TBTFET_R 99 MIN_LINE_WIDTH=0.6 MM VOLTAGE=0.9V
37 =PP3V3_TBTLC_FET PP3V3_TBTLC MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
=PP5V_S0_RMC 98 MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.15 MM
MAKE_BASE=TRUE =PPVCCSA_S0_CPU 13 16
=PP5V_S0_VCCSAS0 62 =PP3V3_TBT_PCH_GPIO 20 Defined here since TBT page does not know PBUS voltage
3.3V Rails
=PP5V_S0_VMON 70 =PPVDDIO_TBT_CLK 25 I1679
PPVIN_SW_TBTBST 37
A 69 =PP3V3_S4_FET PP3V3_S4
VOLTAGE=3.3V
MAKE_BASE=TRUE
7 =PP3V3_TBTLC_RTR 35 36 37
VOLTAGE=12.8V
36 =PP3V3_S4_TBT_R 37 =PP1V05_TBTLC_FET PP1V05_TBTLC 37
PAGE TITLE
=PP3V3_S4_TPAD
=PP3V3_S4_SMC 25 42
VOLTAGE=1.05V
MAKE_BASE=TRUE Backlight Rails Power Aliases
38 =PP3V3_S4_RIO =PP1V05_TBTLC_RTR 36 99 =PPBUS_SW_BKL PPBUS_SW_BKL DRAWING NUMBER SIZE
=PP3V3_S4_BT
69 =PP3V3_SUS_FET PP3V3_SUS
34
37 =PP1V05_TBTCIO_FET PP1V05_TBTCIO
MIN_NECK_WIDTH=0.25 MM VOLTAGE=12.6V
MIN_LINE_WIDTH=0.6 MM MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V PPBUS_S0_LCDBKLT_PWR 86 REVISION
=PP3V3_SUS_P1V05SUSLDO
VOLTAGE=3.3V
68
=PP1V05_TBTCIO_RTR
MAKE_BASE=TRUE
36
R
4.18.0
=PP3V3_SUS_PCH_VCCSUS 21 23 41 SMC_T25_EN_L NC_SMC_T25_EN_L 7 NOTICE OF PROPRIETARY PROPERTY: BRANCH
MAKE_BASE=TRUE
=PP3V3_SUS_PCH_VCCSUS_GPIO 21 23 THE INFORMATION CONTAINED HEREIN IS THE
=PP3V3_SUS_PCH_GPIO 17 18 19 20 37 9 =PP15V_TBT_REG PP15V_TBT THE POSESSOR AGREES TO THE FOLLOWING: PAGE
=PP3V3_SUS_ROM
52
23 21 =PP3V3_SUS_PCH_VCC_SPI
=PP3V3_SUS_PCH_VCCSUS_USB 21 23
VOLTAGE=15V
MAKE_BASE=TRUE
8 OF 132
=PP3V3_SUS_CNTRL 70 =PPHV_SW_TBTAPWRSW 84 99 37 =PP1V05_S0_P1V05TBTFET PP1V05_S0_P1V05TBTFET III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
=PP3V3_SUS_SMC 42 =PPHV_SW_TBTBPWRSW 85
VOLTAGE=1.05V
MAKE_BASE=TRUE IV ALL RIGHTS RESERVED 8 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ZT0915 Frame Holes T29 / GMUX JTAG Signals
CPU signals
2.8R2.3
1 GND_BATT_CHGND
ZT0970
TH-NSP CPU_VID<0..6> CPUIMVP_VID<0..6> TP_CPU_VTT_SELECT CPU_VTTSELECT
GND_CHASSIS_MLBCAN1 1 MAKE_BASE=TRUE MAKE_BASE=TRUE
ZT0950
TH-NSP SL-1.1X0.45-1.4x0.75
1 GND_CHASSIS_FAN
ZT0971 27 MEMVTT_EN =DDRVTT_EN 27 64
SL-2.3X3.9-2.9X4.5 TH-NSP MAKE_BASE=TRUE
GND_CHASSIS_MLBCAN2 1
ZT0974 SL-1.1X0.45-1.4x0.75 TBT_LSOE<3> TBT_LSEO_LSOE3 TBT_LSEO<3>

TH-NSP MAKE_BASE=TRUE NO_TEST=TRUE Unused PEG signals
1 GND_CHASSIS_MLBCAN5 ZT0972 TBT_LSOE<2> TBT_LSEO_LSOE2 TBT_LSEO<2> NC_PEG_D2R_P<15..14> =PEG_D2R_P<15..14>
D SL-1.1X0.45-1.4x0.75
GND_CHASSIS_MLBCAN3 1
TH-NSP MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_D2R_N<15..14>
NO_TEST=TRUE
=PEG_D2R_N<15..14>
10
10
D
ZT0975
TH-NSP SL-1.1X0.45-1.4x0.75
MAKE_BASE=TRUE NO_TEST=TRUE
NC_LVDS_IG_A_DATAP<3> LVDS_IG_A_DATA_P<3> 18 91
NC_PEG_R2D_C_P<15..14> =PEG_R2D_C_P<15..14> 10 MAKE_BASE=TRUE NO_TEST=TRUE
1 GND_CHASSIS_MLBCAN6 MAKE_BASE=TRUE NO_TEST=TRUE
GMUX ALIASES NC_LVDS_IG_A_DATAN<3> LVDS_IG_A_DATA_N<3> 18 91
SL-1.1X0.45-1.4x0.75 ZT0973 NC_PEG_R2D_C_N<15..14> =PEG_R2D_C_N<15..14> 10 MAKE_BASE=TRUE NO_TEST=TRUE
TH-NSP
GND GND_CHASSIS_MLBCAN4 1 82 EG_RESET_L GPU_RESET_L 71 78 T29 Signals Through PEG
MAKE_BASE=TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_DATAP<3> LVDS_IG_B_DATA_P<3> 18
SL-1.1X0.45-1.4x0.75 MAKE_BASE=TRUE NO_TEST=TRUE
18 LVDS_IG_BKL_ON IG_BKLT_EN 82
MAKE_BASE=TRUE 92 35 PCIE_TBT_D2R_P<3..0> =PEG_D2R_P<11..8> 10 NC_LVDS_IG_B_DATAN<3> LVDS_IG_B_DATA_N<3> 18
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
18 LVDS_IG_PANEL_PWR IG_LCD_PWR_EN 82
MAKE_BASE=TRUE 92 35 PCIE_TBT_D2R_N<3..0> =PEG_D2R_N<11..8> 10
MAKE_BASE=TRUE
THERMAL MODULE STANDOFFS PEX_CLKREQ_L EG_CLKREQ_IN_L 78 82
PCIE_TBT_R2D_C_P<3..0> =PEG_R2D_C_P<11..8> NC_LVDS_IG_A_CLK_N LVDS_IG_A_CLK_N
MAKE_BASE=TRUE 92 35 10 18 91
17 PEG_CLKREQ_L EG_CLKREQ_OUT_L 82
MAKE_BASE=TRUE 92 35 PCIE_TBT_R2D_C_N<3..0> =PEG_R2D_C_N<11..8> 10 NC_LVDS_IG_A_CLK_P LVDS_IG_A_CLK_P 18 91
82 DP_TBTSNK0_HPD_IG DPA_IG_HPD 18 82
SH0920 SH0927 SH0926 MAKE_BASE=TRUE
STDOFF-4.5OD2.15H-SM STDOFF-4.5OD2.15H-SM STDOFF-4.5OD2.15H-SM SH0925 82 DP_TBTSNK1_HPD_IG DPB_IG_HPD
GPU signals
18 82
STDOFF-4.5OD1.8H-SM MAKE_BASE=TRUE NC_LVDS_IG_A_DATA_N<2..0> LVDS_IG_A_DATA_N<2..0> 18 91
1 1 1 89 88 71 PEG_D2R_P<7..0> =PEG_D2R_P<7..0> 10 MAKE_BASE=TRUE NO_TEST=TRUE
1 MAKE_BASE=TRUE
NC_LVDS_IG_A_DATA_P<2..0> LVDS_IG_A_DATA_P<2..0> 18 91
89 88 71 PEG_D2R_N<7..0> =PEG_D2R_N<7..0> 10 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
17 PCIE_EXCARD_D2R_N TRUE NC_PCIE_EXCARD_D2R_N
SH0928 PCIE_EXCARD_D2R_P
MAKE_BASE=TRUE
NC_PCIE_EXCARD_D2R_P
89 71 PEG_R2D_C_P<7..0> =PEG_R2D_C_P<7..0> 10 NC_LVDS_IG_B_DATA_N<2..0> LVDS_IG_B_DATA_N<2..0> 18 91
17 TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
STDOFF-4.5OD2.15H-SM SH0923 MAKE_BASE=TRUE
SH0929 PCIE_EXCARD_R2D_C_N NC_PCIE_EXCARD_R2D_C_N PEG_R2D_C_N<7..0> =PEG_R2D_C_N<7..0> NC_LVDS_IG_B_DATA_P<2..0> LVDS_IG_B_DATA_P<2..0>
SH0921 STDOFF-4.5OD2.15H-SM
1 STDOFF-4.5OD1.8H-SM 17
PCIE_EXCARD_R2D_C_P
TRUE
MAKE_BASE=TRUE
NC_PCIE_EXCARD_R2D_C_P
89 71
MAKE_BASE=TRUE
10
18 91
STDOFF-4.5OD2.15H-SM-1 1
17 TRUE
MAKE_BASE=TRUE NC_LVDS_IG_DDC_CLK LVDS_IG_DDC_CLK 18
1 UNUSED TBT PORTS MAKE_BASE=TRUE NO_TEST=TRUE
1
TBT_D2R_P<3..2> NC_TBT_D2RP<3..2> NC_LVDS_IG_DDC_DATA LVDS_IG_DDC_DATA 18
92 17 PCIE_CLK100M_EXCARD_N TRUE NC_PCIE_CLK100M_EXCARD_N MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
TBT_D2R_N<3..2> NC_TBT_D2RN<3..2>
92 17 PCIE_CLK100M_EXCARD_P TRUE NC_PCIE_CLK100M_EXCARD_P MAKE_BASE=TRUE NO_TEST=TRUE NC_PCIE_FW_D2RN PCIE_FW_D2R_N 17
SH0924 TBT_R2D_C_P<3..2> NC_TBT_R2D_CP<3..2>
C SH0922
STDOFF-4.5OD2.15H-SM SH0930
STDOFF-4.5OD1.9H-SM
1
TBT_R2D_C_N<3..2>
MAKE_BASE=TRUE
NC_TBT_R2D_CN<3..2>
MAKE_BASE=TRUE
NO_TEST=TRUE NC_PCIE_FW_D2RP
NC_PCIE_FW_R2D_CN
PCIE_FW_D2R_P
PCIE_FW_R2D_C_N
17
17
C
STDOFF-4.5OD2.15H-SM NO_TEST=TRUE
1
1 NC_PCIE_FW_R2D_CP PCIE_FW_R2D_C_P 17
DPMUX TX & RX MAKE_BASE=TRUE NO_TEST=TRUE
17 TP_PCH_CLKOUT_DPN TRUE DPLL_REF_CLKN 11 89
MAKE_BASE=TRUE
17 TP_PCH_CLKOUT_DPP TRUE DPLL_REF_CLKP 11 89 82 DPMUX_UC_BOOT_TX DPMUX_UC_TX 82

SH0946 SH0945 82 DPMUX_UC_BOOT_RX DPMUX_UC_RX 82

STDOFF-4.9OD2.38H-SM-2 STDOFF-4.9OD2.38H-SM-SL-2.6X2NP-2 17 TP_PCH_GPIO64_CLKOUTFLEX0 TRUE NC_PCH_GPIO64_CLKOUTFLEX0
MAKE_BASE=TRUE
NC_SATA_ODD_D2R_N SATA_ODD_D2R_N 17 91
1 1 17 TP_PCH_GPIO65_CLKOUTFLEX1 TRUE NC_PCH_GPIO65_CLKOUTFLEX1
MAKE_BASE=TRUE NC_SATA_ODD_D2R_P SATA_ODD_D2R_P 17 91
17 TP_PCH_GPIO66_CLKOUTFLEX2 TRUE NC_PCH_GPIO66_CLKOUTFLEX2 SSD PCIE SIGNALS MAKE_BASE=TRUE
MAKE_BASE=TRUE
17 TP_PCH_GPIO67_CLKOUTFLEX3 TRUE NC_PCH_GPIO67_CLKOUTFLEX3 92 39 PCIE_SSD_D2R_P<1..0> =PEG_D2R_P<13..12> 10
MAKE_BASE=TRUE MAKE_BASE=TRUE NC_SATA_ODD_R2D_C_N SATA_ODD_R2D_C_N 17 91
MAKE_BASE=TRUE
92 39 PCIE_SSD_D2R_N<1..0> =PEG_D2R_N<13..12> 10
SD_PWR_EN_PCH ENET_LOW_PWR_PCH 20 24 25 MAKE_BASE=TRUE NC_SATA_ODD_R2D_C_P SATA_ODD_R2D_C_P 17 91
APN 806-2247 MAKE_BASE=TRUE MAKE_BASE=TRUE
92 39 PCIE_SSD_R2D_C_P<1..0> =PEG_R2D_C_P<13..12> 10
38 7 SD_PWR_EN ENET_LOW_PWR 25 MAKE_BASE=TRUE
BR0901 MAKE_BASE=TRUE
PCIE_SSD_R2D_C_N<1..0> =PEG_R2D_C_N<13..12>
1 1 1 MLB-MTG-BRKT-J5 92 39 10
TH TP_FW_PWR_EN FW_PWR_EN 25 MAKE_BASE=TRUE
SH0950 SH0952 SH0951 1
MAKE_BASE=TRUE
TP_PCIE_CLK100M_FW_P PCIE_CLK100M_FW_P
SM SM SM 17 92
MAKE_BASE=TRUE
TP_PCIE_CLK100M_FW_N PCIE_CLK100M_FW_N 17 92
SHLD-J5-USB SHLD-J5-CAN-FENCE-MDP-2 SHLD-J5-CAN-FENCE-MDP-1 MAKE_BASE=TRUE
NC_DP_IG_MLP<3..0> TP_DP_IG_B_MLP<3..0> 18
NC_DP_IG_MLN<3..0> TP_DP_IG_B_MLN<3..0> 18
UNUSED FDI SIGNALS MAKE_BASE=TRUE NO_TEST=TRUE
POGO PINS
SMT GND TEST PONTS NC_PCH_FDI_DATA_N<7..0> =FDI_DATA_N<7..0> 18 TBTBST:N
NC_PCH_FDI_DATA_P<7..0> =FDI_DATA_P<7..0> R0950
B SH0931 SH0932 SH0933 ZT0990 ZT0991 ZT0992
MAKE_BASE=TRUE
NC_PCH_FDI_FSYNC<1..0>
NO_TEST=TRUE
=FDI_FSYNC<1..0>
18
18
37 8 =PPVIN_SW_TBTBST 1
0
2 =PP15V_TBT_REG 8 37 B
2.1SM2.0MM-CIR 2.1SM2.0MM-CIR 2.1SM2.0MM-CIR MAKE_BASE=TRUE NO_TEST=TRUE 5%
POGO-2.3OD-5.5H-SM-LOW-FORCE POGO-2.3OD-5.5H-SM-LOW-FORCE POGO-2.3OD-5.5H-SM-LOW-FORCE SMT-PAD-NSP SMT-PAD-NSP SMT-PAD-NSP NC_PCH_FDI_LSYNC<1..0> =FDI_LSYNC<1..0> 18
1/8W
MF-LF
SM SM SM 1 1 1 MAKE_BASE=TRUE NO_TEST=TRUE 805
1 1 1
NC_CPU_FDI_DATA_N<7..0> FDI_DATA_N<7..0> 10 89
MAKE_BASE=TRUE NO_TEST=TRUE UNUSED USB SIGNALS
NC_CPU_FDI_DATA_P<7..0> FDI_DATA_P<7..0> 10 89 NC_USB3_EXTD_TX_P USB3_EXTD_TX_P 19
SH0937 ZT0993 MAKE_BASE=TRUE

NC_CPU_FDI_FSYNC<1..0>
NO_TEST=TRUE
FDI_FSYNC<1..0>
MAKE_BASE=TRUE
NC_USB3_EXTD_TX_N
NO_TEST=TRUE
USB3_EXTD_TX_N
2.1SM2.0MM-CIR 10 89 19
POGO-2.3OD-5.5H-SM-LOW-FORCE SMT-PAD-NSP MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
SM 1
SH0934 SH0935 SH0936 NC_CPU_FDI_LSYNC<1..0>
FDI_LSYNC<1..0> 10 89 NC_USB3_EXTD_RX_P
USB3_EXTD_RX_P 19
POGO-2.3OD-5.5H-SM-LOW-FORCE POGO-2.3OD-5.5H-SM-LOW-FORCE POGO-2.3OD-5.5H-SM-LOW-FORCE 1

NC_USB3_EXTD_RX_N USB3_EXTD_RX_N 19
SM SM SM MAKE_BASE=TRUE NO_TEST=TRUE
1 1 1 USB SIGNALS NC_USB_EXTD_EHCI_P USB_EXTD_EHCI_P 19
SH0960 91 34 USB_BT_P USBHUB_DN1_P 26

MAKE_BASE=TRUE
NC_USB_EXTD_EHCI_N
NO_TEST=TRUE
USB_EXTD_EHCI_N
2.8OD1.2ID-1.35H-SM MAKE_BASE=TRUE
MAKE_BASE=TRUE NO_TEST=TRUEI1187
19
91 34 USB_BT_N USBHUB_DN1_N 26
1 MAKE_BASE=TRUE NC_USB3_EXTC_TX_P USB3_EXTC_TX_P 19 91
91 49 USB_TPAD_P USBHUB_DN2_P 26
MAKE_BASE=TRUE NC_USB3_EXTC_TX_N USB3_EXTC_TX_N 19 91
USB_TPAD_N USBHUB_DN2_N
SH0940 SH0941 SH0944 SH0961 91 49
MAKE_BASE=TRUE
26
NC_USB3_EXTC_RX_P USB3_EXTC_RX_P 19 91
2.8OD1.2ID-1.35H-SM 2.8OD1.2ID-1.35H-SM 2.8OD1.2ID-1.35H-SM 2.8OD1.2ID-1.35H-SM MAKE_BASE=TRUE NO_TEST=TRUEI1190
91 41 USB_SMC_P USBHUB_DN3_P 26
MAKE_BASE=TRUE NC_USB3_EXTC_RX_N USB3_EXTC_RX_N 19 91
1 1 1 1 MAKE_BASE=TRUE NO_TEST=TRUEI1192
91 41 USB_SMC_N USBHUB_DN3_N 26
MAKE_BASE=TRUE NC_USB_EXTC_P USB_EXTC_P 19 91
PU_USBHUB_DN4P USBHUB_DN4_P 26
MAKE_BASE=TRUE NC_USB_EXTC_N USB_EXTC_N 19 91
Digital Ground PU_USBHUB_DN4N USBHUB_DN4_N 26

A 20 MLB_RAMCFG3
RAMCFG3:L
MAKE_BASE=TRUE
MLB_RAMCFG2 PAGE TITLE
SH0942 SH0943 20
RAMCFG2:L R09131 8 =PP5V_S0_AUDIO_XW

Signal Aliases
2.8OD1.2ID-1.35H-SM 2.8OD1.2ID-1.35H-SM 20 MLB_RAMCFG1 1K
1 1 RAMCFG1:L R09121 5%
1/20W
DRAWING NUMBER SIZE
20 MLB_RAMCFG0 1K MF XW0902
RAMCFG0:L R0911 1 5%
1/20W
201 2 SM
REVISION
1K MF 1 2 PP5V_S0_AUDIO_AMP_L
R09101 5%
1/20W
201 2 MIN_LINE_WIDTH=0.4MM
57 R
4.18.0
1K MF VOLTAGE=5V NOTICE OF PROPRIETARY PROPERTY: BRANCH
5% 201 2 XW0903
1/20W SM THE INFORMATION CONTAINED HEREIN IS THE
MF PROPRIETARY PROPERTY OF APPLE INC.
201 2 1 2 PP5V_S0_AUDIO_AMP_R 57 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
VOLTAGE=5V
9 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP1V05_S0_CPU_VCCIO 8 10 11 13 14 15
1
OMIT_TABLE
R1010
U1000 24.9
1%
IVY-BRIDGE 1/16W
MF-LF
BGA
402
2
89 18 DMI_S2N_N<0> N10 DMI_RX0* (1 OF 11) PEG_ICOMPI G2 89 CPU_PEG_COMP
IN
89 18 DMI_S2N_N<1> R10 DMI_RX1* PEG_ICOMPO H1
IN
89 18 DMI_S2N_N<2> R8 DMI_RX2* PEG_RCOMPO F3
IN
89 18 DMI_S2N_N<3> U10 DMI_RX3*
89 24 10 CPU_CFG<0> B57 (IPU) U1000 BB57
NC
IN
F23
89 24 10 CPU_CFG<1> D57 (IPU) IVY-BRIDGE BB43
NC
PEG_RX0* =PEG_D2R_N<0>
IN 9
B55 BGA BB25
CPU_CFG<2>
89 18 IN DMI_S2N_P<0> N8 DMI_RX0 PEG_RX1* H23 =PEG_D2R_N<1>
IN 9
89 24 10 (IPU)
NC
CPU_CFG<3> A54 (5 OF 11) BB17
T9 DMI_RX1 PEG_RX2* H21 SIGNAL_MODEL=EMPTY
89 24 10 (IPU)
RESERVED NC
D
89 18 DMI_S2N_P<1> =PEG_D2R_N<2> 9
IN IN A58 BB15
D 1 TP CPU_CFG<4> OMIT_TABLE
89 18 IN DMI_S2N_P<2> R6 DMI_RX2 PEG_RX3* H19 =PEG_D2R_N<3> IN 9
SM BEAD-PROBE BP1004
89 24 10 (IPU)
NC
CPU_CFG<5> D55 BB13
89 18 IN DMI_S2N_P<3> U8 DMI_RX3 PEG_RX4* J20 =PEG_D2R_N<4>
IN 9
89 24 10 (IPU)
NC
CPU_CFG<6> C56 BA48
PEG_RX5* G18 =PEG_D2R_N<5>
89 24 10 (IPU)
NC
DMI
IN 9
CPU_CFG<7> E54 BA16
89 18 OUT DMI_N2S_N<0> N4 DMI_TX0* PEG_RX6* K17 =PEG_D2R_N<6> IN 9
89 24 10 (IPU)
NC
CPU_CFG<8> J54 AY45
89 18 OUT DMI_N2S_N<1> R4 DMI_TX1* PEG_RX7* F15 =PEG_D2R_N<7>
IN 9
89 24 (IPU)
NC
CPU_CFG<9> G56 AY41
89 18 OUT DMI_N2S_N<2> P1 DMI_TX2* PEG_RX8* H15 =PEG_D2R_N<8>
IN 9
89 24 (IPU)
CFG NC
CPU_CFG<10> F55 AY17
89 18 OUT DMI_N2S_N<3> U6 DMI_TX3* PEG_RX9* H13 =PEG_D2R_N<9>
IN 9
89 24 (IPU)
NC
CPU_CFG<11> K55 AY15
PEG_RX10* H11 =PEG_D2R_N<10> IN 9
89 24 (IPU)
NC
CPU_CFG<12> F57 AY13
89 18 OUT DMI_N2S_P<0> N2 DMI_TX0 PEG_RX11* J12 =PEG_D2R_N<11>
IN 9
89 24 (IPU)
NC
CPU_CFG<13> E58 AW50
89 18 OUT DMI_N2S_P<1> R2 DMI_TX1 PEG_RX12* E8 =PEG_D2R_N<12>
IN 9
89 24 (IPU)
NC
CPU_CFG<14> H57 AW46
89 18 OUT DMI_N2S_P<2> P3 DMI_TX2 PEG_RX13* G10 =PEG_D2R_N<13> IN 9
89 24 (IPU)
NC
CPU_CFG<15> H55 AW42
89 18 OUT DMI_N2S_P<3> T5 DMI_TX3 PEG_RX14* J8 =PEG_D2R_N<14> IN 9
89 24 (IPU)
NC
CPU_CFG<16> D53 AW14
PEG_RX15* F7 =PEG_D2R_N<15> 9
89 24 10 (IPU)
NC
IN CPU_CFG<17> K57 AJ10
89 9 OUT FDI_DATA_N<0> V7 FDI0_TX0*
89 24 (IPU)
NC
AJ6
89 9 OUT FDI_DATA_N<1> W8 FDI0_TX1* PEG_RX0 G22 =PEG_D2R_P<0> IN 9
NC
G64 AH5
89 9 FDI_DATA_N<2> AA8 FDI0_TX2* PEG_RX1 K23 =PEG_D2R_P<1> 9 SIGNAL_MODEL=EMPTY NC NC
INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

OUT IN 1 TP BJ42 AD5
89 9 OUT FDI_DATA_N<3> AC10 FDI0_TX3* PEG_RX2 K21 =PEG_D2R_P<2>
IN 9 SM BEAD-PROBE BP1011 NC NC
1 TP BJ34 AC6
PEG_RX3 F19 =PEG_D2R_P<3>
IN 9 SM BEAD-PROBE BP1012 NC NC
BJ22 AC4
89 9 OUT FDI_DATA_N<4> U4 FDI1_TX0* PEG_RX4 K19 =PEG_D2R_P<4> IN 9 SIGNAL_MODEL=EMPTY NC NC
BH43 AA4
89 9 OUT FDI_DATA_N<5> W2 FDI1_TX1* PEG_RX5 H17 =PEG_D2R_P<5>
IN 9
NC NC
BH35 P7
89 9 FDI_DATA_N<6> V1 FDI1_TX2* PEG_RX6 K15 =PEG_D2R_P<6> 9
NC RSVD NC
OUT IN BH25 N6
89 9 OUT FDI_DATA_N<7> Y5 FDI1_TX3* PEG_RX7 G14 =PEG_D2R_P<7> IN 9
NC NC
PCI EXPRESS BASED INTERFACE SIGNALS

BH23 M9
PEG_RX8 J16 =PEG_D2R_P<8>
IN 9
NC NC
BH21 M5
89 9 FDI_DATA_P<0> W6 FDI0_TX0 PEG_RX9 K13 =PEG_D2R_P<9> 9 NOTE: NC NC
OUT IN BH19 L10
89 9 OUT FDI_DATA_P<1> W10 FDI0_TX1 PEG_RX10 F11 =PEG_D2R_P<10>
IN 9 Intel is investigating processor driven VREF_DQ generation.
NC NC
BG62 L6
89 9 OUT FDI_DATA_P<2> Y9 FDI0_TX2 PEG_RX11 K11 =PEG_D2R_P<11> IN 9
This connection is to support the same.
NC NC
BG34 L4
NC NC
C 89 9 OUT FDI_DATA_P<3> AA10 FDI0_TX3 PEG_RX12
PEG_RX13
F9
H9
=PEG_D2R_P<12>
=PEG_D2R_P<13>
IN
IN
9
9
NC
BG26
BG22
L2
K49
NC C
89 9 OUT FDI_DATA_P<4> U2 FDI1_TX0 PEG_RX14 H7 =PEG_D2R_P<14>
IN 9
NC NC
PPCPU_MEM_VREFDQ_B BG4 K47
89 9 OUT FDI_DATA_P<5> W4 FDI1_TX1 PEG_RX15 G6 =PEG_D2R_P<15>
IN 9
89 33 (DDR_VREF1) (THERMDA)
NC
MIN_LINE_WIDTH=0.3 mm BF63 K9
89 9 OUT FDI_DATA_P<6> V3 FDI1_TX2 NC NC
MIN_NECK_WIDTH=0.2 mm BF43 K7
89 9 FDI_DATA_P<7> AA6 FDI1_TX3 PEG_TX0* A22 =PEG_R2D_C_N<0> 9
NC NC
OUT OUT BF41 K5
B23
VOLTAGE=0.75V NC RSVD NC
PEG_TX1* =PEG_R2D_C_N<1> OUT 9
BF35 J50
89 9 IN FDI_FSYNC<0> AC8 FDI0_FSYNC PEG_TX2* C18 =PEG_R2D_C_N<2>
OUT 9
NC NC
BF25 J4
89 9 IN FDI_FSYNC<1> AA2 FDI1_FSYNC PEG_TX3* D21 =PEG_R2D_C_N<3>
OUT 9
NC NC
BF23 J2
PEG_TX4* B19 =PEG_R2D_C_N<4>
OUT 9
NC NC
BF21 H49
89 18 IN FDI_INT AD9 FDI_INT PEG_TX5* E20 =PEG_R2D_C_N<5>
OUT 9
NC NC
BF19 H47
PEG_TX6* A14 =PEG_R2D_C_N<6> 9
NC (THERMDC)
NC
OUT PPCPU_MEM_VREFDQ_A BF3 H5
89 9 IN FDI_LSYNC<1> AB3 FDI1_LSYNC PEG_TX7* D17 =PEG_R2D_C_N<7>
OUT 9
89 33 (DDR_VREF0)
NC
MIN_LINE_WIDTH=0.3 mm BE32 G52
89 9 IN FDI_LSYNC<0> AB7 FDI0_LSYNC PEG_TX8* B15 =PEG_R2D_C_N<8> OUT 9
NC NC
MIN_NECK_WIDTH=0.2 mm BE16 G48
PEG_TX9* E16 =PEG_R2D_C_N<9>
OUT 9
NC NC
VOLTAGE=0.75V BE6 G4
89 82 OUT DP_INT_IG_ML_N<0> AG2 EDP_TX0* PEG_TX10* D13 =PEG_R2D_C_N<10>
OUT 9
NC NC
BD33 F5
89 82 OUT DP_INT_IG_ML_N<1> AF1 EDP_TX1* PEG_TX11* A10 =PEG_R2D_C_N<11>
OUT 9
NC NC
BD29 D49
89 82 OUT DP_INT_IG_ML_N<2> AE6 EDP_TX2* PEG_TX12* B11 =PEG_R2D_C_N<12>
OUT 9
NC NC
BD19 D25
89 82 OUT DP_INT_IG_ML_N<3> AG6 EDP_TX3* PEG_TX13* D9 =PEG_R2D_C_N<13>
OUT 9
NC NC
BD15 D3
NC NC
EMBEDDED DISPLAY PORT
PEG_TX14* B7 =PEG_R2D_C_N<14> 9
OUT BD13 C52
89 82 OUT DP_INT_IG_ML_P<0> AG4 EDP_TX0 PEG_TX15* E12 =PEG_R2D_C_N<15> OUT 9
NC NC
15 14 13 11 10 8 =PP1V05_S0_CPU_VCCIO BC42 C24
89 82 OUT DP_INT_IG_ML_P<1> AF3 EDP_TX1 NC NC
BC30 C4
89 82 OUT DP_INT_IG_ML_P<2> AF7 EDP_TX2 PEG_TX0 C22 =PEG_R2D_C_P<0>
OUT 9
NC NC
BC14 B53
1 DP_INT_IG_ML_P<3> AG8 EDP_TX3 PEG_TX1 D23 =PEG_R2D_C_P<1> NC NC
R1030 89 82 OUT OUT 9
B25
OMIT_TABLE 24.9 PEG_TX2 A18 =PEG_R2D_C_P<2>
OUT 9
NC
1 1%
R1031 AE4 B21
1/16W 89 82 BI DP_INT_IG_AUX_P EDP_AUX PEG_TX3 =PEG_R2D_C_P<3>
OUT 9
1K MF-LF
AE2 EDP_AUX* PEG_TX4 D19
B
DP_INT_IG_AUX_N =PEG_R2D_C_P<4>
B
5% 402 89 82 BI OUT 9
2
1/16W
PEG_TX5 F21 =PEG_R2D_C_P<5> 9
MF-LF PLACE_NEAR=U1000.AB1:12.7mm OUT
402
2 89 CPU_EDP_COMP AB1 EDP_ICOMPO PEG_TX6 C14 =PEG_R2D_C_P<6> 9
OUT
AC2 EDP_COMPIO PEG_TX7 B17 =PEG_R2D_C_P<7> 9
OUT
PEG_TX8 D15 =PEG_R2D_C_P<8> 9
OUT
DP_INT_IG_HPD_L AE8 EDP_HPD* PEG_TX9 F17 =PEG_R2D_C_P<9> 9
OUT
PEG_TX10 B13 =PEG_R2D_C_P<10> 9
OUT
PEG_TX11 C10 =PEG_R2D_C_P<11> 9
OUT
D PEG_TX12 D11 =PEG_R2D_C_P<12> 9
3 OUT
PEG_TX13 B9 =PEG_R2D_C_P<13>
Q1031 OUT 9
DP_INT_IG_HPD 1 PEG_TX14 D7 =PEG_R2D_C_P<14>

82 IN 2N7002TXG OUT 9
G SOT-523-3
EDP:YES PEG_TX15 F13 =PEG_R2D_C_P<15> 9
S 2 OUT
89 24 10 CPU_CFG<7>
89 24 10 CPU_CFG<6> 89 24 10 CPU_CFG<16> PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
89 24 10 CPU_CFG<5> 89 24 10 CPU_CFG<3>
116S0066 1 RES,MTL FILM,1/16W,1K,0402,SMD,LF R1031 EDP:YES
89 24 10 CPU_CFG<4> 89 24 10 CPU_CFG<1>
89 24 10 CPU_CFG<2> 89 24 10 CPU_CFG<0> 116S0090 1 RES,MTL FILM,1/16W,10K,0402,SMD,LF R1031 EDP:NO

EDP:YES
NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1 1 1 1 1 1 1 1 1
R1042 R1044 R1045 R1046 R1047 R1040 R1041 R1043 R1049
1K 1K 1K 1K 1K 1K 1K 1K 1K
5% 5% 5% 5% 5% 5% 5% 5% 5%
A 1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
1/16W
MF-LF
402
2
A
PAGE TITLE
CPU DMI/PEG/FDI/RSVD
CPU_CFG<4> should be pulled down to enable EDP These can be Placed close to J2500 and Only for debug access DRAWING NUMBER SIZE

REVISION
CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
R
4.18.0
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED PROPRIETARY PROPERTY OF APPLE INC.
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
10 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
15 14 13 11 10 8 =PP1V05_S0_CPU_VCCIO
15 14 13 11 10 8 =PP1V05_S0_CPU_VCCIO
NOSTUFF NOSTUFF NOSTUFF

1 1 1
R1100 R1104 R1102
1 1K 51 1K
R1101 OMIT_TABLE
68
5%
1/20W
5%
1/16W
5%
1/20W
U1000
5% MF MF-LF MF IVY-BRIDGE
1/16W 201 402 201
2 2 2 BGA DPLL_REF_CLK AJ4 DPLL_REF_CLKP 9 89
MF-LF
IN
2
402
B59 PROC_DETECT* (2 OF 11) DPLL_REF_CLK* AJ2 DPLL_REF_CLKN
NC IN 9 89
89 20 CPU_PROC_SEL_L AH9 PROC_SELECT* BCLK_ITP K63 ITPCPU_CLK100M_P 17 89

OUT IN
CLOCKS
BCLK_ITP* K65 ITPCPU_CLK100M_N
R1103 17 89
C
IN
C 89 65 42 41 BI CPU_PROCHOT_L 2
56
1
89 41 OUT CPU_CATERR_L H53 CATERR*
BCLK D5 DMI_CLK100M_CPU_P 17 89
5%
IN
1/16W CPU_PECI F53 PECI BCLK* C6 DMI_CLK100M_CPU_N
THERMAL
89 42 20 BI IN 17 89
MF-LF
15 14 13 11 10 8 =PP1V05_S0_CPU_VCCIO 402
CPU_PROCHOT_R_L H51 PROCHOT* (IPU) PRDY* J62 XDP_CPU_PRDY_L 24 89

1 OUT
R1126 (IPU) PREQ* H65 XDP_CPU_PREQ_L 24 89
IN
75
1% 89 42 20 PM_THRMTRIP_L F51 THERMTRIP*
OUT
1/16W
MF-LF (IPD) TCK J58 XDP_CPU_TCK 24 89
IN
402
2 R1125 (IPU) TMS H59 XDP_CPU_TMS
IN 24 89
43.2
PWR MGMT
K51 H63
JTAG & BPM

25 24 IN CPU_RESET_L 2 1 PLT_RESET_LS1V1_L RESET* (IPU) TRST* XDP_CPU_TRST_L
IN 24 89
1%
1/16W
MF-LF 89 18 PM_SYNC K53 PM_SYNC (IPU) TDI K61 XDP_CPU_TDI 24 89
402
IN IN
TDO K59 XDP_CPU_TDO 24 89
OUT
89 24 20 CPU_PWRGD C60 UNCOREPWRGOOD
IN
DBR* H61 XDP_DBRESET_L 24 25 89
OUT
PM_MEM_PWRGD_R AY25 SM_DRAMPWROK
(IPU) BPM0* C62 XDP_BPM_L<0> 24 89
BI
27 =MEM_RESET_L BE24 SM_DRAMRST* (IPU) BPM1* D61 XDP_BPM_L<1> 24 89
DDR3 MISC
OUT BI
(IPU) BPM2* E62 XDP_BPM_L<2> 24 89
27 16 14 11 8 =PP1V5_S3_CPU_VCCDDR BI
PLACE_NEAR=R1121.2:1mm CPU_DDR_VREF BJ44 SM_VREF (IPU) BPM3* F63 XDP_BPM_L<3> 24 89
BI
BPM4* D59 XDP_BPM_L<4>
R1120 1
(IPU) BI 24 89
89 CPU_SM_RCOMP<0> BJ46 SM_RCOMP0 (IPU) BPM5* F61 XDP_BPM_L<5> 24 89

200 BI
1% BG46 F59
1/16W
89 CPU_SM_RCOMP<1> SM_RCOMP1 (IPU) BPM6* XDP_BPM_L<6>
BI 24 89
MF-LF BF45 G60
402 R1121 89 CPU_SM_RCOMP<2> SM_RCOMP2 (IPU) BPM7* XDP_BPM_L<7> BI 24 89
2
130
89 27 18 PM_MEM_PWRGD 2 1
IN
1 1 1
B B
1%
R1120 and R1121 are Intel recommended values 1/16W R1112 R1113 R1114
MF-LF 140 25.5 200 1
402 R1111
1% 1% 1% PLACE_NEAR=U1000.BF45:12.7mm
PLACE_NEAR=U1000.AY25:51.562mm 1/16W 1/16W 1/16W 10K
MF-LF MF-LF MF-LF 5% PLACE_NEAR=U1800.AY11:157mm
402 402 402 1/16W
2 2 2
MF-LF
402
27 16 14 11 8 =PP1V5_S3_CPU_VCCDDR 2
PLACE_NEAR=U1000.BG46:12.7mm
R1130 1
1K PLACE_NEAR=U1000.BJ46:12.7mm
PLACE_NEAR=U1000.BJ44:2.54mm 1%
1/16W
MF-LF
402 2
R11311 1
C1130
1K 0.1UF
PLACE_NEAR=U1000.BJ44:2.54mm 1% 10%
1/16W 16V
MF-LF 2 X7R-CERM
402 2 0402
PLACE_NEAR=U1000.BJ44:2.54mm
A A
PAGE TITLE
CPU CLOCK/MISC/JTAG
DRAWING NUMBER SIZE

REVISION
R
4.18.0
11 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
90 29 28 BI MEM_A_DQ<0> AL6 SA_DQ0 U1000 SA_CLK0 BB31 MEM_A_CLK_P<0>

OUT 28 32 90 90 31 30 BI MEM_B_DQ<0> AL4 SB_DQ0 U1000 SB_CLK0 BF33 MEM_B_CLK_P<0>
OUT 30 32 90
90 29 28 BI MEM_A_DQ<1> AL8 SA_DQ1 IVY-BRIDGE SA_CLK0* BA32 MEM_A_CLK_N<0> OUT 28 32 90 90 31 30 BI MEM_B_DQ<1> AK3 SB_DQ1 IVY-BRIDGE SB_CLK0* BH33 MEM_B_CLK_N<0> OUT 30 32 90
90 29 28 MEM_A_DQ<2> AP7 SA_DQ2 BGA 90 31 30 MEM_B_DQ<2> AP3 SB_DQ2 BGA

BI BI
90 29 28 MEM_A_DQ<3> AM5 SA_DQ3 (3 OF 11) SA_CKE0 BC18 MEM_A_CKE<0> 28 32 90 90 31 30 MEM_B_DQ<3> AR2 SB_DQ3 (4 OF 11) SB_CKE0 BD25 MEM_B_CKE<0> 30 32 90
BI OUT BI OUT
D 90 29 28
90 29 28
BI
BI
MEM_A_DQ<4>
MEM_A_DQ<5>
AK7
AL10
SA_DQ4
SA_DQ5
OMIT_TABLE
SA_CLK1 AW34 MEM_A_CLK_P<1>

OUT 29 32 90
90 31 30
90 31 30
BI
BI
MEM_B_DQ<4>
MEM_B_DQ<5>
AL2
AK1
SB_DQ4
SB_DQ5
OMIT_TABLE
SB_CLK1 BF37 MEM_B_CLK_P<1>

OUT 31 32 90
D
90 29 28 MEM_A_DQ<6> AN10 SA_DQ6 SA_CLK1* AY33 MEM_A_CLK_N<1> 29 32 90 90 31 30 MEM_B_DQ<6> AP1 SB_DQ6 SB_CLK1* BH37 MEM_B_CLK_N<1> 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<7> AM9 SA_DQ7 90 31 30 MEM_B_DQ<7> AR4 SB_DQ7
BI BI
90 29 28 MEM_A_DQ<8> AR10 SA_DQ8 SA_CKE1 BD17 MEM_A_CKE<1> 29 32 90 90 31 30 MEM_B_DQ<8> AV3 SB_DQ8 SB_CKE1 BJ26 MEM_B_CKE<1> 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<9> AR8 SA_DQ9 90 31 30 MEM_B_DQ<9> AU4 SB_DQ9
BI BI
90 29 28 MEM_A_DQ<10> AV7 SA_DQ10 SA_CS0* BD41 MEM_A_CS_L<0> 28 32 90 90 31 30 MEM_B_DQ<10> BA4 SB_DQ10 SB_CS0* BE40 MEM_B_CS_L<0> 30 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<11> AY5 SA_DQ11 SA_CS1* BD45 MEM_A_CS_L<1> 29 32 90 90 31 30 MEM_B_DQ<11> BB1 SB_DQ11 SB_CS1* BH41 MEM_B_CS_L<1> 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<12> AT5 SA_DQ12 90 31 30 MEM_B_DQ<12> AV1 SB_DQ12
BI BI
90 29 28 MEM_A_DQ<13> AR6 SA_DQ13 SA_ODT0 BB41 MEM_A_ODT<0> 28 32 90 90 31 30 MEM_B_DQ<13> AU2 SB_DQ13 SB_ODT0 BG42 MEM_B_ODT<0> 30 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<14> AW6 SA_DQ14 SA_ODT1 BC46 MEM_A_ODT<1> 29 32 90 90 31 30 MEM_B_DQ<14> BA2 SB_DQ14 SB_ODT1 BH45 MEM_B_ODT<1> 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<15> AT9 SA_DQ15 90 31 30 MEM_B_DQ<15> BB3 SB_DQ15
BI BI
90 29 28 MEM_A_DQ<16> BA6 SA_DQ16 SA_DQS0* AN8 MEM_A_DQS_N<0> 28 29 90 90 31 30 MEM_B_DQ<16> BC2 SB_DQ16 SB_DQS0* AN4 MEM_B_DQS_N<0> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<17> BA8 SA_DQ17 SA_DQS1* AU6 MEM_A_DQS_N<1> 28 29 90 90 31 30 MEM_B_DQ<17> BF7 SB_DQ17 SB_DQS1* AW2 MEM_B_DQS_N<1> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<18> BG6 SA_DQ18 SA_DQS2* BC6 MEM_A_DQS_N<2> 28 29 90 90 31 30 MEM_B_DQ<18> BF11 SB_DQ18 SB_DQS2* BH9 MEM_B_DQS_N<2> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<19> AY9 SA_DQ19 SA_DQS3* BD9 MEM_A_DQS_N<3> 28 29 90 90 31 30 MEM_B_DQ<19> BJ10 SB_DQ19 SB_DQS3* BF15 MEM_B_DQS_N<3> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<20> AW8 SA_DQ20 SA_DQS4* BC50 MEM_A_DQS_N<4> 28 29 90 90 31 30 MEM_B_DQ<20> BC4 SB_DQ20 SB_DQS4* BF51 MEM_B_DQS_N<4> 30 31 90
BI BI BI BI
MEMORY CHANNEL A
90 29 28 MEM_A_DQ<21> BB7 SA_DQ21 SA_DQS5* BB55 MEM_A_DQS_N<5> 28 29 90 90 31 30 MEM_B_DQ<21> BH7 SB_DQ21 SB_DQS5* BH57 MEM_B_DQS_N<5> 30 31 90
BI BI BI BI
MEM_A_DQ<22> BC8 SA_DQ22 SA_DQS6* BD59 MEM_A_DQS_N<6> MEM_B_DQ<22> BH11 SB_DQ22 SB_DQS6* AY63 MEM_B_DQS_N<6>
MEMORY CHANNEL B
90 29 28 BI BI 28 29 90 90 31 30 BI BI 30 31 90
90 29 28 MEM_A_DQ<23> BE4 SA_DQ23 SA_DQS7* AU60 MEM_A_DQS_N<7> 28 29 90 90 31 30 MEM_B_DQ<23> BG10 SB_DQ23 SB_DQS7* AN62 MEM_B_DQS_N<7> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<24> AW12 SA_DQ24 90 31 30 MEM_B_DQ<24> BJ14 SB_DQ24
BI BI
90 29 28 MEM_A_DQ<25> AV11 SA_DQ25 SA_DQS0 AN6 MEM_A_DQS_P<0> 28 29 90 90 31 30 MEM_B_DQ<25> BG14 SB_DQ25 SB_DQS0 AN2 MEM_B_DQS_P<0> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<26> BB11 SA_DQ26 SA_DQS1 AU8 MEM_A_DQS_P<1> 28 29 90 90 31 30 MEM_B_DQ<26> BF17 SB_DQ26 SB_DQS1 AW4 MEM_B_DQS_P<1> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<27> BA12 SA_DQ27 SA_DQS2 BD5 MEM_A_DQS_P<2> 28 29 90 90 31 30 MEM_B_DQ<27> BJ18 SB_DQ27 SB_DQS2 BF9 MEM_B_DQS_P<2> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<28> BE8 SA_DQ28 SA_DQS3 BC10 MEM_A_DQS_P<3> 28 29 90 90 31 30 MEM_B_DQ<28> BF13 SB_DQ28 SB_DQS3 BH15 MEM_B_DQS_P<3> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<29> BA10 SA_DQ29 SA_DQS4 BB51 MEM_A_DQS_P<4> 28 29 90 90 31 30 MEM_B_DQ<29> BH13 SB_DQ29 SB_DQS4 BH51 MEM_B_DQS_P<4> 30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<30> BD11 SA_DQ30 SA_DQS5 BD55 MEM_A_DQS_P<5> 28 29 90 90 31 30 MEM_B_DQ<30> BH17 SB_DQ30 SB_DQS5 BF57 MEM_B_DQS_P<5> 30 31 90
C
BI BI BI BI
C 90 29 28
90 29 28
BI MEM_A_DQ<31>
MEM_A_DQ<32>
BE12
BB49
SA_DQ31
SA_DQ32
SA_DQS6
SA_DQS7
BD61
AV61
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
BI 28 29 90
28 29 90
90 31 30
90 31 30
BI MEM_B_DQ<31>
MEM_B_DQ<32>
BG18
BH49
SB_DQ31
SB_DQ32
SB_DQS6
SB_DQS7
AY65
AN64
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>
BI 30 31 90
30 31 90
BI BI BI BI
90 29 28 MEM_A_DQ<33> AY49 SA_DQ33 90 31 30 MEM_B_DQ<33> BF47 SB_DQ33
BI BI
90 29 28 MEM_A_DQ<34> BE52 SA_DQ34 SA_MA0 BD27 MEM_A_A<0> 28 29 32 90 90 31 30 MEM_B_DQ<34> BH53 SB_DQ34 SB_MA0 BF31 MEM_B_A<0> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<35> BD51 SA_DQ35 SA_MA1 BA28 MEM_A_A<1> 28 29 32 90 90 31 30 MEM_B_DQ<35> BG50 SB_DQ35 SB_MA1 BH31 MEM_B_A<1> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<36> BD49 SA_DQ36 SA_MA2 BB27 MEM_A_A<2> 28 29 32 90 90 31 30 MEM_B_DQ<36> BF49 SB_DQ36 SB_MA2 BB37 MEM_B_A<2> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<37> BE48 SA_DQ37 SA_MA3 AW26 MEM_A_A<3> 28 29 32 90 90 31 30 MEM_B_DQ<37> BH47 SB_DQ37 SB_MA3 BC34 MEM_B_A<3> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<38> BA52 SA_DQ38 SA_MA4 BB23 MEM_A_A<4> 28 29 32 90 90 31 30 MEM_B_DQ<38> BF53 SB_DQ38 SB_MA4 BF27 MEM_B_A<4> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<39> AY51 SA_DQ39 SA_MA5 BA24 MEM_A_A<5> 28 29 32 90 90 31 30 MEM_B_DQ<39> BJ50 SB_DQ39 SB_MA5 BB33 MEM_B_A<5> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<40> BC54 SA_DQ40 SA_MA6 AY21 MEM_A_A<6> 28 29 32 90 90 31 30 MEM_B_DQ<40> BF55 SB_DQ40 SB_MA6 BH27 MEM_B_A<6> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<41> AY53 SA_DQ41 SA_MA7 BD21 MEM_A_A<7> 28 29 32 90 90 31 30 MEM_B_DQ<41> BH55 SB_DQ41 SB_MA7 BG30 MEM_B_A<7> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<42> AW54 SA_DQ42 SA_MA8 BC22 MEM_A_A<8> 28 29 32 90 90 31 30 MEM_B_DQ<42> BJ58 SB_DQ42 SB_MA8 BH29 MEM_B_A<8> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<43> AY55 SA_DQ43 SA_MA9 BB21 MEM_A_A<9> 28 29 32 90 90 31 30 MEM_B_DQ<43> BH59 SB_DQ43 SB_MA9 BF29 MEM_B_A<9> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<44> BD53 SA_DQ44 SA_MA10 AW38 MEM_A_A<10> 28 29 32 90 90 31 30 MEM_B_DQ<44> BJ54 SB_DQ44 SB_MA10 AY37 MEM_B_A<10> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<45> BB53 SA_DQ45 SA_MA11 AW22 MEM_A_A<11> 28 29 32 90 90 31 30 MEM_B_DQ<45> BG54 SB_DQ45 SB_MA11 BJ30 MEM_B_A<11> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<46> BE56 SA_DQ46 SA_MA12 BA20 MEM_A_A<12> 28 29 32 90 90 31 30 MEM_B_DQ<46> BG58 SB_DQ46 SB_MA12 AW30 MEM_B_A<12> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<47> BA56 SA_DQ47 SA_MA13 BB45 MEM_A_A<13> 28 29 32 90 90 31 30 MEM_B_DQ<47> BF59 SB_DQ47 SB_MA13 BA40 MEM_B_A<13> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<48> BD57 SA_DQ48 SA_MA14 BE20 MEM_A_A<14> 28 29 32 90 90 31 30 MEM_B_DQ<48> BA64 SB_DQ48 SB_MA14 BB29 MEM_B_A<14> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<49> BF61 SA_DQ49 SA_MA15 AW18 MEM_A_A<15> 28 29 32 90 90 31 30 MEM_B_DQ<49> BC62 SB_DQ49 SB_MA15 BE28 MEM_B_A<15> 30 31 32 90
BI OUT BI OUT
90 29 28 MEM_A_DQ<50> BA60 SA_DQ50 90 31 30 MEM_B_DQ<50> AU62 SB_DQ50
BI BI
90 29 28 MEM_A_DQ<51> BB61 SA_DQ51 90 31 30 MEM_B_DQ<51> AW64 SB_DQ51
BI BI
90 29 28 MEM_A_DQ<52> BE60 SA_DQ52 90 31 30 MEM_B_DQ<52> BA62 SB_DQ52
BI BI
90 29 28 MEM_A_DQ<53> BD63 SA_DQ53 90 31 30 MEM_B_DQ<53> BC64 SB_DQ53
BI BI
90 29 28 MEM_A_DQ<54> BB59 SA_DQ54 90 31 30 MEM_B_DQ<54> AU64 SB_DQ54
BI BI
90 29 28 MEM_A_DQ<55> BC58 SA_DQ55 90 31 30 MEM_B_DQ<55> AW62 SB_DQ55
BI BI
90 29 28 MEM_A_DQ<56> AW58 SA_DQ56 90 31 30 MEM_B_DQ<56> AR64 SB_DQ56
BI BI
B 90 29 28
90 29 28
BI
BI
MEM_A_DQ<57>
MEM_A_DQ<58>
AY59
AL60
SA_DQ57
SA_DQ58
90 31 30
90 31 30
BI
BI
MEM_B_DQ<57>
MEM_B_DQ<58>
AT65
AL64
SB_DQ57
SB_DQ58
B
90 29 28 MEM_A_DQ<59> AP61 SA_DQ59 90 31 30 MEM_B_DQ<59> AM65 SB_DQ59
BI BI
90 29 28 MEM_A_DQ<60> AW60 SA_DQ60 90 31 30 MEM_B_DQ<60> AR62 SB_DQ60
BI BI
90 29 28 MEM_A_DQ<61> AY57 SA_DQ61 90 31 30 MEM_B_DQ<61> AT63 SB_DQ61
BI BI
90 29 28 MEM_A_DQ<62> AN60 SA_DQ62 90 31 30 MEM_B_DQ<62> AL62 SB_DQ62
BI BI
90 29 28 MEM_A_DQ<63> AR60 SA_DQ63 90 31 30 MEM_B_DQ<63> AM63 SB_DQ63
BI BI
90 32 29 28 MEM_A_BA<0> BA36 SA_BS0 90 32 31 30 MEM_B_BA<0> BJ38 SB_BS0

OUT OUT
90 32 29 28 MEM_A_BA<1> BC38 SA_BS1 90 32 31 30 MEM_B_BA<1> BD37 SB_BS1
OUT OUT
90 32 29 28 MEM_A_BA<2> BB19 SA_BS2 90 32 31 30 MEM_B_BA<2> AY29 SB_BS2
OUT OUT
90 32 29 28 MEM_A_CAS_L BE44 SA_CAS* 90 32 31 30 MEM_B_CAS_L BH39 SB_CAS*

OUT OUT
90 32 29 28 MEM_A_RAS_L BE36 SA_RAS* 90 32 31 30 MEM_B_RAS_L BG38 SB_RAS*
OUT OUT
90 32 29 28 MEM_A_WE_L BA44 SA_WE* 90 32 31 30 MEM_B_WE_L BF39 SB_WE*
OUT OUT
A SYNC_DATE=01/13/2012 A
PAGE TITLE
CPU DDR3 INTERFACES

DRAWING NUMBER SIZE

REVISION
R
4.18.0
12 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
=PP3V3_S0_CPU_VCCIO_SEL 8 98 45 15 13 8 =PPVCORE_S0_CPU
=PPVCORE_S0_CPU 8 13 15 45 98
For Future Compatibility
1
R1320 R46 U1000 H35
10K
5%
R42 IVY-BRIDGE H31
1/16W
R40 BGA H29
MF-LF
=PPVCCSA_S0_CPU
=PP1V05_S0_CPU_VCCIO 8 10 11 13 14 15
16 13 8 402
2 R36 (6 OF 11) H25
R34
CORE POWER G44
OMIT_TABLE
PLACE_NEAR=R1310.1:2.54mm =PP1V05_S0_CPU_VCCIO 8 10 11 13 14 15
1
W17 U1000 VCCIO_SEL AJ8 CPU_VCCIO_SEL R29 G40
R1300 1 W15 IVY-BRIDGE R27 G38
75 R1302
130 W12 BGA AV23 R23 G34
1% PLACE_NEAR=U1000.A50:2.54mm =PP1V5_S3_CPU_VCCDQ 8 16
1/16W
MF-LF
1%
1/16W
U17 (9 OF 11) AT23 R21 G32
2
402 MF-LF OMIT_TABLE VCCDQ
U15 AP23 N45 G28
R1312 2
402
89 65 CPU_VIDSOUT 402 1/16W 0 1 2 5% MF-LF CPU_VIDSOUT_R U12 AL23 N43 G26

BI
T16 N39 F45
R1311
89 65 CPU_VIDSCLK 402 1/16W 0 1 2 5% MF-LF CPU_VIDSCLK_R T14 AK65 =PP1V8_S0_CPU_VCCPLL_R 8 15 N37 F43
OUT
T11 AK63 N33 F41
R1310 VCCPLL
89 65 CPU_VIDALERT_L 402 1/16W 1 2 5% MF-LF CPU_VIDALERT_L_R N18 AK61 N30 F37
IN
N16
VCCSA N26 F35
43 PLACE_NEAR=U1000.B51:38mm
N14 AV21 =PP1V05_S0_CPU_VCCPQE 8 15
N24 F31
M17 AT21 N20 F29
M15
VCCPQE AP21 M46 F25
=PPVCORE_S0_CPU 8 13 15 45 98
C =PP1V05_S0_CPU_VCCIO 8 10 11 13 14 15
=PPVCORE_S0_CPU 8 13 15 45 98
M12
M11
AL21 M42
M40
E44
E40
C
=PPVCORE_S0_CPU_VCCAXG 8 13 14 =PPVCORE_S0_CPU_VCCAXG 8 13 14 16
16 L18 BJ60 M36 E38
L14 BJ6 M34 E34

PLACE_SIDE=BOTTOM
BH61 M29 E32
PLACE_SIDE=BOTTOM =PPVCCSA_S0_CPU 8 13
PLACE_SIDE=BOTTOM 16 A50 VIDSOUT BH5 M27 E28
PLACE_NEAR=U1000.AW10:50.8mm
NOSTUFF NOSTUFF D51 VIDSCLK BE64 M23 E26
1 1 1 1 1 1 B51 BE2 M21 D45
R1360 R1362 R1366 R1364 R1370 R1368 VIDALERT*
PLACE_NEAR=U1000.B47:50.8mm 100 100 100 49.9 49.9 100 BD65 L44 VCC VCC D43
5% 1% 1% NOSTUFF NOSTUFF 1% 1% 1%
PLACE_SIDE=BOTTOM 89 62 CPU_VCCSA_VID<0> AE10 VCCSA_VID0 BD1 L40 D41
1/16W 1/16W 1/16W 1/20W 1/20W 1/16W
OUT
MF-LF MF-LF MF-LF MF MF MF-LF
89 62 CPU_VCCSA_VID<1> AG10 VCCSA_VID1 F65 L38 D37
402
2 2
402
2
402 201
2 2
201
2
402 OUT
PLACE_SIDE=BOTTOM
PLACE_NEAR=U1000.F49:50.8mm
VSS_NCTF F1 L34 D35
89 65 CPU_VCCSENSE_P B47 VCC_SENSE E64 L32 D31

OUT
89 65 CPU_VCCSENSE_N A46 VSS_SENSE E2 L28 D29
OUT
B61 L26 C44
89 65 CPU_AXG_SENSE_P F49 VAXG_SENSE B5 L22 C40

OUT
89 65 CPU_AXG_SENSE_N E50 VSSAXG_SENSE A60 K45 C38
OUT
A6 K43 C34
89 67 CPU_VCCIOSENSE_P AW10 VCCIO_SENSE K41 C32

OUT
89 67 CPU_VCCIOSENSE_N AU10 VSS_SENSE_VCCIO DC_TEST_A4 A4 TP_DC_TEST_A4 K37 C28
OUT
PLACE_NEAR=U1000.E50:50.8mm DC_TEST_A62 A62 TP_DC_TEST_A62 K35 C26
PLACE_SIDE=BOTTOM TP_CPU_VDDQSENSEP AY19 VDDQ_SENSE DC_TEST_A64 A64 DC_TEST_B63_A64 K31 B45

1
R1367 TP_CPU_VDDQSENSEN AW20 VSS_SENSE_VDDQ DC_TEST_B3 B3 DC_TEST_B3_C2 K29 B43
100
1% DC_TEST_B63 B63 K25 B41
1/16W
89 62 CPU_VCCSASENSE K3 VCCSA_SENSE DC_TEST_B65 B65 DC_TEST_B65_C64 J44 B37
MF-LF OUT
402
2 BF1 J40 B35
DC_TEST_BF1 TP_DC_TEST_BF1
B
NOSTUFF
TP_CPU_DIE_SENSE F47 VCC_DIE_SENSE DC_TEST_BF65
DC_TEST_BG2
BF65
BG2
TP_DC_TEST_BF65
DC_TEST_BH1_BG2
J38
J34
B31
B29
B
CPU_VCC_VALSENSE_P D47 VCC_VAL_SENSE DC_TEST_BG64 BG64 DC_TEST_BG64_BH65 J32 A44
CPU_VCC_VALSENSE_N C48 VSS_VAL_SENSE DC_TEST_BH1 BH1 J28 A40
DC_TEST_BH3 BH3 DC_TEST_BH3_BJ2 J26 A38
CPU_AXG_VALSENSE_P B49 VAXG_VAL_SENSE DC_TEST_BH63 BH63 DC_TEST_BJ64_BH63 H45 A34
CPU_AXG_VALSENSE_N A48 VSSAXG_VAL_SENSE DC_TEST_BH65 BH65 H43 A32
PLACE_NEAR=U1000.A46:50.8mm PLACE_SIDE=BOTTOM DC_TEST_BJ2 BJ2 H41 A28

PLACE_NEAR=U1000.AU10:50.8mm
PLACE_SIDE=BOTTOM DC_TEST_BJ4 BJ4 TP_DC_TEST_BJ4 H37 A26
1 1
R1361 R1363 DC_TEST_BJ62 BJ62 TP_DC_TEST_BJ62
100 100 PLACE_SIDE=BOTTOM
NOSTUFF 1 1
DC_TEST_BJ64 BJ64
5%
1/16W
1%
1/16W
R1314 R1313
MF-LF MF-LF 10K 10K DC_TEST_C2 C2
1
402
2 2
402
R1365 1
5% 5%
DC_TEST_C64 C64
49.9
R1371
PLACE_SIDE=BOTTOM
1/16W
MF-LF
1/16W
MF-LF
NOSTUFF 1% 49.9 402 402 DC_TEST_D1 D1 TP_DC_TEST_D1
2 2
1/20W 1% NOSTUFF
MF 1/20W DC_TEST_D65 D65 TP_DC_TEST_D65
201 MF
2
201
2
NOTE: Intel validation sense lines per doc 439028 rev1.0

HR_PPDG sections 6.2.1 and 6.3.1.
PAGE TITLE
CPU POWER
DRAWING NUMBER SIZE

REVISION
R
4.18.0
13 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BJ56 U1000 AW16 AG12 U1000 L20
BJ52 IVY-BRIDGE AV65 AF65 IVY-BRIDGE L16
BJ48 BGA AV63 AF63 BGA L12
BJ40 (10 OF 11) AV59 AF61 (11 OF 11) L8

OMIT_TABLE
BJ32 AV57 AF11 OMIT_TABLE K39
BJ24 AV50 AF9 K33
BJ20 AV44 AF5 K27
D
BJ16
BJ12
AV38
AV31
AE57
AD16
K1
J64
D
BJ8 AV25 AD14 J60 =PPVCORE_S0_CPU_VCCAXG =PP1V5_S3_CPU_VCCDDR
16 13 8 8 11 16 27
BG60 AV19 AD7 J56
BG56 AV9 AD3 J52 AH65 U1000 BJ36
BG52 AV5 AD1 J48 AH63 IVY-BRIDGE BJ28

BG48 AU54 AC64 J46 AH61 BGA BG40
BG44 AU47 AC62 J42 AH58 (8 OF 11) BG32

=PP1V05_S0_CPU_VCCIO =PP1V05_S0_CPU_VCCIO
OMIT_TABLE 15 14 13 11 10 8 8 10 11 13 14 15
BG36 AU41 AC60 J36 AH56 BD47
BG28 AU35 AC57 J30 AG64 BD43
BG24 AU28 AB11 J24 AG62 BD39

AV55 U1000 AN20
BG20 AU22 AB9 J22 AG60 BD31

AV53 IVY-BRIDGE AN18
AV48 BGA AN16

BG16 AU16 AB5 J18 AF58 BD23
AV17 (7 OF11) AN14
BG12 AU14 AA57 J14 AF56 BB35 IO POWER
AV15 AM11
BG8 AT61 AA17 J10 AE64 AY47 OMIT_TABLE
AV12 AL55
BF5 AT57 AA15 J6 AE62 AY43
AU58 AL53
BE62 AT50 AA12 H39 AE60 AY39
AU56 AL48
BE58 AT44 Y65 H33 AD65 AY35
AU52 AL17
BE54 AT38 Y63 H27 AD63 AY31
AU49 AL15
BE50 AT31 Y61 H3 AD61 AY27
AU20 AL12
BE46 AT25 Y7 G62 AD58 AY23
AU18 AK58
BE42 AT19 Y3 G58 AD56 AV46
AT55 AK56
BE38 AT11 Y1 G54 AB65 AV42
AT53 AJ17
BE34 AT7 W57 G50 AB63 AV40
AT48 AJ15
BE30 AT3 V16 G46 AB61 AV36
AT17 AJ12
BE26 AT1 V14 G42 AB58 AV34
AT15 AH16
BE22 AR54 V11 G36 AB56 AV29 VCCIO VCCIO
C BE18
BE14
AR47
AR41
V9
V5
G30
G24
AA64
AA62
AV27
AU45
AT12
AR58
AH14
AH11 C
AR56 AF16
BE10 AR35 U64 G20 AA60 AU43
GRAPHIC CORE POWER

AR52 AF14
BD35 AR28 U62 G16 Y58 AU39
AR49 AE17
IO POWER DDR3
BD7 AR22 U60 G12 Y56 AU37
AR20 AE15
BD3 AP65 U57 G8 W64 AU33
AR18 AE12
BC60 AP63 T7 VSS VSS F39 W62 AU30
AR16 AD11
BC56 AP57 T3 F33 W60 AU26
AR14 AC17
BC52 AP50 T1 F27 V65 AU24
AP55 AC15
BC48 AP44 R57 E60 V63 AT46
VAXG AP53 AC12
BC44 VSS VSS AP38 R50 E56 V61 AT42
AP48 AB16
BC40 AP31 R44 E52 V58 AT40
AN58 AB14
BC36 AP25 R38 E48 V56 VDDQ AT36
AN56 Y16
BC32 AP19 R31 E46 T65 AT34
AN52 Y14
BC28 AP17 R25 E42 T63 AT29
AN49 Y11
BC26 AP15 R19 E36 T61 AT27
BC24 AP12 R17 E30 T58 AR45
BC20 AP11 R15 E24 T56 AR43

BC16 AP9 R12 E22 R64 AR39
BC12 AP5 P65 E18 R62 AR37
BB65 AN54 P63 E14 R60 AR33

BB63 AN47 P61 E10 R55 AR30
BB47 AN41 P11 E6 R53 AR26

BB39 AN35 P9 E4 R48 AR24
BB9 AN28 P5 D63 N64 AP46
BB5 AN22 N54 D39 N62 AP42
B BA58
BA54
AM61
AM7
N47
N41
D33
D27
N60
N58
AP40
AP36
B
BA50 AM3 N35 C58 N56 AP34
BA46 AM1 N28 C54 N52 AP29
BA42 AL57 N22 C50 N49 AP27
BA38 AL50 M57 C46 M65 AN45
BA34 AL44 M50 C42 M63 AN43
BA30 AL38 M44 C36 M61 AN39
BA26 AL31 M38 C30 M59 AN37
BA22 AL25 M31 C20 M55 AN33
BA18 AL19 M25 C16 M53 AN30

BA14 AK16 M19 C12 M48 AN26
AY61 AK14 M7 C8 L56 AN24
AY11 AK11 M3 B39 L52 AL46
AY7 AK9 M1 B33 L48 AL42
AY3 AK5 L64 B27 AL40
AY1 AJ64 L62 A56 AL36
AW56 AJ62 L60 A52 AL34
AW52 AJ60 L58 A42 AL29
AW48 AJ57 L54 A36 AL27
AW44 AH7 L50 A30
AW40 AH3 L46 A24
AW36 AH1 L42 A20
AW32 AG57 L36 A16
AW28 AG17 L30 A12
AW24 AG15 L24 A8
A A
PAGE TITLE
CPU POWER AND GND

DRAWING NUMBER SIZE

REVISION
R
4.18.0
14 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCORE DECOUPLING
Intel recommendation: 4x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 16x 22uF 0805, 4x 10uF 0603, 20x 1uF 0402, 28x 1uF 0402 (NOSTUFF)
Apple Implementation: 8x 270uF 6mOhm, 0x 470uF 4mOhm , 16x 22uF 0402, 4x 10uF 0402, 20x 1uF 0402, 28x 1uF 0201 (NOSTUFF), 4x 22uF 0402 (NOSTUFF)
PLACEMENT_NOTE (C1600-C16C7):
98 45 13 8 =PPVCORE_S0_CPU
Place on bottom side of U1000
U100.
1 C1600 1 C1601 1 C1602 1 C1603 1 C1604 1 C1605 1 C1606 1 C1607 1 C1608 1 C1609 1 C1610 1 C1611 1 C1612 1 C1613 1 C1614 1 C1615 1 C1616 1 C1617 1 C1618 1 C1619
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
D 2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
2
10%
10V
X6S-CERM
0402
D
NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1
C16A0 1
C16A1 1
C16A2 1
C16A3 1
C16A4 1
C16A5 1
C16A6 1
C16A7 1
C16A8 1
C16A9 1
C16B0 1
C16B1 1
C16B2 1
C16B3 1
C16B4 1
C16B5 1
C16B6 1
C16B7 1
C16B8 1
C16B9
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201
NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF

1
C16C0 1
C16C1 1
C16C2 1
C16C3 1
C16C4 1
C16C5 1
C16C6 1
C16C7
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V 4V
2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S 2 CERM-X6S
0201 0201 0201 0201 0201 0201 0201 0201
PLACEMENT_NOTE (C1620-C1623):
Place near inductors on bottom side. NOSTUFF NOSTUFF NOSTUFF NOSTUFF
Place near U1000 on bottom side
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1
C1620 1
C1621 1
C1622 1
C1623 1 C1690 1 C1691 1 C1698 1 C1693 1 C1694 1 C1695 1 C1696 1 C1699
10UF 10UF 10UF 10UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2V 2V 2V 2V 2V 2V 2V
2
4V
X6S 2
4V
X6S 2
4V
X6S 2
4V
X6S 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 2V
X6T-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
C PLACEMENT_NOTE (C1624-C16D5): C
Place near inductors on bottom side. NOSTUFF NOSTUFF NOSTUFF NOSTUFF
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1 C1624 1 C1625 1 C1626 1 C1627 1 C1628 1 C1629 1 C1630 1 C1631 1 C1632 1 C1633 1 C1634 1 C1635 1 C1636 1 C1637 1 C1638 1 C1639 1 C16D0 1 C16D1 1 C16D2 1 C16D3 1 C16D4 1 C16D5
20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V
2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402

1 1 1 1 1 1 1 1
C1640 C1641 C1642 C1643 C1644 C1645 C1688 C1689
20% 20% 20% 20% 20% 20% 20% 20%
2 2V 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V 2 2V
TANT TANT TANT TANT TANT TANT TANT TANT
CASE-B2-SM CASE-B2-SM CASE-B2-SM CASE-B2-SM CASE-B2-SM CASE-B2-SM CASE-B2-SM CASE-B2-SM
CPU VCCIO/VCCPQ DECOUPLING

Intel recommendation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402
Apple Implementation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402

U100.
CPU VCCPLL DECOUPLING
13 11 10 8 =PP1V05_S0_CPU_VCCIO
B
14
B 1 C1646 1 C1647 1 C1648 1 C1649 1 C1650 1 C1651 1 C1652 1 C1653 1 C1654 1 C1655 1 C1656 1 C1657 1 C1658 1
R1600
0
2
=PP1V8_S0_CPU_VCCPLL_R 8 13
8 =PP1V8_S0_CPU_VCCPLL
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF PLACE_NEAR=U1000.AK61:5MM
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 5%
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V
2
10V 1/16W CRITICAL
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
X6S-CERM
0402
MF-LF
402
1
C1685 1
C1686 1
C1687
1UF 1UF 220UF
10% 10% 20% (Z = 1.2mm, place on short side behind CPU)
10V 10V
2 X6S-CERM 2 X6S-CERM 2 2.5V
TANT
PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA
0402 0402 B16
PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA
1
C1659 1
C1660 1
C1661 1
C1662 1
C1663 1
C1664 1
C1665 1
C1666 1
C1667 1
C1668 1
C1669 1
C1670 1
C1671
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF CPU VCCPLL Low pass filter
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
Place near U1000 on bottom side
1
C1672 1
C1673 1
C1674 1
C1675 1
C1676 1
C1677 1
C1678 1
C1679 1
C1680 1
C1681
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM
0603 0603 0603 0603 0603 0603 0603 0603 0603 0603
CRITICAL CRITICAL
1
C1682 1
C1683
330UF-6MOHM 330UF-6MOHM (Z = 1.5mm, place on tall side next to CPU & under heat pipe)
20% 20%
A 3 2 2.0V
POLY-TANT
D15T-ECGLT-COMBO
3 2 2.0V
POLY-TANT
D15T-ECGLT-COMBO SYNC_MASTER=D2_SEAN SYNC_DATE=03/05/2012 A
PAGE TITLE
CPU DECOUPLING-I
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402 DRAWING NUMBER SIZE
R1601 Apple Inc. 051-9589 D

0.010 REVISION
1 2
1%
=PP1V05_S0_CPU_VCCPQE 8 13 R
4.18.0
1/4W
MF
1
C1684 NOTICE OF PROPRIETARY PROPERTY: BRANCH
0603 1UF THE INFORMATION CONTAINED HEREIN IS THE
10%
10V
2 X6S-CERM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
0402 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
16 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VAXG DECOUPLING
INTEL RECOMMENDATION: 2X 470UF 4MOHM, 2X 470UF 4MOHM (NOSTUFF), 6X 22UF 0805, 2X 22UF 0805 (NOSTUFF), 6X 10UF 0603, 2X 10UF 0603 (NOSTUFF), 9X 1UF 0402, 9X 1UF 0402 (NOSTUFF)
APPLE IMPLEMENTATION: 0X 470UF 4MOHM, 3X 330UF 9MOHM , 6X 22UF 0603, 2X 22UF 0603 (NOSTUFF), 6X 10UF 0402, 2X 10UF 0402 (NOSTUFF), 9X 1UF 0402, 9X 1UF 0402 (NOSTUFF)
14 13 8 =PPVCORE_S0_CPU_VCCAXG
U100.
D NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF D

1
C1700 1
C1701 1
C1702 1
C1703 1
C1704 1
C1705 1
C1706 1
C1707 1
C1708 1
C1709 1
C1710 1
C1711 1
C1712 1
C1713 1
C1714 1
C1715 1
C1716 1
C1717
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
Place close to U1000 on bottom side
NOSTUFF NOSTUFF
1
C1718 1
C1719 1
C1720 1
C1721 1
C1722 1
C1723 1
C1724 1
C1725
20% 20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V 4V
2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S
0402 0402 0402 0402 0402 0402 0402 0402
Place near inductors on bottom side.
NOSTUFF NOSTUFF
1 C1726 1 C1727 1 C1728 1 C1729 1 C1730 1 C1731 1 C1732 1 C1733
20% 20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V 4V
2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S 2 X6S
0603 0603 0603 0603 0603 0603 0603 0603
C 1
CRITICAL
C1734 1
CRITICAL
C1735 1
CRITICAL
C1737 C
330UF-6MOHM 330UF-6MOHM 330UF-6MOHM
20% 20% 20% (Z = 1.5mm, place on tall side next to CPU & under heat pipe)
3 2 2.0V 3 2 2.0V 3 2 2.0V
POLY-TANT POLY-TANT POLY-TANT
D15T D15T D15T
CPU VDDQ/VCCDQ DECOUPLING CPU VCCSA DECOUPLING

27 14 11 8 =PP1V5_S3_CPU_VCCDDR
U100. 13 8 =PPVCCSA_S0_CPU Place on bottom side of U1000
U100.
1
C1738 1
C1739 1
C1740 1
C1741 1
C1742 1
C1743 1
C1744 1
C1745 1
C1746 1
C1747
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
1
C1758 1
C1759 1
C1760 1
C1761 1
C1762
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 1UF 1UF 1UF 1UF 1UF
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10% 10% 10% 10% 10%
2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 10V 10V 10V 10V 10V
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM 2 X6S-CERM
0402 0402 0402 0402 0402
Place close to U1000 on bottom side
1
C1748 1
C1749 1
C1750 1
C1751 1
C1752 1
C1753 1
C1754 1
C1755
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V
20%
4V
1
C1763 1
C1764 1
C1765 1
C1766 1
C1767
2 2 2 2 2 2 2 2
X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM X6S-CERM 10UF 10UF 10UF 10UF 10UF
B 0603 0603 0603 0603 0603 0603 0603 0603
2
20%
4V
X6S-CERM
0603
2
20%
4V
X6S-CERM
0603
2
20%
4V
X6S-CERM
0603
2
20%
4V
X6S-CERM
0603
2
20%
4V
X6S-CERM
0603
B
Place near inductors on bottom side
1 C1756
330UF-0.006OHM CRITICAL
20%
2
2V
POLY
1
C1768
CASE-D2-SM 330UF-6MOHM (Z = 1.5mm, place on tall side next to CPU & under heat pipe)
20%
3 2 2.0V
POLY-TANT
D15T-ECGLT-COMBO
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

R1700
0.010
1 2 =PP1V5_S3_CPU_VCCDQ 8 13
1%
1/4W
MF
0603
1
C1757
1UF
10%
10V
2 X6S-CERM
0402
A SYNC_MASTER=D2_SEAN SYNC_DATE=03/05/2012 A
PAGE TITLE
CPU DECOUPLING-II
DRAWING NUMBER SIZE

REVISION
R
4.18.0
17 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE OMIT_TABLE
91 25 IN SYSCLK_CLK32K_RTC A20
RTCX1 U1800 FWH0/LAD0 C38 LPC_AD_R<0> 17 92 38 7 IN PCIE_ENET_D2R_N BG34
PERN1 U1800 SMBALERT*/GPIO11 E12 SMBUS_PCH_ALERT_L 17
C20
RTCX2 PANTHERPOINT FWH1/LAD1 A38 LPC_AD_R<1> PCIE_ENET_D2R_P BJ34
PERP1 PANTHERPOINT
NC MOBILE
17 92 38 7 IN
MOBILE SMBCLK H14 SMBUS_PCH_CLK OUT 44 92
B37 LPC_AD_R<2> =PP3V3_S0_PCH PCIE_ENET_R2D_C_N AV32
FWH2/LAD2 17 8 23 92 38 7 OUT PETN1 C9
FCBGA
C37 AU32
FCBGA SMBDATA SMBUS_PCH_DATA BI 44 92
(1 OF 10) FWH3/LAD3 LPC_AD_R<3> 17 92 38 7 OUT PCIE_ENET_R2D_C_P PETP1 (2 OF 10)
D20 (IPU)
17 RTC_RESET_L RTCRST* D36
1
R1820 BE34
LPC_FRAME_R_L PCIE_AP_D2R_N
SMBUS
FWH4/LFRAME* 17 92 34 IN PERN2
G22 10K BF34 A12
17 PCH_SRTCRST_L SRTCRST* E36 5% 92 34 IN PCIE_AP_D2R_P PERP2 SML0ALERT*/GPIO60 USB_EXTB_SEL_XHCI OUT 17 26
(IPU) LDRQ0* TP_LPC_DREQ0_L
RTC
LPC
7 1/20W BB32
K22 K36 MF 92 34 OUT PCIE_AP_R2D_C_N PETN2 C8
17 PCH_INTRUDER_L INTRUDER* LDRQ1*/GPIO23 TBT_PWR_EN_PCH OUT 25
2 201 AY32 SML0CLK SML_PCH_0_CLK OUT 44 92
(IPU) PCIE_AP_R2D_C_P PETP2
D 17 PCH_INTVRMEN_L C17
INTVRMEN SERIRQ V5 LPC_SERIRQ BI 7 41 43
92 34
9
OUT
IN PCIE_FW_D2R_N BG36
PERN3
SML0DATA G12 SML_PCH_0_DATA BI 44 92
D
PCIE_FW_D2R_P BJ36
9 IN PERP3
HDA_BIT_CLK_R N34 AM3 SATA_HDD_D2R_N PCIE_FW_R2D_C_N AV34 C13 USB_EXTD_SEL_XHCI
92 17 HDA_BCLK SATA0RXN IN 39 91 9 OUT PETN3 SML1ALERT*/PCHHOT*/GPIO74 OUT 17
AM1 SATA_HDD_D2R_P PCIE_FW_R2D_C_P AU34
SATA0RXP IN 39 91 9 OUT PETP3 E14
L34 AP7 SML1CLK/GPIO58 SML_PCH_1_CLK OUT 44 92
92 17 HDA_SYNC_R HDA_SYNC (IPD-BOOT) SATA0TXN SATA_HDD_R2D_C_N OUT 39 91 BF36 M16
AP5 9 IN PCIE_EXCARD_D2R_N PERN4 SML1DATA/GPIO75 SML_PCH_1_DATA BI 44 92
VSel strap not functional (VCCVRM = 1.8V) SATA0TXP SATA_HDD_R2D_C_P OUT 39 91 BE36
T10 9 IN PCIE_EXCARD_D2R_P PERP4
PCH_SPKR
PCI-E*
17 SPKR (IPD-PLTRST#) AM10 AY34
SATA1RXN SATA_ODD_D2R_N IN 9 91 9 OUT PCIE_EXCARD_R2D_C_N PETN4
AM8 SATA_ODD_D2R_P PCIE_EXCARD_R2D_C_P BB34
SATA1RXP PETP4
IHDA
K34 IN 9 91 9 OUT
HDA_RST_R_L
C-LINK
92 17 HDA_RST* AP11
SATA1TXN SATA_ODD_R2D_C_N OUT 9 91 BG37 M7
AP10 7 TP_PCIE_5_D2RN PERN5 (IPU/IPD) CL_CLK1 TP_CLINK_CLK 7
E34 SATA1TXP SATA_ODD_R2D_C_P OUT 9 91
BH37
92 53 IN HDA_SDIN0 HDA_SDIN0 (IPD) 7 TP_PCIE_5_D2RP PERP5 T11
G34 AD7 AY36 (IPU/IPD) CL_DATA1 TP_CLINK_DATA 7
7 TP_HDA_SDIN1 HDA_SDIN1 (IPD) SATA2RXN TP_SATA_C_D2RN 7 TP_PCIE_5_R2D_CN PETN5
TP_HDA_SDIN2 C34 AD5 TP_SATA_C_D2RP TP_PCIE_5_R2D_CP BB36 P10 TP_CLINK_RESET_L
7 HDA_SDIN2 (IPD) SATA2RXP 7 PETP5 CL_RST1* 7
TP_HDA_SDIN3 A34 AH5 TP_SATA_C_R2D_CN

7 HDA_SDIN3 (IPD) SATA2TXN BJ38
AH4 7 TP_PCIE_6_D2RN PERN6
SATA2TXP TP_SATA_C_R2D_CP BG38
A36 7 TP_PCIE_6_D2RP PERP6
92 25 17 HDA_SDOUT_R HDA_SDO (IPD-BOOT) AB8 AU36
SATA3RXN TP_SATA_D_D2RN 7 7 TP_PCIE_6_R2D_CN PETN6 M10
AB10 AV36 PEG_A_CLKRQ*/GPIO47 PEGCLKRQA_L_GPIO47 17
C36 SATA3RXP TP_SATA_D_D2RP 7 7 TP_PCIE_6_R2D_CP PETP6
20 OUT JTAG_ISP_TMS HDA_DOCK_EN*/GPIO33 AF3 AB37
SATA3TXN TP_SATA_D_R2D_CN 7 CLKOUT_PEG_A_N TP_PCIE_CLK100M_PEGAN
SATA
ENET_MEDIA_SENSE_RDIV N32 TP_PCIE_7_D2RN BG40
17 IN HDA_DOCK_RST*/GPIO13 AF1 7 PERN7 AB38
SATA3TXP TP_SATA_D_R2D_CP 7 BJ40 CLKOUT_PEG_A_P TP_PCIE_CLK100M_PEGAP
7 TP_PCIE_7_D2RP PERP7
Y7 TP_SATA_E_D2RN TP_PCIE_7_R2D_CN AY40
J3 SATA4RXN 7 7 PETN7
24 IN XDP_PCH_TCK JTAG_TCK (IPD) Y5
=PP1V05_S0_PCH_VCCIO_SATA 8 21 23
BB40
SATA4RXP TP_SATA_E_D2RP 7 7 TP_PCIE_7_R2D_CP PETP7 AV22
H7 AD3 PLACE_NEAR=U1800.Y11:2.54mm CLKOUT_DMI_N DMI_CLK100M_CPU_N OUT 11 89
XDP_PCH_TMS JTAG_TMS (IPU) SATA4TXN TP_SATA_E_R2D_CN
JTAG
24 IN 7 BE38 AU22
AD1
1
R1830 7 TP_PCIE_8_D2RN PERN8 CLKOUT_DMI_P DMI_CLK100M_CPU_P OUT 11 89
K5 SATA4TXP TP_SATA_E_R2D_CP 7 BC38
24 IN XDP_PCH_TDI JTAG_TDI (IPU) 37.4 7 TP_PCIE_8_D2RP PERP8
Y3 1% AW38
H1 SATA5RXN TP_SATA_F_D2RN 7 1/20W 7 TP_PCIE_8_R2D_CN PETN8
24 XDP_PCH_TDO JTAG_TDO MF
C
OUT
C
Y1 TP_SATA_F_D2RP TP_PCIE_8_R2D_CP AY38 AM12 TP_PCH_CLKOUT_DPN
SATA5RXP 7
2 201
7 PETP8 CLKOUT_DP_N OUT 9
AB3 TP_SATA_F_R2D_CN AM13 TP_PCH_CLKOUT_DPP
SATA5TXN 7 CLKOUT_DP_P OUT 9
AB1
=PP1V05_S0_PCH 8 23 Y40
SATA5TXP TP_SATA_F_R2D_CP 7 92 38 7 OUT PCIE_CLK100M_ENET_N CLKOUT_PCIE0N
Y39 Controlled by PCIECLKRQ5#
T3 92 38 7 OUT PCIE_CLK100M_ENET_P CLKOUT_PCIE0P
SPI_CLK_R 1
92 43 OUT SPI_CLK Y11 R1831 BF18
SATAICOMPO 91 PCH_SATAICOMP J2 CLKIN_DMI_N PCIE_CLK100M_PCH_N IN 17 92
Y14 Y10
49.9 39 17 IN SSD_CLKREQ_L PCIECLKRQ0*/GPIO73 BE18
92 43 OUT SPI_CS0_R_L SPI_CS0* SATAICOMPI 1% CLKIN_DMI_P PCIE_CLK100M_PCH_P IN 17 92
SPI
1/20W
T1 MF AB49
TP_SPI_CS1_L SPI_CS1* AB12 201 92 9 PCIE_CLK100M_FW_N CLKOUT_PCIE1N
SATA3RCOMPO 2
PCIE_CLK100M_FW_P AB47
V4 AB13 PLACE_NEAR=U1800.AB12:2.54mm 92 9 CLKOUT_PCIE1P BJ30
92 43 OUT SPI_MOSI_R SPI_MOSI (IPD-BOOT) SATA3COMPI 91 PCH_SATA3COMP CLKIN_GND1_N PCH_CLKIN_GNDN1 17
AH1 PCH_SATA3RBIAS FW_CLKREQ_L M1 BG30 PCH_CLKIN_GNDP1
U3 SATA3RBIAS 17 PCIECLKRQ1*/GPIO18 CLKIN_GND1_P 17
92 43 IN SPI_MISO SPI_MISO (IPU)
PLACE_NEAR=U1800.AH1:2.54mm
SATALED* P3 PCH_SATALED_L 1 PCIE_CLK100M_AP_N AA48
17 R1832 92 34 OUT CLKOUT_PCIE2N
CLOCKS
PCIE_CLK100M_AP_P AA47 G24 PCH_CLK96M_DOT_N
V14
750 92 34 OUT CLKOUT_PCIE2P CLKIN_DOT_96N IN 17 92
=PPVRTC_G3_PCH 8 18 21 SATA0GP/GPIO21 XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL OUT 24 1% E24
P1 1/20W V10 CLKIN_DOT_96P PCH_CLK96M_DOT_P IN 17 92
SATA1GP/GPIO19 XDP_DC3_PCH_GPIO19_SATARDRVR_EN OUT 24 MF 34 17 IN AP_CLKREQ_L PCIECLKRQ2*/GPIO20
(IPU) 2 201
PCIE_CLK100M_EXCARD_N Y37
R1802 1
1
R1803 92 9 OUT CLKOUT_PCIE3N AK7
Y36 CLKIN_SATA_N PCH_CLK100M_SATA_N IN 17 92
20K 20K 92 9 OUT PCIE_CLK100M_EXCARD_P CLKOUT_PCIE3P AK5
5% 5% CLKIN_SATA_P PCH_CLK100M_SATA_P IN 17 92
1/20W 1/20W A8
R1800 1 1
R1801 MF MF 17 IN EXCARD_CLKREQ_L PCIECLKRQ3*/GPIO25
201 2
330K 1M 2 201
5% 5% Y43 K45
1/20W 1/20W 7 TP_PCIE_CLK100M_PE4N CLKOUT_PCIE4N REFCLK14IN PCH_CLK14P3M_REFCLK IN 17 92
MF MF RTC_RESET_L 17 Y45
201 2
2 201
7 TP_PCIE_CLK100M_PE4P CLKOUT_PCIE4P
PCH_SRTCRST_L 17
PCH_INTRUDER_L JTAG_DPMUXUC_TRST_L L12

17 17 OUT PCIECLKRQ4*/GPIO26 H45
CLKIN_PCILOOPBACK PCH_CLK33M_PCIIN IN 25 92
PCH_INTVRMEN_L 17
PCIE_CLK100M_SSD_N V45 33MHz clocks must be matched within 5"

92 39 OUT CLKOUT_PCIE5N
C1802 1 1
C1803 17 LPC_AD_R<0> R1860 33 1 2 LPC_AD<0> BI 7 41 43 82 92 V46
5% 1/20W MF 201 92 39 OUT PCIE_CLK100M_SSD_P CLKOUT_PCIE5P
1UF 1UF LPC_AD_R<1> R1861 33 1 2 LPC_AD<1> XTAL25_IN V47 SYSCLK_CLK25M_SB_R
B 10%
10V
X5R 2 2
10%
10V
X5R
17
17 LPC_AD_R<2> R1862 33 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
LPC_AD<2>
BI
BI
7 41 43 82 92
7 41 43 82 92 38 17 7 IN ENET_CLKREQ_L L14
PCIECLKRQ5*/GPIO44
(IPU-RSMRST#)
XTAL25_OUT V49
NC
17 91
B
402 402
17 LPC_AD_R<3> R1863 33 1 2 LPC_AD<3> BI 7 41 43 82 92
5% 1/20W MF 201 23 21 8 =PP1V05_S0_PCH_VCCDIFFCLK
17 LPC_FRAME_R_L R1864 33 1 2 LPC_FRAME_L OUT 7 41 43 82 92 7 TP_PCIE_CLK100M_PEBN AB42
CLKOUT_PEG_B_N
5% 1/20W MF 201 AB40
7 TP_PCIE_CLK100M_PEBP CLKOUT_PEG_B_P 1
92 17 HDA_BIT_CLK_R R1810 33 1 2 HDA_BIT_CLK OUT 53 92
R1890
PEGCLKRQB_L_GPIO56 E6
PLACE_NEAR=U1800.N34:1.27mm 5% 1/20W MF 201 17 PEG_B_CLKRQ*/GPIO56 90.9
1%
92 17 HDA_SYNC_R R1811 33 1 2 HDA_SYNC OUT 53 92 1/20W
PLACE_NEAR=U1800.L34:1.27mm 5% 1/20W MF 201 V40 MF
92 71 OUT PEG_CLK100M_N CLKOUT_PCIE6N 201 2
92 17 HDA_RST_R_L R1812 33 1 2 HDA_RST_L OUT 53 92 V42 PLACE_NEAR=U1800.Y47:2.54mm
PLACE_NEAR=U1800.K34:1.27mm 5% 1/20W MF 201 92 71 OUT PEG_CLK100M_P CLKOUT_PCIE6P Y47
XCLK_RCOMP PCH_XCLK_RCOMP
92 25 17 HDA_SDOUT_R R1813 33 1 2 HDA_SDOUT OUT 53 92
T13
PLACE_NEAR=U1800.A36:1.27mm 5% 1/20W MF 201 17 9 IN PEG_CLKREQ_L PCIECLKRQ6*/GPIO45
=PP3V3_SUS_PCH_GPIO 8 18 19 20
=PP3V3_S0_PCH_GPIO K43 TP_PCH_GPIO64_CLKOUTFLEX0

8 18 19 20 25 37 V38 CLKOUTFLEX0/GPIO64 9
92 35 PCIE_CLK100M_TBT_N CLKOUT_PCIE7N (IPD-PWROK)
CLOCKS
OUT
NO STUFF V37
PCIE_CLK100M_TBT_P CLKOUT_PCIE7P
FLEX
92 35 OUT F47 TP_PCH_GPIO65_CLKOUTFLEX1
R1840 CLKOUTFLEX1/GPIO65 9
K12 (IPD-PWROK)
0 37 17 IN TBT_CLKREQ_L PCIECLKRQ7*/GPIO46
89 11 ITPCPU_CLK100M_N 1 2 (IPU-RSMRST#) H47
CLKOUTFLEX2/GPIO66 TP_PCH_GPIO66_CLKOUTFLEX2 9
R1877 4.7K 1 2 PCH_SPKR 17 NO STUFF 5%
AK14 (IPD-PWROK)
5% 1/20W MF 201 1/20W 89 24 ITPXDP_CLK100M_N CLKOUT_ITPXDP_N
R1878 4.7K 1 2 PCH_SATALED_L 17
R1841 MF
AK13 K49
5% 1/20W MF 201 201 89 24 ITPXDP_CLK100M_P CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 TP_PCH_GPIO67_CLKOUTFLEX3 9
0 (IPD-PWROK)
R1834 10K 1 2 DP_AUXCH_ISOL 24 25 89 11 ITPCPU_CLK100M_P 1 2
5% 1/20W MF 201
R1833 10K 1 2 SATARDRVR_EN 24 5%
1/20W
5% 1/20W MF 201
MF R1872
R1842 10K 1 2 FW_CLKREQ_L 17 201 604
5% 1/20W MF 201 91 25 IN SYSCLK_CLK25M_SB 1 2 SYSCLK_CLK25M_SB_R 17 91
R1869 10K 1 2 AP_CLKREQ_L 17 34
R1844 10K 1 2
5% 1/20W MF 201
EXCARD_CLKREQ_L
1%
1/16W
1.8V -> 1.1V
17
1
R1845 10K 1 2
5% 1/20W MF 201
JTAG_DPMUXUC_TRST_L 17 Unused clock terminations for FCIM Mode
MF-LF
402 R1873
5% 1/20W MF 201 1K
R1847 10K 1 2 ENET_CLKREQ_L 7 17 38 1%
5% 1/20W MF 201 92 17 PCH_CLK96M_DOT_P R1891 10K 1 2 1/20W
R1814 10K
A R1815 10K
2
1
1
2
5%
5%
1/20W
1/20W
MF
MF
201
201
PEG_CLKREQ_L
TBT_CLKREQ_L
9 17
17 37
92 17 PCH_CLK96M_DOT_N R1892 10K 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
MF
2 201 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
92 17 PCH_CLK100M_SATA_P R1893 10K 1 2 PAGE TITLE
R1843 10K SSD_CLKREQ_L
R1846 10K
1
1
2
2
5% 1/20W MF 201
PEGCLKRQA_L_GPIO47
17 39
17 GPU:2P
92 17 PCH_CLK100M_SATA_N R1894 10K 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
PCH SATA/PCIe/CLK/LPC/SPI
5% 1/20W MF 201 DRAWING NUMBER SIZE
GPU:1P R1848 10K 1 2 PEGCLKRQB_L_GPIO56 R1880 10K 1 2 PEGCLKRQB_L_GPIO56 PCIE_CLK100M_PCH_P R1895 10K 1 2
R1853 10K 1 2
5% 1/20W MF 201
SMBUS_PCH_ALERT_L
17
17
5% 1/20W MF 201
17 92 17
92 17 PCIE_CLK100M_PCH_N R1896 10K 1 2

5% 1/20W MF 201
5% 1/20W MF 201 5% 1/20W MF 201 REVISION
R1854 10K 1 2 USB_EXTB_SEL_XHCI
R1855 10K 1 2
5% 1/20W MF 201
USB_EXTD_SEL_XHCI
17 26
17
92 17 PCH_CLK14P3M_REFCLK R1897 10K 1 2
5% 1/20W MF 201
R
4.18.0
5% 1/20W MF 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R1879 10K 1 2 ENET_MEDIA_SENSE_RDIV 17 17 PCH_CLKIN_GNDP1 R1870 10K 1 2 THE INFORMATION CONTAINED HEREIN IS THE
5% 1/20W MF 201 5% 1/20W MF 201 PROPRIETARY PROPERTY OF APPLE INC.
17 PCH_CLKIN_GNDN1 R1871 10K 1 2 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
5% 1/20W MF 201 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
18 OF 132
If HDA = S0, must also ensure that signal cannot be high in S3.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP3V3_SUS_PCH_GPIO 8 17 18 19 20
=PP1V05_S0_PCH_VCCIO_PCIE 8
R19051 R1900
1
10K 49.9
5% 1%
1/20W 1/20W
MF MF
201 2 2 201 OMIT_TABLE OMIT_TABLE
89 10 IN DMI_N2S_N<0> BC24 DMI0RXN U1800 FDI_RXN0 BJ14 =FDI_DATA_N<0> IN 9 18 9 OUT LVDS_IG_BKL_ON J47 L_BKLTEN U1800 SDVO_TVCLKINN AP43 TP_SDVO_TVCLKINN 7
DMI_N2S_N<1> BE20 PANTHERPOINT AY14 =FDI_DATA_N<1> LVDS_IG_PANEL_PWR M45 PANTHERPOINT (IPD) AP45 TP_SDVO_TVCLKINP
89 10 IN DMI1RXN MOBILE FDI_RXN1 IN 9 18 9 OUT L_VDD_EN SDVO_TVCLKINP 7
MOBILE (IPD)
D 89 10
89 10
IN
IN
DMI_N2S_N<2>
DMI_N2S_N<3>
BG18
BG20
DMI2RXN
DMI3RXN
FCBGA
(3 OF 10)
FDI_RXN2
FDI_RXN3
BE14
BH13
=FDI_DATA_N<2>
=FDI_DATA_N<3>
IN
IN
9
9
7 OUT LVDS_IG_BKL_PWM P45 L_BKLTCTL FCBGA
(4 OF 10)
SDVO_STALLN
(IPD)
AM42
AM40
TP_SDVO_STALLN 7 D
BC12 T40 SDVO_STALLP TP_SDVO_STALLP 7
BE24 FDI_RXN4 =FDI_DATA_N<4> IN 9 9 OUT LVDS_IG_DDC_CLK L_DDC_CLK (IPD)
89 10 IN DMI_N2S_P<0> DMI0RXP BJ12 K47 AP39
BC20 FDI_RXN5 =FDI_DATA_N<5> IN 9 9 OUT LVDS_IG_DDC_DATA L_DDC_DATA SDVO_INTN TP_SDVO_INTN 7
89 10 IN DMI_N2S_P<1> DMI1RXP BG10 (IPD-PLTRST#) (IPD) AP40
BJ18 FDI_RXN6 =FDI_DATA_N<6> IN 9 T45 SDVO_INTP TP_SDVO_INTP 7
89 10 IN DMI_N2S_P<2> DMI2RXP BG9 7 TP_LVDS_IG_CTRL_CLK L_CTRL_CLK (IPD)
BJ20 FDI_RXN7 =FDI_DATA_N<7> IN 9 P39
89 10 IN DMI_N2S_P<3> DMI3RXP 7 TP_LVDS_IG_CTRL_DATA L_CTRL_DATA P38
BG14 SDVO_CTRLCLK DPA_IG_DDC_CLK 83
FDI_RXP0 =FDI_DATA_P<0> IN 9 AF37 M39
AW24 BB14 PCH_LVDS_IBG LVD_IBG SDVO_CTRLDATA DPA_IG_DDC_DATA 83
89 10 OUT DMI_S2N_N<0> DMI0TXN FDI_RXP1 =FDI_DATA_P<1> IN 9 PLACE_NEAR=U1800.AF37:2.54mm AF36 (IPD-PLTRST#)
AW20 BF14 7 TP_PCH_LVDS_VBG LVD_VBG AT49
89 10 OUT DMI_S2N_N<1> DMI1TXN FDI_RXP2 =FDI_DATA_P<2> IN 9 R19501 DDPB_AUXN DPA_IG_AUX_CH_N 83 95
89 10 DMI_S2N_N<2> BB18 DMI2TXN FDI_RXP3 BG13 =FDI_DATA_P<3> 9 2.37K AE48 LVD_VREFH DDPB_AUXP AT47 DPA_IG_AUX_CH_P 83 95
OUT IN
AV18 BE12 1% AE47 AT40
89 10 OUT DMI_S2N_N<3> DMI3TXN FDI_RXP4 =FDI_DATA_P<4> IN 9 1/20W LVD_VREFL DDPB_HPD DPA_IG_HPD 9 82
BG12 MF
=FDI_DATA_P<5>
DMI
FDI
DIGITAL DISPLAY INTERFACE

AY24 FDI_RXP5 IN 9 201 2 AV42
89 10 OUT DMI_S2N_P<0> DMI0TXP BJ10 AK39 DDPB_0N TP_DP_IG_B_MLN<0> 9
AY20 FDI_RXP6 =FDI_DATA_P<6> IN 9 91 9 OUT LVDS_IG_A_CLK_N LVDSA_CLK* AV40
89 10 OUT DMI_S2N_P<1> DMI1TXP BH9 AK40 DDPB_0P TP_DP_IG_B_MLP<0> 9
AY18 FDI_RXP7 =FDI_DATA_P<7> IN 9 91 9 OUT LVDS_IG_A_CLK_P LVDSA_CLK AV45
89 10 OUT DMI_S2N_P<2> DMI2TXP DDPB_1N TP_DP_IG_B_MLN<1> 9
LVDS
89 10 DMI_S2N_P<3> AU18 DMI3TXP LVDS_IG_A_DATA_N<0> AN48 LVDSA_DATA0* DDPB_1P AV46 TP_DP_IG_B_MLP<1>
FDI_INT AW16
OUT 91 9 OUT 9
FDI_INT OUT 10 89
AM47 AU48
91 9 OUT LVDS_IG_A_DATA_N<1> LVDSA_DATA1* DDPB_2N TP_DP_IG_B_MLN<2> 9
=PPVRTC_G3_PCH
FDI_FSYNC0 AV12
8 17 21 AK47 AU47
BJ24 =FDI_FSYNC<0> OUT 9 91 9 OUT LVDS_IG_A_DATA_N<2> LVDSA_DATA2* DDPB_2P TP_DP_IG_B_MLP<2> 9
PCH_DMI_COMP DMI_ZCOMP
BG25 FDI_FSYNC1 BC10 =FDI_FSYNC<1> OUT 9 91 9 OUT LVDS_IG_A_DATA_N<3> AJ48 LVDSA_DATA3* DDPB_3N AV47 TP_DP_IG_B_MLN<3> 9
DMI_IRCOMP R1915
1
DDPB_3P AV49 TP_DP_IG_B_MLP<3>
FDI_LSYNC0 AV14 AN47 9
=FDI_LSYNC<0> OUT 9 390K 91 9 OUT LVDS_IG_A_DATA_P<0> LVDSA_DATA0
BH21 5%
PCH_DMI2RBIAS DMI2RBIAS FDI_LSYNC1 BB10 =FDI_LSYNC<1> OUT 9 1/20W 91 9 OUT LVDS_IG_A_DATA_P<1> AM49 LVDSA_DATA1 P46
MF AK49 DDPC_CTRLCLK DPB_IG_DDC_CLK 83
PLACE_NEAR=U1800.BH21:2.54mm 2 201 91 9 OUT LVDS_IG_A_DATA_P<2> LVDSA_DATA2 P42
AJ47 DDPC_CTRLDATA DPB_IG_DDC_DATA 83
R1920
1 LVDS_IG_A_DATA_P<3> LVDSA_DATA3 (IPD-PLTRST#)
DSWVRMEN A18
91 9 OUT
PCH_DSWVRMEN AP47
750 DDPC_AUXN DPB_IG_AUX_CH_N
SYSTEM POWER
83 95
1% C12
PCH_SUSACK_L DPWROK E22 PM_DSW_PWRGD LVDS_IG_B_CLK_N AF40 AP49 DPB_IG_AUX_CH_P
MANAGEMENT
1/20W 18 SUSACK* (IPU) IN 41 7 OUT LVDSB_CLK* DDPC_AUXP 83 95
MF AF39 AT38
2 201 K3 LVDS_IG_B_CLK_P LVDSB_CLK DDPC_HPD DPB_IG_HPD
WAKE* B9
7 OUT 9 82
41 25 PM_SYSRST_L SYS_RESET* PCIE_WAKE_L 7 18 34
C
IN IN
C P12
R1909
1
LVDS_IG_B_DATA_N<0> AH45 LVDSB_DATA0* DDPC_0N AY47 TP_DP_IG_C_MLN<0>
CLKRUN*/GPIO32 N3
91 9 OUT 7
70 41 24 IN PM_PCH_SYS_PWROK SYS_PWROK PM_CLKRUN_L BI 7 18 41 43 100K AH47 AY49
5% 91 9 OUT LVDS_IG_B_DATA_N<1> LVDSB_DATA1* DDPC_0P TP_DP_IG_C_MLP<0> 7
L22 1/20W
70 25 IN PM_PCH_PWROK PWROK SUS_STAT*/GPIO61 G8 LPC_PWRDWN_L OUT 7 25 41 43 MF 91 9 OUT LVDS_IG_B_DATA_N<2> AF49 LVDSB_DATA2* DDPC_1N AY43 TP_DP_IG_C_MLN<1> 7
2 201 LVDS_IG_B_DATA_N<3> AF45 LVDSB_DATA3* DDPC_1P AY45 TP_DP_IG_C_MLP<1>
PM_PCH_APWROK L10 APWROK SUSCLK/GPIO62 N14 PM_CLK32K_SUSCLK_R 9 OUT 7
70 IN OUT 42
DDPC_2N BA47 TP_DP_IG_C_MLN<2>
LVDS_IG_B_DATA_P<0> AH43 LVDSB_DATA0
7
PM_MEM_PWRGD B13 DRAMPWROK SLP_S5*/GPIO63 D10 PM_SLP_S5_L 91 9 OUT

DDPC_2P BA48 TP_DP_IG_C_MLP<2>
89 27 11 OUT OUT 18 41 70
91 9 LVDS_IG_B_DATA_P<1> AH49 LVDSB_DATA1
7
OUT
DDPC_3N BB47 TP_DP_IG_C_MLN<3>
PM_RSMRST_L C21 RSMRST* SLP_S4* H4 PM_SLP_S4_L LVDS_IG_B_DATA_P<2> AF47 LVDSB_DATA2
7
70 IN OUT 7 18 27 34 38 40 41 70 91 9 OUT
DDPC_3P BB49 TP_DP_IG_C_MLP<3>
LVDS_IG_B_DATA_P<3> AF43 LVDSB_DATA3
7
18 PCH_SUSWARN_L K16 SUSWARN*/SUSPWRDNACK/GPIO30 SLP_S3* F4 PM_SLP_S3_L 7 18 27 38 41 70

9 OUT
OUT
DDPD_CTRLCLK M43 TP_DP_IG_D_CTRL_CLK
PM_PWRBTN_L E20 PWRBTN* (IPU) SLP_A* G10 TP_PM_SLP_A_L 7
41 24 18 IN
DDPD_CTRLDATA M36 TP_DP_IG_D_CTRL_DATA 7
G16 N48 (IPD-PLTRST#)
70 42 41 IN SMC_ADAPTER_EN H20 ACPRESENT/GPIO31 SLP_SUS* PM_SLP_SUS_L OUT 18 70 7 TP_CRT_IG_BLUE CRT_BLUE AT45
(IPD-DeepS4/S5) P49 DDPD_AUXN TP_DP_IG_D_AUXN 7
E10 TP_CRT_IG_GREEN CRT_GREEN
PMSYNCH AP14
7 AT43
42 IN PM_BATLOW_L BATLOW*/GPIO72 (IPU) PM_SYNC OUT 11 89 T49 DDPD_AUXP TP_DP_IG_D_AUXP 7
7 TP_CRT_IG_RED CRT_RED BH41
A10 DDPD_HPD TP_DP_IG_D_HPD
SLP_LAN*/GPIO29 K14
7
PCH_RI_L RI* MEM_VDD_SEL_1V5_L OUT 18 64
CRT
7 TP_CRT_IG_DDC_CLK T39 CRT_DDC_CLK DDPD_0N BB43 TP_DP_IG_D_MLN<0> 7
7 TP_CRT_IG_DDC_DATA M40 CRT_DDC_DATA DDPD_0P BB45 TP_DP_IG_D_MLP<0> 7
DDPD_1N BF44 TP_DP_IG_D_MLN<1> 7
7 TP_CRT_IG_HSYNC M47 CRT_HSYNC DDPD_1P BE44 TP_DP_IG_D_MLP<1> 7

20 19 18 17 8 =PP3V3_SUS_PCH_GPIO M49 BF42
7 TP_CRT_IG_VSYNC CRT_VSYNC DDPD_2N TP_DP_IG_D_MLN<2> 7
DDPD_2P BE42 TP_DP_IG_D_MLP<2> 7

R19831 PCH_DAC_IREF T43 DAC_IREF DDPD_3N BJ42 TP_DP_IG_D_MLN<3> 7
10K T42 BG42
5% PLACE_NEAR=U1800.T43:2.54mm CRT_IRTN DDPD_3P TP_DP_IG_D_MLP<3> 7
1/20W
MF
201 2 R1986 R1951
1
1K
0 5%
18 PCH_SUSWARN_L 2 1 PCH_SUSACK_L 18 1/20W
B 5%
1/20W
MF
MF
2 201 B
201
=PP3V3_SUS_PCH_GPIO 8 17 18 19 20
=PP3V3_S0_PCH_GPIO 8 17 19 20 25 37
=PP3V3_S5_PCH 8
R1985 1K 1 2
5% 1/20W MF 201
PM_PWRBTN_L 18 24 41
R1991 8.2K 1 2 PM_CLKRUN_L 7 18 41 43

5% 1/20W MF 201
R1982 10K MEM_VDD_SEL_1V5_L
A R1925 1K
1
1
2
2
5% 1/20W MF 201
PCIE_WAKE_L
18 64
7 18 34
NOSTUFF
R1999 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
5% 1/20W MF 201 MAKE_BASE=TRUE 0 PAGE TITLE
2
5%
1 =TBT_WAKE_L IN 35 42
PCH DMI/FDI/PM/Graphics
1/20W
R1924 100K 2 1 PM_SLP_S3_L 7 18 27 38 41 70 MF
201
DRAWING NUMBER
051-9589
SIZE
D
R1921 100K 2 1
5% 1/20W MF 201
PM_SLP_S4_L 7 18 27 34 38 40 41 70 Apple Inc.
R1922 100K 2 1
5% 1/20W MF 201
PM_SLP_S5_L 18 41 70 R
REVISION
4.18.0
R1923 100K 2 1
5%
5%
1/20W
1/20W
MF
MF
201
201
PM_SLP_SUS_L 18 70
R1981 100K 2 1 LVDS_IG_BKL_ON 9 18 THE INFORMATION CONTAINED HEREIN IS THE
R1984 100K 2 1
5%
5%
1/20W
1/20W
MF
MF
201
201
LVDS_IG_PANEL_PWR 9 18
19 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
BG26
TP1 U1800 RSVD1 AY7
NC PANTHERPOINT NC
BJ26 AV7
NC TP2 MOBILE RSVD2 NC
BH25 AU3
NC TP3 FCBGA RSVD3 NC
BJ16
TP4 (5 OF 10) RSVD4 BG4
NC NC
BG16
NC TP5 AT10
AH38 RSVD5 NC
NC TP6 BC8
AH37 RSVD6 NC
NC TP7
AK43 AU2
NC TP8 RSVD7 NC
AK45 AT4
NC TP9 RSVD8 NC
C18 AT3
TP10 RSVD9
D
NC
NC
N30
H3
TP11 RSVD10 AT1
AY3
NC
NC D
NC TP12 RSVD11 NC
AH12 AT5
NC TP13 RSVD12 NC
AM4 AV3
NC TP14 RSVD13 NC
AM5 AV1
NC TP15 RSVD14 NC
Y13 BB1
NC TP16 RSVD15 NC
K24 BA3
NC TP17 RSVD16 NC
L24 BB5
NC TP18 RSVD17 NC
AB46 BB3
NC TP19 RSVD18 NC
AB45 BB7
NC TP20 RSVD19 NC
BE8
B21 RSVD20 NC
NC TP21 BD4
M20 RSVD21 NC
NC TP22 BF6
AY16 RSVD22 NC
TP_PCH_TP23 TP23
BG46 AV5
NC TP24 RSVD23 NC
AV10
RSVD24 NC
AT8
RSVD25 NC
AY5
RSVD26 NC
BA2
RSVD27 NC
AT12
RSVD28 NC
BF3
RSVD29 NC
USB3_EXTA_RX_N BE28 C24 USB_EXTA_N
91 40 IN USB3RN1 USBP0N BI 40 91
USB3_EXTB_RX_N BC30 A24 USB_EXTA_P

Ext A (XHCI/EHCI)
91 38 7 IN USB3RN2 USBP0P BI 40 91
USB3_EXTC_RX_N BE32
91 9 IN USB3RN3 C25
USBP1N USB_EXTB_XHCI_N 26 91
C
BI
C Ext B (XHCI)
USB3_EXTD_RX_N BJ32
9 IN USB3RN4 B25
USBP1P USB_EXTB_XHCI_P BI 26 91
USB3_EXTA_RX_P BC28
91 40 IN USB3RP1 C26
USBP2N USB_EXTC_N BI 9 91
91 38 7 IN USB3_EXTB_RX_P BE30
USB3RP2 A26 USB_EXTC_P
Ext C (XHCI/EHCI)
BF32 USBP2P BI 9 91
91 9 IN USB3_EXTC_RX_P USB3RP3
USB3_EXTD_RX_P BG32 K28 USB_EXTD_XHCI_N
9 IN USB3RP4 USBP3N BI 26 91
H28 USB_EXTD_XHCI_P
Ext D (XHCI) (Mobiles: Trackpad?)
USB
USBP3P BI 26 91
USB3_EXTA_TX_N AV26
91 40 OUT USB3TN1 E28
USBP4N TP_USB_4N
91 38 OUT USB3_EXTB_TX_N BB26
USB3TN2 D28 TP_USB_4P
Unused
AU28 USBP4P
91 9 OUT USB3_EXTC_TX_N USB3TN3
USB3_EXTD_TX_N AY30 C28 TP_USB_SDN
9 OUT USB3TN4 USBP5N
A28 TP_USB_SDP
RSVD: SD
AU26 USBP5P
91 40 OUT USB3_EXTA_TX_P USB3TP1
USB3_EXTB_TX_P AY26 C29 TP_USB_WLANN
91 38 OUT USB3TP2 USBP6N
USB3_EXTC_TX_P AV28 B29 TP_USB_WLANP
RSVD: WiFi
91 9 OUT USB3TP3 USBP6P
USB3_EXTD_TX_P AW30
9 OUT USB3TP4 N28
USBP7N USB_HUB_UP_N BI 26 91
M28 USB_HUB_UP_P
USB Hub (All LS/FS Devices)
USBP7P BI 26 91
=PP3V3_S0_PCH_GPIO L30 USB_CAMERA_N

37 25 20 19 18 17 8 USBP8N BI 34 91
R2010 10K 1 2 PCI_INTA_L K40 K30 USB_CAMERA_P

Camera
PIRQA* USBP8P BI 34 91
PCI
5% 1/20W MF 201
R2011 10K 1 2 PCI_INTB_L K38
PIRQB* G30
5% 1/20W MF 201 USBP9N USB_EXTB_EHCI_N BI 26 91
R2012 10K 1 2 PCI_INTC_L H38
PIRQC* E30 Ext B (EHCI)
5% 1/20W MF 201 USBP9P USB_EXTB_EHCI_P BI 26 91
R2013 10K 1 2 PCI_INTD_L G38
PIRQD*
5% 1/20W MF 201 C30
USBP10N USB_EXTD_EHCI_N BI 9
JTAG_GMUX_TMS C46 A30 USB_EXTD_EHCI_P

Ext D (EHCI)
19 OUT REQ1*/GPIO50 USBP10P BI 9
BLC_I2C_MUX_SEL C44
19 OUT REQ2*/GPIO52 L32
USBP11N TP_USB_BT_HSN
19 OUT USE_HDD_OOB_L E40
REQ3*/GPIO54 K32 TP_USB_BT_HSP
RSVD: BT (HS)
USBP11P
B TP_PCH_STRP_BBS1 D47
E42
GNT1*/GPIO51 USBP12N G32
E32
TP_USB_12N
Unused
B
NO STUFF TP_PCH_STRP_ESI_L GNT2*/GPIO53 USBP12P TP_USB_12P
R2054 10K 2 1 PCH_STRP_TOPBLK_SWP_L F46
GNT3*/GPIO55 C32
5% 1/20W MF 201 USBP13N TP_USB_13N
(IPU-PCIERST#) A32 TP_USB_13P
Unused
G42 USBP13P
19 IN BLC_GPIO PIRQE*/GPIO2 (IPD)
AUD_IP_PERIPHERAL_DET G40
59 19 IN PIRQF*/GPIO3 C33
C42 USBRBIAS* 91 PCH_USB_RBIAS
35 19 IN TBT_PWR_REQ_L PIRQG*/GPIO4 B33
D44 USBRBIAS PLACE_NEAR=U1800.B33:2.54mm
58 19 IN AUD_I2C_INT_L PIRQH*/GPIO5 1
R2070
TP_PCI_PME_L K10 A14 XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L 22.6
7 PME* (IPU) OC0*/GPIO59 IN 19 24
K20 1%
C6 OC1*/GPIO40 XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L IN 19 24 1/20W
27 25 OUT PLT_RESET_L PLTRST* B17 MF
OC2*/GPIO41 XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L IN 19 24
2 201
LPC_CLK33M_SMC_R H49 C16 XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
92 25 OUT CLKOUT_PCI0 OC3*/GPIO42 IN 19 24
LPC_CLK33M_LPCPLUS_R H43 L16 XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

25 OUT CLKOUT_PCI1 OC4*/GPIO43 IN 19 24
=PP3V3_SUS_PCH_GPIO TP_PCI_CLK33M_OUT2 J48 A16 XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

8 17 18 20 25 CLKOUT_PCI2 OC5*/GPIO9 IN 19 24
=PP3V3_S3_PCH_GPIO TP_PCI_CLK33M_OUT3 K42 D14 XDP_DB2_PCH_GPIO10_AP_PWR_EN

8 25 7 CLKOUT_PCI3 OC6*/GPIO10 OUT 24
=PP3V3_S0_PCH_GPIO PCH_CLK33M_PCIOUT H40 C14 XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

8 17 18 19 20 25 37 25 OUT CLKOUT_PCI4 OC7*/GPIO14 IN 19 24
(IPD)
R2016 10K 1 2 JTAG_GMUX_TMS 19

5% 1/20W MF 201
R2017 10K 1 2 BLC_I2C_MUX_SEL 19
5% 1/20W MF 201
R2018 10K 1 2 USE_HDD_OOB_L 19
5% 1/20W MF 201
R2030 10K 1 2 BLC_GPIO 19
5% 1/20W MF 201 24 19 XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L R2020 1K 1 2 XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L 19 24
5% 1/20W MF 201
NO STUFF Redundant to pull-up on audio page XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L R2021 1K 1 2 XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
24 19 19 24
R2014 10K 1 2 AUD_IP_PERIPHERAL_DET 19 59 5% 1/20W MF 201
5% 1/20W MF 201
R2031 10K 1 2 TBT_PWR_REQ_L 19 35
A NO STUFF
5% 1/20W MF 201
Redundant to pull-up on audio page SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A

R2033 10K 1 2 AUD_I2C_INT_L 19 58
PAGE TITLE
5% 1/20W MF 201
PCH PCI/USB/TP/RSVD
R2069 10K 1 2 XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE 19 24 DRAWING NUMBER SIZE
R2060 10K 1 2
5% 1/20W MF 201
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L 19 24 Apple Inc. 051-9589 D
5% 1/20W MF 201 REVISION
R2061 10K 1 2 XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
R2062 10K 1 2
5% 1/20W MF 201
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L
19 24
19 24
R
4.18.0
R2068 10K 1 2
5% 1/20W MF 201
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L
19 24
5% 1/20W MF 201 THE INFORMATION CONTAINED HEREIN IS THE
R2067 10K 2 1 AP_PWR_EN 24 34 70 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
20 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM
RAMCFG_SLOT RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.
Systems with chip-down memory should add pull-downs on another page and set straps per software.
37 25 20 19 18 17 8 =PP3V3_S0_PCH_GPIO
RAMCFG3:H RAMCFG2:H RAMCFG1:H RAMCFG0:H

R2172 1
1
R2174 1
1
R2173 R2175
10K 10K 10K 10K
D 5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF
D
OMIT_TABLE 201 201 201 201
(TBT_CIO_PLUG_EVENT_ISOL) 2 2 2 2
24 20 IN XDP_FC1_PCH_GPIO0 T7
BMBUSY*/GPIO0 U1800 TACH4/GPIO68 C40 9 MLB_RAMCFG3
PANTHERPOINT
FW_PME_L A42 MOBILE B41 MLB_RAMCFG2
20 IN TACH1/GPIO1 TACH5/GPIO69 9
FCBGA
DPMUX_UC_IRQ H36 C41 MLB_RAMCFG1
82 20 IN TACH2/GPIO6 (6 OF 10) TACH6/GPIO70 9
SMC_RUNTIME_SCI_L E38 A40 MLB_RAMCFG0

41 20 IN TACH3/GPIO7 TACH7/GPIO71 9
TP_PCH_GPIO8 C10
GPIO8 (IPU-RSMRST#)
WOL_EN C4
20 OUT LAN_PHY_PWR_CTRL/GPIO12
P4 PCH_A20GATE
G2 A20GATE 20
24 IN XDP_FC0_PCH_GPIO15 GPIO15 (IPU)
NO STUFF
24 OUT XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH U2
SATA4GP/GPIO16 (IPD) PECI AU16 PCH_PECI R2170 43 1 2 CPU_PECI BI 11 42 89
5% 1/20W
D40 MF 201
43 20 7 BI LPCPLUS_GPIO TACH0/GPIO17 P5
RCIN* PCH_RCIN_L 20
ODD_PWR_EN_L T5
20 OUT SCLOCK/GPIO22
=PP1V8_S0_PCH_VCC_DFTERM 8 21 23
E8 PROCPWRGD AY11 PCH_PROCPWRGD R2140 0 1 2 CPU_PWRGD OUT 11 24 89
CPU/MISC
35 20 TBT_GO2SX_BIDIR GPIO24 5% 1/20W
MF 201
1
41 20 SMC_WAKE_SCI_L E16
GPIO27 (IPU-DeepS4/S5) THRMTRIP* AY10 42 PM_THRMTRIP_L_R R2156 390 1 2 PM_THRMTRIP_L 11 42 89
R2179
IN IN
5% 1/20W 2.2K
P8 MF 201 5%
24 OUT XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L GPIO28 (IPU-RSMRST#) T14 1/20W
INIT3_3V* PCH_INIT3V3_L
GPIO
MF
(IPU) R2178 201
37 OUT TBT_SW_RESET_L R2180 0 1 2 20 TBT_SW_RESET_R_L K1
STP_PCI*/GPIO34 2
5% 1/20W AY1 1K
MF 201 K4 DF_TVS PCH_DF_TVS 2 1 CPU_PROC_SEL_L 11 89
24 OUT XDP_DC1_PCH_GPIO35_MXM_GOOD GPIO35 (IPD-PLTRST#?)
NO STUFF 5% DF_TVS:DMI & FDI Term Voltage
1/20W
V8 AH8
24 20 OUT XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL SATA2GP/GPIO36
(IPD-PLTRST#)
TS_VSS1 R2130 1 MF
201
Set to Vss when Low
C 24 OUT XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK M5
SATA3GP/GPIO37
(IPD-PLTRST#)
TS_VSS2
TS_VSS3
AK11
AH10 5%
1/20W
MF
1K This has internal pull up and should not pulled low.
THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
Set to Vcc when High
C
JTAG_ISP_TDO N2 AK10
20 IN SLOAD/GPIO38 TS_VSS4 201
2
JTAG_ISP_TDI M3
20 OUT SDATAOUT0/GPIO39 P37
NC_1 NC
FW_PWR_EN_PCH V13
25 20 OUT SDATAOUT1/GPIO48
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH V3 BG2
24 OUT SATA5GP/GPIO49/TEMP_ALERT* VSS_NCTF_14
BG48
D6 VSS_NCTF_15
52 43 20 7 BI SPIROM_USE_MLB GPIO57 BH3
VSS_NCTF_16
BH47
VSS_NCTF_17
A4 BJ4
VSS_NCTF_0 VSS_NCTF_18
A44 BJ44
A45 BJ45
A46 BJ46
A5 BJ5
NCTF
A6 BJ6
B3 C2
B47 C48
BD1 D1
BD49 D49
BE1 E1
BE49 E49
BF1 F1
BF49 F49
B B
JTAG Isolation due to glitch in and out of sleep 37 25 20 19 18 17 8 =PP3V3_S0_PCH_GPIO
NOTE: TCK from PCH is Push-Pull CMOS
NOTE: TMS/TDI from PCH is Open Drain 1 C2113
NOTE: TDO from CR is Push-Pull CMOS
0.1UF
10%
=PP3V3_S5_PCH_GPIO 8 CRITICAL CRITICAL 8 2
16V
X5R-CERM
=PP3V3_SUS_PCH_GPIO 8 17 18 19 37 25 20 19 18 17 8 =PP3V3_S0_PCH_GPIO VCC
0201
=PP3V3_TBT_PCH_GPIO
=PP3V3_S0_PCH_GPIO 8 17 18 19 20 25 37
Q2160
8 20
U2100
SOT833
1 1
R2188 SSM6N15AFE R2163 TBT_PWR_EN goes high for JTAG Programming 08
TBT_PWR_EN JTAG_TBT_TCK
74LVC2G08GT
1 7
G 2
10K 10K 35 25 IN A1 Y1 OUT 35
5% SOT563 5%
1/20W 1/20W 24 IN JTAG_ISP_TCK 2
B1
Stuff R2160 or R2574, not both MF MF
TBT_CIO_PLUG_EVENT 5 3 TBT_CIO_PLUG_EVENT_ISOL
NO STUFF 2 201
2 201 35 IN A2 Y2 OUT 24
D
S
JTAG_ISP_TMS JTAG_TBT_TMS 6 Connects to PCH through
R2160 10K 1 2 XDP_FC1_PCH_GPIO0
17 IN OUT 35
B2
6
20 24
1
R2185 10K 1 2
5% 1/20W MF 201
FW_PME_L 1 GND current limiting 1K resistor R2574
20
R2113 1
R2196 10K 1 2
5% 1/20W MF 201
SMC_RUNTIME_SCI_L 20 41 10K R2166 4
R2190 100K 1 2
5% 1/20W MF 201
LPCPLUS_GPIO
CRITICAL 5% 10K
7 20 43 1/20W 5%
5% 1/20W MF 201 37 25 20 19 18 17 8 =PP3V3_S0_PCH_GPIO MF 1/20W
=PP3V3_TBT_PCH_GPIO 8 20 201 2 MF
NO STUFF Must stuff R2197 when R2180 NO STUFFed. Q2160 2 201
R2197 10K 1 2 TBT_SW_RESET_R_L 20
1
R2199 SSM6N15AFE
1
R2161
5% 1/20W MF 201
R2184 10K FW_PWR_EN_PCH
G 5
1 2 20 25 10K 10K
5% 1/20W MF 201 5% SOT563 5%
1/20W 1/20W
R2150 10K 1 2 PCH_A20GATE 20 MF MF
5% 1/20W MF 201 2 201 2 201
R2155 10K 1 2 PCH_RCIN_L 20
D
5% 1/20W MF 201 20 IN JTAG_ISP_TDI JTAG_TBT_TDI OUT 35

3
R2194
4
10K
A R2192 10K
1
1
2
2
5%
5%
1/20W
1/20W
MF
MF
201
201
WOL_EN
TBT_GO2SX_BIDIR
20
20 35
CRITICAL
R2193 100K 1 2 SPIROM_USE_MLB 7 20 43 52 37 25 20 19 18 17 8 =PP3V3_S0_PCH_GPIO Q2162 PAGE TITLE
R2191 10K 1 2
5% 1/20W MF 201
SMC_WAKE_SCI_L 20 41
1
SSM3K15FV
=PP3V3_TBT_PCH_GPIO
1
8 20
PCH GPIO/MISC/NCTF
5% 1/20W MF 201 R2186 SOD-VESM-HF R2162 DRAWING NUMBER SIZE
R2111 20K 051-9589 D
G 1
2 1 DPMUX_UC_IRQ 10K 10K

R2195 100K 2 1
5% 1/20W MF 201
AUD_IPHS_SWITCH_EN_PCH
20 82
24 25
5%
1/20W
5%
1/20W
Apple Inc. REVISION
R2112 10K 2 1
5%
5%
1/20W
1/20W
MF
MF
201
201
ODD_PWR_EN_L 20
MF
2 201
MF
2 201
R
4.18.0
R2198
D
10K 2 1 XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL 20 24 20 OUT JTAG_ISP_TDO JTAG_TBT_TDO IN 35 NOTICE OF PROPRIETARY PROPERTY: BRANCH

5% 1/20W MF 201
3

R2116 10K 2 1 ENET_LOW_PWR_PCH 9 24 25 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
21 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
OMIT_TABLE =PP1V05_S0_PCH_VCC_CORE OMIT_TABLE

23 8
VCCACLK pin left as NC per DG NC

AD49 VCCACLK U1800 VCCIO_29_USB N26 =PP1V05_S0_PCH_VCCIO_USB 8 23 1.44 A Max, 474mA Idle AA23 VCCCORE U1800
PANTHERPOINTVCCIO_30_USB P26 AC23 VCCCORE PANTHERPOINT
23 8 =PP3V3_S5_PCH_VCCDSW T16 VCCDSW3_3 MOBILE P28 AD21 MOBILE
FCBGA VCCIO_31_USB VCCCORE FCBGA
TP_PPVOUT_PCH_DCPSUSBYP V12 DCPSUSBYP (8 OF 10) VCCIO_32_USB T27 AD23 VCCCORE (7 OF 10)
VCCIO_33_USB T29 AF21 VCCCORE VCCADAC U48 PP3V3_S0_PCH_VCCA_DAC_F 23
PP3V3_S0_PCH_VCC3_3_CLK_F T38 VCC3_3_5_CLK
CRT
23
AF23 VCCCORE
VCCSUS3_3_7_USB T23 =PP3V3_SUS_PCH_VCCSUS_USB 8 23
VCCAPLLDMI2 pin left as NC per DG NC BH23 AG21 VSSADAC U47
VCC CORE
VCCAPLLDMI2 T24 VCCCORE
VCCSUS3_3_8_USB AG23 VCCCORE
23 21 8 =PP1V05_S0_PCH_VCCIO_CLK AL29 VCCIO_14_PLLCLK VCCSUS3_3_9_USB V23
AG24
V24 VCCCORE
AL24 VCCSUS3_3_10_USB AG26 CKPLUS_WAIVE=PwrTerm2Gnd
AL24 left as NC per DG NC DCPSUS_3_CLK P24 VCCCORE
=LVDS_VCCA
VCCSUS3_3_6_USB AG27 VCCALVDS AK36 8
VCCCORE
23 21 8 =PP1V05_S0_PCH_VCCASW AA19 VCCASW_1_CLK
AA21 VCCIO_34_PLLUSB T26 =PP1V05_S0_PCH_VCCIO_PLLUSB 8
AG29 VCCCORE VSSALVDS AK37
VCCASW_2_CLK AJ23 VCCCORE
AA24 VCCASW_3_CLK V5REF_SUS M26 =PP5V_SUS_PCH_V5REFSUS 23
AJ26
USB
AA26 VCCCORE
VCCASW_4_CLK
LVDS
DCPSUS_4_USB AN23 NC NC-ed per DG AJ27 VCCCORE
AA27 VCCASW_5_CLK AJ29
PP1V8_S0_PCH_VCCTX_LVDS_F 23
VCCCORE
AA29 VCCASW_6_CLK VCCSUS3_3_1_USB AN24 =PP3V3_SUS_PCH_VCCSUS 8 23
AJ31 VCCTX_LVDS AM37
AA31 VCCCORE AM38
VCCASW_7_CLK VCCTX_LVDS
C
AC26
AC27
VCCASW_8_CLK
VCCASW_9_CLK
V5REF P34 =PP5V_S0_PCH_V5REF 23
8 =PP1V05_S0_PCH_VCCIO_PLLPCIE AN19 VCCIO_28_PLLPCIE
VCCTX_LVDS
VCCTX_LVDS
AP36
AP37 C
AC29 VCCASW_10_CLK VCCSUS3_3_2_GPIO N20 =PP3V3_SUS_PCH_VCCSUS_GPIO 8 23
TP_1V05_S0_PCH_VCCAPLLEXP BJ22 VCCAPLLEXP
CLK/MISC
AC31 VCCASW_11_CLK VCCSUS3_3_3_GPIO N22
=PP3V3_S0_PCH_VCC3_3_HVCMOS 8 23
AD29 VCCASW_12_CLK VCCSUS3_3_4_GPIO P20 23 8 =PP1V05_S0_PCH_VCCIO AN16 VCCIO_15_FDI
VCC3_3_6_HVCMOS V33
HVCMOS
AD31 VCCASW_13_CLK VCCSUS3_3_5_GPIO P22 AN17 VCCIO_16_FDI
PCI/GPIO/
W21 VCCASW_14_CLK
W23 VCC3_3_1_GPIO AA16 =PP3V3_S0_PCH_VCC3_3_GPIO 8 23
AN21 VCCIO_17_PCIE VCC3_3_7_HVCMOS V34
VCCASW_15_CLK
LPC
VCC3_3_8_GPIO W16 AN26 VCCIO_18_PCIE
VCCIO
W24 VCCASW_16_CLK
W26 VCC3_3_4_GPIO T34 AN27 VCCIO_19_PCIE
VCCASW_17_CLK AP21
W29 VCCIO_20_PCIE
VCCASW_18_CLK AP23 VCCIO_21_PCIE VCCVRM_3_DMI AT16 =PP1V8R1V5_S0_PCH_VCCVRM 8 21
W31 VCCASW_19_CLK VCC3_3_2_SATA AJ2 =PP3V3_S0_PCH_VCC3_3_SATA 8 23
AP24
W33 VCCIO_22_PCIE
PCH output, for decoupling only VCCASW_20_CLK
DMI
VCCIO_5_PLLSATA AF13 =PP1V05_S0_PCH_VCCIO_SATA 8 17 21 23
AP26 VCCIO_23_PCIE VCCDMI_1_DMI AT20 =PP1V05_S0_PCH_VCC_DMI 8 23
PLACE_NEAR=U1800.N16:2.54mm
PPVOUT_G3_PCH_DCPRTC N16 DCPRTC AT24 VCCIO_24_PCIE
MIN_LINE_WIDTH=0.2 mm VCCIO_12_SATA3 AH13
MIN_NECK_WIDTH=0.2 mm VCCCLKDMI AB36 PP1V05_S0_PCH_VCCCLKDMI_F 23
1 VOLTAGE=3.3V
=PP1V8R1V5_S0_PCH_VCCVRM Y49 VCCVRM_4_CLK VCCIO_13_SATA3 AH14 AN33 VCCIO_25_DP
C2210 21 8
AN34 VCCIO_26_DP
0.1UF 23 PP1V05_S0_PCH_VCCADPLLA_F BD47 VCCADPLLA VCCIO_6_PLLSATA3 AF14
20%
10V
CERM 2 23 PP1V05_S0_PCH_VCCADPLLB_F BF47 VCCADPLLB 23 8 =PP3V3_S0_PCH_VCC3_3_PCI BH29 VCC3_3_3_PCIE
VCCAPLLSATA AK1 NC VCCAPLLSATA pin left as NC per DG
SATA
402 =PP1V8_S0_PCH_VCC_DFTERM 8 20 23
23 21 8 =PP1V05_S0_PCH_VCCIO_CLK AF17 VCCIO_7_CLK
VCCVRM_1_SATA AF11 =PP1V8R1V5_S0_PCH_VCCVRM 8 21 VCCDFTERM AG16
21 8 =PP1V8R1V5_S0_PCH_VCCVRM AP16 VCCVRM_2_FDI
23 17 8 =PP1V05_S0_PCH_VCCDIFFCLK AF33 VCCDIFFCLKN VCCDFTERM AG17
VCCIO_2_SATA AC16 =PP1V05_S0_PCH_VCCIO_SATA
DFT/SPI
8 17 21 23
55mA Max, 5mA Idle AF34 VCCDIFFCLKN VCCAFDIPLL pin left as NC per DG BG6 VCCAFDIPLL VCCDFTERM AJ16
FDI
VCCIO_3_SATA AC17 NC
AG34 VCCDIFFCLKN VCCDFTERM AJ17
VCCIO_4_SATA AD17 8 =PP1V05_S0_PCH_VCCIO_PLLFDI AP17 VCCIO_27_PLLFDI
23 8 =PP1V05_S0_PCH_VCCSSC AG33 VCCSSC
8 =PP1V05_S0_PCH_VCCDMI_FDI AU20 VCCDMI_2_FDI VCCSPI V1 =PP3V3_SUS_PCH_VCC_SPI 8 23
PPVOUT_S0_PCH_DCPSST V16 DCPSST VCCASW_22_MISC T21 =PP1V05_S0_PCH_VCCASW 8 21 23

MISC
B C2222 1
VOLTAGE=3.3V
NC-ed per DG NC
T17 DCPSUS_1_CLK
V19 DCPSUS_2_CLK
VCCASW_23_MISC V21
VCCASW_21_MISC T19
B
0.1UF PLACE_NEAR=U1800.V16:2.54mm NC
20%
10V
CERM 2
CPU
402 23 8 =PP1V05_S0_PCH_V_PROC_IO BJ8 V_PROC_IO

VCCSUSHDA P32 =PP3V3R1V5_S0_PCH_VCCSUSHDA
HDA
8 23 25
=PPVRTC_G3_PCH A22 VCCRTC 10 mA Max, 1mA Idle

RTC
18 17 8
C2231 1 1 C2232 1 C2233

1UF 0.1UF 0.1UF
10% 20% 20%
6.3V 2 2 10V 10V
2 CERM
CERM CERM
402 402 402
PLACE_NEAR=U1800.A22:2.54mm PLACE_NEAR=U1800.A22:2.54mm
PLACE_NEAR=U1800.A22:2.54mm
A SYNC_MASTER=D2_CLEAN SYNC_DATE=03/19/2012 A
PAGE TITLE
PCH POWER
DRAWING NUMBER SIZE

REVISION
R
4.18.0
22 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
OMIT_TABLE
H5 U1800 AK38
AY4 VSS U1800 VSS H46
VSS VSS AY42 VSS PANTHERPOINT K18
AA17 PANTHERPOINT AK4 VSS
VSS VSS AY46 VSS MOBILE K26
AA2 MOBILE AK42 FCBGA VSS
VSS VSS AY8 VSS K39
AA3 FCBGA AK46 (10 OF 10) VSS
VSS VSS B11 VSS VSS K46
AA33 (9 OF 10) AK8 VSS
VSS VSS B15 VSS K7
AA34 VSS AL16 VSS
VSS VSS B19 VSS L18
AB11 AL17 VSS
VSS VSS B23 VSS L2
AB14 AL19 VSS
VSS VSS B27 VSS L20
AB39 AL2 VSS
VSS VSS B31 VSS L26
AB4 AL21 VSS
VSS VSS
D AB43
AB5
VSS VSS AL23
AL26
B35 VSS
B39 VSS
VSS
VSS
L28
L36 D
VSS VSS B7 VSS L48
AB7 AL27 VSS
VSS VSS F45 VSS M12
AC19 AL31 VSS
VSS VSS BB12 VSS P16
AC2 AL33 VSS
VSS VSS BB16 VSS M18
AC21 AL34 VSS
AC24 AL48 VSS
AC33 AM11 VSS
AC34 AM14 VSS
AC48 AM36 VSS
AD10 AM39 VSS
AD11 AM43 VSS
VSS VSS BB4 VSS M4
AD12 AM45 VSS
AD13 AM46 VSS
VSS VSS BC14 VSS M46
AD19 AM7 VSS
VSS VSS BC18 VSS M8
AD24 AN2 VSS
VSS VSS BC2 VSS N18
AD26 AN29 VSS
VSS VSS BC22 VSS P30
AD27 AN3 VSS
VSS VSS BC26 VSS N47
AD33 AN31 VSS
AD34 AP12 VSS
AD36 AP19 VSS
VSS VSS BC36 VSS T33
AD37 AP28 VSS
AD38 AP30 VSS
AD39 AP32 VSS
AD4 AP38 VSS
VSS VSS BD46 VSS P7
AD40 AP4 VSS
VSS VSS BD5 VSS R2
AD42 AP42 VSS
C AD43
VSS
VSS
VSS
VSS AP46
BE22 VSS
BE26 VSS
VSS
VSS
R48
T12
C
AD45 VSS VSS AP8
BE40 VSS VSS T31
AD46 VSS VSS AR2
BF10 VSS VSS T37
AD8 VSS VSS AR48
BF12 VSS VSS T4
AE2 VSS VSS AT11
BF16 VSS VSS W34
AE3 VSS VSS AT13
BF20 VSS VSS T46
AF10 VSS VSS AT18
BF22 VSS VSS T47
AF12 VSS VSS AT22
BF24 VSS VSS T8
AD14 VSS VSS AT26
BF26 VSS VSS V11
AD16 VSS VSS AT28
BF28 VSS VSS V17
AF16 VSS VSS AT30
BD3 VSS VSS V26
AF19 VSS VSS AT32
BF30 VSS VSS V27
AF24 VSS VSS AT34
BF38 VSS VSS V29
AF26 VSS VSS AT39
BF40 VSS VSS V31
AF27 VSS VSS AT42
BF8 VSS VSS V36
AF29 VSS VSS AT46
BG17 VSS VSS V39
AF31 VSS VSS AT7
BG21 VSS VSS V43
AF38 VSS VSS AU24
BG33 VSS VSS V7
AF4 VSS VSS AU30
BG44 VSS VSS W17
AF42 VSS VSS AV11
BG8 VSS VSS W19
AF46 VSS VSS AV16
BH11 VSS VSS W2
AF5 VSS VSS AV20
BH15 VSS VSS W27
AF7 VSS VSS AV24
BH17 VSS VSS W48
AF8 VSS VSS AV30
BH19 VSS VSS Y12
AG19 VSS VSS AV38
H10 VSS VSS Y38
AG2 VSS VSS AV4
B AG31
AG48
VSS VSS AV43
AV8
BH27 VSS
BH31 VSS
VSS
VSS
Y4
Y42 B
VSS VSS BH33 VSS Y46
AH11 AW14 VSS
VSS VSS BH35 VSS Y8
AH3 AW18 VSS
VSS VSS BH39 VSS
AH36 VSS VSS AW2
BH43 VSS
AH39 VSS VSS AW22
BH7 VSS VSS BG29
AH40 VSS VSS AW26
D3 VSS VSS N24
AH42 VSS VSS AW28
D12 VSS VSS AJ3
AH46 VSS VSS AW32
D16 VSS VSS AD47
AH7 VSS VSS AW34
D18 VSS
AJ19 VSS VSS AW36
D22 VSS VSS B43
AJ21 VSS VSS AW40
D24 VSS VSS BE10
AJ24 VSS VSS AW48
D26 VSS VSS BG41
AJ33 VSS VSS AY12
D30 VSS
AJ34 VSS VSS AY22
D32 VSS VSS G14
AK12 VSS VSS AY28
D34 VSS VSS H16
AK3 VSS D38 VSS
D42 VSS VSS T36
D8 VSS
E18 VSS VSS BG22
E26 VSS VSS BG24
G18 VSS VSS C22
G20 VSS VSS AP13
G26 VSS VSS M14
G28 VSS VSS AP3
A G36 VSS
G48 VSS
VSS
VSS
AP1
BE16 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
H12 VSS BC16
H18 VSS
VSS
VSS BG28 PCH GROUNDS
H22 VSS BJ28 DRAWING NUMBER SIZE
VSS
H24 VSS Apple Inc. 051-9589 D
H26 VSS REVISION
H30 VSS
R
4.18.0
H32 VSS NOTICE OF PROPRIETARY PROPERTY: BRANCH
H34 VSS THE INFORMATION CONTAINED HEREIN IS THE

F3 VSS THE POSESSOR AGREES TO THE FOLLOWING: PAGE
23 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
21 8 =PP3V3_SUS_PCH_VCCSUS 17 8 =PP3V3_S0_PCH
8 =PP5V_SUS_PCH PCH V5REF_SUS Filter & Follower 25 8 =PP5V_S0_PCH PCH V5REF Filter & Follower
21 8 =PP3V3_S0_PCH_VCC3_3_GPIO 21 8 =PP1V05_S0_PCH_VCCSSC
1 mA S0-S5 (PCH Reference for 5V Tolerance on USB) 1 mA (PCH Reference for 5V Tolerance on PCI)
4 1
R2404 2
2 D2400 R2405 2
5 D2400 C2475 1
10 100 1UF
5% NC BAT54DW-X-G 5% NC BAT54DW-X-G 1 C2486 1 C2485
NC
NC
1/16W 1/16W 10%
MF-LF 3
SOT-363
MF-LF 6
SOT-363 0.1UF 0.1UF 6.3V 2
402 1 402 1 10% 10% CERM
25V 25V 402
2 X5R 2 X5R
PLACE_NEAR=U1800.AG33:2.54mm
PP5V_SUS_PCH_V5REFSUS PP5V_S0_PCH_V5REF 402 402
MIN_LINE_WIDTH=0.3 MM MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM <1 mA S0-S5 MIN_NECK_WIDTH=0.2 MM <1 mA PLACE_NEAR=U1800.T34:2.54mm
VOLTAGE=5V VOLTAGE=5V PLACE_NEAR=U1800.AA16:2.54mm
C2438 1 MAKE_BASE=TRUE C2439 1 MAKE_BASE=TRUE
D
0.1UF
20%
10V
CERM 2
=PP5V_SUS_PCH_V5REFSUS 21
1UF
10%
10V
X5R 2
=PP5V_S0_PCH_V5REF 21 21 17 8 =PP1V05_S0_PCH_VCCDIFFCLK D
402 402
PLACE_NEAR=U1800.M26:2.54mm PLACE_NEAR=U1800.P34:2.54mm 21 8 =PP3V3_S0_PCH_VCC3_3_HVCMOS C2434 1
1UF
10%
C2424 1 6.3V 2
CERM
0.1UF 402
10% PLACE_NEAR=U1800.AF34:2.54mm
16V
X7R-CERM 2
0402
PLACE_NEAR=U1800.V33:2.54mm
NO STUFF PP1V8_S0_PCH_VCCTX_LVDS_F 21
MIN_LINE_WIDTH=0.5 MM =PP1V05_S0_PCH_VCCIO_CLK
L2407 MIN_NECK_WIDTH=0.25 MM
VOLTAGE=1.8V
21 8
=PP1V8_S0_PCH_VCCTX_LVDS 0.1UH
8
1 2 21 8 =PP3V3_S5_PCH_VCCDSW 21 8 =PP3V3_S0_PCH_VCC3_3_PCI C2469 1
1UF
0805 10%
NOSTUFF NO STUFF C2499 1 C2421 1 6.3V 2
CERM
NO STUFF 1
R2401 0.1UF 0.1UF 402
C2400 1 1 C2406 1 C2408 5%
0 20%
10V
10%
16V PLACE_NEAR=U1800.AF17:2.54mm
22UF 0.01UF 0.01UF CERM 2 X7R-CERM 2
20% 10% 10% 1/20W 402 0402
6.3V MF
X5R-CERM-1 2 2 16V
X7R-CERM 2 16V
X7R-CERM 2 201 PLACE_NEAR=U1800.T16:2.54mm PLACE_NEAR=U1800.BH29:2.54mm
603 0402 0402 PLACE_NEAR=U1800.AM37:2.54MM
PLACE_NEAR=U1800.AM37:2.54mm 21 17 8 =PP1V05_S0_PCH_VCCIO_SATA
PLACE_NEAR=U1800.AM37:2.54mm
PLACE_NEAR=U1800.AM37:2.54mm
21 8 =PP3V3_SUS_PCH_VCC_SPI 21 8 =PP3V3_S0_PCH_VCC3_3_SATA
C2444 1 C2452 1
C2442 1 C2423 1 1UF 1UF

8 =PP3V3_S0_PCH_VCCADAC R2450 PP3V3_S0_PCH_VCCA_DAC_F 21
1UF 0.1UF
10%
6.3V
10%
6.3V
1
0 2
MIN_LINE_WIDTH=0.4 MM 10% 10% CERM 2 CERM 2
MIN_NECK_WIDTH=0.2 MM 6.3V 16V 402 402
VOLTAGE=3.3V CERM 2 X7R-CERM 2
5%
C 1/20W
MF
201
402 0402
PLACE_NEAR=U1800.AJ2:2.54mm
PLACE_NEAR=U1800.AH13:2.54mm
PLACE_NEAR=U1800.AC17:2.54mm C
PCH VCCIO BYPASS
C2450 1 1 C2451 1 C2455 (PCH USB 1.05V PWR)
10UF 0.1UF 0.01UF
20%
6.3V 2
10% 10% 21 8 =PP3V3_SUS_PCH_VCCSUS_GPIO 21 8 =PP1V05_S0_PCH_VCCIO_USB
X5R 2 16V
X7R-CERM 2 16V
X7R-CERM
603 0402 0402
PLACE_NEAR=U1800.U48:2.54mm
C2476 1 C2446 1
PLACE_NEAR=U1800.U48:2.54mm 1UF 1UF

PLACE_NEAR=U1800.U48:2.54mm 10% 10%
6.3V 6.3V
CERM 2 CERM 2
402 402
PLACE_NEAR=U1800.P22:2.54mm PLACE_NEAR=U1800.P28:2.54mm
PCH VCCSUS3_3 BYPASS

(PCH SUSPEND USB 3.3V PWR)
21 8 =PP3V3_SUS_PCH_VCCSUS_USB 21 8 =PP1V05_S0_PCH_VCCIO
CRITICAL
L2451
8 =PP3V3_S0_PCH_VCC3_3_CLK R2451 10UH-0.12A-0.36OHM PP3V3_S0_PCH_VCC3_3_CLK_F 21
1 C2484 1 C2413 C2401 1 1 C2429 1 C2414 1 C2407 1 C2463
1
1 2 PP3V3_S0_PCH_VCC3_3_CLK_R 1 2 MIN_LINE_WIDTH=0.5 MM 0.1UF 0.1UF 10UF 1UF 1UF 1UF 1UF
MIN_NECK_WIDTH=0.075 MM 10% 10% 20% 10% 10% 10% 10%
MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V
5% MIN_NECK_WIDTH=0.075 MM 0603 2 16V
X7R-CERM 2 16V
X7R-CERM
6.3V 2
X5R 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1/16W VOLTAGE=3.3V 0402 0402 603 402 402 402 402
MF-LF
402
C2453 1 1 C2454 PLACE_NEAR=U1800.P24:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
PLACE_NEAR=U1800.AN27:2.54mm
10UF 1UF PLACE_NEAR=U1800.AN27:2.54mm
20% 10% PLACE_NEAR=U1800.AN27:2.54mm
6.3V 10V
X5R 2 2 X5R PLACE_NEAR=U1800.AN27:2.54mm
603 402
PLACE_NEAR=U1800.T38:2.54mm
PLACE_NEAR=U1800.T38:2.54mm PCH VCCSUSHDA BYPASS 21 8 =PP1V05_S0_PCH_VCCASW
B CRITICAL PCH VCCADPLLA Filter
25 21 8 =PP3V3R1V5_S0_PCH_VCCSUSHDA
B
L2490 (PCH DPLLA PWR) C2441 1 C2420 1 C2428 1 1 C2426 1 C2456 1 C2496
8 =PP1V05_S0_PCH_VCCADPLL R2490 10UH-0.12A-0.36OHM PP1V05_S0_PCH_VCCADPLLA_F 21
0.1UF 22UF 22UF 1UF 1UF 1UF
0 MIN_LINE_WIDTH=0.4 MM 20% 20% 20% 10% 10% 10%
1 2 PP1V05_S0_PCH_VCCADPLLA_R 1 2 MIN_NECK_WIDTH=0.2 MM 68 mA 10V
CERM 2
6.3V
X5R-CERM-1 2
6.3V
X5R-CERM-1 2
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
MIN_LINE_WIDTH=0.4 MM 0603
VOLTAGE=1.05V 402 603 603 402 402 402
5% MIN_NECK_WIDTH=0.2 MM
1/16W VOLTAGE=1.05V PLACE_NEAR=U1800.P32:2.54mm
MF-LF
402
CRITICAL NO STUFF PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
C2491 1 1 C2492 PLACE_NEAR=U1800.AC27:2.54mm
PLACE_NEAR=U1800.AC27:2.54mm
220UF 1UF PLACE_NEAR=U1800.AC27:2.54mm
(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH) 20% 10% PCH VCCCORE BYPASS
2.5V 2 6.3V
2 CERM
TANT
B16 402 21 20 8 =PP1V8_S0_PCH_VCC_DFTERM (PCH 1.05V CORE PWR)
21 8 =PP1V05_S0_PCH_VCC_CORE
PLACE_NEAR=U1800.BD47:2.54MM
PLACE_NEAR=U1800.BD47:2.54MM C2440 1
0.1UF
20%
CRITICAL PCH VCCADPLLB Filter 10V
CERM 2 C2460 1 1 C2481 1 C2482 1 C2483
L2491 (PCH DPLLB PWR) 402 10UF
20%
1UF
10%
1UF
10%
1UF
10%
R2491 10UH-0.12A-0.36OHM PP1V05_S0_PCH_VCCADPLLB_F 21
PLACE_NEAR=U1800.AJ16:2.54mm 6.3V
X5R 2
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
1 2 PP1V05_S0_PCH_VCCADPLLB_R 1 2 MIN_NECK_WIDTH=0.2 MM 69 mA 603 402 402 402
MIN_LINE_WIDTH=0.4 MM 0603 VOLTAGE=1.05V
5% MIN_NECK_WIDTH=0.2 MM PLACE_NEAR=U1800.AG26:2.54mm
1/16W VOLTAGE=1.05V PLACE_NEAR=U1800.AD21:2.54mm
MF-LF
402
CRITICAL NO STUFF =PP1V05_S0_PCH_V_PROC_IO PLACE_NEAR=U1800.AG24:2.54mm
PLACE_NEAR=U1800.AJ27:2.54mm
C2493 1 1 C2494 21 8
220UF 1UF
(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH) 20% 10%
2.5V 2 6.3V
2 CERM
TANT
B16 402 C2416 1 1 C2417 1 C2430
4.7UF 0.1UF 0.1UF
PLACE_NEAR=U1800.BF47:2.54MM 20% 10% 10%
PLACE_NEAR=U1800.BF47:2.54MM 6.3V 2 16V
2 X7R-CERM 16V
2 X7R-CERM
X5R
402 0402 0402
A CRITICAL
L2406
SYNC_MASTER=D2_CLEAN SYNC_DATE=03/19/2012 A
PAGE TITLE
10UH-0.58A-0.35OHM R2415
17 8 =PP1V05_S0_PCH
1 2 PP1V05_S0_PCH_VCCCLKDMI_R 1
0 2
PP1V05_S0_PCH_VCCCLKDMI_F
21
PCH DECOUPLING
1098AS-SM MIN_LINE_WIDTH=0.5 MM VOLTAGE=1.05V DRAWING NUMBER SIZE
MIN_NECK_WIDTH=0.25 MM 5%
(Z = 1.2MM, PLACE ON SHORT SIDE BEHIND PCH) VOLTAGE=1.05V 1/16W
MF-LF
21 8 =PP1V05_S0_PCH_VCC_DMI
402 REVISION
C2419 1 R
4.18.0
C2411 1 1UF NOTICE OF PROPRIETARY PROPERTY: BRANCH
10%
10UF 6.3V
20% CERM 2 THE INFORMATION CONTAINED HEREIN IS THE
6.3V 402
X5R 2 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PLACE_NEAR=U1800.AT20:2.54mm
PLACE_NEAR=U1800.AB36:2.54mm
603 PCH VCCIO BYPASS I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
24 OF 132
PCH VCC3_3 BYPASS
(PCH PCI 3.3V PWR)
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
24 8 =PPVCCIO_S0_XDP CPU Micro2-XDP 24 8 =PPVCCIO_S0_XDP
CRITICAL NOTE: This is not the standard XDP pinout. XDP PLACE_NEAR=J2500.52:2.54mm
XDP_CONN Use with 921-0133 Adapter Flex to 89 24 11 XDP_CPU_TDO R2510 51 2 1
5% 1/20W MF 201
=PP3V3_S0_XDP J2500 support chipset debug.
8 XDP PLACE_NEAR=U1000.K61:2.54mm
DF40RC-60DP-0.4V
NO STUFF M-ST-SM 89 24 11 XDP_CPU_TDI R2511 51 2 1
1 5% 1/20W MF 201
R2540 62 61 XDP PLACE_NEAR=U1000.H59:2.54mm
1K
5% 89 24 11 XDP_CPU_TMS R2512 51 2 1
1/16W 5% 1/20W MF 201
MF-LF
402 2 1 XDP PLACE_NEAR=U1000.J58:2.54mm
2
XDP_CPU_PREQ_L OBSFN_A0 4 3
OBSFN_C0 CPU_CFG<16> XDP_CPU_TCK R2513 51 2 1
D
89 11
89 11
BI
IN XDP_CPU_PRDY_L OBSFN_A1 6
8
5
7
OBSFN_C1 CPU_CFG<17>
IN
IN
10 89
10 89
89 24 11
XDP
5% 1/20W MF
PLACE_NEAR=U1000.H63:2.54mm
201
D
89 24 11 XDP_CPU_TRST_L R2514 51 2 1
(R2560-R2563) 89 11 IN XDP_BPM_L<0> OBSDATA_A0 10 9 OBSDATA_C0 CPU_CFG<0> IN 10 24 89 5% 1/20W MF 201
XDP_CPU:BPM 89 11 IN XDP_BPM_L<1> OBSDATA_A1 12 11

OBSDATA_C1 CPU_CFG<1> IN 10 89
89 11 IN XDP_BPM_L<4> R2560 0 1 2 14 13
5% 1/20W MF 201
89 11 IN XDP_BPM_L<5> R2561 0 1 2 89 11 IN XDP_BPM_L<2> OBSDATA_A2 16 15
5% 1/20W MF 201
89 11 IN XDP_BPM_L<6> R2562 0 1 2 89 11 IN XDP_BPM_L<3> OBSDATA_A3 18 17
5% 1/20W MF 201
89 11 IN XDP_BPM_L<7> R2563 0 1 2 20 19
5% 1/20W MF 201
89 10 IN CPU_CFG<10> OBSFN_B0 22 21 OBSFN_D0 CPU_CFG<8> IN 10 89
(R2564-R2567) 89 10 IN CPU_CFG<11> OBSFN_B1 24 23 OBSFN_D1 CPU_CFG<9> IN 10 89
XDP_CPU:CFG 26 25
89 10 IN CPU_CFG<12> R2564 0 1 2 XDP_OBSDATA_B<0> OBSDATA_B0 28 27 OBSDATA_D0 CPU_CFG<4> IN 10 89

5% 1/20W MF 201
89 10 IN CPU_CFG<13> R2565 0 1 2 XDP_OBSDATA_B<1> OBSDATA_B1 30 29
OBSDATA_D1 CPU_CFG<5> IN 10 89
5% 1/20W MF 201
89 10 IN CPU_CFG<14> R2566 0 1 2 32 31
5% 1/20W MF 201
89 10 IN CPU_CFG<15> R2567 0 1 2 XDP_OBSDATA_B<2> OBSDATA_B2 34 33
OBSDATA_D2 CPU_CFG<6> IN 10 89
5% 1/20W MF 201 XDP PLACE_NEAR=R1841.1:2.54mm
XDP_OBSDATA_B<3> OBSDATA_B3 36 35 OBSDATA_D3 CPU_CFG<7> IN 10 89
R2515 0 1 2 ITPXDP_CLK100M_P IN 17 89
38 37
XDP 5% 1/20W MF 201
89 20 11 IN CPU_PWRGD R2500 1K 1 2 89 XDP_CPU_PWRGD PWRGD/HOOK0 40 39 ITPCLK/HOOK4 89 XDP_CPU_CLK100M_P XDP PLACE_NEAR=R1840.1:2.54mm
PLACE_NEAR=U1000.C60:2.54mm 5% 1/20W MF 201
R2516 0
XDP_CPU_PWRBTN_L HOOK1 42 41 ITPCLK#/HOOK5 89 XDP_CPU_CLK100M_N 1 2 ITPXDP_CLK100M_N IN 17 89
XDP 5% 1/20W MF 201
PM_PWRBTN_L R2502 0 1 2
VCC_OBS_AB 44 43 VCC_OBS_CD
41 24 18 OUT
PLACE_NEAR=U4900.P17:2.54mm 5% 1/20W MF 201 XDP_CPU_CFG<0> HOOK2 46 45
RESET#/HOOK6 XDP_CPURST_L XDP PLACE_NEAR=U1000.G3:2.54mm
XDP XDP_VR_READY HOOK3 48 47
DBR#/HOOK7 XDP_DBRESET_L OUT 11 24 25 89 R2505 1K 1 2 CPU_RESET_L IN 11 25
5% 1/20W MF 201
89 24 10 OUT CPU_CFG<0> R2501 1K 1 2 50 49 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
PLACE_NEAR=U1000.B57:2.54mm 5% 1/20W MF 201
44 24 BI =SMBUS_XDP_SDA SDA 52 51
TDO XDP_CPU_TDO IN 11 24 89
XDP
PM_PCH_SYS_PWROK R2504 330 1 2
44 24 IN =SMBUS_XDP_SCL SCL 54 53
TRSTn XDP_CPU_TRST_L OUT 11 24 89
70 41 18 OUT
5% 1/20W MF 201 TCK1 NC
56 55
TDI XDP_CPU_TDI OUT 11 24 89
C 89 24 11 OUT XDP_CPU_TCK TCK0 58
60
57
59
TMS
XDP_PRESENT#
XDP_CPU_TMS OUT 11 24 89
C
(R2520-R2537) XDP XDP
XDP SIGNALS XDP PCH SIGNALS C2500 1
64 63
1 C2501
PCH SIGNALS Non-XDP Signals
0.1UF 0.1UF
24 OUT XDP_DA0_USB_EXTA_OC_L R2520 33 1 2 XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L IN 19 24
10%
16V
10%
16V
24 OUT XDP_DA1_USB_EXTB_OC_L R2521 33 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L IN 19 24
X7R-CERM
0402
2
998-2516 2 X7R-CERM
0402
24 OUT XDP_DA2_USB_EXTC_OC_L R2522 33 1 2 XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L IN 19 24 19 OUT XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L R2590 0 1 2 USB_EXTA_OC_L IN 40
5% 1/20W MF 201 5% 1/20W MF 201
24 OUT XDP_DA3_USB_EXTD_OC_L R2523 33 1 2 XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L IN 19 24 19 OUT XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L R2591 0 1 2 USB_EXTB_OC_L IN 7 38
5% 1/20W MF 201 5% 1/20W MF 201
24 19 IN XDP_DB2_PCH_GPIO10_AP_PWR_EN R2596 0 1 2 AP_PWR_EN OUT 19 34 70
5% 1/20W MF 201
24 OUT XDP_DB0_USB_EXTB_OC_EHCI_L R2524 33 1 2 XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L IN 19 24 19 OUT XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE R2597 0 1 2 SDCONN_STATE_CHANGE IN 25
5% 1/20W MF 201 5% 1/20W MF 201
24 OUT XDP_DB1_USB_EXTD_OC_EHCI_L R2525 33 1 2 XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L IN 19
5% 1/20W MF 201 NOTE: This is not the standard XDP pinout. 24 17 IN XDP_DC3_PCH_GPIO19_SATARDRVR_EN R2573 0 1 2 SATARDRVR_EN OUT 17
24 IN XDP_DB2_AP_PWR_EN R2526 33 1 2 XDP_DB2_PCH_GPIO10_AP_PWR_EN OUT 19 24 5% 1/20W MF 201
XDP_DB3_SDCONN_STATE_CHANGE R2527 33 1 2
5% 1/20W MF 201
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
Use with 921-0133 Adapter Flex to
24 OUT IN 19 24
5% 1/20W MF 201 support chipset debug. 24 20 OUT XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L R2570 0 1 2 ISOLATE_CPU_MEM_L OUT 27
24 OUT XDP_FC0 R2528 33 1 2 XDP_FC0_PCH_GPIO15 IN 20 5% 1/20W MF 201
5% 1/20W MF 201
24 17 IN XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL R2572 0 1 2 DP_AUXCH_ISOL OUT 17 25
5% 1/20W MF 201
XDP_FC1 R2529 33 1 2 XDP_FC1_PCH_GPIO0
24 OUT
5% 1/20W MF 201
IN 20 24
24 20 OUT XDP_FC1_PCH_GPIO0 R2574 1K 1 2
5% 1/20W MF 201
TBT_CIO_PLUG_EVENT_ISOL IN 20
24 IN XDP_DC0_ISOLATE_CPU_MEM_L R2530 33 1 2 XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L OUT 20 24
24 IN XDP_DC1_MXM_GOOD R2531 33 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
XDP_DC1_PCH_GPIO35_MXM_GOOD OUT 20 PCH Micro2-XDP =PP3V3_S5_XDP 8
24 IN XDP_DC2_DP_AUXCH_ISOL R2532 33 1 2 XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL OUT 17 24

5% 1/20W MF 201
24 IN XDP_DC3_SATARDRVR_EN R2533 33 1 2 XDP_DC3_PCH_GPIO19_SATARDRVR_EN OUT 17 24 CRITICAL
5% 1/20W MF 201
24 IN XDP_DD0_DP_GPU_TBT_SEL R2534 33 1 2 XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL OUT 20 XDP_CONN
5% 1/20W MF 201
24 IN XDP_DD1_JTAG_ISP_TCK R2535 33 1 2 XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK OUT 20 24 J2550
5% 1/20W MF 201
DF40RC-60DP-0.4V 24 20 OUT XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK R2575 0 1 2 JTAG_ISP_TCK OUT 20
M-ST-SM 5% 1/20W MF 201
24 IN XDP_DD2_AUD_IPHS_SWITCH_EN R2536 33 1 2 XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH OUT 20 24 24 20 OUT XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH R2576 0 1 2 AUD_IPHS_SWITCH_EN_PCH OUT 20 25
5% 1/20W MF 201 5% 1/20W MF 201
24 IN XDP_DD3_ENET_LOW_PWR R2537 33 1 2 XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH OUT 20 24
62 61 24 20 OUT XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH R2577 0 1 2 ENET_LOW_PWR_PCH OUT 9 20 25
5% 1/20W MF 201 5% 1/20W MF 201
B PCH/XDP Signal Isolation Notes: 2 1

B
- Following Intel’s Debug Prot Design Guid for HR and CR v1.3 TP_XDP_PCH_OBSFN_A<0> OBSFN_A0 4 3
OBSFN_C0 XDP_FC0 24
doc id 404081. TP_XDP_PCH_OBSFN_A<1> OBSFN_A1 6 5

OBSFN_C1 XDP_FC1 24
Initially, stuffing both 33 and 0 ohms and validate whether 8 7
it is functional in that state, else add BOM options. 24 XDP_DA0_USB_EXTA_OC_L OBSDATA_A0 10 9

OBSDATA_C0 XDP_DC0_ISOLATE_CPU_MEM_L 24
- For isolated GPIOs: 24 XDP_DA1_USB_EXTB_OC_L OBSDATA_A1 12 11 OBSDATA_C1 XDP_DC1_MXM_GOOD 24
- ’Output’ non-XDP signals require pulls. 14 13
- ’Output’ PCH/XDP signals require pulls. 24 XDP_DA2_USB_EXTC_OC_L OBSDATA_A2 16 15

OBSDATA_C2 XDP_DC2_DP_AUXCH_ISOL 24
24 XDP_DA3_USB_EXTD_OC_L OBSDATA_A3 18 17 OBSDATA_C3 XDP_DC3_SATARDRVR_EN 24

20 19 8 =PP1V05_SUS_PCH_JTAG
TP_XDP_PCH_OBSFN_B<0> OBSFN_B0 22 21
OBSFN_D0 TP_XDP_PCH_OBSFN_D<0>
TP_XDP_PCH_OBSFN_B<1> OBSFN_B1 24 23
OBSFN_D1 TP_XDP_PCH_OBSFN_D<1> XDP PLACE_NEAR=J2550.52:2.54mm
26 25 24 17 XDP_PCH_TDO R2550 51 2 1
5% 1/20W MF 201
R252x, R253x, R257x and R259x should be placed where signal path 24 XDP_DB0_USB_EXTB_OC_EHCI_L OBSDATA_B0 28 27 OBSDATA_D0 XDP_DD0_DP_GPU_TBT_SEL 24
XDP PLACE_NEAR=U1800.K5:2.54mm
needs to split between route from PCH to J2550 24 XDP_DB1_USB_EXTD_OC_EHCI_L OBSDATA_B1 30 29
OBSDATA_D1 XDP_DD1_JTAG_ISP_TCK 24
XDP_PCH_TDI R2551 51 2 1
24 17
and path to non-XDP signal destination. 32 31 5% 1/20W MF 201
24 XDP_DB2_AP_PWR_EN OBSDATA_B2 34 33
OBSDATA_D2 XDP_DD2_AUD_IPHS_SWITCH_EN 24 XDP PLACE_NEAR=U1800.H7:2.54mm
24 XDP_DB3_SDCONN_STATE_CHANGE OBSDATA_B3 36 35
OBSDATA_D3 XDP_DD3_ENET_LOW_PWR 24 24 17 XDP_PCH_TMS R2552 51 2 1
5% 1/20W MF 201
38 37
XDP
XDP PLACE_NEAR=U1800.J3:2.54mm
70 41 IN ALL_SYS_PWRGD R2584 1K 1 2 XDP_PCH_S5_PWRGD PWRGD/HOOK0 40 39 ITPCLK/HOOK4 TP_XDP_PCH_HOOK4
PLACE_NEAR=J2550.39:2.54mm 5% 1/20W MF 201 24 17 XDP_PCH_TCK R2556 51 2 1
XDP_PCH_PWRBTN_L HOOK1 42 41 ITPCLK#/HOOK5 TP_XDP_PCH_HOOK5 5% 1/20W MF 201
XDP
PM_PWRBTN_L R2585 0 1 2
VCC_OBS_AB 44 43 VCC_OBS_CD
41 24 18 OUT
PLACE_NEAR=U4900.P17:2.54mm 5% 1/20W MF 201 TP_XDPPCH_HOOK2 HOOK2 46 45 RESET#/HOOK6 XDPPCH_PLTRST_L IN 25 1K series R on PCH Support Page
TP_XDPPCH_HOOK3 HOOK3 48 47
DBR#/HOOK7 XDP_DBRESET_L OUT 11 24 25 89
50 49
NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
A 44 24
44 24
BI =SMBUS_XDP_SDA
=SMBUS_XDP_SCL
SDA
SCL
52
54
51
53
TDO
TRSTn
XDP_PCH_TDO
TP_XDP_PCH_TRST_L
IN 17 24
IN PAGE TITLE
24 17 OUT XDP_PCH_TCK
TCK1
TCK0
NC
56
58
55
57
TDI
TMS
XDP_PCH_TDI
XDP_PCH_TMS
OUT 17 24
OUT 17 24
CPU & PCH XDP
DRAWING NUMBER SIZE
60 59 XDP_PRESENT#
XDP XDP Apple Inc. 051-9589 D
REVISION
C2580 1 1
C2581
0.1UF
64 63
0.1UF
R
4.18.0
10%
16V
10%
16V NOTICE OF PROPRIETARY PROPERTY: BRANCH
X7R-CERM
0402
2
998-2516 2 X7R-CERM
0402 THE INFORMATION CONTAINED HEREIN IS THE
25 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPIO Glitch Prevention PCH Reset Button Platform Reset Connections
25 19 8 =PP3V3_S3_PCH_GPIO
=PP3V3_S0_SB_PM
CRITICAL 8 1 C2650 70 8
Unbuffered R2681 LPC_RESET_L

0.1UF 33 OUT 92
VCC 20% 1
R2695 PLT_RESET_L 1 2 LPCPLUS_RESET_L
U2650
SOT833
10V
2 CERM
4.7K
27 19 IN
MAKE_BASE=TRUE
5%
MAKE_BASE=TRUE OUT 7 43
402
08 XDP
5%
1/16W
1/16W
MF-LF R2683
ENET_LOW_PWR_PCH ENET_LOW_PWR
74LVC2G08GT
24 20 9 IN
1
A1 Y1
7
OUT 9 MF-LF 402 33
R2696 2 402
1 2 SMC_LRESET_L OUT 41
70 25 18 IN PM_PCH_PWROK 2
B1
FW_PWR_EN_PCH 5 3 FW_PWR_EN XDP_DBRESET_L 1
0 2 PM_SYSRST_L
5%
1/16W
20 IN A2 Y2 OUT 9 89 24 11 IN OUT 18 41
6 5% OMIT R2671 MF-LF
402
D
B2
GND
1/16W
MF-LF
402
1
R2697 1
0 2 PCA9557D_RESET_L OUT 33 D
4 0 5%
1/16W
XDP
5%
1/16W
MF-LF
MF-LF
402 R2689
2 402
1K
1 2 XDPPCH_PLTRST_L OUT 24
SILK_PART=SYS RESET 5%
1/16W
25 19 8 =PP3V3_S3_PCH_GPIO R2687 MF-LF
402
0
1 2 DPMUX_LRESET_L
CRITICAL 8 1 C2652 SDCONN_STATE_CHANGE ISOLATION 5%
OUT 82
0.1UF 1/16W
VCC 20% =PP3V3_S3_SDBUF MF-LF
U2652
SOT833
10V
2 CERM
8
=PP3V3_S4_SMC 8 25 42 402
402 1
C2630
08 24 SDCONN_STATE_CHANGE
TBT_PWR_EN_PCH TBT_PWR_EN OUT 0.1UF
74LVC2G08GT
17 IN
1
A1 Y1
7
OUT 20 35
R2641 1
43 41 18 7 IN LPC_PWRDWN_L 2
B1 CRITICAL 2
10%
6.3V
X5R 470K
5%
25 8 =PP3V3_S0_RSTBUF Buffered R2685
0
24 20 IN AUD_IPHS_SWITCH_EN_PCH 5
A2 Y2
3 AUD_IPHS_SWITCH_EN OUT 58
TC7SZ08AFEAPE
SOT665
201
1/20W 1 2 SSD_RESET_L OUT 39
MF
70 25 18 IN PM_PCH_PWROK 6
B2
5
201 2 5%
A
2
CRITICAL 1/16W
MF-LF
GND 4 5 MC74VHC1G08 R2686 402
Y U2630 1 SC70-HF =ENET_RESET_L OUT 38
4
B
1 SDCONN_STATE_CHANGE_RIO IN 7 38 0
U2680 4 PLT_RST_BUF_L 1 2 ENET_RESET_L 7
3 2 MAKE_BASE=TRUE MAKE_BASE=TRUE
5%
42 25 8 =PP3V3_S4_SMC 1/16W
3
1
R2680 MF-LF
402
R2640 1
Q2640 C2680 1 5%
100K =TBT_RESET_L OUT 37
470K SSM6N15FEAPE 0.1UF 1/16W

20% Series R on Pg38, R3803
5% 10V MF-LF R2688
G 2
1/20W SOT563 CERM 2 2 402
MF 0
201 2
402 1 2 AP_RESET_L OUT 34
Q2640 5%
SSM6N15FEAPE 1/16W
R2693
S
G 5
SDCONN_STATE_CHANGE_INV MF-LF
C SOT563 402 0
C
6
BKLT_PLT_RST_L
1
1 2 86
OUT
5%
1/16W
S
42 OUT SDCONN_STATE_CHANGE_SMC MF-LF
402
4
25 8 =PP3V3_S0_RSTBUF Buffered CPU reset
CRITICAL
LPC 33MHz Clock R2655
Series Termination DP_AUXIO_EN INVERSION
R2630
10K
5 U2690
74LVC1G07
SC70
PLACE_NEAR=U1800.N52 37 20 19 18 17 8 =PP3V3_S0_PCH_GPIO 1 2
22 2 4 PLT_RST_CPU_BUF_L CPU_RESET_L OUT 11 24
92 19 IN LPC_CLK33M_SMC_R 1 2 LPC_CLK33M_SMC OUT 41 92 5% DP_AUXIO_EN OUT 84 85 MAKE_BASE=TRUE
1/20W
5% MF NC VTT pullup on CPU page
1/20W
MF
R2656
201
D 3 1 3
1
R2690
PLACE_NEAR=U1800.P53 1
201
22 C2639 1
C2690 1 5%
100K
19 IN LPC_CLK33M_LPCPLUS_R 2 LPC_CLK33M_LPCPLUS OUT 7 43 92
Q2630 0.1UF NC 1/16W
SOD-VESM-HF 0.1UF 20% MF-LF
5% 10% 10V
1/20W
SSM3K15FV 16V CERM 2 2 402
X5R-CERM 2 402
PLACE_NEAR=U1800.P46 R2657 MF
201 1 G S 2 0201
LPC_CLK33M_DPMUX_UC_R 1
22 2 LPC_CLK33M_DPMUX_UC DP_AUXCH_ISOL
OUT 82 24 17 IN
MAKE_BASE=TRUE
5%
TP_PCI_CLK33M_OUT2 1/20W 1 NO STUFF
19 IN R2631
MF
201 R2659 10K
PLACE_NEAR=U1800.P48 1 22 5%
19 IN PCH_CLK33M_PCIOUT 2 PCH_CLK33M_PCIIN OUT 17 92 1/20W
MF
5%
1/20W 2 201
MF
201
B System RTC Power Source & 32kHz / 25MHz Clock Generator PCH ME Disable Strap B
=PPVBAT_G3_SYSCLK PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
8
VDDIO_25M_A: SB power rail for XTAL circuit. If high, ME is disabled. This allows for full re-flashing of SPI ROM.
Coin-Cell: VBAT (300-ohm & 10uF RC)
VDDIO_25M_B: Ethernet power rail for XTAL circuit. SMC controls strap enable to allow in-field control of strap setting.
No Coin-Cell: 3.42V G3Hot (no RC)
VDDIO_25M_C: Thunderbolt power rail for XTAL circuit. Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.
8 =PP3V3_S5_SYSCLK
NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered. 23 8 =PP5V_S0_PCH
Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5
No Coin-Cell: 3.3V S5 R2620
1
100K
GreenClk 25MHz Power 8 =PP3V3_S0_SYSCLK No bypass necessary 5%
1/20W
Q2620 MF
NO STUFF SSM6N37FEAPE 2 201
R2607 SPI_DESCRIPTOR_OVERRIDE_LS5V
G 5
SOT563
0
1 2 SYSCLK_25M_B_GND
MIN_LINE_WIDTH=0.3MM 23 21 8 =PP3V3R1V5_S0_PCH_VCCSUSHDA
Ethernet XTAL Power (Unused on 15" MBP) 5% MIN_NECK_WIDTH=0.2MM
SPI_DESCRIPTOR_OVERRIDE
4 S
1/16W VOLTAGE=0V
+3.42V 13
SB XTAL Power =PPVDDIO_S0_SBCLK MF-LF

VDD_25M 5
+V3.3A 2
3
8
402
TBT XTAL Power 8 =PPVDDIO_TBT_CLK
VBAT and +V3.3A are 1
R2621
internally ORed to Q2620 D 6
5%
1K
NO STUFF create VDD_RTC_OUT. SSM6N37FEAPE 1/20W
C2624 1 C2622 1 C2620 1
1
R2608 C2602 1
SOT563 MF
2 201
0.1UF 0.1UF 0.1UF 5%
0 1UF U2600 +V3.3A should be first
20%
10V
20%
10V
20%
10V 1/16W 10%
10V 2 SLG3NB148A available ~3.3V power HDA_SDOUT_R OUT 17 92
CERM 2 CERM 2 CERM 2 MF-LF X5R TQFN 2 G S 1
402 402 402 2 402 402-1 to reduce VBAT draw. IPD = 9-50k
CRITICAL SPI_DESCRIPTOR_OVERRIDE_L
42 41 IN
11 VDDIO_25M_A 32KHZ_A 12 SYSCLK_CLK32K_RTC OUT 17 91
6 CKPLUS_WAIVE=PwrTerm2Gnd
A C2605 14
VDDIO_25M_B
VDDIO_25M_C 25MHZ_A 9 SYSCLK_CLK25M_SB OUT 17 91 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
12PF R2605 25MHZ_B 8 TP_SYSCLK_CLK25M_ENET PAGE TITLE
2 1 SYSCLK_CLK25M_X2 1
0 2 SYSCLK_CLK25M_X2_R 3 X2 25MHZ_C 15 SYSCLK_CLK25M_TBT OUT 35 91 Chipset Support
5%
5% NO STUFF 4 X1 =PPVRTC_G3_OUT 8 DRAWING NUMBER SIZE
CRITICAL 1/16W
50V MF-LF R2606
1 VDD_RTC_OUT 1 For SB RTC Power 051-9589 D
1
C0G-CERM
0402 NC Y2605 402
1M
Apple Inc. REVISION
THRM
4 2
NC SM-3.2X2.5MM 5% GND
25.000MHZ-12PF-20PPM
1/16W PAD 1 C2610 R
4.18.0
C2606 MF-LF 1UF
10
16
17
3
NOTICE OF PROPRIETARY PROPERTY:

7
12PF 2 402 10% BRANCH

6.3V
2 CERM THE INFORMATION CONTAINED HEREIN IS THE
1 2 SYSCLK_CLK25M_X1 402 PROPRIETARY PROPERTY OF APPLE INC.
NOTE: 30 PPM crystal required
5%
50V
26 OF 132
C0G-CERM SHEET
0402 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM
HUB_ALLREM HUB_NONREM1_0,HUB_NONREM0_0
TABLE_BOMGROUP_ITEM
HUB_1NONREM HUB_NONREM1_0,HUB_NONREM0_1
TABLE_BOMGROUP_ITEM
HUB_2NONREM HUB_NONREM1_1,HUB_NONREM0_0
USB MUX FOR LS/FS INTERNAL DEVICES HUB_3NONREM HUB_NONREM1_1,HUB_NONREM0_1
TABLE_BOMGROUP_ITEM
NON_REM 1 : NON_REM 0 STRAP PIN CFG

BYPASS=U2700.36::2MM
D 26 8 =PP3V3_S3_USB_HUB
BYPASS=U27000.5::5MM 0
0
1
1
:
:
:
:
0
1
0
1
ALL PORTS ARE REMOVABLE
PORT 1 IS NON REMOVABLE
PORT 1&2 ARE NON REMOVABLE
PORT 1&2&3 ARE NON REMOVABLE
D
C2700 1
C2701 1 1
C2702 1
C2703 CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STARPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H
4.7UF 0.1UF 0.1UF 0.1UF
20% 10% 10% 10%
6.3V 16V 16V 16V
2 2 2 2
X5R
603
X7R-CERM
0402
X7R-CERM
0402
X7R-CERM
0402
BOM TABLE TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

BYPASS=U2700.10::2MM CRITICAL
TABLE_5_ITEM
338S0824 1 USB HUB 2514B U2700 USBHUB2514B

BYPASS=U2700.29::2MM TABLE_5_ITEM
BYPASS=U2700.23::5MM BYPASS=U2700.15::2MM 338S0923 1 USB HUB 2513B U2700

CRITICAL USBHUB2513B
TABLE_5_ITEM
338S0983 1 USB HUB 2512B U2700

CRITICAL USBHUB2512B
C2704 1
C2705 1
C2706 1
C2708 1
PPUSB_HUB2_VDD1V8
4.7UF 0.1UF 0.1UF 0.1UF MIN_LINE_WIDTH=0.4MM 15" MBP ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B
20% 10% 10% 10%
6.3V
2
16V
2
16V
2
16V
2 VOLTAGE=1.8V MBP OG ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B
X5R
603
X7R-CERM
0402
X7R-CERM
0402
X7R-CERM
0402 PPUSB_HUB2_VDD1V8PLL
1
C2713 1
C2714
MIN_LINE_WIDTH=0.4MM 0.1UF 1UF
10% 10%
10
15
23
29
36
14
34
16V 16V
CRITICAL VOLTAGE=1.8V 2 2
5
Y2700 BYPASS=U2700.5::2MM 1
C2711 1
C2712 X7R-CERM
0402
X5R
402
0.1UF 1UF
CRFILT
PLLFILT
SM-2 BYPASS=U2650.23::2MM VDD33 10% 10%
24.000MHZ-16PF 16V 16V
2 X7R-CERM 2 X5R
1 3
0402 402
CRITICAL 2 4 CRITICAL SYM VER 1 =PP3V3_S3_USB_HUB 8 26

U2700
C2709 C2710
NC
NC
1 1
USB2513B NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
18PF 18PF 1 1 1 1 1 1
5% 5% R2701 R2716 R2717 R2718 R2719 R2722 R2723
50V
2
R2700 2
50V
100
QFN
10K 10K 10K 10K 10K 10K
HUB_NONREM1_1 HUB_NONREM0_1
C0G-CERM
0402
1M C0G-CERM
0402
1 2 USB_HUB_TEST 11
TEST USBDM_DN1/PRT_DIS_M1 1 USBHUB_DN1_N BI 9 5% 5% 5% 5% 5% 5%
1 2
OMIT BLUETOOTH FOR 15" MBP & MBP OG 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
5% USBDP_DN1/PRT_DIS_P1 2 USBHUB_DN1_P BI 9 MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
1 1 USB_HUB_RESET_L 26
C R2702 R2703 RESET*

C
5% 1/16W 402 402 402 402 402
1/16W MF-LF
26
2 2 2 2 2 2 402
10K 10K MF-LF 402 USBDM_DN2/PRT_DIS_M2 3 USBHUB_DN2_N 9 26
5% 5% 402 USB_HUB_XTAL1 33 XTALIN/CLKIN TRACKPAD/KEYBOARD FOR 15" MBP & MBP OG
1/16W 1/16W CRITICAL 32 USBDP_DN2/PRT_DIS_P2 4 USBHUB_DN2_P 9 26
MF-LF MF-LF USB_HUB_XTAL2 XTALOUT 26 9 USBHUB_DN3_N
402 402
2 2
USBDM_DN3/PRT_DIS_M3 6 USBHUB_DN3_N BI 9 26 26 9 USBHUB_DN3_P
USB_HUB_NONREM0 28
SUSP_IND/LOCAL_PWR/NON_REM0 SMC DEBUG PORT FOR 15" MBP, IR for MBP OG
USBDP_DN3/PRT_DIS_P3 7 USBHUB_DN3_P BI 9 26
USB_HUB_NONREM1 22 USBHUB_DN4_N
SDA/SMBDATA/NON_REM1 26 9
NC 8 USBHUB_DN4_N BI 9 26
24 9 NC FOR 15" MBP, SMC DEBUG PORT FOR MBP OG 26 9 USBHUB_DN4_P
HUB_NONREM1_0 HUB_NONREM0_0
USB_HUB_CFG_SEL0 SCL/SMBCLK/CFG_SEL0 NC USBHUB_DN4_P BI 9 26
USB_HUB_CFG_SEL1 25 12 TP_USB_HUB_PRTPWR1 USBHUB_DN2_N

R2704 1
1
R2705 HS_IND/CFG_SEL1 PRTPWR1/BC_EN1* 26 9
10K 10K PRTPWR2/BC_EN2* 16 NC_USB_HUB_PRTPWR2 7

5% 5% =PP3V3_S3_USB_HUB 26 9 USBHUB_DN2_P
1/16W 1/16W
1 1
PRTPWR3/BC_EN3* 18 NC_USB_HUB_PRTPWR3 7
8 26
MF-LF
402
MF-LF
402
R2706 R2707 NC 20 NC_USB_HUB_PRTPWR4 7
2 2 10K 10K
5% 5%
1/16W 1/16W
IPU OCS1* 13 TP_USB_HUB_OCS1 1
MF-LF
402
MF-LF
402 OCS2* 17 NC_USB_HUB_OCS2 7
R2708
2 2 IPU 10K
19 NC_USB_HUB_OCS3
IPU OSC3* 7 5%
1/16W
IPU NC 21 NC_USB_HUB_OCS4 7 MF-LF
402
2
RBIAS 35 USB_HUB_RBIAS
15" MBP USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION 27 USB_HUB_VBUS_DET
VBUS_DET
MBP OG USES 197S0284 FOR Y2700 TO SAVE COST CRITICAL
CKPLUS_WAIVE=NdifPr_badTerm USBDM_UP 30 USB_HUB_UP_N BI 19 91
1
R2709
USBDP_UP 31 USB_HUB_UP_P BI 19 91 12K TO CONNECT TP/KB TO PCH XHCI
1%
THRM_PAD 1/16W NOSTUFF R5701 & R5702, STUFF R2720 & R2721
8 =PP3V3_S3_USB_RESET
PCH PORT 7 (EHCI1) MF
402
2 NOSTUFF
37
R2720
27
91 19 BI USB_EXTD_XHCI_N 1 2 USB_TPAD_R_N BI 49 96
B 1 TO PCH XHCI
NOSTUFF
R2721
5%
1/16W TO TP/KB B
R2712 27
MF-LF
402
10K 91 19 BI USB_EXTD_XHCI_P 1 2 USB_TPAD_R_P BI 49 96
5%
1/16W 5%
MF-LF 1/16W
MF-LF
2 402 402
USB_HUB_RESET_L 26
C2715 1
0.1UF
10%
16V
X7R-CERM 2
0402
BYPASS=U2700.26::2MM
USB XHCI/EHCI2 PORT MUX FOR EXT B
8 =PP3V3_S3_USBMUX
C2760 1
9
0.1UF
20%
10V VCC
CERM 2
19 USB_EXTB_EHCI_P 402 5 M+ Y+ 1 USB_EXTB_P 7 38 91
BI BI
PCH PORT 9 (EHCI2) 91
USB_EXTB_EHCI_N 4 M- Y- 2 USB_EXTB_N
TO CONNECTOR
91 19 BI U2760 BI 7 38 91
A USB_EXTB_XHCI_P 7 D+
PI3USB102ZLE
TQFN SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PCH PORT 1 (XHCI) 19
91 BI
USB_EXTB_XHCI_N 6 D- CRITICAL PAGE TITLE
91 19 BI
PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE USB HUB & MUX
8 OE* SEL 10 USB_EXTB_SEL_XHCI DRAWING NUMBER SIZE
IN 17
PCH GPIO60 051-9589 D
GND SEL=0 CHOOSE USB EHCI2 PORT Apple Inc. REVISION
SEL=1 CHOOSE USB XHCI PORT
4.18.0
3

27 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

114S0365 1 R2821 PPDDR:1V5
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well RES,MTL FILM,1/16W,33.2K,1,0402,SMD,LF
114S0376 1 R2821 PPDDR:1V35

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary. RES,MTL FILM,1/16W,43.2K,1,0402,SMD,LF
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

D WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated. D
WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L
1V5 S0 "PGOOD" for CPU
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L 8 =PP3V3_S5_CPU_VCCDDR
70 41 40 38 34 18 7 IN PM_SLP_S4_L PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

CPUMEM_S0
1
R2805 16 14 11 8 =PP1V5_S3_CPU_VCCDDR PM_MEM_PWRGD OUT 11 18 89
10K 1
R2822
5%
1/16W 10K
MF-LF 5%
2 402 1/16W CRITICAL 6
MF-LF
P1V5CPU_EN 2 402 D Q2820
CRITICAL OUT 69
R28201
27.4K DMB53D0UV
8 =PP3V3_S3_MEMRESET CPUMEM_S0 1% SOT-563
1/16W
CPUMEM_S0 Q2805 D 6 MF-LF
402 2
PM_MEM_PWRGD_L 2 G
R28011 SSM6N15FEAPE
SOT563
100K
5% 3 CRITICAL
1/16W
MF-LF
402 2 2 G S 1 P1V5_S0_DIV 5 Q2820 S
DMB53D0UV 1
P1V5CPU_EN_L SOT-563
CRITICAL CRITICAL OMIT_TABLE 4
CPUMEM_S0 CPUMEM_S0 R28211 C2820 1
Q2800 D 3 3 D
Q2805 33.2K
1% 4700PF
SSM6N15FEAPE SSM6N15FEAPE
C SOT563 SOT563
1/16W
MF-LF
402 2
10%
100V
CERM 2
402
C
5 G S 4 4 S G 5
24 IN ISOLATE_CPU_MEM_L PM_SLP_S3_L IN 7 18 38 41 70
CPUMEM_S0
1
R2810
10K
5%
1/16W
MF-LF
2 402
MEMVTT_EN
MEMVTT Clamp
OUT 9
27 8 =PP5V_S3_MEMRESET CRITICAL
CPUMEM_S0
CPUMEM_S0 CPUMEM_S0 Q2810 D 6
Ensures CKE signals are held low in S3
R2815 1
R2802 1 SSM6N15FEAPE
SOT563
100K 100K
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 2 402 2 2 G S 1 8 =PPVTT_S0_VTTCLAMP
MEMVTT_EN_L CPUMEM_S0
CRITICAL
CRITICAL CRITICAL R28501
CPUMEM_S0 CPUMEM_S0 10 75mA max load @ 0.75V
CPUMEM_S0 5%
Q2815 Q2800 D 6 3 D
Q2810 1/10W
MF-LF
60mW max power
SSM6N15FEAPE SSM6N15FEAPE 603 2
SSM6N15FEAPE SOT563 SOT563
CRITICAL VTTCLAMP_L
G 2
SOT563
2 G S 1 4 S G 5 27 8 =PP5V_S3_MEMRESET CPUMEM_S0
B PLT_RESET_L CPUMEM_S0 Q2850 D 6
B
6 D
1 S
IN 19 25
R28511 SSM6N15FEAPE
SOT563
100K
5%
NOSTUFF 1/16W
MF-LF
C2817 1 CRITICAL
402 2 2 G S 1
0.047UF =PP1V5_S3_MEMRESET 8
10%
6.3V CPUMEM_S0 CRITICAL VTTCLAMP_EN
X5R 2 CPUMEM_S0
201 Q2815 CPUMEM_S0
SSM6N15FEAPE R2816
1
1 C2816 CPUMEM_S0
NO STUFF
MEMRESET_ISOL_LS5V_L
1K 0.1UF Q2850 D 3
C2851 1
5
33 SOT563 5% 10% SSM6N15FEAPE

1/16W 0.001UF
G
MF-LF 2 16V
X7R-CERM
SOT563
20%
2 402 0402 50V
CERM 2
=MEM_RESET_L CPU_MEM_RESET_L MEM_RESET_L 402
S
3 D
11 IN OUT 28 29 30 31
MAKE_BASE=TRUE 5 G S 4
4
64 9 IN =DDRVTT_EN
CPUMEM_S3
R2817
1
0 2
5%
1/16W
MF-LF
402
Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

S0 0 1 1 1 1 1 CPU_MEM_RESET_L 1 1
1 0 1 1 1 1 1 1 1
to 2 0 0 1 1 1 1 0 1
A S3
3
4
0
0
0
0
0
1
1
1
X
X
1
1
0
0
0
1
PAGE TITLE
to 5
6
0
0
1
1
1
1
1
1
0 (*)
1
1
1
1
1
1
1
CPU Memory S3 Support
DRAWING NUMBER SIZE
S0 7 1 1 1 1 1 CPU_MEM_RESET_L 1 1
REVISION
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO. R
4.18.0
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0 THE INFORMATION CONTAINED HEREIN IS THE
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
28 OF 132
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L. II NOT TO REPRODUCE OR COPY IT
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
89 33 29 28 PP0V75_S3_MEM_VREFDQ_A 89 33 29 28 PP0V75_S3_MEM_VREFDQ_A 89 33 29 28 PP0V75_S3_MEM_VREFDQ_A 89 33 29 28 PP0V75_S3_MEM_VREFDQ_A
89 33 29 28 PP0V75_S3_MEM_VREFCA_A 89 33 29 28 PP0V75_S3_MEM_VREFCA_A 89 33 29 28 PP0V75_S3_MEM_VREFCA_A 89 33 29 28 PP0V75_S3_MEM_VREFCA_A
=PP1V5R1V35_S3_MEM_A 8 28 29 =PP1V5R1V35_S3_MEM_A 8 28 29 =PP1V5R1V35_S3_MEM_A 8 28 29 =PP1V5R1V35_S3_MEM_A 8 28 29
C2907 1
C2917 1 C2927 1 C2937 1
0.47UF C2908 1 1 C2909 C2918 1 1 C2919 C2928 1 1 C2929 C2938 1 1 C2939
20% 0.47UF 0.47UF 0.47UF
4V 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF
CERM-X5R-1 2
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
CERM-X5R-1 2 CERM-X5R-1 2 CERM-X5R-1 2
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
201 4V 2 4V 4V 2 4V 4V 2 4V 4V 2 4V
CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1
H2 201 201 H2 201 201 H2 201 201 H2 201 201
VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC VDD VDDQ NC
H10 H10 H10 H10
NC NC NC NC
NC
NC
NC
NC
K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC
90 32
MEM_A_A<0> A0 MEM_A_A<0> A0 MEM_A_A<0> A0 MEM_A_A<0> A0
D
28 12
29
90
28 12
32 29
MEM_A_A<1> L8
L4
A1 U2900
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
90 32 29 28 12
32 29 28 12
90 27 28 29
MEM_A_A<1> L8
L4
A1 U2910
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
90 32 29 28 12
32 29 28 12
90 27 28 29
MEM_A_A<1> L8
L4
A1 U2920
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
90 32 29 28 12
32 29 28 12
90 27 28 29
MEM_A_A<1> L8
L4
A1 U2930
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
D
27 28 29 30 31
MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2
90 32
MEM_A_A<3> K3 FBGA B4 MEM_A_DQ<0> MEM_A_A<3> K3 FBGA B4 MEM_A_DQ<14> MEM_A_A<3> K3 FBGA B4 MEM_A_DQ<22> MEM_A_A<3> K3 FBGA B4 MEM_A_DQ<31>
28 12
90
A3 (SYM VER 2) DQ0 12 29 A3 (SYM VER 2) DQ0 12 29 A3 (SYM VER 2) DQ0 12 29 A3 (SYM VER 2) DQ0 12 29 90
29 90 90 90
32 29
28 12 MEM_A_A<4> L9 A4 DQ1 C8 MEM_A_DQ<6> 12 29 MEM_A_A<4> L9 A4 DQ1 C8 MEM_A_DQ<9> 12 29 MEM_A_A<4> L9 A4 DQ1 C8 MEM_A_DQ<21> 12 29 MEM_A_A<4> L9 A4 DQ1 C8 MEM_A_DQ<24> 12 29 90
90 90 90
90
28
32
12 MEM_A_A<5> L3 A5 DQ2 C3 MEM_A_DQ<7> 28 12 MEM_A_A<5> L3 A5 DQ2 C3 MEM_A_DQ<10> 12 29 MEM_A_A<5> L3 A5 DQ2 C3 MEM_A_DQ<16> 12 29 MEM_A_A<5> L3 A5 DQ2 C3 MEM_A_DQ<27> 12 29 90
29 90 32 29 90 90
28
90
12 MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<5> 12 29 MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<15> 12 29 MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<17> 12 29 MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<28> 12 29 90
32 29 90 90 90
MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<3> 12 29 MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<11> 12 29 MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<18> 12 29 MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<30> 12 29 90
90 90 90
90 32
28 12 MEM_A_A<8> N9 A8 NF/DQ5 E9 MEM_A_DQ<1> 12 29 MEM_A_A<8> N9 A8 NF/DQ5 E9 MEM_A_DQ<13> 12 29 MEM_A_A<8> N9 A8 NF/DQ5 E9 MEM_A_DQ<23> 12 29 MEM_A_A<8> N9 A8 NF/DQ5 E9 MEM_A_DQ<25> 12 29 90
29 90 90 90
90
28 12 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<2> 12 29 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<8> 12 29 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<20> 12 29 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<26> 12 29 90
32 29 90 90 90
28 12 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<4> 12 29 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<12> 12 29 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<19> 12 29 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<29> 12 29 90
32 29 90 90 90
32
28 12
90 MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11
29
K8 DQS C4 MEM_A_DQS_P<0> 12 29 K8 DQS C4 MEM_A_DQS_P<1> 12 29 K8 DQS C4 MEM_A_DQS_P<2> 12 29 K8 DQS C4 MEM_A_DQS_P<3> 12 29
9090 32 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90
DQS* D4 DQS* D4 DQS* D4 DQS* D4
28 12
29
N4 MEM_A_DQS_N<0> 12 29
N4 MEM_A_DQS_N<1> 12 29
N4 MEM_A_DQS_N<2> 12 29
N4 MEM_A_DQS_N<3> 12 29
90
28 12 MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90
32 29 90 32 29 28 90 32 29 28 90 32 29 28
28 12 MEM_A_A<14> N8 A14 DM/TDQS B8 90 32 29 28 12 MEM_A_A<14> N8 A14 DM/TDQS B8 90 32 29 28 12 MEM_A_A<14> N8 A14 DM/TDQS B8 90 32 29 28 12 MEM_A_A<14> N8 A14 DM/TDQS B8
32 29
90 90 MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8
28 12
32 29 NC 90 32 29 28 12
NC 90 32 29 28 12
NC 90 32 29 28 12
NC
90
28 12 MEM_A_BA<0> J3 BA0 CS* H3 MEM_A_CS_L<0> 12 28 MEM_A_BA<0> J3 BA0 CS* H3 MEM_A_CS_L<0> 12 28 MEM_A_BA<0> J3 BA0 CS* H3 MEM_A_CS_L<0> 12 28 MEM_A_BA<0> J3 BA0 CS* H3 MEM_A_CS_L<0> 12 28 32 90
32 29 32 90 32 90 32 90
28 12 MEM_A_BA<1> K9 BA1 CKE G10 MEM_A_CKE<0> 12 28 MEM_A_BA<1> K9 BA1 CKE G10 MEM_A_CKE<0> 12 28 MEM_A_BA<1> K9 BA1 CKE G10 MEM_A_CKE<0> 12 28 MEM_A_BA<1> K9 BA1 CKE G10 MEM_A_CKE<0> 12 28 32 90
32 29 32 90 32 90 32 90
90
28 12
90 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2
32 29 CK F8 MEM_A_CLK_P<0> 12 28 32 90 CK F8 MEM_A_CLK_P<0> 12 28 32 90 CK F8 MEM_A_CLK_P<0> 12 28 32 90 CK F8 MEM_A_CLK_P<0> 12 28 32 90
90
28 12 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<0> 32
12 28 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<0> 12 28 32 90
32 29 90 90 90
MEM_A_CAS_L G4 CAS* MEM_A_CAS_L G4 CAS* MEM_A_CAS_L G4 CAS* MEM_A_CAS_L G4 CAS*
A1 90 32 29 28 12 A1 90 32 29 28 12 A1 90 32 29 28 12 A1
90
28 12 MEM_A_WE_L H4 WE* NC MEM_A_WE_L H4 WE* NC MEM_A_WE_L H4 WE* NC MEM_A_WE_L H4 WE* NC
32 29 A4 90 32 29 28 12 A4 90 32 29 28 12 A4 90 32 29 28 12 A4
NC NC NC NC
28 12 MEM_A_ODT<0> G2 ODT NC
A11
NC 90 32 28 12 MEM_A_ODT<0> G2 ODT NC
A11
A11
A11
NC
90 32
F2 F2 F2 F2
MEM_A_ZQ<0> H9 ZQ NC MEM_A_ZQ<1> H9 ZQ NC MEM_A_ZQ<2> H9 ZQ NC MEM_A_ZQ<3> H9 ZQ NC
F10 F10 F10 F10
VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC VSS VSSQ NC
C R2900
2 2
R2910 R2920
2
R2930
2
C
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201

C2947 1
C2948 1 1 C2949 C2957 1
C2958 1 1 C2959 C2967 1 C2968 1 1 C2969 C2977 1 C2978 1 1 C2979
0.47UF 0.47UF 0.47UF 0.47UF
20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
CERM-X5R-1 2 CERM-X5R-1 2 CERM-X5R-1 2 CERM-X5R-1 2
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
4V 2 4V 4V 2 4V 4V 2 4V 4V 2 4V
201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1
H2 201 201 H2 201 201 H2 201 201 H2 201 201
H10 H10 H10 H10
NC NC NC NC
NC
NC
NC
NC
K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC
90
28 12 MEM_A_A<0> A0 N11 90 32 29 28 12 MEM_A_A<0> A0 N11 90 32 29 28 12 MEM_A_A<0> A0 N11 90 32 29 28 12 MEM_A_A<0> A0 N11
32 29
MEM_A_A<1> L8 A1 U2940 NC
N3 MEM_RESET_L 32 29 28 12 MEM_A_A<1> L8 A1 U2950 NC
N3 MEM_RESET_L
90
28 12 MEM_A_A<2> L4 A2 DDR3-1333 RESET* 90 27 28 29
90 32 29 28 12 30 31 MEM_A_A<2> L4 A2 DDR3-1333 RESET* 90 27 28 29
90 32 29 28 12 30 31 MEM_A_A<2> L4 A2 DDR3-1333 RESET* 90 27 28 29
90 32 29 28 12 30 31 MEM_A_A<2> L4 A2 DDR3-1333 RESET* 27 28 29 30 31
32 29
28 12 A3 (SYM VER 2) DQ0 12 29 A3 (SYM VER 2) DQ0 12 29 A3 (SYM VER 2) DQ0 12 29 A3 (SYM VER 2) DQ0 12 29 90
32 29 90 90 90
90
28 12
32 29 90 90 90
90
32 29 90 90 90 32 29
MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<35> 12 29 MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<43> 12 29 MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<51> 28 12 MEM_A_A<6> M9 A6 DQ3 C9 MEM_A_DQ<59> 12 29 90
90 90 90 32 29
90
28 12 MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<36> 12 29 MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<44> 12 29 MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<52> 12 29 MEM_A_A<7> M3 A7 NF/DQ4 E4 MEM_A_DQ<60> 12 29 90
32 29 90 90 90
B
32 29 90 90 90
B 90
28 12
32 29
90
90
28 12
32 29
MEM_A_A<9>
MEM_A_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_A_DQ<38>
MEM_A_DQ<39>
12 29
90
12 29
90
MEM_A_A<9>
MEM_A_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_A_DQ<46>
MEM_A_DQ<47>
12 29
90
12 29
90
MEM_A_A<9>
MEM_A_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_A_DQ<54>
MEM_A_DQ<55>
12 29
90
12 29
90
MEM_A_A<9>
MEM_A_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_A_DQ<62>
MEM_A_DQ<63>
12 29 90
12 29 90
MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11 MEM_A_A<11> M8 A11

90 32
29 90
N4 DQS* D4 MEM_A_DQS_N<4> 12 29
N4 DQS* D4 MEM_A_DQS_N<5> 12 29
N4 DQS* D4 MEM_A_DQS_N<6> 12 29 N4 DQS* D4 MEM_A_DQS_N<7> 12 29
32 29
28 12 MEM_A_A<13> A13 90
90 32 29
12
28
MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90
90 32 29 28 90 32 29 28
90 32
29
90
MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8 MEM_A_A<15> J8 A15 NF/TDQS* A8
28 12
32 29 NC 90 32 29 28 12
NC 90 32 29 28 12
NC 90 32 29 28 12
NC
90
32 29
32 90 32 90 32 90
90 32
29 32 90 32 90 32 90
90
28 12 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2 MEM_A_BA<2> J4 BA2
90
28 12 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<0> 12 28 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<0> 12 28 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<0> 12 28 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<0> 12 28 32 90
32 29 32 90 32 90 32 90
A1 90 32 29 28 12 A1 90 32 29 28 12 A1 90 32 29 28 12 A1
90
32 29 A4 90 32 29 28 12
A4 90 32 29 28 12
A4 90 32 29 28 12
A4
NC NC NC NC
A11
A11
A11
A11
NC
90 32
F2 F2 F2 F2
F10 F10 F10 F10
R2940
2 2
R2950 R2960
2
R2970
2
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201
=PP1V5R1V35_S3_MEM_A 8 28 29 SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

PAGE TITLE
C2900 1 C2901 1 C2910 1 C2911 1 C2920 1 C2921 1 C2930 1 C2931 1 1 C2903 1 C2904 1 C2905 1 C2913 1 C2914 1 C2915 1 C2923 1 C2924 1 C2925 1 C2933 1 C2934 1 C2935 DDR3 SDRAM Bank A (1 OF 2)
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% DRAWING NUMBER SIZE
10V 10V 10V 10V 10V 10V 10V 10V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V 6.3V
X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R 2 X5R 2 X5R
051-9589 D
402 402 402 402 402 402 402 402 201 201 201 201 201 201 201 201 201 201 201 201
Apple Inc. REVISION
R
4.18.0
C2940 1 C2941 1 C2950 1 C2951 1 C2960 1 C2961 1 C2970 1 C2971 1 1 C2943 1 C2944 1 C2945 1 C2953 1 C2954 1 C2955 1 C2963 1 C2964 1 C2965 1 C2973 1 C2974 1 C2975 THE INFORMATION CONTAINED HEREIN IS THE
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
20% 20% 20% 20% 20% 20% 20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
6.3V
2 X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
6.3V
2 X5R 6.3V
2 X5R I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
29 OF 132
402 402 402 402 402 402 402 402 201 201 201 201 201 201 201 201 201 201 201 201
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C3007 1
C3008 1 1 C3009 C3017 1
C3018 1 1 C3019 C3027 1 C3028 1 1 C3029 C3037 1 C3038 1 1 C3039
0.47UF 0.47UF 0.47UF 0.47UF
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
4V 2 4V 4V 2 4V 4V 2 4V 4V 2 4V
H2 201 201 H2 201 201 H2 201 201 H2 201 201
H10 H10 H10 H10
NC NC NC NC
NC
NC
NC
NC
K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC
90
MEM_A_A<0> A0 MEM_A_A<0> A0 MEM_A_A<0> A0 MEM_A_A<0> A0
D
28 12
32 29
MEM_A_A<1> L8
L4
A1 U3000
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
90 32 29 28 12
32 29 28 12
90 27 28 29
MEM_A_A<1> L8
L4
A1 U3010
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
90 32 29 28 12
32 29 28 12
90 27 28 29
MEM_A_A<1> L8
L4
A1 U3020
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
90 32 29 28 12
32 29 28 12
90 27 28 29
MEM_A_A<1> L8
L4
A1 U3030
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
D
27 28 29 30 31
90
28 12 MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2 90 32 29 28 12 30 31 MEM_A_A<2> A2
32 29
32 29 90 90 90
90
28 12
32 29 90 90 90
90
32 29 90 90 90
90 90 90
90
32 29 90 90 90
32 29 90 90 90
90
28 12
90 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<1> 12 28 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<13> 12 28 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<23> 12 28 MEM_A_A<9> M4 A9 NF/DQ6 D3 MEM_A_DQ<25> 12 28 90
32 29 90 90 90
90
28 12 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<3> 12 28 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<11> 12 28 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<18> 12 28 MEM_A_A<10> H8 A10/AP NF/DQ7 E8 MEM_A_DQ<30> 12 28 90
32 29 90 90 90
90
MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90 MEM_A_A<12> A12/BC* 90
28 12
32 29
N4 MEM_A_DQS_N<0> 12
90
28
N4 MEM_A_DQS_N<1> 12 28
N4 MEM_A_DQS_N<2> 12 28 N4 MEM_A_DQS_N<3> 12 28
MEM_A_A<13> A13 90 32 29 28 12 MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90 12 MEM_A_A<13> A13 90
90 32 29 28 90 32 29 28
90
32 29
28
32
12
29 NC 90 32 29 28 12
NC 90 32 29 28 12
NC 90 32 29 28 12
NC
90 90
32
28
29
12 MEM_A_BA<1> J3 BA0 CS* H3 MEM_A_CS_L<1> 28 12 MEM_A_BA<1> J3 BA0 CS* H3 MEM_A_CS_L<1> 12 29 MEM_A_BA<1> J3 BA0 CS* H3 MEM_A_CS_L<1> 12 29 MEM_A_BA<1> J3 BA0 CS* H3 MEM_A_CS_L<1> 12 29 32 90
90 32 29 32 90 32 90
90 32
29 32 90 32 90 32 90
90
90 32
28 12 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<1>90 32 28 12 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<1> 32
12 29 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<1> 12 29 32 90
29 29 90 90
90
28 12 MEM_A_CAS_L G4 CAS* MEM_A_CAS_L G4 CAS* MEM_A_CAS_L G4 CAS* MEM_A_CAS_L G4 CAS*
32 29 A1 90 32 29 28 12 A1 90 32 29 28 12 A1 90 32 29 28 12 A1
32 29 A4 90 32 29 28 12 A4 90 32 29 28 12 A4 90 32 29 28 12 A4
90 NC NC NC NC
29 12
90 32
MEM_A_ODT<1> G2 ODT NC
A11
A11
A11
A11
NC
F2 F2 F2 F2
F10 F10 F10 F10
C R3000
2 2
R3010 R3020
2
R3030
2
C
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201

C3047 1
C3048 1 1 C3049 C3057 1
C3058 1 1 C3059 C3067 1 C3068 1 1 C3069 C3077 1 C3078 1 1 C3079
0.47UF 0.47UF 0.47UF 0.47UF
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
4V 2 4V 4V 2 4V 4V 2 4V 4V 2 4V
H2 201 201 H2 201 201 H2 201 201 H2 201 201
H10 H10 H10 H10
NC NC NC NC
NC
NC
NC
NC
K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC
90
28 12 MEM_A_A<0> A0 N11 90 32 29 28 12 MEM_A_A<0> A0 N11 90 32 29 28 12 MEM_A_A<0> A0 N11 90 32 29 28 12 MEM_A_A<0> A0 N11
32 29
MEM_A_A<1> L8 A1 U3040 NC
N3 MEM_RESET_L
90
90 32 29 28 12 30 31 MEM_A_A<2> L4 A2 DDR3-1333 RESET* 27
90 32 29 28 12 28
90
90 32 29 28 12 30 31 MEM_A_A<2> L4 A2 DDR3-1333 RESET* 27 28 29 30 31
32 29
MEM_A_A<4> K3 FBGA B4 MEM_A_DQ<33> MEM_A_A<4> K3 FBGA B4 MEM_A_DQ<41>
31
MEM_A_A<4> K3 FBGA B4 MEM_A_DQ<49> MEM_A_A<4> K3 FBGA B4 MEM_A_DQ<57>
32 29 90 32 29 90 90
90
28 12
32 29 90 90 90
90
32 29 90 90 32 29 90
90 90 90
90
32 29 90 90 32 29 90
B
32 29 90 32 29 90 90
B 90
28 12
32 29
90
90
28 12
32 29
MEM_A_A<9>
MEM_A_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_A_DQ<37>
MEM_A_DQ<36>
28 12
90 32 29
12 28
90
MEM_A_A<9>
MEM_A_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_A_DQ<45>
MEM_A_DQ<44>
12 28
90
12 28
90
MEM_A_A<9>
MEM_A_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_A_DQ<53>
MEM_A_DQ<52>
12 28
90
12 28
90
MEM_A_A<9>
MEM_A_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_A_DQ<61>
MEM_A_DQ<60>
12 28 90
12 28 90

90 32
DQS* D4 MEM_A_DQS_N<4> DQS* D4 MEM_A_DQS_N<5> DQS* D4 MEM_A_DQS_N<6> DQS* D4 MEM_A_DQS_N<7>
90 90 90
29
32 29
28 12 MEM_A_A<13> N4 A13
12 28
90 32 29 28 12 MEM_A_A<13> N4 A13
12 28
90 32 29 28 12 MEM_A_A<13> N4 A13
12
90
28
12 MEM_A_A<13> N4 A13
12 28
90
90 32 29 28
90 32
29
90
28 12
32 29 NC 90 32 29 28 12
NC 90 32 29 28 12
NC 90 32 29 28 12
NC
90
32 29
32 90 32 90 32 90
90 32
29 90 32 29 32 90 32 90
90
90 32
28 12 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<1>90 28 12 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<1> 12 29 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<1> 12 29 MEM_A_RAS_L F4 RAS* CK* G8 MEM_A_CLK_N<1> 12 29 32 90
29 32 29 32 90 32 90
90
28 12
32 29 A1 90 32 29 28 12 A1 90 32 29 28 12 A1 90 32 29 28 12 A1
32 29 A4 90 32 29 28 12
A4 90 32 29 28 12
A4 90 32 29 28 12
A4
90 NC NC NC NC
A11
A11
A11
A11
NC
90 32
F2 F2 F2 F2
F10 F10 F10 F10
R3040
2 2
R3050 R3060
2
R3070
2
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201
=PP1V5R1V35_S3_MEM_A 8 28 29 SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

PAGE TITLE
C3000 1 C3001 1 C3010 1 C3011 1 C3020 1 C3021 1 C3030 1 C3031 1 1 C3003 1 C3004 1 C3005 1 C3013 1 C3014 1 C3015 1 C3023 1 C3024 1 C3025 1 C3033 1 C3034 1 C3035 DDR3 SDRAM Bank A (2 OF 2)
051-9589 D
402 402 402 402 402 402 402 402 201 201 201 201 201 201 201 201 201 201 201 201
Apple Inc. REVISION
R
4.18.0
20% 20% 20% 20% 20% 20% 20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
6.3V
2 X5R 6.3V
30 OF 132
402 402 402 402 402 402 402 402 201 201 201 201 201 201 201 201 201 201 201 201
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
89 33 31 30 PP0V75_S3_MEM_VREFDQ_B 89 33 31 30 PP0V75_S3_MEM_VREFDQ_B 89 33 31 30 PP0V75_S3_MEM_VREFDQ_B 89 33 31 30 PP0V75_S3_MEM_VREFDQ_B
89 33 31 30 PP0V75_S3_MEM_VREFCA_B 89 33 31 30 PP0V75_S3_MEM_VREFCA_B 89 33 31 30 PP0V75_S3_MEM_VREFCA_B 89 33 31 30 PP0V75_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B 8 30 31 =PP1V5R1V35_S3_MEM_B 8 30 31 =PP1V5R1V35_S3_MEM_B 8 30 31 =PP1V5R1V35_S3_MEM_B 8 30 31
C3107 1
C3108 1 1 C3109 C3117 1
C3118 1 1 C3119 C3127 1 C3128 1 1 C3129 C3137 1 C3138 1 1 C3139
0.47UF 0.47UF 0.47UF 0.47UF
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
4V 2 4V 4V 2 4V 4V 2 4V 4V 2 4V
H2 201 201 H2 201 201 H2 201 201 H2 201 201
H10 H10 H10 H10
NC NC NC NC
NC
NC
NC
NC
K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC
90 32
MEM_B_A<0> A0 MEM_B_A<0> A0 MEM_B_A<0> A0 MEM_B_A<0> A0
D
30 12
31
90
30 12
32 31
MEM_B_A<1> L8
L4
A1 U3100
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
90 32 31 30 12
32 31 30 12
90
MEM_B_A<1> L8
L4
A1 U3110
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
90 32 31 30 12
32 31 30 12
90
MEM_B_A<1> L8
L4
A1 U3120
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
90 32 31 30 12
32 31 30 12
90
MEM_B_A<1> L8
L4
A1 U3130
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
D
27 28 29 30 31
MEM_B_A<2> A2 90 32 31 30 12 MEM_B_A<2> A2 90 32 31 30 12 MEM_B_A<2> A2 90 32 31 30 12 MEM_B_A<2> A2
90 32
MEM_B_A<3> K3 FBGA B4 MEM_B_DQ<6> MEM_B_A<3> K3 FBGA B4 MEM_B_DQ<14> MEM_B_A<3> K3 FBGA B4 MEM_B_DQ<18> MEM_B_A<3> K3 FBGA B4 MEM_B_DQ<27>
30 12
31 90
A3 (SYM VER 2) DQ0 30 12
90 32 31
A3 (SYM VER 2) DQ0 30 12
90 32 31
A3 (SYM VER 2) DQ0 30 12
90 32 31
A3 (SYM VER 2) DQ0 12 31 90
32 31
30 12 MEM_B_A<4> L9 A4 DQ1 C8 MEM_B_DQ<1> 30 12 MEM_B_A<4> L9 A4 DQ1 C8 MEM_B_DQ<9> 30 12 MEM_B_A<4> L9 A4 DQ1 C8 MEM_B_DQ<20> 30 12 MEM_B_A<4> L9 A4 DQ1 C8 MEM_B_DQ<25> 12 31 90
90 32 31 90 32 31 90 32 31
90 32
31 90 90 32 31 90
90
30 12 MEM_B_A<6> M9 A6 DQ3 C9 MEM_B_DQ<5> 30 12 MEM_B_A<6> M9 A6 DQ3 C9 MEM_B_DQ<13> 30 12 MEM_B_A<6> M9 A6 DQ3 C9 MEM_B_DQ<16> 30 12 MEM_B_A<6> M9 A6 DQ3 C9 MEM_B_DQ<29> 12 31 90
32 31 90 32 31 90 32 31 90 32 31
MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<2> 30 12 MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<10> 30 12 MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<23> 30 12 MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<30> 12 31 90
90 32 31 90 32 31 90 32 31
90 32
30 12 MEM_B_A<8> N9 A8 NF/DQ5 E9 MEM_B_DQ<4> 30 12 MEM_B_A<8> N9 A8 NF/DQ5 E9 MEM_B_DQ<12> 30 12 MEM_B_A<8> N9 A8 NF/DQ5 E9 MEM_B_DQ<21> 30 12 MEM_B_A<8> N9 A8 NF/DQ5 E9 MEM_B_DQ<28> 12 31 90
31 90 32 31 90 32 31 90 32 31
90
30 12 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<7> 30 12 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<15> 30 12 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<22> 30 12 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<31> 12 31 90
32 31 90 32 31 90 32 31 90 32 31
MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<0> MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<8> 90 30 12 MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<17>90 30 12 MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<24> 12 31 90
32 31 32 31
90
30 12 MEM_B_A<11> M8 A11 90 32
MEM_B_A<11> M8 A11 90
MEM_B_A<11> M8 A11 90
MEM_B_A<11> M8 A11
DQS C4
30 12
DQS C4
30 12
DQS C4
30 12
32 31
K8 MEM_B_DQS_P<0> 31
K8 MEM_B_DQS_P<1> 32 31
K8 MEM_B_DQS_P<2> 32 31
K8 DQS C4 MEM_B_DQS_P<3> 12 31
MEM_B_A<12> A12/BC*
90
MEM_B_A<12> A12/BC* MEM_B_A<12> A12/BC* MEM_B_A<12> A12/BC* 90
30 12 30 12 30 12 30 12
32 31
N4 MEM_B_DQS_N<0> 32 31
N4 MEM_B_DQS_N<1> 32 31
N4 MEM_B_DQS_N<2> 32 31
N4 MEM_B_DQS_N<3> 12 31
90
30 12
90 MEM_B_A<13> A13 90 32 31 30 12 MEM_B_A<13> A13 90 32 31 30 12
90 MEM_B_A<13> A13 90 32 31 30 12
90 MEM_B_A<13> A13 90
32 31
90
30 12 MEM_B_A<14> N8 A14 DM/TDQS B8 90 32 31 30 12 MEM_B_A<14> N8 A14 DM/TDQS B8 90 32 31 30 12 MEM_B_A<14> N8 A14 DM/TDQS B8 90 32 31 30 12 MEM_B_A<14> N8 A14 DM/TDQS B8
32 31
MEM_B_A<15> J8 A15 NF/TDQS* A8 MEM_B_A<15> J8 A15 NF/TDQS* A8 MEM_B_A<15> J8 A15 NF/TDQS* A8 MEM_B_A<15> J8 A15 NF/TDQS* A8
30 12
32 31 NC 90 32 31 30 12
NC 90 32 31 30 12
NC 90 32 31 30 12
NC
90
90
30 12 MEM_B_BA<0> J3 BA0 CS* H3 MEM_B_CS_L<0> 30 12 MEM_B_BA<0> J3 BA0 CS* H3 MEM_B_CS_L<0> 30 12 MEM_B_BA<0> J3 BA0 CS* H3 MEM_B_CS_L<0> 30 12 MEM_B_BA<0> J3 BA0 CS* H3 MEM_B_CS_L<0> 12 30 32 90
32 31 90 32 31 90 32 31 90 32 31
30 12 MEM_B_BA<1> K9 BA1 CKE G10 MEM_B_CKE<0> 30 12 MEM_B_BA<1> K9 BA1 CKE G10 MEM_B_CKE<0> 30 12 MEM_B_BA<1> K9 BA1 CKE G10 MEM_B_CKE<0> 30 12 MEM_B_BA<1> K9 BA1 CKE G10 MEM_B_CKE<0> 12 30 32 90
32 31 90 32 31 90 32 31 90 32 31
90
30 12
90 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2
32 31 CK F8 MEM_B_CLK_P<0> 30 12
32 31 12 30 32 90 CK F8 MEM_B_CLK_P<0> 30 12
32 31 12 30 32 90 CK F8 MEM_B_CLK_P<0> 12 30 32 90 CK F8 MEM_B_CLK_P<0> 12 30 32 90
90 90
90
30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0>90 30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0> 30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0> 32
12 30 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0> 12 30 32 90
32 31 32 31 90 32 31 90
MEM_B_CAS_L G4 CAS* MEM_B_CAS_L G4 CAS* MEM_B_CAS_L G4 CAS* MEM_B_CAS_L G4 CAS*
A1 90 32 31 30 12
A1 90 32 31 30 12 A1 90 32 31 30 12 A1
90
30 12 MEM_B_WE_L H4 WE* NC MEM_B_WE_L H4 WE* NC MEM_B_WE_L H4 WE* NC MEM_B_WE_L H4 WE* NC
32 31 A4 90 32 31 30 12
A4 90 32 31 30 12 A4 90 32 31 30 12 A4
NC NC NC NC
30 12 MEM_B_ODT<0> G2 ODT NC
A11
NC 90 32 30 12 MEM_B_ODT<0> G2 ODT NC
A11
A11
A11
NC
90 32
F2 F2 F2 F2
MEM_B_ZQ<0> H9 ZQ NC MEM_B_ZQ<1> H9 ZQ NC MEM_B_ZQ<2> H9 ZQ NC MEM_B_ZQ<3> H9 ZQ NC
F10 F10 F10 F10
C R3100
2 2
R3110 R3120
2
R3130
2
C
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201

C3147 1
C3148 1 1 C3149 C3157 1
C3158 1 1 C3159 C3167 1 C3168 1 1 C3169 C3177 1 C3178 1 1 C3179
0.47UF 0.47UF 0.47UF 0.47UF
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
4V 2 4V 4V 2 4V 4V 2 4V 4V 2 4V
H2 201 201 H2 201 201 H2 201 201 H2 201 201
H10 H10 H10 H10
NC NC NC NC
NC
NC
NC
NC
K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC
90
30
32
12 MEM_B_A<0> A0 N11 90 32 31 30 12 MEM_B_A<0> A0 N11 90 32 31 30 12 MEM_B_A<0> A0 N11 90 32 31 30 12 MEM_B_A<0> A0 N11
31
30
90
12 MEM_B_A<1> L8 A1 U3140 NC
N3 MEM_RESET_L 32 31 30 12 MEM_B_A<1> L8 A1 U3150 NC
N3 MEM_RESET_L
32 31
MEM_B_A<2> L4 A2 DDR3-1333 RESET* 90
90 32 31 30 12 MEM_B_A<2> L4 A2 DDR3-1333 RESET* 90
90 32 31 30 12 MEM_B_A<2> L4 A2 DDR3-1333 RESET* 90
90 32 31 30 12 MEM_B_A<2> L4 A2 DDR3-1333 RESET* 27 28 29 30 31
90 32
30 12
90
31 90 90 32 31 90 32 31
32 31
90 32 31 90 32 31 90 32 31
90 32
31 90 32 31 90 32 31 90 32 31
90
32 31 90 32 31 90 32 31 90 32 31
MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<36> 30 12 MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<44> 30 12 MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<52> 30 12 MEM_B_A<7> M3 A7 NF/DQ4 E4 MEM_B_DQ<60> 12 31 90
90 32 31 90 32 31 90 32 31
90 32
B
31 90 32 31 90 32 31 90 32 31
B 90
30 12
32 31
MEM_B_A<9>
MEM_B_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_B_DQ<38>
MEM_B_DQ<39>90
30
90 32
30 12
32 31
12
31
MEM_B_A<9>
MEM_B_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_B_DQ<46>
MEM_B_DQ<47>90
30
90 32
30 12
32 31
12
31
MEM_B_A<9>
MEM_B_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_B_DQ<54>
MEM_B_DQ<55>90
30
90 32
30 12
32 31
12
31
MEM_B_A<9>
MEM_B_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_B_DQ<62>
MEM_B_DQ<63>
12 31 90
12 31 90
90
30 12 MEM_B_A<11> M8 A11
90
MEM_B_A<11> M8 A11
90
MEM_B_A<11> M8 A11
90
MEM_B_A<11> M8 A11
DQS C4
30 12
DQS C4
30 12
DQS C4
30 12
32 31
K8 MEM_B_DQS_P<4> 32 31
K8 MEM_B_DQS_P<5> 32 31
K8 MEM_B_DQS_P<6> 32 31
30 12 MEM_B_A<12> A12/BC* MEM_B_A<12> A12/BC* MEM_B_A<12> A12/BC* MEM_B_A<12> A12/BC* 90
DQS* D4
30 12
DQS* D4
30 12
DQS* D4
30 12
32 31
N4 MEM_B_DQS_N<4> 32 31
N4 MEM_B_DQS_N<5> 32 31
N4 MEM_B_DQS_N<6> 32 31
N4 DQS* D4 MEM_B_DQS_N<7> 12 31
90
30 12
90 MEM_B_A<13> A13 90 32 31 30 12
90 MEM_B_A<13> A13 90 32 31 30 12
90 MEM_B_A<13> A13 90 32 31 30 12
90 MEM_B_A<13> A13 90
32 31
90
32 31
30 12
32 31 NC 90 32 31 30 12
NC 90 32 31 30 12
NC 90 32 31 30 12
NC
90
90
32 31 90 32 31 90 32 31 90 32 31
32 31 90 32 31 90 32 31 90 32 31
90
30 12
90 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2
32 31 CK F8 MEM_B_CLK_P<0> 30 12
32 31 12 30 32 90 CK F8 MEM_B_CLK_P<0> 30 12
32 31 12 30 32 90 CK F8 MEM_B_CLK_P<0> 30
32
12
31 12 30 32 90 CK F8 MEM_B_CLK_P<0> 12 30 32 90
90 90 90
90
30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0>90 30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0>90 30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0>90 30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<0> 12 30 32 90
32 31 32 31 32 31 32 31
A1 90 32 31 30 12 A1 90 32 31 30 12 A1 90 32 31 30 12 A1
90
32 31 A4 90 32 31 30 12
A4 90 32 31 30 12
A4 90 32 31 30 12
A4
NC NC NC NC
A11
A11
A11
A11
NC
90 32
F2 F2 F2 F2
F10 F10 F10 F10
R3140
2 2
R3150 R3160
2
R3170
2
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201
=PP1V5R1V35_S3_MEM_B 8 30 31 SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

PAGE TITLE
C3100 1 C3101 1 C3110 1 C3111 1 C3120 1 C3121 1 C3130 1 C3131 1 1 C3103 1 C3104 1 C3105 1 C3113 1 C3114 1 C3115 1 C3123 1 C3124 1 C3125 1 C3133 1 C3134 1 C3135 DDR3 SDRAM Bank B (1 OF 2)
051-9589 D
402 402 402 402 402 402 402 402 201 201 201 201 201 201 201 201 201 201 201 201
Apple Inc. REVISION
R
4.18.0
20% 20% 20% 20% 20% 20% 20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
6.3V
2 X5R 6.3V
31 OF 132
402 402 402 402 402 402 402 402 201 201 201 201 201 201 201 201 201 201 201 201
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C3207 1
C3208 1 1 C3209 C3217 1
C3218 1 1 C3219 C3227 1 C3228 1 1 C3229 C3237 1 C3238 1 1 C3239
0.47UF 0.47UF 0.47UF 0.47UF
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
4V 2 4V 4V 2 4V 4V 2 4V 4V 2 4V
H2 201 201 H2 201 201 H2 201 201 H2 201 201
H10 H10 H10 H10
NC NC NC NC
NC
NC
NC
NC
K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC
90
MEM_B_A<0> A0 MEM_B_A<0> A0 MEM_B_A<0> A0 MEM_B_A<0> A0
D
30 12
32 31
MEM_B_A<1> L8
L4
A1 U3200
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
90 32 31 30 12
32 31 30 12
90 27 28 29
MEM_B_A<1> L8
L4
A1 U3210
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
90 32 31 30 12
32 31 30 12
90 27 28 29
MEM_B_A<1> L8
L4
A1 U3220
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
90 32 31 30 12
32 31 30 12
90 27 28 29
MEM_B_A<1> L8
L4
A1 U3230
DDR3-1333 RESET*
N11
N3
NC
MEM_RESET_L
D
27 28 29 30 31
90
30 12 MEM_B_A<2> A2 90 32 31 30 12 30 31 MEM_B_A<2> A2 90 32 31 30 12 30 31 MEM_B_A<2> A2 90 32 31 30 12 30 31 MEM_B_A<2> A2
32 31
30 12
32 31
A3 (SYM VER 2) DQ0 12 30
90
A3 (SYM VER 2) DQ0 12 30
90
A3 (SYM VER 2) DQ0 12 30
90
A3 (SYM VER 2) DQ0 12 30 90
90
30 12
90 MEM_B_A<3> L9 A4 DQ1 C8 MEM_B_DQ<6> 30 12 MEM_B_A<3> L9 A4 DQ1 C8 MEM_B_DQ<14> 12 30 MEM_B_A<3> L9 A4 DQ1 C8 MEM_B_DQ<18> 12 30 MEM_B_A<3> L9 A4 DQ1 C8 MEM_B_DQ<27> 12 30 90
32 31 90 32 31 90 90
90
32 31 90 90 90
MEM_B_A<5> M9 A6 DQ3 C9 MEM_B_DQ<3> 30 12 MEM_B_A<5> M9 A6 DQ3 C9 MEM_B_DQ<11> 12 30 MEM_B_A<5> M9 A6 DQ3 C9 MEM_B_DQ<19> 12 30 MEM_B_A<5> M9 A6 DQ3 C9 MEM_B_DQ<26> 12 30 90
90 32 31 90 90
90
30 12 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<0> 12 30 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<8> 12 30 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<17> 12 30 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<24> 12 30 90
32 31 90 90 90
32 31 90 90 90
90
30 12
90 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<4> 12 30 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<12> 12 30 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<21> 12 30 MEM_B_A<9> M4 A9 NF/DQ6 D3 MEM_B_DQ<28> 12 30 90
32 31 90 90 90
90
30 12 MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<2> 30 12 MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<10> 12 30 MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<23> 12 30 MEM_B_A<10> H8 A10/AP NF/DQ7 E8 MEM_B_DQ<30> 12 30 90
32 31 90 32 31 90 90
MEM_B_A<11> M8 A11 MEM_B_A<11> M8 A11 MEM_B_A<11> M8 A11 MEM_B_A<11> M8 A11
K8 DQS C4 MEM_B_DQS_P<0> 12 30 K8 DQS C4 MEM_B_DQS_P<1> 12 30
90 32
MEM_B_A<12> A12/BC* 90 MEM_B_A<12> A12/BC* 90 MEM_B_A<12> A12/BC* 90 MEM_B_A<12> A12/BC* 90
30 12
31 90
N4 MEM_B_DQS_N<0> 12 30
N4 MEM_B_DQS_N<1> 12 30
N4 MEM_B_DQS_N<2> 12 30
N4 MEM_B_DQS_N<3> 12 30
32 31
30 12 MEM_B_A<13> A13 90 12 MEM_B_A<13> A13 90 12 MEM_B_A<13> A13 90 12 MEM_B_A<13> A13 90
90 32 31 30 90 32 31 30 90 32 31 30
90 32
31
90
30 12
32 31 NC 90 32 31 30 12
NC 90 32 31 30 12
NC 90 32 31 30 12
NC
90
32 31
32 90 32 90 32 90
90 32
31 32 90 32 90 32 90
90
30 12 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2
32 31 CK F8 MEM_B_CLK_P<1> 12 31 32 90 CK F8 MEM_B_CLK_P<1> 12 31 32 90 CK F8 MEM_B_CLK_P<1> 12 31 32 90 CK F8 MEM_B_CLK_P<1> 12 31 32 90
90 32
30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<1> 32
12 31 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<1> 12 31 32 90
31 90 90 90
90
30 12 MEM_B_CAS_L G4 CAS* MEM_B_CAS_L G4 CAS* MEM_B_CAS_L G4 CAS* MEM_B_CAS_L G4 CAS*
32 31 A1 90 32 31 30 12 A1 90 32 31 30 12 A1 90 32 31 30 12 A1
32 31 A4 90 32 31 30 12 A4 90 32 31 30 12 A4 90 32 31 30 12 A4
90 NC NC NC NC
31 12
90 32
MEM_B_ODT<1> G2 ODT NC
A11
A11
A11
A11
NC
F2 F2 F2 F2
F10 F10 F10 F10
C R3200
2 2
R3210 R3220
2
R3230
2
C
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201

C3247 1
C3248 1 1 C3249 C3257 1
C3258 1 1 C3259 C3267 1 C3268 1 1 C3269 C3277 1 C3278 1 1 C3279
0.47UF 0.47UF 0.47UF 0.47UF
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
A10
K10
M10
B10
E10
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
A3
D8
G9
G3
K2
M2
C2
E3
VREFDQ E2
VREFCA J9
4V 2 4V 4V 2 4V 4V 2 4V 4V 2 4V
H2 201 201 H2 201 201 H2 201 201 H2 201 201
H10 H10 H10 H10
NC NC NC NC
NC
NC
NC
NC
K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC K4 OMIT_TABLE N1
NC
90
30 12 MEM_B_A<0> A0 N11 90 32 31 30 12 MEM_B_A<0> A0 N11 90 32 31 30 12 MEM_B_A<0> A0 N11 90 32 31 30 12 MEM_B_A<0> A0 N11
32 31
MEM_B_A<1> L8 A1 U3240 NC
N3 MEM_RESET_L
90
30 12 MEM_B_A<2> L4 A2 DDR3-1333 RESET* 90
90 32 31 30 12 MEM_B_A<2> L4 A2 DDR3-1333 RESET* 90 27 28 29
90 32 31 30 12 30 31 MEM_B_A<2> L4 A2 DDR3-1333 RESET* 90 27 28 29
90 32 31 30 12 30 31 MEM_B_A<2> L4 A2 DDR3-1333 RESET* 27 28 29 30 31
32 31
90 90 90
90
32 31 90 90 90
MEM_B_A<6> L3 A5 DQ2 C3 MEM_B_DQ<35> 12 30 MEM_B_A<6> L3 A5 DQ2 C3 MEM_B_DQ<43> 12 30 MEM_B_A<6> L3 A5 DQ2 C3 MEM_B_DQ<51> 30 12 MEM_B_A<6> L3 A5 DQ2 C3 MEM_B_DQ<59> 12 30 90
90 90 90 32 31
90 32
31 90 90 90
90
30 12 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<39> 12 30 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<47> 30 12 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<55> 12 30 MEM_B_A<8> M3 A7 NF/DQ4 E4 MEM_B_DQ<63> 12 30 90
32 31 90 90 32 31 90
B
32 31 90 90 90
B 90
30 12
32 31
90
90
30 12
32 31
MEM_B_A<9>
MEM_B_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_B_DQ<37>
MEM_B_DQ<36>
12 30
90
12 30
90
MEM_B_A<9>
MEM_B_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_B_DQ<45>
MEM_B_DQ<44>
12 30
90
12 30
90
MEM_B_A<9>
MEM_B_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_B_DQ<53>
MEM_B_DQ<52>
12 30
90
12 30
90
MEM_B_A<9>
MEM_B_A<10>
M4
H8
A9
A10/AP
NF/DQ6
NF/DQ7
D3
E8
MEM_B_DQ<61>
MEM_B_DQ<60>
12 30 90
12 30 90
MEM_B_A<11> M8 A11 MEM_B_A<11> M8 A11 MEM_B_A<11> M8 A11 MEM_B_A<11> M8 A11

K8 DQS C4 MEM_B_DQS_P<4> 12 30 K8 DQS C4 MEM_B_DQS_P<5> 12 30 K8 DQS C4 MEM_B_DQS_P<6> 12 30 K8 DQS C4 MEM_B_DQS_P<7> 12 30
90 32
30 12 MEM_B_A<12> A12/BC* 90 MEM_B_A<12> A12/BC* 90 MEM_B_A<12> A12/BC* 90 MEM_B_A<12> A12/BC* 90
31 90
N4 DQS* D4 MEM_B_DQS_N<6> 12 30 N4 DQS* D4 MEM_B_DQS_N<7> 12 30
32 31
30 12 MEM_B_A<13> A13 90
90 32 31
12
30
MEM_B_A<13> A13 90 12 MEM_B_A<13> A13 90 12 MEM_B_A<13> A13 90
90 32 31 30 90 32 31 30
90 32
31
90
30 12
32 31 NC 90 32 31 30 12
NC 90 32 31 30 12
NC 90 32 31 30 12
NC
90
32 31
32 90 32 90 32 90
90 32
31 32 90 32 90 90 32 31
90
30 12 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2 MEM_B_BA<2> J4 BA2
32 31 CK F8 MEM_B_CLK_P<1> 12 31 32 90 CK F8 MEM_B_CLK_P<1> 12 31 32 90 CK F8 MEM_B_CLK_P<1> 12 31 32 90 CK F8 MEM_B_CLK_P<1> 12 31 32 90
90 32
30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<1> 12 31 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<1> 12 31 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<1>90 30 12 MEM_B_RAS_L F4 RAS* CK* G8 MEM_B_CLK_N<1> 12 31 32 90
31 32 90 32 90 32 31
90
30 12
32 31 A1 90 32 31 30 12 A1 90 32 31 30 12 A1 90 32 31 30 12 A1
32 31 A4 90 32 31 30 12
A4 90 32 31 30 12
A4 90 32 31 30 12
A4
90 NC NC NC NC
A11
A11
A11
A11
NC
90 32
F2 F2 F2 F2
F10 F10 F10 F10
R3240
2 2
R3250 R3260
2
R3270
2
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
A2
B2
J2
L2
N2
F3
A9
D9
F9
J10
L10
N10
B3
D2
B9
C10
D10
240 240 240 240
1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
1 201 1 201 1 201 1 201
=PP1V5R1V35_S3_MEM_B 8 30 31 SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

PAGE TITLE
C3200 1 C3201 1 C3210 1 C3211 1 C3220 1 C3221 1 C3230 1 C3231 1 1 C3203 1 C3204 1 C3205 1 C3213 1 C3214 1 C3215 1 C3223 1 C3224 1 C3225 1 C3233 1 C3234 1 C3235 DDR3 SDRAM Bank B (2 OF 2)
051-9589 D
402 402 402 402 402 402 402 402 201 201 201 201 201 201 201 201 201 201 201 201
Apple Inc. REVISION
R
4.18.0
20% 20% 20% 20% 20% 20% 20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
6.3V
2 X5R 6.3V
32 OF 132
402 402 402 402 402 402 402 402 201 201 201 201 201 201 201 201 201 201 201 201
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE
8 =PP0V75_S0_MEM_VTT_A
90 29 12 MEM_A_CS_L<1> RP3305 36 1 8
IN
90 28 12 MEM_A_CKE<0> RP3301 36 4 5 5% 1/32W 4X0201
IN
90 29 28 12 MEM_A_A<0> RP3302 36 2 7 5% 1/32W 4X0201 1 C3300
IN
90 29 28 12 MEM_A_A<7> RP3306 36 2 7 5% 1/32W 4X0201 0.47UF
IN 20%
90 29 28 12 MEM_A_A<5> RP3303 36 1 8 5% 1/32W 4X0201
2 4V
IN CERM-X5R-1
90 29 28 12 MEM_A_BA<0> RP3302 36 1 8 5% 1/32W 4X0201 201
IN
90 28 12 MEM_A_ODT<0> RP3301 36 2 7 5% 1/32W 4X0201
IN
MEM_A_A<15> RP3305 36 2 7 5% 1/32W 4X0201
D
90 29 28 12
90 29 28 12
IN
IN MEM_A_BA<1> RP3303 36 2 7
5% 1/32W 4X0201 1 C3302
0.47UF
1 C3303
0.47UF
D
90 29 28 12 MEM_A_A<14> RP3307 36 3 6 5% 1/32W 4X0201 20% 20%
IN 4V 4V
90 29 28 12 MEM_A_A<8> RP3306 36 1 8 5% 1/32W 4X0201 2 CERM-X5R-1 2 CERM-X5R-1
IN 201 201
5% 1/32W 4X0201
90 29 28 12 MEM_A_A<12> RP3305 36 3 6
IN
90 29 28 12 MEM_A_A<9> RP3306 36 4 5 5% 1/32W 4X0201 1 C3304 1 C3305
IN
90 29 28 12 MEM_A_BA<2> RP3302 36 3 6 5% 1/32W 4X0201 0.47UF 0.47UF
IN 20% 20%
90 29 12 MEM_A_ODT<1> RP3304 36 3 6 5% 1/32W 4X0201
2 4V 2 4V
IN CERM-X5R-1 CERM-X5R-1
90 29 28 12 MEM_A_A<4> RP3303 36 4 5 5% 1/32W 4X0201 201 201
IN
90 29 28 12 MEM_A_RAS_L RP3304 36 1 8 5% 1/32W 4X0201
IN
90 29 28 12 MEM_A_A<1> RP3307 36 2 7 5% 1/32W 4X0201
IN
90 29 28 12 MEM_A_WE_L RP3302 36 4 5 5% 1/32W 4X0201 1 C3306 1 C3307
IN
90 29 28 12 MEM_A_A<6> RP3303 36 3 6 5% 1/32W 4X0201 0.47UF 0.47UF
IN 20% 20%
90 29 28 12 MEM_A_A<2> RP3307 36 1 8 5% 1/32W 4X0201
2 4V 2 4V
90 29 28 12 MEM_A_A<3> RP3305 36 4 5 5% 1/32W 4X0201 201 201
IN
5% 1/32W 4X0201
RP3307
1 C3308
90 29 28 12 IN MEM_A_A<13> 36 4 5 0.47UF
20%
90 29 12 MEM_A_CKE<1> RP3304 36 2 7 5% 1/32W 4X0201 4V
2 CERM-X5R-1
IN
90 29 28 12 MEM_A_A<10> RP3304 36 4 5 5% 1/32W 4X0201 201
IN
90 29 28 12 MEM_A_CAS_L RP3301 36 3 6 5% 1/32W 4X0201
IN
90 28 12 MEM_A_CS_L<0> RP3301 36 1 8 5% 1/32W 4X0201
IN
90 29 28 12 MEM_A_A<11> RP3306 36 3 6 5% 1/32W 4X0201 1 C3310
IN
5% 1/32W 4X0201 0.47UF
20%
4V
2 CERM-X5R-1
C 201
C
8 =PP0V75_S0_MEM_VTT_B
90 30 12 MEM_B_ODT<0> RP3322 36 2 7
IN
90 31 30 12 MEM_B_A<13> RP3325 36 1 8 5% 1/32W 4X0201 1 C3320
IN
5% 1/32W 4X0201 0.47UF
90 31 30 12 MEM_B_A<15> RP3328 36 1 8 20%
IN 4V
90 31 30 12 MEM_B_A<11> RP3325 36 2 7 5% 1/32W 4X0201 2 CERM-X5R-1
IN 201
5% 1/32W 4X0201
90 31 30 12 MEM_B_CAS_L RP3328 36 2 7
IN
90 31 30 12 MEM_B_A<1> RP3325 36 3 6 5% 1/32W 4X0201
IN
5% 1/32W 4X0201
MEM Clock Termination 90 30 12 MEM_B_CS_L<0> RP3320 36 2 7 1 C3322 1 C3323
IN
Place RC end termination after last DRAM 90 31 30 12 MEM_B_A<14> RP3326 36 4 5 5% 1/32W 4X0201 0.47UF 0.47UF
IN 20% 20%
Place Source Cterm at neckdown at first DRAM 90 31 30 12 MEM_B_A<0> RP3330 36 2 7 5% 1/32W 4X0201 4V
2 CERM-X5R-1
4V
2 CERM-X5R-1
IN
90 31 30 12 MEM_B_BA<2> RP3320 36 3 6 5% 1/32W 4X0201 201 201
IN
MEM_B_BA<1> RP3330 36 1 8 5% 1/32W 4X0201
R3350 C3351 90 31 30 12 IN
RP3330 36 3 6 5% 1/32W 4X0201
0.1UF 90 31 30 12 IN MEM_B_A<4>
30 RP3324 5% 1/32W
90 28 12 IN MEM_A_CLK_N<0> 1 2 MEM_A_CLK0_TERM_R 1 2 90 31 12 IN MEM_B_CS_L<1>
RP3326
36 4 5
5% 1/32W
4X0201 1 C3324 1 C3325
5% 90 31 30 12 IN MEM_B_A<6> 36 2 7 4X0201 0.47UF 0.47UF
10% 20% 20%
C3350 1
1/20W
MF 6.3V 90 31 30 12 MEM_B_A<12> RP3324 36 1 8 5% 1/32W 4X0201 4V
2 CERM-X5R-1
4V
2 CERM-X5R-1
X5R IN
3.3PF 201
201 90 31 30 12 MEM_B_A<9> RP3326 36 3 6 5% 1/32W 4X0201 201 201
5% IN
PLACE_NEAR=U2900.F7:3.2mm 25V
MEM_B_CKE<0> RP3322 36 3 6 5% 1/32W 4X0201
CERM 2 90 30 12 IN
201 R3351 90 31 30 12 IN MEM_B_A<7> RP3326 36 1 8 5% 1/32W 4X0201
30 RP3330
B 90 28 12 IN MEM_A_CLK_P<0> 1
5%
2 90 31 30 12
90 31 30 12
IN
IN
MEM_B_A<5>
MEM_B_A<3> RP3324
36
36
4
3
5
6
5% 1/32W
5% 1/32W
4X0201
4X0201
1 C3326
0.47UF
20%
1 C3327
0.47UF
20%
B
1/20W
MF 90 31 30 12 MEM_B_A<2> RP3324 36 2 7 5% 1/32W 4X0201
2 4V 2 4V
201
90 31 30 12 MEM_B_A<8> RP3325 36 4 5 5% 1/32W 4X0201 201 201
IN
R3355 C3356 5% 1/32W 4X0201
0.1UF
30 RP3320 36
MEM_A_CLK_N<1> 1 2 MEM_A_CLK1_TERM_R 1 2 MEM_B_BA<0> 4 5
90 29 12 IN
5%
90 31 30 12 IN
MEM_B_A<10> RP3320 36 1 8 5% 1/32W 4X0201 1 C3328
1/20W 10% 90 31 30 12 IN
RP3322 5% 1/32W 0.47UF
C3355 1 MF
201
6.3V
X5R 90 31 30 12 IN MEM_B_RAS_L 36 1 8
5% 1/32W
4X0201 20%
2 4V
3.3PF 201 4X0201 CERM-X5R-1
5% 201
PLACE_NEAR=U3000.F7:3.2mm 25V
CERM 2
201 R3356
30 RP3328 36
MEM_A_CLK_P<1> 1 2 MEM_B_ODT<1> 4 5
90 29 12 IN
5%
90 31 12 IN
MEM_B_CKE<1> RP3328 36 3 6 5% 1/32W 4X0201 1 C3330
1/20W
90 31 12 IN
RP3322 5% 1/32W 4X0201
0.47UF
MF 90 31 30 12 IN MEM_B_WE_L 36 4 5 20%
4V
201 5% 1/32W 4X0201 2 CERM-X5R-1
201
R3360 C3361
0.1UF
30
90 30 12 IN MEM_B_CLK_N<0> 1 2 MEM_B_CLK0_TERM_R 1 2
5%
1/20W 10%
C3360 1 MF
201
6.3V
X5R
PLACE_NEAR=U3170.F7:3.2mm3.3PF
5%
201
25V
CERM 2
201
R3361
30
90 30 12 IN MEM_B_CLK_P<0> 1 2
5%
1/20W
MF
201
A R3365 C3366
0.1UF
30 PAGE TITLE
90 31 12 IN MEM_B_CLK_N<1> 1
5%
2 MEM_B_CLK1_TERM_R 1
10%
2
DDR3 Termination
1/20W DRAWING NUMBER SIZE
C3365 1 MF
201
6.3V
X5R 051-9589 D
3.3PF 201 Apple Inc.
PLACE_NEAR=U3270.F7:3.2mm 5% REVISION
25V
CERM 2
201 R3366
R
4.18.0
30 NOTICE OF PROPRIETARY PROPERTY: BRANCH
90 31 12 IN MEM_B_CLK_P<1> 1 2
5% PROPRIETARY PROPERTY OF APPLE INC.
1/20W THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MF
201 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
33 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Must not enable more than two SO-DIMM margining
8 =PP3V3_S3_VREFMRGN
buffers at once or VRef source may be overloaded.
VREFDQ:LDO_DAC
OMIT
=PPVTT_S3_DDR_BUF R3403
R3418 64 8
200 PLACE_NEAR=J2900.1:2.54mm
1
SHORT
2 PP3V3_S3_VREFMRGN_DAC
10mA max load 1 2
MIN_LINE_WIDTH=0.3 mm CRITICAL 1%
NONE MIN_NECK_WIDTH=0.2 mm DDRVREF_DAC DDRVREF_DAC 1/16W
NONE VOLTAGE=3.3V MF-LF
NONE C3400 1 1 C3401 DDRVREF_DAC 402
PP0V75_S3_MEM_VREFDQ_A
402
2.2UF 0.1UF DDRVREF_DAC 28 29 33 89
20% 20% CRITICAL C3403 1
B1 U3402 MIN_LINE_WIDTH=0.3 mm
VREFDQ:LDO_DAC
D
6.3V
CERM
402-LF
2 2
10V
CERM
402
DDRVREF_DAC
U3400
0.1UF
20%
10V
CERM 2
A2
V+
MAX4253
UCSP
R3404
133
VOLTAGE=0.75V
D
8
402
A1 VREFMRGN_DQ_SODIMMA_BUF 1 2
VDD
A4 1% PLACE_NEAR=R3403.2:1mm
44 IN =I2C_VREFDACS_SCL 6 SCL
MSOP VOUTA 1 VREFMRGN_SODIMMA_DQ A3
V- 1/16W
MF-LF
B4 402
DAC5574
44 BI =I2C_VREFDACS_SDA 7 SDA VOUTB 2 VREFMRGN_SODIMMB_DQ
9 A0 VOUTC 4 VREFMRGN_SODIMMS_CA
Addr=0x98(WR)/0x99(RD) 10 A1 VOUTD 5 VREFMRGN_MEMVREG_FBVREF VREFDQ:LDO_DAC
NOTE: MEMVREG and FRAMEBUF share R3405

GND 200 PLACE_NEAR=J3100.1:2.54mm
a DAC output, cannot enable DDRVREF_DAC 1 2
3
both at the same time! 1 CRITICAL
R3401 1%
1/16W
100K
NC
MF-LF
OMIT 5% 402
1/16W DDRVREF_DAC PP0V75_S3_MEM_VREFDQ_B 30 31 33 89
R3419 MF-LF VREFDQ:LDO_DAC MIN_LINE_WIDTH=0.3 mm
2 402 C2
B1 U3402 MIN_NECK_WIDTH=0.2 mm
SHORT MAX4253 R3406 VOLTAGE=0.75V
1 2 PP3V3_S3_VREFMRGN_CTRL V+ UCSP
MIN_LINE_WIDTH=0.3 mm C1
133
VREFMRGN_DQ_SODIMMB_BUF
Page Notes
NONE MIN_NECK_WIDTH=0.2 mm 1 2
NONE VOLTAGE=3.3V CRITICAL
NONE DDRVREF_DAC C3 C4
1% PLACE_NEAR=R3405.2:1mm
402 DDRVREF_DAC 1/16W
16
C3402 1 V- MF-LF
Power aliases required by this page: 0.1UF VCC
B4 402
- =PP3V3_S3_VREFMRGN 20%
10V
2 U3401
- =PPVTT_S3_DDR_BUF CERM
NC
402 PCA9557 VREFCA:LDO_DAC
- =PPDDR_S3_MEMVREF QFN
6
DDRVREF_DAC R3409
(OD) P0 NC 1
R3402 200 PLACE_NEAR=J2900.126:2.54mm
3 A0 P1 7 VREFMRGN_DQ_SODIMMA_EN 1 2
Signal aliases required by this page: 100K CRITICAL
Addr=0x30(WR)/0x31(RD) 4
A1 P2 9 VREFMRGN_DQ_SODIMMB_EN 5% 1%
- =I2C_VREFDACS_SCL 5 10 VREFMRGN_CA_SODIMMA_EN
1/16W 1/16W
A2 P3 MF-LF MF-LF
- =I2C_VREFDACS_SDA 11 VREFMRGN_CA_SODIMMB_EN 2 402
DDRVREF_DAC 402
PP0V75_S3_MEM_VREFCA_A
P4 DDRVREF_DAC 28 29 89
C -
-
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA =I2C_PCA9557D_SCL 1
P5
P6
12
13
VREFMRGN_MEMVREG_EN
VREFMRGN_FRAMEBUF_EN
C3404
0.1UF
20%
1
A2
B1
V+
U3403
MAX4253
VREFCA:LDO_DAC
R3410
VOLTAGE=0.75V
C
44 IN SCL 10V UCSP
CERM 2 133
BOM options provided by this page: 44 BI =I2C_PCA9557D_SDA 2
SDA P7 14
NC 402
A1 VREFMRGN_CA_SODIMMA_BUF 1 2
DDRVREF_DAC - Stuffs Apple margining circuit.

15 A3 A4 1% PLACE_NEAR=R3409.2:1mm
THRM RESET* V- 1/16W
VREFDQ:LDO - LDO outputs sent to DQ inputs. MF-LF
PAD GND B4 402
VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.
17
8
VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.
VREFCA:LDO_DAC
VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.
VREFCA:LDO - LDO outputs sent to CA inputs. R3411
200 PLACE_NEAR=J3100.126:2.54mm
VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs. 1 2
1%
25 IN PCA9557D_RESET_L DDRVREF_DAC 1/16W
NC
MF-LF
1
R3407 CRITICAL 402
RST* on ’platform reset’ so that system DDRVREF_DAC PP0V75_S3_MEM_VREFCA_B 30 31 89
100K VREFCA:LDO_DAC MIN_LINE_WIDTH=0.3 mm
watchdog will disable margining. 5%
C2
B1 U3403 MIN_NECK_WIDTH=0.2 mm
1/16W MAX4253 R3412 VOLTAGE=0.75V
MF-LF V+ UCSP
NOTE: Margining will be disabled across all 2 402 C1 VREFMRGN_CA_SODIMMB_BUF 1
133
2
soft-resets and sleep/wake cycles.
C4 1% PLACE_NEAR=R3411.2:1mm
33 8 =PPDDR_S3_MEMVREF C3
V- 1/16W
MF-LF
B4 402
CRITICAL PLACE_NEAR=Q3420.6:1mm
PLACE_NEAR=Q3420.6:2mm
NC
VREFDQ:M1_M3 VREFDQ:M1_M3
VREFDQ:M1_M3
Q3420 1
R3421 DDRVREF_DAC
1
C3420 1
SSM6N15FEAPE 0.1UF 1K R3408
1%
MEMRESET_ISOL_LS5V_L 10% 100K
2
33 27 SOT563 16V 1/16W CRITICAL

2 MF-LF 5%
G
X7R-CERM
0402 2
402 1/16W DDRVREF_DAC DDRVREF_DAC
MF-LF DDRVREF_DAC
2 402
C3405 1
C2
B1 U3404
0.1UF MAX4253 R3414
S
PPCPU_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A V+
B
89 10 28 29 33 89
20% UCSP
33.2K
B
6
1
10V C1 VREFMRGN_MEMVREG_BUF 1 2 DDRREG_FB

CERM 2 OUT 64
VREFDQ:M1_M3 402
C4 1%
1 C3
R3422 V- PLACE_NEAR=R7320.2:1mm 1/16W
MF-LF
1K B4 402
PLACE_NEAR=R3421.2:1mm 1%
1/16W
MF-LF
2 402
NOTE: CPU DAC output step sizes:

DDR3 (1.5V) 7.70mV per step
=PPDDR_S3_MEMVREF
DDR3L (1.35V) 6.99mV per step VREFMRGN_FRAMEBUF_BUF
DDRVREF_DAC
NC
33 8
DDRVREF_DAC 1
CRITICAL PLACE_NEAR=Q3420.3:1mm 1 R3413 DDRVREF_DAC
VREFDQ:M1_M3 PLACE_NEAR=Q3420.3:2mm VREFDQ:M1_M3 R3416 100K B1 U3404 DDRVREF_DAC Required zero ohm resistors when no VREF margining circuit stuffed
0 A2
5% MAX4253
Q3420 VREFDQ:M1_M3 1
R3441 5% 1/16W V+ UCSP CRITICAL
1
R3417
1/16W MF-LF PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
SSM6N15FEAPE 1 C3440 1K MF-LF
2
402 A1 0
1% 402 5%
MEMRESET_ISOL_LS5V_L 0.1UF 2
5
33 27 SOT563 10% 1/16W A3 A4 1/16W 116S0004 2 RES,MTL FILM,0,5%,0402,SM,LF R3403,R3405 VREFDQ:LDO

MF-LF MF-LF
G
2
16V
402
V- 402
X7R-CERM 2 2
0402
B4 116S0004 2 RES,MTL FILM,0,5%,0402,SM,LF R3409,R3411 VREFCA:LDO
VREFMRGN_MEMVREG_FBVREF_R
VREFMRGN_FRAMEBUF_BUF_R
S
89 10 PPCPU_MEM_VREFDQ_B PP0V75_S3_MEM_VREFDQ_B 30 31 33 89
NC
3
4
VREFDQ:M1_M3 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
1
R3442 DDRVREF_DAC
1
114S0218 4 RES,MTL FILM,1K,1%,0402,SM,LF R3421,R3422,R3441,R3442 VREFDQ:M1_DAC
1K R3415
1%
PLACE_NEAR=R3441.2:1mm 1/16W 100K 114S0171 2 RES,MTL FILM,332,1%,0402,SM,LF R3404,R3406 VREFDQ:M1_DAC
MF-LF 5%
402 1/16W
2
MF-LF
402
2
A MEM A VREF DQ MEM B VREF DQ MEM A VREF CA MEM B VREF CA MEM VREG GPU Frame Buffer (1.8V, 70% VRef)
PAGE TITLE
DAC Channel: A B C C D D
DDR3/FRAMEBUF VREF MARGINING
DRAWING NUMBER SIZE
PCA9557D Pin: 1 2 3 4 5 6
REVISION
Nominal value 0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A) 1.267V (DAC: 0x8B) R
4.18.0
Margined target: 0.300V - 1.200V (+/- 450mV) 1.000V - 2.000V (+/- 500mV) 1.056V - 1.442V (+/- 180mV) NOTICE OF PROPRIETARY PROPERTY: BRANCH
DAC range: 0.000V - 1.501V (0x00 - 0x74) 0.000V - 3.000V (0x00 - 0x74) 0.000V - 3.300V (0x00 - 0xFF) PROPRIETARY PROPERTY OF APPLE INC.
VRef current: +3.4mA - -3.4mA (- = sourced) +61uA - -61uA (- = sourced) +6.0mA - -5.0mA (- = sourced) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
34 OF 132
DAC step size: 7.69mV / step @ output 8.59mV / step @ output 1.51mV / step @ output
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
L3570 PLACE_NEAR=J3501.15:2.54MM
92 PCIE_AP_R2D_PI_P C3531
1 2 1 2
0.1UF PCIE_AP_R2D_C_P 17 92
IN
10% 16V X7R-CERM0402
0.6NH+/-0.1NH-0.85A
0201 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
NOSTUFF
NOSTUFF
1 C3570 117S0002 4 RES, 0OHM, 0201 L3570,L3571,L3573,L3574
1 C3571
D 2
0.1UF
10%
16V
X5R-CERM
0.1UF
10%
16V
D
0201
2 X5R-CERM
0201
L3571
1 2 92 PCIE_AP_R2D_PI_N 1 2
0.1UF PCIE_AP_R2D_C_N IN 17 92
WIFI_EVENT_L 0.6NH+/-0.1NH-0.85A
10% 16V X7R-CERM0402
IN 7 41 42
3V S3 WLAN FET
0201 C3530
NOSTUFF OMIT_TABLE NOSTUFF PLACE_NEAR=J3501.17:2.54MM
1 C3572 MOSFET DMP2018LFK
1 C3573
0.1UF
10% 0.1UF CHANNEL P-TYPE
16V 10%
2 X5R-CERM 16V 14 mOhm Typ
0201 2 X5R-CERM RDS(ON) @ 2.5V 20 mOhm Max
0201
LOADING 1 A (EDP)
OMIT_TABLE
L3573 CRITICAL
1 2 PCIE_AP_D2R_P
Q3550
NOSTUFF
OUT 17 92
DMP2018LFK
92 7 PCIE_AP_R2D_P 0.6NH+/-0.1NH-0.85A DFN2563-6
1 C3574 0201 1 C3575
92 7 PCIE_AP_R2D_N 155S0367
0.1UF 0.1UF
10% 10% 2
2 16V
NOSTUFF
2 16V
L3504 CURRENT SENSE 4 1
S
X5R-CERM X5R-CERM
CRITICAL 0201 0201 1A PEAK FERR-120-OHM-3A

L3574 42 7 PP3V3_WLAN 1 2 PP3V3_WLAN_F IN 34 99 OUT PP3V3_WLAN_R =PP3V3_S3_WLAN 8 34
514S0335 MIN_LINE_WIDTH=1 mm
0603
MIN_LINE_WIDTH=1 mm MIN_LINE_WIDTH=1 mm
J3501
G
MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm
1 2 PCIE_AP_D2R_N 17 92
OUT VOLTAGE=3.3V VOLTAGE=3.3V VOLTAGE=3.3V
SSD-K99 NOSTUFF C3522 1
C3521 1
3 C3551 1
1
R3551
F-RT-SM1 0.6NH+/-0.1NH-0.85A 10K
1 C3576 0201 1 C3577 0.1uF 0.1uF 0.033UF
C
5%
C
20% 20% 10%
1 0.1UF OMIT_TABLE 0.1UF 10V 10V 16V
1/16W
2 2 2 MF-LF
10% 10% CERM CERM C3550 X5R
2 2 16V
NOSTUFF
2 16V 402 402
0.1UF
402 R3550 2
402
X5R-CERM X5R-CERM
3 0201 0201
PLACE_NEAR=J3501.29:2.54MM PLACE_NEAR=J3501.29:2.54MM 33K
92 7 PCIE_AP_D2R_PI_P 1 2 P3V3WLAN_SS 1 2 PM_WLAN_EN_L IN 70
4
5
92 7 PCIE_AP_D2R_PI_N
CRITICAL
L3501
AIRPORT 10%
16V
X7R-CERM
5%
1/16W
MF-LF
402
6 90-OHM-100MA 0402
DLP11S
7 SYM_VER-1
8 96 7 PCIE_CLK100M_AP_CONN_P 1 2 PCIE_CLK100M_AP_P IN 17 92
9
10
11
96 7 PCIE_CLK100M_AP_CONN_N 4 3 PCIE_CLK100M_AP_N IN 17 92
12 PLACE_NEAR=J3501.11:2.54MM
SIGNAL_MODEL=EMPTY
13
BLUETOOTH PP3V3_S3RS4_BT_F 7 34
BTPWR:S4
=BT_WAKE_L OUT 42
14
PCIE_WAKE_L OUT 7 18
Q3510
SSM3K15FV D 3
15 NOSTUFF BTPWR:S3 NOSTUFF SOD-VESM-HF
16 USB_BT_CONN_N
1
R3517 R35181 1 C3510 1
R3514
91 7
15K 0 0.1UF 15K
17 USB_BT_CONN_P 10%
9
91 7 1% 5% 6.3V 1%
18 BTPWR:S4 1/20W 1/20W 2 X5R 1/20W
PP3V3_S3RS4_BT_F MF MF VCC MF
L3505 201
2 201 201 2 2 201 1 G S 2
VOLTAGE=3.3V 1 Y+ M+ 5 91 USB_BT_WAKE_P
19 2 1 =PP3V3_S4_BT 8
1 C3532 2 Y- M- 4 USB_BT_WAKE_N
20
0.01UF FERR-120-OHM-1.5A NOSTUFF NOSTUFF U3510 91
BTPWR:S4 NOSTUFF
PI3USB102ZLE
21
2
10%
16V
0402-LF
PLACE_NEAR=J3501.27:2.54MM
1
R3515 1R3516 TQFN
D+ 7 USB_BT_P BI 9 91
1
R3512 1R3513
X7R-CERM
15K 15K CRITICAL 15K 15K
0402
1% 1% D- 6 USB_BT_N BI 9 91 1% 1%
BTPWR:S3 1/20W 1/20W 1/20W 1/20W
MF MF MF MF
L3506
B 2 1 =PP3V3_S3_BT 8
2 201 2 201 10 SEL
GND
OE* 8 2 201 2 201 Supervisor & CLKFREG # Isolation B
BTPWR:S4
FERR-120-OHM-1.5A Delay = 130 ms +/- 20%
R3511
3
0402-LF
PLACE_NEAR=J3501.27:2.54MM 0 PP3V3_WLAN_F =PP3V3_S3_WLAN
IN PM_SLP_S4_L 1 2 BTMUX_SEL 34 99 8 34
5%
1/20W
SEL OUTPUT
NOSTUFF
MF CRITICAL
1
201 C3511 1 L USB_BT_WAKE 1
R3553
1
R3554 VDD
0.01UF H USB_BT 100K 232K 1
C3540
10%
16V
X7R-CERM 2
1%
1/16W
1%
1/16W U3540 0.1uF
20%
0402
2
MF-LF
402
2
MF-LF
402
SLG4AP041V 2
10V
CERM
TDFN 402
P3V3WLAN_VMON
2 SENSE
+
VREF -
518S0767 1 CONN,HDR,TWIN-AX,P=0.4MM,6P,HF J3502 CRITICAL DLY
7 AP_RESET_CONN_L
4 RESET* AP_RESET_L
OMIT MR* 3 IN 25
CRITICAL
J3502 EN 6
AP_PWR_EN
19 24 70
CCR20-6K710S IN
F-RT-SM 7 AP_CLKREQ_Q_L OUT 8 OUT 17
7 IN (OD)
8 AP_CLKREQ_L
THRM
PAD GND
1
R3555
5
6 =I2C_ALS_SDA BI 44
100K
5 =I2C_ALS_SCL IN 44 1%
275 mA peak 1/16W
4 7 PP5V_S3_ALSCAMERA_F PLACE_NEAR=J3502.6:2.54MM MF-LF
MIN_LINE_WIDTH=0.5 mm 206 mA nominal max 402
3 USB_CAMERA_CONN_N 2
ALS
91 7 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V L3508
A USB_CAMERA_CONN_P
2
A
91 7
FERR-120-OHM-1.5A
1
SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012
2 1 =PP5V_S3_ALSCAMERA 8
PAGE TITLE
7
CRITICAL
L3507
CAMERA 0402-LF
X29/ALS/CAMERA CONNECTOR
90-OHM
1
C3552 DRAWING NUMBER SIZE
DLP0NS
SYM_VER-1
0.1uF
20%
10V
2 CERM REVISION
1 2 USB_CAMERA_N BI 19 91 402 R
4.18.0
4 3 USB_CAMERA_P BI 19 91 THE INFORMATION CONTAINED HEREIN IS THE
PLACE_NEAR=J3502.3:2.54MM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
35 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
NO_TEST=TRUE
NO_TEST=TRUE
92 9 IN PCIE_TBT_R2D_C_P<0> C3600 1 2
AB9 OMIT_TABLE AD5
C3640 1 2 PCIE_TBT_D2R_P<0> OUT 9 92
10% 16V X5R-CERM0201 92 PCIE_TBT_R2D_P<0> PERP_0 PETP_0 92 PCIE_TBT_D2R_C_P<0> 10% 16V X5R-CERM 0201
0.1UF 0.1UF
92 PCIE_TBT_R2D_N<0> AA10
PERN_0 U3600 PETN_0 AD7 92 PCIE_TBT_D2R_C_N<0>
92 9 IN PCIE_TBT_R2D_C_N<0> C3601 1 2
CACTUSRIDGE4C C3641 1 2
PCIE_TBT_D2R_N<0> OUT 9 92
10% 16V X5R-CERM 0201 NO_TEST=TRUE 10% 16V X5R-CERM 0201
0.1UF FCBGA NO_TEST=TRUE 0.1UF
NO_TEST=TRUE NO_TEST=TRUE
(SYM 1 OF 2)
92 9 IN PCIE_TBT_R2D_C_P<1> C3602 1 2 C3642 1 2 PCIE_TBT_D2R_P<1> OUT 9 92
PCIE GEN2
PCIE_TBT_R2D_P<1> AA12 AD9 PCIE_TBT_D2R_C_P<1>
10% 16V X5R-CERM 0201 92 PERP_1 PETP_1 92 10% 16V X5R-CERM 0201
0.1UF AB13 AD11
0.1UF
92 PCIE_TBT_R2D_N<1> PERN_1 PETN_1 92 PCIE_TBT_D2R_C_N<1>
C3603 C3643
RECEIVE
TRANSMIT
92 9 IN PCIE_TBT_R2D_C_N<1> 1 2 1 2
PCIE_TBT_D2R_N<1> OUT 9 92
10% 16V X5R-CERM 0201 NO_TEST=TRUE 10% 16V X5R-CERM 0201
0.1UF NO_TEST=TRUE 0.1UF
NO_TEST=TRUE
NO_TEST=TRUE
PCIE_TBT_R2D_C_P<2> C3604 C3644 PCIE_TBT_D2R_P<2>
D
1 2 1 2
92 9 IN OUT 9 92
PCIE_TBT_R2D_P<2> AB15 AD13 PCIE_TBT_D2R_C_P<2>
PERP_2 PETP_2
D 10% 16V X5R-CERM 0201 92 92 10% 16V X5R-CERM 0201
0.1UF AA16 AD15
0.1UF
92 PCIE_TBT_R2D_N<2> PERN_2 PETN_2 92 PCIE_TBT_D2R_C_N<2>
92 9 IN PCIE_TBT_R2D_C_N<2> C3605 1 2 C3645 1 2 PCIE_TBT_D2R_N<2> OUT 9 92
10% 16V X5R-CERM 0201 10% 16V X5R-CERM 0201
0.1UF NO_TEST=TRUE NO_TEST=TRUE 0.1UF
37 36 35 =PP3V3_S4_TBT
NO_TEST=TRUE NO_TEST=TRUE
92 9 IN PCIE_TBT_R2D_C_P<3> C3606 1 2
AA18 AD17
C3646 1 2 PCIE_TBT_D2R_P<3> OUT 9 92
10% 16V X5R-CERM0201 92 PCIE_TBT_R2D_P<3> PERP_3 PETP_3 92 PCIE_TBT_D2R_C_P<3> 10% 16V X5R-CERM 0201
R36101 0.1UF
92 PCIE_TBT_R2D_N<3> AB19
PERN_3 PETN_3 AD19 92 PCIE_TBT_D2R_C_N<3>
0.1UF
47K 92 9 IN PCIE_TBT_R2D_C_N<3> C3607 1 2 C3647 1 2 PCIE_TBT_D2R_N<3> OUT 9 92
5% 10% 16V X5R-CERM 0201 NO_TEST=TRUE 10% 16V X5R-CERM 0201
1/20W 0.1UF NO_TEST=TRUE 0.1UF
MF R6 U20 37 36 35 =PP3V3_S4_TBT
201 2 37 IN TBT_PCIE_RESET_L PERST_N RSENSE TBT_RSENSE
37 IN TBT_PWR_ON_POC_RST_L J2
PWR_ON_POC_RSTN W20
RBIAS TBT_RBIAS 1
R3655
NO STUFF
1K R36851 1
R3686
=PP3V3_TBTLC_RTR 8 35 36 37 C3610 1 TP_TBT_MONDC0 AD23
MONDC0
NC U4 1% 10K
5% 5%
10K
0.1UF OMIT TP_TBT_MONDC1 AC24
MONDC1 NC 1/20W
MF 1/20W 1/20W
10% 201 MF MF
16V
X5R-CERM 2
0201
R3615 1 DEBUG: For monitoring current/voltage
2
201 2 2 201
C3690 1
R3692 1
1
R3693 NOSTUFF TBT_MONOBSP W18
MONOBS_P
R3690 1
1
R3691 1UF NONE W16 84 35 TBT_A_DP_PWRDN
3.3K 3.3K NONE TBT_MONOBSN MONOBS_N
3.3K 3.3K 10%
6.3V 5% 5% NONE Not used in host mode. 85 35 TBT_B_DP_PWRDN
PCIE RESET
5% 5% 2 1/20W 1/20W 0201 2 DEBUG: For monitoring clock
TBT_A_HV_EN
MISC
1/20W 1/20W
CERM
402 CRITICAL MF MF
TP_TBT_THERM_DP Y7 PCIE_RST_0_N N6 TP_TBT_PCIE_RESET0_L 7 84 37 35
MF MF 201 201 47 THERMDA
201
2 2
201 8 OMIT_TABLE 2 2
Use AA8 GND ball for THERM_DN PCIE_RST_1_N T1 TP_TBT_PCIE_RESET1_L 7 85 37 35 TBT_B_HV_EN
VCC Y5 TP_TBT_PCIE_RESET2_L
R4 PCIE_RST_2_N 7
93 TBT_SPI_MOSI EE_DI
PCIE_RST_3_N U2 TP_TBT_PCIE_RESET3_L R36881 1
R3687
EEPROM
7
(TBT_SPI_MOSI) 5 D U3690
M95256-RMC6XG
Q 2 (TBT_SPI_MISO) 93 TBT_SPI_MISO
TBT_SPI_CS_L
P5
AD3
EE_DO
10K 10K
6
93 EE_CS_N W6 5% 5%
(TBT_SPI_CLK) C MLP W4 PCIE_CLKREQ_OD_N =TBT_CLKREQ_L OUT 37 1/20W 1/20W
93 TBT_SPI_CLK EE_CLK =PP3V3_TBTLC_RTR 8 35 36 37 MF MF
201 2 2 201
(TBT_SPI_CS_L) 1 S*
EN_LC_PWR K5 TBT_EN_LC_PWR
JTAG/TEST PORT
V1 OUT 37
20 IN JTAG_TBT_TDI TDI 1
R3698
TBTROM_WP_L 3 W*
JTAG_TBT_TMS AB3
20 IN TMS 10K
REFCLK_100_IN_P AB21 PCIE_CLK100M_TBT_P 17 92 5%
C
IN
C 7 HOLD*
TBTROM_HOLD_L JTAG_TBT_TCK AA6
20 IN TCK AD21 1/20W
R2 REFCLK_100_IN_N PCIE_CLK100M_TBT_N IN 17 92 MF
VSS THM 20 OUT JTAG_TBT_TDO TDO 2
201
R3695
PAD N4
TBT_TEST_EN TEST_EN 806
CLOCKS
4 9 XTAL_25_IN AA24 91 SYSCLK_CLK25M_TBT_R 1 2 SYSCLK_CLK25M_TBT 25 91
TBT_TEST_PWR_GOOD AB5 IN
TEST_PWR_GOOD
XTAL_25_OUT AB23 TP_TBT_XTAL25OUT 7 1%
1/20W
Divides 3.3V to 1.8V
MF
1 1
R3625 R3629 95 35 7 DP_TBTSNK0_ML_P<3> E14
DPSNK0_3_P TMU_CLK_OUT AA4 TBT_TMU_CLK_OUT
201
0 0
5% 5% 95 35 7 DP_TBTSNK0_ML_N<3> D13
DPSNK0_3_N TMU_CLK_IN Y3 TBT_TMU_CLK_IN 37 36 35 8 =PP3V3_TBTLC_RTR
1/20W 1/20W
MF MF E16 NO STUFF
201 2 2 201 95 35 7 DP_TBTSNK0_ML_P<2> DPSNK0_2_P
95 35 7 DP_TBTSNK0_ML_N<2> D15
DPSNK0_2_N DPSRC_3_P A14 TP_DP_TBTSRC_ML_CP<3> 7
R3697
1
R3699
1 1
R3696 R36801
DISPLAYPORT
100K 10K
SINK PORT 0
B15
10K 1K
E18 DPSRC_3_N TP_DP_TBTSRC_ML_CN<3> 7 5% 5% 5% 5%
95 35 7 DP_TBTSNK0_ML_P<1> DPSNK0_1_P 1/20W 1/20W 1/20W 1/20W
D17 A12 MF MF MF MF
DP_TBTSNK0_ML_N<1> DPSNK0_1_N DPSRC_2_P TP_DP_TBTSRC_ML_CP<2>
95 35 7 7
2 201 201 2
2 201
201 2
B13 TP_DP_TBTSRC_ML_CN<2>
DPSRC_2_N 7
DP_TBTSNK0_ML_P<0> E20
DPSNK0_0_P TBT_DDC_XBAR_EN_L
SOURCE PORT 0
95 35 7 82 35
DP_TBTSNK0_ML_N<0> D19 A10 TP_DP_TBTSRC_ML_CP<1>

95 35 7 DPSNK0_0_N DPSRC_1_P 7
A6 DPSRC_1_N B11 TP_DP_TBTSRC_ML_CN<1> 7 35 TBT_GPIO_9

95 35 7 DP_TBTSNK0_AUXCH_P DPSNK0_AUX_P
35 TBT_GPIO_14
SNK0 AC Coupling
95 35 7 DP_TBTSNK0_AUXCH_N B5
DPSNK0_AUX_N DPSRC_0_P A8 TP_DP_TBTSRC_ML_CP<0> 7
1
R3681 NO STUFF
DP_TBTSNK0_HPD U6 DPSRC_0_N B9 TP_DP_TBTSRC_ML_CN<0> 7 0 R36831 R3682
1
82 OUT DPSNK0_HPD 5%
95 77 7 IN DP_TBTSNK0_ML_C_P<0> C3620 1 2 DP_TBTSNK0_ML_P<0> 7 35 95 C2 1/20W 10K 10K
10% 16V DPSRC_AUX_P TP_DP_TBTSRC_AUXCH_CP 7 MF 5% 5%
0.1UF X5R-CERM 0201
DP_TBTSNK1_ML_P<3> E6 D3 TP_DP_TBTSRC_AUXCH_CN 2 201 1/20W 1/20W
DP_TBTSNK0_ML_C_N<0> C3621 1 2 DP_TBTSNK0_ML_N<0> R3630 1 95 35 7 DPSNK1_3_P DPSRC_AUX_N 7 MF
201 2
MF
95 77 7 IN
10% 16V
7 35 95
100K 95 35 7 DP_TBTSNK1_ML_N<3> D5
DPSNK1_3_N 2 201
0.1UF V3 DP_TBTSRC_HPD
X5R-CERM0201 5% DPSRC_HPD_OD
1/20W E8
MF 95 35 7 DP_TBTSNK1_ML_P<2> DPSNK1_2_P
95 77 7 IN DP_TBTSNK0_ML_C_P<1> C3622 1 2 DP_TBTSNK0_ML_P<1> 7 35 95 201 D7
10% 16V
2
95 35 7 DP_TBTSNK1_ML_N<2> DPSNK1_2_N R3632 1
Y1 TBT_GO2SX_BIDIR
SINK PORT 1
0.1UF X5R-CERM 0201 GPIO_2/GO2SX BI 20
100K
95 77 7 IN DP_TBTSNK0_ML_C_N<1> C3623 1 2
10% 16V
DP_TBTSNK0_ML_N<1> 7 35 95 95 35 7 DP_TBTSNK1_ML_P<1> E10
DPSNK1_1_P (FORCE_PWR) GPIO_3 W2 TBT_PWR_EN IN 20 25 5%
1/20W
CR HPD INPUTS (S4) FORWARDED TO GMUX (S0)
0.1UF DP_TBTSNK1_ML_N<1> D9
DPSNK1_1_N GPIO_4/WAKE_N_OD J4 =TBT_WAKE_L =PP3V3_S0_DPMUX_UC
B 95 77 7 IN DP_TBTSNK0_ML_C_P<2> C3624 1
X5R-CERM 0201
2 DP_TBTSNK0_ML_P<2> 7 35 95
82 OUT
95 35 7
95 35 7 DP_TBTSNK1_ML_P<0> E12
DPSNK1_0_P
GPIO_5/CIO_PLUG_EVENT AA2 TBT_CIO_PLUG_EVENT
OUT
OUT
18 42
20
MF
201
2
82 78 35 8
NOSTUFF
U3610
B
10% 16V D11 GPIO_6/CIO_SDA_OD AB1 =I2C_TBTRTR_SDA BI 44 74LVC2G126GT/S500
0.1UF X5R-CERM 0201 R3631 1 95 35 7 DP_TBTSNK1_ML_N<0> DPSNK1_0_N 8 SOT833
GPIO_7/CIO_SCL_OD AC2 =I2C_TBTRTR_SCL IN 44
95 77 7 IN DP_TBTSNK0_ML_C_N<2> C3625 1 2 DP_TBTSNK0_ML_N<2> 7 35 95 100K VCC DP_TBTPB_HPD_BUF
10% 16V 5% 95 35 7 DP_TBTSNK1_AUXCH_P A4
DPSNK1_AUX_P GPIO_8/EN_CIO_PWR_OD* P3
(TBT_EN_CIO_PWR_L) TBT_PWR_REQ_L 19 85 35 IN DP_TBTPB_HPD 5
A Y
3
OUT 82
0.1UF X5R-CERM0201 1/20W
MF 95 35 7 DP_TBTSNK1_AUXCH_N B3
DPSNK1_AUX_N GPIO_9/OK2GO2SX_OD* M5 35 TBT_GPIO_9 GND
201 TBT_EN_CIO_PWR_L OUT 37 OE
95 77 7 IN DP_TBTSNK0_ML_C_P<3> C3626 1 2
DP_TBTSNK0_ML_P<3> 7 35 95
2
T5 GPIO_14 T3 TBT_GPIO_14 35 MAKE_BASE=TRUE 4
10% 16V DP_TBTSNK1_HPD DPSNK1_HPD 7
0.1UF X5R-CERM0201 GPIO_15 V5 TBT_DDC_XBAR_EN_L OUT 35 82
R3644
1
95 77 7 IN DP_TBTSNK0_ML_C_N<3> C3627 1 2 DP_TBTSNK0_ML_N<3> 7 35 95 NOSTUFF 100K

0.1UF
10% 16V
X5R-CERM0201 93 84 7 OUT TBT_A_R2D_C_P<0> G24
PA_CIO0_TX_P/DP_SRC_0_P PB_CIO2_TX_P/DP_SRC_0_P R24 TBT_B_R2D_C_P<0> OUT 7 85 93
R3642 5%
1/20W
1K MF
93 84 7 OUT TBT_A_R2D_C_N<0> E24
PA_CIO0_TX_N/DP_SRC_0_N PB_CIO2_TX_N/DP_SRC_0_N N24 TBT_B_R2D_C_N<0> OUT 7 85 93 82 78 35 8 =PP3V3_S0_DPMUX_UC 1 2 DP_TBTPB_HPD_BUF_EN 201
2
95 83 7 DP_TBTSNK0_AUXCH_C_P C3628 1 2 DP_TBTSNK0_AUXCH_P 7 35 95 5%
PORT0
PORT2
BI TBT_A_D2R_P<0> G22 R22 TBT_B_D2R_P<0>
10% 16V 93 84 7 IN PA_CIO0_RX_P PB_CIO2_RX_P IN 7 85 93 1/20W
0.1UF X5R-CERM0201 MF
93 84 7 IN TBT_A_D2R_N<0> E22
PA_CIO0_RX_N PB_CIO2_RX_N N22 TBT_B_D2R_N<0> IN 7 85 93 201
95 83 7 BI DP_TBTSNK0_AUXCH_C_N C3629 1 2 DP_TBTSNK0_AUXCH_N 7 35 95
10% 16V 82 78 35 8 =PP3V3_S0_DPMUX_UC
0.1UF X5R-CERM 0201 84 82 OUT TBT_A_CONFIG1_BUF K1
PA_CONFIG1/CIO_0_LSEO PB_CONFIG1/CIO_2_LSEO P1 TBT_B_CONFIG1_BUF OUT 82 85
TBT_A_CONFIG2_RC G4 H5 TBT_B_CONFIG2_RC NOSTUFF

84 IN PA_CONFIG2/CIO_0_LSOE PB_CONFIG2/CIO_2_LSOE IN 85 U3610
74LVC2G126GT/S500
SNK1 AC Coupling 8 SOT833
93 84 7 OUT TBT_A_R2D_C_P<1> L24

PA_CIO1_TX_P/DP_SRC_2_P PB_CIO3_TX_P/DP_SRC_2_P W24 TBT_B_R2D_C_P<1> OUT 7 85 93 VCC DP_TBTPA_HPD_BUF
95 77 7 IN DP_TBTSNK1_ML_C_P<0> C3630 1 2 DP_TBTSNK1_ML_P<0> 7 35 95 84 35 IN DP_TBTPA_HPD 2 6
OUT 82
10% 16V 93 84 7 OUT TBT_A_R2D_C_N<1> J24
PA_CIO1_TX_N/DP_SRC_2_N PB_CIO3_TX_N/DP_SRC_2_N U24 TBT_B_R2D_C_N<1> OUT 7 85 93
A Y
0.1UF X5R-CERM 0201 GND
OE
PORT1
PORT3
95 77 7 IN DP_TBTSNK1_ML_C_N<0> C3631 1 2 DP_TBTSNK1_ML_N<0> 7 35 95 93 84 7 IN TBT_A_D2R_P<1> L22
PA_CIO1_RX_P PB_CIO3_RX_P W22 TBT_B_D2R_P<1> IN 7 85 93 4
0.1UF
10% 16V
X5R-CERM0201 93 84 7 TBT_A_D2R_N<1> J22
PA_CIO1_RX_N PB_CIO3_RX_N U22 TBT_B_D2R_N<1> 7 85 93
1 R36451
IN IN
100K
DP_TBTSNK1_ML_C_P<1> C3632 DP_TBTSNK1_ML_P<1> TBT_A_LSTX N2 L6 TBT_B_LSTX NOSTUFF 5%
95 77 7 IN
1 2
7 35 95 84 OUT PA_LSTX/CIO_1_LSEO PB_LSTX/CIO_3_LSEO OUT 85
R3643 1/20W
10% 16V MF
0.1UF X5R-CERM0201 84 IN TBT_A_LSRX J6
PA_LSRX/CIO_1_LSOE PB_LSRX/CIO_3_LSOE G6 TBT_B_LSRX IN 85 1K 201
2
82 78 35 8 =PP3V3_S0_DPMUX_UC 1 2 DP_TBTPA_HPD_BUF_EN
95 77 7 IN DP_TBTSNK1_ML_C_N<1> C3633 1 2 DP_TBTSNK1_ML_N<1> 7 35 95
10% 16V 5%
DP_TBTPA_ML_C_P<1> A16 A20 DP_TBTPB_ML_C_P<1>
PORTS
0.1UF X5R-CERM 0201 93 84 OUT PA_DPSRC_1_P PB_DPSRC_1_P OUT 85 93 1/20W
MF
DP_TBTPA_ML_C_N<1> DP_TBTPB_ML_C_N<1>
A
B17 B21
PA_DPSRC_1_N PB_DPSRC_1_N
A
93 84 85 93 201
DP_TBTSNK1_ML_C_P<2> C3634 1 2
DP_TBTSNK1_ML_P<2> OUT OUT
95 77 7 IN 7 35 95
10% 16V SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012
0.1UF X5R-CERM 0201 93 84 OUT DP_TBTPA_ML_C_P<3> A18
PA_DPSRC_3_P PB_DPSRC_3_P A22 DP_TBTPB_ML_C_P<3> OUT 85 93
PAGE TITLE
DP_TBTSNK1_ML_C_N<2> C3635 1 2 DP_TBTSNK1_ML_N<2> DP_TBTPA_ML_C_N<3> B19
PA_DPSRC_3_N PB_DPSRC_3_N B23 DP_TBTPB_ML_C_N<3>
95 77 7 IN
0.1UF
10% 16V
X5R-CERM0201
7 35 95 93 84 OUT OUT 85 93
Thunderbolt Host (1 of 2)
DRAWING NUMBER SIZE
DP_TBTPA_AUXCH_C_P F3
PA_AUX_P PB_AUX_P D1 DP_TBTPB_AUXCH_C_P
95 77 7 IN DP_TBTSNK1_ML_C_P<3> C3636 1 2
10% 16V
DP_TBTSNK1_ML_P<3> 7 35 95
93 84
93 84
BI
DP_TBTPA_AUXCH_C_N F1
PA_AUX_N PB_AUX_N E2 DP_TBTPB_AUXCH_C_N
BI 85 93
85 93 Apple Inc. 051-9589 D

0.1UF BI BI
X5R-CERM 0201 REVISION
95 77 7 IN DP_TBTSNK1_ML_C_N<3> C3637 1 2
10% 16V
DP_TBTSNK1_ML_N<3> 7 35 95 84 35 IN DP_TBTPA_HPD H1
PA_DPSRC_HPD PB_DPSRC_HPD K3 DP_TBTPB_HPD IN 35 85
R
4.18.0
0.1UF X5R-CERM 0201
TBT_A_HV_EN G2 M1 TBT_B_HV_EN NOTICE OF PROPRIETARY PROPERTY: BRANCH
84 37 35 OUT GPIO_0/PA_HV_EN/BYP0 GPIO_1/PB_HV_EN/BYP0 OUT 35 37 85
84 OUT TBT_A_CIO_SEL M3
GPIO_10/PA_CIO_SEL/BYP1 GPIO_11/PB_CIO_SEL/BYP1 L2 TBT_B_CIO_SEL OUT 85 PROPRIETARY PROPERTY OF APPLE INC.
95 83 7 BI DP_TBTSNK1_AUXCH_C_P C3638 1 2 DP_TBTSNK1_AUXCH_P 7 35 95 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
TBT_A_DP_PWRDN H3
GPIO_12/PA_DP_PWRDN/BYP2 GPIO_13/PB_DP_PWRDN/BYP2 L4 TBT_B_DP_PWRDN
0.1UF
10% 16V
X5R-CERM 0201
84 35 OUT OUT 35 85
36 OF 132
95 83 7 BI DP_TBTSNK1_AUXCH_C_N C3639 1 2 DP_TBTSNK1_AUXCH_N 7 35 95
For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.
0.1UF
10% 16V
X5R-CERM 0201 IV ALL RIGHTS RESERVED 35 OF 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 =PP1V05_TBTLC_RTR
???? mW (Single Port)
250 mW (Dual Port) =PP1V05_TBTCIO_RTR 8
CRITICAL
D EDP: 1600 mA C3700
10UF
20%
1 1
C3710
1.0UF
20%
1
C3711
1.0UF
20%
1
C3712
1.0UF
20%
1
C3713
1.0UF
20%
1
C3714
1.0UF
20% J10 OMIT_TABLE K11
???? mW (Single-Port)
2700 mW (Dual-Port)
D
6.3V 10V 10V 10V 10V 10V VCC1P0_ON VCC1P0
CERM-X5R 2 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM J12 U3600 K15 EDP: 1100 mA
0402-1 0201-1 0201-1 0201-1 0201-1 0201-1 VCC1P0_ON VCC1P0
J14
VCC1P0_ON CACTUSRIDGE4C VCC1P0 L10
C3740 1
C3741 1
C3742 1
C3743 1
C3744 1
C3745 1 1
C3705
J16 FCBGA L14 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 10UF
VCC1P0_ON (SYM 2 OF 2) VCC1P0 20% 20% 20% 20% 20% 20% 20%
J8 M11 10V 10V 10V 10V 10V 10V 6.3V
VCC1P0_ON VCC1P0 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 2 CERM-X5R
K17 M15 0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 0402-1
VCC1P0_ON VCC1P0
C3701 1 1 C3715 1 C3716 1 C3717 T15 N10
10UF 1.0UF 1.0UF 1.0UF VCC1P0_ON VCC1P0
20% 20% 20% 20% U14 N14
6.3V 10V 10V 10V VCC1P0_ON VCC1P0
CERM-X5R 2 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM V7 P11
0402-1 0201-1 0201-1 0201-1 VCC1P0_ON VCC1P0
W8 P15
VCC1P0_ON VCC1P0
R10
G10 VCC1P0
VCC1P0_PE
VCC
R14
G12 VCC1P0
VCC1P0_PE T11
G14 VCC1P0
VCC1P0_PE U10
G16 VCC1P0
VCC1P0_PE V11
G18 VCC1P0
VCC1P0_PE W10
=PP3V3_TBTLC_RTR 8 35 37
H19 VCC1P0
VCC1P0_PE ??? mW (Single-Port)
K19
VCC1P0_PE M7 250 mW (Dual-Port)
M19 VCC3P3
VCC1P0_PE P7 EDP: 240 mA
P19 VCC3P3
VCC1P0_PE
T19 VCC3P3 T7
C3770 1
C3771 1
C3772 1
C3773 1
C3774 1 1
C3760
VCC1P0_PE 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 10UF
V15 L18 20% 20% 20% 20% 20% 20%
VCC1P0_PE VCC3P3_CIO 10V 10V 10V 10V 10V 6.3V
V19 N18 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 2 CERM-X5R
VCC1P0_PE VCC3P3_CIO 0201-1 0201-1 0201-1 0201-1 0201-1 0402-1
W12 R18
VCC1P0_PE VCC3P3_CIO
W14
VCC1P0_PE H11
VCC3P3_DP
C G8
H9
VCC1P0_DPAUX
VCC1P0_DPAUX
VCC3P3_DP
VCC3P3_DP
H13
H15 C
H17
VCC3P3_DP
AD1 H7
VSS VCC3P3_DPAUX
K13 PP3V3_S4_TBT
VSS
K9
VSS
VOLTAGE=3.3V
MAKE_BASE=TRUE
R3790
L12 =PP3V3_S4_TBT 1
0 2 =PP3V3_S4_TBT_R
VSS 37 35 8
L16 K7 5%
VSS VCC3P3_POC EDP: 10 mA
1/16W
L8 MF-LF
VSS
402
M13
VSS VSSPE C22
C3790 1
M17
VSS VSSPE C24 1.0UF
20%
M9 C4 10V
VSS VSSPE X5R-CERM 2
N12 C6 0201-1
VSS VSSPE
N16 C8
VSS VSSPE
N8 D21
VSS VSSPE
P13 D23
VSS VSSPE
P17 E4
VSS VSSPE
P9 F11
VSS VSSPE
R12 F13
VSS VSSPE
R16 F15
VSS VSSPE
R8 F17
VSS VSSPE
T13 F19
VSS VSSPE
T17 F21
VSS VSSPE
T9 F23
VSS VSSPE
U12 F5
VSS VSSPE
GND
U16 F7
VSS VSSPE
B U8
V9
VSS
VSS
VSSPE
VSSPE
F9
G20
B
H21
VSSPE
A2 H23
VSSPE VSSPE
A24 J18
VSSPE VSSPE
AA14 J20
VSSPE VSSPE
AA20 K21
VSSPE VSSPE
AA22 K23
VSSPE VSSPE
AA8 L20
VSSPE VSSPE
AB11 M21
VSSPE VSSPE
AB17 M23
VSSPE VSSPE
AB7 N20
VSSPE VSSPE
AC10 P21
VSSPE VSSPE
AC12 P23
VSSPE VSSPE
AC14 R20
VSSPE VSSPE
AC16 T21
VSSPE VSSPE
AC18 T23
VSSPE VSSPE
AC20 U18
VSSPE VSSPE
AC22 V13
VSSPE VSSPE
AC4 V17
VSSPE VSSPE
AC6 V21
VSSPE VSSPE
AC8 V23
VSSPE VSSPE
B1 Y11
VSSPE VSSPE
B7 Y13
VSSPE VSSPE
C10 Y15
VSSPE VSSPE
C12 Y17
VSSPE VSSPE
A C14
C16
VSSPE
VSSPE
VSSPE
VSSPE
Y19
Y21 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A

PAGE TITLE
C18 Y23
VSSPE VSSPE
C20
VSSPE VSSPE Y9 Thunderbolt Host (2 of 2)
DRAWING NUMBER SIZE

REVISION
R
4.18.0
37 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:
- =PPVIN_SW_TBTBST (8-13V Boost Input) CRITICAL
SI8409DB:
Vds(max):
Vgs(max):
-30V
+/-12V
Thunderbolt 15V Boost Regulator
- =PP15V_TBT_REG (15V Boost Output) TBTBST:Y CRITICAL
Vgs(th): -1.4V
- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input) Q3880 TBTBST:Y
Rds(on): 46mOhm @ 4.5V Vgs L3895
- =PP3V3_TBTLC_FET (3.3V FET Output)
=PPVIN_SW_TBTBST SI8409DB
9 8 BGA Id(max): 3.7A @ 70C 3.3UH-6.5A
- =PP3V3_S0_TBTPWRCTL
8-13V Input PPVIN_SW_TBTBST 1 2 TBTBST_BOOST
3
- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input) 8
Changes required MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
D
PIMB063T-SM
2
- =PP1V05_TBTLC_FET (1.05V FET Output) MIN_NECK_WIDTH=0.25 mm TBTBST:Y TBTBST:Y MIN_NECK_WIDTH=0.25 mm
for 2S. SWITCH_NODE=TRUE
Signal aliases required by this page:
TBTBST:Y TBTBST:Y Voltage not specified here,
add property on another page.
C3860 1 C3861 1 DIDT=TRUE
10UF 10UF TBTBST_SNS1
R38801 C3880 D
G
- =TBT_CLKREQ_L 1 TBTBST:Y 20% 20%
D - =TBT_RESET_L
470K
5%
1/16W 10%
0.1UF
R3891 1
25V
X5R-CERM 2
0603
25V
X5R-CERM 2
0603
TBTBST:Y
R38891 1 2
1
25V 200K CRITICAL
27
8
9
20
21
38
MF-LF 2 X5R
BOM options provided by this page: 402 2 402 1% 0
1/16W VIN 5% TBTBST:Y
TBTBST:Y - Stuffs 15V boost circuitry. MF-LF SW 1/20W
TBTBST_PWREN_DIV_L 402 2 CRITICAL MF
201 2
D3895
TBTBST:Y <R1> TBTBST_EN_UVLO 25 EN/UVLO TBTBST:Y PDS540XF
SNS1 6 PWRDI5
R3881 1
U3890 TBTBST_SNS2 3
330K LT3957 SNS2 3
5%
1/16W TBTBST_INTVCC 28 INTVCC QFN
XW3895
SM
MF-LF 2 1
402 2 PLACE_NEAR=C3895.1:2 mm
1 TBTBST_VSNS
TBTBST_PWREN_L TBTBST_VC 30 VC
2 TBTBST:Y
TBTBST:Y
TBTBST:Y TBTBST:Y TBTBST:Y TBTBST:Y TBTBST:Y TBTBST:Y NC 10
NC TBTBST:Y R38951
Q3805 D 6 Q3805 D 3 C3890 1 C3891 1 C3892 1 1 C3887 R38931 TBTBST_RT 33 RT 35 1 C3888 137K
SSM6N37FEAPE SSM6N37FEAPE 2.2UF 2.2UF 2.2UF 68PF 49.9K 36 10PF 1% =PP15V_TBT_REG 8 9
20% 20% 20% 5% 1% 5% 1/16W
SOT563 SOT563 1/16W MF-LF
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2 2 50V
COG-CERM MF-LF
402 2 TBTBST_SS 32 SS
50V
2 C0G-CERM 402 2
TBTBST:Y NO STUFF
Vout = 15.47V
402 402 402 0402 0402 <Ra> 1 C3895 1 C3897 Max Current = 2A?
2 G S 1 5 G S 4 TBTBST_VC_RC FBX 31 TBTBST_FBX 10UF 10UF
TBTBST:Y TBTBST:Y
TBTBST:Y
34 SYNC
NO STUFF
TBTBST:Y 10%
2 25V
10%
2 25V
Freq = 300KHz
1 1 1 X5R X5R
R3892 1 C3893 R3894 1 C3894 1 C3889 R3896 1206-2 805
84 35 IN TBT_A_HV_EN 73.2K 0.0033UF 28.7K 0.33UF 100PF 15.8K TBTBST:Y
1% 1% SGND GND 1% TBTBST:Y
TBT_B_HV_EN 1/16W
MF-LF
10%
50V
2 X7R-CERM
1/16W
MF-LF
10%
6.3V
2 CERM-X5R
5%
2 50V
1/16W
MF-LF C3896 1 1 C3899
23
24
37
12
13
14
15
16
17
85 35 IN CERM 402 2 20%
2 402 402 2
4
0402 402 402 25V 0.001UF
<R2> GND_TBTBST_SGND <Rb> POLY-TANT 2
10%
50V
2 X7R-CERM
MIN_LINE_WIDTH=0.5 mm 0402
UVLO(falling) = 1.22 * (R1 + R2) / R2 MIN_NECK_WIDTH=0.25 mm CASE-D3L
VOLTAGE=0V
UVLO(rising) = UVLO(falling) + (2uA * R1) 33UF-0.06OHM
SGND shorted to
Vout = 1.6V * (1 + Ra / Rb) C
C UVLO = 4.55V (falling), 4.95 (rising)
GND inside package,
no XW necessary.
Supervisor & CLKREQ# Isolation
8 =PP3V3_S0_TBTPWRCTL
TBTBST:Y
C3800 1 =PP3V3_TBTLC_RTR
6 D
Q3888 TBTBST:Y
8 35 36 37
SSM6N37FEAPE 1
R3888
0.1UF SOT563
10%
16V 1
330K
2 CRITICAL R3807 5%
1
X5R-CERM
0201 1/16W
VDD 100K MF-LF
Q3840 1
R3840
U3800
5%
1/20W 1 S G 2 Max Vgs: 10V 2 402
G 1
SSM3K15FV 10K MF
5%
SLG4AP016V 2
201 TBTBST_SHDN_DIV
SOD-VESM-HF 1/20W
MF TDFN PP1V05_TBTLC 8 TBTBST:Y
2 201 1 TBTBST:Y
+ SENSE
2
R3887 3 D Q3888
D
35 IN TBT_EN_LC_PWR - 0.7V 330K SSM6N37FEAPE

3
5%
1/16W SOT563
MF-LF
Platform (PCIe) Reset DLY
2 402
RESET* 4 TBT_PCIE_RESET_L OUT 35
=TBT_RESET_L 3 MR* G 5
25 IN
DLY = 60 ms +/- 20% 4 S
SMC_DELAYED_PWRGD IN 41 42 70
6 EN
=TBT_CLKREQ_L IN 35
17 OUT TBT_CLKREQ_L 8 OUT
(OD) IN 7 TBT_CLKREQ_ISOL_L
MAKE_BASE=TRUE
Pull-ups provided by SB page. THRM
GND PAD
5
TBT "POC" Power-up Reset

B Intel investigating whether RC is sufficient. B
36 35 =PP3V3_S4_TBT
3.3V TBT "LC" Switch

CRITICAL
1
U3810 Pull-up: R3610
=PP3V3_S0_P3V3TBTFET TPS22924 =PP3V3_TBTLC_FET VDD =PP3V3_S0_PCH_GPIO
8 8 8 17 18 19 20 25
CSP
A2 A1 Max Current = 2A (85C) 2 SENSE
U3830 RESET* 6 TBT_PWR_ON_POC_RST_L OUT 35
VIN VOUT
R3811
B2 B1
TPS3808 R3830
1
36.5K2
CRITICAL U3810 TBTPOCRST_CT 3 CT QFN MR* 4 TBTPOCRST_MR_L Q3825 5%
100K
C3810 THRM
G 5
1 1 TBT_EN_LC_3V3 C2 ON GND SSM6N37FEAPE 1/20W
Part TPS22924C PAD MF
1UF
20%
1%
C3811 1
GND 1 C3831 C3830 1 SOT563 2 201
7
1/20W
0.0047UF 0.1UF TPS3808G25
C1
6.3V MF
X5R 2
1UF Type Load Switch 10% 10%
201
2 25V 25V 2 TBT_SW_RESET_L
S
0201 10% Vt = 2.33V +/- 2%
6.3V
R(on) 18.3 mOhm Typ CERM X5R IN 20
CERM 2 0402 402
4
402 Delay = 27.3ms
@ 2.5V 24 mOhm Max
TBT_EN_LC_ISOL
1 C3825
330PF
10%
16V
R38161 2 X7R-CERM
5%
1/20W
0
1.05V TBT "CIO" Switch 0201
MF 99 37 8 =PP1V05_S0_P1V05TBTFET
201 2
=PP3V3_TBTLC_RTR
TBT_EN_LC_1V05
1.05V TBT "LC" Switch
37 36 35 8
U3820
TPS22920 =PP1V05_TBTCIO_FET 8
99 37 8 =PP1V05_S0_P1V05TBTFET U3815
1
R3820 A2
CSP
A1 Max Current = 4A (85C)
TPS22924 =PP1V05_TBTLC_FET 8 100K B2 B1
5% VIN VOUT
A2
CSP
A1 Max Current = 2A (85C)
1/20W
MF C2 C1 U3820
A B2 VIN
CRITICAL
VOUT B1
U3815
2 201
TBT_EN_CIO_PWR D2 ON
CRITICAL
Part TPS22920 SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012 A
PAGE TITLE
C3815 1 C2 ON GND Type Load Switch
1UF GND Part TPS22924C 1 C3820
Thunderbolt Power Support
D1
20%
Type Load Switch
Q3825 D 6
1UF R(on) 8 mOhm Typ DRAWING NUMBER SIZE
C1
6.3V
X5R
0201
2
SSM6N37FEAPE
SOT563
20%
6.3V
2 X5R
@ 1.05V 11.5 mOhm Max
R(on) 20.3 mOhm Typ 0201 REVISION
NOSTUFF @ 1.0V 28.6 mOhm Max
R
4.18.0
C3816 1 2 G S 1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1UF THE INFORMATION CONTAINED HEREIN IS THE
10% PROPRIETARY PROPERTY OF APPLE INC.
6.3V
CERM 2 C3816 must be 10% THE POSESSOR AGREES TO THE FOLLOWING: PAGE
402 RC guarantees minimum 5ms to reach 0.5V
35 TBT_EN_CIO_PWR_L
38 OF 132
IN
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
J4400
20525-130E-01
F-RT-SM
SIGNAL_MODEL=EMPTY 31
TP 1
BP4405 BEAD-PROBE SM
TP 1 91 26 7 BI USB_EXTB_P
BP4406 BEAD-PROBE SM 2
91 26 7 BI USB_EXTB_N
SIGNAL_MODEL=EMPTY GND_VOID=TRUE GND_VOID=TRUE 3
TP 1 C4401 0.1UF
BP4401 BEAD-PROBE SM 91 19 IN USB3_EXTB_TX_P 1 2 97 7 USB3_EXTB_TX_C_P GND_VOID=TRUE 4
TP 1 C4402 0.1UF
BP4402 BEAD-PROBE SM 91 19 IN USB3_EXTB_TX_N 1 2 X5R-CERM 0201 10% 16V 97 7 USB3_EXTB_TX_C_N GND_VOID=TRUE 5
SIGNAL_MODEL=EMPTY X5R-CERM 0201 10% 16V 6

12 R4403 7
91 19 7 OUT USB3_EXTB_RX_P 1 2 97 USB3_EXTB_RX_RC_P GND_VOID=TRUE
516S0853 91 19 7 USB3_EXTB_RX_N 1/20W 1% MF 201 97 USB3_EXTB_RX_RC_N GND_VOID=TRUE 8
OUT
GND_VOID=TRUE 9
15PF 1 2 C4403 HDMI_EG_DATA_C_P<0> 10
GND_VOID=TRUE
J4410 5% 25V NP0-CERM 0201 SIGNAL_MODEL=EMPTY
95 77 7 IN
HDMI_EG_DATA_C_N<0> GND_VOID=TRUE 11
AXK732327G GND_VOID=TRUE
95 77 7 IN
TP 1
F-ST-SM BP4403 BEAD-PROBE SM 12
33 12 TP 1
R4404 BP4404 BEAD-PROBE SM 95 77 7 IN HDMI_EG_DATA_C_P<1> GND_VOID=TRUE 13
1 2
C 25 =ENET_RESET_L 1 2 PM_SLP_S3_L 7 18 27 41 70
1/20W 1%
GND_VOID=TRUE
MF 201
SIGNAL_MODEL=EMPTY 95 77 7 IN HDMI_EG_DATA_C_N<1> GND_VOID=TRUE 14
15 C
IN IN
ENET_CLKREQ_L 3 4 PM_SLP_S4_L 15PF 1 2 C4404 95 77 7 IN HDMI_EG_DATA_C_P<2> GND_VOID=TRUE 16
17 7 OUT IN 7 18 27 34 40 41 70
95 77 7 HDMI_EG_DATA_C_N<2> GND_VOID=TRUE 17
SD_PWR_EN 5 6 HDMI_EG_DDC_CLK 5% 25V NP0-CERM 0201 IN
9 7 IN IN 7 77
GND_VOID=TRUE 18
25 7 OUT SDCONN_STATE_CHANGE_RIO 7 8 HDMI_EG_DDC_DATA BI 7 77
19
95 77 7 IN HDMI_EG_CLK_C_P
24 7 OUT USB_EXTB_OC_L 9 10 HDMI_HPD_L OUT 7 42 82
20
95 77 7 IN HDMI_EG_CLK_C_N
8 =PP1V5_S0_RIO 11 12
21
8 =PP3V3_S3_RIO 13 14
22
15 16 92 17 7 IN PCIE_CLK100M_ENET_P
92 17 7 PCIE_CLK100M_ENET_N 23
17 18 IN
24
8 =PP3V3_S4_RIO 19 20
25
92 17 7 OUT PCIE_ENET_D2R_P GND_VOID=TRUE
44 =I2C_HDMIRDRV_SCL 21 22
26
92 17 7 OUT PCIE_ENET_D2R_N GND_VOID=TRUE
44 =I2C_HDMIRDRV_SDA 23 24
27
25 26
92 17 7 PCIE_ENET_R2D_C_P GND_VOID=TRUE 28
27 28 IN
92 17 7 PCIE_ENET_R2D_C_N GND_VOID=TRUE 29
=PP5V_S4_RIO 29 30 IN
8
30
31 32
33
34 34
35
36
37
38
39
40
41
B B
32
518S0829
PAGE TITLE
RIO CONNECTOR
DRAWING NUMBER SIZE

REVISION
R
4.18.0
44 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
CRITICAL
PLACE_NEAR=J4501.9:3mm R4599
CRITICAL 0.005
1%
1W
L4500 MF
0612
FERR-26-OHM-6A PP3V3_S0_SSD_R 2 1 =PP3V3_S0_SSD 8
MIN_LINE_WIDTH=0.6mm
PP3V3_S0_SSD_FLT MIN_NECK_WIDTH=0.25mm 4 3
MIN_LINE_WIDTH=0.6mm VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25mm 0603
VOLTAGE=3.3V ISNS_SSD_P OUT 97 99
1
C4501 1
C4502 ISNS_SSD_N OUT 97 99
0.1UF 0.1UF
20% 20%
10V 10V
2 CERM 2 CERM
402 402
8 =PP3V3_S0_SATAMUX
1
C4505 1
C4514 1
C4519
514S0393
C CRITICAL 2
0.1UF
20%
10V
CERM 2
0.1UF
20%
10V
CERM 2
0.01UF
20%
16V
X7R-CERM
C
402 402 0402
J4501 Per PCIe spec, only TX side should have AC cap
SSD-J5
F-RT-SM R4505
1 PLACE_NEAR=U4510.10:2 mm
PLACE_NEAR=U4510.6:2 mm
GND_VOID=TRUE 100K
1 GND_VOID=TRUE 5%
GND_VOID=TRUE 1/16W
2 GND_VOID=TRUE MF-LF GND_VOID=TRUE
2 402 GND_VOID=TRUE
GND_VOID=TRUE
3
R4526
10
GND_VOID=TRUE
1 2 0
6
92 PCIE_SSD_D2R_C_P<1> PCIE_SSD_D2R_P<1> 9 92
4 GND_VOID=TRUE 5% 1/20W MF 201 OUT
SIGNAL_MODEL=EMPTY
R4525 R4518 1 1 TP
VDD
VDD
VDD
5 GND_VOID=TRUE 92 PCIE_SSD_D2R_C_N<1> 1 2 0 PCIE_SSD_D2R_N<1> 9 92 92 PCIE_SSD_D2R_MUX_OUT_P 2 0 PCIE_SSD_D2R_P<0> 9 92 SM BEAD-PROBE BP4501
5% 1/20W MF 201 OUT 5% 1/20W MF 201 OUT
6
7 GND_VOID=TRUE 91 SATA_SSD_D2R_P U4510 92 PCIE_SSD_D2R_MUX_OUT_N R4517 1 2 0
1 TP
SIGNAL_MODEL=EMPTY
SM BEAD-PROBE BP4502
8 GND_VOID=TRUE 91 SATA_SSD_D2R_N CBTL02043ABQ 5% 1/20W MF 201
PCIE_SSD_D2R_N<0>
OUT 9 92
9 3 VQFN B0_P 19
C4521 0.1UF 1 2
A0_P
0.1UF
10 GND_VOID=TRUE 92 PCIE_SSD_R2D_P<1> PCIE_SSD_R2D_C_P<1>
IN 9 92
4 A0_N B0_N 18 92 PCIE_SSD_R2D_MUX_IN_P C4513 1 2 PCIE_SSD_R2D_C_P<0>
IN 9 92
X5R-CERM 10% 16V 0201
11 GND_VOID=TRUE 92 PCIE_SSD_R2D_N<1> C4520 0.1UF 1 2 PCIE_SSD_R2D_C_N<1> 9 92
10% 16V 0201
IN 7
12 X5R-CERM 10% 16V 0201
A1_P B1_P 17 X5R-CERM
8 CRITICAL C4512 0.1UF

13 GND_VOID=TRUE A1_N B1_N 16 92 PCIE_SSD_R2D_MUX_IN_N 1 2 PCIE_SSD_R2D_C_N<0>
IN 9 92
91 SATA_SSD_R2D_P
10% 16V 0201
14 GND_VOID=TRUE 91 SATA_SSD_R2D_N C0_P 15 X5R-CERM
15 9 SEL C0_N 14 GND_VOID=TRUE
GND_VOID=TRUE
16 PCIE_CLK100M_SSD_P GND_VOID=TRUE
IN 17 92 SATAMUX_EN_L
2 XSD C1_P 13 GND_VOID=TRUE
17 PCIE_CLK100M_SSD_N SIGNAL_MODEL=EMPTY
IN 17 92
18 C1_N 12 C4516 0.01UF 1 2 1 TP
SM BEAD-PROBE
91 SATA_SSD_D2R_MUX_OUT_P SATA_HDD_D2R_P
OUT 17 91 BP4503
THRM
PAD
VSS
VSS
VSS
10% 25V X7R 402
19
R4510
1
C4515 0.01UF
SSD_CLKREQ_L IN 17 10K 91 SATA_SSD_D2R_MUX_OUT_N 1 2 SATA_HDD_D2R_N
OUT 17 91
5
11
20
21
20 5% 10% 25V X7R 402
SSD_RESET_L
B 21
22
SATA_PCIE_SEL
IN 25 1/20W
MF
2 201
C4511 0.01UF 1 2
B
SMC_OOB1_RX_L OUT 91 SATA_SSD_R2D_MUX_IN_P SATA_HDD_R2D_C_P
IN 17 91
23 SMC_OOB1_TX_L IN
R4520 10% 25V X7R 402
24 SSD_P3V3S0_EN 1
0 2 =P3V3S0_EN IN 69 70
C4510 0.01UF 1 2
91 SATA_SSD_R2D_MUX_IN_N SATA_HDD_R2D_C_N 17 91
25 5% IN
1/20W 10% 25V X7R 402
26 MF
201
27
28
29 353S3361
30
31
32
33
34
35
PCIE/SATA GUMSTICK2 CONNECTOR

PAGE TITLE
SSD CONNECTOR
DRAWING NUMBER SIZE

REVISION
R
4.18.0
45 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
USB Port Power Switch
Left USB Port A
8 =PP5V_S3_LTUSB
CRITICAL
PM_SLP_S4_L CRITICAL
70 41 38 34 27 18 7
U4600 L4605
TPS2557DRB We can add protection to 5V if we want, but leaving NC for now
1 FERR-120-OHM-3A
R4690 SON
Place L4605 and L4615 at connector pin
5.1K 2 IN_0 OUT1 6 PP5V_S3_LTUSB_A_ILIM 1 2 PP5V_S3_LTUSB_A_F
5% MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
1/16W 3 IN_1 OUT2 7 MIN_NECK_WIDTH=0.25 mm 0603 MIN_NECK_WIDTH=0.25 mm
MF-LF VOLTAGE=5V VOLTAGE=5V
402
8 FAULT* C4605 1
2
24 OUT USB_EXTA_OC_L ILIM 5 USB_ILIM 0.01UF 514-0804
20% CRITICAL CRITICAL
4 EN
USB_PWR_EN R46011 16V
X7R-CERM 2
L4600 J4600
THRM 22.1K 0402 90-OHM-50MA
USB3.0-J5
1% TCM0605-1
GND PAD 1/20W SYM_VER-1
F-RT-TH
MF 1 4
USB_EXTA_MUXED_N
9
201 2 91
1
CRITICAL C4695 1
VBUS
C4690 1 1 C4691 USB_ILIM_R 10UF 2
C4692 1
C4696 1
10UF 0.1UF 20%
91 USB_LT1_N D-
0.47UF 3
10%
220UF-35MOHM
20%
20%
6.3V
2 2
20%
10V R46001 6.3V
X5R 2 91 USB_EXTA_MUXED_P 2 3 91 USB_LT1_P
4
D+
10V
X5R 2 6.3V
POLY-TANT
2
X5R
603
CERM
402 22.1K 603
GND
0402 1% 5
CASE-B2-SM1 1/16W 97 USB3_EXTA_RX_RC_N
MF-LF 2 5 3 4 STDA_SSRX-
402 2 97 USB3_EXTA_RX_RC_P 6
NC
IO
NC
IO
STDA_SSRX+
6 VBUS 7
GND_DRAIN
97 USB3_EXTA_TX_C_N 8
1 GND STDA_SSTX-
CURRENT LIMIT (R4600+R4601): 2.19A MIN / 2.76A MAX 97 USB3_EXTA_TX_C_P 9
C 10
11
STDA_SSTX+
SHLD C
D4600 SHLD
USB/SMC Debug Mux RCLAMP0502N
SLP1210N6
12
13
SHLD
SHLD
CRITICAL
14
15
8 =PP3V42_G3H_SMCUSBMUX 16
SMC_DEBUG_YES 17
1 SIGNAL_MODEL=EMPTY
SMC_DEBUG_YES R4650 18
C4650 1 10K SIGNAL_MODEL=EMPTY BEAD-PROBE
BP4604
9
5%
0.1UF
20%
1/16W BEAD-PROBE
VCC MF-LF SM
10V
CERM 2 2 402 BP4602
42 41 IN SMC_DEBUGPRT_RX_L 402 5
M+ Y+ 1 12 1 2 R4613 SM
SMC_DEBUGPRT_TX_L 4 M- Y- 2
42 41 OUT U4650 1/20W 1% MF 201
PI3USB102ZLE GND_VOID=TRUE
1
91 19 BI USB_EXTA_P 7
D+ TQFN
NO_TEST=TRUE 15PF 1 2 C4613
CRITICAL
1
91 19 BI USB_EXTA_N 6
D- 91 19 OUT USB3_EXTA_RX_N
5% 25V NP0-CERM 0201 NO_TEST=TRUE
SMC_DEBUG_YES GND_VOID=TRUE
8 OE* SEL 10 SMC_DEBUGPRT_EN_L IN 41
91 19 OUT USB3_EXTA_RX_P 12 1 2 R4612 NO_TEST=TRUE
GND SEL=0 Choose SMC
NO_TEST=TRUE
SEL=1 Choose USB 1/20W 1% MF 201
3
GND_VOID=TRUE
CRITICAL CRITICAL
15PF 2 2
1 2 C4612 D4610 D4611
5% 25V NP0-CERM 0201 ESD0P2RF-02LS ESD0P2RF-02LS
SMC_DEBUG_NO GND_VOID=TRUE TSSLP-2-1 TSSLP-2-1
R4651
B 1
0 2
1 1
B
5% SMC_DEBUG_NO
1/20W
MF
201 R4652
1
0 2
5%
1/20W
MF
201
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
BEAD-PROBE BEAD-PROBE
BP4606 BP4605
SM SM
GND_VOID=TRUE
NO_TEST=TRUE
C4610 0.1UF NO_TEST=TRUE
USB3_EXTA_TX_N 1 2
1
1
91 19 IN
10% 16V 0201
X5R-CERM
C4611 0.1UF
91 19 IN USB3_EXTA_TX_P 1 2
1
1
10% 16V 0201
NO_TEST=TRUE X5R-CERM NO_TEST=TRUE
GND_VOID=TRUE CRITICAL 2 2
CRITICAL
SM SM
D4612 D4613
ESD0P2RF-02LS ESD0P2RF-02LS
BP4608 BP4607 TSSLP-2-1 TSSLP-2-1
BEAD-PROBE BEAD-PROBE
1 1
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
PAGE TITLE
USB 3.0 CONNECTORS

DRAWING NUMBER SIZE

REVISION
R
4.18.0
46 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
L4901
78 42 8 =PP3V3_S5_SMC 30-OHM-1.7A
1 2 PP3V3_S5_SMC_VDDA
0402 MIN_NECK_WIDTH=0.1 MM
1 C4901
C4902 1 1 C4903 1 C4904 1 C4905 1 C4906
VOLTAGE=3.3V
0.1UF
1UF 0.1UF 0.1UF 0.1UF 0.1UF 1
R4902 20%
20%
10V
20%
10V
20%
10V
20%
10V
20%
10V 1M U4900 10V
2 CERM
D
D X5R-CERM 2
0603-1
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402 5%
1/20W
MF
LM4FSXAH5BB
BGA
402
201
2 (2 OF 2)
61 43 42 7 SMC_RESET_L G10 RST* SWCLK/TCK C10 SMC_TCK 7 42 43
IN
OMIT_TABLE A10
SWDIO/TMS SMC_TMS 7 42 43
1 C4907 1 C4908 1 C4909
42 34 7 WIFI_EVENT_L (OD) B11 PK4/RTCCLK SWO/TDO A11 SMC_TDO 7 42 43
0.1UF 0.1UF 0.1UF BI
U4900 2
20%
10V
2
20%
10V
2
20%
10V
SMC_WAKE_L N13 WAKE* TDI B10 SMC_TDI 7 42 43
LM4FSXAH5BB CERM
402
CERM
402
CERM
402 7 NC_SMC_HIB_L M12 HIB*
BGA NC A2
92 82 43 17 7 LPC_AD<0> B13 LPC0AD0 (1 OF 2) AIN00 E2 SMC_ADC0 42
NC
BI IN
42 SMC_CLK32K M10 XOSC0
LPC_AD<1> A13 E1 SMC_ADC1 IN
92 82 43 17 7 BI LPC0AD1 AIN01 IN 42
N10
7 NC_SMC_XOSC1 XOSC1
92 82 43 17 7 BI LPC_AD<2> C12 LPC0AD2 OMIT_TABLE AIN02 F2 SMC_ADC2 IN 42
VDDA D3
92 82 43 17 7 BI LPC_AD<3> D11 LPC0AD3 AIN03 F1 SMC_ADC3 IN 42
42 SMC_EXTAL G12 OSC0
LPC_CLK33M_SMC H12 LPC0CLK AIN04 B3 SMC_ADC4
92 25 IN IN 42
42 SMC_XTAL G13 OSC1 VREFA+ D2 PP3V3_S5_AVREF_SMC 7 42
92 82 43 17 7 IN LPC_FRAME_L D12 LPC0FRAME* AIN05 A3 SMC_ADC5 IN 42
VREFA- D1
25 IN SMC_LRESET_L C13 LPC0RESET* AIN06 B4 SMC_ADC6 IN 42
K12 VBAT
XW4900
SM
43 17 7 BI LPC_SERIRQ (OD) H13 LPC0SERIRQ AIN07 A4 SMC_ADC7 IN 42
99 46 45 42 C3 GND_SMC_AVSS 2 1
43 18 7 PM_CLKRUN_L (OD) G11 LPC0CLKRUN* AIN08 B5 SMC_ADC8 42
OUT IN D7 GNDA E3
43 25 18 7 LPC_PWRDWN_L F13 LPC0PD* AIN09 A5 SMC_ADC9 42 PLACE_NEAR=U4900.A1:4MM
IN IN E6
20 SMC_RUNTIME_SCI_L F12 LPC0SCI* AIN10 B6 SMC_ADC10 42
OUT IN E8 A1
20 SMC_WAKE_SCI_L B12 PK5 AIN11 A6 SMC_ADC11 42
OUT IN E9 C7
AIN12 C1 SMC_ADC12 IN 42 F10 VDD D9
94 44 SMBUS_SMC_0_S0_SCL (OD) E10 I2C0SCL AIN13 C2 SMC_ADC13 42
BI IN J7 E5
94 44 BI SMBUS_SMC_0_S0_SDA (OD) D13 I2C0SDA AIN14 B1 SMC_ADC14 IN 42 J9 F9
1 C4920 1 C4921
SMBUS_SMC_1_S0_SCL (OD) M4 I2C1SCL AIN15 B2 SMC_ADC15 J10
0.01UF 1UF
94 44 BI IN 42 H5 10% 10%
94 44 SMBUS_SMC_1_S0_SDA (OD) N2 I2C1SDA AIN16 G2 SMC_ADC16 42 2 10V 6.3V
2 CERM
BI IN H9 X5R-CERM
94 44 7 SMBUS_SMC_2_S3_SCL (OD) N8 I2C2SCL AIN17 G1 SMC_ADC17 42
GND 0201 402
J1 J5
C
BI IN
C 94 44 7
94 44
BI SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
(OD)
(OD)
M8
L8
I2C2SDA
I2C3SCL
AIN18
AIN19
H1
H2
SMC_ADC18
SMC_ADC19
IN 42
42 NO STUFF
42 PP1V2_S5_SMC_VDDC
VOLTAGE=1.2V
J6 J8
BI IN 1 C4910 1 C4911 1 C4912 1 C4913 1 C4914 1 C4915 1 C4916 1 C4917 K13 VDDC J11
94 44 BI SMBUS_SMC_3_SDA (OD) K8 I2C3SDA AIN20 B7 SMC_ADC20 IN 42
1UF 1UF 1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF D6 K11
42 BI SMBUS_SMC_4_ASF_SCL (OD) N7 I2C4SCL AIN21 A7 SMC_ADC21 IN 42
10% 10% 10% 20% 20% 20% 20% 20%
25V 25V 25V 10V 10V 10V 10V 10V
M7 B8 2 X5R 2 X5R 2 X5R 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
42 BI SMBUS_SMC_4_ASF_SDA (OD) I2C4SDA AIN22 SMC_ADC22 IN 42 402 402 402 402 402 402 402 402
44 7 SMBUS_SMC_5_G3_SCL (OD) N4 I2C5SCL AIN23 A8 SMC_ADC23 42
BI IN
44 7 SMBUS_SMC_5_G3_SDA (OD) N3 I2C5SDA
BI
C0- K2 CPU_PROCHOT_L 11 42 65 89
IN
48 OUT SMC_FAN_0_CTL H11 PM6/FAN0PWM0 C0+ K1 SMC_VCCIO_CPU_DIV2 42
48 IN SMC_FAN_0_TACH L13 PM7/FAN0TACH0 C1- L2 SMC_S5_PWRGD_VIN 42
48 OUT SMC_FAN_1_CTL C11 PK6/FAN0PWM1 PC5/C1+ L1 SPI_DESCRIPTOR_OVERRIDE_L OUT 25 42
48 SMC_FAN_1_TACH A12 PK7/FAN0TACH1 T3CCP1/PJ5/C2- C5 CPU_CATERR_L 11 89

IN IN
TP_SMC_MPM5_LED_PWR G3 PN2/FAN0PWM2 T3CCP0/PJ4/C2+ D5 CPU_THRMTRIP_3V3 42
IN
TP_SMC_MPM5_LED_CHG D10 PN3/FAN0TACH2
SSI0CLK/PA2 M2 SMC_PM_G2_EN 42 70
OUT
50 OUT SMC_SYS_KBDLED L11 PN4/FAN0PWM3 SSI0FSS/PA3 M3 PM_DSW_PWRGD OUT 18
8 SMC_T25_EN_L N12 PN5/FAN0TACH3 SSI0RX/PA4 L4 SMC_DELAYED_PWRGD 37 42 70

OUT OUT
60 SYS_TDM_ONEWIRE N11 PN6/FAN0PWM4 SSI0TX/PA5 N1 SMC_PROCHOT 42
BI OUT
60 SYS_ONEWIRE M11 PN7/FAN0TACH4
BI
42 IN HISIDE_ISENSE_OC J4 PH2/FAN0PWM5 U1RX/B0 F11 SMC_DEBUGPRT_RX_L IN 40 42
42 IN SMC_ODD_DETECT J2 PH3/FAN0TACH5 U1TX/PB1 E11 SMC_DEBUGPRT_TX_L OUT 40 42
T0CCP0/PB6 F4 SMC_SYS_LED 42
OUT
42 BI CPU_PECI_R C4 PECI0RX T0CCP1/PB7 F3 (OD) SMC_GFX_THROTTLE_L BI 78
42 OUT SMC_PECI_L C6 PECI0TX

SSI1RX/PF0 M9 SPI_SMC_MISO IN 42
42 IN SMC_BIL_BUTTON_L M13 PP0/IRQ116 SSI1TX/PF1 N9 SPI_SMC_MOSI OUT 42
B 42
42
IN
IN
SMC_DP_HPD_L
SMC_PME_S4_WAKE_L
L12
M5
PP1/IRQ117
PP2/IRQ118
SSI1CLK/PF2
SSI1FSS/PF3
L10
K10
SPI_SMC_CLK
SPI_SMC_CS_L
OUT
OUT
42
42
B
42 SMC_PME_S4_DARK_L J12 PP3/IRQ119 PF4 L9 S5_PWRGD 70
IN IN
70 42 OUT SMC_S4_WAKESRC_EN J13 PP4/IRQ120 PF5 K9 PM_PCH_SYS_PWROK IN 18 24 70
L5 PP5/IRQ121
NC
NC D8 PP6/IRQ122 WT0CCP0/PG4 K7 SMC_DEBUGPRT_EN_L OUT 40
49 42 IN SMC_LID K6 PP7/IRQ123 WT0CCP1/PG5 L7 SMC_GFX_OVERTEMP IN 42 78
42 OUT ENET_ASF_GPIO D4 PQ0/IRQ124 WT2CCP0/PH0 K3 ALL_SYS_PWRGD IN 24 70
51 42 IN SMS_INT_L E4 PQ1/IRQ125 WT2CCP1/PH1 K4 SMC_THRMTRIP OUT 42
60 42 SMC_BC_ACOK F5 PQ2/IRQ126
IN
42 G3_POWERON_L N5 PQ3/IRQ127 WT3CCP0/PH4 J3 PM_PWRBTN_L 18 24
IN OUT
70 38 27 18 7 PM_SLP_S3_L N6 PQ4/IRQ128 WT3CCP1/PH5 H4 (OD) PM_SYSRST_L 18 25
IN OUT
70 40 38 34 27 18 7 PM_SLP_S4_L K5 PQ5/IRQ129 WT4CCP0/PH6 H3 (OD) MEM_EVENT_L 42
IN BI
70 18 PM_SLP_S5_L M6 PQ6/IRQ130 WT4CCP1/PH7 G4 SMC_ADAPTER_EN 18 42 70
IN OUT
49 42 SMC_ONOFF_L L6 PQ7/IRQ131
IN
T1CCP0/PJ0 C9 SMC_OOB1_RX_L IN 39
43 42 7 SMC_RX_L L3 U0RX T1CCP1/PJ1 B9 SMC_OOB1_TX_L 39 42

IN OUT
43 42 7 SMC_TX_L M1 U0TX T2CCP0/PJ2 A9 IR_RX_OUT_RC 42
OUT IN
T2CCP1/PJ3 C8 BDV_BKL_PWM OUT 42
91 9 BI USB_SMC_N E13 USB0DM

91 9 BI USB_SMC_P E12 USB0DP WT5CCP1/PM3 H10 SMC_BATLOW_L OUT 42 70
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
A If SMS interrupt is not used, pull up to SMC rail.

PAGE TITLE
SMC
DRAWING NUMBER SIZE

REVISION
R
4.18.0
49 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SMC Reset "Button", Supervisor & AVREF Supply 41 ENET_ASF_GPIO NC_ENET_ASF_GPIO
SMC12 PECI SUPPORT

MAKE_BASE=TRUE
R5027 41 SMC_SYS_LED NC_SMC_SYS_LED

MAKE_BASE=TRUE
7
=PP3V3_S5_SMC 1
47 2 PP3V42_G3H_SMC_SPVSR MEM_EVENT_L NC_MEM_EVENT_L
41 8 41
78 42 MIN_LINE_WIDTH=0.4 mm MAKE_BASE=TRUE
5%
1/16W 1 C5027 MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.42V 41 SMC_ODD_DETECT NC_SMC_ODD_DETECT 7 =PPVCCIO_S0_SMC 8 42
MF-LF
402 4.7UF R50001 MAKE_BASE=TRUE
CRITICAL
20% 100K 61 45 =CHGR_ACOK SMC_BC_ACOK 41 42 60 41 IR_RX_OUT_RC NC_IR_RX_OUT_RC
2 6.3V
X5R 5% MAKE_BASE=TRUE MAKE_BASE=TRUE
Q5030
402 1/16W
MF-LF 41 HISIDE_ISENSE_OC NC_HISIDE_ISENSE_OC SSM3K15AMFVAPE D 3
8 =PPVIN_S5_SMCVREF 402 2 MAKE_BASE=TRUE
VESM
41 SMC_ADC0 SMC_CPU_VSENSE 45
MAKE_BASE=TRUE
Mac Mini: 5V
C5020 1
3
SMC_ADC1 SMC_CPU_ISENSE
D Mobiles: 3.42V 0.47UF

10%
6.3V
V+
U5010
VIN R5028
0
41
41 SMC_ADC2
MAKE_BASE=TRUE
SMC_GPU_HI_ISENSE
46
46 1 G S 2
D
CERM-X5R 2
SMC_RESET_R_L 1 2 SMC_RESET_L
OUT 7 41 43 61 MAKE_BASE=TRUE
R5032
402 VREF-3.3V-VDET-3.0V
5% 41 SMC_ADC3 SMC_DCIN_VSENSE 45 0
6
DFN
5
1/20W MAKE_BASE=TRUE 41 IN SMC_PECI_L 1 2 SMC_PECI_L_R
49 IN SMC_TPAD_RST_L MR1* SN0903048
(IPU) RESET* MF
201 41 SMC_ADC4 SMC_DCIN_ISENSE 46 5%
49 42 41 IN SMC_ONOFF_L 7
MR2* (IPU) MAKE_BASE=TRUE From SMC 1/16W OMIT
PP3V3_S5_AVREF_SMC 7 41 89 65 41 11 BI CPU_PROCHOT_L MF-LF
1 1
MIN_LINE_WIDTH=0.4 mm 41 SMC_ADC5 SMC_PBUS_VSENSE 45 402
R5033 R5031
SMC_MANUAL_RST_L 4 DELAY CRITICAL REFOUT 8 MIN_NECK_WIDTH=0.1 mm MAKE_BASE=TRUE
VOLTAGE=3.3V NOSTUFF 330
OMIT THRM 41 SMC_ADC6 SMC_SSD_ISENSE 99 NONE 5%
GND PAD NOSTUFF MAKE_BASE=TRUE NONE 1/16W
1
R5001 C5001 1 C5028 1 SMC_ADC7 SMC_CHGR_BMON_ISENSE 6 D Q5059
NONE MF-LF
9
402
0 C5025 1 1
C5026
41 46
2 2 402
5% 0.01UF 1000PF MAKE_BASE=TRUE
SSM6N15FEAPE
1/10W
10% 10uF 0.01UF 5% 41 SMC_ADC8 SMC_CPU_HI_ISENSE 46 SOT563
16V 20% 10% 25V
MF-LF
603
X7R-CERM 2 6.3V
2 2
16V NP0-C0G 2 MAKE_BASE=TRUE
2 0402 X5R X7R-CERM 402 SMC_ADC9 SMC_OTHER_HI_ISENSE
603 0402 41 46
SILK_PART=SMC_RST MAKE_BASE=TRUE
S G 2
R5034
GND_SMC_AVSS
41 SMC_ADC10 SMC_P1V5MEM_ISENSE 45 1
CPU_PECI_R 1
43 2 CPU_PECI
PLACEMENT_NOTE=Place R5001 on BOTTOM side 41 45 46 99 MAKE_BASE=TRUE 41 OUT BI 11 20 89
MIN_LINE_WIDTH=0.4 mm ADC10 AND ADC11 ARE SHARED WITH COMPARATORS ON STACK BOARD SMC_PROCHOT IN 41
MIN_NECK_WIDTH=0.1 mm 41 SMC_ADC11 SMC_CPUVCCIO_ISENSE 45 5% From/To CPU/PCH
MR1* and MR2* must both be low to cause manual reset. VOLTAGE=0V MAKE_BASE=TRUE To SMC 1/16W
MF-LF
Used on mobiles to support SMC reset via keyboard. 41 SMC_ADC12 SMC_GFX_VSENSE 45 402
MAKE_BASE=TRUE 20 OUT PM_THRMTRIP_L_R
NOTE: Internal pull-ups are to VIN, not V+. 41 SMC_ADC13 SMC_CPU_SA_ISENSE 45
MAKE_BASE=TRUE
41 PP1V2_S5_SMC_VDDC 41 SMC_ADC14 SMC_GPU_CORE_VSENSE 45

3 D Q5059
MAKE_BASE=TRUE
SSM6N15FEAPE
1SMC_PACKAGE:ENG 41 SMC_ADC15 SMC_GPU_CORE_ISENSE 45 SOT563
R5099 MAKE_BASE=TRUE
Debug Power "Buttons"

0
5%
1/16W
41 SMC_ADC16
SMC_ADC17
SMC_LCDBKLT_VSENSE
MAKE_BASE=TRUE
SMC_LCDBKLT_ISENSE
99
4
S G 5
SMC12 SPI SUPPORT
MF-LF 41 99
2 402 MAKE_BASE=TRUE
SMC_ONOFF_L OUT 41 42 49 41 SMC_ADC18 SMC_CPU_GFX_ISENSE 46 SMC_THRMTRIP IN 41 42
OMIT OMIT
42 41 SMC_ADC23 MAKE_BASE=TRUE
R5021
C PLACE_SIDE=TOP
R5016
0
1 1
R5015
0 PLACE_SIDE=BOTTOM
41 SMC_ADC19
SMC_ADC20
SMC_GPU_P1V35_ISENSE
MAKE_BASE=TRUE
SMC_CPU_SA_VSENSE
99
41 OUT SPI_SMC_MISO 1
12
5%
2 SPI_MLB_MISO IN 43 52 C
41 99 3 D Q5057
5%
1/10W
5%
1/10W ENG PACKAGE REQUIRES 1.2V ON SMC_ADC23 PIN MAKE_BASE=TRUE
SSM6N15FEAPE
R5022 1/16W
MF-LF
MF-LF MF-LF 41 SMC_ADC21 SMC_PCH_CORE_ISENSE 99 33 402
603
2 2
603 MAKE_BASE=TRUE SOT563 41 IN SPI_SMC_MOSI 1 2 SPI_MLB_MOSI OUT 43 52
SMC_PACKAGE:PROD PLACE_NEAR=U6100.5:1MM
SILK_PART=PWR_BTN SILK_PART=PWR_BTN 41 SMC_ADC22 SMC_X29_ISENSE
MAKE_BASE=TRUE
99
R5013 5%
1/16W R5023
42 8 =PPVCCIO_S0_SMC 0 MF-LF 33
42 41 SMC_ADC23 SMC_TBT_ISENSE_R 1 2 SMC_TBT_ISENSE IN 99 S G 5 41 IN SPI_SMC_CLK 402 1 2 SPI_MLB_CLK OUT 43 52
MAKE_BASE=TRUE 4 PLACE_NEAR=U6100.6:1MM
5% 5%
1
R5097 41 SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SCL
MAKE_BASE=TRUE
7 1/16W
MF-LF SMC_GFX_OVERTEMP IN 41 78
R5024 1/16W
MF-LF
100K 402 33 402
SMC Crystal Circuit 1%
1/20W
41 SMBUS_SMC_4_ASF_SDA NC_SMBUS_SMC_4_ASF_SDA
MAKE_BASE=TRUE
7 41 IN SPI_SMC_CS_L 1 2
PLACE_NEAR=U6100.1:1MM
SPI_MLB_CS_L OUT 43 52
MF 5%
2 201 41 BDV_BKL_PWM NC_BDV_BKL_PWM 1/16W
MAKE_BASE=TRUE MF-LF
R5010 41 SMC_VCCIO_CPU_DIV2 42 41 SMC_PME_S4_DARK_L SDCONN_STATE_CHANGE_SMC 25
402
2.49K2 MAKE_BASE=TRUE
41 SMC_XTAL 1 SMC_XTAL_R 78 42 41 8 =PP3V3_S5_SMC
=TBT_WAKE_L 18 35
1% CRITICAL 1 =PP3V3_S4_SMC
1/20W R5096 42 25 8
MF
201 Y5010
3.2X2.5MM-SM-1
100K
1%
R5068 100K
NO STUFF
SMC_OOB1_TX_L 1 2
12.000MHZ-30PPM-10PF
1/20W
R5012 41 39
MF
2 201 22 42 41 SMC_PME_S4_DARK_L R5069 100K 1 2
5% 1/20W MF 201
SMC_EXTAL 1 3 PM_CLK32K_SUSCLK_R 1 2 SMC_CLK32K 5% 1/20W MF 201
41 18 IN
PLACE_NEAR=U1800.N14:5.1mm
OUT 41
49 42 41 SMC_ONOFF_L R5070 10K 1 2
5% 5% 1/20W MF 201
2 4 1/20W 41 G3_POWERON_L R5072 10K 1 2
MF
201 SMC_LID R5071 100K 1 2
5% 1/20W MF 201
1 C5010 1 C5011 CPU_THRMTRIP_3V3 49 42 41
NC
NC
5% 1/20W MF 201
12PF 12PF
42 41 OUT
43 41 7 SMC_TX_L R5073 10K 1 2
5% 1/20W MF 201
5%
50V
5%
50V CRITICAL 43 41 7 SMC_RX_L R5074 100K 1 2
2 C0G-CERM 2 C0G-CERM 3
HDMI HPD ESD PROTECTION R5075 5% 1/20W MF 201
SMC_DEBUGPRT_TX_L 10K 1 2
0402 0402 Q5058 1
PM_THRMTRIP_B_L 41 40
SMC_DEBUGPRT_RX_L R5076 100K 1 2

5% 1/20W MF 201
Inversion now taking place on RIO MMBT3904LP-7 41 40

5% 1/20W MF 201
DFN1006-3
R5058 43 41 7 SMC_TMS R5077 10K 1 2
5% 1/20W MF 201
=PP3V3_S4_SMC 2 3.3K 2 SMC_TDO R5078 10K 1 2
B 1
8 25 42
1
5%
PM_THRMTRIP_L IN 11 20 89
43 41 7
43 41 7 SMC_TDI R5079
R5080
10K
10K
1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
B
R5059 1/20W 43 41 7 SMC_TCK 1 2
MF 5% 1/20W MF 201
SMC USB CLOCK REQUIRE THESE CRYSTAL VALUES:5,6,8,10,12,16,18,20,24,25 MHZ 100K 201 41 SMC_BIL_BUTTON_L R5081 10K 1 2
5% 5% 1/20W MF 201
1/20W 60 42 41 SMC_BC_ACOK R5087 470K 1 2
MF
2 201 41 SMC_S5_PWRGD_VIN R5092 100K 1 2
5% 1/20W MF 201
5% 1/20W MF 201
R5057 51 41 SMS_INT_L R5093 10K 1 2
5% 1/20W MF 201
1K CPU_THRMTRIP_3V3 R5094 100K 1 2
Hall Effect pads 41 OUT SMC_DP_HPD_L 1 2 HDMI_HPD_L IN 7 38 82
42 41
41 25 SPI_DESCRIPTOR_OVERRIDE_L NOSTUFF R5095 10K 1 2

5% 1/20W MF 201
5% 5% 1/20W MF 201
1/20W
MF
201 SMC_ROMBOOT
APN: 998-3029 1K for ESD protection
=PP3V3_S4_SMC 8 25 42
43 7
OMIT_TABLE 1
R5088
J5050 1
R5082 1K
HALL-SENSOR-MLB-PADS-K99 100K 5%
SM 5% 1/20W
1/20W MF
MF
1 8 2 201
NC NC 201
R5086 10K
2 7 =PP3V42_S3_HALL R5050 2
42 41 SMC_THRMTRIP 1 2
5% 1/20W MF 201
3 6 0 49 IN =PSOC_WAKE_L SMC_PME_S4_WAKE_L OUT 41
7SMC_LID_R 1 2 SMC_LID 41 42 49 MAKE_BASE=TRUE
NC
4 5
NC 5% 34 IN =BT_WAKE_L 70 41 37 SMC_DELAYED_PWRGD R5091 100K 1 2
1/16W
MF-LF
402
1 C5050 70 41 SMC_PM_G2_EN R5098 100K 1 2
5% 1/20W MF 201
0.001UF
BATLOW# ISOLATION
5% 1/20W MF 201
10% 70 41 18 SMC_ADAPTER_EN R5085 10K 1 2
5% 1/20W MF 201
2 50V
X7R-CERM 70 41 SMC_S4_WAKESRC_EN R5090 100K 1 2
0402 5% 1/20W MF 201
8 =PP3V3_S5_SMCBATLOW =PP3V3_SUS_SMC 8
34 7 PP3V3_WLAN
41 34 7 WIFI_EVENT_L R5089 10K 1 2
5% 1/20W MF 201
A PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION

R5040
100K
1
5%
Q5040 PAGE TITLE
1
607-6811 1 SUBASSY,PCBA HALL EFFECT,K99 J5050 CRITICAL
1/20W
MF
201
SSM3K15FV
SOD-VESM-HF
G
Internal 20K pull-up on PM_BATLOW_L in PCH.
SMC Support
2
DRAWING NUMBER SIZE

D
70 41 IN SMC_BATLOW_L PM_BATLOW_L OUT 18

3 2 REVISION
R
4.18.0
R5041 NOTICE OF PROPRIETARY PROPERTY: BRANCH
0 THE INFORMATION CONTAINED HEREIN IS THE
1 2 PROPRIETARY PROPERTY OF APPLE INC.
5%
1/16W
MF-LF
NOSTUFF I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
50 OF 132
402 SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
LPC+SPI Connector
CRITICAL
LPCPLUS_CONN:YES
J5100
55909-0374
M-ST-SM
8 =PP3V3_S5_LPCPLUS 31 32
8 =PP5V_S0_LPCPLUS
1 2 LPC_CLK33M_LPCPLUS IN 7 25 92
92 82 41 17 7 BI LPC_AD<0> 3 4 LPC_AD<2> BI 7 17 41 82 92
92 82 41 17 7 BI LPC_AD<1> 5 6 LPC_AD<3> BI 7 17 41 82 92
7 8
43 7 IN SPI_ALT_MOSI 9 10 SPIROM_USE_MLB BI 7 20 52
43 7 OUT SPI_ALT_MISO 11 12 SPI_ALT_CLK IN 7 43
92 82 41 17 7 IN LPC_FRAME_L 13 14 SPI_ALT_CS_L IN 7 43
41 18 7 OUT PM_CLKRUN_L 15 16 LPC_SERIRQ BI 7 17 41
42 41 7 OUT SMC_TMS 17 18 LPC_PWRDWN_L IN 7 18 25 41
25 7 IN LPCPLUS_RESET_L 19 20 SMC_TDI OUT 7 41 42
42 41 7 OUT SMC_TDO 21 22 SMC_TCK OUT 7 41 42
7 TP_SMC_TRST_L 23 24 SMC_RESET_L OUT 7 41 42 61
7 TP_SMC_MD1 25 26 SMC_ROMBOOT OUT 7 42
42 41 7 IN SMC_TX_L 27 28 SMC_RX_L OUT 7 41 42

29 30 LPCPLUS_GPIO BI 7 20
C 33 34 C
516S0573
SPI Bus Series Termination

SPI_ALT_MISO 7 43
SPI_ALT_MOSI 7 43
SPI_ALT_CLK 7 43
SPI_ALT_CS_L 7 43
LPCPLUS_R:YES LPCPLUS_R:YES LPCPLUS_R:YES LPCPLUS_R:YES

1
R5128 1
R5127 R5126
1 1
R5125 PLACE_NEAR=J5100.14:5mm
12 33 33 33 PLACE_NEAR=J5100.12:5mm
5% 5% 5% 5% PLACE_NEAR=J5100.9:5mm
1/16W 1/16W 1/16W 1/16W PLACE_NEAR=J5100.11:5mm
MF-LF MF-LF MF-LF MF-LF
2 402 2 402 2 402 2 402
PLACE_NEAR=U1800.AV3:5mm R5110 R5120

15 33
92 17 IN SPI_CS0_R_L 1 2 92 SPI_CS0_L 1 2 SPI_MLB_CS_L OUT 42 52
5% 5% PLACE_NEAR=R5125.2:5mm
1/16W
B
1/16W
B PLACE_NEAR=U1800.BA2:5mm R5111
15
MF-LF
402 R5121
33
MF-LF
402
92 17 IN SPI_CLK_R 1 2 92 SPI_CLK 1 2 SPI_MLB_CLK OUT 42 52
1/16W 1/16W
PLACE_NEAR=U1800.AY1:5mm R5112 MF-LF
402 R5122 MF-LF
402
SPI_MOSI_R 1
15
2 92 SPI_MOSI 1
33 2 SPI_MLB_MOSI
92 17 IN OUT 42 52
1/16W 1/16W
MF-LF
402 R5123 MF-LF
402
60.4 2
92 17 OUT SPI_MISO 1 SPI_MLB_MISO IN 42 52
1% PLACE_NEAR=U6100.2:5mm
1/16W
MF-LF
402
PAGE TITLE
LPC+SPI Debug Connector

DRAWING NUMBER SIZE

REVISION
R
4.18.0
51 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH SMBus "0" Connections SMC "0" SMBus Connections SMC "5" SMBUS CONNECTIONS
44 8 =PP3V3_S0_SMBUS_PCH 8 =PP3V3_S0_SMBUS_SMC_0_S0 8 =PP3V42_G3H_SMBUS_SMC_5
R5200 1
1
R5250 1
1
R5280 1
1
Panther Point R5201 SMC R5251 GPU Temp (Ext) SMC R5281 Battery Charger
1K 1K 4.7K 4.7K 2.0K 2.0K
5% 5% 5% 5% 5% 5%
U1800 1/16W 1/16W U4900 1/16W 1/16W EMC1414-A: U5550 U4900 1/16W 1/16W ISL6258 - U7000
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
(MASTER) 402
2 2
402 (MASTER) 402
2 2
402 (Write: 0x98 Read: 0x99) (MASTER) 402
2 2
402 (Write: 0x12 Read: 0x13)
94
SMBUS_PCH_CLK SMB_0_S0_CLK SMBUS_SMC_0_S0_SCL =SMBUS_GPUTHMSNS_SCL SMB_5_CLK SMBUS_SMC_5_G3_SCL =SMBUS_CHGR_SCL
D
92 17 41 47 61
D 92 17
MAKE_BASE=TRUE
SMBUS_PCH_DATA
MAKE_BASE=TRUE
TBT SMB_0_S0_DATA 94
41
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUE
=SMBUS_GPUTHMSNS_SDA 47 SMB_5_DATA
MAKE_BASE=TRUE
SMBUS_SMC_5_G3_SDA
MAKE_BASE=TRUE
=SMBUS_CHGR_SDA 61
U3600
(WRITE: 0xFE READ: 0xFF)
VRef DACs =I2C_TBTRTR_SCL 35 GPU Temp (Int) Battery

GK107: U8000
U3300 =I2C_TBTRTR_SDA 35 J6950
(Write: 0x9E Read: 0x9F)
(Write: 0x98 Read: 0x99) (Write: 0x16 Read: 0x17)
VBIOS may overwrite as 0x82/0x83
33 =I2C_VREFDACS_SCL GPU_SMB_CLK_R 78 =SMBUS_BATT_SCL 60
33 =I2C_VREFDACS_SDA GPU_SMB_DAT_R 78 =SMBUS_BATT_SDA 60
Margin Control SMC "2" SMBUS CONNECTIONS

U3301
NOTE: SMC RMT bus remains powered and may be active in S3 state
SMC "3" SMBUS CONNECTIONS
(Write: 0x30 Read: 0x31) 8 =PP3V3_S3_SMBUS_SMC_2_S3
The bus formerly known as "Battery B"
33 =I2C_PCA9557D_SCL 8 =PP3V3_S3_SMBUS_SMC_3
33 =I2C_PCA9557D_SDA R5270 1
1
R5271
SMC 1K 1K
Trackpad
1 1
U4900
5%
1/16W
5%
1/16W J5800 SMC R5290 R5291 DEBUG SENSOR ADC A
MF-LF MF-LF 4.7K 4.7K
(MASTER) 402 2 2 402 (Write: 0x90 Read: 0x91) 5% 5%
U4900 1/16W 1/16W UD100
Audio SMB_2_S3_CLK SMBUS_SMC_2_S3_SCL =I2C_TPAD_SCL
MF-LF MF-LF
49 (MASTER) 402 2
2 402
(Write: 0x10 Read: 0x11)
MAKE_BASE=TRUE
U6751 & U6750 94
SMB_2_S3_DATA SMBUS_SMC_2_S3_SDA =I2C_TPAD_SDA 49 SMB_3_CLK 41 SMBUS_SMC_3_SCL =I2C_SMC_ADCS_SCL 98
C Mikey (WRITE: 0X72 READ: 0X73)

China HS (WRITE: 0X76 READ: 0X77)
58 =I2C_MIKEY_SCL
MAKE_BASE=TRUE
SMB_3_DATA
MAKE_BASE=TRUE
94
41 SMBUS_SMC_3_SDA
MAKE_BASE=TRUE
=I2C_SMC_ADCS_SDA 98
C
58 =I2C_MIKEY_SDA J3502
ALS
XDP Connectors =I2C_ALS_SCL 34
J2500 & J2550

=I2C_ALS_SDA 34
(MASTER)
24 =SMBUS_XDP_SCL
SMS
24 =SMBUS_XDP_SDA U5920
(WRITE: 0X30/31 READ: 0X32/33)
GYRO
51 =I2C_SMC_SMS_SCL
U5940
(WRITE: 0XD0 READ: 0XD1)
51 =I2C_SMC_SMS_SDA
=I2C_SMC_GYRO_SCL 51
=I2C_SMC_GYRO_SDA 51
SMC "1" SMBUS CONNECTIONS

B PCH "SMLink 0" Connections =PP3V3_S0_SMBUS_SMC_1_S0
44 8 =PP3V3_S0_DPMUXI2C
B
8
HDMI REDRIVER SMBUS CONNECTION
44 8 =PP3V3_S0_SMBUS_PCH
1 1 DPMUX IC R52361 R5237
1
R5260 R5261 HDMI Redriver (on RIO)
SMC CPU/DDR3/PCH/AIRFLOW TEMP 4.7K 4.7K
1K 1K U9100 5% 5% J4410 -> U9700
1 1
5% 5% 1/20W 1/20W
R5210 R5211 U4900 1/16W 1/16W EMC1414-A: U5570 (MASTER) MF MF (WRITE: 0xCC READ: 0xCD)
Panther Point 8.2K 8.2K
MF-LF MF-LF 201 2 2 201
(MASTER) 402 2 2 402 (Write: 0x98 Read: 0x99)
5% 5%
U1800 1/16W 1/16W 94 82 =I2C_DPMUX_A_SCL 7 I2C_DPMUX_A_SCL =I2C_HDMIRDRV_SCL 38
MF-LF MF-LF SMB_1_S0_CLK 41 SMBUS_SMC_1_S0_SCL =I2C_CPUTHMSNS_SCL 47 MAKE_BASE=TRUE
(MASTER) 402 402 MAKE_BASE=TRUE
2 2
94 82 =I2C_DPMUX_A_SDA 7 I2C_DPMUX_A_SDA =I2C_HDMIRDRV_SDA 38
SMB_1_S0_DATA 41 SMBUS_SMC_1_S0_SDA =I2C_CPUTHMSNS_SDA 47 MAKE_BASE=TRUE
92 17 SML_PCH_0_CLK MAKE_BASE=TRUE
MAKE_BASE=TRUE
92 17 SML_PCH_0_DATA
MAKE_BASE=TRUE
44 8 =PP3V3_S0_DPMUXI2C
LED BACKLIGHT SMBUS CONNECTION

X29 TEMP DPMUX IC R5234
1 1
R5235 LED BACKLIGHT
PCH "SMLink 1" Connections TMP105: U5523 U9100
4.7K
5% 5%
4.7K
U9700
1/16W 1/16W
(WRITE: 0X92 READ: 0X93) (MASTER) MF-LF MF-LF (WRITE: 0x58 READ: 0x59)
402 2 2 402
44 8 =PP3V3_S0_SMBUS_PCH
=I2C_X29THMSNS_SCL 47
82 =I2C_DPMUX_UC_SCL I2C_DPMUX_UC_SCL =I2C_BKL_1_SCL 86
MAKE_BASE=TRUE
NO STUFF NO STUFF =I2C_X29THMSNS_SDA 47
82 =I2C_DPMUX_UC_SDA I2C_DPMUX_UC_SDA =I2C_BKL_1_SDA 86
1 1
Panther Point R5220 R5221 MAKE_BASE=TRUE
8.2K 8.2K R5223
5% 5%
A U1800
1/16W
MF-LF
402
2 2
1/16W
MF-LF
402
0
5%
1/16W
MF-LF
402 PAGE TITLE
SML_PCH_1_CLK 1 2
92 17
MAKE_BASE=TRUE SMBus Connections
92 17 SML_PCH_1_DATA 1 2 DRAWING NUMBER SIZE
MAKE_BASE=TRUE
R5222 Apple Inc. 051-9589 D
0 REVISION
5%
1/16W
MF-LF
R
4.18.0
SMLink 1 is slave port to 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
access PCH & CPU via PECI. PROPRIETARY PROPERTY OF APPLE INC.
52 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOSTUFF
PLACE_NEAR=U4900.N11:5mm
PBUS Voltage Sense Enable & Filter GPU VCore Load Side Current Sense / Filter R5310
4.53K
GFXIMVP6_IMON 1 2
CRITICAL 80 IN
SENSOR_NONPROD:Y 1%
=PP3V3_S0_ISNS 1/20W
Q5300 98 45 8
99 CRITICAL MF
201
NTUD3169CZ
SOT-963
1
C5310
N-CHANNEL 0.1UF
6 PBUSVSENS_EN_L 20%
10V
2 CERM
Enables PBUS VSense D 402
SENSOR_NONPROD:Y
1
divider when in S0. R5302 EDP:50A CRITICAL
100K Vimon=3x50A*(0.2/R8915)*R8912=1V U5310 SENSOR_NONPROD:Y
70 IN =PBUSVSENS_EN 2 G 1%
SMC Key IG0C
D 1
S 1/16W
MF-LF
402
2
3
V+
8 OPA2333
DFN R5308
4.53K
SMC_ADC15 D
1 GPUVCORE_IOUT 1 2 SMC_GPU_CORE_ISENSE OUT 42
3 PBUS_S0_VSENSE
SMC Key VP0R
GPUVCORE_INV 2 V- 1%
1/20W
SENSOR_NONPROD:Y
D THRM MF 1
C5308
R5303 1 SMC_ADC5 9
4
201
0.22UF
27.4K 20%
5 G 1% 2
6.3V
X5R
S 1/16W PLACE_NEAR=U4900.L8:5MM 0201
8 =PPBUS_S0_VSENSE MF-LF
4
402
2
RTHEVENIN = 4573 Ohms SENSOR_NONPROD:Y Gain: 3.004x GND_SMC_AVSS
P-CHANNEL SMC_PBUS_VSENSE OUT 42

1
R5309 SENSOR_NONPROD:Y
R5307
499K
R5301 1 PLACE_NEAR=U4900.L8:5MM
1%
1/16W 1
1M
2
100K R5304 1 1
C5304
MF-LF
2 402
1% 1%
1/16W 5.49K 0.22UF
1/16W
MF-LF 1% MF-LF
20% 402
402 1/16W 6.3V
2
MF-LF 2 X5R
402 SIGNAL_MODEL=EMPTY
PBUSVSENS_EN_L_DIV 2 402
PLACE_NEAR=U4900.L8:5MM GND_SMC_AVSS 41 42 45 46 99
DC-In Voltage Sense Enable & Filter

EDP:21.329A
CPU 1.05V VCCIO Current Sense / Filter
CRITICAL SENSOR_NONPROD:Y
NC
=CHGR_ACOK IN 42 61 Vi=Voltage across R7640=0.02139V CRITICAL SMC Key IC1C
NOSTUFF SENSOR_NONPROD:Y U5310
Q5310 R5323 PLACE_NEAR=U4900.L12:5mm SMC_ADC11
1
R5315 NTUD3169CZ 6.49K 8 OPA2333 SENSOR_NONPROD:Y
R5327
0 Enables DC-In VSense SOT-963 96 67 IN CPUVCCIOS0_CS_P 1 2 96 CPUVCCIOISNS_R_P 5 DFN
5%
1/20W divider when AC present.
N-CHANNEL 6 DCINVSENS_EN_L 1%
V+ 7 ISENSE_CPUVCCIO_IOUT 1
4.53K
2 SMC_CPUVCCIO_ISENSE 42
OUT
MF 1/16W
2 201 D
MF-LF
SENSOR_NONPROD:Y 402
6 V- 1%
1/16W SENSOR_NONPROD:Y
R5312 1 R5324 THRM
4 MF-LF
402 1
C5327
C DCINVSENS_EN 2 G
100K
1% 96 67 IN CPUVCCIOS0_CS_N 1
6.49K
2 96 CPUVCCIOISNS_R_N
9
Gain: 154x 0.22UF
PLACE_NEAR=U4900.L12:5mm
C
NC
20%
S 1/16W 6.3V
NC
MF-LF 1% 2
1/16W X5R
402 SENSOR_NONPROD:Y
1
R5316 1 2 MF-LF
402
1
R5325 SENSOR_NONPROD:Y
R5326
402
0 3 DCIN_S5_VSENSE 1M GND_SMC_AVSS 41 42 45 46 99
5% Enables DC-In VSense 1% 1M
1/20W 1/16W 1 2
MF divider when SUS present. D MF-LF
2 201 R53131 SMC KEY VD0R 2
402 1%
1/16W
PM_SUS_EN IN 70
5 G
30.9K
1%
PLACE_NEAR=U4900.N9:5MM SMC_ADC3 MF-LF
402
SIGNAL_MODEL=EMPTY
S 1/16W
8 =PPDCIN_S5_VSENSE MF-LF Divider set for Vin max of 22.32V
4
402 2 RTHEVENIN = 4567 Ohms
P-CHANNEL SMC_DCIN_VSENSE 42
OUT
1
R5311 PLACE_NEAR=U4900.N9:5MM
100K
1%
R5314 1
1
PLACE_NEAR=U4900.N9:5MM
C5314
CPU SA Current Sense / Filter
1/16W 5.36K 0.22UF 99 98 45 8 =PP3V3_S0_ISNS
MF-LF 1% 20%
402
2
1/16W 6.3V
MF-LF 2
PDCINVSENS_EN_L_DIV
402 2
X5R
402
1
C5360
EDP:6A 0.1UF
GND_SMC_AVSS 20%
41 42 45 46 99
Vi=Voltage across R7140=0.006V CRITICAL 2
10V
U5360
X7R-CERM
0402 SMC Key IC2C
R5363 8 OPA2333 PLACE_NEAR=U4900.M10:5mm SMC_ADC13
1.82K R5367
96 62 IN VCCSAS0_CS_P 1 2 96 VCCSAISNS_R_P 3 DFN
CPU Vcore Voltage Sense / Filter 1%

V+ 1 ISENSE_SA_IOUT 1
4.53K
2 SMC_CPU_SA_ISENSE 42
1/16W
OUT
SMC Key VC0C

MF-LF
402
2 V- 1%
1/16W
THRM MF-LF
SMC_ADC0 R5364 4
402 1
C5367
XW5320 R5320 VCCSAS0_CS_N
1.82K 9
0.22UF
PLACE_NEAR=U4900.M10:5mm
98 15 13 8 =PPVCORE_S0_CPU SM 96 62 IN
1 2 96 VCCSAISNS_R_N
4.53K 20%
1 2 CPUVSENSE_IN 1 2 SMC_CPU_VSENSE OUT 42 1% 2
6.3V
1/16W GAIN:549X X5R
402
B B
PLACE_NEAR=R7510.2:5 MM 1% PLACE_NEAR=U4900.N10:5MM MF-LF
1
1/16W
MF-LF 1
C5320
402
R5365 GND_SMC_AVSS
402 1M R5366 41 42 45 46 99
PLACE_NEAR=U4900.N10:5MM 0.22UF 1% 1M
20% 1 2
6.3V 1/16W
2 X5R MF-LF
402 1%
402 2 1/16W
MF-LF
GND_SMC_AVSS 41 42 45 46 99 402
SIGNAL_MODEL=EMPTY
GFX Vcore Voltage Sense / Filter

SMC Key VN0C PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
XW5330 SMC_ADC12
66 8 =PPVCORE_S0_AXG_REG SM
R5330 116S0114 1 RES,MTL FILM,100K,5,1/16W,0402,SMD,LF C5327 SENSOR_NONPROD:N
4.53K
1 2 GFXVSENSE_IN 1 2 SMC_GFX_VSENSE OUT 42
117S0008 1 RES,MF,1/20W,100K OHM,5,0201,SMD C5308 SENSOR_NONPROD:N
PLACE_NEAR=R7550.2:5 MM 1% PLACE_NEAR=U4900.N12:5MM
1/16W
MF-LF
402
1
C5330
PLACE_NEAR=U4900.N12:5MM 0.22UF
20%
6.3V
2 X5R
402
GND_SMC_AVSS 41 42 45 46 99
DDR3 1.5V DRAM ONLY CURRENT SENSE / FILTER
SMC KEY IM0C
SMC_ADC10
NC
GPU Vcore Voltage Sense / Filter EDP CURRENT:8A
CRITICAL
=PPVIN_S3_MEM_ISNS_R U5360 PLACE_NEAR=U4900.N13:5mm
8 IN R5373 OPA2333
SMC KEY VG0C
A
8
7.32K
8 =PPVCORE_GPU_REG
XW5335
SM
R5335 SMC_ADC14
R5360
0612
MF
2 4
96 ISNS_1V5_MEM_P
1
1%
2 96 ISNS_1V5_MEM_R_P 5
V+
DFN
7 ISENSE_P1V5MEM_IOUT 1
R5377
4.53K
2 SMC_P1V5MEM_ISENSE OUT 42
SYNC_MASTER=D2_SEAN
PAGE TITLE
SYNC_DATE=03/05/2012 A
4.53K 1W
1/16W
1 2 GPUVSENSE_IN 1 2 SMC_GPU_CORE_VSENSE OUT 42 MF-LF 6 V- 1%
1%
1%
402
THRM
1/16W Voltage & Load Side Current Sensing
PLACE_NEAR=R8940.1:5 MM PLACE_NEAR=U4900.L10:5MM 0.003 R5374 4 MF-LF
1/16W 96 ISNS_1V5_MEM_N 402 1
C5377 DRAWING NUMBER SIZE
MF-LF 1
C5335 1 3 7.32K 9 PLACE_NEAR=U4900.N13:5mm
402
0.22UF CRITICAL 1 2 96 ISNS_1V5_MEM_R_N 0.22UF
NC
20%
PLACE_NEAR=U4900.L10:5MM 6.3V
NC
20%
6.3V
1% GAIN:136.6X 2 X5R REVISION
=PPVIN_S3_MEM_ISNS 1/16W
2 X5R
402
8 OUT MF-LF
1
402 R
4.18.0
402
R5375 R5376 GND_SMC_AVSS 41 42 45 46 99 NOTICE OF PROPRIETARY PROPERTY: BRANCH
GND_SMC_AVSS 41 42 45 46 99 1M 1M
1% 1 2 THE INFORMATION CONTAINED HEREIN IS THE
1/16W PROPRIETARY PROPERTY OF APPLE INC.
MF-LF 1% THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1/16W
2
402
MF-LF
402
SIGNAL_MODEL=EMPTY I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
53 OF 132
Gain: 182x III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
COMPUTING High Side Current Sense / Filter
SIGNAL_MODEL=EMPTY
46 8 =PP3V3_S0_HS_ISNS
SENSOR_NONPROD:Y
SMC Key IC0R
CPU VCore Load Side Current Sense / Filter
C5401 PLACE_NEAR=R7510.3:5MM R5456
1 5.23K
EDP Current:20.1A 0.1UF SMC_ADC8 97 66 65 CPUIMVP_ISNS1_P 1 2
20% IN
10V 0.5%
3
CERM 1/16W
2
8 OUT =PPVIN_S5_HS_COMPUTING_ISNS V+
402 MF
402 46 8 =PP3V3_S0_IMVPISNS SENSOR_NONPROD:Y
PLACE_NEAR=U4900.N8:5MM SENSOR_NONPROD:Y PLACE_NEAR=U5450.5:3MM
U5400 R5403 PLACE_NEAR=R7520.3:5MM
R5457
R5400
2 4 INA213 4.53K 5.23K
SIGNAL_MODEL=EMPTY 1 C5450
0612
ISNS_HS_COMPUTING_N 5 IN- 6 HS_COMPUTING_IOUT 1 2 SMC_CPU_HI_ISENSE CPUIMVP_ISNS2_P 1 2 0.1UF
OUT
D
96 SC70 42 97 66 65
OUT IN
MF 20% SMC Key IC0C
D Power Drop across R5400 at EDP becomes 1.21W
1W
1%
96 ISNS_HS_COMPUTING_P 4 IN+
CRITICAL
REF 1
1%
1/16W
MF-LF
1
PLACE_NEAR=U4900.N8:5MM
C5403
0.5%
1/16W
MF
SENSOR_NONPROD:Y
10V
2 X7R-CERM
0402 SMC_ADC1
0.003 1 3
402
0.22UF SENSOR_NONPROD:Y 402 SENSOR_NONPROD:Y CRITICAL
20%
CRITICAL GND 6.3V
PLACE_NEAR=R7530.3:5MM
R5458 R5452 U5450 SENSOR_NONPROD:Y
X5R
2 402 5.23K 3.48K OPA333DCKG4 PLACE_NEAR=U4900.M11:5MM
Gain:50x 5
2
CPUIMVP_ISNS3_P 1 2 96 CPUIMVP_ISNS_P 1 2 CPUIMVP_ISUM_R_P 1
97 66 65 IN 97
+ SC70-5 R5451
8 IN =PPVIN_S5_HS_COMPUTING_ISNS_R SIGNAL_MODEL=EMPTY 0.5% 1% V+ 4.53K
GND_SMC_AVSS 41 42 45 46 99 1/16W 1/16W 4 CPUIMVP_ISUM_IOUT 1 2 SMC_CPU_ISENSE OUT 42
MF MF-LF
402 402 1% SENSOR_NONPROD:Y
SENSOR_NONPROD:Y 3 V- 1/16W PLACE_NEAR=U4900.M11:5MM
PLACE_NEAR=R7510.4:5MM - MF-LF
R5470 R5453 2
402 1 C5451
5.23K 3.48K
GRAPHICS High Side Current Sense / Filter 97 66 IN
CPUIMVP_ISNS1_N 1 2 CPUIMVP_ISNS_N 1 2 97 CPUIMVP_ISUM_R_N 0.22UF
20%
6.3V
SIGNAL_MODEL=EMPTY 0.5% 1% 2 X5R
1/16W 1/16W
402
SENSOR_NONPROD:Y MF MF-LF SENSOR_NONPROD:Y
402 402
=PP3V3_S0_HS_ISNS SENSOR_NONPROD:Y GND_SMC_AVSS
46 8
R5455 41 42 45 46 99
PLACE_NEAR=R7520.4:5MM 1 732K
SENSOR_NONPROD:Y R5471 R5454 1 2
1 C5411 5.23K 732K
0.1UF 97 66 IN CPUIMVP_ISNS2_N 1 2 1% 1% Gain:140x
SMC Key IG0R 1/16W 1/16W SIGNAL_MODEL=EMPTY
20%
SIGNAL_MODEL=EMPTY 0.5% MF-LF MF-LF Scale: 28.55A / V
EDP Current:4.9A
10V
SMC_ADC2 1/16W
2 402
402
3
2 CERM
402
MF
402
Max VOut: 3.3V at 94.2A
=PPVIN_S5_HS_GPU_ISNS V+
8 OUT
PLACE_NEAR=U4900.K9:5MM SENSOR_NONPROD:Y R5472
R5410 U5410 R5413 CPUIMVP_ISNS3_N 1
5.23K
2
97 66 IN
0612
2 4 INA210 4.53K SIGNAL_MODEL=EMPTY
MF
96 ISNS_HS_GPU_N 5 IN- SC70OUT 6 HS_GPU_IOUT 1 2 SMC_GPU_HI_ISENSE OUT 42 SIGNAL_MODEL=EMPTY 0.5%
1/16W
1W
1% CRITICAL 1% PLACE_NEAR=U4900.K9:5MM MF
1/16W 402
0.003 96 ISNS_HS_GPU_P 4 IN+ REF 1 MF-LF
1 C5413
1 3
402
0.22UF Sense R is R7510, R7520 & R7530
CRITICAL GND
20%
6.3V Individual Sense R is 0.75mOhm
2 X5R
402 EDP: 94A TDP :45A
2
8 IN =PPVIN_S5_HS_GPU_ISNS_R
Gain:200x
C GND_SMC_AVSS 41 42 45 46 99
(Effective Sense R is 0.25mOhm due to summing of the 3 phases)
C
OTHER High Side Current Sense / Filter

46 8 =PP3V3_S0_HS_ISNS GFX/IG VCore Load Side Current Sense / Filter
SMC Key IO0R
1 C5431
EDP Current:12.546A 0.1UF SENSOR_NONPROD:Y
20%
SMC_ADC9 PLACE_NEAR=R7560.3:5MM
10V R5468
3
=PPVIN_S5_HS_OTHER_ISNS CERM =PP3V3_S0_IMVPISNS

8 OUT 2 5.23K 46 8 SENSOR_NONPROD:Y
V+
402
97 66 IN CPUIMVP_ISNS2G_P 1 2
PLACE_NEAR=U4900.L7:5MM PLACE_NEAR=U5460.5:3MM
R5430 2 4
U5430 R5433
SIGNAL_MODEL=EMPTY 0.5%
1/16W
MF
1 C5460
0612 96 ISNS_HS_OTHER_N INA213 4.53K 402 0.1UF
MF 6
1W 5 IN- SC70 OUT HS_OTHER_IOUT 1 2 SMC_OTHER_HI_ISENSE OUT 42 SENSOR_NONPROD:Y 20%
10V SMC Key IN0C
1% 2 X7R-CERM
CRITICAL 1% PLACE_NEAR=U4900.L7:5MM SENSOR_NONPROD:Y SENSOR_NONPROD:Y CRITICAL
0.005 1/16W 0402
SMC_ADC18
1 3
96 ISNS_HS_OTHER_P 4 IN+ REF 1 MF-LF
402 1 C5433 PLACE_NEAR=R7550.3:5MM
R5466 R5462 U5460 SENSOR_NONPROD:Y
CRITICAL 0.22UF 5.23K 5.49K OPA333DCKG4 PLACE_NEAR=U4900.M13:5MM
20% CPUIMVP_ISNS1G_P 1 2 CPUIMVP_ISNS1G_R_P 1 2 97 CPUIMVP_ISUMG_R_P 1 5
GND 6.3V 96 66 IN + SC70-5 R5461
2
X5R
402 SIGNAL_MODEL=EMPTY 0.5% 1% V+ 4CPUIMVP_ISUMG_IOUT 4.53K
=PPVIN_S5_HS_OTHER_ISNS_R SMC_CPU_GFX_ISENSE
2
8 1/16W 1/16W 1 2 42
IN OUT
Gain:50x MF
402
MF-LF
402 1%
SENSOR_NONPROD:Y
V- PLACE_NEAR=U4900.M13:5MM
3 1/16W
GND_SMC_AVSS SENSOR_NONPROD:Y - MF-LF 1
C5461
41 42 45 46 99 2
0.22UF
PLACE_NEAR=R7550.4:5MM 20%
R5467 R5463 2
6.3V
X5R
5.23K 5.49K
96 66 IN
CPUIMVP_ISNS1G_N 1 2 CPUIMVP_ISNS1G_R_N 1 2 CPUIMVP_ISUMG_R_N 402
B SIGNAL_MODEL=EMPTY 0.5%
1/16W
MF
1%
1/16W
MF-LF
SENSOR_NONPROD:Y
R5465
GND_SMC_AVSS 41 42 45 46 99
B
402 402 732K
SENSOR_NONPROD:Y 1 2 Gain:90.31x
R5469 1% SIGNAL_MODEL=EMPTY
5.23K 1/16W
97 66 IN CPUIMVP_ISNS2G_N 1 2 MF-LF
SIGNAL_MODEL=EMPTY 0.5%
1
1/16W
MF R5464
402 732K
SENSE R IS R7550, R7560, 0.75MOHM 1%
1/16W
MF-LF
EDP: 33A TDP: 21.5A 2
402
SIGNAL_MODEL=EMPTY
CHARGER BMON HIGH SIDE (BATTERY DISCHARGE) CURRENT SENSE & FILTER PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
116S0114 2 RES,MTL FILM,100K,5,1/16W,0402,SMD,LF C5451,C5461 SENSOR_NONPROD:N
IPBR
R5423 R5420 SMC_ADC7
45.3K 0
61 IN CHGR_BMON 1 2 SMC_CHGR_BMON_INSENSE_R 1 2 SMC_CHGR_BMON_ISENSE OUT 42
1% 5%
From charger 1/16W
MF-LF 1 C5421 1/16W
MF-LF
402 0.022UF 402
10%
16V
2 X5R-X7R-CERM
0402
A GND_SMC_AVSS 41 42 45 46 99
SYNC_MASTER=D2_SEAN SYNC_DATE=03/05/2012 A
PAGE TITLE
DC-IN (AMON) Current Sense Filter High Side and CPU/AXG Current Sensing
PLACE_NEAR=U4900.K10:5MM SMC Key ID0R DRAWING NUMBER SIZE
EDP Current:4.6A
R5441 SMC_ADC4
45.3K2 REVISION
CHGR_AMON 1 SMC_DCIN_ISENSE
61 IN
1% PLACE_NEAR=U4900.K10:5MM
OUT 42 R
4.18.0
1/16W NOTICE OF PROPRIETARY PROPERTY: BRANCH
MF-LF
402
1 C5441 THE INFORMATION CONTAINED HEREIN IS THE
0.0022UF PROPRIETARY PROPERTY OF APPLE INC.
10% THE POSESSOR AGREES TO THE FOLLOWING: PAGE
50V
2 CERM
402
54 OF 132
GND_SMC_AVSS 41 42 45 46 99
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPU PROXIMITY/GPU DIE/LEFT FIN STACK/RIGHT FIN STACK

R5550
47
8 =PP3V3_S0_GPUTHMSNS 1 2 PP3V3_S0_GPUTHMSNS_R
5% MIN_NECK_WIDTH=0.2 mm
1/16W
MF-LF
VOLTAGE=3.3V
1
C5550
402 0.1UF
20%
PLACE_NEAR=U5550.2:5mm
2
10V R5551 1 1
R5552
GPU_TDIODE_P PLACE_NEAR=U5550.3:5mm X7R-CERM 10K 10K
96 77 BI 0402
D Detect GPU Die Temperature SIGNAL_MODEL=EMPTY

1
VDD
5%
1/16W
MF-LF
402
5%
1/16W
MF-LF
402
D
C5551 1
U5550 2 2
TG0D 0.0022uF
10%
EMC1414-A-AIA
50V DFN
CERM 2 2 DP1 THERM*/ADDR 7 GPUTHMSNS_THM_L
402
96 77 GPU_TDIODE_N 3 DN1 ALERT* 8 GPUTHMSNS_ALERT_L

BI
CRITICAL
GPUTHMSNS_D_P 4 DP2/DN3 9 =SMBUS_GPUTHMSNS_SDA
Q5501 96 SMDATA BI 44
BC846BMXXH 2
SOT732-3 CRITICAL 3
SIGNAL_MODEL=EMPTY
5 DN2/DP3 SMCLK 10 =SMBUS_GPUTHMSNS_SCL 44
BI
1
C5552 1 GND THRM_PAD
Placement note: Q5503 1
0.0022uF 6 11
PLACE Q5501 ON TOP SIDE BC846BMXXH 10%
TG0P GPU PROXIMITY TEMPERATURE
SOT732-3 50V
CERM 2
3
CLOSE TO THE LEFT FIN STACK 2 402
96 GPUTHMSNS_D_N
Placement note:
PLACE U5550 ON TOP SIDE UNDER GPU
Th2H LEFT FIN STACK TEMPERATURE Th1H RIGHT FIN STACK TEMPERATURE PLACE_NEAR=U5550.4:5mm
PLACE_NEAR=U5550.5:5mm THSP TBT DIE
Placement note: TP_TBT_THERM_DP 97 TBT_THERMD_P
35 BI
PLACE Q5503 ON BOTTOM SIDE NEAR RIGHT FIN STACK Write Address: 0x98 MAKE_BASE=TRUE
NOSTUFF
Read Address: 0x99
1
R5520
10K
PLACE_SIDE=BOTTOM 5%
1/16W
DDR3 PROXIMITY/CPU PROXIMITY/PCH PROXIMITY/AIRFLOW PROXIMITY

MF-LF
402
PLACE_NEAR=U3600.B1:2mm 2
1 2 97 TBT_THERMD_N
R5570 XW5520
C 8 =PP3V3_S0_CPUTHMSNS 1
47
2 PP3V3_S0_CPUTHMSNS_R
SM
C
5% MIN_NECK_WIDTH=0.2 mm Use GND pin B1 on U3600 for N leg
1/16W
MF-LF
VOLTAGE=3.3V
1
C5570
0.1UF
402
1 20% R5571 1 1
R5572
10V
VDD 2 10K 10K
TM0P DDR3 PROXIMITY TEMPERATURE X7R-CERM
5% 5%
U5570 0402
1/16W
MF-LF
1/16W
MF-LF
96 DDR3THMSNS_D1_P EMC1414-A-AIA 402
2 2
402
DFN
2 DP1 THERM*/ADDR 7 CPUTHMSNS_THM_L
CRITICAL 3 PLACE_NEAR=U5570.3:5mm
C5571 1 3 DN1 ALERT* 8 CPUTHMSNS_ALERT_L

Placement note:
Q5506 1
0.0022uF
BC846BMXXH 10% 4 DP2/DN3 SMDATA 9 =I2C_CPUTHMSNS_SDA 44
SOT732-3 50V BI
PLACE Q5503 ON TOP SIDE NEAR DDR3 SIGNAL_MODEL=EMPTY CERM 2
2 5 DN2/DP3 10
402
SMCLK =I2C_CPUTHMSNS_SCL BI 44
96 DDR3THMSNS_D1_N GND THRM_PAD

6 11 TC0P CPU PROXIMITY TEMPERATURE
Ta0P AIRFLOW PROXIMITY TEMPERATURE
CRITICAL
96 CPUTHMSNS_D2_P
Placement note:
Q5502 PLACE U5570 ON TOP SIDE UNDER CPU
SIGNAL_MODEL=EMPTY
BC846BMXXH 2
CRITICAL 3
SOT732-3 C5590 1
1
Q5504 1 0.0022uF
10%
BC846BMXXH 50V
2
SOT732-3 CERM
402
2
3
96 CPUTHMSNS_D2_N Write Address: 0x98
TP0P PCH PROXIMITY TEMPERATURE Read Address: 0x99
Placement note: PLACE_NEAR=U5570.5:5mm
B PLACE Q5502 ON TOP SIDE

CLOSE TO BOARD EDGE Placement note:
B
PLACE Q5504 ON TOP SIDE UNDER PCH
TW0P X29 PROXIMITY

8 =PP3V3_S0_X29THMSNS
1 C5523 1
PLACE_NEAR=J3501
R5522
PLACE_SIDE=BOTTOM 0.1uF 10K
C1 20%
5%
10V
V+ 2 CERM
1/16W
402 MF-LF
U5523 2 402
TMP105
WCSP-6
44 BI =I2C_X29THMSNS_SDA A1 SDA A0 C2 X29THMSNS_A0
CRITICAL
44 BI =I2C_X29THMSNS_SCL B1 SCL ALERT B2 NC
GNDS WRITE ADDRESS: 0X92

A2 READ ADDRESS: 0X93
PAGE TITLE
Thermal Sensors
DRAWING NUMBER SIZE
Placement note: Apple Inc. 051-9589 D

REVISION
PLACE U5523 ON BOTTOM NEAR X29 CONN R
4.18.0
55 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C Left Fan Right Fan C

8 =PP5V_S0_FAN_LT 8 =PP5V_S0_FAN_RT
8 =PP3V3_S0_FAN_LT 8 =PP3V3_S0_FAN_RT
CRITICAL CRITICAL
R5650 1 J5650 R5660 1 J5660
47K FF14A-5C-R11DL-B-3H 47K FF14A-5C-R11DL-B-3H
5% F-RT-SM 5% F-RT-SM
1/16W 1/16W
6 6
MF-LF
NC MF-LF
NC
R5655 402 2
R5665 402 2
47K 1 47K 1
41 OUT SMC_FAN_0_TACH 1 2 7 FAN_LT_TACH 41 OUT SMC_FAN_1_TACH 1 2 7 FAN_RT_TACH
5% 2 5% 2
1/16W 1/16W
MF-LF 3 MF-LF 3
402 402
4 4
1 1
R5651 5 R5661 5
100K NC 100K NC
5% 5 5% 2
1/16W Q5660 7 1/16W Q5660 7
MF-LF MF-LF
402 2
G 2N7002DW-X-G NC 402 2
G 2N7002DW-X-G NC
SOT-363 SOT-363
4 S D 3 518S0769 1 S D 6 518S0769
41 IN SMC_FAN_0_CTL 7 FAN_LT_PWM 41 IN SMC_FAN_1_CTL 7 FAN_RT_PWM
B B
PAGE TITLE
Fan Connectors
DRAWING NUMBER SIZE

REVISION
R
4.18.0
56 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
IC PIN NAME CURRENT R_SNS V_SNS POWER
PSOC USB CONTROLLER - USB INTERFACES TO MLB
TMP102
3V3 LDO
V+
VDD
10UA
80UA
60MA (MAX)
2.55 KOHM
10 OHM
0.0255
0.204
0.6
V
V
V
0.255E-6
16.32E-6
36E-3
W
W
W Keyboard Connector
VOUT 60MA (MAX) 0.2 OHM 0.012 V 0.72E-3 W
- SPI HOST TO Z2
- TRACKPAD PICK BUTTONS PSOC VDD 8MA (TYP)
14MA (MAX)
1.5 OHM 0.012
0.021
V
V
96E-6
294E-6
W
W
IPD Flex Connector
- KEYBOARD SCANNER 18V BOOSTER VIN 4MA (MAX) 4.7 OHM 0.0188 V 75.2E-6 W CRITICAL
49 8 =PP3V3_S4_TPAD 32
PLACE_SIDE=BOTTOM 49 8 =PP3V42_G3H_TPAD
49 8 =PP3V3_S4_TPAD R5704 BYPASS=U5701.49:50:11 mm

BYPASS=U5701.49:50:8 mm R5708 J5700 516S0689 30
2 1.5 1 BYPASS=U5701.49:50:5 mm 0 55560-0228 29

PP3V3_S3_PSOC 49 8 =PP3V3_S4_TPAD 1 2 PP3V3_TPAD_CONN M-ST-SM 28
MIN_LINE_WIDTH=0.50MM VOLTAGE=3.3V WS_KBD1
D
5%
1/16W
MF-LF
VOLTAGE=3.3V 1 C5704 1 C5705 1 C5706
5%
1/20W
MF 1
NOSTUFF
C5708
MIN_LINE_WIDTH=0.50MM 2 1
49 7
49 7 WS_KBD2 27 D
402 100PF 0.1UF 4.7UF 201
0.1UF 49 7 Z2_CS_L 4 3 Z2_KEY_ACT_L 7 49 49 7 WS_KBD3 26
1 5% 10% 20%
R5703 2 25V
NP0-CERM 2 6.3V
X5R
6.3V
2 X5R
10%
2 6.3V NC
6 5
NC 49 7 WS_KBD4 25
220K 0201 201 402
X5R
201 49 7 Z2_MOSI 8 7 PSOC_F_CS_L 7 49 49 7 WS_KBD5 24
5%
1/20W 49 7 Z2_MISO 10 9 PICKB_L 7 49 49 7 WS_KBD6 23
MF TPAD_5V_SW_S4
201 2 PLACE_NEAR=J5800.18:3MM 49 7 Z2_SCLK 12 11 PSOC_MISO 7 49 49 7 WS_KBD7 22
=PSOC_WAKE_L WS_KBD23
L5700 NC
14 13 PSOC_MOSI 7 49 49 7 WS_KBD8 21
42 OUT 7 49 FERR-120-OHM-1.5A 49 7 Z2_HOST_INTN 16 15 PSOC_SCLK 7 49 49 7 WS_KBD9 20
49 7 PICKB_L WS_KBD22 7 49
8 =PP5V_S4_TPAD 1 2 PP5V_S4_CUMULUS 18 17 =I2C_TPAD_SDA 44 49 7 WS_KBD10 19
49 BUTTON_DISABLE WS_KBD21 7 49 VOLTAGE=5V
0402-LF MIN_NECK_WIDTH=0.20MM 49 7 Z2_CLKIN 20 19 =I2C_TPAD_SCL 44 CAPS:INT 49 7 WS_KBD11 18
49 7 Z2_HOST_INTN WS_KBD20 7 49 TPAD_5V_SW_S4 MIN_LINE_WIDTH=0.50MM 22 21 17
49 WS_LEFT_SHIFT_KEY WS_KBD19 7 49
1 C5700 R57001 NC R5714 49 7 WS_KBD12
0.1UF 56.2 2 49 7 WS_KBD13 16
49 WS_LEFT_OPTION_KEY WS_KBD18 7 49
10% 220K 49 WS_KBD15_C 1
15
10V PLACE_NEAR=J5800.18:3MM 5% 49 7 WS_KBD14
2 X5R-CERM 1/20W 1%
MF 1/16W 49 7 WS_KBD15_CAP 14
0201
56
55
54
53
52
51
50
49
48
47
46
45
44
43
201 2 MF-LF
TPAD_5V_LDO 402 7 WS_KBD16_NUM 13
P2_5 PLACE_NEAR=J5800.18:3MM
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
WS_KBD17 12
L5707 R5715
10K
49 7
WS_KBD18 11
49 WS_CONTROL_KEY 1 P2_3 P2_2 42 WS_KBD17 7 49
FERR-120-OHM-1.5A 49 WS_KBD16N 1 2
49 7
49 7 WS_KBD19 10
49 7 Z2_KEY_ACT_L 2 P2_1 CRITICAL P2_0 41 WS_KBD16N 49 49 PP5V_S5RS4_CUMULUS 1 2 1%
9
1/16W WS_KBD20
SMC Manual Reset & Isolation
49 7
3 P4_7 OMIT P4_6 40 WS_KBD15_C 0402-LF MF-LF
NC 49
TPAD_5V_LDO 402 49 7 WS_KBD21 8
TPAD_VBUS_EN 4 P4_5 U5701 P4_4 39 WS_KBD14
70 IN
5 P4_3 P4_2 38 WS_KBD13
7 49
1 C5707 Left shift, option & control keys combined with power button cause SMC RESET# assertion. 49 7 WS_KBD22 7
NC CY8C24794 7 49
0.1UF Keys ANDed with PSoC power to isolate when PSoC is not powered. R5710 49 7 WS_KBD23 6
NC
6 P4_1 MLF P4_0 37 WS_KBD12 7 49
10%
10V PLACE_NEAR=J5800.18:3MM 1K 5
2 X5R-CERM No IPD on OE input pin PP3V3_S4 (symbol error). 42 41 OUT SMC_ONOFF_L 1 2 7 WS_KBD_ONOFF_L
49 7 PSOC_MISO 7 P3_7 (SYM-VER2) P3_6 36 WS_KBD11 7 49 0201 4
49 8 =PP3V42_G3H_TPAD 5%
8 35
49 7
49 7
PSOC_F_CS_L
PSOC_MOSI 9
P3_5
P3_3
337S2983 P3_4
P3_2 34
WS_KBD10
WS_KBD9
7 49
7 49
C5710
0.1UF
1
1/16W
MF-LF
402
49 7 WS_LEFT_SHIFT_KBD 3
2
49 7 WS_LEFT_OPTION_KBD
49 7 PSOC_SCLK 10 P3_1 P3_0 33 WS_KBD8 7 49
1 C5750 20%
C 49 7 Z2_MISO 11 P5_7 P5_6 32 WS_KBD7 7 49

0.1UF
10%
10V
CERM
402
2 49 7 WS_CONTROL_KBD 1
C
10
49 7 Z2_CS_L 12 P5_5 P5_4 31 WS_KBD1 7 49 2 16V
X7R-CERM PLACEMENT_NOTE=NEAR J5713
31
49 7 Z2_MOSI 13 P5_3 P5_2 30 WS_KBD2 7 49 VDD
0402
Z2_SCLK 14 P5_1 P5_0 29 WS_KBD3

49 7 7 49
U5750
23 P7_7
24 P7_0
25 P1_0
26 P1_2
27 P1_4
28 P1_6
15 P1_7
16 P1_5
17 P1_3
18 P1_1
F-RT-SM
19 VSS
22 VDD
THRML SLG4AP021 FF14A-30C-R11DL-B-3H

20 D+
21 D-
PAD 57
TQFN
49 8 =PP3V3_S4_TPAD 4 OE J5713
(IPD) CRITICAL
TP_PSOC_SCL WS_KBD4 7 49
1 IN_1
OUT_1 9 WS_LEFT_SHIFT_KEY 49 518S0752
49 7 WS_LEFT_SHIFT_KBD
TP_PSOC_SDA WS_KBD5 7 49 (IPD)
OUT_2 8 WS_LEFT_OPTION_KEY 49
7 TP_PSOC_P1_3 WS_KBD6 7 49 49 7 WS_LEFT_OPTION_KBD 2 IN_2
(IPD)
TP_ISSP_SCLK_P1_1 TP_ISSP_SDATA_P1_0 3 IN_3
OUT_3 7 WS_CONTROL_KEY 49
WS_CONTROL_KBD
ISSP SCLK/I2C SCL ISSP SDATA/I2C SDA 49 7
(IPD)
Pull-up in U5010.
R5701 Z2_CLKIN 7 49 OUT_ALL# 6 SMC_TPAD_RST_L OUT 42
USB_TPAD_P 1
24 2 96
26 USB_TPAD_R_P TP_P7_7
91 9
5% THRM
1/20W
MF
(PP3V3_S3_PSOC) GND PAD
WS_KBD15_C CAP_COMP_H CAP_COMP_L Q5736 Q5738 LED Current
11
201
R5702 1 C5702 1 C5703 1 C5701 Z 1 1 off off none
24 100PF 0.1UF 4.7UF
91 9 USB_TPAD_N 1 2 96
26 USB_TPAD_R_N 5% 10% 20% 1 0 1 on off source
2 25V
NP0-CERM 2 6.3V
X5R 2 6.3V
X5R
5%
1/20W 0201 201 402 0 1 0 off on sink
MF
201
BYPASS=U5701.22:19:5 mm CAPS:EXT CAPS:EXT CAPS:EXT
BYPASS=U5701.22:19:8 mm
BYPASS=U5701.22:19:11 mm R57401 R57381 R57361
10K 10K 10K 1 CAPS:EXT
B
Caps Lock LED Drive 5%
1/20W
MF
5%
1/20W
MF
5%
1/20W
MF S Q5736
B
TPAD_5V_NO_FET
201 2 201 2 201 2 NTZD3152P
2 SOT-563-HF
R5720 5V TPAD FET G
0 49 8 =PP3V3_S4_TPAD
1 2
5% MOSFET SiA413 CAPS:EXT CAPS:EXT CAPS:EXT D
All RC values are TBD 1/16W
MF-LF
402 CHANNEL P-TYPE 12V
1
R5730 1
R5732 R5734
1
CAPS:EXT 8
6
10K 10K 20K CAP_SOURCE
5% 5% 5% V+ CAPS:EXT MIN_LINE_WIDTH=0.2MM
5V TRACKPAD S4 FET TPAD_5V_FET RDS(ON) 29 mOhm @4.5V 1/20W 1/20W 1/20W MIN_NECK_WIDTH=0.1MM
CRITICAL MF MF MF U5730 R57371
Q5720 LOADING 16 mA (EDP) 2 201 2 201 2 201 LM393ADGKR 113
SIA413DJ CAP_VREF_L 6 MSOP 1%
7 1/20W
SC70-6L MF
8 =PP5V_S5_TPAD 49 WS_KBD15_C 5 201 2
7
WS_KBD15_CAP
S
7 49
D
PP5V_S5RS4_CUMULUS CAPS:EXT MIN_LINE_WIDTH=0.2MM

4
49
TPAD_5V_FET TPAD_5V_FET VOLTAGE=5V 2 MIN_NECK_WIDTH=0.1MM
Q5721 TPAD_5V_FET MIN_NECK_WIDTH=0.20MM 1 CAP_COMP_H R57391
C5722 1
MIN_LINE_WIDTH=0.50MM CAP_VREF_H 3
SSM3K15FV D 3 R57211 0.033UF
113
CAPS:EXT CAPS:EXT CAPS:EXT
G
1%
SOD-VESM-HF 220K 10%
GND 1/20W
5%
1/20W
16V
X5R
2
TPAD_5V_FET
1
R5731 1
R5733 R5735
1 MF
201 2
3
MF TPAD_5V_FET 402
10K 20K 10K 4
201 2 C5723 5% 5% 5% CAP_SINK
R5722 0.01UF
1/20W
MF
1/20W
MF
1/20W
MF
1 G S 2 P5VCUMULUS_EN_L 1
3.3K 2 P5VCUMULUS_SS 1 2 2 201 2 201 2 201 3
70 IN =P5VS4_TPAD_EN 5%
10%
D CAPS:EXT
1/20W
10V
MF
201 X5R CAPS:EXT Q5738
201 CAP_COMP_L_INV 1 G DMN3730UFB4
CRITICAL S DFN1006H4-3
Q5734
TPAD Buttons Disable BOM Options available to CSA 5 SSM3K15AMFVAPE D 3
A 49 BUTTON_DISABLE
PLACE THESE COMPONENTS CLOSE TO J5800
TPAD_5V:SW_S4
TPAD_5V:LDO_S4
Original implementation off PP5V_S4
PP5V_S5 LDO power in S4 only
VESM 2
PAGE TITLE
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB TPAD_5V:LDO_S5 PP5V_S5 LDO power
Q5701 D 6
KEYBOARD/TRACKPAD (1 OF 2)
SSM6N15FEAPE 1 G S 2 DRAWING NUMBER SIZE
SOT563 CAP_COMP_L
TABLE_BOMGROUP_HEAD

THE TPAD BUTTONS WILL BE DISABLE TABLE_BOMGROUP_ITEM
REVISION
R
2 G S 1
WHEN THE LID IS CLOSED TPAD_5V:SW_S4 TPAD_5V_SW_S4 4.18.0
LID OPEN => SMC_LID_LC ~ 3.42V TABLE_BOMGROUP_ITEM

42 41 IN SMC_LID TPAD_5V:LDO_S4 TPAD_5V_FET,TPAD_5V_LDO
LID CLOSE => SMC_LID_LC < 0.50V THE INFORMATION CONTAINED HEREIN IS THE
TABLE_BOMGROUP_ITEM

TPAD_5V:LDO_S5 TPAD_5V_NO_FET,TPAD_5V_LDO THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 57 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 =PP3V3_S0_TPAD
1
R5853
470K
5% J5815 PIN 4 IS GROUNDED
1/16W
MF-LF ON KEYBOARD BACKLIGHT FLEX
2 402 CRITICAL
50 41 OUT SMC_SYS_KBDLED J5815

AA07A-S010-VA1
F-ST-SM
1
R5854 12
4.7K 11
5%
D
1/16W
MF-LF
2 402 2 1 KBDLED_ANODE2 7 50
D
7 SMC_KBDLED_PRESENT_L 4 3
6 5
NC
8 7 KBDLED_ANODE1 7 50
10 9
13
14
516S0899
Keyboard Backlight Connector
C C
Keyboard Backlight Driver & Detection

B To detect Keyboard backlight, SMC will B
tristate and read SMC_SYS_KBDLED:
If LOW, keyboard backlight present

If HIGH, keyboard backlight not present
R5853 always stuffed, R5854 only

grounded when KB BL flex connected. R5856
0 SMC_SYS_KBDLED_R
50 41 IN SMC_SYS_KBDLED 1 2
5%
1/16W
MF-LF
NOSTUFF 8 =PP5V_S0_KBDLED 402 353S3472
8
OMIT_TABLE
1
R5857 CRITICAL CTRL
10K L5850 U5850 10
5%
1/16W
15UH-20%-740MA-0.42OHM 1 VIN LED 7 KBDLED_ANODE1 1 2 R5855
MF-LF MIN_LINE_WIDTH=0.25 MM
2 402
1 2 KBDLED_SW1
LT3591 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=35V
1%
1/16W KBD_BL:SANDWICH KBD_BL:SANDWICH KBD_BL:TBONE KBD_BL:TBONE
SMC_SYS_KBDLED_FILTER VLF403212MT-SM MIN_NECK_WIDTH=0.25 MM 3 SW DFN CAP 5 MF-LF
SWITCH_NODE=TRUE 402 CRITICAL CRITICAL CRITICAL CRITICAL
NOSTUFF NOSTUFF 1 C5850 4 SW CAP 6 KBDLED_CAP1 1 C5855 1 C5856 1 C5857 1 C5858
C5859 1UF MIN_LINE_WIDTH=0.25 MM 1.0UF 1.0UF 1.0UF 1.0UF
1
10UF
1
R5858 10% GND PAD MIN_NECK_WIDTH=0.2 MM 10% 10% 10% 10% PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
120K 2 10V 2 50V 2 50V 2 50V 2 50V
2
20% 5% X5R X5R X5R X7R X7R

10V 402-1 0603 0603 0805 0805
2 X5R 1/16W 353S1612 2 IC,DC/DC CVTR,BOOST,WHITE LED,1MHZ,DFN8 U5850,U5860 CRITICAL
0603 MF-LF
2 402
R5866
SMC_SYS_KBDLED_ANALOG 1
0 2
5% NOSTUFF
NOSTUFF 1/16W
MF-LF
A
1
R5859 402
353S3472
A
8
100K OMIT_TABLE SYNC_MASTER=D2_KEPLER SYNC_DATE=01/13/2012

5% CRITICAL CTRL PAGE TITLE
1/16W
MF-LF L5860 U5860 10 KEYBOARD/TRACKPAD (2 OF 2)
2 402 15UH-20%-740MA-0.42OHM 1 VIN LED 7 50 7 KBDLED_ANODE2 1 2 R5865
MIN_LINE_WIDTH=0.25 MM DRAWING NUMBER SIZE
1 2 KBDLED_SW2 LT3591 MIN_NECK_WIDTH=0.2 MM 1%
1/16W KBD_BL:SANDWICH KBD_BL:SANDWICH KBD_BL:TBONE KBD_BL:TBONE 051-9589 D
VLF403212MT-SM
SWITCH_NODE=TRUE
3 SW DFN CAP 5
VOLTAGE=35V
MF-LF
402 CRITICAL CRITICAL CRITICAL CRITICAL
Apple Inc. REVISION
1 C5860 4 SW CAP 6 KBDLED_CAP2 1 C5865 1 C5866 1 C5867 1 C5868 R
4.18.0
1UF MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM 1.0UF 1.0UF 1.0UF 1.0UF NOTICE OF PROPRIETARY PROPERTY: BRANCH
10% GND PAD 10% 10% 10% 10%
10V 50V 50V 50V 50V
2 X5R 2 X5R 2 X5R 2 X7R 2 X7R THE INFORMATION CONTAINED HEREIN IS THE
2
402-1 0603 0603 0805 0805 PROPRIETARY PROPERTY OF APPLE INC.

58 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 =PP3V3_S3_SMS
BYPASS=U5920.14:13:8 mm
D SMS SMS D
C5926 C5922
14
1 1
SMS SMS NOSTUFF
1
10UF 0.1UF 1 1
20% 10% VDD VDD_IO R5920 R5925
6.3V 6.3V
X5R 2 2 X5R NC 2 10K 10K
603 201 SMS NC U5920 5% 5%
1 NC 3 1/20W 1/20W SMS
BYPASS=U5920.14:13:8 mm R5924 LIS331DLH MF MF
10K LGA
201
2
201
2 R5923
5% 10 CS 8 SMS_I2C_SEL 0
1/20W RESERVED 1 2 =I2C_SMC_SMS_SDA BI 44
MF 15
201 CRITICAL 5%
2
SDO 7 SMS_ADDR_SELECT 1/20W
MF
42 41 OUT SMS_INT_L 11 INT1 SDA/SDI/SDO 6 I2C_SMC_SMS_SDA_R 201
TP_SMS_INT2 9 INT2 SCL/SPC 4 I2C_SMC_SMS_SCL_R SMS

GND SMS R5922
1 0
R5921
12
13
16
1 2 =I2C_SMC_SMS_SCL IN 44
10K
338S0687 5% 5%
1/20W
1/20W
MF MF
PLACEMENT_NOTE=See schematic for orientation. 201
2
201
SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd)

Desired orientation when SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)
placed on board bottom-side (view thru top):
NOTE: SDA and SCL have internal pull-ups to VDD_IO.
+Y
Front of system
+X
+Z (dn)
C C
Circle indicates pin 1 location when placed
in correct orientation
8 =PP3V3_S3_GYRO
GYRO GYRO GYRO

1 C5940 1 C5941 1 C5943
GYRO
0.1UF
10%
6.3V
2 X5R
201
10%
6.3V
2 X5R
201
0.1UF 10UF
20%
6.3V
2 CERM-X5R
0402-1
GYRO
1 (WRITE: 0XD0 READ: 0XD1)
R5944
10K
5% GYRO
15
VDD 16
1
1/20W
MF GYRO
2 201 RES/VDD VDD_IO
R5946
CS PU = I2C U5940 338S0927 = 8KHZ 1
0
2 =I2C_SMC_GYRO_SCL IN 44
INT ARE PUSH-PULL

AP3GDL8B 5%
LGA 1/20W
MF
GYRO_CS 5 CS SCL_SPC 2 I2C_SMC_GYRO_SCL_R 201
B TP_IRQ_GYRO_INT2_L
TP_GYRO_SYNC
6
8
DRDY/
INT2
DEN
SDA_SDI_SDO 3
SDO_SA0 4
I2C_SMC_GYRO_SDA_R GYRO
R5947
B
CRITICAL 0
7 INT1 9 1 2 =I2C_SMC_GYRO_SDA BI 44
TP_IRQ_GYRO_INT1_L RES0
5%
14 PLLFILT RES1 10 1/20W
MF
RES2 11 201
RES3 12
GND
13
PLLFILT_GYRO
GYRO
1 C5942
0.47UF
10%
2 6.3V
CERM-X5R
402 GYRO
PLLFILT_GYRO1 GYRO 1 C5945
0.01UF
R5945
1
10%
10V
10K 2 X5R-CERM
5% 0201
1/20W
MF
2 201
PAGE TITLE
DIGITAL ACCELEROMETER & GYRO

DRAWING NUMBER SIZE

REVISION
R
4.18.0
59 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
8 =PP3V3_SUS_ROM
1
R6101 C6100 1 CRITICAL
8
3.3K 0.1UF VDD
5% 20%
1/16W 10V
MF-LF CERM 2
2 402 402 U6100
64MBIT
SPI_MLB_CLK SOIC SPI_MLB_MOSI
43 42 IN 6 SCK SI 5 IN 42 43
SST25VF064C
SPI_MLB_CS_L OMIT
43 42 IN 1 CE* SPI_MLB_MISO
SPI_WP_L SO 2 OUT 42 43
3 WP*
43 20 7 IN SPIROM_USE_MLB 7 HOLD*
NOTE: If HOLD* is asserted VSS
4
ROM will ignore SPI cycles.
B B
PAGE TITLE
SPI ROM
DRAWING NUMBER SIZE

REVISION
R
4.18.0
61 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO CODEC
APPLE P/N 353S2355
L6201 U6201 CONSUMES 40MA MAX. FROM 1.5V RAIL
FERR-22-OHM-1A-0.065-OHM PP5V_AUDIO_HPAMP 53
=PP1V5_S0_AUDIO 1 2 PP1V5_S0_AUDIO_DIG
8 IN
0201 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
C6210 1 1
C6211
D 4.7UF
20%
4V
0.1UF
10%
6.3V
PP4V5_AUDIO_ANALOG IN 53 58 59
D
X5R-1 2 2 X5R
402 201 CRITICAL CRITICAL
1
C6214 1 1 C6213
C6219 0.1UF 10UF
10UF C6218 1 1 10% 20%
20%
C6217 16V 10V
GND_AUDIO_CODEC 16V 0.1UF 10UF X5R-CERM 2 2 X5R-CERM
59 58 54 53 2 0201 0402-1
TANT-POLY 10% 20%
24
46
25
16V
CRITICAL CRITICAL 2012-LLP 2 2 16V
9
PP4V5_AUDIO_ANALOG X7R-CERM TANT-POLY GND_AUDIO_CODEC
59 58 53 IN
C6221 1 1 C6220 VD VA_REF VA_HP VA
0402 2012-LLP
GND_AUDIO_CODEC
53 54 58 59
15UF 15UF MIN_LINE_WIDTH=0.20MM

53 54 58 59
20% 20% VBIAS_DAC 29 VBIAS_DAC
1 4V 2 4V
R6210 X5R 2 X5R MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM HPOUT_L 38 MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM AUD_HP_PORT_L 7 54 58
0402 0402 CS4206_FP OUT
2.67K 44 VHP_FILT+
HPOUT_R 40 AUD_HP_PORT_R
1%
1/20W CS4206_FN
41 VHP_FILT- U6201 MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM OUT 7 54 58
2
MF
201 MIN_NECK_WIDTH=0.15MM CS4206B HPREF 39 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM AUD_HP_PORT_REF IN 58
QFN
59 IN AUD_DMIC_SDA1 2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35 AUD_LO1_L_P OUT 57 96
59 IN AUD_DMIC_SDA2 12 GPIO1/DMIC_SDA2 LINEOUT_L1- 34 AUD_LO1_L_N OUT 57 96 LFT SUBWOOFER AMP. SIG. SOURCE
/SPDIF_OUT2
TP_XCVR_ADC_RSTN 14 GPIO2 LINEOUT_R1+ 36 AUD_LO1_R_P OUT 57 96
RT. SUBWOOFER AMP. SIG. SOURCE
GPIO3 = SPKR AMP SHDN CONTROL 57 OUT AUD_GPIO_3 15 GPIO3 LINEOUT_R1- 37 AUD_LO1_R_N OUT 57 96
59 IN AUD_SENSE_A 13 SENSE_A LINEOUT_L2+ 31 AUD_LO2_L_P OUT 57 96

MIN_LINE_WIDTH=0.20MM LFT. SPKR AMP. SIG. SOURCE
MIN_NECK_WIDTH=0.15MM CS4206_FLYP LINEOUT_L2- 30 AUD_LO2_L_N OUT 57 96
58 53 8 IN =PP3V3_S0_AUDIO_DIG MIN_NECK_WIDTH=0.15MM CS4206_FLYC LINEOUT_R2+ 32 AUD_LO2_R_P OUT 57 96
45 FLYP RT. SPKR AMP. SIG. SOURCE
LINEOUT_R2- 33 AUD_LO2_R_N
C6222 1 1 C6223 43 FLYC OUT 57 96
C6216 1 1 C6226 15UF 15UF 42 FLYN

20% 20%
1UF 0.1UF 4V 4V
MICBIAS 16 TP_AUD_CODEC_MICBIAS
10% 10% X5R 2 2 X5R
10V 6.3V 0402 0402 MIN_LINE_WIDTH=0.20MM
2 2 MIN_NECK_WIDTH=0.15MM
X5R
402-1
X5R
201 CS4206_FLYN
3 VL_HD CRITICAL MIN_LINE_WIDTH=0.20MM
C MIN_LINE_WIDTH=0.20MM
1 VL_IF
VCOM 28 CS4206_VCOM
C
LINEIN_L+ 21 NO_TEST=TRUE NC_AUD_LI_P_L NC
92 17 IN HDA_BIT_CLK 6 BITCLK
LINEIN_C- 22 NO_TEST=TRUE NC_AUD_LI_REF NC
92 17 IN HDA_SYNC LINEIN_R+ 23 NO_TEST=TRUE NC_AUD_LI_P_R NC
R6211 10 SYNC
22
92 17 HDA_SDIN0 1 2 92 AUD_SDI_R 8 SDI MICIN_L+ 18 AUD_MIC_INL_P 58 96
IN IN
EXT MIC CODEC INPUT
5% 5 SDO MICIN_L- 17 AUD_MIC_INL_N IN 58 96
1/20W
MF MICIN_R+ 19
201 11 RESET*
92 17 OUT HDA_SDOUT MICIN_R- 20
92 17 IN HDA_RST_L TP_AUD_MIC_INP_R
TP_AUD_SPDIF_IN 47 SPDIF_IN
VREF+_ADC 27 CS4206_VREF_ADC NC
AUD_SPDIF_OUT 48 SPDIF_OUT MIN_LINE_WIDTH=0.20MM TP_AUD_MIC_INN_R
DMIC_SCL 4 AUD_DMIC_CLK_R R6241

0
1 2 AUD_DMIC_CLK OUT 59
5%
DGND THRM_PAD AGND 1/16W
MF-LF
402
49
26
1 1
C6224 C6225
1UF 10UF
20% 20%
16V 2 2 16V
TANT TANT-POLY
0603-SM 2012-LLP
R6220
B 58 7 OUT AUD_SPDIF_OUT_JACK 1
33 2
B
5% 59 58 54 53 GND_AUDIO_CODEC MIN_NECK_WIDTH=0.15MM
1/16W VOLTAGE=0V
MF-LF
402
4.5V POWER SUPPLY FOR CODEC NOTES ON CODEC I/O

DIFF FSINPUT= 2.45VRMS
APPLE P/N 353S2456 SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
L6202 MIN_LINE_WIDTH=0.20MM
FERR-22-OHM-1A-0.065-OHM MIN_NECK_WIDTH=0.15MM DAC2/3 FSOUTPUTSE= 1.34VRMS
VOLTAGE=5V
15" MBP: PLACE XW6201 NEAR 5V SOURCE 1 2 PP5V_AUDIO_HPAMP 53
0201
L6200 MIN_LINE_WIDTH=0.20MM MIN_LINE_WIDTH=0.20MM

XW6201
SM
FERR-22-OHM-1A-0.065-OHM MIN_NECK_WIDTH=0.15MM
VOLTAGE=5V
U6200 MIN_NECK_WIDTH=0.15MM
VOLTAGE=4.5V
TPS71745
=PP5V_S4_AUDIO 1 2 PP5V_S4_AUDIO_XW 1 2 4V5_REG_IN 6 SON 1 PP4V5_AUDIO_ANALOG
59 8 IN IN OUT OUT 53 58 59
MIN_NECK_WIDTH=0.20MM 0201 CRITICAL
VOLTAGE=5V R6200 4V5_REG_EN 4 EN NR/FB 3 4V5_NR
2.2K
58 53 8 IN =PP3V3_S0_AUDIO_DIG 1 2
A 5%
1/20W
MF 1
C6200
GND
2
NC 5
CRITICAL
C6202 1 1
CRITICAL
C6203 SYNC_MASTER=D2_CARA SYNC_DATE=03/16/2012 A
201 PAGE TITLE
0.1UF 1.0UF
2
1UF
10%
10V
X5R
1
C6201
1UF
10%
XW6200
SM
10%
16V
X5R-CERM 2
20%
10V
2 X5R-CERM
AUDIO: CODEC/REGULATOR
1 2 DRAWING NUMBER SIZE
402 10V 0201 0201-1
2 X5R
402
GND_AUDIO_CODEC 53 54 58 59 REVISION
R
4.18.0
PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5 NOTICE OF PROPRIETARY PROPERTY: BRANCH
62 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
58 53 7 IN AUD_HP_PORT_L OUT
CRITICAL
C6300 1
B 0.1UF
10%
6.3V
B
X5R 2
201
1
R6302
10K
NC AUD_HP_ZOBEL_L 1%
1/20W
MF
R63001 2 201
39
5%
1/20W
MF
201 2
59 58 53 IN GND_AUDIO_CODEC
R63101
39
5%
1/20W
MF
201 2
1
R6312
10K
1%
NC AUD_HP_ZOBEL_R 1/20W
MIN_LINE_WIDTH=0.30MM MF
CRITICAL 2 201
C6310 1
0.1UF
10%
6.3V 2
X5R
201
58 53 7 IN AUD_HP_PORT_R OUT
A SYNC_MASTER=D2_CARA SYNC_DATE=03/16/2012 A
PAGE TITLE
AUDIO: HEADPHONE FILTER

DRAWING NUMBER SIZE

REVISION
R
4.18.0
63 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
B B
PAGE TITLE
AUDIO: IV SENSE
DRAWING NUMBER SIZE

REVISION
R
4.18.0
64 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
B B
PAGE TITLE
AUDIO: IV SENSE FILTER

DRAWING NUMBER SIZE

REVISION
R
4.18.0
65 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
57 9 PP5V_S0_AUDIO_AMP_L
CRITICAL
1
CRITICAL CRITICAL
C6612
47UF
L6610 C6613 20%
6.3V 2 PLACE_NEAR=U6610.A1
FERR-1000-OHM 0.01UF TANT-POLY 1 C6611
CASE-A4
AUD_LO2_L_P 1 2
AUD_SPKRAMP_LIN_P 1 2 0.1UF
A1
96 53 IN 96
10%
0402
NO_TEST=TRUE CRITICAL 16V
CRITICAL 10%
2 X7R-CERM
L6611 50V PVDD 0402
4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375) C6614 X7R-CERM
APN: 353S2888 & 353S2958

FERR-1000-OHM 0.01UF 0402 U6610
AUD_LO2_L_N 1 2
AUD_SPKRAMP_LIN_N 1 2
NO_TEST=TRUE MAX98300 SPKRCONN_L_OUT_P
D GAIN = +3 DB
1ST ORDER FC (L&R) = NOM 569 HZ
96 53 IN
0402
CRITICAL
96
NO_TEST=TRUE
10%
96 SPKRAMP_LIN_P A3 IN+
B3 IN-
WLP
OUT+ B1
OUT 7 59 96
D
50V
96 SPKRAMP_LIN_N OUT- C1
1ST ORDER FC (SUB) = NOM 9 HZ X7R-CERM NO_TEST=TRUE
0402
57 AUD_SPKRAMP_SHUTDOWN_L C2 SHDN* GAIN C3 SPKR_L_GAIN

SPKRCONN_L_OUT_N OUT 7 59 96
B2 NC MIN_LINE_WIDTH=0.40 MM
L6601 MIN_NECK_WIDTH=0.10 MM
FERR-1000-OHM 1 1
R6600 R6610
53 IN AUD_GPIO_3 1 2 100K 100K
5% PGND 5%
0402 1/16W 1/16W
CRITICAL
A2
MF-LF MF-LF
402 402
2 2
57 9 PP5V_S0_AUDIO_AMP_R PLACE_NEAR=U6620.A1
CRITICAL 1
1
C6621
CRITICAL C6622 0.1UF
L6620 C6623 47UF 10%
A1
FERR-1000-OHM 16V
0.01UF 20% CRITICAL 2 X5R-CERM
6.3V 2
1 2 1 2 0201
96 53 IN AUD_LO2_R_P 96 AUD_SPKRAMP_RIN_P POLY-TANT PVDD
NO_TEST=TRUE 2012-LLP
0402 SPKRCONN_R_OUT_P
CRITICAL 10%
CRITICAL
U6620 MIN_LINE_WIDTH=0.40 MM
OUT 7 59 96
C L6621
FERR-1000-OHM
C6624
0.01UF
50V
X7R-CERM
0402
96
NO_TEST=TRUE
SPKRAMP_RIN_P A3 IN+
MAX98300
WLP
OUT+ B1
SPKRCONN_R_OUT_N OUT
7 59 96
C
96 53 AUD_LO2_R_N 1 96
2 AUD_SPKRAMP_RIN_N 1 2
IN
NO_TEST=TRUE 96 SPKRAMP_RIN_N B3 IN- OUT- C1
0402
10% NO_TEST=TRUE
CRITICAL 50V
X7R-CERM
57 AUD_SPKRAMP_SHUTDOWN_L C2 SHDN* GAIN C3 SPKR_R_GAIN
0402
B2 NC
NOSTUFF R66201
R6601 1 100K
100K PGND 5%
57 9 PP5V_S0_AUDIO_AMP_R 5% 1/16W
A2
1/20W MF-LF
MF 402 2
201 2
PLACE_NEAR=U6630.C2
1 CRITICAL 1 CRITICAL 1
C6631
CRITICAL C6635 C6632
CRITICAL 47UF 47UF 0.1UF
L6630 C6633 20% 20% 10%
16V
C2
FERR-1000-OHM 2 6.3V 2 6.3V 2 X5R-CERM
0.22UF POLY-TANT POLY-TANT CRITICAL 0201 SPKRCONN_SR_OUT_P
1 2 1 2
2012-LLP 2012-LLP VDD OUT 7 59 96
96 53 IN AUD_LO1_R_P 96 AUD_SPKRAMP_RSUBIN_P RSUBIN_P MIN_LINE_WIDTH=0.40 MM
0402
NO_TEST=TRUE NO_TEST=TRUE U6630 MIN_NECK_WIDTH=0.10 MM
10% SSM2375
16V WLCSP
CERM B1 C3
402
IN+ OUT+
A1 B3
CRITICAL IN- OUT-
CRITICAL NO_TEST=TRUE
L6631 C6634 A2 A3
FERR-1000-OHM 57 AUD_SPKRAMP_SHUTDOWN_L SD* GAIN TP_SWR_GAIN SPKRCONN_SR_OUT_N OUT 7 59 96
0.22UF MIN_LINE_WIDTH=0.40 MM
B2 MIN_NECK_WIDTH=0.10 MM
1 2 1 2
96 53 IN AUD_LO1_R_N 96 AUD_SPKRAMP_RSUBIN_N RSUBIN_N EDGE
NO_TEST=TRUE
0402
10%
GND
C1
16V
CERM
402
B B
57 9 PP5V_S0_AUDIO_AMP_L
CRITICAL 1 CRITICAL PLACE_NEAR=U6640.C2

CRITICAL C6645 1 CRITICAL
L6640 C6643 47UF C6642 1
C6641
FERR-1000-OHM 0.22UF 20% 47UF 0.1UF
2 6.3V 20% 10%
1 2 1 2 16V SPKRCONN_SL_OUT_P
AUD_LO1_L_P AUD_SPKRAMP_LSUBIN_P LSUBIN_P POLY-TANT
C2
96 53 IN 96 2 6.3V 2 X7R-CERM OUT 7 59 96
NO_TEST=TRUE NO_TEST=TRUE 2012-LLP POLY-TANT CRITICAL
0402 0402
10%
2012-LLP VDD MIN_LINE_WIDTH=0.40 MM
16V
CERM
U6640
402 SSM2375
WLCSP
CRITICAL B1 C3
CRITICAL IN+ OUT+
L6641 C6644 A1 B3
FERR-1000-OHM IN- OUT-
0.22UF
OUT 7 59 96
1 2 A2 A3
57 AUD_SPKRAMP_SHUTDOWN_L TP_SWL_GAIN
1 2
96 53 IN AUD_LO1_L_N 96 AUD_SPKRAMP_LSUBIN_N LSUBIN_N SD* GAIN MIN_LINE_WIDTH=0.40 MM
NO_TEST=TRUE NO_TEST=TRUE SPKRCONN_SL_OUT_N MIN_NECK_WIDTH=0.10 MM
0402
10% B2
16V
EDGE
CERM
402
GND
C1
PAGE TITLE
AUDIO: SPEAKER AMP

DRAWING NUMBER SIZE

REVISION
R
4.18.0
66 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
59 53 PP4V5_AUDIO_ANALOG
58 53 8 =PP3V3_S0_AUDIO_DIG PORT B LEFT(HEADSET MIC) AUDIO JACK: HP CONNECTOR WITH MIKEY & CHS
HP=80HZ, LP=10.63KHZ
1C6795 1 C6794 1 C6755
R6762 1
1.0UF 1.0UF 1.0UF
10K 20%
10V
20%
10V
20%
10V
I2C PULLUPS ON SOUTHBRIDGE PAGE 5% 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM
1/20W 0201-1 0201-1 0201-1 MIKEY 1A
MF
R6757 201 2 APN:353S2640
=I2C_MIKEY_SCL 1
33 2
MIKEY ADDRESS: WRITE=72H, READ=73H
44 IN
5%
L6754 MIN_LINE_WIDTH=0.20MM
A2
FERR-22-OHM-1A-0.065-OHM MIN_NECK_WIDTH=0.15MM
R6758 1/20W
MF
VOLTAGE=3.42V
D 44 BI =I2C_MIKEY_SDA 1
33 2
201 AVDD
U6751
8 =PP3V42_G3H_AUDIO 1
0201
2 PP3V42_GH3_AUDIO_LC
D
5%
1/20W CD3282A1
MF WCSP CRITICAL
201 1 C6793 1 C6792 1 C6790
58 AUDIO_SCL C3 SCL MICBIAS C1 HS_MIC_BIAS NO_TEST=TRUE
1.0UF 1.0UF 1.0UF L6701
20% 20% 20% PLACE_NEAR=U6750.A1 FERR-33-OHM-0.8A-0.09-OHM
58 AUDIO_SDA B3 SDA DETECT B1 HS_SW_DET 2
10V
2
10V
2
10V 1 C6754 AUD_CONN_MIC
X5R-CERM X5R-CERM X5R-CERM 7 US_HS_MIC 1 2
0201-1 0201-1 0201-1 0.1UF
19 AUD_I2C_INT_L D3 INT* BYPASS D1 HS_RX_BP 10% 0201
OUT 16V
2 X5R-CERM
CRITICAL
AUD_IPHS_SWITCH_EN A3 ENABLE MIKEY 0201
25 IN
R67541 L6700
HS_HDET A1 HDET 1K 59 58 54 53 GND_AUDIO_CODEC 120-OHM-25%-1.3A
NOSTUFF NO_TEST=TRUE 5% 1 2
US_HS_GND AUD_CONN_SLEEVE_XW
C2 DGND
D2 AGND
1/20W 58 7 OUT
B2
R6761 CS MF MIN_LINE_WIDTH=0.4MM
0402
A1
201 2 MIN_NECK_WIDTH=0.2MM
47K 1 C6756 MIN_NECK_WIDTH=0.06MM
59 IN AUD_PORTA_DET_L 1 2
R6755 1
0.01UF VDD CRITICAL
5% 100K 10%
1/20W
MF
5% 2 10V
X5R-CERM
U6750 L6702
201
1/20W
MF
0201 120-OHM-25%-1.3A
201 2 TS3A8235YFP CH_HS_GND 1 2 AUD_CONN_MIC_XW
WCSP 58 7 OUT
MIN_LINE_WIDTH=0.4MM MIN_LINE_WIDTH=0.4MM
CRITICAL MIN_NECK_WIDTH=0.06MM 0402 MIN_NECK_WIDTH=0.2MM
D4 RAMPI
NO_TEST=TRUE CHS_CLAMPI
59 58 54 53 GND_AUDIO_CODEC
D3
R6751 R6752 R6753 RAMPO
2
1K 1 1
2.2K 2 1
2.2K 2 CHS_CLAMPO
C4 CLAMPI
MIKEY
CRITICAL 5% 1% 1%
B4 APN:510S0009
C6752 MIKEY
R6750
1/20W
MF
1/20W
MF
1/20W
MF NO_TEST=TRUE
CLAMPO
0.1UF 2.2K 2
201 201 201 CRITICAL CRITICAL
96 53 OUT AUD_MIC_INL_P
1 2 NO_TEST=TRUE HS_MIC_HI_RC 1 NO_TEST=TRUE HS_MIC_HI D2 MIC MIC1 B1 L6703 J6701
MIKEY MIKEY 5% MIKEY HS_MIC_LO D1 REF MIC2 C1 FERR-33-OHM-0.8A-0.09-OHM 51138-0274
10% CRITICAL 1/20W CRITICAL NO_TEST=TRUE AUD_CONN_SLEEVE F-ST-SM
R67561 C6751 C6791 C
C
6.3V MF 1 1 7 CH_HS_MIC 1 2 22
X5R
201 100K
1 C6750 201 1 C6758 10UF 10UF AUDIO_SCL A3 SCL 0201 CRITICAL 21
MIKEY 6800PF 27PF 20% 20% 58 IN
CRITICAL
5%
1/20W 10%
10V
MIKEY
5%
25V
10V
2 X5R-CERM 2 10V
X5R-CERM 58 BI AUDIO_SDA A4 SDA L6704
C6753 MF
201 2
2 X5R-X7R-CERM
0201 R6759
2 NP0-C0G
0201 58 54
0402-1 0402-1 A2 ADDR 120-OHM-25%-1.3A 1 2
0.1UF 0 53
59
GND_AUDIO_CODEC
AUD_HP_PORT_L 1 2 AUD_CONN_HP_LEFT 3 4
54 53 7 IN
GND1
GND2
1 2 1 2 MIN_LINE_WIDTH=0.3MM MIN_LINE_WIDTH=0.3MM
96 53 OUT AUD_MIC_INL_N 0402 5 6
GND MIN_NECK_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM
HS_MIC_LO_RC 5%
10%
6.3V
1/20W
MF
XW6751
SM
7 8
X5R 201 9 10
C2
B2
B3
C3
201 53 AUD_HP_PORT_REF 1 2 59
AUD_CONN_TIPDET_INV
OUT 11 12
R/C6750 FILTER TO ADDRESS OUT-OF-BAND PLACE_NEAR=U6750.D1
NOISE ISSUE SEEN ON EARLY HEADSETS 13 14
(SEE RADAR # 6210118)
IN US_HS_GND
R67601 IN CH_HS_GND
15 16
47K 17 18
5% 19 20
1/20W 59 58 54 53 GND_AUDIO_CODEC
MF 58 53 8 =PP3V3_S0_AUDIO_DIG
201 2
NOSTUFF AUD_SPDIF_OUT_JACK
23
53 7 OUT 24
59 58 54 53 GND_AUDIO_CODEC
CRITICAL
L6705
120-OHM-25%-1.3A
B 54 53 7 IN AUD_HP_PORT_R
1
0402
2
B
AUD_CONN_HP_RIGHT
I2C ADDRESSES CRITICAL
L6706
MIKEY U6751 READ 0111 0011 0X73 FERR-470-OHM
MIKEY U6751 WRITE 0111 0010 0X72 59 7 AUD_TYPEDET 1 2 AUD_CONN_TYPEDET
OUT
CHS U6750 READ 0111 0111 0X77 0201
CHS U6750 WRITE 0111 0110 0X76
PAGE TITLE
AUDIO: JACK
DRAWING NUMBER SIZE

REVISION
R
4.18.0
67 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CODEC OUTPUT SIGNAL PATHS
3-MIC CONNECTOR SPEAKER CONNECTOR HP=80HZ
FUNCTION VOLUME CONVERTER PIN COMPLEX MUTE CONTROL DET ASSIGNMENT
R6885 APN: 518S0627
HP/LINE OUT 0X02 (2) 0X02 (2) 0X09 (9,A) N/A 0X09 (B)
1
0 2
7 CON_DMIC_PWR
TWEETERS 0X04 (4) 0X04 (4) 0X0B (11) GPIO_3 N/A
SUB 0X03 (3) 0X03 (03) 0X0A (10) GPIO_3 N/A 59 8 =PP3V3_S0_AUDIO 5%
1/16W
SPDIF OUT N/A 0X08 (8) 0X10 (16) N/A 0X0C (A) MF-LF CRITICAL CRITICAL
402
R6884 J6801 J6802
0 FF14A-5C-R11DL-B-3H 78171-6006
OUT AUD_DMIC_SDA1 CON_DMIC_SDA1
CODEC INPUT SIGNAL PATHS 53 1 2 7 F-RT-SM M-RT-SM
5% 6 7
D FUNCTION
DMIC 1
CONVERTER
0X06 (6)
PIN COMPLEX
0X0E (D,E)
VREF
3V3
DET ASSIGNMENT
N/A
1/16W
MF-LF
402
NC
1
D
96 57 7 IN SPKRCONN_L_OUT_P 1
DMIC2 0X05 (5) 0X12 (12,C) 3V3 0X0C (12,C) R6886 2 96 57 7 IN SPKRCONN_L_OUT_N 2
SPDIF IN 0X07 (7) 0X0F (15) N/A N/A 0 3
53 OUT AUD_DMIC_SDA2 1 2 7 CON_DMIC_SDA2 59 7 IN SPKRCONN_L_ID 3
HEADSET MIC 0X06 (6) 0X0D (13,V22,B,LEFT) MIKEY MIKEY 4
5% 4
1/16W
MF-LF 5 96 57 7 SPKRCONN_SL_OUT_P 5
402 IN
SYSTEM INT AND GPIO LINES 96 57 7 IN SPKRCONN_SL_OUT_N 6
R6883 NC
7
FUNCTION INT GPIO 0
53 OUT AUD_DMIC_CLK 1 2 7 CON_DMIC_CLK 8
MIKEY ENABLE SATA4GP/GPIO 16
5%
MIKEY INTERRUPT PIRQ H GPIO 5 1/16W
MF-LF
PERIPHERAL DETECT PIRQ F GPIO 3 402
CRITICAL
J6803
78171-6006
M-RT-SM
PORT B DETECT(SPDIF DELEGATE) PORT A DETECT (HEADPHONES) 7
OUT AUD_SENSE_A SPKRCONN_R_OUT_P

59 53 96 57 7 1
IN
96 57 7 IN SPKRCONN_R_OUT_N 2
1
R6896 1
R6895 59 7 IN SPKRCONN_R_ID 3
20.0K 39.2K 4
1% 1%
1/16W 1/16W 96 57 7 IN SPKRCONN_SR_OUT_P 5
MF-LF MF-LF 59 53 8 =PP5V_S4_AUDIO
402 402 96 57 7 IN SPKRCONN_SR_OUT_N 6
2 2
AUD_PORTA_DET_L 58 AUD_PORTB_DET_L NC
SPEAKERID SPEAKERID
8
Q6897 D 6
Q6896 D 3 R68101 R6811
1
100K 100K
C SSM6N15FEAPE
SOT563
SSM6N15FEAPE
SOT563
1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
C
2 402
2 G S 5 G S 59 7 IN SPKRCONN_L_ID SPKRCONN_R_ID IN 7 59
1 4
AUD_OUTJACK_INSERT_L
59 IN R6812 1
R6813
1
100K 100K
1% 1%
AUD_TYPEDET_OD OUT 59 1/16W 1/16W
R6802 MF-LF
402 2
MF-LF
2 402 PORT C DETECT(SPEAKER MISMATCH)
100K 1 PP4V5_AUDIO_ANALOG
59 58 54 53 GND_AUDIO_CODEC 2 SPEAKERID SPEAKERID
5%
1/20W
1
R6801 59 53 OUT AUD_SENSE_A
MF
201
3 150K
1% SPEAKERID
Q6800 1/20W
MF R6816
D
2 201 SPEAKERID
DMC2400UV 100K 2
P-CHN
SOT563 1
R68941
G
5 AUD_TYPEDET IN 7 58 1% 10K
1/16W 1%
S
MF-LF 1/16W
402 MF-LF
402 2
R6803 4
59 53 8 =PP5V_S4_AUDIO
100K 1 PP4V5_AUDIO_ANALOG 53 58 59
59 58 53 PP4V5_AUDIO_ANALOG 2 AUD_TYPEDET_OD_INV SPEAKERID
NC AUD_PORTC_DET_L
5%
1/20W
1 C6810
MF
6 0.1UF
201 C6800 1 PLACE_NEAR=Q6800.4 10%
6.3V
2 X5R
0.1UF
D 10% 201 SPEAKERID
Q6800 6.3V
N-CHN
X5R 2 Q6896 D 6
DMC2400UV 201
G 2 AUD_TYPEDET_OD SSM6N15FEAPE
B SOT563
S
IN 59
SPEAKERID
CRITICAL
SPEAKERID
SOT563
B
U6800 L6802 SPEAKERID
MCP6514_POS 3 5 MCP6541T FERR-1000-OHM R6820 2 G S 1
1
GND_AUDIO_CODEC SC70-5 33
53 54 58 59
59 8 =PP3V3_S0_AUDIO 1 MCP6514_OUT 1 2 SPKR_MATCH_DRV_R 1 2 SPKR_MATCH_DRV
R6867 0402 5%
0 MCP6514_NEG 4 1/16W
1 2 AUD_IP_PERIPHERAL_DET OUT 19 2 MF-LF
402
5%
1
R6865 1/16W
MF-LF 59 53 8 =PP5V_S4_AUDIO
47K 402 EXTRACTION NOTIFICATION
5% SPEAKERID
1/20W
MF
2 201
R68141
274K 59 58 54 53 GND_AUDIO_CODEC
1
R6866 1%
1/16W
475K AUD_OUTJACK_INSERT_L MF-LF
1% OUT 59 402 2 SPEAKERID
1/20W
MF
AUD_TIPDET_FET1
R6817
2 201 45.3K2
1
APN:376S0613
1%
Q6803 SPEAKERID CRITICAL
SPEAKERID
1/16W
MF-LF
SSM6N15FEAPE
SOT563
D 6 Q6897 D 3
R68151 1 C6811
402 AUDIO CONNECTOR DETECT STATES
SSM6N15FEAPE 90.9K
SOT563 1% 4.7UF
1/16W 20% NOTHING SPDIF HEADPHONE
10V
MF-LF 2 X5R-CERM
402 2 0402 AUD_J1_TYPEDET_R 1 1 0
R6892 2 G S 1 5 G S 4 AUD_J1_TIPDET_R 0 1 1
CRITICAL
1.5K AUD_OUTJACK_INSERT_L 1 0 0
58 IN
AUD_CONN_TIPDET_INV
1 2 7 AUD_TIPDET_INV L6801 AUD_SENSE_A 1 20K/2.67K RDIV 39.2K/2.67K RDIV
1% FERR-33-OHM-0.8A-0.09-OHM
1/16W
MF-LF 1 2 AUD_TIPDET_FET2
A 402
1
C6860
0201
1 SYNC_MASTER=D2_CARA SYNC_DATE=03/16/2012 A
1UF C6891 PAGE TITLE
10% 25V
2 X5R 402 1UF
10%
2 X5R
25V
402
Alternate Parts AUDIO: JACK TRANSLATORS
TABLE_ALT_HEAD
DRAWING NUMBER SIZE

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
TABLE_ALT_ITEM
REVISION
353S3452 353S1286 U6800
NOM R6892-C6860 FC = 106Hz 59 58 54 53 GND_AUDIO_CODEC
MAXIM ALT TO MICROCHIP R
4.18.0
SSM6N15FE Vth = 0.8V to 1.5V NOTICE OF PROPRIETARY PROPERTY: BRANCH
SSM6N15FE IGSS = +/-1uA THE INFORMATION CONTAINED HEREIN IS THE
FLEX-SIDE RPULLDOWN = 100k (TB 49.9k in REV 3) THE POSESSOR AGREES TO THE FOLLOWING: PAGE
68 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
MagSafe DC Power Jack F6905
6AMP-32V-0.0095OHM
1 2 =PP18V5_DCIN_CONN 8
0603
TDM LEVEL SHIFT
7 PP18V5_DCIN_FUSE
CRITICAL MIN_LINE_WIDTH=1MM
VOLTAGE=18.5V
J6900
D WTB-PWR-M82
M-RT-SM
1
C6905
0.01UF
20%
D
1 2
50V
CERM =PP3V42_G3H_ONEWIREPROT 8
LAYOUT NOTE:
2 0603
TDM:MLB
3 7 TDM_ONEWIRE_MPM 1
C6908 =PP3V42_G3H_TDM
CRITICAL Q0220 NEEDS 10 SQ CM
4 0.1UF
8 K
D6970 OF 1 OZ CU FOR THERMAL
20%
5 CRITICAL 10V PLACEMENT_NOTE=PLACE NEAR U6900 and U6901 DDZ9694T
2 CERM
6 U6901 402 A SOD523 2 TDM:MLB
SMC_BC_ACOK_VCC TC7SZ08FEAPE 5 CRITICAL
SOT665
A
2 SMC_BC_ACOK IN 41 42
TDM:MPM TDM:MLB
TDM_RX_D
TDM:MLB
TDM_PD_BASE 1 Q6970
518S0508 4 ZXTN619MA
1
C6900
0.1UF
1
R69291
Y
B
1 R69771 R69751 TDM:MLB
1
R6973 3
DFN
22 2.21K 24.9K
20% 2.0K
1
10V 3
5% 1% VDD 1%
CERM 2 VCC 5% 1/20W 1/20W 1/20W
1/16W MF MF MF
402
U6900
MF-LF
402 2
201 2
TDM:MLB
201 2 U6970 2 201
MAX9940 SLG4AP030 TDM:MLB
SC70-5 R6976 TDFN
TDM_RX CRITICAL 3
7 ADAPTER_SENSE 5 EXT INT 4 SYS_ONEWIRE BI 41
SYS_TDM_ONEWIRE 1
22 2 TDM_ONEWIRE_MLB 2 IN_A OUT_C 6
TDM:MLB Q6971 1
41 BI MMBT2222AM3T5G
CRITICAL
5%
4 IN_B1
1
R6974 TDM:MLB SOT723
1/20W OUT_D1 3 6.34K R6972
1
2
MF 1%
NC GND 201
7 IN_B2 1/20W 54.9
OUT_D2 8 MF 1% TDM_PD_DS
R6912
2
3
1
2 201 1/20W
MF
22.1K Input impedance of 22.1K meets CRITICAL 2 201
1%
NC 1/20W sparkitecture requirements TDM:MLB TDM:MLB
MF
2 201 for 15" MBP design only GND
THRM
PAD R6971
1
R6970
1
12.1 12.1
9
1% 1%
Q6910 1/8W
MF-LF
1/8W
MF-LF
SI5419DU 2 805 2 805
1-Wire OverVoltage Protection
C The chassis ground will otherwise float and can
POWERPAK
TDM_PD_BASE_R C
send transients onto ADAPTER_SENSE when AC is 5A 1
R6910
connected. 100K
D
1 5%
S
5 1/20W
MF
C6912
G
1
2 201 When input voltage is 2V the FET will be off
4 0.047UF
10% blocking the leakage path and 22.1K can be
25V
2 X5R
0402
R6911 properly detected.
1
10K 2
5%
DCIN_ISOL_GATE_R 1/20W When input voltage is at 16V+, FET will
MF
201 conduct and power charger and 3.42V reg
DCIN_ISOL_GATE
8 =PP18V5_DCIN_ISOL
K
D6910
GDZT2R6.8
6.8V Zener GDZ-0201
A
R6920 CRITICAL
47 D6905
1 2 PP18V5_DCIN_CONN_R
MIN_LINE_WIDTH=0.6 mm BAT30CWFILM
1% MIN_NECK_WIDTH=0.25 mm SOT-323
1/3W VOLTAGE=18.5V
MF 1
BATTERY CONNECTOR
805
3.425V "G3Hot" Supply
B R6905
10
3 PPVIN_G3H_P3V42G3H
MIN_NECK_WIDTH=0.2 mm Supply needs to guarantee 3.31V delivered to SMC VRef generator
B
61 8 =PPBUS_G3H 1 2 PPBUS_G3H_R 2 VOLTAGE=18.5V
518-0376 5% MIN_NECK_WIDTH=0.25 mm P3V42G3H_BOOST
1/8W VOLTAGE=18.5V DIDT=TRUE
CRITICAL MF-LF
805
J6950
3
C6994 1
BAT-J5 NOSTUFF NOSTUFF NOSTUFF VIN BOOST 0.22UF CRITICAL

F-ST-TH C6990 1 C6991 1 C6992 1 C6993 1 C6996 1 C6997 1
U6990 10%
10V
L6995
4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 4.7UF LT3470AED CERM 2
12 POS 1 10% 10% 10% 10% 10% 10% 402 33UH-20%-0.39A-0.435OHM =PP3V42_G3H_REG
35V 35V 35V 35V 35V 35V DFN 8
13 POS 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 8 SHDN*
0603 0603 0603 0603 0603 0603 SW 4 P3V42G3H_SW 1 2
14 POS 3 MIN_LINE_WIDTH=0.5 mm Vout = 3.425V

BIAS 2 MIN_NECK_WIDTH=0.25 mm DP418C-SM
15 POS 4 7 NC CRITICAL SWITCH_NODE=TRUE

61 7 PPVBAT_G3H_CONN
NC DIDT=TRUE 100MA MAX OUTPUT
16 SCL 5 =SMBUS_BATT_SCL FB 1
NC 44
<Ra> (Switcher limit)
17 SDA 6 =SMBUS_BATT_SDA THRM
NC 44
GND PAD
18 SYS_DETECT 7 7 SYS_DETECT_L 1
C6995 R6995 1
9
NEG 22PF 348K
19 8 1%
5%
CRITICAL 1/20W
20 NEG 9 2
50V
MF
21 NEG 10 D6950 1
R6950 NP0-C0G-CERM
0201 201
2 1 C6999
10K
1
RCLAMP2402B 22UF
22 NEG 11 C6950 1 C6960 1 5%
1/16W
P3V42G3H_FB 20%
0.1UF 1UF SC-75
MF-LF <Rb> 2 6.3V
10% 10% X5R-CERM-1
25V 25V 2 402 603
X5R 2 X5R 2 R6996 1
402 603-1 200K
3
1%
1/20W
MF
201
2
A Vout = 1.25V * (1 + Ra / Rb)
PAGE TITLE
DC-In & Battery Connectors

DRAWING NUMBER SIZE

REVISION
R
4.18.0
69 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOSTUFF
CRITICAL CHGR_5V:LDO R7090
Q7080 R7092 MIN_NECK_WIDTH=0.25 mm
For Erp Lot6 spec (P5V1_BIAS) 1 0
IRF9395TRPBF 0 2 CHGR_DCIN 61
DIRECTFET-MC 61 CHGR_DCIN_D_R 1 2 P5V1_VIN P5V1_BOOST
MIN_NECK_WIDTH=0.25 mm DIDT=TRUE MF-LF 5% 402
MIN_LINE_WIDTH=0.5 mm MF-LF 5% 402 1/16W
1/16W
NC NC NC NC
3
C7090 1 C7094 1
CHGR_5V:LDO
NO STUFF 4.7UF VIN BOOST 0.22UF R7091
10
CRITICAL
2
1
7
For EMC Reverse-Current Protection 10%
35V U7090
10%
10V
L7095 1
0
2 PP5V1_CHGR_VDDP
FROM ADAPTER Inrush Limiter X5R-CERM 2 CERM 2 61
1 C7080 0805 LT3470A
DFN
402 33UH-20%-0.39A-0.435OHM
MIN_NECK_WIDTH=0.25 mm MF-LF 5% 402
1/16W
4.7UF MIN_LINE_WIDTH=0.5 mm
D
8 =PPDCIN_S5_CHGR 10%
PPDCIN_G3H_INRUSH 8 SHDN* SW 4 P5V1_SW 1 2
25V MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.5 mm

2 X5R-CERM MIN_NECK_WIDTH=0.25 mm BIAS 2 MIN_NECK_WIDTH=0.25 mm DP418C-SM CRITICAL CRITICAL
CRITICAL
D 1
C7085
1
R7085
0603 1
R7080
VOLTAGE=18.5V
NC
7 NC
SWITCH_NODE=TRUE
DIDT=TRUE
P5V1_BIAS <Ra>
1 C7098
10UF
1 C7099
10UF D
G
0.1UF 470K
1% 5%
100K FB 1
R7095 1 20% 20%
THRM 10V 10V
8 =PPDCIN_S5_CHGR_ISOL 10%
1/16W 1/16W
GND
1
C7095 681K 2 X5R 2 X5R
2
25V
MF-LF MF-LF PAD 1% Vout = 5.50V
3
X5R
402 402
22PF 1/20W
0603 0603
100MA MAX OUTPUT
9
402 2 2 5%
50V MF
2 201
CHGR_AGATE_DIV CHGR_SGATE_DIV NP0-C0G-CERM
0201
2
(Switcher limit)
MIN_LINE_WIDTH=0.3 mm MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm
1
P5V1_FB
R7081 <Rb>
R7086 1 62K
332K
1%
5%
1/16W
R7096 1
1/16W MF-LF 200K
CRITICAL MF-LF
2
402 1%
402 2 1/20W
D7005 (CHGR_AGATE) (CHGR_SGATE) Vout = 1.25V * (1 + Ra / Rb)
MF
201
BAT30CWFILM 2
SOT-323
1
R7005
20 R7021
3 61 CHGR_DCIN_D_R 1 2 (CHGR_DCIN)
10
5% 1 2
2 1/16W CRITICAL
ACIN pin threshold is 3.2V, +/- 50mV MF-LF 5%
4 2
402 1/16W 96 CHGR_CSI_R_P R7020
1
C7020 MF-LF
0.020
Divider sets ACIN threshold at 13.55V 0.047UF
402
0.5%
10%
Sparkitecture impedance is set by R6912 in 15" MBP 10V
1W
2 X5R-CERM R7022 96 CHGR_CSI_R_N MF-LF
30mA max load 0402 3 1
0612
10
1 2
PP5V1_CHGR_VDD R7001 PPDCIN_G3H_CHGR
MIN_LINE_WIDTH=0.2 mm 4.7 5% MIN_LINE_WIDTH=0.6 mm
70 8 =PP3V42_G3H_CHGR MIN_NECK_WIDTH=0.1 mm 1 2 61 PP5V1_CHGR_VDDP 1/16W MIN_NECK_WIDTH=0.25 mm CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
MF-LF
VOLTAGE=5.1V
5%
1/16W
MIN_NECK_WIDTH=0.2 mm 402
VOLTAGE=18.5V 1
C7030 1
C7031 1
C7032 1
C7033 1
C7034 1 C7035 1 C7036 1
C7037
MF-LF
VOLTAGE=5.1V
10UF 10UF 10UF 10UF 10UF 1UF 1UF 0.001UF
402 C7001 1 C7022 1 1 C7021 20% 20% 20% 20% 20% 10% 10% 10%
35V 35V 50V
1UF 0.1UF 0.1UF 2 35V 2 35V 2 35V 2 35V 2 35V 2 X5R 2 X5R 2 X7R-CERM
NO STUFF TANT-POLY TANT-POLY TANT-POLY TANT-POLY TANT-POLY
C R7012 1
C7002
1UF
10%
1
1
R7002
100K
10%
10V
X5R
402
2
10%
25V
X5R
402
2 2
10%
25V
X5R
402
CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM CASE-D2-SM 603 603 0402
C
1K 10V
X5R 2 5%
19
20
1% 402 1/16W
1/16W 61 MF-LF
MF-LF 402 5
402 2 GND_CHGR_AGND 2 VDD VDDP
R7000 12 VHST CRITICAL DCIN 2 61 CHGR_DCIN CRITICAL
0 D Max Current = 8A
R7010
1
IN SMC_RESET_L 1 2 CHGR_RST_L 13 SMB_RST_N
SGATE 26 CHGR_SGATE Q7030
130K 5% 44 IN =SMBUS_CHGR_SCL 11 SCL U7000 4 G RJK0332DPB-01 (L7030 limit)
1% 1/16W
=SMBUS_CHGR_SDA
AGATE 1 CHGR_AGATE 1
C7025
1/16W MF-LF 44 BI
10 SDA TQFN
0.22UF
LFPAK-SM
MF-LF 402 CSIP 28 94 CHGR_CSI_P f = 400 kHz
ISL6259
2 402 70 IN CHGR_VFRQ 4 VFRQ 10%
CSIN 27 94 CHGR_CSI_N 2
10V
CERM S
CHGR_CELL 6 CELL CRITICAL CRITICAL
402
L7030 TO SYSTEM
CHGR_ACIN 3 ACIN
BOOT 25 CHGR_BOOT DIDT=TRUE
1 2 3 4.7UH-20%-14.5A-9MOHM
F7040
UGATE 24 CHGR_UGATE GATE_NODE=TRUE DIDT=TRUE 8AMP-32V-0.006OHM
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
CHGR_ICOMP 5 ICOMP PHASE 23 CHGR_PHASE 1 2 1 2 =PPBUS_G3H 8 60
R7011
1
CHGR_VCOMP 7 VCOMP
MIN_NECK_WIDTH=0.2 mm PIME173T-SM
40.2K CHGR_VNEG 8
LGATE 21 CHGR_LGATE GATE_NODE=TRUE DIDT=TRUE SWITCH_NODE=TRUE 0603
1% VNEG MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm DIDT=TRUE
1/16W 1 CHGR_CSO_P 18 CHGR_BGATE
152S1466 CRITICAL
MF-LF R7015 94 CSOP BGATE 16
2 402 330K 94 CHGR_CSO_N 17 CSON 20V/V AMON 9 CHGR_AMON OUT 46
F7041
5% 8AMP-32V-0.006OHM
THRM_PAD
1/16W 36V/V BMON 15 CHGR_BMON OUT 46

MF-LF PPVBAT_G3H_CHGR_REG 1 2
1
C7050 =CHGR_ACOK
(AGND)
2 402 (OD) ACOK 14

OUT 42 45 MIN_LINE_WIDTH=0.6 mm OMIT_TABLE
PGND
1UF VOLTAGE=12.6V CRITICAL 0603
CHGR_VCOMP_R 10%
16V 5
1
C7040 1
C7045
2 X5R 68UF 0.001UF
29
22
402 10%
353S2392 CRITICAL 20%
C7015 1
2 16V
POLY-TANT
2
50V
X7R-CERM
220PF Q7035 CASE-D2E-SM 0402
10%
50V
4
RJK0305DPB CRITICAL CRITICAL
X7R-CERM 2
0402
LFPAK-HF
R7050 Q7055
0.005
B 1
R7042
0
1%
1W
MF
SI7137DP
SO-8
TO/FROM BATTERY B
5% R7016 1 XW7000
0612
S
1/16W 1 2 3 2 1 PPVBAT_G3H_CHGR_R
3.01K
3
MF-LF SM MIN_LINE_WIDTH=0.6 mm
D
4 3 PPVBAT_G3H_CONN
2 402 1%
1 2 (GND)
MIN_NECK_WIDTH=0.2 MM 7 60
5
1/16W VOLTAGE=12.6V MIN_LINE_WIDTH=0.6 mm
MF-LF C7055 1
C7056 1
C7057 1
1
402
2
PLACE_NEAR=U7000.29:1mm 1UF 0.1UF 0.01UF VOLTAGE=12.6V
G
10% 10% 10%
CHGR_VNEG_R 25V 16V 16V
X5R 2 X7R-CERM 2 X7R-CERM 2
4
603-1 0402 0402
1
C7016 (CHGR_CSO_P) R7051 2.2 1 2 96 CHGR_CSO_R_P
5% 1/16W MF-LF 402
470PF
10% (CHGR_CSO_N) R7052 0 1 2 96 CHGR_CSO_R_N
50V 5% 1/16W MF-LF 402
2 CERM
0402
(PPVBAT_G3H_CHGR_R) (PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)
CHGR_ICOMP_RC
1
C7042 C7011 1 1
C7000 C7005 1 C7026 1
NO STUFF
0.068UF 0.01UF 1UF 0.22UF 0.001UF CRITICAL
10% 10% 10% 10% 10%
2
10V
X5R-CERM
16V
X7R-CERM 2 2
10V
X5R
50V
X5R-CERM 2
50V
X7R-CERM 2 R7055
0402 0402 402-1 0603-1 0402 0.001
61 GND_CHGR_AGND 1%
MIN_LINE_WIDTH=0.2 mm 1W
MIN_NECK_WIDTH=0.2 mm MF
VOLTAGE=0V 0612
2 1
4 3
PAGE TITLE
PBus Supply & Battery Charger

DRAWING NUMBER SIZE

REVISION
R
4.18.0
70 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
8 =PPVIN_S0_VCCSAS0
8 =PP5V_S0_VCCSAS0
PLACE_NEAR=Q7100.2:1.5mm
VCCSAS0_BOOT_RC
MIN_LINE_WIDTH=0.3 mm CRITICAL CRITICAL
R7101 1
1
C7101 DIDT=TRUE C7119 1
C7120 1
C7121 1 1
C7122
2.2 10UF 10UF 10UF 0.1UF 1000PF
20% 20% 20% 10% 5%
5%
1/16W 2
10V
X5R 1
1
C7130 25V
X5R-CERM 2
25V
X5R-CERM 2
16V
X7R-CERM 2 2
25V
NP0-C0G
MF-LF
402
603 R7130 0.22UF 0603 0603 0402 402
2 0 10%
10V
5% 2 CERM
PP5V_S0_VCCSAS0_VCC 1/10W 402
MIN_LINE_WIDTH=0.6 mm MF-LF
MIN_NECK_WIDTH=0.2 mm 603
2
VOLTAGE=5V
19
20
VCC PVCC VCCSAS0_VBST
MIN_LINE_WIDTH=0.3 mm 376S0944
U7100 MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
2
CRITICAL
C =PVCCSA_EN 15
EN
ISL95870AH
UTQFN
BOOT 18
VCCSAS0_DRVH
Q7100
RJK0222DNS CRITICAL
CRITICAL
R7140
C
R7151 70 IN MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm 0.001
CPU_VCCSASENSE 1
1.62K
2 CPU_VCCSASENSE_DIV 10 CRITICAL 17 GATE_NODE=TRUE
1 HWSON L7100 1%
1W =PPVCCSA_S0_REG
89 13 IN FB UGATE DIDT=TRUE 1.0UH-7A MF-1
8 99
1% 0612
1/16W VCCSAS0_SREF 7
SREF PHASE 16 VCCSAS0_LL 7 1 2 PPVCCSA_S0_REG_R 2 1
MF-LF MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm
402
VCCSAS0_VO 12 1 MIN_NECK_WIDTH=0.2 mm PIMB053T-SM MIN_NECK_WIDTH=0.2 mm 4 3 6A Max Output
1 VO LGATE SWITCH_NODE=TRUE VOLTAGE=1.05V
R7147 DIDT=TRUE
152S1302 f = 300 kHz
41.2K VCCSAS0_OCSET 11
OCSET 6
1%
1/16W 14
R7153 MF-LF 70 OUT PVCCSA_PGOOD PGOOD
1.62K 2 402
VCCSAS0_RTN 1 2 VCCSAS0_RTN_DIV 4 VCCSAS0_DRVL
RTN 3 4 5
1% 13 MIN_NECK_WIDTH=0.2 mm
1/16W VCCSAS0_FSEL FSEL GATE_NODE=TRUE
MF-LF DIDT=TRUE
402 8
VCCSAS0_SET0 SET0
2 C7103 1
0.022UF VCCSAS0_SET1 9
XW7101 10%
SET1
SM 16V
2
X5R-X7R-CERM 1 6
1
0402 R7148 VID0
52.3K 5 (ENDIAN SWAP)
1%
1/16W
R7103 1 VID1
96 45 VCCSAS0_CS_P
MF-LF 0
2 402
1
C7102 5%
96 45 VCCSAS0_CS_N
1/16W
2.2UF
10%
MF-LF
402
GND PGND
R7141 1
16V 2 1.5K
2
2 X5R
R7150 603 1%
1/16W
82.5K MF-LF C7140
1 2 402 2
1000PF
1%
1/16W 89 13 IN CPU_VCCSA_VID<1> 2 1
MF-LF
402 CPU_VCCSA_VID<0>
B 1 C7106
10PF
1
R7154
4.64K
1
R7152
4.64K
1 C7105
10PF VCCSAS0_SET_R
89 13 IN 5%
25V
NP0-C0G
1
R7142 B
1% 1% 402 1.5K
5%
50V 1/16W 1/16W 5%
50V 1 1% OCP = R7141 x 8.5uA / R7140
2 C0G-CERM MF-LF MF-LF 2 C0G-CERM R7149 1/16W
0402 2 402 2 402 0402 499K (VCCSAS0_OCSET)
MF-LF
OCP = 8.5A
1% 2 402
1/16W
MF-LF (VCCSAS0_VO)
2 402
XW7100
SM
VCCSAS0_AGND 1 2
VOLTAGE=0V
INTEL TABLE:
VID1 VID0 Voltage fb = (R7151+R7152)/R7152 = 1.349 and Vref = 0.5;
VID1=1, VIC0=1:
0 0 0.9V
Vout<1,1> = Vref x fb;
1 0 0.8V VID1=0, VID0=1:
Vout<0,1> = Vref x (1+R7147 / (R7148 + R7149 )) x fb
0 1 0.725V
VID1=1, VID0=0
Vout<1,0> = Vref x (1+ (R7147 + R7148) / R7149 )) x fb
1 1 0.675V
VID1=0, VID0=0
Vout<0,0> = Vref x (1+ (R7147 / (R7148 + R7149 // R7150 )) x fb
PAGE TITLE
System Agent Supply

DRAWING NUMBER SIZE

REVISION
R
4.18.0
71 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
63 8 =PP5V_S4_REG
8 =PPVIN_S5_P5VP3V3
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE

CRITICAL CRITICAL CRITICAL CRITICAL
=PP5V_S5_LDO 8
C7240 1
C7242 1 1
C7241 1
C7270 C7280 1
C7282 1 1
C7281 1
C7283
68UF 68UF 1UF 0.001UF C7200 1
VOUT = 5V 68UF 68UF 1UF 0.001UF
20% 20% 10% 10% 20% 20% 10% 10%
16V 2 16V 2 2
25V
2
50V 1UF 100MA MAX OUTPUT 16V 2 16V 2 2
25V
2
50V
POLY-TANT POLY-TANT X5R X7R-CERM 10% POLY-TANT POLY-TANT X5R X7R-CERM
CASE-D2E-SM CASE-D2E-SM 603-1 0402 25V CASE-D2E-SM CASE-D2E-SM 603-1 0402
X5R 2
603-1 1
C7205
P5VP3V3_VREG3 10UF
20%
6.3V
2
P5VP3V3_VREF2 X5R
603
63 8 =PP5V_S4_REG SKIP_5V3V3:INAUDIBLE =PP3V3_S5_REG 8
R72011
23
29
22
13
VOUT = 5.0V C7201 1 1
C7203 VOUT = 3.3V
2
SKIP_5V3V3:AUDIBLE
0
1
0.22UF 2.2UF
R72001 5%
V5SW
VIN
VREG5
VREG3
VREF2
11A MAX OUTPUT 1 152S0688 MIN_LINE_WIDTH=0.6 MM
0
1/20W 10%
10V
20%
10V MIN_LINE_WIDTH=0.6 MM CRITICAL 152S0754 10A MAX OUTPUT
MIN_NECK_WIDTH=0.2 MM MF 2 2 MIN_NECK_WIDTH=0.2 MM
CRITICAL 5% 201 2
CERM X5R-CERM
C7264 1
Q7260 CRITICAL
F = 400 KHZ 1
C7224 1/20W 402 402
F = 400 KHZ
CRITICAL
L7220 CRITICAL 0.1UF MF
201 2 6 SKIPSEL1
0.1UF
10%
RJK0214DPA
2 WPAK2
L7260
NOSTUFF 1.0UH-21A-0.006OHM 10%
CRITICAL 50V 1.0UH-22A CRITICAL
PCMB103T-1R0MS Q7220 2
50V
R7244 1 P5VP3V3_SKIPSEL 19 SKIPSEL2 X7R 2
PCMC063T-SM
1
C7253 1
C7271 CSD58872Q5D
X7R
U7201 R7263
603-1
C7272 1
C7293 1
C 20%
150UF 0.001UF
10%
2
1 VIN SON5X6
TG 3
603-1
P5VS4_TG
1
5%
1/16W
14 OCSEL
QFN
EN 12 =P5VS5_EN IN 70
1
0
2 P3V3S5_TG
0.001UF
10%
150UF
20%
C
TPS51980
50V 50V
2 6.3V 2 X7R-CERM MIN_LINE_WIDTH=0.6 MM MF-LF MIN_LINE_WIDTH=0.6 MM
1 X7R-CERM 2 6.3V 2
POLY-TANT P5VS4_VBST 31 VBST1 VBST2 26 P3V3S5_VBST 5% POLY-TANT
2
MIN_NECK_WIDTH=0.2 MM 402 MIN_NECK_WIDTH=0.2 MM
CASE-B2-SM 0402 P5VS4_VSW 6 VSW DIDT=TRUE
2
DIDT=TRUE DIDT=TRUE 1/16W DIDT=TRUE
0402 CASE-B2-SM
CRITICAL CRITICAL CRITICAL MIN_LINE_WIDTH=0.6 MM
7 TGR 4
MF-LF GATE_NODE=TRUE
7
CRITICAL
MIN_NECK_WIDTH=0.2 MM P5VS4_DRVH 1 DRVH1 DRVH2 24 P3V3S5_DRVH 402
C7254 1 C7252 1
C7250 1
DIDT=TRUE
GATE_NODE=TRUE DIDT=TRUE DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 MM
1
C7290 1
C7292
150UF 330UF 10UF P5VS4_LL 32 SW1 SW2 25 P3V3S5_LL 10UF 330UF
PLACE_NEAR=L7220.1:3MM
20% 20% 20%
20%
10V NO STUFF MIN_LINE_WIDTH=0.6 MM SWITCH_NODE=TRUE DIDT=TRUE DIDT=TRUE SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6 MM NO STUFF 6.3V
20%
6.3V 2 6.3V 2 2 MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM 2 2 6.3V
POLY-TANT X5R 1 BG 5 P5VS4_DRVL P3V3S5_DRVL 6 X5R
CASE-B2-SM
POLY-TANT
CASE-D3L-SM 805 R7299 MIN_LINE_WIDTH=0.6 MM GATE_NODE=TRUE DIDT=TRUE
30 DRVL1 DRVL2 27
DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 MM
R7298 1 603
POLY-TANT
CASE-D3L-SM
1 MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM 10
5% PGND P5VS4_CSP1 7 CSP1 CSP2 18 P3V3S5_CSP2 5%
1/10W 1/10W
P5VS4_CSN1 8 CSN1 CSN2 P3V3S5_CSN2
9
17
MF-LF
603
C7218 C7288 3 4 5
MF-LF
603
2 2
0.1UF 0.1UF
P3V3S5_RF
11 MODE RF 3
P5VS4_SNUBR 1 2 1 2 P3V3S5_SNUBR
MIN_LINE_WIDTH=0.6 MM P5VS4_VFB1 9 VFB1 VFB2 16 P3V3S5_VFB2 MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
10%
16V
P5VS4_COMP1 10 COMP1 COMP2 15 P3V3S5_COMP2 10%
16V
DIDT=TRUE
X7R-CERM
R7206 1
X7R-CERM
2 NO STUFF NO STUFF 2
0402
70 IN =P5VS4_EN 4 EN1 EN2 21 =P3V3S5_EN IN 70
0402
XW7222 C7299 1
P5VS4_PGOOD 5 P3V3S5_PGOOD
249K 1
C7298 XW7262
SM 0.0033UF R7247 70 OUT PGOOD1 PGOOD2 20
OUT 70 1%
R7246 0.001UF SM
1/16W
10% 3.24K 1.43K 10%
50V 1 2 GND THRM_PAD MF-LF
1 2 50V
1 X7R-CERM 2 402 2 X7R-CERM 1
2
0402 0402
28
33
1% 1%
P5VS4_VFB1_R 1/16W 1/16W P3V3S5_VFB2_R
2 2 R7256 1 MF-LF
1 R7236 1 1
R7238 R7239 1 MF-LF 1
R7216 2 2
3.92K
402
R7237 12.1K 12.1K 10K
402
3.83K
XW7220 XW7221 1% 10K 1% 1% 1% 1%
XW7260 XW7261
SM SM SM SM
1/16W 1% 1/16W 1/16W 1/16W 1/16W
1
R7220 1 1
MF-LF
402
1/16W
MF-LF
MF-LF
402 2
MF-LF
402
MF-LF
402
MF-LF
402 1 1
R7260 1
40.2K 2 2 2 2 2 23.2K
402
1%
1/16W P5VS4_CSP1_R
2
P5VS4_COMP1_R XW7200
SM
P3V3S5_COMP2_R P3V3S5_CSP2_R
1%
1/16W
MF-LF MF-LF
402 PLACE_NEAR=U7200.28:1MM 402
2 2
1
C7237 1 1 C7236 C7238 1 1
C7239
150PF 4700PF 4700PF 47PF
B 1
R7221
5%
50V
C0G-CERM
0402
2
10%
100V
2 CERM
402
10%
100V
CERM 2
402
2
5%
50V
CERM
402 R7261 1
B
10K (P5VP3V3_VREF2) (P5VP3V3_VREF2) 10K
1% 1%
1/16W 1/16W
MF-LF MF-LF
402 402
2 2
GND_5V3V3_AGND
VOLTAGE=0V
PAGE TITLE
5V / 3.3V Power Supply

DRAWING NUMBER SIZE

REVISION
R
4.18.0
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 72 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D DDR3 (1V5R1V35 S3) REGULATOR D
8 =PPVIN_S3_DDRREG
OMIT_TABLE OMIT_TABLE
CRITICAL CRITICAL
C7330 1
C7331 1 1 C7332 1 C7333 1
C7334
68UF 68UF 1UF 0.001UF 1UF
20% 20% 10% 10% 10%
16V 2 16V 2 25V 50V 25V
2 X5R 2 X7R-CERM 2 X5R
POLY-TANT POLY-TANT
=PPVIN_S0_DDRREG_LDO CASE-D2E-SM CASE-D2E-SM 603-1 0402 603-1
8
8 =PP5V_S3_DDRREG
C7301 1
10UF
20%
10V
C7300 1 X5R 2
R7330
10UF
603
1
1 2
(DDRREG_DRVH) DDRREG_DRVH_R
20%
MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm
10V 5%
X5R 2 MIN_NECK_WIDTH=0.17 mm MIN_NECK_WIDTH=0.17 mm
1/16W
603 MF-LF
402
2
C VLDOIN
C7325
0.1UF
CRITICAL
Q7330
C
V5IN VBST 1 2
12 15 DDRREG_VBST MIN_LINE_WIDTH=0.6 mm CSD58872Q5D
DRVH 14 DDRREG_DRVH SON5X6 VIN 1 CRITICAL
U7300 GATE_NODE=TRUE
10% 3 TG
27 9 IN =DDRVTT_EN (VTT Enable) 17 S3 SW 13 DDRREG_LL
DIDT=TRUE
50V
X7R
L7330
TPS51916 SWITCH_NODE=TRUE DIDT=TRUE
603-1 VSW 6 0.68UH-18A-3.3MOHM
70 IN =DDRREG_EN (VDDQ/VTTREF Enable) 16 S5 QFN
DRVL 11 DDRREG_DRVL (DDRREG_LL)
4 TGR 7 1 2 =PPDDR_S3_REG 8
DDRREG_1V8_VREF 6 VREF GATE_NODE=TRUE DIDT=TRUE MIN_LINE_WIDTH=0.6 mm
8 PCMB103T
CRITICAL PGOOD 20 DDRREG_PGOOD
OUT 88 MIN_NECK_WIDTH=0.17 mm CRITICAL Vout = 1.5V
1
1
OMIT_TABLE VDDQSNS 9 DDRREG_VDDQSNS DDRREG_VSW 152S0905 C7340 18A max output
R7315 33 DDRREG_FB 8 REFIN 5 BG SWITCH_NODE=TRUE
C7315 1
VTT 3 8 =PPVTT_S0_DDR_LDO XW7360 (DDRREG_DRVL) DIDT=TRUE 270UF (Q7335 limit)
0.1UF 20.0K SM MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm 20%
10%
1% DDRREG_MODE 19 MODE VTTSNS 1
DDRREG_VTTSNS 1 2
PGND
MIN_NECK_WIDTH=0.17 mm 2 2V
TANT
1
C7346 f = 400 kHz
1/16W
16V
2 MF-LF DDRREG_TRIP 18 TRIP PLACE_NEAR=C7361.1:3mm CASE-B4-SM 0.001UF
X7R-CERM 10%
9
402 =PPVTT_S3_DDR_BUF 8 33
0402 2 50V
VTTREF 5 CRITICAL 2 X7R-CERM
10mA max load
C7341 1 1
C7345 0402
2
NOSTUFF VTT THRM C7360 1 1

C7361 270UF 10UF
OMIT_TABLE PGND GND GND PAD 20% 20% XW7301
10UF 10UF
R7319 1 1
R7316 1
C7316 20% 20%
2V 2 2
6.3V
X5R
SM
10
21
TANT
150K 100K 0.01UF
6.3V
2 2
6.3V CASE-B4-SM 603
1 PLACE_NEAR=C7340.1:1MM
1%
1/16W
1%
1/16W
10%
1
R7317 1
R7318 X5R
603
X5R
603
MF-LF MF-LF 2
16V
X7R-CERM 200K 61.9K PLACE_NEAR=C3101.1:1mm PLACE_NEAR=C3101.1:3mm
402 2 2
402 0402 1% 1%
1/16W 1/16W
DDRREG_P1V35_L MF-LF MF-LF C7360, C7361 close to memory
402
2 402 C7350
Q7319 2
2
0.22UF
1
(DDRREG_VDDQSNS)
SSM3K15FV D 3 XW7300 10%
SOD-VESM-HF SM 10V
CERM 2
402
NOSTUFF 1
GND_DDRREG_SGND
1 G S 2 MIN_NECK_WIDTH=0.17 mm
B
VOLTAGE=0V
B
MEM_VDD_SEL_1V5_L IN 18

114S0343 1 RES,MTL FILM,1/16W,20.0K,1,0402,SMD,LF R7315 PPDDR:1V5
114S0411 1 RES,MTL FILM,1/16W,100K,1,0402,SMD,LF R7316 PPDDR:1V5
PAGE TITLE
1V5R1V35V DDR3 SUPPLY

DRAWING NUMBER SIZE

REVISION
R
4.18.0
73 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D =PP5V_S0_CPUIMVP 8 66 D
R7401
10
PP5V_S0_CPUIMVP_VCC 1 2
MIN_NECK_WIDTH=0.2 MM 5%
VOLTAGE=5V 1/16W
MF-LF =PPVIN_S0_CPUIMVP 8 66
402
8 =PPVCCIO_S0_CPUIMVP 1
C7402 1
C7403
C7401 1 2.2UF 2.2UF
20% 20%
2.2UF 2
10V
2
10V
20% X6S-CERM X6S-CERM
10V 0402 0402
2
R74791 1
R7480 X6S-CERM
0402
54.9 130
1% 1%
1/20W 1/20W PLACE_NEAR=U7400.24:2mm
MF MF
201 2 2 201 PLACE_NEAR=U7400.15:2mm
VCC 46
29
19
PLACE_NEAR=U7400.18:2mm PLACE_NEAR=U7400.16:2mm
SIGNAL_MODEL=EMPTY
VDDA
VDDB
R7406
R7403 300
182K 2 1 2 CPUIMVP_ISNS1_P
U7400 1
1%
IN 46 66 97
MAX15119GTM 1% 1/20W
QFN 1/20W MF
66 OUT CPUIMVP_AXG_PWM2 13 DRVPWMB TONB 1 CPUIMVP_TONB MF
R7402 201
201
182K 2 R7407
66 OUT CPUIMVP_PWM3 37 DRVPWMA TONA 48 CPUIMVP_TONA 1
300
25 1% 1 2 CPUIMVP_ISNS2_P IN 46 66 97
66 65 IN CPUIMVP_ISUM3P 45 CSPA3 CRITICAL BSTA1 CPUIMVP_BOOT1 OUT 66 1/20W SIGNAL_MODEL=EMPTY
MF 1%
89 42 41 11 CPU_PROCHOT_L 4 VRHOT* DHA1 27 CPUIMVP_UGATE1 66 201 1/20W
OUT OUT
LXA1 26 CPUIMVP_PHASE1 66
C7408 MF
SIGNAL_MODEL=EMPTY
201
C
OUT
C 70
88
OUT CPUIMVP_PGOOD 24
CPUIMVP_AXG_PGOOD 12
POKA
POKB
DLA1
CSPA1
28
42
CPUIMVP_LGATE1
CPUIMVP_ISUM1P
OUT 66
66
150PF
1 2 CPUIMVP_ISUM_R R7408
300
OUT OUT
10%
1 2 CPUIMVP_ISNS3_P IN 46 66 97
70 IN CPUIMVP_VR_ON 47 EN CSPAAVE 41 CPUIMVP_ISUM 25V

X7R-CERM
1%
1/20W
CSNA
66
43 CPUIMVP_ISUMN 0201 MF
89 13 CPU_VIDSOUT 21 VDIO NO STUFF 201
FBA 3
BI
89 13 IN CPU_VIDSCLK 23 CLK
CPUIMVP_FBA 65
C7409 R7410 SIGNAL_MODEL=EMPTY
44 470PF
89 13 OUT CPU_VIDALERT_L 22 ALERT* CSPA2 CPUIMVP_ISUM2P 1 2 1
1 2
BSTA2 34 CPUIMVP_BOOT2 66
39 OUT
CPUIMVP_NTC THERMA 32 10%
5%
DHA2 CPUIMVP_UGATE2 OUT 66 1/20W
CPUIMVP_NTCG 40 THERMB 16V MF
LXA2 33 CPUIMVP_PHASE2 66
X5R-X7R-CERM NO STUFF 201
OUT 0201
CPUIMVP_SLEW 38 SR DLA2 31 CPUIMVP_LGATE2 OUT 66
R7409
1
40.2K2
CPUIMVP_IMAXA 35 BSTB 14 CPUIMVP_BOOT1G
IMAXA OUT 66
1%
CPUIMVP_IMAXB 36 IMAXB DHB 16 CPUIMVP_UGATE1G 66 1/20W CPUIMVP_ISUMG2P 66
OUT MF IN
1 1 NO STUFF
LXB 15 CPUIMVP_PHASE1G OUT 66
201
R7468 R7466 1 1 1 OUT 66
5.76K 5.76K R7464 R7462 R7460 8 CSPBAVE DLB 18 CPUIMVP_LGATE1G 66 SIGNAL_MODEL=EMPTY

OUT
1% 1% 200K 301K 301K
1/20W 1/20W 1% 1% 1% 11
MF MF 1/20W 1/20W 1/20W CSPB2
201 201 MF MF MF 9
2 2 CPUIMVP_ISUMG1P
2
201
2
201
2
201 CSPB1 IN 66
CSNB 10
FBB 6 CPUIMVP_FBB 65
GNDSA
GNDSB
PGNDA
PGNDB
THRM
PAD
1 1 AGND CPUIMVP_ISUM3P 65 66
CRITICAL CRITICAL
1 1 1 NO STUFF
5
20
49
30
17
R7469 R7467 R7465 R7463 R7461 NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF
CPUIMVP_ISUMGN 66
1 IN
200K 137K 137K 1
C7418 1
C7419 1
C7414 1
C7415 1
C7416 1
C7417 C7410
100KOHM 100KOHM 1% 1% 1% XW7400 100PF 100PF 100PF 100PF 100PF 100PF 100PF
1/20W 1/20W 1/20W SM
0402 0402 5% 5% 5% 5% 5% 5% 5%
B 2 2 2
MF
201
2
MF
201
2
MF
201 2 1 2
25V
NP0-CERM
0201
2
25V
NP0-CERM
0201
2
25V
NP0-CERM
0201
2
25V
NP0-CERM
0201
2
25V
NP0-CERM
0201
2
25V
NP0-CERM
0201
2
25V
NP0-CERM
0201
B
GND_CPUIMVP_SGND
PLACE_NEAR=Q7510.1:7mm MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
C7473
PLACE_NEAR=Q7550.1:6mm 1
C7440 100PF SIGNAL_MODEL=EMPTY
1000PF 1 2
10%
16V
1
C7412
2 X7R-CERM R7440 5% 1000PF
SIGNAL_MODEL=EMPTY
0201
10 25V 10%
CPU_AXG_SENSE_R 1 2 CPU_AXG_SENSE_N 13 89
NP0-CERM 2
16V
IN 0201 X7R-CERM
1% R7412 0201 R7413
66 IN CPUIMVP_ISUMG_AVEP 1
C7441 1/20W
MF CPUIMVP_FBA 1
12.1K
2 CPUIMVP_FBA_R 1
10
2 CPU_VCCSENSE_P
65 IN 13 89
1000PF 201
10% 1% 1%
16V 1/20W 1/20W
2 X7R-CERM MF MF
0201 R7441 201 SIGNAL_MODEL=EMPTY 201
CPU_VCCSENSE_R 1 2 CPU_VCCSENSE_N IN 13 89
1%
C7422 1
1/20W 1000PF
NO STUFF NO STUFF 10%
MF
1
C7442 1
C7443 201 16V
X7R-CERM 2
1000PF 1000PF R7422 0201 R7423
10%
16V
10%
16V
16.2K 10
2 X7R-CERM 2 X7R-CERM 65 CPUIMVP_FBB 1 2 CPUIMVP_FBB_R 1 2 CPU_AXG_SENSE_P IN 13 89
0201 0201 1% 1%
1/20W 1/20W
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY MF MF
201 201
PAGE TITLE
CPU IMVP7 & AXG VCore Regulator

DRAWING NUMBER SIZE

REVISION
R
4.18.0
74 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
65 8 =PPVIN_S0_CPUIMVP
THESE TWO CAPS ARE FOR EMC THESE TWO CAPS ARE FOR EMC
OMIT_TABLE OMIT_TABLE NOSTUFF NOSTUFF OMIT_TABLE OMIT_TABLE NOSTUFF
1 1 1 1 1 1 1 1 1 1 1 1 1 1
C7513 C7514 C7515 C7516 C7517 C7518 C7519 C7523 C7524 C7525 C7526 C7527 C7528 C7529
10UF 10UF 1UF 0.001UF 0.001UF 10UF 10UF 1UF 0.001UF 0.001UF
5
6
7
8
CRITICAL 68UF 68UF CRITICAL 68UF 68UF
PHASE 1 PHASE 2
376S1010 20% 20% 20% 20% 10% 10% 10% 20% 20% 20% 20% 10% 10% 10%
D Q7510 2 16V
POLY-TANT
2 16V
POLY-TANT
2
16V
X6S-CERM 2
16V
X6S-CERM 2
16V
X6S-CERM 2
50V
X7R-CERM 2
50V
X7R-CERM
376S1010
D Q7510 2 16V
POLY-TANT
2 16V
POLY-TANT
2
16V
X6S-CERM 2
16V
X6S-CERM 2
16V
X6S-CERM 2
50V
X7R-CERM 2
50V
X7R-CERM
IRF6802SDTRPBF CASE-D2E-SM CASE-D2E-SM 0603 0603 0402 0402 0402
IRF6802SDTRPBF CASE-D2E-SM CASE-D2E-SM 0603 0603 0402 0402 0402
1 G DIRECTFET-SA CRITICAL 2 G DIRECTFET-SA CRITICAL

CPUIMVP_BOOT1_RC CPUIMVP_BOOT2_RC
MIN_LINE_WIDTH=0.25 MM S R7510 MIN_LINE_WIDTH=0.25 MM S R7520
MIN_NECK_WIDTH=0.25 MM CRITICAL 0.00075 MIN_NECK_WIDTH=0.25 MM CRITICAL 0.00075
DIDT=TRUE L7510 1% DIDT=TRUE L7520 1%
3
1W 1W
0.36UH-20%-36A-0.00108OHM 0.36UH-20%-36A-0.00108OHM
D R7511
1
1
1 2 PPVCORE_S0_CPU_PH1 1
MF
0612
2 =PPVCORE_S0_CPU_REG 8
R7521
1
1
1 2 PPVCORE_S0_CPU_PH2 1
MF
0612
2 =PPVCORE_S0_CPU_REG 8 66
D
C7511 PIMS103T-SM
MIN_LINE_WIDTH=0.6 MM 66 C7521 PIMS103T-SM
0 0.22UF NOSTUFF
MIN_NECK_WIDTH=0.25 MM 3 4 0 0.22UF NOSTUFF
MIN_NECK_WIDTH=0.25 MM 3 4
5% 10% 1 152S1538 VOLTAGE=1.25V 5% 10% 1 152S1538 VOLTAGE=1.25V
1/16W 16V R7512 97 46 CPUIMVP_ISNS1_N 1/16W 16V R7522 97 46 CPUIMVP_ISNS2_N
MF-LF 2 CERM
2.2 97 65 46 CPUIMVP_ISNS1_P MF-LF 2 CERM
2.2 97 65 46 CPUIMVP_ISNS2_P
NC
NC
402 2 402 1 1
402 2 402 1 1
NC
NC
5% R7513 R7514 5% R7523 R7524
1/10W 1/10W
MF-LF 46.4 10 65 IN CPUIMVP_BOOT2 MF-LF 46.4 10
603 2 1% 1% MIN_LINE_WIDTH=0.25 MM DIDT=TRUE 603 2 1% 1%
65 IN CPUIMVP_BOOT1 1/20W 1/20W MIN_NECK_WIDTH=0.2 MM 1/20W 1/20W
1
2
8
7
MIN_LINE_WIDTH=0.25 MM MF MF MF MF
DIDT=TRUE CPUIMVP_UGATE2
1
2
8
7
MIN_NECK_WIDTH=0.2 MM 201 2 201 65 IN 201 2 201
CPUIMVP_PH1_SNUB 2
MIN_LINE_WIDTH=0.5 MM DIDT=TRUE CRITICAL CPUIMVP_PH2_SNUB 2
CPUIMVP_UGATE1 D
65 IN
DIDT=TRUE
GATE_NODE=TRUE
D CRITICAL
Q7515
DIDT=TRUE
NOSTUFF
CPUIMVP_ISUMN 65 66 65
CPUIMVP_PHASE2
GATE_NODE=TRUE
Q7525 DIDT=TRUE
NOSTUFF
CPUIMVP_ISUMN 65 66
65 CPUIMVP_PHASE1 649135PBF 1 C7512

IN
DIDT=TRUE
SWITCH_NODE=TRUE
649135PBF 1 C7522
IN 4 G DIRECTFET_S3C
DIDT=TRUE
MIN_NECK_WIDTH=0.2 MM 4 G DIRECTFET_S3C 0.001UF 65 CPUIMVP_LGATE2 0.001UF 1
C7582
SWITCH_NODE=TRUE 10% 1 IN 376S1011 10%
376S1011 50V C7581 MIN_LINE_WIDTH=0.5 MM DIDT=TRUE S 50V 330PF
65 CPUIMVP_LGATE1 2 MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE 2
330PF
IN S X7R-CERM X7R-CERM 10%
MIN_LINE_WIDTH=0.5 MM DIDT=TRUE 0402 10% 0402

Schem, MLB, Kepler, 2phase, D2: Schematic / PCB #'S

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Schem, MLB, Kepler, 2phase, D2: Schematic / PCB #'S

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8 7 6 5 4 3 2 1

D (.csa) Date (.csa) Date (.csa) Date

10 CPU DMI/PEG/FDI/RSVD D2_KEPLER 55 AUDIO: IV SENSE D2_CARA

13 CPU POWER D2_KEPLER 58 AUDIO: JACK D2_CARA

15 CPU DECOUPLING-I D2_SEAN 60 DC-In & Battery Connectors D2_KEPLER

23 PCH DECOUPLING D2_CLEAN 68 Misc Power Supplies D2_KEPLER

25 Chipset Support D2_KEPLER 70 Power Control 1/ENABLE D2_KEPLER

26 USB HUB & MUX D2_KEPLER 71 KEPLER PCI-E D2_KEPLER

27 CPU Memory S3 Support D2_KEPLER 72 KEPLER CORE/FB POWER D2_SEAN

28 DDR3 SDRAM Bank A (1 OF 2) D2_KEPLER 73 KEPLER FRAME BUFFER I/F D2_SEAN

30 DDR3 SDRAM Bank B (1 OF 2) D2_KEPLER 75 GDDR5 Frame Buffer A D2_SEAN

31 DDR3 SDRAM Bank B (2 OF 2) D2_KEPLER 76 GDDR5 Frame Buffer B D2_SEAN

32 DDR3 Termination D2_KEPLER 77 KEPLER EDP/DP/GPIO D2_SEAN

33 DDR3/FRAMEBUF VREF MARGINING D2_KEPLER 78 KEPLER GPIOS,CLK & STRAPS D2_SEAN

36 Thunderbolt Host (2 of 2) D2_KEPLER 81 eDP Display Connector D2_KEPLER

38 RIO CONNECTOR D2_KEPLER 83 eDP Muxed Graphics Support D2_SEAN

39 SSD CONNECTOR D2_KEPLER 84 Thunderbolt Connector A D2_KEPLER

40 USB 3.0 CONNECTORS D2_KEPLER 85 Thunderbolt Connector B D2_KEPLER

42 SMC Support D2_KEPLER 87 PCH VCCIO (1.05V) POWER SUPPLY D2_KEPLER

U8000 INTEL CPU 苹果笔记本维修交流群群号：325742634

GPIO FDI DMI RTC

SPI FAN CONN AND CONTROL

DP MUX HUB 2 J4610

LCD PANEL PG 26,28

PG 31 J4310 Apple Inc. 051-9589 D

J6900 F7040 V Q5315

GPU VCORE SMC_CPU_FSB_ISENSE

EG_RAIL2_EN P3V3GPU_EN U2850 (PAGE 16~21)

U1800 LCD_BKLT_NO LP8550

(PAGE 16~21) U4900

Apple Inc. 051-9589 D

607-9546 D2,MLB,KEPLER_2PHASE,COMMON D2_COMMON,POSCAP_MYLAR_PAIR 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY3Y] CRITICAL EEEE:DY3Y TABLE_ALT_ITEM

639-3378 PCBA,2.3G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY3V BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY3V,DEVEL_BOM,RAM_2G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DY44] CRITICAL EEEE:DY44 TABLE_ALT_ITEM

D 639-3379 PCBA,2.3G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY3W BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY3W,DEVEL_BOM,RAM_2G_HYNIX_1600

Fairchild alt to Siliconix

639-3381 PCBA,2.3G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY40 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY40,DEVEL_BOM,RAM_2G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DRF1] CRITICAL EEEE:DRF1 TABLE_ALT_ITEM

639-3384 PCBA,2.3G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DY43 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY43,DEVEL_BOM,RAM_4G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DRF4] CRITICAL EEEE:DRF4 TABLE_ALT_ITEM

639-3385 PCBA,2.3G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DY44 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY44,DEVEL_BOM,RAM_4G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DRDN] CRITICAL EEEE:DRDN TABLE_ALT_ITEM

639-3386 PCBA,2.3G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DY45 BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_HYNIX_A_DIE,EEEE:DY45,DEVEL_BOM,RAM_4G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DRDW] CRITICAL EEEE:DRDW TABLE_ALT_ITEM

639-3387 PCBA,2.3G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DY4C BASE_BOM,CPU_IVY:2_3GHZ,FB_2G_SAMSUNG,EEEE:DY4C,DEVEL_BOM,RAM_4G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DT9H] CRITICAL EEEE:DT9H TABLE_ALT_ITEM

639-2821 PCBA,2.6G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,DRF1 BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRF1,DEVEL_BOM,RAM_2G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DT9D] CRITICAL EEEE:DT9D TABLE_ALT_ITEM

639-2825 PCBA,2.6G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,DRF4 BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRF4,DEVEL_BOM,RAM_2G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DT9F] CRITICAL EEEE:DT9F TABLE_ALT_ITEM

639-2817 PCBA,2.6G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DRDN BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DRDN,DEVEL_BOM,RAM_2G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DT9G] CRITICAL EEEE:DT9G TABLE_ALT_ITEM

639-2815 PCBA,2.6G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,DRDW BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DRDW,DEVEL_BOM,RAM_2G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0HN] CRITICAL EEEE:F0HN TABLE_ALT_ITEM

639-2979 PCBA,2.6G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,DT9H BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9H,DEVEL_BOM,RAM_4G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0HR] CRITICAL EEEE:F0HR TABLE_ALT_ITEM

639-2980 PCBA,2.6G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DT9D BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9D,DEVEL_BOM,RAM_4G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DYW4] CRITICAL EEEE:DYW4 TABLE_ALT_ITEM

639-2981 PCBA,2.6G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,DT9F BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_HYNIX_A_DIE,EEEE:DT9F,DEVEL_BOM,RAM_4G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0HV] CRITICAL EEEE:F0HV TABLE_ALT_ITEM

639-2982 PCBA,2.6G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,DT9G BASE_BOM,CPU_IVY:2_6GHZ,FB_2G_SAMSUNG,EEEE:DT9G,DEVEL_BOM,RAM_4G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0HM] CRITICAL EEEE:F0HM TABLE_ALT_ITEM

639-3618 PCBA,2.7G,8G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HN BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HN,DEVEL_BOM,RAM_2G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:DYW5] CRITICAL EEEE:DYW5 TABLE_ALT_ITEM

639-3619 PCBA,2.7G,8G_HYN,VRAM_SAM,MLB_KEPLER,D2,F0HR BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HR,DEVEL_BOM,RAM_2G_HYNIX_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0HY] CRITICAL EEEE:F0HY TABLE_ALT_ITEM

639-3561 PCBA,2.7G,8G_SAM,VRAM_HYN,MLB_KEPLER,D2,DYW4 BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:DYW4,DEVEL_BOM,RAM_2G_SAMSUNG_1600 825-7563 1 LABEL,MLB/LIO,MBA [EEEE:F0HT] CRITICAL EEEE:F0HT

C 639-3620 PCBA,2.7G,8G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HV BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HV,DEVEL_BOM,RAM_2G_SAMSUNG_1600

Panasonic alt to TDK

639-3627 PCBA,2.7G,16G_HYN,VRAM_HYN,MLB_KEPLER,D2,F0HM BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HM,DEVEL_BOM,RAM_4G_HYNIX_1600 TABLE_ALT_ITEM

639-3562 PCBA,2.7G,16G_HYN,VRAM_SAM,MLB_KEPLER,D2,DYW5 BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:DYW5,DEVEL_BOM,RAM_4G_HYNIX_1600 TABLE_ALT_ITEM

639-3628 PCBA,2.7G,16G_SAM,VRAM_HYN,MLB_KEPLER,D2,F0HY BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_HYNIX_A_DIE,EEEE:F0HY,DEVEL_BOM,RAM_4G_SAMSUNG_1600 TABLE_ALT_ITEM

639-3629 PCBA,2.7G,16G_SAM,VRAM_SAM,MLB_KEPLER,D2,F0HT BASE_BOM,CPU_IVY:2_7GHZ,FB_2G_SAMSUNG,EEEE:F0HT,DEVEL_BOM,RAM_4G_SAMSUNG_1600

BOM Groups TABLE_BOMGROUP_HEAD

D2_COMMON ALTERNATE,COMMON,D2_COMMON1,D2_COMMON2,D2_PROGPARTS,D2_PVB 337S4313 1 IC,MCU,H8S/2113,9X9MM,TLP-145V U9100 CRITICAL DPMUXMCU:BLANK

DRAM SPD Straps TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION

IVB,S R0MP,PRQ,E1,2.3,45W,4+2,1.2,6M,BGA CPU_IVY:2_3GHZ