Aliases Resolved: Schem, MLB, M82 PVT

8 7 6 5 4 3 2 1
CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
SCHEM,MLB,M82 546198
DATE DATE
PVT
11/14/2007
D D
(.csa) Date (.csa) Date
Page
TABLE_TABLEOFCONTENTS_HEAD
Contents Sync Page
TABLE_TABLEOFCONTENTS_HEAD
Contents Sync
1 N/A 50 01/09/2007
TABLE_TABLEOFCONTENTS_ITEM
1 Table of Contents N/A
42 SMC SUPPORT M70
2 05/11/2006 51 01/09/2007
2 System Block Diagram WFERRY-WF
43 LPC+SPI Debug Connector M70
3 06/30/2005 52 01/09/2007
3 Power Block Diagram POWER
44 SMBUS CONNECTIONS M70
4 (N/A) 53 01/09/2007
4 CONFIGURATION OPTIONS (N/A)
45 Voltage Sensors M70
5 N/A 55 01/09/2007
5 Acoustic Cap BOM Config Tables N/A 46 TEMPERATURE SENSORS M70
www.laptop-schematics.com
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
6 (MASTER) 56 01/09/2007
6 ICT Test Points (MASTER)
47 Fan M70
7 (MASTER) 59 01/12/2007
7 Functional Test and No-Tests (MASTER)
48 Sudden Motion Sensor (SMS) M76_MLB
8 06/15/2006 61 04/26/2006
8 Power Aliases WFERRY
49 SPI ROMs WFERRY
9 (MASTER) 69 01/09/2007
9 SIGNAL ALIAS /RESET (MASTER)
50 DC-In & Battery Connectors M70
10 (MASTER) 70 01/09/2007
10 CPU FSB (MASTER)
51 S0 FETS & Power Sequencing M70
11 (MASTER) 71 07/13/2005
11 CPU Power & Ground (MASTER)
52 IMVP6 CPU VCore Regulator POWER
12 04/26/2006 72 (MASTER)
12 CPU Decoupling & VID MSARWAR
53 Render VCore Supplies (MASTER)
13 01/24/2007 73 01/09/2007
13 eXtended Debug Port (XDP) M75
54 1.5V/1.05V Supplies M70
14 (MASTER) 75 01/09/2007
14 NB CPU Interface (MASTER)
55 1.8V/0.9V Supplies M70
15 01/09/2007 76 02/01/2007
15 NB PEG / Video Interfaces M70 56 5V/3.3V Supplies M70
C
16
16
17
NB Misc Interfaces M70
01/09/2007
01/09/2007
57
77
78
3.42V/1.25V Switcher M70
01/09/2007
02/01/2007
C
17 NB DDR2 Interfaces M70
58 S3 FET & S3/S5 Control M70
18 01/09/2007 79 01/09/2007
18 NB Power 1 M70
59 PBUS Supply/Battery Charger M70
19 01/09/2007 90 06/23/2006
19 NB Power 2 M70
60 LVDS,Camera Conn. and ALS Conn. GPU
20 01/09/2007 92 06/06/2005
20 NB Grounds M70
61 SDVO/TMDS Tx GRAPHIC
21 01/09/2007 93
21 NB Standard Decoupling M70
62 HDCP uController
22 01/09/2007 94 01/09/2007
22 NB Graphics Decoupling M70
63 DVI CONNECTIONS M70
23 01/09/2007 97 (MASTER)
23 SB Enet, Disk, FSB, LPC M70
64 LED Backlight Driver (MASTER)
24 01/09/2007 99
24 SB PCI, PCIe, DMI, USB M70
65 Additional CPU/GPU Decoupling
25 01/09/2007 100 01/30/2007
25 SB Pwr Mgt, GPIO, Clink M70
66 CPU/FSB Constraints T9
26 01/09/2007 101 01/30/2007
26 SB Power & Ground M70
67 NB Constraints T9
27 02/01/2007 102 01/30/2007
27 SB Decoupling M70
68 Memory Constraints T9
28 01/09/2007 103 01/30/2007
28 SB Misc M70
69 SB Constraints (1 of 2) T9
29 02/01/2007 104 01/30/2007
29 Clock (CK505) M70
70 SB Constraints (2 of 2) T9
30 01/09/2007 105 01/30/2007
30 Clock Termination M70
71 Clock & SMC Constraints T9
31 (MASTER) 108 (MASTER)
31 DDR2 DRAM Channel A (MASTER)
72 M82 Power and Ground Nets (MASTER)
32 (MASTER) 109 (MASTER)
32 DDR2 DRAM Channel B (MASTER)
73 M82 Rule Definitions (MASTER)
33 01/09/2007
33 Memory Active Termination
B TABLE_TABLEOFCONTENTS_ITEM
34
34
DDR2 BYPASSING 1
M70
MEMORY
06/20/2005 B
35 06/20/2005
35 DDR2 BYPASSING 2 MEMORY
41 01/09/2007
36 Wireless M93 Connector M70
42 (MASTER)
37 Hatch and Audio Connectors (MASTER)
44 (MASTER)
38 PATA HDD CONNECTOR (MASTER)
46 01/09/2007
39 USB EXTERNAL CONNECTORS M70
48 01/09/2007
40 IPD Connector M70
49 01/09/2007
41 SMC M70
A
ALIASES RESOLVED DIMENSIONS ARE IN MILLIMETERS
XX
X.XX
DRAFTER
METRIC
DESIGN CK
APPLE INC.
NOTICE OF PROPRIETARY PROPERTY A

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
ENG APPD MFG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
Schematic / PCB #’s ANGLES II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
QA APPD DESIGNER TITLE
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
DO NOT SCALE DRAWING
051-7230 1 SCHEM,MLB,M82 SCH CRITICAL
RELEASE SCALE SCHEM,MLB,M82
820-2179 1 PCBF,MLB,M82 PCB CRITICAL NONE
DRAWING SIZE DRAWING NUMBER

TITLE=M82_MLB MATERIAL/FINISH REV.
ABBREV=DRAWING
LAST_MODIFIED=Wed Nov 14 17:25:50 2007 THIRD ANGLE PROJECTION
NOTED AS
APPLICABLE
D 051-7230
SHT 1
B.0.0
OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U1000
CPU U2900
2.0 GHz SLG2AP101

Core ~1.2V
Clocks TERMS
Pg 10 J1300 Pg 28 Pg 29
Pg 9
MINI XDP CONN
PG 12
D 64-Bit
FSB J6900/50
DC/Batt Power
D
800 MHz
MEM Active Conn Supplies

PG 55 PG 55-64
Parallel TOP ALS PG 65
Pg 13 J9050
U3100
U1400 U3110 Term M93
U3120 U4100 PG 36
U9200 U3130 J4800
Main Memory
PCI-E
U3140 Pg 32
SIL1392 NB-GMCH U3150
Pg 15/16
U3160
SDVO U3170
TMDS Core IPD
DDR2 - Dual Channel U5550 PG 46
Pg 14 MLB Temp Sensor
1.05 - 1.25V 1.8V - 64 Bits PG 40
DDR2 RAM CPU Temp Sensor U5520 PG 46
533/667 MHz
Out
TV
PG 66 Pg30
HEAT-PIPE/FIN Temp Sensor J5500 PG 46

U5900
VGA
Misc
J4200
SMS
Pg 17,18,19 Pg 15
LVDS
U9401 U3200 PG 48
DMI CLnk 0 U3210
DVI-I MUX U3220 U5900 SUDDEN MOTION DETECT PG 48
EN_L
Pg 14 Pg 15 Pg 15 U3230
U3240
PG 67 U3250
U3260
U3270 VOLTAGE SENSORS PG 45
PG 67
J9000 U6100
DDR2 RAM J5600
FAN CONN PG 47
SPI Pg31
LVDS Int Disp
Boot ROM
Conn x4 DMI
C PG 65 2.5 GHz
PG 48
A B 0 BSA MGMT ADC Fan Ser

C
J5100
Prt
SMC
FrankCard Conn
U4900 PG 41 PG 43
DMI CLnk 0 SPI
Pg 22
LPC
Pg 23 Pg 24 Pg 23
U2300
J4200
SATA
Pg 22
J4800
GPIOs
External
Pg 24
Well Spring USB
J4400 Trackpad/Keyboard
SB-ICH8 PG 40 PG 39
HDD PATA Core 1.05V
9
Conn
8
Pg 22
IDE
PG 38
7
6
Pg 23
5
USB
4
Ln1
3
2
Ln2
1
0
Ln3
PCI-E
B B
Pg 23
U2900
Ln4
Clk Gen
Pg 24
SMB
Core SLG2AP101
Ln5
Pg 25
PG 29
Ln6
E-NET CLnk 1 PCI HDA

Pg 22 Pg 24 Pg 23 Pg 22
J9050
DIGITAL MIC
CONNECTOR
PG 60
J4260
Audio
Connector
J4100 Pg 50
M93 AirPort/BT
Pg 35 System Block Diagram

A SYNC_MASTER=WFERRY-WF
NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=05/11/2006
A
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
II NOT TO REPRODUCE OR COPY IT
SIZE DRAWING NUMBER REV.
D 051-7230 B.0.0
APPLE INC. SCALE SHT OF

NONE 2 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AC
ADAPTER
IN
6A FUSE 01
M82 POWER SYSTEM ARCHITECTURE
=PPDCIN_G3H D6901 SMC PWRGD
04
PP18V5_DCIN =PP18V5_G3H_CHGR RN5VD30A-F SMC_RESET_L
02 PP3V42_G3H_SMC
U5000
PPVBAT_G3H_R D6901
J6980 F6900 (PAGE 41)
=PPDCIN_G3H ENABLE
PPBUSB_G3H D6901 3.425V G3HOT
03
LT1934 PP3V42_G3H_REG
SMC_BATT_CHG_EN (? A MAX CURRENT)
U7790
7A FUSE
R7980 (PAGE 62)
D ENABLES
VOUT
PPVBAT_G3H_CHGR_REG PPBUSB_G3H
=PBUSA_G3H D
PBUS CONVERTER/
CLOCK
BATTERY 2S2P
BATTERY CHARGER
ISL6258
A R7930 02 CLK_PWRGD
PWRGD
SLG2AP101
NB_RESET_L
Q7950 TMDS_RST_L
U7900 VIN U2900
VIN 1V05S0_RUNSS 1.05V PP1V05_S0_REG (PAGE 28)
(PAGE 63) 17 ENA1 VOUT1 18 AIRPORT_RST_L
(S0) (9.9 A MAX CURRENT)
CHGR_SMBUS
01 17 1V5S0_RUNSS 1.5V PP1V5_S0_REG

18 LCDBKLT_PLT_RST_L
CHGR_BGATE ENA2 VOUT2
(S0) (3.3 A MAX CURRENT) ICH8M 06-1
CK_PWRGD
TPS51124 U2803 PWRBTN*
U7300 PGOOD_1V5S0 VR_PWRGD_CK505 VR_PWRGD_CLKEN
BATT_POS_F (PAGE 58) VRMPWRGD 29 U2880
PGOOD_1V05S0 19
PLTRST* PLT_RST_L
RSMRST*
PM_SB_PWROK
12
DELAY 24 CPU_PWRGD
PWROK
P5VS3_EN_L CPU_PWRGD(GPIO49)
R-10K
02 CPUVCORE PPVCORE_S0_CPU_REG PPVCORE_S0_CPU
11 Q7860 C-0.002uF (S3) 28
VOUT U2300
VIN (30 A MAX CURRENT)
DELAY 25 (PAGE 22)
P3V3S3_EN_L
R-10K VR_PWRGD_CK505_L U2801
C-0.01uF (S3) CLKEN#
IMVP_VR_ON
VR_ON
12 23 26
ISL6261CRZ PGOOD VR_PWRGOOD_DELAY VR_PWRGOOD_DELAY CPU
U7100
C PPBUS_G3H
(PAGE 56) Q7000
16 PWRGOOD C
PP5V_S0
ICH RESET*
08
PM_S4_STATE_L
TPS79933 U1000
P5VS0_EN VIN (PAGE 9)
U2280 ?
ENA
(PAGE 21)
=PPBUSB_G3H Q7865 13 P3V3_S0_NB_TVDAC
VOUT
PG2 (205mA MAX CURRENT)
PM_SLP_S3_L PG3
PP5V_S3
SMC 08
12
02 P5VS3_EN_L
08
VIN
06 07 PP5V_S5_REG PP5V_S5
5VS5_RUNSS VO1
EN1 5V (? A MAX CURRENT)
SMC_PM_G2_EN (S5)
U4900
P60 (S5) PP3V3_S5_REG CRESTLINE 30
PP3V3_S5
(PAGE 40) 3V3S5_RUNSS VO2
(S5)
EN2 3.3V (? A MAX CURRENT)
PWROK H_CPURST*
FSB_CPURST_L
07 1.25V S0
08 Q7866 13 1V25S0_RUNSS
TPS51120 17 EN LTC3412A 18
U7600 PP3V3_S3 U7750 PP1V25_S0_REG U1400
(PAGE 60) VIN VOUT
(PAGE 13)
(PAGE 61) (3 A MAX CURRENT)
PGOOD1,2
RSMRST_PWRGD
09 P3V3S3_EN_L
U7002 10
22
B 16
PP1V25_S0_FET
ALL_SYS_PWRGD
SMC
RSMRST_OUT(P15)
PM_RSMRST_L B
PP5V_S0_NB_GFX_IMVP Q7001
SMC_ADAPTER_PRESENT ALL_SYS_PWRGD_AND PWRGD(P12) 99ms DLY
04 IMVP_VR_ON
PP3V3_S0 IMVP_VR_ON(P16) 23
VCC 09 RSMRST_PWRGD
GPU_VCORE RSMRST_IN(P13)
VIN SMC_LRESET_L
PLT_RST*
SMC_ONOFF_L
ADP3209 21 15 PWR_BUTTON(P90)
=PPVCORE_S0_NB_GFX_IMVP P3V3S0_EN PGOOD_1V5S0 PM_PWRBTN_L
GFX_VR_EN GCORE_EN U7200 VOUT P17(BTN_OUT)
EN
(PAGE 57) (13 A MAX CURRENT) PGOOD_1V05S0 BATTERY ONLY: 05
20 SMC_RESET_L
RST*
WOW_EN 15
PGOOD_SEQUENCER ADAPTER IN : 10-1
PM_WLAN_EN_L
19
PM_SLP_S5_L
SLP_S5_L(P95)
14
PM_S4_STATE_L
Q7004 SLP_S4_L(P94)
PP1V8_S3_FET =PP1V8_S0_FET 16 PM_SLP_S3_L

SLP_S3_L(P93)
MCH DPLL
=PP1V8_S0_NB_DPLL
PP1V8_S3_REG TPS731125
VIN U2265 18 U4900
P1V8S0_EN (PAGE 21) (PAGE 40)
ENA
12 P1V25_S0_NB_DPLL
15 VOUT
R7870 VIN VLDOIN 13
1V8S3_RUNSS 1.8V PP1V8_S3_REG
S5 VOUT1
(11 A MAX CURRENT)
PM_SLP_S3_L
S3 0.9V PP0V9_S0_REG U7000
Power Block Diagram
VOUT2 RST* P5VS0_EN
DELAY 14 18 GATE A 15
Q7006 Q7007
ISL6130IRZA
A RUNSS_GATE_D R-330
C-0.022uF
1V5S0_RUNSS
(S0)
17 TPS51116
U7500 PGOOD_1V8S3 PGOOD_1V8S3 GATE B
P3V3S0_EN
15
SYNC_MASTER=POWER

A
15 UVLO_A
(PAGE 59)
DELAY
PP5V_S0_FET UVLO_B THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Q7006 Q7007 P1V8S0_EN PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1V05S0_RUNSS GATE C 15 AGREES TO THE FOLLOWING
R-330 17 PP3V3_S0_FET UVLO_C
C-0.01uF (S0) I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
PP1V8_S0_FET RUNSS_GATE_D
UVLO)D GATE D 15 II NOT TO REPRODUCE OR COPY IT
Q7006 Q7006 DELAY
PM_SLP_S3_L III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
R-330
1V25S0_RUNSS ENABLE_1
17
C-1000PF (S0) SIZE DRAWING NUMBER REV.
(PAGE 56)
14
D 051-7230 B.0.0

NONE 3 73
8 7 6 5 4 3 2 1
PAGE_BORDER=TRUE
8 7 6 5 4 3 2 1
BOMs BOMOPTION Groups

TABLE_BOMGROUP_HEAD TABLE_BOMGROUP_HEAD
BOM NUMBER BOM NAME BOM OPTIONS BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM
630-7886 PCBA,MLB,1.6GHZ,MI 2GB,SS CAP,M82 EEE_XSC,M82_COMMON,M82_MICRON,CPU_PRQ_1_6GHZ,M82_SS_CAP M82_COMMON ALTERNATE,COMMON,M82_COMMON1,M82_COMMON2,M82_COMMON3

630-9024 PCBA,MLB,1.6GHZ,HY 2GB,SS CAP,M82 EEE_YMS,M82_COMMON,M82_HYNIX,CPU_PRQ_1_6GHZ,M82_SS_CAP M82_COMMON1 ISL6258,BOOTROM_DEVEL,SMC_PRGRM

630-9133 PCBA,MLB,1.8GHZ,MI 2GB,SS CAP,M82 EEE_Z80,M82_COMMON,M82_MICRON,CPU_PRQ_1_8GHZ,M82_SS_CAP M82_COMMON2 SMS_MOT_DIS,LPCPLUS,XDP,DRAM_2GB

630-9134 PCBA,MLB,1.8GHZ,HY 2GB,SS CAP,M82 EEE_Z81,M82_COMMON,M82_HYNIX,CPU_PRQ_1_8GHZ,M82_SS_CAP M82_COMMON3

D 630-9204 PCBA,MLB,1.6GHZ,HY 2GB,MU CAP,M82 EEE_ZU5,M82_COMMON,M82_HYNIX,CPU_PRQ_1_6GHZ,M82_MU_CAP

TABLE_BOMGROUP_ITEM
M82_MICRON DRAM_MICRON,DRAM_SPD_1
TABLE_BOMGROUP_ITEM
D
630-9205 PCBA,MLB,1.6GHZ,HY 2GB,TY CAP,M82 EEE_ZU6,M82_COMMON,M82_HYNIX,CPU_PRQ_1_6GHZ,M82_TY_CAP M82_HYNIX DRAM_HYNIX,DRAM_SPD_2
630-9206 PCBA,MLB,1.6GHZ,MI 2GB,MU CAP,M82 EEE_ZU7,M82_COMMON,M82_MICRON,CPU_PRQ_1_6GHZ,M82_MU_CAP M82_HYNIX_LP DRAM_HYNIX_LP,DRAM_SPD_2

630-9207 PCBA,MLB,1.6GHZ,MI 2GB,TY CAP,M82 EEE_ZU8,M82_COMMON,M82_MICRON,CPU_PRQ_1_6GHZ,M82_TY_CAP M82_SS_CAP SS_CAP_1UF,SS_CAP_2_2UF,SS_CAP_10UF

630-9208 PCBA,MLB,1.8GHZ,HY 2GB,MU CAP,M82 EEE_ZU9,M82_COMMON,M82_HYNIX,CPU_PRQ_1_8GHZ,M82_MU_CAP M82_MU_CAP MU_CAP_1UF,MU_CAP_2_2UF,MU_CAP_10UF

630-9209 PCBA,MLB,1.8GHZ,HY 2GB,TY CAP,M82 EEE_ZUA,M82_COMMON,M82_HYNIX,CPU_PRQ_1_8GHZ,M82_TY_CAP M82_TY_CAP TY_CAP_1UF,TY_CAP_2_2UF,TY_CAP_10UF

TABLE_BOMGROUP_ITEM
630-9210 PCBA,MLB,1.8GHZ,MI 2GB,MU CAP,M82 EEE_ZUB,M82_COMMON,M82_MICRON,CPU_PRQ_1_8GHZ,M82_MU_CAP

TABLE_BOMGROUP_ITEM
630-9211 PCBA,MLB,1.8GHZ,MI 2GB,TY CAP,M82 EEE_ZUC,M82_COMMON,M82_MICRON,CPU_PRQ_1_8GHZ,M82_TY_CAP
Module Parts
Bar Code Label / EEE #’s
337S3522 1 IC,SANTAYNEZ,MEROM,1.6GHZ,ES,20W,956BGA U1000 CRITICAL CPU_1_6GHZ
337S3523 1 IC,SANTAYNEZ,MEROM,1.8GHZ,ES,20W,956BGA U1000 CRITICAL CPU_1_8GHZ
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:XSC] CRITICAL EEE_XSC
338S0420 1 IC,965GM,CRESTLINE,USFF BGA U1400 CRITICAL
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:YMS] CRITICAL EEE_YMS
338S0421 1 IC,ICH8M,USFF BGA U2300 CRITICAL
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:Z80] CRITICAL EEE_Z80
359S0130 1 LOW POWER CLOCK SYNTHESIZER,SLG2AP101,68PIN U2900 CRITICAL
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:Z81] CRITICAL EEE_Z81
335S0510 1 IC, 16MBIT 8-PIN SERIAL FLASH,VWQPN U6100 CRITICAL BOOTROM_BLANK_2MB
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:ZU5] CRITICAL EEE_ZU5
335S0509 1 IC, 32MBIT 8-PIN SERIAL FLASH, WSON8 U6100 CRITICAL BOOTROM_BLANK_4MB
341S2111 1 IC,EFI,BOOTROM DEVELOPMENT (UNLOCKED),M82 U6100 CRITICAL BOOTROM_DEVEL
1 U6100 CRITICAL BOOTROM_FINAL
C 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:ZU8] CRITICAL EEE_ZU8
341S2112
337S3477 1
IC,EFI,BOOTROM FINAL (LOCKED),M82
SST89V54RD MICROCONTROLLER U9300 CRITICAL SST8051_BLANK

C
341S2173 1 IC,PRGM,SST SST89V54RD,UCNTRLR,M82 U9300 CRITICAL SST8051_PRGRM
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:ZUA] CRITICAL EEE_ZUA
338S0422 1 IC,SMC,HS8/2117 U4900 CRITICAL SMC_BLANK
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:ZUB] CRITICAL EEE_ZUB
341S2115 1 IC,PRGRM,SMC (NEW),M82 U4900 CRITICAL SMC_PRGRM
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEE:ZUC] CRITICAL EEE_ZUC
333S0406 4 MICRON,DRAM,64M16,8x12.5 U3100,U3110,U3120,U3130 CRITICAL DRAM_MICRON
333S0411 4 HYNIX,DRAM,64M16,8x13 U3100,U3110,U3120,U3130 CRITICAL DRAM_HYNIX
333S0415 4 HYNIX,DRAM,64M16,8x13,LP U3100,U3110,U3120,U3130 CRITICAL DRAM_HYNIX_LP
353S1938 1 IC,ISL6258,REV2,BAT CHGR, 28P QFN U7900 CRITICAL ISL6258

B 197S0213 1 14.318MHZ XTAL, 2.5x2.0 Y9390 CRITICAL SST8051_14MHZ B
197S0231 1 20MHZ XTAL, 2.5x2.0 Y9390 CRITICAL SST8051_20MHZ
197S0257 1 33MHZ XTAL, 2.5x2.0 Y9390 CRITICAL SST8051_33MHZ
337S3563 1 IC,SANTAYNEZ,MEROM,1.6GHZ,PRQ,REV3,20W,956BGA U1000 CRITICAL CPU_PRQ_1_6GHZ
337S3564 1 IC,SANTAYNEZ,MEROM,1.8GHZ,PRQ,REV3,20W,956BGA U1000 CRITICAL CPU_PRQ_1_8GHZ
338S0514 1 IC,965GM,CRESTLINE,PRQ,USFF BGA U1400 CRITICAL NB_PRQ
338S0515 1 IC,ICH8M,PRQ,USFF BGA U2300 CRITICAL SB_PRQ
Alternate Parts
PART NUMBER ALTERNATE FOR REFERENCE DESIGNATOR(S) DESCRIPTION BOM OPTION
PART NUMBER
128S0093 128S0092 ALL 33UF 20% 16V DCASE
376S0466 376S0410 ALL Si4413 for Si4405
740S0044 740S0028 ALL 0.5A OC FUSE
104S0023 104S0018 ALL 1206 1/4W .002 OHM
CONFIGURATION OPTIONS
SYNC_MASTER=(N/A) SYNC_DATE=(N/A)
A NOTICE OF PROPRIETARY PROPERTY
A
D 051-7230 B.0.0

NONE 4 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

SAMSUNG MURATA TAIYO YUDEN
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
138S0629 5 CAP, 1UF, 6.3V, 10%, 0402 C1801,C1802,C2144,C2151,C2170 CRITICAL SS_CAP_1UF 138S0628 5 CAP, 1UF, 6.3V, 10%, 0402 C1801,C1802,C2144,C2151,C2170 CRITICAL MU_CAP_1UF 138S0630 5 CAP, 1UF, 6.3V, 10%, 0402 C1801,C1802,C2144,C2151,C2170 CRITICAL TY_CAP_1UF
138S0629 9 CAP, 1UF, 6.3V, 10%, 0402 C2265,C2280,C2600,C2703,C2805,C2900,C7000,C7100,C7101 CRITICAL SS_CAP_1UF 138S0628 9 CAP, 1UF, 6.3V, 10%, 0402 C2265,C2280,C2600,C2703,C2805,C2900,C7000,C7100,C7101 CRITICAL MU_CAP_1UF 138S0630 9 CAP, 1UF, 6.3V, 10%, 0402 C2265,C2280,C2600,C2703,C2805,C2900,C7000,C7100,C7101 CRITICAL TY_CAP_1UF
D D
2.2UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS
138S0632 10 CAP, 2.2UF, 6.3V, 20%, 0402 C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP, 2.2UF, 6.3V, 20%, 0402 C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP, 2.2UF, 6.3V, 20%, 0402 C1240,C1241,C1242,C1243,C1244,C1245,C1246,C1247,C1248,C1249 CRITICAL TY_CAP_2_2UF
138S0632 8 CAP, 2.2UF, 6.3V, 20%, 0402 C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267 CRITICAL SS_CAP_2_2UF 138S0633 8 CAP, 2.2UF, 6.3V, 20%, 0402 C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267 CRITICAL MU_CAP_2_2UF 138S0634 8 CAP, 2.2UF, 6.3V, 20%, 0402 C1260,C1261,C1262,C1263,C1264,C1265,C1266,C1267 CRITICAL TY_CAP_2_2UF
138S0632 6 CAP, 2.2UF, 6.3V, 20%, 0402 C2214,C2215,C2240,C2241,C2242,C2243 CRITICAL SS_CAP_2_2UF 138S0633 6 CAP, 2.2UF, 6.3V, 20%, 0402 C2214,C2215,C2240,C2241,C2242,C2243 CRITICAL MU_CAP_2_2UF 138S0634 6 CAP, 2.2UF, 6.3V, 20%, 0402 C2214,C2215,C2240,C2241,C2242,C2243 CRITICAL TY_CAP_2_2UF
138S0632 12 CAP, 2.2UF, 6.3V, 20%, 0402 C1283,C1283,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296 CRITICAL SS_CAP_2_2UF 138S0633 12 CAP, 2.2UF, 6.3V, 20%, 0402 C1283,C1283,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296 CRITICAL MU_CAP_2_2UF 138S0634 12 CAP, 2.2UF, 6.3V, 20%, 0402 C1283,C1283,C1285,C1286,C1287,C1288,C1291,C1292,C1293,C1294,C1295,C1296 CRITICAL TY_CAP_2_2UF
138S0632 3 CAP, 2.2UF, 6.3V, 20%, 0402 C1622,C1624,C4800 CRITICAL SS_CAP_2_2UF 138S0633 3 CAP, 2.2UF, 6.3V, 20%, 0402 C1622,C1624,C4800 CRITICAL MU_CAP_2_2UF 138S0634 3 CAP, 2.2UF, 6.3V, 20%, 0402 C1622,C1624,C4800 CRITICAL TY_CAP_2_2UF
C 138S0632 10 CAP, 2.2UF, 6.3V, 20%, 0402 C3420,C3421,C3424,C3425,C3430,C3431,C3434,C3435,C3440,C3441 CRITICAL SS_CAP_2_2UF 138S0633 10 CAP, 2.2UF, 6.3V, 20%, 0402 C3420,C3421,C3424,C3425,C3430,C3431,C3434,C3435,C3440,C3441 CRITICAL MU_CAP_2_2UF 138S0634 10 CAP, 2.2UF, 6.3V, 20%, 0402 C3420,C3421,C3424,C3425,C3430,C3431,C3434,C3435,C3440,C3441 CRITICAL TY_CAP_2_2UF C
B
10UF 0603 CAPACITOR VENDOR TABLES FOR ACOUSTICS B
138S0626 10 CAP, 10UF, 6.3V, 20%, 0603 C1200,C1201,C1202,C1203,C1204,C1205,C1206,C1207,C1208,C1209 CRITICAL SS_CAP_10UF 138S0625 10 CAP, 10UF, 6.3V, 20%, 0603 C1200,C1201,C1202,C1203,C1204,C1205,C1206,C1207,C1208,C1209 CRITICAL MU_CAP_10UF 138S0627 10 CAP, 10UF, 6.3V, 20%, 0603 C1200,C1201,C1202,C1203,C1204,C1205,C1206,C1207,C1208,C1209 CRITICAL TY_CAP_10UF
138S0626 3 CAP, 10UF, 6.3V, 20%, 0603 C1230,C1231,C1280 CRITICAL SS_CAP_10UF 138S0625 3 CAP, 10UF, 6.3V, 20%, 0603 C1230,C1231,C1280 CRITICAL MU_CAP_10UF 138S0627 3 CAP, 10UF, 6.3V, 20%, 0603 C1230,C1231,C1280 CRITICAL TY_CAP_10UF
138S0626 9 CAP, 10UF, 6.3V, 20%, 0603 C2190,C2195,C2213,C2219,C2231,C2232,C2260,C2266,C2285 CRITICAL SS_CAP_10UF 138S0625 9 CAP, 10UF, 6.3V, 20%, 0603 C2190,C2195,C2223,C2219,C2231,C2232,C2260,C2266,C2285 CRITICAL MU_CAP_10UF 138S0627 9 CAP, 10UF, 6.3V, 20%, 0603 C2190,C2195,C2223,C2219,C2231,C2232,C2260,C2266,C2285 CRITICAL TY_CAP_10UF
138S0626 6 CAP, 10UF, 6.3V, 20%, 0603 C3490,C3491,C3492,C3590,C3591,C3592 CRITICAL SS_CAP_10UF 138S0625 6 CAP, 10UF, 6.3V, 20%, 0603 C3490,C3491,C3492,C3590,C3591,C3592 CRITICAL MU_CAP_10UF 138S0627 6 CAP, 10UF, 6.3V, 20%, 0603 C3490,C3491,C3492,C3590,C3591,C3592 CRITICAL TY_CAP_10UF
138S0626 8 CAP, 10UF, 6.3V, 20%, 0603 C4109,C4400,C4613,C5066,C7281,C7301,C7350,C7351 CRITICAL SS_CAP_10UF 138S0625 8 CAP, 10UF, 6.3V, 20%, 0603 C4109,C4400,C4613,C5066,C7281,C7301,C7350,C7351 CRITICAL MU_CAP_10UF 138S0627 8 CAP, 10UF, 6.3V, 20%, 0603 C4109,C4400,C4613,C5066,C7281,C7301,C7350,C7351 CRITICAL TY_CAP_10UF
138S0626 8 CAP, 10UF, 6.3V, 20%, 0603 C7502,C7507,C7508,C7541,C7603,C7604,C7650,C7690 CRITICAL SS_CAP_10UF 138S0625 8 CAP, 10UF, 6.3V, 20%, 0603 C7502,C7507,C7508,C7541,C7603,C7604,C7650,C7690 CRITICAL MU_CAP_10UF 138S0627 8 CAP, 10UF, 6.3V, 20%, 0603 C7502,C7507,C7508,C7541,C7603,C7604,C7650,C7690 CRITICAL TY_CAP_10UF
Acoustic Cap BOM Config Tables

A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
D 051-7230 B.0.0

NONE 5 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ICT_TEST
ICT Test Points These nets have a ICT_TEST property This indicates a MUSTHAVE requirement for ICT
TRUE PP18V5_DCIN 6 7 50 72 I126 TRUE NB_CFG<3> 6 7 13 16 I158 TRUE CK505_PCI5_FCTSEL1 29 30 I190 TRUE DVI_HPDET_RC 62 I414 TRUE IDE_IRQ14 23 38 69 I350 TRUE LVDS_A_DATA_N<2> 7 15 60 67 I478 TRUE P1V8S0_EN 51
I95 TRUE BATT_POS 57 58 60 72

I128 TRUE NB_CFG<4> 6 7 13 16 I160 TRUE CK505_PCIF0_CLK 29 30 I192 TRUE EXCARD_OC_L 24 I415 TRUE IDE_PDA<2..0> 23 38 69 I351 TRUE LVDS_A_DATA_P<2> 7 15 60 67 I480 TRUE P3V3S0_EN 51 I493 TRUE PP18V5_DCIN_ONEWIRE 50 72
44 49 51 56
27 28 36 43
I96 TRUE PP3V3_S5 7 8 24 25 26 I127 TRUE NB_CFG<5> 6 7 13 16 I159 TRUE CK505_PCIF1_CLK 29 30 71 I191 TRUE EXTAUSB_OC_F_L 39 I416 TRUE IDE_PDCS1_L 23 38 69 I352 TRUE LVDS_DDC_CLK 7 15 60 I479 TRUE P3V3S3_EN_L 58 I492 TRUE PP18V5_G3H 7 8 50 59 72
41 42 43 44
I97 TRUE PP3V42_G3H 6 7 8 23 26 I129 TRUE NB_CFG<6> 6 7 13 16 I161 TRUE CK505_SRC_CLKREQ6_L 7 29 36 I193 TRUE EXTAUSB_OC_L 7 9 13 24 39 I417 TRUE IDE_PDCS3_L 23 38 69 I353 TRUE LVDS_DDC_DATA 7 15 60 I481 TRUE P3V3TVDAC_EN_RC 22 I494 TRUE PP18V5_S5_CHGR_SW_R 59 72
27 28 39 40
27 30 42 54 72
TRUE GND 57 59 72
I131 TRUE NB_CFG<7> 6 7 13 16 I163 TRUE CK505_USB48_FSA 29 30 I195 TRUE EXTBUSB_OC_L 7 9 13 24 I418 TRUE IDE_PDD<15..0> 23 38 69 I354 TRUE LVDS_IBG 15 60 67 I482 TRUE P3V3TVDAC_NOISE 22 I495 TRUE PP1V05_S0 6 7 8 10 11 12 13
14 18 19 21 23 26
I100 TRUE PM_SLP_S3_L 6 7 25 36 37 I130 TRUE NB_CFG<8> 6 7 13 16 I162 TRUE CK505_XTAL_OUT 29 I194 TRUE EXTGPU_LVDS_EN 7 13 24 I419 TRUE IDE_PDDACK_L 23 38 69 I355 TRUE LVDS_VDD_EN 15 60 I483 TRUE P3V42G3H5_BOOST 57 I496 TRUE PP1V05_S0_NB_VCCPEG 15 19 21 72
41 42 51 55
I99 TRUE PM_S4_STATE_L 6 25 36 41 58 I132 TRUE NB_CFG<9> 6 16 I164 TRUE CLINK_NB_CLK 16 25 70 I196 TRUE EXT_COMPVID_B 63 67 I420 TRUE IDE_PDDREQ 23 38 69 I356 TRUE MEM_ODT<3..0> 16 31 32 I485 TRUE P3V42G3H_SHDN_L 57 I498 TRUE PP1V25_S0 6 7 8 16 18 19 21
33 68 26 27 51 57 72
I101 TRUE PM_SLP_S5_L 6 25 41 42 I134 TRUE NB_RESET_L 6 16 28 I166 TRUE CLINK_NB_DATA 16 25 70 I198 TRUE EXT_C_R 63 67 I421 TRUE IDE_PDIORDY 23 38 69 I357 TRUE MEM_RCOMP 16 I484 TRUE P3V42G3H_SHDN_L1 57 I497 TRUE PP1V25_S0M_NB_VCCA_HPLL 19 21 72
D I102
I104
TRUE
TRUE
SMC_PM_G2_EN
IMVP_VR_ON
6 41 56 58
6 41 52
I133
I135
TRUE
TRUE
NB_SB_SYNC_L 6 16 25
NB_TEST1 6 16
I165
I167
TRUE
TRUE
CLINK_NB_RESET_L 16 25 70
CLK_PWRGD 25 29
I197
I199
TRUE
TRUE
EXT_Y_G
FAN_RT_PWM
63 67
7 47
I422
I424
TRUE
TRUE
IDE_PDIOR_L
IDE_PDIOW_L
23 38 69
23 38 69
I358
I360
TRUE
TRUE
MEM_RCOMP_L
MEM_RCOMP_VOH
16
16
I486
I487
TRUE
TRUE
P5VS0_EN
P5VS3_EN_L
51
58
I499
I500
TRUE
TRUE
PP1V25_S0_NB_DPLL 22 72
PP1V25_S0_NB_PEGPLL 19 21 72
D
I103 TRUE GFX_VR_EN 6 9 16 53 I136 TRUE NB_TEST2 6 16 I168 TRUE CPU_A20M_L 6 10 23 66 I200 TRUE FAN_RT_TACH 7 47 I423 TRUE IDE_RESET_BUF_L 38 I359 TRUE MEM_RCOMP_VOL 16 I488 TRUE PBUS_ISENSE_IN_NEG 59 I501 TRUE PP1V25_S0_NB_PEGPLL_RC 21 72
I105 TRUE SMC_BATT_CHG_EN 6 41 42 I137 TRUE 1V05S0_RUNSS 51 54 I169 TRUE CPU_BSEL<0> 10 30 66 I201 TRUE FRANKCARD_GPIO 25 43 I425 TRUE IDE_RESET_L 24 38 I361 TRUE NB_BSEL<0> 6 7 13 16 I490 TRUE PBUS_ISENSE_VREG 59 I503 TRUE PP1V25_S0_NB_VCCA_DPLLA 19 22 72
30 66
I107 TRUE SMC_ONOFF_L 6 7 40 41 42 I138 TRUE 1V05S0_TRIP 54 I170 TRUE CPU_BSEL<1> 10 30 66 I202 TRUE FSB_CLK_CPU_N 10 29 30 71 I427 TRUE IMVP6_BOOT 52 I363 TRUE NB_BSEL<1> 6 7 13 16 I489 TRUE PBUS_S0_SMC_VSENSE 45 I502 TRUE PP1V25_S0_NB_VCCA_DPLLB 19 22 72
30 66 59
I106 TRUE ALL_SYS_PWRGD_AND 6 51 I139 TRUE 1V25S0_RUNSS 51 57 I171 TRUE CPU_BSEL<2> 10 30 66 I203 TRUE FSB_CLK_CPU_P 10 29 30 71 I426 TRUE IMVP6_BOOT_RC 52 I362 TRUE NB_BSEL<2> 6 7 13 16 I517 TRUE PBUS_SMC_VSENSE_EN_L I508
42 45 TRUE PP1V5_S0 6 7 8 11 12 22 26
30 66 27 54 72
I108 TRUE PPVBAT_G3H_CHGR_REG 6 59 72 I141 TRUE 1V51V05S0_V5FILT 54 I173 TRUE CPU_COMP<0> 10 66 I205 TRUE FSB_CLK_NB_N 14 29 30 71 I428 TRUE IMVP6_COMP_R 52 I364 TRUE NB_CFG<16> 6 16 I519 TRUE PCIE_CLK100M_MINI_N I506 TRUE PP1V5_S0_NB_QDAC 22 72
I109 TRUE CPU_PWRGD 6 10 13 23 66 I140 TRUE 1V5S0_RUNSS 51 54 I172 TRUE CPU_COMP<1> 10 66 I204 TRUE FSB_CLK_NB_P 14 29 30 71 I429 TRUE IMVP6_DROOP 52 I365 TRUE NB_CFG<19> 6 16 I518 TRUE PCIE_CLK100M_MINI_N_F I507
7 36 TRUE PP1V5_S0_NB_VCCD_CRT 19 22 72
I110 TRUE PM_RSMRST_L 6 25 41 I142 TRUE 1V5S0_TRIP 54 I174 TRUE CPU_COMP<2> 10 66 I206 TRUE FSB_CPURST_L 10 13 14 66 I430 TRUE IMVP6_PHASE 52 I366 TRUE NB_CFG<20> 6 16 I520 TRUE PCIE_CLK100M_MINI_P I505 TRUE PP1V5_S0_NB_VCCD_QDAC 19 22 72
I112 TRUE PM_PWRBTN_L 6 25 41 I143 TRUE 1V8S3_CS 55 I175 TRUE CPU_COMP<3> 10 66 I207 TRUE FWH_MFG_MODE 25 I432 TRUE IMVP6_PVCC 52 I368 TRUE NB_CFG<3> 6 7 13 16 I521 TRUE PCIE_CLK100M_MINI_P_F 7 I504 TRUE PP1V5_S0_SB_VCC1_5_B 23 24 26 27 72
36
I111 TRUE TP_PCI_RST_L 9 24 I144 TRUE 1V8S3_V5FILT 55 I176 TRUE CPU_DPRSTP_L 6 10 16 23 52 I208 TRUE GCORE_BST_D 53 I431 TRUE IMVP6_RBIAS 52 I367 TRUE NB_CFG<4> 6 7 13 16 I522 TRUE PCIE_E_D2R_N 24 36 70 I514 TRUE PP1V5_S0_SB_VCCDMIPLL 26 27 72
66
I113 TRUE PLT_RST_L 6 7 24 28 60 I146 TRUE 1V8S3_VDDQSET 55 I178 TRUE CPU_DPSLP_L 6 10 23 66 I210 TRUE GCORE_COMP_R 53 I433 TRUE IMVP6_SOFT 52 I369 TRUE NB_CFG<5> 6 7 13 16 I523 TRUE PCIE_E_D2R_N_F 7 36 I512 TRUE PP1V5_S0_SB_VCCDMIPLL_F 27 72
64
I115 TRUE SMC_RESET_L 6 41 42 43 I145 TRUE 3V3S5_CS 56 I177 TRUE CPU_FERR_L 6 10 23 66 I209 TRUE GCORE_CSFB 53 I434 TRUE IMVP6_VDIFF 52 I370 TRUE NB_CFG<6> 6 7 13 16 I524 TRUE PCIE_E_D2R_P 24 36 70 I513 TRUE PP1V5_S0_SB_VCCSATAPLL 26 27 72
41
28
I114 TRUE PM_SYSRST_L 6 27 54 72 I147 TRUE 5V3V3S5_TONSEL 56 I179 TRUE CPU_GTLREF 10 66 I211 TRUE GCORE_FBRTN 53 I435 TRUE IMVP6_VDIFF_RC 52 I371 TRUE NB_CFG<7> 6 7 13 16 I525 TRUE PCIE_E_D2R_P_F 7 36 I511 TRUE PP1V8_S0 6 7 8 19 22 51 61
2511 12 22 26 72
8
I116 TRUE PP1V5_S0 54 672
I149 TRUE 5V3V3S5_V5FILT 56 I181 TRUE CPU_IERR_L 10 66 I213 TRUE GCORE_LLINE 53 I436 TRUE IMVP6_VO_R 52 I372 TRUE NB_CFG<8> 6 7 13 16 I527 TRUE PCIE_E_R2D_C_N 24 36 70 I510 TRUE PP1V8_S0_ANALOG_SDVO_F 61 72
23 726 27 30
13 14 18 19
I118 TRUE PP1V05_S0 6 7 8 10 11 I148 TRUE 5V3V3S5_VREF 56 I180 TRUE CPU_IGNNE_L 10 23 66 I212 TRUE GCORE_PMON 53 I437 TRUE IMVP6_VR_TT 52 I373 TRUE NB_CFG<9> 6 16 I526 TRUE PCIE_E_R2D_C_N_F 7 36 I509 TRUE PP1V8_S0_ANALOG_TMDS_F 61 72
12 42
PP1V8_S0 2161 72 5V3V3S5_VREG3 56 CPU_INIT_L GCORE_PMONFS IMVP6_VSEN_N NB_CLINK_VREF PCIE_E_R2D_C_P 24 36 70 PP1V8_S0_NB_VCCTXLVDS 19 22 72
I117 TRUE 72
6 7 8 19 22
51 I151 TRUE I183 TRUE 10 23 66 I215 TRUE 53 I438 TRUE 52 66 I374 TRUE 16 70 I528 TRUE I515 TRUE
NB_CLK100M_DPLLSS_N 30
35 51 55 68 71
I119 TRUE PP1V8_S3 6 7 8 16 18 I150 TRUE 5VS5_CS 56 I182 TRUE CPU_INTR 10 23 66 I214 TRUE GCORE_PWRGD 53 I439 TRUE IMVP6_VSEN_P 52 66 I375 TRUE 9 16
I529 TRUE PCIE_E_R2D_C_P_F 7 36 I516 TRUE PP1V8_S0_PVCC1_TMDS_F 61 72
21 31 32 34 29
71
I120 TRUE PP0V9_S0 6 7 8 33 55 I152 TRUE 5VS5_VREG 56 I184 TRUE CPU_NMI 10 23 66 I216 TRUE GCORE_RAMP 53 I440 TRUE IMVP6_VSUM 52 I376 TRUE NB_CLK100M_DPLLSS_P 9291630 I551 TRUE PCIE_E_R2D_N 36 I534 TRUE PP1V8_S0_PVCC2_TMDS_F 61 72
72
55 72
I121 TRUE PP0V9_S3 72
6 8 31 32 I154 TRUE ADAPTER_SENSE 50 I186 TRUE CPU_PROCHOT_BUF 42 I218 TRUE GCORE_RPM 53 I441 TRUE IMVP6_VW 52 I377 TRUE NB_CLK100M_PCIE_N 71
16 29 30
I553 TRUE PCIE_E_R2D_P 36 I532 TRUE PP1V8_S0_TMDS_F 61 72
26 27 51 57 72
I122 TRUE PP1V25_S0 6 7 8 16 18 I153 TRUE AIRPORT_RST_L 7 28 36 I185 TRUE CPU_PROCHOT_L 10 42 52 66 I217 TRUE GCORE_RT 53 I442 TRUE IMVP_DPRSLPVR 52 66 I378 TRUE NB_CLK100M_PCIE_P 16 29 30 I552 TRUE PCIE_WAKE_L 7 25 36 I533 TRUE PP1V8_S3 6 7 8 16 18 21 31
19 21 71 32 34 35 51 55 68
58 72
I123 TRUE PP5V_S5 6 7 8 27 39 I155 TRUE ALL_SYSPWRGD_DLY 51 I187 TRUE CPU_PROCHOT_L_R 42 I219 TRUE GCORE_ST 53 I443 TRUE IMVP_VR_ON 6 41 52 I379 TRUE NB_CLK96M_DOT_N 9 16 29 30 I554 TRUE PCI_CLK33M_LPCPLUS 30 43 I531 TRUE PP1V8_S3M_NB_VCCSMCK 19 21 72
51 54 55 56 71 71
I125 TRUE PP5V_S3 6 7 8 40 58 I156 TRUE ALL_SYS_PWRGD 28 41 51 52 I188 TRUE CPU_PWRGD 6 10 13 23 66 I220 TRUE GCORE_SW 53 I445 TRUE INT_PIRQA_L 24 70 I381 TRUE NB_CLK96M_DOT_P 9 16 29 30 I555 TRUE PCI_CLK33M_SB 24 30 71 I530 TRUE PP1V8_S3_NB_VCCSMCK_RC 21 72
60 72 71
28 29 30 42 44 46
I124 TRUE PP5V_S0 I157 TRUE ALL_SYS_PWRGD_AND 6 51 I189 TRUE CPU_SMI_L 10 23 66 I221 TRUE GCORE_SW_R 53 I444 TRUE INT_PIRQB_L 24 70 I380 TRUE NB_CLKREQ_L 16 29 I556 TRUE PCI_CLK33M_SMC 30 41 71 I540 TRUE PP3V3_A_S0 6 7 8 13 16 19 21
22 23 24 25 26 27
53 60 63 64
I292 TRUE PP3V3_S3 44 46 51 52
I273 TRUE ARB_DETECT_L 25 I254 TRUE CPU_STPCLK_L 10 23 66 I222 TRUE GCORE_VARFREQ 53 I447 TRUE INT_PIRQC_L 24 70 I383 TRUE NB_FSB_RCOMP 14 I557 TRUE PCI_DEVSEL_L 24 70 I538 TRUE PP3V3_B_S0 51 52 53 60 63 64
6
28 29 30 42 8 38 47 51 61 62 63
24 25 26 27
I294 TRUE PP3V3_A_S0 6 7 8 13 16 I274 TRUE AUD_MIC_CLK 7 37 60 I255 TRUE CPU_THERMD_N 10 46 66 I223 TRUE GCORE_VCC 53 I446 TRUE INT_PIRQD_L 24 70 I382 TRUE NB_FSB_SCOMP 14 I558 TRUE PCI_FRAME_L 24 70 I539 TRUE PP3V3_LCDVDD_SW 60 72
19 21 22 23
63
I293 TRUE PP3V3_B_S0 6 8 38 47 51 I275 TRUE AUD_MIC_CLK_F 60 I256 TRUE CPU_THERMD_P 10 46 66 I224 TRUE GCORE_VDC_DIV 53 I448 TRUE INT_PIRQE_L 24 70 I384 TRUE NB_FSB_SCOMP_L 14 I559 TRUE PCI_FW_GNT_L 24 70 I537 TRUE PP3V3_LCDVDD_SW_F 7 60 72
C I295 TRUE
TRUE
PPVCORE_S0_CPU 65 72
52 65 72
61 62
6 7 8 11 12
PPVCORE_S0_NB_GFX 6 7 8 18
I276 TRUE
TRUE
AUD_MIC_DATA 7 37 60
AUD_MIC_DATA_F 60
I257 TRUE
TRUE
CPU_THERMTRIP_R 23
CPU_VCCSENSE_N 11 52 66
I225 TRUE
TRUE
GCORE_VRPM
GFX_VID<3..0>
53
16 22 53
I450 TRUE
TRUE
INT_PIRQF_L
INT_SERIRQ
24 70
25 41 43
I386 TRUE
TRUE
NB_FSB_SWING
NB_FSB_VREF
14
14
I561 TRUE
TRUE
PCI_FW_REQ_L
PCI_IRDY_L
24 70
24 70
I536 TRUE
TRUE
PP3V3_S0_ANALOG_SDVO_F 61 72
PP3V3_S0_CK505_VDD48 72
C
I297 22 45 53 I277 I258 I226 I449 I385 I560 I535
I296 TRUE XDP_TCK 6 7 10 13 66 I278 TRUE BATT_POS 6 7 50 I259 TRUE CPU_VCCSENSE_P 11 52 66 I227 TRUE GFX_VR_EN 6 9 16 53 I452 TRUE LAN_ENERGY_DET 23 I388 TRUE NB_RESET_L 6 16 28 I562 TRUE PCI_LOCK_L 24 70 I544 TRUE PP3V3_S0_CK505_VDDA 72
I298 TRUE XDP_TDI 6 7 10 13 66 I279 TRUE BATT_POS_F 50 59 I260 TRUE CPU_VID<6..0> 11 12 52 66 I228 TRUE GLAN_COMP 23 70 I451 TRUE LAN_PHYPC 23 25 I387 TRUE NB_SB_SYNC_L 6 16 25 I563 TRUE PCI_PERR_L 24 70 I545 TRUE PP3V3_S0_CK505_VDDA_R 72
I300 TRUE XDP_TDO 6 7 10 13 66 I280 TRUE BOOTROM_OVR_EN_L 23 25 43 I261 TRUE CRT_BLUE 15 63 67 I229 TRUE GND_1V51V05S0_SGND 54 I453 TRUE LCDBKLT_ENA 64 I389 TRUE NB_TEST1 6 16 I564 TRUE PCI_PME_FW_L 25 I541 TRUE PP3V3_S0_CK505_VDD_CPU_SRC 29 72
I299 TRUE XDP_TMS 6 7 10 13 66 I281 TRUE CHGR_AGATE 59 I262 TRUE CRT_GREEN 15 63 67 I230 TRUE GND_1V8S3_CSGND 55 I455 TRUE LCDBKLT_ISET 64 I391 TRUE NB_TEST2 6 16 I565 TRUE PCI_REQ1_L 24 70 I543 TRUE PP3V3_S0_CK505_VDD_PCI 72
I301 TRUE XDP_TRST_L 6 7 10 13 66 I283 TRUE CHGR_AMON 59 I264 TRUE CRT_HSYNC_LS 63 I232 TRUE GND_1V8S3_SGND 55 I454 TRUE LCDBKLT_OVP 64 I390 TRUE NB_VCCSM_LF1 18 68 I566 TRUE PCI_REQ2_L 24 70 I542 TRUE PP3V3_S0_CK505_VDD_REF 72
I302 TRUE XDP_CPURST_L 6 7 13 66 I282 TRUE CHGR_BGATE 59 I263 TRUE CRT_HSYNC_LS_R 63 I231 TRUE GND_5V3V3S5_SGND 56 I457 TRUE LCDBKLT_PWM_UNBUF 9 15 64 I393 TRUE NB_VCCSM_LF2 18 68 I568 TRUE PCI_SERR_L 24 70 I549 TRUE PP3V3_S0_HDCP_F 62
I303 TRUE XDP_BPM_L<4> 6 7 10 13 66 I284 TRUE CHGR_BMON 59 I265 TRUE CRT_HSYNC_R 15 63 67 I233 TRUE GND_ALS_F I456 TRUE LCDBKLT_PWREN 9 15 64 I392 TRUE NB_VCCSM_LF3 18 68 I567 TRUE PCI_STOP_L 24 70 I550 TRUE PP3V3_S0_IMVP6_3V3 52 72
I304 TRUE XDP_BPM_L<5> 6 7 10 13 66 I286 TRUE CHGR_BOOT 59 I267 TRUE CRT_RED 15 63 67 I235 TRUE GND_CHGR_SGND 59 I458 TRUE LCDBKLT_RT 64 I394 TRUE NB_VCCSM_LF4 18 68 I569 TRUE PCI_TRDY_L 24 70 I546 TRUE PP3V3_S0_LCD_F 7 60 72
I305 TRUE XDP_DBRESET_L 6 7 10 13 28 I285 TRUE CHGR_CSIN 59 I266 TRUE CRT_TVO_IREF 15 63 67 I234 TRUE GND_GCORE_PGND 53 I460 TRUE LCDBKLT_RTN<6..1> 7 60 64 I396 TRUE NB_VCCSM_LF5 18 68 I571 TRUE PEG_COMP 15 I548 TRUE PP3V3_S0_NBCORE_FOLLOW_R 21 72
I307 TRUE XDP_PWRGD 6 7 13 I287 TRUE CHGR_CSIP 59 I268 TRUE CRT_VSYNC_LS 63 I236 TRUE GND_IMVP6_SGND 52 I459 TRUE LCDBKLT_RTN_RC<6..1> 64 I395 TRUE NB_VCCSM_LF6 18 68 I570 TRUE PEG_D2R_N<1> 15 61 67 I547 TRUE PP3V3_S0_NB_CRTDAC_F 22 72
I306 TRUE SPI_A_SCLK_R 6 43 49 69 I288 TRUE CHGR_CSON 59 I269 TRUE CRT_VSYNC_LS_R 63 I237 TRUE GND_LCDBKLT_GNDA 64 I462 TRUE LCDBKLT_SSTCMP 64 I398 TRUE NB_VCCSM_LF7 18 68 I577 TRUE PEG_D2R_P<1> 15 61 67 I574 TRUE PP3V3_S0_NB_TVDAC 22 72
I308 TRUE SMC_MANUAL_RST_L 6 42 I289 TRUE CHGR_CSOP 59 I270 TRUE CRT_VSYNC_R 15 63 67 I238 TRUE GND_P1V2S3_SGND 57 I461 TRUE LCDBKLT_SSTCMP_RC 64 I397 TRUE NB_VTTLF_CAP1 19 I578 TRUE PEG_R2D_C_N<3..0> 15
67
61
I575 TRUE PP3V3_S0_NB_TVDAC_F 22 72
I309 TRUE SMC_TCK 6 41 42 43 I291 TRUE CHGR_DCIN 59 I272 TRUE DEBUG_RESET_L 28 43 I240 TRUE GND_SMC_AVSS 41 42 45 53 59 I463 TRUE LCDBKLT_VREF 64 I399 TRUE NB_VTTLF_CAP2 19 I579 TRUE PEG_R2D_C_P<3..0> 15 61 I576 TRUE PP3V3_S0_NB_TVDAC_FOLLOW 22 72
67
I310 TRUE SMC_TDI 6 41 42 43 I290 TRUE CHGR_LOWCURRENT_GATE 59 I271 TRUE DLY_OFF_A 51 I239 TRUE HDA_BIT_CLK 7 9 23 37 69 I465 TRUE LCDVDD_PWREN_L 60 I401 TRUE NB_VTTLF_CAP3 19 I580 TRUE PGOOD_1V25S0 51 57 I573 TRUE PP3V3_S0_NB_VCCA_CRTDAC 19 22 72
I338 TRUE SMC_TDO 6 41 42 43 I324 TRUE CHGR_LOWCURRENT_REF 59 I311 TRUE DLY_OFF_B 51 I241 TRUE HDA_BIT_CLK_R 23 69 I464 TRUE LCDVDD_PWREN_L_R 60 I400 TRUE ODD_PWR_EN_L 24 I581 TRUE PGOOD_1V8S3 51 55 I572 TRUE PP3V3_S0_NB_VCCA_DAC_BG 19 22 72
I337 TRUE SMC_TMS 6 41 42 43 I325 TRUE CHGR_SGATE 59 I312 TRUE DLY_OFF_C 51 I242 TRUE HDA_DOCK_EN_L 23 I466 TRUE LOCAL_CTRL_CLK 7 13 15 I402 TRUE ONEWIRE_DCIN_DIV 50 I601 TRUE PLT_RST_BUF_L 28 I582 TRUE PP3V3_S0_NB_VCCA_TVDACA 19 22 72
I339 TRUE SMC_TRST_L 6 41 43 I326 TRUE CHGR_SGATE_DIV 59 I313 TRUE DLY_OFF_D 51 I243 TRUE HDA_RST_L 9 23 37 69 I468 TRUE LOCAL_CTRL_DATA 7 13 15 I404 TRUE ONEWIRE_EN 50 I603 TRUE PLT_RST_L 6 7 24 28 I583 TRUE PP3V3_S0_NB_VCCA_TVDACB 19 22 72
60 64
I341 TRUE CPU_A20M_L 6 10 23 66 I327 TRUE CHGR_VCOMP_R 59 I314 TRUE DMI_IRCOMP_R 24 I244 TRUE HDA_RST_L_R 23 69 I467 TRUE LPC_AD<3..0> 23 41 43 I403 TRUE ONEWIRE_ESD 50 I602 TRUE PM_BATLOW_L 25 41 I584 TRUE PP3V3_S0_NB_VCCA_TVDACC 19 22 72
I340 TRUE CPU_DPRSTP_L 6 10 16 23 52 I328 TRUE CHGR_VDD 59 I315 TRUE DMI_N2S_N<3..0> 16 24 67 I245 TRUE HDA_SDIN0 7 9 23 37 69 I470 TRUE LPC_FRAME_L 23 41 43 I406 TRUE ONEWIRE_OV 50 I604 TRUE PM_BMBUSY_L 16 25 I589 TRUE PP3V3_S0_SPVCC_TMDS_F 61 72
66
I343 TRUE CPU_DPSLP_L 6 10 23 66 I329 TRUE CHGR_VDDP 59 I316 TRUE DMI_N2S_P<3..0> 16 24 67 I246 TRUE HDA_SDIN1 I469 TRUE LSOC_H I405 TRUE ONEWIRE_PWR_EN_L 50 I606 TRUE PM_CLKRUN_L 25 41 43 I586 TRUE PP3V3_S3 6 7 8 36 42 44 48
51 58 60 72
I342 TRUE CPU_FERR_L 6 10 23 66 I330 TRUE CHGR_VNEG 59 I317 TRUE DMI_S2N_N<3..0> 16 24 67 I247 TRUE HDA_SDOUT 7 9 23 37 69 I471 TRUE LSOC_H_R 7 I407 TRUE ONEWIRE_PWR_EN_L_DIV 50 I605 TRUE PM_DPRSLPVR 16 25 52 I585 TRUE PP3V3_S3_ALS_F
66
I344 TRUE NB_BSEL<0> 6 7 13 16 30 I331 TRUE CHGR_VNEG_R 59 I318 TRUE DMI_S2N_P<3..0> 16 24 67 I248 TRUE HDA_SDOUT_R 23 69 I473 TRUE LVDS_A_CLK_F_N 7 60 I409 TRUE P1V25S0NBDPLL_FB 22 I608 TRUE PM_EXTTS_L<0> 16 41 I588 TRUE PP3V3_S3_AP_AUX 7 36 72
66
I346 TRUE NB_BSEL<1> 6 7 13 16 30 I332 TRUE CK505_CLK14P3M_TIMER 30 29
I319 TRUE DVI_HOST 7 37 63 I249 TRUE HDA_SYNC 7 9 23 37 69 I472 TRUE LVDS_A_CLK_F_P 7 60 I408 TRUE P1V25S0NBDPLL_RF 22 I607 TRUE PM_EXTTS_L<1> 16 41 I587 TRUE PP3V3_S5_AVREF_SMC 41 42 72
66
I345 TRUE NB_BSEL<2> 6 7 13 16 30 I333 TRUE CK505_FSA 30 71 I320 TRUE DVI_HOTPLUG_DET 24 61 62 I250 TRUE HDA_SYNC_R 23 69 I475 TRUE LVDS_A_CLK_N 15 60 67 I411 TRUE P1V25S0_ITH 57 I609 TRUE PM_LAN_ENABLE 25 41 I594 TRUE PP3V3_S5_SMC_AVCC 41 72
66
B I347
I348
TRUE
TRUE
NB_CFG<16>
NB_CFG<19>
6 16
6 16
I334
I336
TRUE
TRUE
CK505_FSB_TEST_MODE 29
CK505_FSC 30 71
30 I321
I323
TRUE
TRUE
DVI_HOTPLUG_DET_BUF 61 62
DVI_HOTPLUG_DET_DEL_L 62
I251
I253
TRUE
TRUE
HDMI_HOST 7 37 63
I2C_TOP_ALS_SCL_F 60
I474
I476
TRUE
TRUE
LVDS_A_CLK_P 15 60 67
LVDS_A_DATA_F_N<2..0> 60 67
I410
I412
TRUE
TRUE
P1V25S0_ITH_RC
P1V25S0_MODE
57
57
I611
I610
TRUE
TRUE
PM_LAN_PWRGD 41 42
PM_LATRIGGER_L 7 13 24
I591
I590
TRUE
TRUE
PP3V42G3H_SW
PP3V42_G3H
57 72
57 59 72
6 7 8 23 26 27 28
B
39 40 41 42 43 44
I349 TRUE NB_CFG<20> 6 16 I335 TRUE CK505_PCI3_CLK 29 30 71 I322 TRUE DVI_HOTPLUG_DET_INT_L 62 I252 TRUE I2C_TOP_ALS_SDA_F 60 I477 TRUE LVDS_A_DATA_F_P<2..0> 60 67
I413 TRUE P1V25S0_RT 57 I612 TRUE PM_PWRBTN_L 6 25 41 I593 TRUE PP3V42_G3H_IPD_F 7 40
I613 TRUE PM_RI_L 25 I592 TRUE PP3V42_G3H_SMCUSBMUX_R 39 72

42
I639 TRUE PPVBAT_G3H_CHGR_OUT 59 72 I620 TRUE SB_INTVRMEN 23 I726 TRUE SMC_BS_ALRT_L 7 41 42 50 I691 TRUE SMC_TMS 6 I796 TRUE SST8051_RST 62 I761 TRUE TMDS_TX_CLK_N I857 TRUE VGA_B I614 TRUE PM_RSMRST_L 6 25 41 I599 TRUE PP5V_S0 6 7 8 22 27 40 43
41 67 47 51 52 53 63 72
63
I641 TRUE PPVBAT_G3H_CHGR_REG 6 59 72 I621 TRUE SB_LAN100_SLP 23 I725 TRUE SMC_CASE_OPEN 41 42 I690 TRUE SMC_TRST_L 43
I795 TRUE SST8051_SW_RESET_L 25 62 I760 TRUE TMDS_TX_CLK_P I858 TRUE VGA_G 7 I616 TRUE PM_S4_STATE_L 6 25 36 41 I597 TRUE PP5V_S0_DVIPORT 7 37 63 72
37 58
42
I640 TRUE PPVBAT_G3H_CHRGR_REG_0 59 72 I622 TRUE SB_RCIN_L 23 I728 TRUE SMC_DCIN_ISENSE 41 59 I692 TRUE SMC_TX_L 39 I798 TRUE SST8051_UPDATE_L 25 62 I762 TRUE TMDS_TX_CONN_CLK_N I860 TRUE VGA_HSYNC 67
I615 TRUE PM_SB_PWROK 9 25 28 I596 TRUE PP5V_S0_DVIPORT_D 63 72
41 63
37 51 55
I642 TRUE PPVBAT_G3H_CHRGR_REG_R 59 72 I627 TRUE SB_RTC_RST_L 23 28 I727 TRUE SMC_EXTAL 41 42 I693 TRUE SMC_VCL 43
I797 TRUE SST8051_XTAL1 62 I763 TRUE TMDS_TX_CONN_CLK_P I859 TRUE VGA_R 7 I618 TRUE PM_SLP_S3_L 6 7 25 36 I595 TRUE PP5V_S0_IMVP6_VDD 52 72
41 37 41 42
I644 TRUE PPVCORE_S0_CPU 72
6 7 8 11 I624 TRUE SB_RTC_X1 23 28 I729 TRUE SMC_FAN_0_CTL 41 47 I694 TRUE SMC_WAKE_SCI_L 25
7 I799 TRUE SST8051_XTAL2 62 I764 TRUE TMDS_TX_CONN_N<2..0> I864 63 7 37 TRUE VGA_VSYNC 63
7 I617 TRUE PM_SLP_S4_LS5V 39 58 I598 TRUE PP5V_S0_KBDLED_F 7 40 72
12 52 65 13 37
I643 TRUE PPVCORE_S0_NB_GFX I623 TRUE SB_RTC_X1_R 28 I731 TRUE SMC_FAN_0_TACH 41 47 I695 TRUE SMC_XTAL 41 I801 TRUE SUS_CLK_SB 25 42 I765 TRUE TMDS_TX_CONN_P<2..0> I863 63 7 37 TRUE VR_PWRGD_CK505 I619 TRUE PM_SLP_S5_L 6 25 41 42 I600 TRUE PP5V_S0_SB_V5REF 26 27 72
42
I646 TRUE PPVDCIN_G3H_PRE 45 59 72 I626 TRUE SB_RTC_X2 23 28 I730 TRUE SMC_GPU_ISENSE 41 53 I696 TRUE SMS_MOT_EN 48 I800 TRUE SYS_ONEWIRE 7 41 42 50 I766 TRUE TMDS_TX_N<2..0> I861 TRUE VR_PWRGD_CK505_L I836 28 52 TRUE PM_STPCPU_L 25 29 30 I834 TRUE PP5V_S0_TMDS_FUSE 63 72
28 52
I645 TRUE PPVDCIN_G3H_PRE2 59 72 I625 TRUE SB_SLOAD 25 I732 TRUE SMC_GPU_VSENSE 41 45 I697 TRUE SMS_ONOFF_L 41 I802 TRUE SYS_ONEWIRE_BILAT 50 I767 TRUE TMDS_TX_P<2..0> I862 TRUE VR_PWRGOOD_DELAY I835 9 16 TRUE PM_STPPCI_L 25 29 30 I832 TRUE PP5V_S3 6 7 8 40 58 60 72
48
I647 TRUE PPVDCIN_G3H_PRE_0 59 72 I632 TRUE SB_SM_INTRUDER_L 23 28 I734 TRUE SMC_KBC_MDE 41 I698 TRUE SMS_X_AXIS 41 I804 TRUE THRM_CPU_ALERT_L 46 I768 TRUE TV_A_DAC I866 TRUE WOL_EN 25 I837 TRUE PM_SUS_STAT_L 25 41 43 I833 TRUE PP5V_S3_CAMERA_F 7 60 72
48
24
I649 TRUE PPVDCIN_G3H_PRE_R 59 72 I629 TRUE SB_SPKR 25 I733 TRUE SMC_LID 7 40 41 42 I700 TRUE SMS_Y_AXIS 41 I803 TRUE THRM_CPU_DXN 46 I770 TRUE TV_B_DAC I865 TRUE WOW_EN 7 I839 TRUE PM_SYSRST_L 6 25 28 41 I830 TRUE PP5V_S3_TOPCASE_F 7 40
48 13
I648 TRUE PPVIN_S5_IMVP6_VIN 52 72 I628 TRUE SDVO_CTRLCLK 16 61 I736 TRUE SMC_LRESET_L 28 41 I701 TRUE SMS_Z_AXIS 41 I806 TRUE THRM_CPU_DXP 46 I771 TRUE TV_C_DAC I867 TRUE XDP_BPM_L<0> 36 I838 TRUE PM_THRMTRIP_L 10 16 23 I831 TRUE PP5V_S3_USB2_EXTA 39 72
48 66 42 66
I650 TRUE PPVOUT_S0_LCDBKLT 7 60 64 72 I631 TRUE SDVO_CTRLDATA 16 61 I735 TRUE SMC_MANUAL_RST_L 6 42 I699 TRUE SPI_A_INT_CLK 49 I805 TRUE THRM_CPU_THM_L 46 I769 TRUE TV_DCONSEL<1> I868 TRUE XDP_BPM_L<1> 13
7 I849 TRUE PM_THRM_L 25 I844 TRUE PP5V_S3_USB2_EXTA_F 7 37 39 72
10
I651 TRUE PPVOUT_S0_LCDBKLT_SW 64 72 I630 TRUE SMBUS_SB_ME_SCL 25 44 I737 TRUE SMC_MANUAL_RST_L1 42 I702 TRUE SPI_A_INT_HOLD_L 49 I807 TRUE TMDS_DDC_SCL 7 37 61 62 I772 TRUE USB2_AIRPORT_N I869 TRUE XDP_BPM_L<2> 66 I850 TRUE PM_WLAN_EN_L 36 I842 TRUE PP5V_S5 6 7 8 27 39 51 54
69 63 67 13 55 56 58 72
I652 TRUE RSMRST_PWRGD 41 42 56 I637 TRUE SMBUS_SB_ME_SDA 25 44 I739 TRUE SMC_MD1 41 43 I703 TRUE SPI_A_INT_SI 49 I809 TRUE TMDS_DDC_SDA 7 37 61 62 I773 TRUE USB2_AIRPORT_N_F I870 TRUE XDP_BPM_L<3> 710 I851 TRUE PM_WLAN_EN_L1 36 I843 TRUE PP5V_S5_SB_V5REF_SUS 26 27 72
69 63 67
I654 TRUE RSVD_EXTGPU_LVDS_EN 25 I635 TRUE SMBUS_SB_SCL 25 29 I738 TRUE SMC_NMI 41 43 I704 TRUE SPI_A_INT_WP_L 69
I808 TRUE TMDS_EXT_RES 61 I774 TRUE USB2_AIRPORT_P I871 TRUE XDP_BPM_L<4> 13
6 7 I853 TRUE PM_WLAN_EN_L2 36 I840 TRUE PPBUS_G3H 7 8 37 45 50 56 59 64 72
44 69 49 10
43
I653 TRUE RUNSS_GATE_D 51 I634 TRUE SMBUS_SB_SDA I741 TRUE SMC_ODD_DETECT 41 42 I705 TRUE SPI_A_SCLK_R 6 I811 TRUE TMDS_EXT_SWING 61 I775 TRUE USB2_AIRPORT_P_F I872 TRUE XDP_BPM_L<5> 66 I852 TRUE PM_WLAN_EN_L_SS 36 I841 TRUE PPBUS_R_G3H 7 8 42 52 53 54 55 59 72
66
I656 TRUE RUNSS_GATE_D_L 51 I633 TRUE SMBUS_SMC_0_S0_SCL 71

7 41 I740 TRUE SMC_ONOFF_H 40 42 57 I706 TRUE SPI_A_SI_R 69
43 I810 TRUE TMDS_HTPLG 7 37 61 63 I776 TRUE USB2_CAMERA_F_N I874 TRUE XDP_CLK_N 29
7 I855 TRUE PP0V9_S0 6 7 8 33 I847 TRUE PPDCIN_G3H 7 8 50 57 72
44 46 49 13 55 72
30
I655 TRUE S0PWRGD_1V8_DIV 51 I636 TRUE SMBUS_SMC_0_S0_SDA 7 41 I742 TRUE SMC_ONOFF_L 6 7 40 41 I707 TRUE SPI_A_SO_R I812 TRUE TMDS_HTPLG_R 61 I777 TRUE USB2_CAMERA_F_P I873 TRUE XDP_CLK_P 71 I854 TRUE PP0V9_S3 6 8 31 32 I848 TRUE PPDCIN_G3H_R 50 72
44 46 42 55 72
69
I657 TRUE S0PWRGD_3V3_DIV 51 I638 TRUE SMBUS_SMC_A_S3_SCL 71 I744 TRUE SMC_PBUS_ISENSE 41 59 I711 TRUE SPI_CE_L<0> 43 I814 TRUE TMDS_HW_RESET_L 28 61 62 I781 TRUE USB2_CAMERA_N I875 TRUE XDP_CPURST_L 66
6 7 I856 TRUE PP18V5_DCIN 6 7 50 72 I846 TRUE PPVBATT_G3H_R 50 72
44 71 49 13
I665 TRUE S0PWRGD_5V_DIV 51 I658 TRUE SMBUS_SMC_A_S3_SDA 40 41
7 36 I743 TRUE SMC_PBUS_VSENSE 41 45 I710 TRUE SPI_CE_R_L<0> 24 I813 TRUE TMDS_INT_N 61 67 I780 TRUE USB2_CAMERA_P I876 TRUE XDP_DBRESET_L 6 7 10 13 28
49
I664 TRUE S0SEQ_BEGIN 51 I659 TRUE SMBUS_SMC_BSA_SCL 59 71
7 41
44 50 I746 TRUE SMC_PF3 41 42 I709 TRUE SPI_CE_R_L<1> 69
I816 TRUE TMDS_INT_P 61 67 I779 TRUE USB2_EXTA_F_N I877 TRUE XDP_OBS20 7 13 ICT Test Points
I667 TRUE SATA_B_DET_L 25 I660 TRUE SMBUS_SMC_BSA_SDA I745 TRUE SMC_PM_G2_EN 6 41 56 58 I708 TRUE SPI_EXT_A_SCLK_R 43 I815 TRUE TMDS_LINT_L 61 62 I778 TRUE USB2_EXTA_F_P I878 TRUE XDP_PWRGD 6 7 13
A I666 TRUE
TRUE
SB_A20GATE
SB_CLINK_VREF0
23
25 70
I661 TRUE
TRUE
SMBUS_SMC_B_S3_SCL 7 41
44 60
SMBUS_SMC_B_S3_SDA 7 41
I747 TRUE
TRUE
SMC_PROCHOT
SMC_PROCHOT_3_3_L
41 42
41 42
I712 TRUE
TRUE
SPI_EXT_A_SI_R
SPI_EXT_CE_L<0>
43
43
I817 TRUE TMDS_LSCL
TRUE TMDS_LSDA
61 62
61 62
I782 TRUE
TRUE
USB2_EXTA_N
USB2_EXTA_P
I879 TRUE
TRUE
XDP_TCK
XDP_TDI
6 7 10 13
6 7 10 13
66
66 NOTICE OF PROPRIETARY PROPERTY

A
I668 I662 44 60 I749 I713 I819 I783 I880
I669 TRUE SB_CLINK_VREF1 25 70 I663 TRUE SMBUS_SMC_MGMT_SCL 41 44 I748 TRUE SMC_RESET_L 6 41 42 43 I714 TRUE SPI_INT_CE_L<0> 43 I818 TRUE TMDS_SDB_N 61 67 I784 TRUE USB2_MUXED_EXTA_N I882 TRUE XDP_TDO 6 7 10 13 66
48 71 49 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
I677 TRUE SB_CLK100M_DMI_N 24 29 30 I670 TRUE SMBUS_SMC_MGMT_SDA 41 44 I750 TRUE SMC_RUNTIME_SCI_L 25 41 I715 TRUE SPI_SCLK_R 24 I820 TRUE TMDS_SDB_P 61 67 I785 TRUE USB2_MUXED_EXTA_P I881 TRUE XDP_TMS 6 7 10 13 66 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
71 48 71 49 AGREES TO THE FOLLOWING
I676 TRUE SB_CLK100M_DMI_P 24 29 30 I671 TRUE SMB_AIRPORT_CONN_CLK 7 36 I751 TRUE SMC_RX_L 39 41 42 I716 TRUE SPI_SI_R 69
I821 TRUE TMDS_SDC_N 61 67 I786 TRUE USB2_WSPRING_N 7 I883 TRUE XDP_TRST_L 6 7 10 13 66
71 43 9 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
49
I679 TRUE SB_CLK14P3M_TIMER 25 30 71 I672 TRUE SMB_AIRPORT_CONN_DATA 7 36 I752 TRUE SMC_SMS_INT 9 41 48 I717 TRUE SPI_SO 24 I822 TRUE TMDS_SDC_P 61 67 I787 TRUE USB2_WSPRING_P 24 40 69
7
43 9 24 40 69 II NOT TO REPRODUCE OR COPY IT
SB_CLK48M_USBCTLR SMC_ACIN_VSENSE SMC_SUS_CLK SST8051_DDC_CLK 69 TMDS_SDG_N USB_DEBUGPRT_EN_L
I678 TRUE 25 30 71 I673 TRUE 41 45 I754 TRUE 41 42 I718 TRUE I824 TRUE 61 67 I788 TRUE 39 41
I680 TRUE SB_CRT_TVOUT_MUX_L 25 63 I674 TRUE SMC_ADAPTER_EN 9 36 I753 TRUE SMC_SYS_KBDLED 7 40 41 I719 TRUE SST8051_DDC_DATA 62 I823 TRUE TMDS_SDG_P 61 67 I789 TRUE USB_EXTC_OC_L 24
41 42
I681 TRUE SB_GPIO10_CL1 23 25 I675 TRUE SMC_BATTPACK_STAT 41 42 I755 TRUE SMC_SYS_LED 7 40 41 I720 TRUE SST8051_DDC_EN 62 I825 TRUE TMDS_SDR_N 61 67 I790 TRUE USB_EXTD_OC_L 7 13 24 SIZE DRAWING NUMBER REV.
SB_GPIO18 SMC_BATT_CHG_EN SMC_TCK SST8051_DVI_HOTPLUG_DET TMDS_SDR_P USB_IR_N
I687
I686
TRUE
TRUE SB_GPIO30
25
7 13 24
I684
I683
TRUE
TRUE SMC_BATT_ISENSE
6 41
42
41 59
I756
I757
TRUE
TRUE SMC_TDI
6 41 42 43 I722
6 41 42 43 I721
TRUE
TRUE SST8051_EA_L 62
I826
I827
62 TRUE
TRUE TMDS_SW_RESET_L
61 67
25 61
I792
I791
TRUE
TRUE USB_IR_P
7 9 24 40 69
7 9 24 40 69
D 051-7230 B.0.0
I685 TRUE SB_GPIO36 25 I682 TRUE SMC_BC_ACOK 41 42 I759 TRUE SMC_TDO 6 41 42 43 I724 TRUE SST8051_P25_AUDIO_CONFIG
I829 62 TRUE TMDS_TX<2..0> 61 I794 TRUE USB_RBIAS 24 69
50 59
TRUE SB_GPIO40 7 13 24 TRUE SMC_BC_ACOK_ONEWIRE_R 50 TRUE SMC_THRMTRIP 41 42 TRUE SST8051_P34_AUDIO_CONFIG 62 TRUE TMDS_TX_CLK 61 TRUE VCCCL1_5V 26 NONE 6 73
I689 I688 I758 I723 I828 I793
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
Functional Test Points
NB NO_TESTS
These are normally testpoints but become NC
NO_TEST
I236 TRUE NC_LVDS_VBG NC_LVDS_VBG 7 15 FUNC TEST - XDP/ITP CONNECTOR FUNC TEST - Power Supplies
MAKE_BASE=TRUE FUNC TEST - BATTERY CONNECTOR
I254 TRUE NC_NB_RSVD_31 NC_NB_RSVD_31 7 16
MAKE_BASE=TRUE x3 I647 TRUE BATT_POS 6 50 I593 TRUE XDP_BPM_L<0..5> 6 10 I92
PPVCORE_S0_CPU 6 8 11 12 52 65 72
I255 TRUE NC_NB_RSVD_32 NC_NB_RSVD_32 7 13 66
MAKE_BASE=TRUE x3 I649 TRUE GND I595 TRUE NB_BSEL<0..2> 6 13 I454
PP0V9_S0 6 8 33 55 72
I257 TRUE NC_NB_RSVD_33 NC_NB_RSVD_33 7 16 30 66
MAKE_BASE=TRUE I638 TRUE SMC_BS_ALRT_L 6 41 42 50 I680 TRUE NB_CFG<3..8> 6 13 I455 PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21
16 23 26 27 30 42 54 72
TRUE SMBUS_SMC_BSA_SCL 6 41 44 50 59 I681 TRUE XDP_PWRGD 6 13 PP1V25_S0 6 8 16 18 19 21 26 27 51 57 72
D I279
I280
TRUE
TRUE
NC_MEM_A_RCVEN_L
NC_MEM_B_RCVEN_L
NC_MEM_A_RCVEN_L
MAKE_BASE=TRUE
NC_MEM_B_RCVEN_L
7 17
7 17
I640
I639 TRUE SMBUS_SMC_BSA_SDA

71
6 41 44 50 59 I683
71
TRUE XDP_OBS20 6 13
I457
I460
PP1V5_S0 6 8 11 12 22 26 27 54 72 D
MAKE_BASE=TRUE I682 TRUE TP_XDP_HOOK2 13 I459
PP1V8_S0 6 8 19 22 51 61 72
MAKE_BASE=TRUE I684 TRUE TP_XDP_HOOK3 13 I458 PPVCORE_S0_NB_GFX 6 8 18 22 45 53 65 72
MAKE_BASE=TRUE FUNC TEST - DC-IN CONNECTOR I685 TRUE LOCAL_CTRL_DATA 6 13 I461 PP5V_S0 6 7 8 22 27 40 43 47 51 52 53
I370 TRUE NC_NB_RSVD_3 NC_NB_RSVD_3 7 16 15 63 72
MAKE_BASE=TRUE x2 I648 TRUE PP18V5_DCIN 6 50 72 I687 TRUE LOCAL_CTRL_CLK 6 13 I466
PP3V3_S0 72
I372 TRUE NC_NB_RSVD_4 NC_NB_RSVD_4 7 16 15
MAKE_BASE=TRUE I650 TRUE SYS_ONEWIRE 6 41 42 50 I686 TRUE XDP_TCK 6 10 I465 PP1V8_S3 6 8 16 18 21 31 32 34 35 51 55
I377 TRUE NC_NB_RSVD_5 NC_NB_RSVD_5 7 16 13 66 68 72
MAKE_BASE=TRUE x2 I706 TRUE GND I688 TRUE SMC_WAKE_SCI_L 6 13 I463
PP3V3_S3 6 8 36 42 44 48 51 58 60 72
MAKE_BASE=TRUE I689 TRUE EXTAUSB_OC_L 6 9 I462 PP5V_S3 6 8 40 58 60 72
I378 TRUE NC_NB_RSVD_7 NC_NB_RSVD_7 7 16 FUNC TEST - TEMP SENSOR CONNECTOR 13 24 39
MAKE_BASE=TRUE I691 TRUE SB_GPIO40 6 13 I467 PP3V3_S5 6 8 24 25 26 27 28 36 43 44 49
I380 TRUE NC_NB_RSVD_8 NC_NB_RSVD_8 7 16 I673 TRUE SMBUS_SMC_0_S0_SCL 6 41 44 46 71 24 51 56 57 58 60 72
MAKE_BASE=TRUE 41 44 46 71 I690 TRUE USB_EXTD_OC_L 6 13 I468 PP5V_S5 6 8 27 39 51 54 55 56 58 72
I244 TRUE NC_NB_RSVD_14 NC_NB_RSVD_14 7 16 I674 TRUE SMBUS_SMC_0_S0_SDA 6 24
MAKE_BASE=TRUE 44 46 51 52
24 25 26 27 I692 TRUE WOW_EN 6 13 I469 PP3V42_G3H 6 8 23 26 27 28 39 40 41 42 43
PP3V3_A_S0
I246 TRUE NC_NB_RSVD_21 NC_NB_RSVD_21 7 16 I675 TRUE 6 7 8 13 16 24 36 44 57 59 72
28 29 30 42 I694 TRUE PM_LATRIGGER_L 6 13 I474 PP18V5_G3H 6 8 50 59 72
I356 TRUE NC_NB_RSVD_22 NC_NB_RSVD_22 7 16 53 60 63 64 24
MAKE_BASE=TRUE FUNC TEST - FAN CONNECTOR I695 TRUE EXTGPU_LVDS_EN 6 13 I473
PPDCIN_G3H 6 8 50 57 72
24
MAKE_BASE=TRUE I668 TRUE PP5V_S0 6 7 8 22 27 I696 TRUE SB_GPIO30 6 13 I472
PPBUS_G3H 6 7 8 37 45 50 56 59 64 72
I360 TRUE NC_NB_RSVD_24 NC_NB_RSVD_24 7 16 40 43 47 51 24
MAKE_BASE=TRUE I667 TRUE FAN_RT_PWM 6 47 I697 TRUE EXTBUSB_OC_L 6 9 I471 PPBUS_R_G3H 6 8 42 52 53 54 55 59 72
MAKE_BASE=TRUE I669 TRUE FAN_RT_TACH 6 47 I698 TRUE XDP_CLK_P 6 13
MAKE_BASE=TRUE I714 TRUE GND I699 TRUE XDP_CLK_N 6 13
I366 TRUE NC_NB_RSVD_27 NC_NB_RSVD_27 7 16 29 30 66 71 FUNC TEST - M93 WIRELESS CONNECTOR
MAKE_BASE=TRUE I701 TRUE XDP_CPURST_L 6 13
I258 TRUE NC_NB_RSVD_35 NC_NB_RSVD_35 7 16 FUNC TEST - CAMERA USB, LVDS, ALS XDP_DBRESET_L
66
PLT_RST_L
MAKE_BASE=TRUE I700 TRUE 6 10 I470 6 24 28 60 64
I259 TRUE NC_NB_RSVD_36 NC_NB_RSVD_36 7 16 x2 I654 TRUE PP5V_S3_CAMERA_F 6 60 72 13 28
MAKE_BASE=TRUE I702 TRUE XDP_TDO 6 10 I475 PCIE_WAKE_L 6 7 25 36
I260 TRUE NC_NB_CFG_10 NC_NB_CFG_10 7 16 I655 TRUE USB2_CAMERA_F_P 6 60 69 13 66
MAKE_BASE=TRUE I703 TRUE XDP_TRST_L 6 10 I479 CK505_SRC_CLKREQ6_L 6 7 29 36
I262 TRUE NC_NB_CFG_11 NC_NB_CFG_11 7 16 I656 TRUE USB2_CAMERA_F_N 6 60 69 13 66
MAKE_BASE=TRUE I704 TRUE XDP_TDI 6 10 63 64 I478 PCIE_CLK100M_MINI_N_F 6 36
I261 TRUE NC_NB_CFG_14 NC_NB_CFG_14 7 16 I657 TRUE LCDBKLT_RTN<1..6> 6 60 64 13 66 46 51
30 42
MAKE_BASE=TRUE I705 TRUE XDP_TMS 6 10 27 28 I476
PCIE_CLK100M_MINI_P_F 6 36
I263 TRUE NC_NB_CFG_15 NC_NB_CFG_15 7 16 I658 TRUE LVDS_A_DATA_N<0..2> 6 15 60 67 13 66 24 25
21 2253
MAKE_BASE=TRUE I707 TRUE PP3V3_A_S0 6 7 8 13 16 I477
PCIE_E_D2R_N_F 6 36
I264 TRUE NC_NB_CFG_17 NC_NB_CFG_17 7 16 I659 TRUE LVDS_A_DATA_P<0..2> 6 15 60 67
72
19 21 23 2623
19
MAKE_BASE=TRUE I708 TRUE PP1V05_S0 6 7 8 10 1126 I480 PCIE_E_D2R_P_F 6 36
I265 TRUE NC_NB_NC_1 NC_NB_NC_1 7 16 I660 TRUE PPVOUT_S0_LCDBKLT 6 60 64 12 13 14 1829
MAKE_BASE=TRUE 72 x16I709 TRUE GND 27 30 42 5444
52 I483
PCIE_E_R2D_C_N_F 6 7 36
I329 TRUE NC_NB_NC_2 NC_NB_NC_2 7 16 I661 TRUE LVDS_A_CLK_F_N 6 60 60
PCIE_E_R2D_C_P_F
C I331 TRUE
TRUE
NC_NB_NC_3
NC_NB_NC_4
MAKE_BASE=TRUE
NC_NB_NC_3
MAKE_BASE=TRUE
NC_NB_NC_4
7 16
7 16
I662 TRUE
TRUE
LVDS_A_CLK_F_P
LVDS_DDC_CLK
6 60
6 15 60
I484
I482
AIRPORT_RST_L
6 7 36
6 7 28 36
C
I333 I663
MAKE_BASE=TRUE I499
SMB_AIRPORT_CONN_CLK 6 36
I335 TRUE NC_NB_NC_5 NC_NB_NC_5 7 16 I664 TRUE LVDS_DDC_DATA 6 15 60
MAKE_BASE=TRUE I500
SMB_AIRPORT_CONN_DATA 6 36
I337 TRUE NC_NB_NC_6 NC_NB_NC_6 7 16 I665 TRUE PP3V3_S0_LCD_F 6 60 72
MAKE_BASE=TRUE I501 PCIE_E_R2D_C_N_F 6 7 36
I339 TRUE NC_NB_NC_7 NC_NB_NC_7 7 16 x2 I666 TRUE PP3V3_LCDVDD_SW_F 6 60 72
MAKE_BASE=TRUE FUNC TEST - RIO HATCH CONNECTOR I502 PCIE_E_R2D_C_P_F 6 7 36
I348 TRUE NC_NB_NC_8 NC_NB_NC_8 7 16 I711 TRUE SMBUS_SMC_B_S3_SDA 6 41 44 60
MAKE_BASE=TRUE I716 TRUE HDMI_HOST 6 37 I503
PP3V3_S3_AP_AUX 6 36 72
I350 TRUE NC_NB_NC_9 NC_NB_NC_9 7 16 I712 TRUE SMBUS_SMC_B_S3_SCL 6 41 44 60 63
MAKE_BASE=TRUE I717 TRUE DVI_HOST 6 37
I349 TRUE NC_NB_NC_10 NC_NB_NC_10 7 16 x10I713 TRUE GND 63
MAKE_BASE=TRUE I718 TRUE TMDS_HTPLG 6 37
I352 TRUE NC_NB_NC_11 NC_NB_NC_11 7 16 61 63
MAKE_BASE=TRUE FUNC TEST - AUDIO CONNECTOR I719 TRUE TMDS_DDC_SDA 6 37
I351 TRUE NC_NB_NC_12 NC_NB_NC_12 7 16 61 62 63 67
MAKE_BASE=TRUE I720 TRUE TMDS_DDC_SCL 6 37
I353 TRUE NC_NB_NC_13 NC_NB_NC_13 7 16 I645 TRUE HDA_SYNC 6 9 23 37 69 61 62 63 67
MAKE_BASE=TRUE I721 TRUE VGA_VSYNC 6 37
I354 TRUE NC_NB_NC_14 NC_NB_NC_14 7 16 I646 TRUE HDA_BIT_CLK 6 9 23 37 69 63
MAKE_BASE=TRUE I722 TRUE VGA_HSYNC 6 37
I383 TRUE NC_NB_RSVD_29 NC_NB_RSVD_29 7 16 I735 TRUE AUD_MIC_DATA 6 37 60 63
MAKE_BASE=TRUE I723 TRUE TMDS_TX_CONN_CLK_P 6 37
I384 TRUE NC_NB_RSVD_28 NC_NB_RSVD_28 7 16 I736 TRUE HDA_SDOUT 6 9 23 37 69 63 67
MAKE_BASE=TRUE 72 I724 TRUE TMDS_TX_CONN_CLK_N 6 37
I386 TRUE NC_NB_RSVD_30 NC_NB_RSVD_30 7 16 I737 TRUE PPBUS_G3H 6 7 8 37 45 63 67
I725 TRUE TMDS_TX_CONN_P<0..2> 6 37
I738 TRUE HDA_SDIN0 6 9 23 37 69 63
I726 TRUE TMDS_TX_CONN_N<0..2> 6 37
I740 TRUE AUD_MIC_CLK 6 37 60 63
I727 TRUE USB2_EXTA_F_P 6 37
I739 TRUE PM_SLP_S3_L 6 25 36 37 41 39 69
42 51 55
I728 TRUE USB2_EXTA_F_N 6 37
I431 TRUE NC_CRT_DDC_CLK NC_CRT_DDC_CLK 7 15 39 69
MAKE_BASE=TRUE x14I730 TRUE PP5V_S3_USB2_EXTA_F 6 37
I433 TRUE NC_CRT_DDC_DATA NC_CRT_DDC_DATA 7 15 39 72
MAKE_BASE=TRUE I729 TRUE PP5V_S0_DVIPORT 6 37
63 72
I731 TRUE VGA_B 6 37
63 67
FUNC TEST - IPD CONNECTOR I733 TRUE VGA_G 6 37
Power Supply NO_TESTs I507 TRUE SMC_LID 6 40 41 42 I732 TRUE VGA_R

63 67
6 37
63 67
I506 TRUE PP3V42_G3H_IPD_F 6 40 x14I710 TRUE GND
NO_TEST SMC_SYS_KBDLED
I508 TRUE 6 40 41
TRUE SMC_SYS_LED 6 40 41 FUNC TEST - AIRPORT

B I509
I510 TRUE USB2_WSPRING_N 6 9 24 40 69 I741 TRUE CK505_SRC_CLKREQ6_L 6 7

29 36
B
I512 TRUE USB2_WSPRING_P 6 9 24 40 69 I742 TRUE PCIE_WAKE_L 6 7
25 36
I511 TRUE SMC_ONOFF_L 6 7 40 41 42 I743 TRUE AIRPORT_RST_L 6 7
28 36
I513 TRUE USB_IR_N 6 7 9 24 40 I744 TRUE SMBUS_SMC_A_S3_SCL 6 7
69 36 40 41 44 71
I514 TRUE USB_IR_P 6 7 9 24 40 I745 TRUE SMBUS_SMC_A_S3_SDA 6 7
69 36 40 41 44 71
I515 TRUE PP5V_S0_KBDLED_F 6 7 40 72 I746 TRUE GND
CLOCK NO_TESTS I517 TRUE PP5V_S3_TOPCASE_F 6 40
I516 TRUE SMBUS_SMC_A_S3_SCL 6 7 36 40 41 44 71

NO_TEST
I518 TRUE SMBUS_SMC_A_S3_SDA 6 7 36 40 41 44 71 x13I522 GND
I520 TRUE SMC_ONOFF_L 6 7 40 41 42
I519 TRUE USB_IR_N 6 7 9 24 40 69
I521 TRUE USB_IR_P 6 7 9 24 40 69
I676 TRUE PP5V_S0_KBDLED_F 6 7 40 72
I734 TRUE LSOC_H_R 6
LVDS NO_TESTS REQUIRED NETS NICE2HAVE NETS

NO_TEST
Functional Test and No-Tests

A
D 051-7230 B.0.0

NONE 7 73
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
"S0,S0M" RAILS 64 63 60 53
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0 PP3V3_A_S0 53 60 63 64
6 7 8 13 16 19 21 22 23 24 25 "S5" RAILS
52 51 46 44 42 30 29 28 27 26 MIN_LINE_WIDTH=0.30MM 26 27 28 29 30 42 44 46 51 52
MIN_NECK_WIDTH=0.20MM
(REGULATOR OUTPUT CPU VCORE PWR) VOLTAGE=3.3V
MAKE_BASE=TRUE
65 52 12 11 8 7 6 PPVCORE_S0_CPU PPVCORE_S0_CPU 6 7 8 11 12 52 65 72
72 MIN_LINE_WIDTH=0.25 MM PP3V3_A_S0 44 46 51 52 53 60
6 7 8 13 16 19 21
63 64
22 23 24 25
MIN_NECK_WIDTH=0.20 MM 26 27 28 29 30 42 44 43 36 28 27 26 25 24 8 7 6 PP3V3_S5 PP3V3_S5 6 7 8 24 25 26 27 28 36 43 44
(CPU VCOR PWRE) VOLTAGE=0.9V PP3V3_A_S0 53 60 63 64
6 7 8 13 16 19 21 22 23 24 25 72 60 58 57 56 51 49 MIN_LINE_WIDTH=0.6 mm 49 51 56 57 58 60 72
MAKE_BASE=TRUE 26 27 28 29 30 42 44 46 51 52 MIN_NECK_WIDTH=0.2 mm
PP3V3_A_S0 6 7 8 13 16 19 21 22 23 24 25 VOLTAGE=3.3V
PPVCORE_S0_CPU 6 7 8 11 12 52 65 72 26 27 28 29 30 42 44 46 51 52 MAKE_BASE=TRUE
PP3V3_A_S0 53 60 63 64
28 29 30 42 44 46 51 52 53 60 PP3V3_S5 6 7 8 24 25 26 27 28 36 43 44
PP3V3_A_S0 8 13 16 19 21 22 23 24 25 26
6 63 64 49 51 56 57 58 60 72
D 33 8 7 6
72 55
PP0V9_S0 PP0V9_S0
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
6 7 8 33 55 72
PP3V3_A_S0
7 52 53 60 63 64
27 8 13 16 19 21 22 23 24 25 26
6
63 764
27 28 29 30 42 44 46 51
PP3V3_S5
PP3V3_S5
6 7 8
49 51
6 7 8
24
56
24
25
57
25
26 27 28 36 43 44
58 60 72
26 27 28 36 43 44
D
VOLTAGE=0.9V PP3V3_A_S0 28 29 30 42 44 46 51 52 53 60
6 7 8 13 16 19 21 22 23 24 25 49 51 56 57 58 60 72
(DDR2 TERMINATION 0.9V PWR) MAKE_BASE=TRUE 26 27 PP3V3_S5 6 7 8 24 25 26 27 28 36 43 44
PP3V3_A_S0 44 46 51 52 53 60 63 64
6 7 8 13 16 19 21 22 23 24 25 49 51 56 57 58 60 72
PP0V9_S0 6 7 8 33 55 72 26 27 28 29 30 42 PP3V3_S5 6 7 8 24 25 26 27 28 36 43 44
PP3V3_A_S0 53 60 63 64
6 7 8 13 16 19 21 22 23 24 25 49 51 56 57 58 60 72
26 27 28 29 30 42 44 46 51 52 PP3V3_S5 6 7 8 24 25 26 27 28 36 43 44
PP3V3_A_S0 6 7 8 13 16 19 21 22 23 24 25 49 51 56 57 58 60 72
26 27 28 29 30 42 44 46 51 52 PP3V3_S5 6 7 8 24 25 26 27 28 36 43 44
(REGULATOR OUTPUT CPU 0.90V PWR) PP3V3_A_S0 53 60 63 64
6 26 27 28 29 30 42 49 51 56 57 58 60 72
7 8 13 16 19 21 22 23 24 25 PP3V3_S5 6 7 8 24 25 26 27 28 36 43 44
R0800 PP3V3_A_S0 44 46 51 52 53 60 63 64 49 51 56 57 58 60 72
72 55 32 31 8 6 PP0V9_S3 PP0V9_S3 6 PP3V3_S5 6 7 8 24 25 26 27 28 36 43 44
MIN_LINE_WIDTH=0.4 mm 8 31 32 55 0 PP3V3_A_S0 53 60 63 64
6 7 8 13 16 19 21 22 23 24 25 49 51 56 57 58 60 72
MIN_NECK_WIDTH=0.2 mm 72 2 1 PP0V9_S3M_MEM_NBVREFA 16 21 68 26 27 28 29 30 42 44 46 51 52 PP3V3_S5 6 7 8 24 25 26 27 28 36 43 44
VOLTAGE=0.9V MIN_LINE_WIDTH=0.4 mm PP3V3_A_S0 6 7 8 13 16 19 21 22 23 24 25 49 51 56 57 58 60 72
(NB MEM VREF 0.9V PWR) MAKE_BASE=TRUE 5% MIN_NECK_WIDTH=0.2 mm 26 27 28 29 30 42 44 46 51 52 PP3V3_S5 6 7 8 24 25 26 27 28 36 43 44
1/20W VOLTAGE=0.9V PP3V3_A_S0 53 60 63 64 49 51 56 57 58 60 72
PP0V9_S3 MF 52 53 60 63 64 PP3V3_S5 6 7 8 24 25 26 27 28 36 43 44
201 PP3V3_A_S0 8 13 16 19 21 22 23 24 25 26
6 27 28 29 30 42 44 46 51 49 51 56 57 58 60 72
PP0V9_S3 PP3V3_S5
63 764 6 7 8 24 25 26 27 28 36 43 44
R0801 PP3V3_A_S0 27 28 29 30 42 44 46 51 52 53
6 7 8 13 16 19 21 22 23 24 25 49 51 56 57 58 60 72
PP0V9_S3 6 8 26 64 PP3V3_S5 6 7 8 24 25 26 27 28 36 43 44
31 32 55 72 0 PP3V3_A_S0 60
27 28 29 30 42 44 46 51 52 49 51 56 57 58 60 72
2 1 PP0V9_S3M_MEM_NBVREFB 16 21 68
13 16 19 21 22 23 24 25 26
MIN_LINE_WIDTH=0.4 mm PP3V3_A_S0 8
46 651 52 53 60 63 64
53 60 63
72 54 42 30
12 11 10 8 7 6 PP1V05_S0 PP1V05_S0 12 13
6 7 8
14
5% MIN_NECK_WIDTH=0.2 mm 16 719 21 22 23 24 25 26 27 28
27 26 23 21 19 18 14 13 MIN_LINE_WIDTH=0.6 mm 10 11
18 19 21
1/20W VOLTAGE=0.9V PP3V3_A_S0 8
6 52 53 60 63 64
29 30 42 44
MIN_NECK_WIDTH=0.2 mm 23 26 27 MF 7 26 27 28 29 30 42 44 46 51
VOLTAGE=1.05V 30 42 54 201 PP3V3_A_S0 13 7 8 13 16 19 21 22 23 24 25
6
MAKE_BASE=TRUE 72 28 29 30 42 44 46 51 52 53 60
72 58 56 55 54 51 39 27 8 7 6 PP5V_S5 PP5V_S5 6 7 8 27 39 51 54 55 56 58 72
PP3V3_A_S0 8 13 16 19 21 22 23 24 25 26
6 63 64 MIN_LINE_WIDTH=0.6 mm
PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 7 52 53 60 63 64 MIN_NECK_WIDTH=0.2 mm
23 26 27 30 42 54 72 PP3V3_A_S0 27 8 13 16 19 21 22 23 24 25 26
6 27 28 29 30 42 44 46 51 VOLTAGE=5V
PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 63 764
MAKE_BASE=TRUE
23 26 27 30 42 54 72 PP3V3_A_S0 28 29 30 42 44 46 51 52 53 60
6 7 8 13 16 19 21 22 23 24 25
PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 26 27 PP5V_S5 6 7 8 27 39 51 54 55 56 58 72
23 26 27 30 42 54 72 PP3V3_A_S0 44 46 51 52 53 60 63 64
6 7 8 13 16 19 21 22 23 24 25
PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 26 27 28 29 30 42 PP5V_S5 6 7 8 27 39 51 54 55 56 58 72
23 26 27 30 42 54 72 PP3V3_A_S0 53 60 63 64
6 7 8 13 16 19 21 22 23 24 25
PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 26 27 28 29 30 42 44 46 51 52 PP5V_S5 6 7 8 27 39 51 54 55 56 58 72
23 26 27 30 42 54 72 PP3V3_A_S0
PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 52 53 60 63 64 PP5V_S5 6 7 8 27 39 51 54 55 56 58 72
23 26 27 30 42 54 72 PP3V3_A_S0 8 13 16 19 21 22 23 24 25 26
6 27 28 29 30 42 44 46 51
PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 3V3_S0 split into 2 63 764 PP5V_S5 6 7 8 27 39 51 54 55 56 58 72
23 26 27 30 42 54 72 PP3V3_A_S0 28 29 30 42 44 46 51 52 53 60
6 7 8 13 16 19 21 22 23 24 25
PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 26 27 PP5V_S5 6 7 8 27 39 51 54 55 56 58 72
23 26 27 30 42 54 72 for layout optimization PP3V3_A_S0 44 46 51 52 53 60 63 64
6 7 8 13 16 19 21 22 23 24 25
PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 26 27 28 29 30 42
23 26 27 30 42 54 72 PP3V3_A_S0 53 60 63 64
6 7 8 13 16 19 21 22 23 24 25
PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 of plane splits 26 27 28 29 30 42 44 46 51 52
C 72
21 19 18 16 8 7 6 PP1V25_S0 PP1V25_S0
23 26 27 30 42 54 72
6 7 8 16 18 19 21 26 27 51 57
C
57 51 27 26 MIN_LINE_WIDTH=0.6 mm 72
VOLTAGE=1.25V
MAKE_BASE=TRUE
"G3H" RAILS
PP1V25_S0 6 7 8 16 18 19 21 26 27 51 57
72
PP1V25_S0 6 7 8 16 18 19 21 26 27 51 57
63 62 61 51 47 38 8 6 PP3V3_B_S0 PP3V3_B_S0 6 8 38 47 51 61 62 63
MIN_LINE_WIDTH=0.30MM
72
MIN_NECK_WIDTH=0.20MM 42 41 40 39 28 27 26 23 8 7 6 PP3V42_G3H PP3V42_G3H 6 7 8 23 26 27 28 39 40 41 42
PP1V25_S0 6 7 8 16 18 19 21 26 27 51 57 3V3_B_S0 plane on right side VOLTAGE=3.3V 72 59 57 44 43 MIN_LINE_WIDTH=0.3 mm 43 44 57 59 72
72 MAKE_BASE=TRUE MIN_NECK_WIDTH=0.2 mm
PP1V25_S0 6 7 8 16 18 19 21 26 27 51 57 VOLTAGE=3.42V
72 (peninsula) PP3V3_B_S0 6 8 38 47 51 61 62 63 MAKE_BASE=TRUE
PP1V25_S0 6 7 8 16 18 19 21 26 27 51 57
72 PP3V3_B_S0 6 8 38 47 51 61 62 63 PP3V42_G3H 6 7 8 23 26 27 28 39 40 41 42
PP1V25_S0 6 7 8 16 18 19 21 26 27 51 57 43 44 57 59 72
72 PP3V3_B_S0 6 8 38 47 51 61 62 63 PP3V42_G3H 6 7 8 23 26 27 28 39 40 41 42
43 44 57 59 72
PP3V3_B_S0 6 8 38 47 51 61 62 63 PP3V42_G3H 6 7 8 23 26 27 28 39 40 41 42
43 44 57 59 72
PP3V3_B_S0 6 8 38 47 51 61 62 63 PP3V42_G3H 6 7 8 23 26 27 28 39 40 41 42
43 44 57 59 72
PP3V42_G3H 6 7 8 23 26 27 28 39 40 41 42
26 22 12 11 8 7 6 PP1V5_S0 PP1V5_S0 6 7 8 11 12 22 26 27 54 72 43 44 57 59 72
72 54 27 MIN_LINE_WIDTH=0.5 mm PP3V42_G3H 6 7 8 23 26 27 28 39 40 41 42
MIN_NECK_WIDTH=0.2 mm 43 44 57 59 72
VOLTAGE=1.5V PP3V42_G3H 6 7 8 23 26 27 28 39 40 41 42
MAKE_BASE=TRUE 43 44 57 59 72
PP3V42_G3H
PP1V5_S0 6 7 8 11 12 22 26 27 54 72 "S3" RAILS 6 7 8 23 26 27 28 39 40 41 42
43 44 57 59 72
PP1V5_S0 6 7 8 11 12 22 26 27 54 72 PP1V8_S3
51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 6 7 8 16 18 21 31 32 34 35 51
PP1V5_S0 6 7 8 11 12 22 26 27 54 72 72 68 55 MIN_LINE_WIDTH=0.6 mm 55 68 72
PP1V5_S0 6 7 8 11 12 22 26 27 54 72 VOLTAGE=1.8V 72 59 50 8 7 6 PP18V5_G3H PP18V5_G3H 6 7 8 50 59 72
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.3 MM
PP1V5_S0 6 7 8 11 12 22 26 27 54 72 MIN_NECK_WIDTH=0.2 MM
PP1V8_S3 6 7 8 16 18 21 31 32 34 35 51 VOLTAGE=18.5V
PP1V5_S0 6 7 8 11 12 22 26 27 54 72 55 68 72 MAKE_BASE=TRUE
PP1V8_S3 6 7 8 16 18 21 31 32 34 35 51
PP1V5_S0 6 7 8 11 12 22 26 27 54 72 55 68 72
PP1V8_S3 6 7 8 16 18 21 31 32 34 35 51
PP1V5_S0 6 7 8 11 12 22 26 27 54 72 55 68 72
PP1V8_S3 6 7 8 16 18 21 31 32 34 35 51 72 57 50 8 7 6 PPDCIN_G3H PPDCIN_G3H 6 7 8 50 57 72
PP1V5_S0 6 7 8 11 12 22 26 27 54 72 55 68 72 MIN_LINE_WIDTH=0.6 mm
VOLTAGE=18.5V
B MAKE_BASE=TRUE
PPDCIN_G3H 6 7 8 50 57 72
B
72 60 58 51 48 44 42 36 8 7 6 PP3V3_S3 PP3V3_S3 6 7 8 36 42 44 48 51 58 60 72
MIN_LINE_WIDTH=0.2mm
61 51 22 19 8 7 6 PP1V8_S0 PP1V8_S0 6 7 8 19 22 51 61 72 MIN_NECK_WIDTH=0.2mm
72 MIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE 72 59 55 54 53 52 42 8 7 6 PPBUS_R_G3H PPBUS_R_G3H 6 7 8 42 52 53 54 55 59 72
VOLTAGE=1.8V MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE PP3V3_S3 6 7 8 36 42 44 48 51 58 60 72 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V
PP1V8_S0 6 7 8 19 22 51 61 72 PP3V3_S3 6 7 8 36 42 44 48 51 58 60 72 MAKE_BASE=TRUE
PP1V8_S0 6 7 8 19 22 51 61 72 PP3V3_S3 6 7 8 36 42 44 48 51 58 60 72
PPBUS_R_G3H 6 7 8 42 52 53 54 55 59 72
PP1V8_S0 6 7 8 19 22 51 61 72 PP3V3_S3 6 7 8 36 42 44 48 51 58 60 72
PPBUS_R_G3H 6 7 8 42 52 53 54 55 59 72
PP3V3_S3 6 7 8 36 42 44 48 51 58 60 72
PPBUS_R_G3H 6 7 8 42 52 53 54 55 59 72
53 45 22 18 8 7 6 PPVCORE_S0_NB_GFX PPVCORE_S0_NB_GFX 6 7 8 18 22 45 53 65 72 PP3V3_S3 6 7 8 36 42 44 48 51 58 60 72
PPBUS_R_G3H
72 65 MIN_LINE_WIDTH=0.5 mm 6 7 8 42 52 53 54 55 59 72
MIN_NECK_WIDTH=0.2 mm PP3V3_S3 6 7 8 36 42 44 48 51 58 60 72
PPBUS_R_G3H
VOLTAGE=1.25V 6 7 8 42 52 53 54 55 59 72
MAKE_BASE=TRUE PP3V3_S3 6 7 8 36 42 44 48 51 58 60 72
PPVCORE_S0_NB_GFX 6 7 8 18 22 45 53 65 72
72 64 59 56 50 45 37 8 7 6 PPBUS_G3H PPBUS_G3H 6 7 8 37 45 50 56 59 64 72
72 60 58 40 8 7 6 PP5V_S3 PP5V_S3 6 7 8 40 58 60 72 MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm VOLTAGE=18.5V
72 63 53 52
27 22 8 7 6 PP5V_S0 PP5V_S0 6 7 8 22 27 40 43 47 51 52 53 MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE
51 47 43 40 MIN_LINE_WIDTH=0.30 MM 63 72 VOLTAGE=5V
MIN_NECK_WIDTH=0.20 MM MAKE_BASE=TRUE PPBUS_G3H
VOLTAGE=5V 6 7 8 37 45 50 56 59 64 72
MAKE_BASE=TRUE PPBUS_G3H 6 7 8 37 45 50 56 59 64 72
PP5V_S0 6 7 8 22 27 40 43 47 51 52 53 PP5V_S3 6 7 8 40 58 60 72
63 72 PPBUS_G3H 6 7 8 37 45 50 56 59 64 72
PP5V_S0 6 7 8 22 27 40 43 47 51 52 53 PP5V_S3 6 7 8 40 58 60 72
63 72 PPBUS_G3H 6 7 8 37 45 50 56 59 64 72
PP5V_S0 6 7 8 22 27 40 43 47 51 52 53
63 72 PPBUS_G3H 6 7 8 37 45 50 56 59 64 72
PP5V_S0 6 7 8 22 27 40 43 47 51 52 53
63 72
PP5V_S0 6 7 8 22 27 40 43 47 51 52 53
63 72
PP5V_S0 6 7 8 22 27 40 43 47 51 52 53
PP5V_S0
63 72
6 7 8 22 27 40 43 47 51 52 53
Power Aliases
63 72
PP5V_S0
A 6 7 8 22 27 40 43 47 51 52 53
63 72
SYNC_MASTER=WFERRY

A
D 051-7230 B.0.0

NONE 8 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
EMI SPRING CLIPS LVDS ALIASES USB ALIASES

SATA ALIASES
PLACE CLIPS PER MCO ON TOPSIDE NEAR BATTERY CONNECTOR J6900 NO-CONNECT UNUSED LVDS INTERFACE PORTS
NO_TEST NO-CONNECT UNUSED SATA INTERFACE PORTS USB PORT [0] = External USB2.0 Port A
NC_SATA_A_D2R_N NC_SATA_A_D2R_N 69
CRITICAL CRITICAL 67 15 9 NC_LVDS_B_CLK_N NC_LVDS_B_CLK_N TRUE 9 15 67 69 9 TRUE 9 69 69 39 24 9 6 USB2_EXTA_P 39 24 9 6 USB2_EXTA_P USB2_EXTA_P 6 9 24 39 69
MAKE_BASE=TRUE MAKE_BASE=TRUE
SC0900
1 EMI-SPRING
SC0901
1 EMI-SPRING
67 15 9 NC_LVDS_B_CLK_P NC_LVDS_B_CLK_P TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
9 15 67 69 9 NC_SATA_A_D2R_P NC_SATA_A_D2R_P TRUE
MAKE_BASE=TRUE
9 69 69 39 24 9 6 USB2_EXTA_N
69
39 24 9 6
39 24
USB2_EXTA_N
MAKE_BASE=TRUE
USB2_EXTA_N 6 9 24 39 69
15 9 NC_LVDS_B_DATA_N0 NC_LVDS_B_DATA_N0 TRUE 9 15 69 23 9 NC_SATA_A_R2D_C_N NC_SATA_A_R2D_C_N TRUE 9 23 69 39 24 13 9 7 6 EXTAUSB_OC_L 13 9 7 6 EXTAUSB_OC_L EXTAUSB_OC_L 6 7 9 13 24 39

PS-25N PS-25N MAKE_BASE=TRUE
15 9 NC_LVDS_B_DATA_N1 NC_LVDS_B_DATA_N1 TRUE 9 15 69 23 9 NC_SATA_A_R2D_C_P NC_SATA_A_R2D_C_P TRUE 9 23 69 USB2_MUXED_EXTA_N USB2_MUXED_EXTA_N 6 9 39 69
69 39 9 6
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
15 9 NC_LVDS_B_DATA_N2 NC_LVDS_B_DATA_N2 TRUE 9 15 69 39 9 6 USB2_MUXED_EXTA_P USB2_MUXED_EXTA_P 6 9 39 69
MAKE_BASE=TRUE 69 9 NC_SATA_B_D2R_N NC_SATA_B_D2R_N TRUE 9 69 MAKE_BASE=TRUE
67 9 NC_LVDS_B_DATA_N3 NC_LVDS_B_DATA_N3 TRUE 9 67 MAKE_BASE=TRUE
69 9 NC_SATA_B_D2R_P NC_SATA_B_D2R_P TRUE 9 69
MAKE_BASE=TRUE
MAKE_BASE=TRUE
USB PORT [1] = PCI-E Mini Card
D 15 9
15 9
NC_LVDS_B_DATA_P0
NC_LVDS_B_DATA_P1
NC_LVDS_B_DATA_P0
NC_LVDS_B_DATA_P1
TRUE
TRUE
MAKE_BASE=TRUE
9 15
9 15
69 23 9
69 23 9
NC_SATA_B_R2D_C_N
NC_SATA_B_R2D_C_P
NC_SATA_B_R2D_C_N
NC_SATA_B_R2D_C_P
TRUE
MAKE_BASE=TRUE
TRUE
9 23 69
9 23 69
69 36 24 9 6 USB2_AIRPORT_P
69 36 24 9 6 USB2_AIRPORT_N
69 36
24 9 6
69 36
24 9 6
USB2_AIRPORT_P
MAKE_BASE=TRUE
USB2_AIRPORT_N
USB2_AIRPORT_P 6 9 24 36 69
USB2_AIRPORT_N 6 9 24 36 69
D
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
15 9 NC_LVDS_B_DATA_P2 NC_LVDS_B_DATA_P2 TRUE 9 15
MAKE_BASE=TRUE 69 9 NC_SATA_C_D2R_N NC_SATA_C_D2R_N TRUE 9 69
67 9 NC_LVDS_B_DATA_P3 NC_LVDS_B_DATA_P3 TRUE 9 67 MAKE_BASE=TRUE USB PORT [2] = Unused
MAKE_BASE=TRUE 69 9 NC_SATA_C_D2R_P NC_SATA_C_D2R_P TRUE 9 69 TP_USB2_3G_P 69 24 9 TP_USB2_3G_P TP_USB2_3G_P 9 24 69
MAKE_BASE=TRUE 69 24 9
67 9 NC_LVDS_A_DATA_P3 NC_LVDS_A_DATA_P3 TRUE 9 67 69 23 9 NC_SATA_C_R2D_C_N NC_SATA_C_R2D_C_N TRUE 9 23 69 TP_USB2_3G_N 69 24 9 TP_USB2_3G_N MAKE_BASE=TRUE TP_USB2_3G_N 9 24 69
MAKE_BASE=TRUE
BOSSES TO CONNECT TO HEATSINK 67 9 NC_LVDS_A_DATA_N3 NC_LVDS_A_DATA_N3 TRUE
MAKE_BASE=TRUE
9 67 69 23 9 NC_SATA_C_R2D_C_P NC_SATA_C_R2D_C_P TRUE
MAKE_BASE=TRUE
9 23 69 MAKE_BASE=TRUE
USB PORT [3] = CAMERA
Z0900 STANDOFFS 69 60 24 9 6 USB2_CAMERA_P

69 60
24 9 6 USB2_CAMERA_P USB2_CAMERA_P 6 9 24 60 69
4.0OD2.0H-M2X0.4
CLOCK ALIASES 69 60 MAKE_BASE=TRUE
Z0910 PCI_EXPRESS GRAPHICS ALIASES NO-CONNECT UNUSED CLOCK INTERFACE PORTS
69 60 24 9 6 USB2_CAMERA_N 24 9 6 USB2_CAMERA_N
MAKE_BASE=TRUE
USB2_CAMERA_N 6 9 24 60 69
1 STDOFF-4.0OD2.4H-0.5-THNP NO-CONNECT UNUSED SDVO INTERFACE PORTS
1 15 9 NC_PEG_D2R_N0 NC_PEG_D2R_N0 TRUE 9 15 29 9 NC_CK505_SRC1_N NC_CK505_SRC1_N TRUE 9 29 USB PORT [4] = IR CONTROLLER
NC_PEG_D2R_N2 NC_PEG_D2R_N2 NC_CK505_SRC1_P NC_CK505_SRC1_P 69
15 9 TRUE 9 15 29 9 TRUE 9 29 69 40 24 9 7 6 USB_IR_P 40 24 9 7 6 USB_IR_P USB_IR_P
MAKE_BASE=TRUE MAKE_BASE=TRUE 6 7 9 24 40 69
15 9 NC_PEG_D2R_N3 NC_PEG_D2R_N3 TRUE 9 15 29 9 NC_CK505_SRC_CLKREQ1_L NC_CK505_SRC_CLKREQ1_LTRUE 9 29 69 40 24 9 7 6 USB_IR_N USB_IR_N MAKE_BASE=TRUE USB_IR_N
MAKE_BASE=TRUE 6 7 9 24 40 69
Z0911 15 9 NC_PEG_D2R_N4 NC_PEG_D2R_N4 TRUE
MAKE_BASE=TRUE
9 15 29 9 NC_CK505_SRC3_N NC_CK505_SRC3_N TRUE 9 29 MAKE_BASE=TRUE
STDOFF-4.0OD2.4H-0.5-THNP 15 9 NC_PEG_D2R_N5 NC_PEG_D2R_N5 TRUE

MAKE_BASE=TRUE
9 15 29 9 NC_CK505_SRC3_P NC_CK505_SRC3_P TRUE
MAKE_BASE=TRUE
9 29 USB PORT [5] = Trackpad(Wellspring)
1 15 9 NC_PEG_D2R_N6 NC_PEG_D2R_N6 TRUE 9 15 29 9 NC_CK505_SRC_CLKREQ3_L NC_CK505_SRC_CLKREQ3_LTRUE 9 29 69 40 24 9 7 6 USB2_WSPRING_P
69 40 24
9 7 6 USB2_WSPRING_P USB2_WSPRING_P 6 7 9 24 40 69
MAKE_BASE=TRUE
Z0902 15 9 NC_PEG_D2R_N7 NC_PEG_D2R_N7 TRUE
MAKE_BASE=TRUE
9 15 29 9 NC_CK505_SRC4_N NC_CK505_SRC4_N TRUE 9 29
69 40 24 9 7 6 USB2_WSPRING_N
69 40 24
9 7 6
MAKE_BASE=TRUE
USB2_WSPRING_N USB2_WSPRING_N 6 7 9 24 40 69
4.0OD2.0H-M2X0.4 15 9 NC_PEG_D2R_N8 NC_PEG_D2R_N8 TRUE
MAKE_BASE=TRUE
9 15 29 9 NC_CK505_SRC4_P NC_CK505_SRC4_P TRUE
MAKE_BASE=TRUE
9 29 MAKE_BASE=TRUE
1 15 9 NC_PEG_D2R_N9 NC_PEG_D2R_N9 TRUE 9 15 29 9 NC_CK505_SRC_CLKREQ4_L NC_CK505_SRC_CLKREQ4_LTRUE 9 29 USB PORT [6] = BLUETOOTH
Z0912 NC_PEG_D2R_N10 NC_PEG_D2R_N10 TRUE
MAKE_BASE=TRUE
NC_CK505_SRC7_N NC_CK505_SRC7_N TRUE
MAKE_BASE=TRUE
STDOFF-4.0OD2.4H-0.5-THNP 15 9
MAKE_BASE=TRUE
9 15 29 9
MAKE_BASE=TRUE
9 29
69 24 9 NC_USB_BT_P 69 24 9 NC_USB_BT_P NC_USB_BT_P 9 24 69
15 9 NC_PEG_D2R_N11 NC_PEG_D2R_N11 TRUE 9 15 29 9 NC_CK505_SRC7_P NC_CK505_SRC7_P TRUE 9 29 MAKE_BASE=TRUE
Z0903 1
NC_PEG_D2R_N12 NC_PEG_D2R_N12 TRUE
MAKE_BASE=TRUE
29 9 NC_CK505_PGMODE NC_CK505_PGMODE TRUE
MAKE_BASE=TRUE
69 24 9 NC_USB_BT_N 69 24 9 NC_USB_BT_N
MAKE_BASE=TRUE
NC_USB_BT_N 9 24 69
4.0OD2.0H-M2X0.4 15 9
MAKE_BASE=TRUE
9 15
MAKE_BASE=TRUE
9 29
15 9 NC_PEG_D2R_N13 NC_PEG_D2R_N13 TRUE 9 15 29 9 NC_CK505_SRC8_N NC_CK505_SRC8_N TRUE 9 29

1 MAKE_BASE=TRUE MAKE_BASE=TRUE USB PORT [7] = Unused
15 9 NC_PEG_D2R_N14 NC_PEG_D2R_N14 TRUE 9 15 29 9 NC_CK505_SRC8_P NC_CK505_SRC8_P TRUE 9 29
MAKE_BASE=TRUE MAKE_BASE=TRUE 69 24 9 NC_USB2_EXTB_P NC_USB2_EXTB_P 9 24 69
15 9 NC_PEG_D2R_N15 NC_PEG_D2R_N15 TRUE 9 15 29 9 NC_CK505_SRC_CLKREQ8_L NC_CK505_SRC_CLKREQ8_LTRUE 9 29
MAKE_BASE=TRUE
MAKE_BASE=TRUE MAKE_BASE=TRUE 69 24 9 NC_USB2_EXTB_N NC_USB2_EXTB_N 9 24 69

MAKE_BASE=TRUE 24
15 9 NC_PEG_D2R_P0 NC_PEG_D2R_P0 TRUE 9 15
C 15 9 NC_PEG_D2R_P2
NC_PEG_D2R_P3
NC_PEG_D2R_P2
NC_PEG_D2R_P3
TRUE
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
9 15
29 9
29 9
NC_GPU_STOP_L
NC_CK505_PCI1_CLK
NC_GPU_STOP_L
NC_CK505_PCI1_CLK TRUE
TRUE
MAKE_BASE=TRUE
9 29
24 13 9 7 6 EXTBUSB_OC_L 13 9 7 6 EXTBUSB_OC_L
MAKE_BASE=TRUE
EXTBUSB_OC_L 6 7 9 13 24
C
15 9
MAKE_BASE=TRUE
9 15
MAKE_BASE=TRUE
9 29 USB PORT [8] = Unused
15 9 NC_PEG_D2R_P4 NC_PEG_D2R_P4 TRUE 9 15 29 9 NC_CK505_PCI2_CLK NC_CK505_PCI2_CLK TRUE 9 29 TP_USB_EXCARD_P TP_USB_EXCARD_P 9 24 69
MAKE_BASE=TRUE MAKE_BASE=TRUE 69 24 9
15 9 NC_PEG_D2R_P5 NC_PEG_D2R_P5 TRUE 9 15 29 9 NC_CK505_PCI4_CLK NC_CK505_PCI4_CLK TRUE 9 29
SMC ALIASES 15 9 NC_PEG_D2R_P6 NC_PEG_D2R_P6 TRUE
MAKE_BASE=TRUE
9 15
MAKE_BASE=TRUE
69 24 9
MAKE_BASE=TRUE
TP_USB_EXCARD_N TP_USB_EXCARD_N 9 24 69
NO-CONNECT UNUSED SMC INTERFACE PORTS MAKE_BASE=TRUE MAKE_BASE=TRUE
NO_TEST MAKE_BASE=TRUE
USB PORT [9] = Unused
41 9 NC_SMC_PA0 NC_SMC_PA0 TRUE
MAKE_BASE=TRUE
9 41
15 9 NC_PEG_D2R_P9 NC_PEG_D2R_P9 TRUE
MAKE_BASE=TRUE
9 15
SB ALIASES 69 24 9
TP_USB_EXTC_P TP_USB_EXTC_P 9 24 69
41 9 NC_SMC_PA1 NC_SMC_PA1 TRUE 9 41 MAKE_BASE=TRUE NO-CONNECT UNUSED INTERFACE PORTS

MAKE_BASE=TRUE
TP_USB_EXTC_N TP_USB_EXTC_N 9 24 69
MAKE_BASE=TRUE 15 9 NC_PEG_D2R_P10 NC_PEG_D2R_P10 TRUE 9 15 69 24 9
41 9 NC_SMC_PB0 NC_SMC_PB0 TRUE 9 41 MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE 15 9 NC_PEG_D2R_P11 NC_PEG_D2R_P11 TRUE 9 15 28 25 9 6 VR_PWRGD_CK505 VR_PWRGD_CK505 6 9 25 28
41 9 NC_SMC_PG0 NC_SMC_PG0 TRUE 9 41 MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE 15 9 NC_PEG_D2R_P12 NC_PEG_D2R_P12 TRUE 9 15 28 25 9 6 PM_SB_PWROK PM_SB_PWROK 6 9 25 28
41 9 NC_SMC_P14 NC_SMC_P14 TRUE 9 41 MAKE_BASE=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE 15 9 NC_PEG_D2R_P13 NC_PEG_D2R_P13 TRUE 9 15
41 9 NC_SMC_P20 NC_SMC_P20 TRUE 9 41 MAKE_BASE=TRUE
MAKE_BASE=TRUE 15 9 NC_PEG_D2R_P14 NC_PEG_D2R_P14 TRUE 9 15 70 PCI_AD<0..31> NC_PCI_AD<0..31> TRUE 24 70
MAKE_BASE=TRUE 15 9 NC_PEG_D2R_P15 NC_PEG_D2R_P15 TRUE 9 15 70 PCI_C_BE_L<0..3> NC_PCI_C_BE_L<0..3>TRUE 24
MAKE_BASE=TRUE 15 9 NC_PEG_R2D_C_N4 NC_PEG_R2D_C_N4 TRUE 9 15 70 24 9 NC_PCI_PAR NC_PCI_PAR TRUE 9 24 70
MAKE_BASE=TRUE 15 9 NC_PEG_R2D_C_N5 NC_PEG_R2D_C_N5 TRUE 9 15 24 9 6 TP_PCI_RST_L TP_PCI_RST_L 6 9 24
MAKE_BASE=TRUE 15 9 NC_PEG_R2D_C_N6 NC_PEG_R2D_C_N6 TRUE 9 15
41 9 NC_SMC_P43 NC_SMC_P43 TRUE

MAKE_BASE=TRUE
9 41
15 9 NC_PEG_R2D_C_N8 NC_PEG_R2D_C_N8 TRUE
MAKE_BASE=TRUE
9 15 NB ALIASES
MAKE_BASE=TRUE 15 9 NC_PEG_R2D_C_N9 NC_PEG_R2D_C_N9 TRUE 9 15 GFX_VR_EN GFX_VR_EN
53 16 9 6
MAKE_BASE=TRUE
6 9 16 53
MAKE_BASE=TRUE 15 9 NC_PEG_R2D_C_N10 NC_PEG_R2D_C_N10 TRUE 9 15 VR_PWRGOOD_DELAY VR_PWRGOOD_DELAY
52 28 16 9 6
MAKE_BASE=TRUE
6 9 16 28 52
MAKE_BASE=TRUE 15 9 NC_PEG_R2D_C_N11 NC_PEG_R2D_C_N11 TRUE 9 15 71 30 29 16 9 6
NB_CLK96M_DOT_P NB_CLK96M_DOT_P 6 9 16 29 30 71
NB_CLK96M_DOT_N NB_CLK96M_DOT_N 6 9 16 29 30 71
MAKE_BASE=TRUE 15 9 NC_PEG_R2D_C_N13 NC_PEG_R2D_C_N13 TRUE 9 15 71 30 29 16 9 6 NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_P 6 9 16 29 30 71
41 9 NC_SMC_P64 NC_SMC_P64 TRUE 9 41 MAKE_BASE=TRUE 71 30 29 16 9 6 NB_CLK100M_DPLLSS_N NB_CLK100M_DPLLSS_N MAKE_BASE=TRUE
MAKE_BASE=TRUE
41 9 NC_SMC_P81 NC_SMC_P81 TRUE 9 41
B 41 9 NC_SMC_GFX_OVERTEMP_L NC_SMC_GFX_OVERTEMP_L TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
9 41
15 9
15 9
NC_PEG_R2D_C_P4
NC_PEG_R2D_C_P5
NC_PEG_R2D_C_P4
NC_PEG_R2D_C_P5
TRUE
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
9 15
9 15 64 15 9 6 LCDBKLT_PWM_UNBUF LCDBKLT_PWM_UNBUF 6 9 15 64
B
41 9 NC_EXCARD_OC_L NC_EXCARD_OC_L TRUE 9 41 MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE 15 9 NC_PEG_R2D_C_P6 NC_PEG_R2D_C_P6 TRUE 9 15 64 15 9 6 LCDBKLT_PWREN LCDBKLT_PWREN 6 9 15 64
41 9 NC_SMC_BATT_TRICKLE_EN_L NC_SMC_BATT_TRICKLE_EN_L TRUE 9 41 MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE 15 9 NC_PEG_R2D_C_P7 NC_PEG_R2D_C_P7 TRUE 9 15
41 9 NC_SMC_EXCARD_CP NC_SMC_EXCARD_CP TRUE 9 41 MAKE_BASE=TRUE
41 9 NC_SMC_ENRGYSTR_LDO_EN NC_SMC_ENRGYSTR_LDO_EN TRUE 9 41 MAKE_BASE=TRUE
41 9 NC_SMC_ENRGYSTR_LDO_PGOOD NC_SMC_ENRGYSTR_LDO_PGOODTRUE 9 41 MAKE_BASE=TRUE
41 9 NC_ALS_RIGHT NC_ALS_RIGHT TRUE 9 41 MAKE_BASE=TRUE
41 9 NC_ALS_GAIN NC_ALS_GAIN TRUE 9 41 MAKE_BASE=TRUE
41 9 NC_SMC_EXCARD_PWR_EN NC_SMC_EXCARD_PWR_EN TRUE 9 41 MAKE_BASE=TRUE
41 9 NC_SMC_FAN_1_CTL NC_SMC_FAN_1_CTL TRUE 9 41 MAKE_BASE=TRUE
MAKE_BASE=TRUE
41 9 NC_SMC_FAN_1_TACH NC_SMC_FAN_1_TACH TRUE 9 41
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
41 9 NC_SMC_PF0 NC_SMC_PF0 TRUE 9 41
MAKE_BASE=TRUE
41 9 NC_SMC_BATT_VSET NC_SMC_BATT_VSET TRUE 9 41
MAKE_BASE=TRUE
41 9 NC_SMC_SYS_VSET NC_SMC_SYS_VSET TRUE 9 41
41 9 NC_SMC_RSTGATE_L NC_SMC_RSTGATE_L TRUE

MAKE_BASE=TRUE
9 41
AUDIO ALIASES
MAKE_BASE=TRUE
41 9 NC_SMC_GFX_THROTTLE_L NC_SMC_GFX_THROTTLE_L TRUE 9 41 69 37 23 9 7 6 HDA_BIT_CLK HDA_BIT_CLK 6 7 9 23 37 69
41 9 NC_SYS_ISET NC_SYS_ISET TRUE 9 41 69 37 23 9 7 6 HDA_SYNC HDA_SYNC 6 7 9 23 37 69
41 9 NC_BATT_ISET NC_BATT_ISET TRUE 9 41 69 37 23 9 6 HDA_RST_L HDA_RST_L 6 9 23 37 69
41 9 NC_ISENSE_CAL_EN NC_ISENSE_CAL_EN TRUE 9 41 69 37 23 9 7 6 HDA_SDIN0 HDA_SDIN0 6 7 9 23 37 69
41 9 NC_SMC_FWE NC_SMC_FWE TRUE 9 41 69 37 23 9 7 6 HDA_SDOUT HDA_SDOUT 6 7 9 23 37 69
41 9 NC_SMC_ANALOG_ID NC_SMC_ANALOG_ID TRUE

MAKE_BASE=TRUE
9 41
MAKE_BASE=TRUE SIGNAL ALIAS /RESET
MAKE_BASE=TRUE
NC_SMC_TEST_DAC1 NC_SMC_TEST_DAC1
A 41 9
41 9 NC_SMC_TEST_DAC2 NC_SMC_TEST_DAC2
TRUE
TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
9 41
9 41
SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)
A
41 9 NC_SMC_TEST_DAC3 NC_SMC_TEST_DAC3 TRUE 9 41
MAKE_BASE=TRUE
GND
VOLTAGE=0V SIZE DRAWING NUMBER REV.
MIN_NECK_WIDTH=0.20 MM
48 41 9 6
42 41 36 9 6
SMC_SMS_INT
MAKE_BASE=TRUE
SMC_ADAPTER_EN
SMC_SMS_INT
SMC_ADAPTER_EN
6 9 41 48
6 9 36 41 42
MIN_LINE_WIDTH=0.30 MM
D 051-7230 B.0.0
MAKE_BASE=TRUE APPLE INC. SCALE SHT OF

NONE 9 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
66 14 FSB_A_L<3> P2 A3* OMIT ADS* M4 FSB_ADS_L 14 66

BI BI
66 14 BI FSB_A_L<4> V4 A4* U1000 BNR* J5 FSB_BNR_L BI 14 66
66 14 BI FSB_A_L<5> W1 A5* MEROM_SFF

(1 OF 8) BPRI* L5 FSB_BPRI_L BI 14 66
66 14 FSB_A_L<6> T4 A6* BGA

BI PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21
66 14 BI FSB_A_L<7> AA1 A7* DEFER* N5 FSB_DEFER_L BI 14 66 23 26 27 30 42 54 72
66 14 BI FSB_A_L<8> AB4 A8* DRDY* F38 FSB_DRDY_L BI 14 66

1
66 14 FSB_A_L<9> T2 A9* DBSY* J1 FSB_DBSY_L 14 66
R1002
BI BI 54.9
66 14 BI FSB_A_L<10> AC5 A10* 1%
1/20W
66 14 BI FSB_A_L<11> AD2 A11* BR0* M2 FSB_BREQ0_L BI 14 66 MF
2 201
D 66 14
66 14
BI
BI
FSB_A_L<12>
FSB_A_L<13>
AD4
AA5
A12*
A13* IERR* B40 CPU_IERR_L
D
66 14 BI FSB_A_L<14> AE5 A14* INIT* D8 CPU_INIT_L IN 6 23 66
66 14 BI FSB_A_L<15> AB2 A15*

66 14 BI FSB_A_L<16> AC1 A16* LOCK* N1 FSB_LOCK_L BI 14 66
66 14 BI FSB_ADSTB_L<0> Y4 ADSTB0*
ADDR GROUP0
RESET* G5 FSB_CPURST_L IN 6 13 14 66
66 14 FSB_REQ_L<0> R1 REQ0* RS0* K2 FSB_RS_L<0> 14 66
CONTROL
BI IN
66 14 BI FSB_REQ_L<1> R5 REQ1* RS1* H4 FSB_RS_L<1> IN 14 66
66 14 BI FSB_REQ_L<2> U1 REQ2* RS2* K4 FSB_RS_L<2> IN 14 66
66 14 BI FSB_REQ_L<3> P4 REQ3* TRDY* L1 FSB_TRDY_L IN 14 66
66 14 BI FSB_REQ_L<4> W5 REQ4*
OMIT
HIT* H2 FSB_HIT_L BI 14 66
PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21
66 14 BI FSB_A_L<17> AN1 A17* HITM* F2 FSB_HITM_L BI 14 66 23 26 27 30 42 54 72 66 14 BI FSB_D_L<0> F40 D0* D32* AP44 FSB_D_L<32> BI 14 66
66 14 BI FSB_A_L<18> AK4 A18* 66 14 BI FSB_D_L<1> G43 D1* U1000 D33* AR43 FSB_D_L<33> BI 14 66
66 14 BI FSB_A_L<19> AG1 A19* BPM0* AY8 XDP_BPM_L<0> BI 6 7 13 66 66 14 BI FSB_D_L<2> E43 D2* MEROM_SFF
(2 OF 8) D34* AH40 FSB_D_L<34> BI 14 66
XDP/ITP SIGNALS
1
66 14 FSB_A_L<20> AT4 A20* BPM1* BA7 XDP_BPM_L<1> 6 7 13 66
R1003 66 14 FSB_D_L<3> J43 D3* BGA D35* AF40 FSB_D_L<35> 14 66
BI BI BI BI
54.9
FSB_A_L<21> AK2 A21* BPM2* BA5 XDP_BPM_L<2> FSB_D_L<4> H40 D4* D36* AJ43 FSB_D_L<36>
ADDR GROUP1
66 14 BI BI 6 7 13 66 1% 66 14 BI BI 14 66
1/20W
66 14 BI FSB_A_L<22> AT2 A22* BPM3* AY2 XDP_BPM_L<3> BI 6 7 13 66 MF 66 14 BI FSB_D_L<5> H44 D5* D37* AG41 FSB_D_L<37> BI 14 66
201
66 14 FSB_A_L<23> AH2 A23* PRDY* AV10 XDP_BPM_L<4> 6 7 13 66
2 66 14 FSB_D_L<6> G39 D6* D38* AF44 FSB_D_L<38> 14 66
BI BI BI BI
66 14 BI FSB_A_L<24> AF4 A24* PREQ* AV2 XDP_BPM_L<5> BI 6 7 13 66 66 14 BI FSB_D_L<7> E41 D7* D39* AH44 FSB_D_L<39> BI 14 66
66 14 BI FSB_A_L<25> AJ5 A25* TCK AV4 XDP_TCK IN 6 7 10 13 66 66 14 BI FSB_D_L<8> L41 D8* D40* AM44 FSB_D_L<40> BI 14 66
66 14 BI FSB_A_L<26> AH4 A26* TDI AW7 XDP_TDI IN 6 7 10 13 66 66 14 BI FSB_D_L<9> K44 D9* D41* AN43 FSB_D_L<41> BI 14 66
66 14 BI FSB_A_L<27> AM4 A27* TDO AU1 XDP_TDO OUT 6 7 10 13 66 66 14 BI FSB_D_L<10> N41 D10* D42* AM40 FSB_D_L<42> BI 14 66
66 14 BI FSB_A_L<28> AP4 A28* TMS AW5 XDP_TMS IN 6 7 10 13 66 66 14 BI FSB_D_L<11> T40 D11* D43* AK40 FSB_D_L<43> BI 14 66
66 14 BI FSB_A_L<29> AR5 A29* TRST* AV8 XDP_TRST_L IN 6 7 10 13 66 CPU_PROCHOT_L TO SMC 66 14 BI FSB_D_L<12> M40 D12* D44* AG43 FSB_D_L<44> BI 14 66
C 66 14
66 14
BI FSB_A_L<30>
FSB_A_L<31>
AJ1
AL1
A30*
A31*
1
R1004
AND CPU VR TO INFORM
CPU IS HOT
66 14
66 14
BI FSB_D_L<13>
FSB_D_L<14>
G41
M44
D13*
D14*
D45*
D46*
AP40
AN41
FSB_D_L<45>
FSB_D_L<46>
BI 14 66
14 66
C
BI BI BI
DATA GRP 0
DATA GRP 2
68
66 14 BI FSB_A_L<32> AM2 A32* THERMAL 5% 66 14 BI FSB_D_L<15> L43 D15* D47* AL41 FSB_D_L<47> BI 14 66
1/20W
66 14 BI FSB_A_L<33> AU5 A33* MF 66 14 BI FSB_DSTB_L_N<0> K40 DSTBN0* DSTBN2* AK44 FSB_DSTB_L_N<2> BI 14 66
201
66 14 FSB_A_L<34> AP2 A34* 2 66 14 FSB_DSTB_L_P<0> J41 DSTBP0* DSTBP2* AL43 FSB_DSTB_L_P<2> 14 66
BI BI BI
66 14 BI FSB_A_L<35> AR1 A35* PROCHOT* D38 CPU_PROCHOT_L OUT 6 42 52 66 66 14 BI FSB_DINV_L<0> P40 DINV0* DINV2* AJ41 FSB_DINV_L<2> BI 14 66
66 14 BI FSB_ADSTB_L<1> AN5 ADSTB1* THRMDA BB34 CPU_THERMD_P OUT 6 46 66
THRMDC BD34 CPU_THERMD_N OUT 6 46 66
DATA GRP 3
IN CPU_A20M_L C7 A20M* FSB_D_L<16> P44 D16* D48* AV38 FSB_D_L<48>
DATA GRP1
66 23 6 66 14 BI BI 14 66
66 23 6 OUT CPU_FERR_L D4 FERR* THERMTRIP* B10 PM_THRMTRIP_L OUT 6 16 23 42 66 66 14 BI FSB_D_L<17> V40 D17* D49* AT44 FSB_D_L<49> BI 14 66 LAYOUT NOTE:
PM_THRMTRIP#
66 23 6 IN CPU_IGNNE_L F10 IGNNE* 66 14 BI FSB_D_L<18> V44 D18* D50* AV40 FSB_D_L<50> BI 14 66 COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE
SHOULD CONNECT TO
ICH 66 14 BI FSB_D_L<19> AB44 D19* D51* AU41 FSB_D_L<51> BI 14 66 TRACE LENGTH SHORTER THAN 0.5".
H CLK ICH AND GMCH
66 23 6 IN CPU_STPCLK_L F8 STPCLK* 66 14 BI FSB_D_L<20> R41 D20* D52* AW41 FSB_D_L<52> BI 14 66 COMP1,3 CONNECT WITH ZO=55OHM, MAKE
WITHOUT T-ING (NO
66 23 6 IN CPU_INTR C9 LINT0 66 14 BI FSB_D_L<21> W41 D21* D53* AR41 FSB_D_L<53> BI 14 66 TRACE LENGTH SHORTER THAN 0.5".
STUB)
66 23 6 IN CPU_NMI C5 LINT1 BCLK0 A35 FSB_CLK_CPU_P IN 6 29 30 71 66 14 BI FSB_D_L<22> N43 D22* D54* BA37 FSB_D_L<54> BI 14 66
66 23 6 IN CPU_SMI_L E5 SMI* BCLK1 C35 FSB_CLK_CPU_N IN 6 29 30 71 66 14 BI FSB_D_L<23> U41 D23* D55* BB38 FSB_D_L<55> BI 14 66
66 14 BI FSB_D_L<24> AA41 D24* D56* AY36 FSB_D_L<56> BI 14 66
66 14 BI FSB_D_L<25> AB40 D25* D57* AT40 FSB_D_L<57> BI 14 66
66 14 BI FSB_D_L<26> AD40 D26* D58* BC35 FSB_D_L<58> BI 14 66

28 13 7 6 OUT XDP_DBRESET_L J7 DBR*
66 14 BI FSB_D_L<27> AC41 D27* D59* BC39 FSB_D_L<59> BI 14 66
RSVD7 J9 NC_CPU_RSVD7
66 14 BI FSB_D_L<28> AA43 D28* D60* BA41 FSB_D_L<60> BI 14 66
NC_CPU_TEST1 E37 TEST1 RSVD9 F4 NC_CPU_RSVD9
R1016
66 14 BI FSB_D_L<29> Y40 D29* D61* BB40 FSB_D_L<61> BI 14 66
NC_CPU_TEST2 D40 TEST2 RSVD10 H8 NC_CPU_RSVD10 21 19 18 14 13 12 11 10 8 7 6 PP1V05_S0 27.4
72 54 42 30 27 26 23 66 14 FSB_D_L<30> Y44 D30* D62* BA35 FSB_D_L<62> 14 66 1 2
NC_CPU_TEST3 C43 V2 NC_CPU_RSVD11 BI BI
TEST3 RSVD11
66 14 BI FSB_D_L<31> T44 D31* D63* AU43 FSB_D_L<63> BI 14 66 1%
NC_CPU_TEST4 AE41 TEST4 RSVD12 Y2 NC_CPU_RSVD12 1 1/20W
R1005 66 14 FSB_DSTB_L_N<1> U43 DSTBN1* DSTBN3* AY40 FSB_DSTB_L_N<3> 14 66
R1017 MF
NC_CPU_TEST5 NC_CPU_RSVD13 BI BI
AY10 TEST5 RSVD13 AG5 1K 54.9 201
1% 66 14 FSB_DSTB_L_P<1> W43 DSTBP1* DSTBP3* AY38 FSB_DSTB_L_P<3> 14 66 1 2
NC_CPU_TEST6 AC43 AL5 NC_CPU_RSVD14 BI BI
TEST6 RSVD14 1/20W
B MF
201
2 0.5" MAX LENGTH FOR CPU_GTLREF
66 14 BI FSB_DINV_L<1> R43 DINV1* DINV3* BC37 FSB_DINV_L<3> BI 14 66 1%
1/20W
MF R1018 B
201 27.4
66 6 CPU_GTLREF AW43 GTLREF COMP0 AE43 66 6 CPU_COMP<0> 1 2
MISC COMP1 AD44 66 6 CPU_COMP<1> 1%
1/20W
1 COMP2 AE1 66 6 CPU_COMP<2> R1019 MF
R1006 54.9 201
2K COMP3 AF2 66 6 CPU_COMP<3> 1 2
1%
R1020 PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 1/20W 1%
54.9 23 26 27 30 42 54 72 MF 1/20W
66 13 10 7 6 XDP_TMS 1 2 201 DPRSTP* G7 CPU_DPRSTP_L 6 16 23 52 66 MF
2 IN 201
1% DPSLP* B8 CPU_DPSLP_L IN 6 23 66
1/20W
R1021 MF DPWR* C41 FSB_DPWR_L IN 14 66
54.9 201
66 13 10 7 6 XDP_TDI 1 2 66 30 6 CPU_BSEL<0> A37 BSEL0 PWRGOOD E7 CPU_PWRGD 6 13 23 66
OUT IN
1% 66 30 6 OUT CPU_BSEL<1> C37 BSEL1 SLP* D10 FSB_CPUSLP_L IN 14 66
1/20W
MF R1024 66 30 6 OUT CPU_BSEL<2> B38 BSEL2 PSI* BD10 NC_CPU_PSI_L
201 54.9
66 13 10 7 6 XDP_TDO 1 2
PLACEMENT_NOTE=Place R1024 near ITP connector (if present) 1%
1/20W
MF
201
R1022
54.9
66 13 10 7 6 XDP_TCK 1 2
1%
1/20W
R1023 MF
649 201
66 13 10 7 6 XDP_TRST_L 1 2
1%
1/20W
MF
201 CPU FSB
A SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)
A
D 051-7230 B.0.0

NONE 10 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PPVCORE_S0_CPU PP1V05_S0 27 30 42 54 72
72 65 52 12 11 8 7 6 6 7 8 10 11 12 13
14 18 19 21 23 26 Y6 (6 OF 8) AJ3 B42 (4 OF 8) AP34 E21 (5 OF 8) AE17
OMIT OMIT
OMIT
PPVCORE_S0_CPU 6 7 8 11 12 52 65 72 BD30 (7 OF 8)
OMIT K20 (8 OF 8)
Y8
U1000 AG3 H42 U1000 AM34 E23
U1000 AE19
(CPU CORE POWER) 29A AE37 OMIT R13 AK6 BGA AE3 F42 BGA AV36 E25 BGA AR17
BB28 U1000 M16
MEROM_SFF
U1000
MEROM_SFF
MEROM_SFF
AP38 P12 AK8 AR3 D42 AT36 N21 AR19
BB30 BGA M18
AN37 BGA P14 AH6 AN3 D44 AY34 N23 AN17
MEROM_SFF
B24 K16
MEROM_SFF
H32 OMIT AD28 AL37 AB10 AH8 AL3 F44 AW33 N25 AN19
B22 K18
G33 U1000 AD30
H22 V20
C33 AD14 AF6 AW3 M42 AW35 L21 AL17
F32 MEROM_SFF AB28
H24 T20
B32 AC11 AF8 AU3 K42 AV34 L23 AL19
N33 (3 BGA
OF 8) AB30 H36 AC13 AP6 BD4 V42 AU35 L25 AW17
F22 P20
M32 Y28 F36 AB12 AP8 BC3 T42 BD36 J21 AW19
F24 V16
L33 Y30 G35 AB14 AM6 BB2 P42 BB36 J23 AU17
D24 V18
D K32
J33
AK26
AH26
D22 T16
F34
E33
AA11
AA13
AM8
AY6
BA3
G1
AD42
AB42
BC33
BA33
J25
W21
AU19
BC17
D
M22 T18
W33 AF26 E35 Y14 AW9 E1 Y42 C31 W23 BC19
M24 P16
V32 AK28 D32 AK10 AU7 AW1 AK42 C29 W25 BA17
K22 P18
U33 AK30 K36 AF10 AV6 BA1 AH42 C27 U21 BA19
K24 AD20
T32 AH28 N35 AK12 AU9 A39 AF42 G31 U23 C15
V22 AB20
R33 AH30 L35 AK14 AT6 VSS VSS A41 AP42 E31 U25 C11
V24 Y20
P32 AF28 J35 AJ11 AT8 A31 AM42 G27 R21 H10
T22 AD16
AD32 AF30 W35 AJ13 BD6 A27 AY42 G29 R23 G15
T24 AD18
AC33 AP26 V36 AH14 BC9 A29 AV42 E27 R25 E15
P22 AB16
AB32 VCC AM26 P36 AG11 BB6 A21 AT42 E29 AC21 M10
P24 AB18
AA33 AP28 U35 AG13 BA9 A23 AV44 N31 AC23 N15
AD22 Y16
Y32 AP30 R35 AF12 C3 A25 AY44 L31 AC25 L15
AD24 Y18
AK32 AM28 AB36 AF14 B4 A17 BB42 J31 AA21 J15
AB22 AK20
AJ33 AM30 AC35 AE11 G3 A19 BA43 N27 AA23 M12
AB24 AK16
AH32 AY26 AA35 AE13 E3 A15 C39 N29 AA25 T10
Y22 AK18
AG33 AV26 AK36 AP10 D2 A11 H38 L27 AJ21 W15
Y24 AH20
AF32 AT26 AF36 AR11 N3 A9 G37 L29 AJ23 U15
AK22 AF20
AE33 AY28 AJ35 AR13 L3 A5 E39 J27 AJ25 R15
AK24 AH16
AR33 AY30 AG35 AP12 J3 A7 N39 J29 AG21 T12
AH22 VCC VCC AH18
AP32 AV28 AE35 AN11 W3 M38 W31 AG23 AD10
AH24 AF16 VCCP VCCP
AN33 AV30 AP36 AN13 U3 L39 W27 AG25 Y10
AF22 AF18
AM32 AT28 AN35 AL11 R3 J39 W29 AE21 AC15
AF24 AP20
AL33 AT30 AL35 AL13 AC3 W39 U31 AE23 AA15
AP22 AM20
AY32 BD26 C13 AU11 AA3 U39 R31 AE25 AD12
AP24 AP16
AV32 BB26 B14 AU13 T38 U27 AR21 Y12
VCC AM22 AP18
AU33 BD28 B12 N7 R39 U29 AR23 AH10
C AT32
AT34 N37
(CPU IO POWER 1.05V) 2.5A
PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21
AM24
AY22
AM16
AM18
H12
H14
N9
L7
AD38
AC39
R27
R29
AR25
AN21
AJ15
AG15
C
23 26 27 30 42 54 72 AY24 AY20 VSS VSS
BD32 L37 G11 L9 AA39 VSS VSS AC31 AN23 AE15
AV22 AV20
BB32 K38 G13 W7 Y38 AA31 AN25 AH12
AV24 AT20
B26 J37 F12 W9 AJ39 AC27 AL21 AM10
AT22 AY16
B30 W37 F14 U7 AH38 AC29 AL23 AR15
AT24 AY18
B28 V38 E11 U9 AG39 AA27 AL25 AN15
BD22 AV16
H26 U37 E13 R7 AE39 AA29 AW21 AL15
BD24 AV18
F26 VCCP R37 D14 R9 AR37 AJ31 AW23 AM12
BB22 AT16
D26 P38 D12 AC7 AR39 AG31 AW25 AT10
BB24 AT18
H28 AC37 K10 AC9 AN39 AE31 AU21 AW15
B20 BD20
H30 AB38 N11 AA7 AM38 AJ27 AU23 AU15
B18 BB20
F28 AA37 N13 AA9 AL39 AJ29 AU25 AY12
B16 BD16
F30 AK38 M14 AJ7 AW37 AG27 BC21 AW11
H20 BD18
D30 AJ37 L11 AJ9 AW39 AG29 BC23 AW13
F20 BB16
D28 AG37 L13 AG7 AU37 AE27 BC25 AV12
D20 BB18
M26 AF38 K12 AG9 AU39 AE29 BA21 AT12
H16 AP14
K26 (CPU INTERNAL PLL POWER 1.5V) 0.130A VCCA=1.5 ONLY K14 AE7 AT38 AR31 BA23 BC15
H18 AM14
M28 B34 PP1V5_S0 6 7 8 12 22 J11 AE9 BD38 AR27 BA25 BA15
VCCA
26 27 54 72 F16 AY14
M30 D34 J13 AR7 BD40 AR29 C19 BC11
F18 AV14
K28 V10 AR9 BC41 AN31 C17
D18 AT14
K30 BD8 CPU_VID<0> OUT 6 12 52 66 P10 AN7 BA39 AL31 G17 BB12
D16 BD14
V26 BC7 CPU_VID<1> OUT 6 12 52 66 W11 AN9 B36 AN27 G19 BA11
M20 BB14
T26 BB10 CPU_VID<2> OUT 6 12 52 66 W13 AL7 D36 AN29 E17 BA13
P26 VID BB8 CPU_VID<3> OUT 6 12 52 66 V12 AL9 H34 AL27 E19 B6
PPVCORE_S0_CPU 6 7 8 11 12 52 65 72
V28 BC5 CPU_VID<4> OUT 6 12 52 66 V14 A33 M36 AL29 N17 H6
B V30
T28
BB4
AY4
CPU_VID<5>
CPU_VID<6>
OUT
OUT
6 12 52 66
6 12 52 66
1
U11
U13
A13 M34
K34
AW31
AU31
N19
L17
G9
F6
B
T30 R1100 T14 T36 AW27 L19 E9
100
P28 VCCSENSE BD12 1% R11 V34 AW29 J17 D6
1/20W
P30 MF T34 AU27 J19 M6
AD26 VSSSENSE BC13 2 201 P34 AU29 W17 M8
AB26 CPU_VCCSENSE_P OUT 6 52 66 AD36 BC31 W19 K6
Y26 Y36 BA31 U17 K8
CPU_VCCSENSE_N OUT 6 52 66 AD34 BC27 U19 U5
AB34 BC29 R17 V6
1 LAYOUT NOTE: Y34 BA27 R19 V8
R1101
100 PLACE R1100 AND R1101 AK34 BA29 AC17 T6
1%
LAYOUT NOTE: 1/20W
WITHIN 1 INCH OF CPU W/ NO STUB AH36 C25 AC19 T8
MF
CPU_VCCSENSE_P/CPU_VCCSENSE_N USE 201 AH34 C23 AA17 P6
2
ZO=27.4 OHM DIFFERENTIAL TRACE ROUTING. AF34 C21 AA19 P8
AR35 G21 AJ17 AD6
AM36 G23 AJ19 AD8
G25 AG17 AB6
LAYOUT NOTE: AG19 AB8
PROVIDE A TEST POINT (WITH NO STUB)
TO CONNECT A DIFFERENTIAL PROBE
BETWEEN VCCSENSE AND VSSSENSE
CPU Power & Ground


SYNC_DATE=(MASTER)
A
D 051-7230 B.0.0

NONE 11 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCORE HF AND BULK DECOUPLING

3x 330uF. 32x 10uF 0603, 28x 1uF 0402
Intel recommends 32+28 but is evaluating 24+24
72 65 52 11 8 7 6 PPVCORE_S0_CPU
D 10UF 0603 = APN:138S0568 = MURATA,TAIYO,TDK,SAMSUNG D

LAYOUT NOTE:
OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
PLACE ON OPPOSITE SIDE OF CPU
C1200 C1201 C1202 C1203 C1204 C1205 C1206 C1207 C1208 C1209
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
603 603 603 603 603 603 603 603 603 603
CPU VCORE VID CONNECTIONS
66 52 11 6 CPU_VID<0..6> IMVP6_VID<0..6> 66
MAKE_BASE=TRUE
LAYOUT NOTE: OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT
PLACE ON OPPOSITE SIDE OF CPU C1210 C1211 C1212 C1213 C1214 C1215 C1216 C1217 C1218 C1219
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R X5R X5R X5R X5R X5R X5R X5R X5R X5R
603 603 603 603 603 603 603 603 603 603
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
C 6.3V
X5R
603
6.3V
X5R
603
6.3V
X5R
603
6.3V
X5R
603
6.3V
X5R
603
6.3V
X5R
603
6.3V
X5R
603
6.3V
X5R
603
6.3V
X5R
603
6.3V
X5R
603
C
LAYOUT NOTE: OMIT OMIT

CRITICAL CRITICAL
PLACE ON OPPOSITE SIDE OF CPU C1230 C1231
10UF 10UF
20% 20%
6.3V 6.3V
X5R X5R
603 603
VCCA (CPU AVdd) DECOUPLING

LAYOUT NOTE: 72 54 27 26 22 11 8 7 6 PP1V5_S0
OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT 1x 10uF, 1x 0.01uF
C1240 C1241 C1242 C1243 C1244 C1245 C1246 C1247 C1248 C1249 OMIT
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF C1280 1 1
C1281
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 10uF 0.01UF
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM 20% 10%
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 6.3V 10V LAYOUT NOTE:
X5R 2 2 X5R
603 201 PLACE C1281 NEAR PIN B34 OF U1000
B B
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL 23 21 19 18 14 13 11 10 8 7 6 PP1V05_S0
72 54 42 30 27 26
VCCP (CPU I/O) DECOUPLING
PLACE ON OPPOSITE SIDE OF CPU C1250 C1251 C1252 C1253 C1254 C1255 C1256 C1257 C1258 C1259 1X 330UF, 12X 2.2UF
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM 1 OMIT
C1283 1 OMIT
C1284 1 OMIT
C1285 1 OMIT
C1286 1 OMIT
C1287 1 OMIT
C1288
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 6.3V
CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
LAYOUT NOTE: OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
PLACE ON OPPOSITE SIDE OF CPU C1260 C1261 C1262 C1263 C1264 C1265 C1266 C1267 CRITICAL
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT 1 OMIT
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V C1290 1 C1291 C1292 C1293 C1294 C1295 C1296
CERM CERM CERM CERM CERM CERM CERM CERM 330UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V
2.5V 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 6.3V
CERM
POLY
CASE-C2-SM-1 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
LAYOUT NOTE:
PLACE C1290 CLOSE TO CPU
PLACE C1283-C1288 CLOSE TO FSB ADDRESS PINS
PLACE C1291-C1296 CLOSE TO FSB DATA PINS
CPU Decoupling & VID
LAYOUT NOTE: CRITICAL CRITICAL CRITICAL
A PLACE ON SAME SIDE AS CPU 1

C1270
330UF
1
C1271
330UF
1
C1272
330UF
LAYOUT NOTE:
PLACE ON SAME SIDE AS CPU
SYNC_MASTER=MSARWAR

A
20% 20% 20%
3 2 2.0V 3 2 2.0V 3 2 2.0V
TANT TANT TANT THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
D2T D2T D2T PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
Intel recommends 3x220UF @ 9mOHM
D 051-7230 B.0.0

NONE 12 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Mini-XDP Connector
NOTE: This is not the standard XDP pinout.
Use with 920-0451 adapter board to support CPU, NB & SB debugging.
64 63 60
26 25 24 23 22 21 19 16 8 7 6 PP3V3_A_S0
53 52 51 46 44 42 30 29 28 27
23 21 19 18 14 12 11 10 8 7 6 PP1V05_S0
72 54 42 30 27 26
XDP XDP XDP

CRITICAL
R1315 1 R13301 1
R1331 XDP_CONN
54.9
1%
10K
5% 5%
10K J1300
1/20W 1/20W 1/20W LTH-030-01-G-D-NOPEGS
MF MF MF F-ST-SM
201 2
201 2 2 201
2 1
66 10 7 6 XDP_BPM_L<5> OBSFN_A0 4 3 OBSFN_C0 NB_CFG<8> 6 7 16 NB CFG[8]

OUT IN
66 10 7 6 XDP_BPM_L<4> OBSFN_A1 6 5 OBSFN_C1 SMC_WAKE_SCI_L 6 7 25 41 SB GPIO[8]
IN IN
8 7
66 10 7 6 XDP_BPM_L<3> OBSDATA_A0 10 9 OBSDATA_C0 EXTAUSB_OC_L 6 7 9 24 39 SB OC[0]#

BI IN
66 10 7 6 XDP_BPM_L<2> OBSDATA_A1 12 11 OBSDATA_C1 SB_GPIO40 6 7 24 SB OC[1]#
IN IN
14 13
66 10 7 6 XDP_BPM_L<1> OBSDATA_A2 16 15 OBSDATA_C2 USB_EXTD_OC_L 6 7 24 SB OC[2]#

IN IN
66 10 7 6 XDP_BPM_L<0> OBSDATA_A3 18 17 OBSDATA_C3 WOW_EN 6 7 24 36 SB OC[3]#
IN IN
20 19
C NB CFG[0] 66 30 16 7 6 BI NB_BSEL<0> (OBSDATA_A0) 22 21 (OBSDATA_A2) NB_BSEL<2> IN 6 7 16 30 66 NB CFG[2]
C
NB CFG[1] 66 30 16 7 6 NB_BSEL<1> (OBSDATA_A1) 24 23 (OBSDATA_A3) NB_CFG<3> 6 7 16 NB CFG[3]
IN IN
26 25
NB CFG[4] 16 7 6 NB_CFG<4> OBSDATA_B0 28 27 OBSDATA_D0 PM_LATRIGGER_L 6 7 24 SB OC[4]#

BI IN
NB CFG[5] 16 7 6 NB_CFG<5> OBSDATA_B1 30 29 OBSDATA_D1 EXTGPU_LVDS_EN 6 7 24 SB OC[5]#
IN IN
32 31
NB CFG[6] 16 7 6 NB_CFG<6> OBSDATA_B2 34 33 OBSDATA_D2 SB_GPIO30 6 7 24 SB OC[6]#

IN IN
XDP 36 35
NB CFG[7] 16 7 6 IN NB_CFG<7> OBSDATA_B3 OBSDATA_D3 EXTBUSB_OC_L IN 6 7 9 24 SB OC[7]#
R1399 38 37
1K 40 39
66 23 10 6 CPU_PWRGD 1 2 7 6 XDP_PWRGD PWRGD/HOOK0 ITPCLK/HOOK4 XDP_CLK_P 6 7 29 30 66 71
IN IN
7 42 41 XDP
5% 6 XDP_OBS20 HOOK1 ITPCLK#/HOOK5 XDP_CLK_N IN 6 7 29 30 66 71
1/20W
MF VCC_OBS_AB 44 43 (VCC_OBS_CD) R1303
201
46 45 1K
7 TP_XDP_HOOK2 HOOK2 RESET#/HOOK6 66 7 6 XDP_CPURST_L 1 2 FSB_CPURST_L 6 10 14 66
IN
7 TP_XDP_HOOK3 HOOK3 48 47 DBR#/HOOK7 XDP_DBRESET_L 6 7 10 28 5%
OUT 1/20W
50 49 MF
201
15 7 6 LOCAL_CTRL_DATA SDA 52 51 TDO XDP_TDO 6 7 10 66
BI IN
15 7 6 LOCAL_CTRL_CLK SCL 54 53 TRSTn XDP_TRST_L 6 7 10 66
BI OUT
TCK1 NC 56 55 TDI XDP_TDI OUT 6 7 10 66
66 10 7 6 XDP_TCK TCK0 58 57 TMS XDP_TMS 6 7 10 66

OUT OUT
60 59 XDP_PRESENT#
XDP XDP
C1300 1 1
C1301
0.1UF 998-1571 0.1UF
10% 10%
6.3V 6.3V
X5R 2 2 X5R
201 201
B B
Direction of XDP module to edge of board

Please avoid any obstructions
eXtended Debug Port (XDP)

A SYNC_MASTER=M75

A
D 051-7230 B.0.0

NONE 13 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
CRESTLINE_USFF
66 10 BI FSB_D_L<0> H6 H_D0* FCBGA H_A3* C15 FSB_A_L<3> BI 10 66
66 10 FSB_D_L<1> H2 H_D1* (1 OF 10) H_A4* G17 FSB_A_L<4> 10 66
D
BI BI
D
HOST
66 10 BI FSB_D_L<2> F4 H_D2* H_A5* H14 FSB_A_L<5> BI 10 66
66 10 BI FSB_D_L<3> K2 H_D3* H_A6* F12 FSB_A_L<6> BI 10 66
66 10 BI FSB_D_L<4> P6 H_D4* H_A7* B16 FSB_A_L<7> BI 10 66
66 10 BI FSB_D_L<5> H4 H_D5* H_A8* B18 FSB_A_L<8> BI 10 66
66 10 BI FSB_D_L<6> M2 H_D6* H_A9* D14 FSB_A_L<9> BI 10 66
66 10 BI FSB_D_L<7> N7 H_D7* H_A10* D18 FSB_A_L<10> BI 10 66
66 10 BI FSB_D_L<8> N9 H_D8* H_A11* L15 FSB_A_L<11> BI 10 66
66 10 BI FSB_D_L<9> G3 H_D9* H_A12* C17 FSB_A_L<12> BI 10 66
66 10 BI FSB_D_L<10> L3 H_D10* H_A13* D16 FSB_A_L<13> BI 10 66
66 10 BI FSB_D_L<11> M4 H_D11* H_A14* F16 FSB_A_L<14> BI 10 66
66 10 BI FSB_D_L<12> K10 H_D12* H_A15* A17 FSB_A_L<15> BI 10 66
66 10 BI FSB_D_L<13> N11 H_D13* H_A16* F14 FSB_A_L<16> BI 10 66
66 10 BI FSB_D_L<14> K4 H_D14* H_A17* K20 FSB_A_L<17> BI 10 66
66 10 BI FSB_D_L<15> J3 H_D15* H_A18* B20 FSB_A_L<18> BI 10 66
66 10 BI FSB_D_L<16> R3 H_D16* H_A19* F18 FSB_A_L<19> BI 10 66
66 10 BI FSB_D_L<17> R11 H_D17* H_A20* F22 FSB_A_L<20> BI 10 66
66 10 BI FSB_D_L<18> U3 H_D18* H_A21* G19 FSB_A_L<21> BI 10 66
66 10 BI FSB_D_L<19> T10 H_D19* H_A22* K22 FSB_A_L<22> BI 10 66
66 10 BI FSB_D_L<20> T6 H_D20* H_A23* D20 FSB_A_L<23> BI 10 66
66 10 BI FSB_D_L<21> T2 H_D21* H_A24* J17 FSB_A_L<24> BI 10 66
66 10 BI FSB_D_L<22> R9 H_D22* H_A25* K18 FSB_A_L<25> BI 10 66
66 10 BI FSB_D_L<23> P4 H_D23* H_A26* L17 FSB_A_L<26> BI 10 66
66 10 BI FSB_D_L<24> V10 H_D24* H_A27* J19 FSB_A_L<27> BI 10 66
66 10 BI FSB_D_L<25> T4 H_D25* H_A28* C21 FSB_A_L<28> BI 10 66
66 10 BI FSB_D_L<26> W9 H_D26* H_A29* D22 FSB_A_L<29> BI 10 66
66 10 BI FSB_D_L<27> N1 H_D27* H_A30* C19 FSB_A_L<30> BI 10 66
C 66 10
66 10
BI
BI
FSB_D_L<28>
FSB_D_L<29>
V2
P2
H_D28*
H_D29*
H_A31*
H_A32*
A21
L21
FSB_A_L<31>
FSB_A_L<32>
BI
BI
10 66
10 66
C
66 10 BI FSB_D_L<30> U11 H_D30* H_A33* J21 FSB_A_L<33> BI 10 66
66 10 BI FSB_D_L<31> N3 H_D31* H_A34* B22 FSB_A_L<34> BI 10 66
66 10 BI FSB_D_L<32> Y2 H_D32* H_A35* G21 FSB_A_L<35> BI 10 66
66 10 BI FSB_D_L<33> AC7 H_D33*

66 10 BI FSB_D_L<34> W3 H_D34* H_ADS* F10 FSB_ADS_L BI 10 66
66 10 BI FSB_D_L<35> W7 H_D35* H_ADSTB0* G15 FSB_ADSTB_L<0> BI 10 66
66 10 BI FSB_D_L<36> Y6 H_D36* H_ADSTB1* F20 FSB_ADSTB_L<1> BI 10 66
66 10 BI FSB_D_L<37> AB10 H_D37* H_BNR* B8 FSB_BNR_L BI 10 66
66 10 BI FSB_D_L<38> AB2 H_D38* H_BPRI* F8 FSB_BPRI_L OUT 10 66
66 10 BI FSB_D_L<39> W11 H_D39* H_BREQ* C11 FSB_BREQ0_L BI 10 66
66 10 BI FSB_D_L<40> V4 H_D40* H_DEFER* B10 FSB_DEFER_L OUT 10 66
66 10 BI FSB_D_L<41> Y10 H_D41* H_DBSY* D6 FSB_DBSY_L BI 10 66
66 10 BI FSB_D_L<42> Y4 H_D42* HPLL_CLK AG7 FSB_CLK_NB_P IN 6 29 30 71
66 10 BI FSB_D_L<43> AA3 H_D43* HPLL_CLK* AJ7 FSB_CLK_NB_N IN 6 29 30 71
66 10 BI FSB_D_L<44> AC11 H_D44* H_DPWR* H10 FSB_DPWR_L BI 10 66
66 10 BI FSB_D_L<45> AC9 H_D45* H_DRDY* E3 FSB_DRDY_L BI 10 66
66 10 BI FSB_D_L<46> AB4 H_D46* H_HIT* H8 FSB_HIT_L BI 10 66
66 10 BI FSB_D_L<47> AA1 H_D47* H_HITM* D8 FSB_HITM_L BI 10 66
66 10 BI FSB_D_L<48> AF2 H_D48* H_LOCK* G11 FSB_LOCK_L IN 10 66
66 10 BI FSB_D_L<49> AE3 H_D49* H_TRDY* B12 FSB_TRDY_L OUT 10 66
66 10 BI FSB_D_L<50> AD10 H_D50*

66 10 BI FSB_D_L<51> AH6 H_D51*
66 10 BI FSB_D_L<52> AD2 H_D52*
66 10 BI FSB_D_L<53> AF10 H_D53*
H_DINV0* L5 FSB_DINV_L<0> BI 10 66
66 10 FSB_D_L<54> AE11 H_D54*
B 66 10
BI
BI FSB_D_L<55> AD4 H_D55*
H_DINV1*
H_DINV2*
V6
AB6
FSB_DINV_L<1>
FSB_DINV_L<2>
BI
BI
10 66
10 66
B
66 10 BI FSB_D_L<56> AG1 H_D56*
H_DINV3* AD6 FSB_DINV_L<3> BI 10 66
66 10 BI FSB_D_L<57> AC3 H_D57*
66 10 BI FSB_D_L<58> AG3 H_D58*
23 21 19 18 13 12 11 10 8 7 6 PP1V05_S0 H_DSTBN0* L9 FSB_DSTB_L_N<0> BI 10 66
72 54 42 30 27 26 66 10 BI FSB_D_L<59> AH4 H_D59*
H_DSTBN1* U7 FSB_DSTB_L_N<1> BI 10 66
66 10 BI FSB_D_L<60> AH2 H_D60*
H_DSTBN2* AA11 FSB_DSTB_L_N<2> BI 10 66
66 10 BI FSB_D_L<61> AF6 H_D61*
1 1 1 AE9 FSB_DSTB_L_N<3>
R1421 R1420 R1410 FSB_D_L<62> AJ3 H_DSTBN3* BI 10 66
54.9 54.9 221

66 10 BI H_D62*
1% 1% 1% 66 10 BI FSB_D_L<63> AF4 H_D63* H_DSTBP0* K8 FSB_DSTB_L_P<0> BI 10 66
1/20W 1/20W 1/20W
MF MF MF H_DSTBP1* U9 FSB_DSTB_L_P<1> BI 10 66
201 201 201
2 2 2 AA9 FSB_DSTB_L_P<2>
H_DSTBP2* BI 10 66
6 NB_FSB_SWING C5 H_SWING H_DSTBP3* AE7 FSB_DSTB_L_P<3> BI 10 66
6 NB_FSB_RCOMP E5 H_RCOMP
H_REQ0* G13 FSB_REQ_L<0> BI 10 66
6 NB_FSB_SCOMP J5 H_SCOMP H_REQ1* D12 FSB_REQ_L<1> BI 10 66
6 NB_FSB_SCOMP_L F6 H_SCOMP* H_REQ2* B14 FSB_REQ_L<2> BI 10 66
1 H_REQ3* A13 FSB_REQ_L<3> BI 10 66

R1425 66 13 10 6 FSB_CPURST_L C9 H_CPURST* H_REQ4* C13 FSB_REQ_L<4> 10 66
1K OUT BI
1% 66 10 OUT FSB_CPUSLP_L J13 H_CPUSLP*
1/20W
MF H_RS0* L19 FSB_RS_L<0> OUT 10 66
201
2 A9 FSB_RS_L<1>
H_RS1* OUT 10 66
6 NB_FSB_VREF K14 H_AVREF H_RS2* C7 FSB_RS_L<2> OUT 10 66
L13 H_DVREF
1 1 1
R1426 1 C1425 R1415 R1411 1 C1410 NB CPU Interface
2K 24.9 100
1%
0.1UF 1% 1%
0.1UF
10% 10%
A 1/20W
MF
201
2
2
6.3V
X5R
201
1/20W
MF
201
2
1/20W
MF
201
2
2
6.3V
X5R
201

SYNC_DATE=(MASTER)
A
D 051-7230 B.0.0

NONE 14 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP1V05_S0_NB_VCCPEG 6 19 21 72
1
R1510
OMIT 24.9
1%
1/20W
U1400 MF
2 201
LVDS Disable CRESTLINE_USFF
64 9 6 LCDBKLT_PWM_UNBUF C43 L_BKLT_CTRL FCBGA PEG_COMPI T44 6 PEG_COMP
D Can leave all signals NC if LVDS is not implemented. 64 9 6

OUT
OUT LCDBKLT_PWREN G41 L_BKLT_EN (3 OF 10) PEG_COMPO P44 SDVO Alternate Function D
Tie VCC_TX_LVDS and VCCA_LVDS to GND. 13 7 6 BI LOCAL_CTRL_CLK B40 L_CTRL_CLK
PEG_RX0* G55 NC_PEG_D2R_N0 IN 9 SDVO_TVCLKIN#
13 7 6 BI LOCAL_CTRL_DATA D42 L_CTRL_DATA
If SDVO is used, VCCD_LVDS must remain powered with proper PEG_RX1* J55 PEG_D2R_N<1> IN 6 61 67 SDVO_INT#
60 7 6 BI LVDS_DDC_CLK C39 L_DDC_CLK
decoupling. Otherwise, tie VCCD_LVDS to GND also. PEG_RX2* R47 NC_PEG_D2R_N2 IN 9 SDVO_FLDSTALL#
60 7 6 BI LVDS_DDC_DATA D38 L_DDC_DATA
PEG_RX3* U47 NC_PEG_D2R_N3 IN 9
60 6 OUT LVDS_VDD_EN G43 L_VDD_EN
PEG_RX4* P50 NC_PEG_D2R_N4 IN 9
PEG_RX5* V46 NC_PEG_D2R_N5 IN 9

67 60 6 BI LVDS_IBG L49 LVDS_IBG
PEG_RX6* Y50 NC_PEG_D2R_N6 IN 9
7 NC_LVDS_VBG K50 LVDS_VBG
PEG_RX7* AB46 NC_PEG_D2R_N7 IN 9
TP_LVDS_VREFH L43 LVDS_VREFH
PEG_RX8* Y52 NC_PEG_D2R_N8 IN 9
TP_LVDS_VREFL K42 LVDS_VREFL
PEG_RX9* AB50 NC_PEG_D2R_N9 IN 9
67 60 6 OUT LVDS_A_CLK_N A49 LVDSA_CLK*
PEG_RX10* R53 NC_PEG_D2R_N10 IN 9
67 60 6 OUT LVDS_A_CLK_P C49 LVDSA_CLK
PEG_RX11* AE55 NC_PEG_D2R_N11 IN 9
67 9 OUT NC_LVDS_B_CLK_N D46 LVDSB_CLK*
LVDS
PEG_RX12* AF50 NC_PEG_D2R_N12 IN 9
67 9 OUT NC_LVDS_B_CLK_P B46 LVDSB_CLK
PEG_RX13* U55 NC_PEG_D2R_N13 IN 9
PEG_RX14* AC55 NC_PEG_D2R_N14 IN 9

67 60 7 OUT LVDS_A_DATA_N<0> J41 LVDSA_DATA0*
PEG_RX15* AD50 NC_PEG_D2R_N15 IN 9
67 60 7 OUT LVDS_A_DATA_N<1> C51 LVDSA_DATA1*
67 60 7 6 OUT LVDS_A_DATA_N<2> F50 LVDSA_DATA2* PEG_RX0 G53 NC_PEG_D2R_P0 IN 9 SDVO_TVCLKIN
TP_LVDS_A_DATA_N<3> E53 LVDSA_DATA3* PEG_RX1 J53 PEG_D2R_P<1> IN 6 61 67 SDVO_INT
PEG_RX2 T48 NC_PEG_D2R_P2 IN 9 SDVO_FLDSTALL
67 60 7 OUT LVDS_A_DATA_P<0> H42 LVDSA_DATA0
PEG_RX3 U45 NC_PEG_D2R_P3 IN 9
67 60 7 OUT LVDS_A_DATA_P<1> B50 LVDSA_DATA1
PEG_RX4 P52 NC_PEG_D2R_P4 IN 9
67 60 7 6 OUT LVDS_A_DATA_P<2> E49 LVDSA_DATA2
V48 NC_PEG_D2R_P5
PCI-EXPRESS GRAPHICS
PEG_RX5 IN 9
TP_LVDS_A_DATA_P<3> D52 LVDSA_DATA3
PEG_RX6 AA51 NC_PEG_D2R_P6 IN 9
PEG_RX7 AB48 NC_PEG_D2R_P7 IN 9

9 OUT NC_LVDS_B_DATA_N0 H44 LVDSB_DATA0*
C 9
9
OUT NC_LVDS_B_DATA_N1
NC_LVDS_B_DATA_N2
G47
A47
LVDSB_DATA1*
LVDSB_DATA2*
PEG_RX8
PEG_RX9
AA55
AB52
NC_PEG_D2R_P8
NC_PEG_D2R_P9
IN
IN
9
9
C
OUT
PEG_RX10 R55 NC_PEG_D2R_P10 IN 9
TP_LVDS_B_DATA_N<3> G45 LVDSB_DATA3*
PEG_RX11 AD52 NC_PEG_D2R_P11 IN 9
9 OUT NC_LVDS_B_DATA_P0 H46 LVDSB_DATA0 PEG_RX12 AF52 NC_PEG_D2R_P12 IN 9
9 OUT NC_LVDS_B_DATA_P1 E47 LVDSB_DATA1 PEG_RX13 T52 NC_PEG_D2R_P13 IN 9
9 OUT NC_LVDS_B_DATA_P2 C47 LVDSB_DATA2 PEG_RX14 AC53 NC_PEG_D2R_P14 IN 9
TP_LVDS_B_DATA_P<3> F46 LVDSB_DATA3 PEG_RX15 AE51 NC_PEG_D2R_P15 IN 9
TV-Out Signal Usage: PEG_TX0* F52 PEG_R2D_C_N<0> OUT 6 61 67 SDVOB_RED#

PEG_TX1* K54 PEG_R2D_C_N<1> OUT 6 61 67 SDVOB_GREEN#
Composite: DACA only 67 63 6 OUT TV_A_DAC B32 TVA_DAC
PEG_TX2* N47 PEG_R2D_C_N<2> OUT 6 61 67 SDVOB_BLUE#
S-Video: DACB & DACC only 67 63 6 OUT TV_B_DAC D32 TVB_DAC
PEG_TX3* V50 PEG_R2D_C_N<3> OUT 6 61 67 SDVOB_CLKN
Component: DACA, DACB & DACC 67 63 6 OUT TV_C_DAC A33 TVC_DAC
PEG_TX4* T50 NC_PEG_R2D_C_N4 OUT 9 SDVOC_RED#
Unused DAC outputs must remain powered, but can PEG_TX5* L53 NC_PEG_R2D_C_N5 OUT 9 SDVOC_GREEN#
omit filtering components. Unused DAC outputs PEG_TX6* U53 NC_PEG_R2D_C_N6 OUT 9 SDVOC_BLUE#
TV
OUT GND B30 TVA_RTN
should connect to GND through 75-ohm resistors. PEG_TX7* N53 NC_PEG_R2D_C_N7 OUT 9 SDVOC_CLKN
OUT GND F32 TVB_RTN
PEG_TX8* M52 NC_PEG_R2D_C_N8 OUT 9
TV-Out Disable / CRT Enable OUT GND F30 TVC_RTN
PEG_TX9* AA47 NC_PEG_R2D_C_N9 OUT 9
Tie TVx_DAC and TVx_RTN to GND. Must power all PEG_TX10* AE53 NC_PEG_R2D_C_N10 OUT 9
TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can PEG_TX11* AG45 NC_PEG_R2D_C_N11 OUT 9
63 OUT TV_DCONSEL<0> K36 TV_DCONSEL0
share filtering with VCCA_CRT_DAC. PEG_TX12* AD48 NC_PEG_R2D_C_N12 OUT 9
63 6 OUT TV_DCONSEL<1> J35 TV_DCONSEL1
PEG_TX13* AG49 NC_PEG_R2D_C_N13 OUT 9
CRT Disable / TV-Out Enable PEG_TX14* W53 NC_PEG_R2D_C_N14 OUT 9
PEG_TX15* AA53 NC_PEG_R2D_C_N15 OUT 9

Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.
All CRT/TVDAC rails must be powered. All PEG_TX0 F54 PEG_R2D_C_P<0> OUT 6 61 67 SDVOB_RED
rails must be filtered except for VCCA_CRT. 67 63 6 CRT_BLUE C35 CRT_BLUE PEG_TX1 K52 PEG_R2D_C_P<1> 6 61 67 SDVOB_GREEN
B OUT
OUT GND D34 CRT_BLUE* PEG_TX2 M48 PEG_R2D_C_P<2>
OUT
OUT 6 61 67 SDVOB_BLUE B
CRT & TV-Out Disable 67 63 6 OUT CRT_GREEN F34 CRT_GREEN PEG_TX3 V52 PEG_R2D_C_P<3> OUT 6 61 67 SDVOB_CLKP
OUT GND G33 CRT_GREEN* PEG_TX4 U51 NC_PEG_R2D_C_P4 OUT 9 SDVOC_RED
Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,
67 63 6 OUT CRT_RED B34 CRT_RED PEG_TX5 L55 NC_PEG_R2D_C_P5 OUT 9 SDVOC_GREEN
VSYNC and CRT_TVO_IREF to GND.
OUT GND C33 CRT_RED* PEG_TX6 V54 NC_PEG_R2D_C_P6 OUT 9 SDVOC_BLUE
VGA
Can tie the following rails to GND:
PEG_TX7 P54 NC_PEG_R2D_C_P7 OUT 9 SDVOC_CLKP
VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,
PEG_TX8 N55 NC_PEG_R2D_C_P8 OUT 9
VCCD_CRT, VCCD_QDAC and VCC_SYNC.
7 BI NC_CRT_DDC_CLK F36 CRT_DDC_CLK PEG_TX9 AA45 NC_PEG_R2D_C_P9 OUT 9
NOTE: Must keep VDDC_TVDAC powered 7 BI NC_CRT_DDC_DATA G35 CRT_DDC_DATA PEG_TX10 AF54 NC_PEG_R2D_C_P10 OUT 9
and filtered at all times! 67 63 6 OUT CRT_HSYNC_R A35 CRT_HSYNC PEG_TX11 AF46 NC_PEG_R2D_C_P11 OUT 9
67 63 6 OUT CRT_TVO_IREF D30 CRT_TVO_IREF PEG_TX12 AE47 NC_PEG_R2D_C_P12 OUT 9
67 63 6 OUT CRT_VSYNC_R J37 CRT_VSYNC PEG_TX13 AF48 NC_PEG_R2D_C_P13 OUT 9
PEG_TX14 W55 NC_PEG_R2D_C_P14 OUT 9
Internal Graphics Disable PEG_TX15 AB54 NC_PEG_R2D_C_P15 OUT 9
Follow instructions for LVDS and CRT & TV-Out Disable above.
Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and
TV_DCONSELx to GND.
Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.
Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).
Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).
Tie VCC_AXG and VCC_AXG_NCTF to GND.
Leave GFX_VID<3..0> and GFX_VR_EN as NC.
NB PEG / Video Interfaces
A SYNC_MASTER=M70

A
D 051-7230 B.0.0

NONE 15 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NB_CFG<3> RESERVED
OMIT
NB_CFG<4> RESERVED
RSVD bit ordering based on CRB numbering U1400
NB CFG<5> chooses DMI x4 w/ TP CRESTLINE_USFF
NB_CFG<5> High = DMIx4
TP_NB_RSVD<42> MEM_CLK_P<0>
A39 FCBGA SM_CK0 BC37 OUT 31 33 68
DMI x2 Select Low = DMIx2 7 NC_NB_RSVD_8 AG11 (2 OF 10) SM_CK1 BC25 MEM_CLK_P<1> OUT 31 33 68
7 NC_NB_RSVD_7 AG9 SM_CK3 BB36 MEM_CLK_P<3> OUT 32 33 68
NB_CFG<6> RESERVED NB_CFG<9>

7 NC_NB_RSVD_5 AH10 SM_CK4 BB24 MEM_CLK_P<4> OUT 32 33 68
6 16
7 NC_NB_RSVD_6 AJ11
NBCFG_PEG_REVERSE SM_CK0* BA37 MEM_CLK_N<0> 31 33 68
D NB_CFG<7> RESERVED 1
R1659
TP_NB_RSVD<12>
TP_NB_RSVD<11>
AJ43
AL43
SM_CK1* BC23 MEM_CLK_N<1>
OUT
OUT 31 33 68 D
4.02K SM_CK3* BB34 MEM_CLK_N<3> OUT 32 33 68
1% TP_NB_RSVD<13> AN43
1/20W SM_CK4* BB26 MEM_CLK_N<4> OUT 32 33 68
NB_CFG<8> RESERVED MF TP_NB_RSVD<10> AR43
201
2 TP_NB_RSVD<45> B36 SM_CKE0 BE33 MEM_CKE<0> 31 33 68
OUT
TP_NB_RSVD<41> B38 SM_CKE1 BE35 MEM_CKE<1> OUT 31 33 68
NB_CFG<9> High = Normal
DDR MUXING
7 NC_NB_RSVD_21 B55 SM_CKE3 BF40 MEM_CKE<3> OUT 32 33 68
PCIe Graphics
Low = Reversed 7 NC_NB_RSVD_28 BA33 SM_CKE4 BE39 MEM_CKE<4> OUT 32 33 68
Lane Reversal
NB_CFG<16> 6 16 7 NC_NB_RSVD_35 BB22
SM_CS0* BA23 MEM_CS_L<0> OUT 35 34 32 31 21 18 8 7 6 PP1V8_S3
NBCFG_DYN_ODT_DISABLE 7 NC_NB_RSVD_29 BC33 72 68 55 51
NB_CFG<10> RESERVED 1 SM_CS1* BH16 MEM_CS_L<1> OUT 31 33 68
R1666 7 NC_NB_RSVD_30 BF22
SM_CS2* BE15 MEM_CS_L<2> OUT 32 33 68
4.02K 7 NC_NB_RSVD_31 BE23
1% SM_CS3* BH14 MEM_CS_L<3> OUT 32 33 68 R1610
1 1
R1620
NB_CFG<11> RESERVED 1/20W 7 NC_NB_RSVD_24 BH18
MF 20 1K
2 201 7 NC_NB_RSVD_36 BE27 RSVD SM_ODT0 BJ15 MEM_ODT<0> OUT 6 31 33 68 1% 1%
1/20W 1/20W
7 NC_NB_RSVD_22 BJ17 SM_ODT1 BF20 MEM_ODT<1> OUT 6 31 33 68 MF MF
NB_CFG<12> See Below NC_NB_RSVD_25 BK16 BE13 MEM_ODT<2>
201
2 2
201
7 SM_ODT2 OUT 6 32 33 68
7 NC_NB_RSVD_27 BK18 SM_ODT3 BH12 MEM_ODT<3> OUT 6 32 33 68
NB_CFG<13> See Below 53 60 63 64

TP_NB_RSVD<34> BK32
PP3V3_A_S0 6 7 8 13 16 19 21 22 23 24 25 SM_RCOMP BL13 6 MEM_RCOMP
1 OMIT
26 27 28 29 30 42 44 46 51 52 7 NC_NB_RSVD_26 BL17 C1623 1
C1622
NBCFG_DMI_REVERSE SM_RCOMP* BK14 6 MEM_RCOMP_L
NC_NB_RSVD_23 BL19 0.01UF 2.2UF 1
NB_CFG<14> RESERVED 1 7
10% 20% R1622
R1669 TP_NB_RSVD<43> C37 SM_RCOMP_VOH BK36 6 MEM_RCOMP_VOH 10V
2 2
6.3V
3.01K
X5R CERM
4.02K 201 402-LF
1%
1% TP_NB_RSVD<9> D10 SM_RCOMP_VOL BL37 6 MEM_RCOMP_VOL 1/20W
1/20W MF
NB_CFG<15> RESERVED MF TP_NB_RSVD<44> D36 201
2 201 SM_VREF0 AM54 PP0V9_S3M_MEM_NBVREFA IN 8 21 68

2
7 NC_NB_RSVD_4 G51
SM_VREF1 AT12 PP0V9_S3M_MEM_NBVREFB IN 8 21 68
NB_CFG<19> 6 16 TP_NB_RSVD<20> G9
NB_CFG<16> High = Enabled
NC_NB_RSVD_3
7 H52 1 1
FSB Dynamic C1615 C1616
Low = Disabled 7 NC_NB_RSVD_14 J25 0.1UF 0.1UF
C ODT
PP3V3_A_S0
NBCFG_SDVO_AND_PCIE
53 60 63 64
6 7 8 13 16 19 21 22 23 24 25
26 27 28 29 30 42 44 46 51 52
7
7
NC_NB_RSVD_1
NC_NB_RSVD_2
M46
N45
DPLL_REF_CLK
DPLL_REF_CLK*
C45
B44
NB_CLK96M_DOT_P
NB_CLK96M_DOT_N
IN 6 9 29 30 71
6 9 29 30 71
10%
6.3V
X5R
2 2
10%
6.3V
X5R
R1611
20
1%
1
C1625
0.01UF
1 1
OMIT
C1624
2.2UF
1
R1624
1K
1%
C
IN
NB_CFG<17> RESERVED 1
201 201
1/20W
10%
10V
20%
6.3V
1/20W
R1670 DPLL_REF_SSCLK H50 NB_CLK100M_DPLLSS_P IN 6 9 29 30 71 MF X5R
2 2
CERM
MF
201 201
2 201 402-LF 2
4.02K DPLL_REF_SSCLK* G49 NB_CLK100M_DPLLSS_N IN 6 9 29 30 71
1%
NB_CFG<18> RESERVED
CLK
1/20W
MF PEG_CLK N51 NB_CLK100M_PCIE_P IN 6 29 30 71
201
2 PEG_CLK* M50 NB_CLK100M_PCIE_N 6 29 30 71
IN
NB_CFG<19> High = Reversed NB_CFG<20> 6 16 Clk used for PEG and DMI
DMI Lane
Low = Normal
Reversal
66 30 13 7 6 IN NB_BSEL<0> H28 CFG0 DMI_RXN0 AL45 DMI_S2N_N<0> IN 6 24 67
66 30 13 7 6 IN NB_BSEL<1> G25 CFG1 DMI_RXN1 AK54 DMI_S2N_N<1> IN 6 24 67

NB_CFG<20> High = Both active
66 30 13 7 6 IN NB_BSEL<2> C25 CFG2 DMI_RXN2 AJ55 DMI_S2N_N<2> IN 6 24 67
Concurrent Low = Only SDVO
13 7 6 OUT NB_CFG<3> K24 CFG3 IPU DMI_RXN3 AH52 DMI_S2N_N<3> IN 6 24 67
SDVO/PCIe x1 or PCIe x16 NB CFG<8:0> used for debug access
13 7 6 BI NB_CFG<4> B28 CFG4 IPU
DMI_RXP0 AM46 DMI_S2N_P<0> IN 6 24 67
13 7 6 BI NB_CFG<5> G27 CFG5 IPU
NB_CFG<13:12> NB_CFG<6>
DMI_RXP1 AK52 DMI_S2N_P<1> IN 6 24 67
13 7 6 OUT B26 CFG6 IPU
DMI_RXP2 AJ53 DMI_S2N_P<2> IN 6 24 67
NB_CFG<7> D26 CFG7
DMI
00 = RESERVED 13 7 6 OUT IPU
DMI_RXP3 AH50 DMI_S2N_P<3>
CFG
IN 6 24 67
01 = XOR Mode Enabled 13 7 6 OUT NB_CFG<8> D24 CFG8 IPU
10 = All-Z Mode Enabled 16 6 NB_CFG<9> F26 CFG9 IPU DMI_TXN0 AH48 DMI_N2S_N<0> OUT 6 24 67
11 = Normal Operation 7 NC_NB_CFG_10 A25 CFG10 IPU DMI_TXN1 AK48 DMI_N2S_N<1> OUT 6 24 67
7 NC_NB_CFG_11 L23 CFG11 IPU DMI_TXN2 AG55 DMI_N2S_N<2> OUT 6 24 67
TP_NB_CFG<12> D28 CFG12 IPU DMI_TXN3 AL53 DMI_N2S_N<3> OUT 6 24 67
NB CFG<13:12> require ICT access TP_NB_CFG<13> F24 CFG13 IPU

DMI_TXP0 AJ47 DMI_N2S_P<0> OUT 6 24 67
7 NC_NB_CFG_14 C29 CFG14 IPU
DMI_TXP1 AK50 DMI_N2S_P<1> OUT 6 24 67
7 NC_NB_CFG_15 C27 CFG15 IPU
64 63 60 53 DMI_TXP2 AG53 DMI_N2S_P<2> OUT 6 24 67
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0 16 6 NB_CFG<16> A29 CFG16 IPU
52 51 46 44 42 30 29 28 27 26 DMI_TXP3 AL55 DMI_N2S_P<3> 6 24 67
B 7 NC_NB_CFG_17
TP_NB_CFG<18>
J27
G31
CFG17 IPU
CFG18 IPD
OUT
B
GRAPHICS VID
1 1 NB_CFG<19> K30
R1630 R1631 16 6 CFG19 IPD
10K 10K 16 6 NB_CFG<20> L37 CFG20 IPD
5% 5% GND OUT
1/20W 1/20W
MF MF 25 6 OUT PM_BMBUSY_L F44 PM_BM_BUSY*
201 201 GFX_VID0 G37 GFX_VID<0> OUT 6 22 53
2 2 CPU_DPRSTP_L C41
66 52 23 10 6 IN PM_DPRSTP*
GFX_VID1 A45 GFX_VID<1> OUT 6 22 53
41 6 IN PM_EXTTS_L<0> L39 PM_EXT_TS0*
B42 GFX_VID<2>
PM
GFX_VID2 OUT 6 22 53
41 6 IN PM_EXTTS_L<1> J39 PM_EXT_TS1*
GFX_VID3 D44 GFX_VID<3> OUT 6 22 53
52 28 16 9 6 IN VR_PWRGOOD_DELAY AT50 PWROK
GFX_VR_EN F42 GFX_VR_EN OUT 6 9 53
28 6 IN NB_RESET_L BB20 RSTIN*
66 42 23 10 6 OUT PM_THRMTRIP_L F28 THERMTRIP*
66 52 25 6 IN PM_DPRSLPVR F40 DPRSLPVR
PP1V25_S0 6 7 8 18 19 21 26 27 51 57 72
7 NC_NB_NC_14 A52
NC_NB_NC_13 1
7 A54 R1640
CL_CLK BF52 CLINK_NB_CLK BI 6 25 70
7 NC_NB_NC_12 B54 1K
ME CL_DATA BE53 CLINK_NB_DATA BI 6 25 70 1%
7 NC_NB_NC_10 BH1 1/20W
CL_PWROK AP50 VR_PWRGOOD_DELAY IN 6 9 16 28 52 MF NOTE: GMCH CL_PWROK input must be PWRGD signal for
7 NC_NB_NC_2 BH55 2
201
CL_RST* BH52 CLINK_NB_RESET_L OUT 6 25 70 PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,
7 NC_NB_NC_9 BK1
CL_VREF BF54 70 6 NB_CLINK_VREF PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.
7 NC_NB_NC_8 BK2 NC
NC
If ME/AMT is not used, short CL_PWROK to PWROK.

7 NC_NB_NC_4 BK54 1
7 NC_NB_NC_1 BK55 C1640 1 R1641
392
7 NC_NB_NC_7 BL2 SDVO_CTRL_CLK K38 SDVO_CTRLCLK 6 61
0.1UF 1%
BI 10%
1/20W
6.3V
7 NC_NB_NC_6 BL4 SDVO_CTRL_DATA K40 SDVO_CTRLDATA BI 6 61 X5R 2 MF
201
7 NC_NB_NC_5 BL52 CLKREQ* G39 NB_CLKREQ_L OUT 6 29
201 2
NB Misc Interfaces
MISC
7 NC_NB_NC_3 BL54 ICH_SYNC* D40 NB_SB_SYNC_L OUT 6 25
A 7 NC_NB_NC_11 D55
TEST1 F38 6 NB_TEST1
SYNC_MASTER=M70

A
TEST2 K34 6 NB_TEST2
1 1
R1691 R1690 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
20K 0
5% 5% II NOT TO REPRODUCE OR COPY IT
1/20W 1/20W
MF MF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
201 201
2 2
D 051-7230 B.0.0

NONE 16 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D OMIT OMIT
D
U1400 U1400
68 31 BI MEM_A_DQ<0> AN49 SA_DQ0 CRESTLINE_USFF SA_BS0 BC21 MEM_A_BS<0> OUT 31 33 68 68 32 BI MEM_B_DQ<0> AT52 SB_DQ0 CRESTLINE_USFF SB_BS0 BB16 MEM_B_BS<0> OUT 32 33 68
FCBGA FCBGA
68 31 BI MEM_A_DQ<1> AL51 SA_DQ1 SA_BS1 BA21 MEM_A_BS<1> OUT 31 33 68 68 32 BI MEM_B_DQ<1> AN53 SB_DQ1 SB_BS1 BF16 MEM_B_BS<1> OUT 32 33 68
(4 OF 10) (5 OF 10)
68 31 BI MEM_A_DQ<2> AV50 SA_DQ2 SA_BS2 BF34 MEM_A_BS<2> OUT 31 33 68 68 32 BI MEM_B_DQ<2> AV52 SB_DQ2 SB_BS2 BH38 MEM_B_BS<2> OUT 32 33 68
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY B

68 31 BI MEM_A_DQ<3> AT46 SA_DQ3 68 32 BI MEM_B_DQ<3> AP54 SB_DQ3
SA_CAS* BE19 MEM_A_CAS_L OUT 31 33 68 SB_CAS* BJ13 MEM_B_CAS_L OUT 32 33 68
68 31 BI MEM_A_DQ<4> AM48 SA_DQ4 68 32 BI MEM_B_DQ<4> AP52 SB_DQ4
68 31 BI MEM_A_DQ<5> AM50 SA_DQ5 68 32 BI MEM_B_DQ<5> AN55 SB_DQ5
SA_DM0 AR49 MEM_A_DM<0> OUT 31 68 SB_DM0 AR55 MEM_B_DM<0> OUT 32 68
68 31 BI MEM_A_DQ<6> AU49 SA_DQ6 68 32 BI MEM_B_DQ<6> AU53 SB_DQ6
SA_DM1 BD50 MEM_A_DM<1> OUT 31 68 SB_DM1 BA53 MEM_B_DM<1> OUT 32 68
68 31 BI MEM_A_DQ<7> AU47 SA_DQ7 68 32 BI MEM_B_DQ<7> AV54 SB_DQ7
SA_DM2 BF48 MEM_A_DM<2> OUT 31 68 SB_DM2 BJ49 MEM_B_DM<2> OUT 32 68
68 31 BI MEM_A_DQ<8> AY50 SA_DQ8 68 32 BI MEM_B_DQ<8> BC53 SB_DQ8
SA_DM3 BF42 MEM_A_DM<3> OUT 31 68 SB_DM3 BJ43 MEM_B_DM<3> OUT 32 68
68 31 BI MEM_A_DQ<9> BB50 SA_DQ9 68 32 BI MEM_B_DQ<9> BC55 SB_DQ9
SA_DM4 BE11 MEM_A_DM<4> OUT 31 68 SB_DM4 BH8 MEM_B_DM<4> OUT 32 68
68 31 BI MEM_A_DQ<10> BC49 SA_DQ10 68 32 BI MEM_B_DQ<10> AY52 SB_DQ10
SA_DM5 BF4 MEM_A_DM<5> OUT 31 68 SB_DM5 BD4 MEM_B_DM<5> OUT 32 68
68 31 BI MEM_A_DQ<11> AW45 SA_DQ11 68 32 BI MEM_B_DQ<11> BD52 SB_DQ11
SA_DM6 AU7 MEM_A_DM<6> OUT 31 68 SB_DM6 AV4 MEM_B_DM<6> OUT 32 68
68 31 BI MEM_A_DQ<12> AW49 SA_DQ12 68 32 BI MEM_B_DQ<12> AW55 SB_DQ12
SA_DM7 AK6 MEM_A_DM<7> OUT 31 68 SB_DM7 AN3 MEM_B_DM<7> OUT 32 68
68 31 BI MEM_A_DQ<13> BA49 SA_DQ13 68 32 BI MEM_B_DQ<13> AW53 SB_DQ13
68 31 BI MEM_A_DQ<14> AU45 SA_DQ14 68 32 BI MEM_B_DQ<14> BD54 SB_DQ14
SA_DQS0 AR45 MEM_A_DQS_P<0> BI 31 68 SB_DQS0 AT54 MEM_B_DQS_P<0> BI 32 68
68 31 BI MEM_A_DQ<15> BB46 SA_DQ15 68 32 BI MEM_B_DQ<15> AY54 SB_DQ15
SA_DQS1 BA47 MEM_A_DQS_P<1> BI 31 68 SB_DQS1 BB52 MEM_B_DQS_P<1> BI 32 68
68 31 BI MEM_A_DQ<16> AV46 SA_DQ16 68 32 BI MEM_B_DQ<16> BK50 SB_DQ16
SA_DQS2 BE47 MEM_A_DQS_P<2> BI 31 68 SB_DQS2 BH48 MEM_B_DQS_P<2> BI 32 68
68 31 BI MEM_A_DQ<17> BF50 SA_DQ17 68 32 BI MEM_B_DQ<17> BL47 SB_DQ17
SA_DQS3 BC41 MEM_A_DQS_P<3> BI 31 68 SB_DQS3 BH42 MEM_B_DQS_P<3> BI 32 68
68 31 BI MEM_A_DQ<18> BA45 SA_DQ18 68 32 BI MEM_B_DQ<18> BJ47 SB_DQ18
SA_DQS4 BC13 MEM_A_DQS_P<4> BI 31 68 SB_DQS4 BL9 MEM_B_DQS_P<4> BI 32 68
68 31 BI MEM_A_DQ<19> BE45 SA_DQ19 68 32 BI MEM_B_DQ<19> BG51 SB_DQ19
SA_DQS5 BA7 MEM_A_DQS_P<5> BI 31 68 SB_DQS5 BE3 MEM_B_DQS_P<5> BI 32 68
68 31 BI MEM_A_DQ<20> BD48 SA_DQ20 68 32 BI MEM_B_DQ<20> BJ51 SB_DQ20
SA_DQS6 AU11 MEM_A_DQS_P<6> BI 31 68 SB_DQS6 AW1 MEM_B_DQS_P<6> BI 32 68
68 31 BI MEM_A_DQ<21> BE49 SA_DQ21 68 32 BI MEM_B_DQ<21> BK46 SB_DQ21
SA_DQS7 AL9 MEM_A_DQS_P<7> BI 31 68 SB_DQS7 AM2 MEM_B_DQS_P<7> BI 32 68
68 31 BI MEM_A_DQ<22> AY46 SA_DQ22 68 32 BI MEM_B_DQ<22> BH50 SB_DQ22
C 68 31
68 31
BI MEM_A_DQ<23>
MEM_A_DQ<24>
BF46
BF44
SA_DQ23
SA_DQ24
SA_DQS0*
SA_DQS1*
AR47
AW47
MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
BI
BI
31 68
31 68
68 32
68 32
BI MEM_B_DQ<23>
MEM_B_DQ<24>
BH46
BK44
SB_DQ23
SB_DQ24
SB_DQS0*
SB_DQS1*
AR53
BB54
MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
BI
BI
32 68
32 68
C
BI BI
SA_DQS2* BC47 MEM_A_DQS_N<2> BI 31 68 SB_DQS2* BK48 MEM_B_DQS_N<2> BI 32 68
68 31 BI MEM_A_DQ<25> BA43 SA_DQ25 68 32 BI MEM_B_DQ<25> BJ41 SB_DQ25
SA_DQS3* BE41 MEM_A_DQS_N<3> BI 31 68 SB_DQS3* BK42 MEM_B_DQS_N<3> BI 32 68
68 31 BI MEM_A_DQ<26> BA41 SA_DQ26 68 32 BI MEM_B_DQ<26> BH40 SB_DQ26
SA_DQS4* BA13 MEM_A_DQS_N<4> BI 31 68 SB_DQS4* BJ9 MEM_B_DQS_N<4> BI 32 68
68 31 BI MEM_A_DQ<27> BB44 SA_DQ27 68 32 BI MEM_B_DQ<27> BJ45 SB_DQ27
SA_DQS5* BC7 MEM_A_DQS_N<5> BI 31 68 SB_DQS5* BF2 MEM_B_DQS_N<5> BI 32 68
68 31 BI MEM_A_DQ<28> BC45 SA_DQ28 68 32 BI MEM_B_DQ<28> BH44 SB_DQ28
SA_DQS6* AU9 MEM_A_DQS_N<6> BI 31 68 SB_DQS6* AW3 MEM_B_DQS_N<6> BI 32 68
68 31 BI MEM_A_DQ<29> BE43 SA_DQ29 68 32 BI MEM_B_DQ<29> BL43 SB_DQ29
SA_DQS7* AL7 MEM_A_DQS_N<7> BI 31 68 SB_DQS7* AM4 MEM_B_DQS_N<7> BI 32 68
68 31 BI MEM_A_DQ<30> BC39 SA_DQ30 68 32 BI MEM_B_DQ<30> BK40 SB_DQ30
68 31 BI MEM_A_DQ<31> BB42 SA_DQ31 68 32 BI MEM_B_DQ<31> BL39 SB_DQ31
SA_MA0 BC19 MEM_A_A<0> OUT 31 33 68 SB_MA0 BA19 MEM_B_A<0> OUT 32 33 68
68 31 BI MEM_A_DQ<32> BA15 SA_DQ32 68 32 BI MEM_B_DQ<32> BK8 SB_DQ32
SA_MA1 BH22 MEM_A_A<1> OUT 31 33 68 SB_MA1 BE37 MEM_B_A<1> OUT 32 33 68
68 31 BI MEM_A_DQ<33> BB14 SA_DQ33 68 32 BI MEM_B_DQ<33> BJ7 SB_DQ33
SA_MA2 BL23 MEM_A_A<2> OUT 31 33 68 SB_MA2 BF36 MEM_B_A<2> OUT 32 33 68
68 31 BI MEM_A_DQ<34> BE7 SA_DQ34 68 32 BI MEM_B_DQ<34> BK6 SB_DQ34
SA_MA3 BF24 MEM_A_A<3> OUT 31 33 68 SB_MA3 BA17 MEM_B_A<3> OUT 32 33 68
68 31 BI MEM_A_DQ<35> BC9 SA_DQ35 68 32 BI MEM_B_DQ<35> BH6 SB_DQ35
SA_MA4 BH24 MEM_A_A<4> OUT 31 33 68 SB_MA4 BJ37 MEM_B_A<4> OUT 32 33 68
68 31 BI MEM_A_DQ<36> BC15 SA_DQ36 68 32 BI MEM_B_DQ<36> BJ11 SB_DQ36
SA_MA5 BK24 MEM_A_A<5> OUT 31 33 68 SB_MA5 BK38 MEM_B_A<5> OUT 32 33 68
68 31 BI MEM_A_DQ<37> BB12 SA_DQ37 68 32 BI MEM_B_DQ<37> BH10 SB_DQ37
SA_MA6 BJ25 MEM_A_A<6> OUT 31 33 68 SB_MA6 BC35 MEM_B_A<6> OUT 32 33 68
68 31 BI MEM_A_DQ<38> BC11 SA_DQ38 68 32 BI MEM_B_DQ<38> BK10 SB_DQ38
SA_MA7 BH26 MEM_A_A<7> OUT 31 33 68 SB_MA7 BF38 MEM_B_A<7> OUT 32 33 68
68 31 BI MEM_A_DQ<39> BF10 SA_DQ39 68 32 BI MEM_B_DQ<39> BK12 SB_DQ39
SA_MA8 BF32 MEM_A_A<8> OUT 31 33 68 SB_MA8 BA35 MEM_B_A<8> OUT 32 33 68
68 31 BI MEM_A_DQ<40> BB10 SA_DQ40 68 32 BI MEM_B_DQ<40> BH4 SB_DQ40
SA_MA9 BK26 MEM_A_A<9> OUT 31 33 68 SB_MA9 BH34 MEM_B_A<9> OUT 32 33 68
68 31 BI MEM_A_DQ<41> BA9 SA_DQ41 68 32 BI MEM_B_DQ<41> BB4 SB_DQ41
SA_MA10 BB18 MEM_A_A<10> OUT 31 33 68 SB_MA10 BE17 MEM_B_A<10> OUT 32 33 68
68 31 BI MEM_A_DQ<42> BD6 SA_DQ42 68 32 BI MEM_B_DQ<42> BC1 SB_DQ42
SA_MA11 BE25 MEM_A_A<11> OUT 31 33 68 SB_MA11 BJ33 MEM_B_A<11> OUT 32 33 68
68 31 BI MEM_A_DQ<43> AW11 SA_DQ43 68 32 BI MEM_B_DQ<43> BG3 SB_DQ43
SA_MA12 BF26 MEM_A_A<12> OUT 31 33 68 SB_MA12 BH36 MEM_B_A<12> OUT 32 33 68
68 31 BI MEM_A_DQ<44> AY10 SA_DQ44 68 32 BI MEM_B_DQ<44> BC3 SB_DQ44
SA_MA13 BC17 MEM_A_A<13> OUT 31 33 68 SB_MA13 BF14 MEM_B_A<13> OUT 32 33 68
68 31 BI MEM_A_DQ<45> BD8 SA_DQ45 68 32 BI MEM_B_DQ<45> BJ5 SB_DQ45
SA_MA14 BH32 TP_MEM_A_A<14> OUT SB_MA14 BJ39 TP_MEM_B_A<14> OUT
68 31 BI MEM_A_DQ<46> AW9 SA_DQ46 68 32 BI MEM_B_DQ<46> BF6 SB_DQ46
68 31 BI MEM_A_DQ<47> BB6 SA_DQ47 68 32 BI MEM_B_DQ<47> BD2 SB_DQ47
SA_RAS* BE21 MEM_A_RAS_L OUT 31 33 68 SB_RAS* BF18 MEM_B_RAS_L OUT 32 33 68
68 31 BI MEM_A_DQ<48> AV10 SA_DQ48 68 32 BI MEM_B_DQ<48> BB2 SB_DQ48
SA_RCVEN* BJ19 NC_MEM_A_RCVEN_L 7 SB_RCVEN* BJ23 NC_MEM_B_RCVEN_L 7
B 68 31
68 31
BI
BI
MEM_A_DQ<49>
MEM_A_DQ<50>
AT10
AT6
SA_DQ49
SA_DQ50
68 32
68 32
BI
BI
MEM_B_DQ<49>
MEM_B_DQ<50>
AU3
BA3
SB_DQ49
SB_DQ50
B
SA_WE* BH20 MEM_A_WE_L OUT 31 33 68 SB_WE* BF12 MEM_B_WE_L OUT 32 33 68
68 31 BI MEM_A_DQ<51> AR9 SA_DQ51 68 32 BI MEM_B_DQ<51> AY2 SB_DQ51
68 31 BI MEM_A_DQ<52> AW7 SA_DQ52 68 32 BI MEM_B_DQ<52> AY4 SB_DQ52
68 31 BI MEM_A_DQ<53> AY6 SA_DQ53 68 32 BI MEM_B_DQ<53> AT2 SB_DQ53
68 31 BI MEM_A_DQ<54> AR7 SA_DQ54 68 32 BI MEM_B_DQ<54> AV2 SB_DQ54
68 31 BI MEM_A_DQ<55> AP6 SA_DQ55 68 32 BI MEM_B_DQ<55> AT4 SB_DQ55
68 31 BI MEM_A_DQ<56> AM6 SA_DQ56 68 32 BI MEM_B_DQ<56> AR1 SB_DQ56
68 31 BI MEM_A_DQ<57> AM10 SA_DQ57 68 32 BI MEM_B_DQ<57> AK4 SB_DQ57
68 31 BI MEM_A_DQ<58> AL11 SA_DQ58 68 32 BI MEM_B_DQ<58> AK2 SB_DQ58
68 31 BI MEM_A_DQ<59> AN11 SA_DQ59 68 32 BI MEM_B_DQ<59> AP4 SB_DQ59
68 31 BI MEM_A_DQ<60> AN7 SA_DQ60 68 32 BI MEM_B_DQ<60> AP2 SB_DQ60
68 31 BI MEM_A_DQ<61> AN9 SA_DQ61 68 32 BI MEM_B_DQ<61> AL3 SB_DQ61
68 31 BI MEM_A_DQ<62> AP10 SA_DQ62 68 32 BI MEM_B_DQ<62> AR3 SB_DQ62
68 31 BI MEM_A_DQ<63> AR11 SA_DQ63 68 32 BI MEM_B_DQ<63> AL1 SB_DQ63
NB DDR2 Interfaces
A SYNC_MASTER=M70

A
D 051-7230 B.0.0

NONE 17 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NCTF balls are Not Critical To Function
These connections can break without
impacting part performance.
PPVCORE_S0_NB_GFX 6 7 8 18 22 45 53 65 72
PP1V25_S0
21 19 18 14 13 12 11 10 8 7 6
72 54 42 30 27 26 23
PP1V05_S0 POWER
OMIT
640mA
6 7 8 16 19 21 26 27 51 57 72
AA40 AL18
(7 OF 10)
AA13
AA15
AC13
AC16
AD15
AD16
AE13
VCCA_SM
AA41 AM18
21 19 18 14 13 12 11 10 8 7 6 PP1V05_S0 AC40 U1400 AN22
D
72 54 42 30 27 26 23
VCC_AXG_NCTF AC41
FCBGA AN24 D
CRESTLINE_USFF
AA32 OMIT AE15 AD40 AN37
AA34 AE16 AE40 AN38
1310 mA (Ext Graphics)
AA35
POWER AG13 AE41
1600 mA (Int Graphics) AA38 (6 OF 10) AG15 AE43 AN15
AA37 AG16 AG40 AN16
AC32 U1400 AH16 AG41 AR13
AC34 FCBGA AJ13 AG43 AR15
CRESTLINE_USFF
AC35 AJ15 AH40 AR16
VCC_NCTF
AC37 AJ16 AH41 AR22
AC38 AL13 R35 AR24
VCC_AXG_NCTF
AD34 AL15 R38 AR25
AD35 AM15 R40 AR37
AD37 AN13 R43 AR38
VCC
AD38 R27 T35 AT15
AE35 R29 T38 AT18
AE37 R31 T40 AT19
AG35 T27 U35 AT21
AG37 T29 U38 AT22
AH37 T31 U40 AT24
AH38 U27 U41 AT25
L29 U29 U43 AT27
W35 U31 W40 AT28
W38 Y15 PPVCORE_S0_NB_GFX 6 7 8 18 22 45 53 65 72 W41 AT29
Y32 Y40 AT34
7700 mA (Int Graphics)
Y34 AT35
VCCA_SM_NCTF
Y35 W29 PP1V05_S0 AT37
C Y37 Y19 21 19 18 14 13 12 11 10 8 7 6
72 54 42 30 27 26 23
AH31
AT38 C
Y38 Y21 AU13
55 51 35 34 32 31 21 16 8 7 6
72 68
PP1V8_S3 Y25
AH32
AU16
AJ31
BA27 Y27 AU18
3300 mA (2 ch, 667MHz) AJ32
BA29 Y28 AU19
2700 mA (2 ch, 533MHz) AJ34
BA31 Y29 AU21
1700 mA (1 ch, 667MHz) AJ35
BB28 AA18 AU22
VCC_AXM
1395 mA (1 ch, 533MHz) AL31
BB30 AA19 540mA AU24
5 mA (standby) AL32
BB32 AA21 AU25
AL34
BC27 AA22 AU27
AL35
BC29 AA24 AU28
AL37
BC31 AA25 AU29
AL38
BD28 AA27 AU31
AM31
BD30 AA28 AU32
VCC_SM
AM32
BE29 AA29 AU34
BE31 AC18 AU35
BF28 AC19 21 19 18 14 13 12 11 10 8 7 6
72 54 42 30 27 26 23
PP1V05_S0 AW14
BF30 AC21 AL40 AW16
BG27 AC22 AL41 AW26
BG29 AC24 AM40 AW28
VCC_AXM_NCTF
BG31 AC25 AM41 AW30
BH28 AC27 AN40 AW32
BH30 AC28 AN41
BJ29 AC29 AR41 BL55
BK28 AD18 AT40 BL1
VSS_SCB
BK30 AD19 AT41 D1
B BL29 AD21
AD22
AU41
AU43
B2
A4
B
AW36 AD24 AW42 A55
AW38 AD25
VCC_SM_NCTF
AW40 AD27
VCC_AXG
AD28
68 6 NB_VCCSM_LF1 AP46 AD29
NB_VCCSM_LF2 BC43 AD31
VCC_SM_LF
68 6
68 6 NB_VCCSM_LF3 BA39 AE18

68 6 NB_VCCSM_LF6 BF8 AE27
68 6 NB_VCCSM_LF7 AV6 AE28
OMIT OMIT AE31
C1807 1 C1806 1 C1805 1 C1804 1 C1803 1 C1802 1 C1801 1 AH22 AG18
0.1UF 0.1UF 0.22UF 0.22UF 0.47UF 1uF 1uF AH24 AG19
10% 10% 20% 20% 10% 10% 10%
6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V 2 6.3V 2 AH25 AG21
X5R X5R X5R X5R CERM-X5R 2 CERM CERM
VCC_AXG
201 201 402 402 402 402 402 AH27 AG22

AH28 AG24
AH29 AG25
AJ18 AG27
AJ21 AG29
AJ24 AH19
AJ27 AH21
NB Power 1
VCC_AXG
A SYNC_MASTER=M70 SYNC_DATE=01/09/2007
A
AJ28
AL22
AL24
AL25
AL27
AL28
W27

D 051-7230 B.0.0

NONE 18 73
Current numbers from Crestline EDS, doc #21749.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400 F2
PP1V05_S0 6 7 8 10 11 12 13 14 TBD mA
18 21 23 26 27 30 42 54 72
@ 1067MHz FSB (1.25V)
30 mA
44 42 30 29
13 8 7 6 PP3V3_A_S0 L35 VCC_SYNC CRESTLINE_USFF 850 mA @ 800MHz FSB (1.05V)
28 27 26 25 24 23 22 21 19 16 B6
64 63 60 53 52 51 46 FCBGA 770 mA @ 667MHz FSB (1.05V)
H12
80 mA 72 22 6 PP3V3_S0_NB_VCCA_CRTDAC J33 VCCA_CRT_DAC (8 OF 10)
H16
CRT
L33 VCCA_CRT_DAC
R7
L7
J31 VCCA_DAC_BG
VTT
5 mA 72 22 6 PP3V3_S0_NB_VCCA_DAC_BG
P10
L11
D
GND H32 VSSA_DAC_BG
K12
N18
D
POWER K16
72 22 6 PP1V25_S0_NB_VCCA_DPLLA D50 VCCA_DPLLA

G7 NB_VTTLF_CAP1
VTTLF
6
100 mA AA7 6 NB_VTTLF_CAP2
PLL
72 22 6 PP1V25_S0_NB_VCCA_DPLLB J49 VCCA_DPLLB 1 C1900
P12 6 NB_VTTLF_CAP3
0.47UF
10%
50 mA 72 21 6 PP1V25_S0M_NB_VCCA_HPLL AK10 VCCA_HPLL 1 C1902 1 C1901 2 6.3V
U13 CERM-X5R
0.47UF 0.47UF 402
T15 10% 10%
6.3V 6.3V
VTT_FSB_NCTF
R13 2 CERM-X5R 2 CERM-X5R
402 402
R15
A LVDS
N14
S0 or S3M is acceptable
J45 VCCA_LVDS
R19
10 mA 72 22 19 6 PP1V8_S0_NB_VCCTXLVDS L45 VCCA_LVDS
R18
R16
GND K44 VSSA_LVDS
N16
PP1V25_S0 6 7 8 16 18 19 21 26 27 515 mA
51 57 72
42 30 29 Y48 VCCA_PEG_BG AN29
A PEG
0.4 mA 13 8 7 6 PP3V3_A_S0
28 27 26 25 24 23 22 21 19 16
64 63 60 53 52 51 46 44 AN28
VCC_AXD
GND W47 VSSA_PEG_BG AN27
AXD
AN35
100 mA 72 21 6 PP1V25_S0_NB_PEGPLL P48 VCCA_PEG_PLL AN34
AN19
AN18
C VCC_AXD_NCTF AR32
C
VCC_AXD_NCTF AR31
PP1V25_S0 6 7 8 16 18 19 21 26 27 495 mA
51 57 72
J23
C23
VCC_AXF
B24
W18
W22
W24
AXF
N22
R22
R24
T22
VCC_AXF_NCTF
T24
A CK
U16
35 mA 16 8 7 6 PP1V25_S0 BK34 VCCA_SM_CK1 U18
72 57 51 27 26 21 19 18
BL35 VCCA_SM_CK2 U19
U21
U22
U24
M25 VCCA_TVA_DAC W16
CRT
40 mA 72 22 6 PP3V3_S0_NB_VCCA_TVDACA
72 22 6 PP3V3_S0_NB_VCCA_TVDACB K26 VCCA_TVB_DAC
40 mA 72 22 6 PP3V3_S0_NB_VCCA_TVDACC K28 VCCA_TVC_DAC VCC_DMI AK44 PP1V25_S0 6 7 8 16 18 19 21 26 27 51 100 mA
57 72
B PP1V8_S3M_NB_VCCSMCK 6 21 72 200 mA B
SM CK
40 mA
VCC_SM_CK BL21
VCC_SM_CK BK22
VCC_SM_CK BJ21
TV/CRT
60 mA 72 22 19 6 PP1V5_S0_NB_VCCD_CRT L31 VCCD_CRT
60 mA 72 22 19 6 PP1V5_S0_NB_VCCD_CRT G29 VCCD_TVDAC VCC_TX_LVDS J43 PP1V8_S0_NB_VCCTXLVDS 6 19 22 72 100 mA
5 mA 72 22 6 PP1V5_S0_NB_VCCD_QDAC H30 VCCD_QDAC

VCC_HV L41
51 52 53 60 63 64
PP3V3_A_S0 6 7 8 13 16 19 21 22 23 100 mA
24 25 26 27 28 29 30 42 44 46
PP1V05_S0_NB_VCCPEG 6 15 21 72 1260 mA
VCC_PEG AB44
PEG
250 mA 16 8 7 6 PP1V25_S0 AH8 VCCD_HPLL
72 57 51 27 26 21 19 18 VCC_PEG AC45
D
Y44 VCCD_PEG_PLL VCC_PEG AD46
VCC_PEG AE45
LVDS
PP1V05_S0_NB_VCCRXRDMI 260 mA
DMI
21
150 mA 8 7 6 PP1V8_S0 J47 VCCD_LVDS1 VCC_RXR_DMI AK46

72 61 51 22
L47 VCCD_LVDS2 VCC_RXR_DMI AH46
NB Power 2
A SYNC_MASTER=M70

A
D 051-7230 B.0.0

NONE 19 73
Current numbers from Crestline EDS, doc #21749.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
VSS VSS
A11 AN1 BE9 (10 OF 10) M21
A15 U1400 AN21 BG11 M23
A19 FCBGA AN25 BG13 U1400 M27
FCBGA
CRESTLINE_USFF
A23 AN31 BG15 M29
CRESTLINE_USFF
A27 AN32 BG17 M31
A31 AN45 BG19 M33
A37 AN47 BG21 M35
A41 AN5 BG23 M37
A43 AN51 BG25 M39
D A7
AA16
AP12
AP44
BG33
BG35
M41
M43
D
AA31 AP48 BG37 M54
AA43 AP8 BG39 M6
AA49 AR18 BG41 M8
AA5 AR19 BG43 N20
AB12 AR21 BG45 N24
AB8 AR27 BG47 N26
AC1 AR28 BG49 N28
AC15 AR29 BG5 N30
AC31 AR34 BG53 N32
AC43 AR35 BG7 N34
AC47 AR40 BG9 N36
AC49 AR5 BJ27 N38
AC5 AR51 BJ31 N40
AC51 AT16 BJ35 N42
AD12 AT31 BK20 N49
AD32 AT32 BL11 N5
AD41 AT44 BL15 P46
AD44 AT48 BL25 P8
AD54 AT8 BL27 R1
AD8 AU1 BL31 R21
AE1 AU15 BL33 R25
AE19 AU37 BL41 R28
AE22 AU38 BL45 R32
AE25 AU40 BL49 R34
AE29 AU5 BL7 R37
C AE32 AU51 C31 R41 C
AE34 AU55 D4 R45
AE38 AV12 D48 R49
AE49 AV44 E11 R5
AE5 AV48 E13 R51
AF12 AV8 E15 T12
AF44 AW18 E17 T16
AF8 AW20 E19 T18
AG28 AW22 E21 T19
AG31 AW24 E23 VSS VSS T21
AG32 AW34 E25 T25
AG34 AW5 E27 T28
AG38 AW51 E29 T32
AG47 AY13 E31 T34
AG5 AY15 E33 T37
VSS VSS
AG51 AY17 E35 T41
AH12 AY19 E37 T46
AH15 AY21 E39 T54
AH18 AY23 E41 T8
AH34 AY25 E43 U1
AH35 AY27 E45 U15
AH44 AY29 E51 U25
AH54 AY31 E7 U28
AJ1 AY33 E9 U32
AJ19 AY35 F48 U34
AJ22 AY37 G1 U37
B AJ25
AJ29
AY39
AY41
G23
G5
U49
U5
B
AJ37 AY43 H18 V12
AJ38 AY48 H20 V44
AJ40 AY8 H22 V8
AJ41 B48 H24 W1
AJ45 BA1 H26 W13
AJ49 BA5 H34 W15
AJ5 BA51 H36 W19
AJ51 BA55 H38 W21
AJ9 BB38 H40 W25
AK12 BB40 H48 W28
AK8 BB48 H54 W31
AL16 BB8 J1 W32
AL19 BC5 J11 W34
AL21 BC51 J15 W37
AL29 BD10 J29 W43
AL47 BD12 J51 W45
AL49 BD14 J7 W49
AL5 BD16 J9 W5
AM12 BD18 K32 W51
AM16 BD20 K46
AM19 BD22 K48 Y12
AM21 BD24 K6 Y16
AM22 BD26 L1 Y18 NB Grounds
AM24 BD32 L25 Y22
A AM25 BD34 L27 Y24
SYNC_MASTER=M70

A
AM27 BD36 L51 Y31
AM28 BD38 M10 Y41 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
AM29 BD40 M13 Y46 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AM34 BD42 M15 Y54 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
AM35 BD44 M17 Y8 II NOT TO REPRODUCE OR COPY IT
AM37 BD46 M19 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
AM38 BE1
AM44 BE5 SIZE DRAWING NUMBER REV.
AM52 BE51 D 051-7230 B.0.0

AM8 BE55
NONE 20 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I/O voltage Supply

GMCH Core Power Host PLL Digital Supply
57 51 27 26 21 19 18 16 8 7 6 PP1V25_S0 PP1V25_S0 6 7 8 16 18 19 21 26 27 51 57
21 19 18 14 13 12 11 10 8 7 6 PP1V05_S0 72 72 57 51 27 26 21 19 18 16 8 7 6 PP1V25_S0 PP1V25_S0 6 7 8 16 18 19 21 26 27 51 57
72 54 42 30 27 26 23 495 mA 72 72
1600 mA OMIT 450 mA 250 mA

CRITICAL 1 C2170
D C2100 1
330UF
1 C2101
22UF
1 C2102
0.22uF
1 C2103
0.22uF
1 C2104
0.1UF
1UF
10%
Layout Note:
PLACE C2170 NEAR J23..W24
1 C2180
0.1UF Layout Note: D
20% 20%
6.3V
20%
6.3V
20%
6.3V
10%
6.3V 2 6.3V
CERM
10%
6.3V Place C2180 Near Pin AH8
2.5V 2 2 CERM 2 X5R 2 X5R 2 X5R 2 X5R
POLY 402
CASE-C2-SM-1 805 402 402 201 201
250mA,0.5ohm
PLACEMENT_NOTE=Place in GMCH cavity
L2181 Host PLL Analog Supply
120-OHM-0.3A-EMI PP1V25_S0M_NB_VCCA_HPLL 6 19 72
CRITICAL 1 2 MIN_LINE_WIDTH=0.25 MM
GMCH ME Core Power MIN_NECK_WIDTH=0.2 MM
L2173 Analog,I/O logic,and Term Voltage for PCI-E Graphics 0402-LF
VOLTAGE=1.25V 50 mA
21 19 18 14 13 12 11 10 8 7 6 PP1V05_S0 21 19 18 14 13 12 11 10 8 7 6 PP1V05_S0 91NH PP1V05_S0_NB_VCCPEG 6 15 19 72
72 54 42 30 27 26 23 72 54 42 30 27 26 23 MIN_LINE_WIDTH=0.5 MM C2181 1 1 C2182
1 2 MIN_NECK_WIDTH=0.2 MM
540 mA 1520 mA VOLTAGE=1.05V 1260 mA 22UF 0.1UF Layout Note:
1210 CRITICAL 20% 10%
6.3V
2 6.3V
1 1 1 CERM 2 X5R Place C2182 Near Pin AK10
1 C2110 1 C2111 1 C2112 C2113 C2114 C2115 C2173 1 C2174 805 201
22UF 0.22uF 0.22uF 0.1UF 0.1UF 0.1UF Layout Note: 220UF 22UF
20% 20% 20% 10% 10% 10% 20% Layout Note:
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V Place L and C 20% 6.3V
2 CERM 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2.5V 2
POLY CERM 22uF caps should 250mA,0.5ohm
805 402 402 201 201 201 close to MCH CASE-B2-HF 805
be close to MCH
on opposite side.
Place C2110-12 on edge near AH31..AM32 Place C2113-2115 close as possible to AH31..AM32
Place C2174 Near Pins AB44..AE45
These supplies are still needed even using external GPU

GMCH FSB I/O Rail
RX and I/O Logic for DMI
21 19 18 14 13 12 11 10 8 7 6 PP1V05_S0 PP1V05_S0_NB_VCCRXRDMI 19
72 54 42 30 27 26 23
850 mA 260 mA
C2121 1 C2122 1 C2123 1 C2124 1 1 C2177

4.7uF 4.7uF 2.2uF 0.47UF 22UF Layout Note:
20% 20% 20% 10% 20% 22uF caps should
6.3V 2 6.3V 2 6.3V 6.3V 6.3V
CERM CERM CERM1 2 CERM-X5R 2 2 CERM
603 603 603 402 805 be close to MCH
C PLACEMENT_NOTE=Place C2121-24 close to U1400.F2..K16

on opposite side.
Place C2177 Near Pins AH46,AK46
C
GMCH Memory I/O Rail
51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3
72 68 55
3300 mA
CRITICAL
C2130 1 1 C2135 1 C2132 1 C2133
330UF 0.1UF 22UF 22UF
20% 10% 20% 20%
2.0V 6.3V 6.3V 6.3V
2 2 X5R 2 CERM 2 CERM
POLY
CASE-B2-HF 201 805 805
this is "1 of 2" 1.8V bulk decoupling caps.

PLACEMENT_NOTE=Place C2132,C2133 close to U1400.BA27..BL29
Place C2135 where LVDS taps from DDR2 plane.

D2186 R2186
Memory I/O logic and DLL voltage. 1SS418 10
72 54 42 30 27 2 1 53 60 63 64
57 51 27 26 21 19 18 16 8 7 6 PP1V25_S0 PP1V25_S0 6 7 8 16 18 19 21 26 27 51 57 8 7 6 PP1V05_S0 PP3V3_S0_NBCORE_FOLLOW_R 1 2 PP3V3_A_S0 6 7 8 13 16 19 21 22 23 24 25
72 72 26 23 21 19 18 14 13 12 11 10 MIN_LINE_WIDTH=0.4 MM 26 27 28 29 30 42 44 46 51 52
MIN_NECK_WIDTH=0.2 MM 1%
675 mA 640 mA SOD-723 VOLTAGE=3.3V 1/16W
CRITICAL OMIT MF-LF
402
C2140 1 1
C2142 1
C2143 1
C2144
Layout Note: NOTE: This follower is redundant if VCORE is always 1.05V.
100UF 22UF
20% 10%
4.7UF
10%
1UF
20% 6.3V 6.3V 6.3V PLACE C2143,C2144 NEAR AL18..AN38
6.3V 2 2 CERM 2 X5R-CERM 2 CERM
POLY
B2-HF 805 603 402
Analog PLL Voltage for PCI-E GPU

L2190
Memory clock logic voltage. FERR-220-OHM-2.5A
57 51 27 26 21 19 18 16 8 7 6 PP1V25_S0 PP1V25_S0_NB_PEGPLL 6 19 72
PP1V25_S0 6 7 8 16 18 19 21 26 27 51 57 72
1 2 MIN_LINE_WIDTH=0.25 MM
72 MIN_NECK_WIDTH=0.2 MM
B 35 mA
100 mA 0603
VOLTAGE=1.25V 100 mA
B
1 C2145 1 C2148 R2190 1 1 C2191 1 C2192 Layout Note:
22UF 0.1UF Layout Note: 1.1 0.1UF 0.1UF
20% 10% 1% 10% 10% PLACE C2191 NEAR U1400.P48
6.3V 6.3V PLACE C2145,C2148 NEAR BL35,BK34 1/16W 6.3V 6.3V
2 CERM 2 X5R MF-LF 2 X5R 2 X5R PLACE C2192 NEAR U1400.Y44
805 201 402 201 201
2
72 6 PP1V25_S0_NB_PEGPLL_RC
OMIT MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V
C2190 1
Memory voltage supply. 10uF
20%
515 mA 6.3V 2
PP1V25_S0 X5R
6 7 8 16 18 19 21 26 27 51 57 603
72
OMIT
1 C2151
Layout Note: 1UF
10%
6.3V need to find "1uH,220mA,150mohm max"
PLACE C2151 NEAR AN29..AN18 2 CERM
402
PP1V8_S3 PP1V8_S3 L2195
51 35 34 32 31 21 18 16 8 7 6
72 68 55
51 35 34 32 31 21 18 16 8 7 6
72 68 55
1.0UH-0.23A PP1V8_S3M_NB_VCCSMCK 6 19 72
72 1 2 MIN_LINE_WIDTH=0.25 MM
31 21 18 16 8 7 6 200 mA PP1V8_S3 MIN_NECK_WIDTH=0.2 MM
68 55 51 35 34 32
0603
VOLTAGE=1.8V 200 mA
NB_VTTREF_DIV1 NB_VTTREF_DIV
1 1
R2112 R2110 R2195 1 C2196 1 Layout Note:
Layout Note:
1K 1K 1.1 22UF C2197
20% 0.1UF PLACE C2197 AND FILTER CLOSE TO BL21..BJ21
PLACE C2161 NEAR PIN L41 1% 1% 1% 6.3V 10%
60 53 52 51 46 44 1/20W 1/20W 1/16W CERM 2 6.3V
100 mA 21 19 16 13 8 7 6 PP3V3_A_S0
42 30 29 28 27 26 25 24 23 22
MF MF MF-LF 805 2 X5R
100 mA 72
64 63 PP1V25_S0
6
57 51 27 26 21 19 18 16 8 7
PP3V3_A_S0 28 29
6 7 85 mA
13 16 19 21 22 23 24 25 26 27
201
2
PP0V9_S3M_MEM_NBVREFA 8 16 68
201
2
PP0V9_S3M_MEM_NBVREFB 8 16 68
402
2 201
NB Standard Decoupling
30 42 44 46 51 52 53 60 63 64
A Layout Note:
1 C2160
0.1UF
1 C2161
0.1UF
1 C2165
0.1UF
Layout Note:
PLACE C2165 BETWEEN Y48,W47
NB_VTTREF_DIV
R2113 1 NB_VTTREF_DIV
R21111 72 6 PP1V8_S3_NB_VCCSMCK_RC
SYNC_MASTER=M70

A
10% 10% 10% 1K 1K
PLACE C2160 NEAR PIN AK44 6.3V 6.3V 6.3V OMIT MIN_NECK_WIDTH=0.2 MM
2 X5R 2 X5R 2 X5R 1% 1% VOLTAGE=1.8V
201 201 201 1/20W 1/20W C2195 1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
MF MF
10uF PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
201
2 201
2 20% AGREES TO THE FOLLOWING
GND 6.3V 2
Layout Note: X5R I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
Layout Note: Route to caps, then GND PLACE NEAR NB 603 II NOT TO REPRODUCE OR COPY IT
D 051-7230 B.0.0

Current numbers from Crestline EDS Addendum, doc ..... NONE 21 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
63 53 52 51 47 43 40 27 8 7 6 PP5V_S0
72
205 mA
1
CRITICAL
R2281 CRITICAL C2289
0
5%
U2280 MIN_LINE_WIDTH=0.6MM
L2288
180-OHM-1.5A
22000pF-1000mA
16V
1/20W TPS79933 VOLTAGE=3.3V NFM18 PP3V3_S0_NB_VCCA_CRTDAC 6 19 72
OMIT MF
6 IN SON OUT 1 205 mA 1 3 MIN_LINE_WIDTH=0.4 MM
201 72 6 PP3V3_S0_NB_TVDAC 72 6 PP3V3_S0_NB_CRTDAC_F MIN_NECK_WIDTH=0.2 MM
C2280 1 2
0603
MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V 80 mA
1UF MIN_NECK_WIDTH=0.2 MM 1
10% P3V3TVDAC_EN_RC 4 EN NR 2
VOLTAGE=3.3V C2295 1 2
6 6 P3V3TVDAC_NOISE 80 mA C2288 Layout Note:
D
6.3V
CERM 2
402 1
NO STUFF NC
5 NC
THRML C2282 1 1
OMIT
C2285 2
0.01UF
10%
10V
0.1UF
10% These 2 caps should be D
C2281 PAD
X5R
2 6.3V within 6.35 mm of NB edge
NOTE: This filter is required even if using only external graphics. GND 0.01UF 10UF 201 X5R
1UF 10% 20%
201
2 10%
6.3V
3 7 10V 2 6.3V
2 X5R
VCCD_TVDAC also powers internal thermal sensors. CERM
402
X5R
CRITICAL 201 603
C2201
22000pF-1000mA CRITICAL
72 16V CRITICAL C2292
12 11 8 7 6 PP1V5_S0 NFM18 PP1V5_S0_NB_VCCD_CRT 6 19 22 72 NO STUFF NO STUFF
54 27 26 22
1 3 MIN_LINE_WIDTH=0.2 MM D2285 L2290 22000pF-1000mA
125 mA
VOLTAGE=1.5V 60 mA 1SS418 R2285 180-OHM-1.5A 16V
NFM18 PP3V3_S0_NB_VCCA_TVDACA 6 19
72 54 27 2 1 10 1 3 MIN_LINE_WIDTH=0.3 MM 72
1 2 PP1V5_S0_NB_VCCD_CRT 6 19 22 72 11 8 7 6 PP1V5_S0 PP3V3_S0_NB_TVDAC_FOLLOW 1 2 72 6 PP3V3_S0_NB_TVDAC_F MIN_NECK_WIDTH=0.2 MM

C2202 1 C2200 MIN_LINE_WIDTH=0.2 MM 26 22 12 MIN_LINE_WIDTH=0.4 MM
1% 0603
MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V 40 mA
0.01UF 0.1UF MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM 1
10% VOLTAGE=1.5V 60 mA SOD-723 VOLTAGE=3.3V 1/16W VOLTAGE=3.3V C2293 2
10%
10V 6.3V
MF-LF 125 mA 0.01UF
X5R 2 2 X5R 402
10%
201 201 2 10V
X5R
19 6
72 22
PP1V5_S0_NB_VCCD_CRT PP1V5_S0_NB_VCCD_CRT 22
6
201
MAKE_BASE=TRUE 19
72
C2291 1
R22051 0.1UF
10%
100 CRITICAL 6.3V
X5R 2 CRITICAL
1%
1/16W C2206 201 C2294
MF-LF 22000pF-1000mA 22000pF-1000mA
402 2 16V OMIT OMIT OMIT OMIT OMIT OMIT OMIT 16V
NFM18 PP1V5_S0_NB_VCCD_QDAC 6 19 72
1 1 1 1 1 1 1 NFM18 PP3V3_S0_NB_VCCA_TVDACB 6 19
PP1V5_S0_NB_QDAC 1 3 MIN_LINE_WIDTH=0.2 MM C2219 C2231 C2232 C2240 C2241 C2242 C2243 1 3 MIN_LINE_WIDTH=0.3 MM 72
MIN_NECK_WIDTH=0.2 MM 10uF 10uF 10uF 2.2UF 2.2UF 2.2UF 2.2UF MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.2 MM VOLTAGE=1.5V 500 uA 20% 20% 20% 20% 20% 20% 20% VOLTAGE=3.3V 40 mA
MIN_NECK_WIDTH=0.2 MM 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
VOLTAGE=1.5V 1 1 2 1 2 X5R 2 X5R 2 X5R 2 CERM 2 CERM 2 CERM 2 CERM 2
C2205 C2207 C2208 603 603 603 402-LF 402-LF 402-LF 402-LF
Filtering changed per SR MOW # 541194 0.01UF 0.1UF 1UF GMCH Graphics Core Power
10% 10% 10%
10V 6.3V 10V
X5R 2 2 X5R 2 X5R Layout Note:
201 201 402-1 72 65 53 45 18 8 7 6 PPVCORE_S0_NB_GFX
These 11 caps should be
7700 mA within 6.35 mm of NB edge
C CRITICAL
C2210 1 1
OMIT
C2213 1
OMIT
C2214 1
OMIT
C2215 1 C2216 1 C2217 1 C2218 CRITICAL
C
330UF 10uF
20%
2.2UF
20%
2.2UF
20%
0.47UF
10%
0.1UF
10%
0.1UF
10%
C2296
Layout Note: 20% 22000pF-1000mA
2.5V 2 2 6.3V
X5R 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM-X5R 2 6.3V
X5R 2 6.3V
X5R 16V
These 4 caps should be POLY
603 402-LF 402-LF 402 201 201 NFM18 PP3V3_S0_NB_VCCA_TVDACC 6 19
CASE-C2-SM-1 MIN_LINE_WIDTH=0.3 MM 72
within 6.35 mm of NB edge 1 3 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V 40 mA
PLACEMENT_NOTE=Place in GMCH cavity Place smaller caps as close as possible to NB pins.
2
NEED TO FIND A "1#GH, 500MA, 78MOHM" INDUCTOR

L2220
72 61 51 22 19 8 7 6 PP1V8_S0 1.0UH-0.5A-0.675A PP1V8_S0_NB_VCCTXLVDS 6 19 72
1 2 MIN_LINE_WIDTH=0.2 MM CRITICAL
64 63 60 53 MIN_NECK_WIDTH=0.2 MM C2298
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0 260 mA VOLTAGE=1.8V 110 mA
52 51 46 44 42 30 29 28 27 26 1007 22000pF-1000mA
16V
CRITICAL1 1 C2221
1 C2223 NFM18 PP3V3_S0_NB_VCCA_DAC_BG 6 19
C2220 1000PF Place C2221,C2223 close between J45,L45,J43 and K44 1 3 MIN_LINE_WIDTH=0.2 MM 72
1NO STUFF 1NO STUFF 1 NO STUFF 1 220UF 1000PF 10%

R2242 R2243 R2244 R2245 20% 10% 16V
2 X7R
VOLTAGE=3.3V 5 mA
22K 22K 22K 22K 2.5V 2 2 16V
X7R 201 2
5% 5% 5% 5% POLY 1 C2299 1 C2297
CASE-B2-SM-HF 201 GND
1/20W 1/20W 1/20W 1/20W 0.01UF 0.1UF
MF MF MF MF 10% 10%
2 201 2 201 2 201 2 201 Layout Note: Route to cap, then GND 2
10V 6.3V
2 X5R
X5R
201 201
GFX_VID<0> OUT 6 16 53 GND
GFX_VID<1> OUT 6 16 53
PP1V8_S0 6 7 8 19 22 51 61 72 Layout Note: Route to caps, then GND
GFX_VID<2> OUT 6 16 53
GFX_VID<3> OUT 6 16 53 150 mA

1 C2226
1 1NO STUFF 22UF Place C2226 close to Pins J47, L47
R2247 1R2248 1
R2249 R2250 20%
B 5%
22K
1/20W
22K
5%
1/20W
5%
22K
1/20W
22K
5%
1/20W
6.3V
2 CERM
805 B
MF MF MF MF
2 201 2 201 2 201 2 201
64 63 60 53
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0
52 51 46 44 42 30 29 28 27 26
10 mA 1 C2230
0.1UF Place C2230 close to Pin L35
10%
6.3V
2 X5R
201
CRITICAL
Vout = 1.204V * (Ra + Rb)/Rb
WARNING VOLTAGE DROP U2265 Ra || Rb should be 19Kohms
72 61 51 22 19 8 7 6 PP1V8_S0 TPS731125
SOT23-5
(1.7V - 5.5V) 1 IN OUT 5 72 6 PP1V25_S0_NB_DPLL R2261 PP1V25_S0_NB_VCCA_DPLLA 6 19 72
3 EN MIN_LINE_WIDTH=0.4 MM 0 MIN_LINE_WIDTH=0.3 MM
80 mA OMIT NR/FB 4 MIN_NECK_WIDTH=0.2 MM 1 2 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V 80 mA VOLTAGE=1.25V
C2265 1
GND 5%
1UF OMIT 1/16W
1
2 P1V25S0NBDPLL_FB 6
1
MF-LF C2261
10% C2266 402
6.3V
CERM 2 10UF
0.1UF
10% 80 mA
NB Graphics Decoupling
402 20% 6.3V
2 X5R Place C2261 close to Pin D50
2 6.3V
A 6 P1V25S0NBDPLL_RF
X5R
603
201 SYNC_MASTER=M70

A
1
1 C2267 R2266 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
0.300 R2262 PP1V25_S0_NB_VCCA_DPLLB 6 19 72 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
0.01UF 5% 0 MIN_LINE_WIDTH=0.3 MM AGREES TO THE FOLLOWING
10% 1/10W 1 2 MIN_NECK_WIDTH=0.2 MM
2 10V
X5R FF OMIT VOLTAGE=1.25V I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
603 5%
201 2 C2260 1 1/16W II NOT TO REPRODUCE OR COPY IT
MF-LF 1 C2262
10uF 402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
20% 0.1UF Place C2262 close to Pin J49
6.3V 10%
X5R 2 6.3V
603 2 X5R SIZE DRAWING NUMBER REV.
201
D 051-7230 B.0.0

Current numbers from Crestline EDS Addendum, doc #20127. NONE 22 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
64 63 60 53
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0
52 51 46 44 42 30 29 28 27 26
1
R2310
8.2K
72 27 26 24 6 PP1V5_S0_SB_VCC1_5_B 5%
1/20W
43 42 41 40 39 28 27 26 8 7 6 PP3V42_G3H MF
72 59 57 44 201
2
D R2300
1 1
R2301
1
R2302 D
332K 332K 24.9
1% 1% 1%
1/20W 1/20W 1/20W
MF MF MF
201 201 201
2 2 2 OMIT
28 6 IN SB_RTC_X1 AA23 RTCX1 FWH0/LAD0 E7 LPC_AD<0> BI 6 41 43
28 6 SB_RTC_X2 AA24 RTCX2 U2300 FWH1/LAD1 D6 LPC_AD<1> 6 41 43 PP3V3_A_S0 53 60 63 64

6 7 8 13 16 19 21 22 23 24 25
INT PU
OUT BI 26 27 28 29 30 42 44 46 51 52
SB_ICH8M FWH2/LAD2 C6 LPC_AD<2> BI 6 41 43
28 6 SB_RTC_RST_L AB22 RTCRST* BGA FWH3/LAD3 B6 LPC_AD<3> 6 41 43

IN BI 8
(1 OF 6) 8
28 6 IN SB_SM_INTRUDER_L AB23 INTRUDER* FWH4/LFRAME* B2 LPC_FRAME_L OUT 6 41 43 RP2502
8.2K RP2405
10K
6 SB_INTVRMEN AA19 INTVRMEN INT PU LDRQ0* F8 TP_LPC_DRQ0_L 5% PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21
RTC LPC 1/32W 5% 26 27 30 42 54 72
6 SB_LAN100_SLP Y19 LAN100_SLP INT PU LDRQ1*/GPIO23 B1 NC_EXTGPU_PWR_EN BI 4X0201 1/32W
1 4X0201
1 PLACEMENT_NOTE=Place R2309 within 50mm of R2308 (NO STUB)
TP_ENET_GLAN_CLK C23 GLAN_CLK A20GATE AC9 6 SB_A20GATE
1 1
A20M* Y17 CPU_A20M_L 6 10 66
R2305 R2309
OUT 54.9 54.9
TP_LAN_RSTSYNC C22 LAN_RSTSYNC 1% 1%
DPRSTP* AA20 CPU_DPRSTP_L OUT 6 10 16 52 66 1/20W 1/20W
MF MF
TP_LAN_D2R<0> B21 LAN_RXD0 INT PU DPSLP* W21 CPU_DPSLP_L 6 10 66 201
OUT 2 2 201
TP_LAN_D2R<1> D18 LAN_RXD1 INT PU
FERR* W19 CPU_FERR_L IN 6 10 66
TP_LAN_D2R<2> B20 LAN_RXD2 INT PU
TP_LAN_R2D<0> B23 LAN_TXD0 LAN/GLAN CPUPWRGD/GPIO49 Y22 CPU_PWRGD OUT 6 10 13 66
TP_LAN_R2D<1> C18 LAN_TXD1

TP_LAN_R2D<2> A23 LAN_TXD2 IGNNE* Y20 CPU_IGNNE_L OUT 6 10 66
25 6 LAN_PHYPC W18 GLAN_DOCK*/GPIO12 INIT* AA22 CPU_INIT_L OUT 6 10 66
INTR AA21 CPU_INTR OUT 6 10 66
70 6 GLAN_COMP D24 GLAN_COMPI CPU RCIN* AD8 6 SB_RCIN_L

C D23 GLAN_COMPO
NMI Y23 CPU_NMI OUT 6 10 66
C
69 37 9 7 6 OUT HDA_BIT_CLK R2313 27 1 2 69 6 HDA_BIT_CLK_R AC10 HDA_BIT_CLK INT PD SMI* W22 CPU_SMI_L OUT 6 10 66
5% 1/20W MF 201
69 37 9 7 6 OUT HDA_SYNC R2314 27 1 2 69 6 HDA_SYNC_R AD9 HDA_SYNC INT PD
5% 1/20W MF 201 STPCLK* W24 CPU_STPCLK_L OUT 6 10 66
R2308
69 37 9 6 OUT HDA_RST_L R2315 27 1 2 69 6 HDA_RST_L_R AD13 HDA_RST* 24.9
5% 1/20W MF 201 THRMTRIP* W20 6 CPU_THERMTRIP_R 1 2 PM_THRMTRIP_L 6 10 16 42 66
IN
69 37 9 7 6 IN HDA_SDIN0 AD12 HDA_SDIN0 INT PD NO STUFF 1%
1
1/20W PLACEMENT_NOTE=Place R2308 within 50mm of U2300
TP_HDA_SDIN1 Y11 HDA_SDIN1 INT PD TP8 W23 TP_SB_TP8 R2304 MF
201
TP_HDA_SDIN2 AD11 HDA_SDIN2 INT PD IHDA 2.2K
5%
TP_HDA_SDIN3 W11 HDA_SDIN3 INT PD DD0 M1 IDE_PDD<0> BI 6 38 69 1/20W
MF
DD1 L5 IDE_PDD<1> BI 6 38 69 201
2
69 37 9 7 6 HDA_SDOUT R2316 27 1 2 69 6 HDA_SDOUT_R AB10 HDA_SDOUT INT PD DD2 M4 IDE_PDD<2> 6 38 69
OUT BI
5% 1/20W MF 201
DD3 M6 IDE_PDD<3> BI 6 38 69
6 HDA_DOCK_EN_L AD3 HDA_DOCK_EN*/GPIO33 DD4 N4 IDE_PDD<4> BI 6 38 69
TP_HDA_DOCK_RST_L AD10 HDA_DOCK_RST*/GPIO34 DD5 N3 IDE_PDD<5> BI 6 38 69
DD6 R3 IDE_PDD<6> BI 6 38 69
TP_SB_SATALED_L AC3 SATALED* INT PU INT PD DD7 P1 IDE_PDD<7> BI 6 38 69
DD8 L2 IDE_PDD<8> BI 6 38 69
UNUSED SATA INTERFACE
AA4 SATA0RXN DD9 L3 IDE_PDD<9> BI 6 38 69
AA3 SATA0RXP DD10 M5 IDE_PDD<10> BI 6 38 69
9 NC_SATA_A_R2D_C_N AB1 SATA0TXN DD11 U1 IDE_PDD<11> BI 6 38 69

69
NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

9 NC_SATA_A_R2D_C_P AB2 SATA0TXP DD12 N6 IDE_PDD<12> BI 6 38 69
69
DD13 M3 IDE_PDD<13> BI 6 38 69
W4 SATA1RXN DD14 M2 IDE_PDD<14> BI 6 38 69
W3 SATA1RXP DD15 T3 IDE_PDD<15> BI 6 38 69
9 NC_SATA_B_R2D_C_N Y1 SATA1TXN
69 DA0 R5 IDE_PDA<0> OUT 6 38 69
9 NC_SATA_B_R2D_C_P Y2 SATA1TXP
B 69 DA1
DA2
P5
T4
IDE_PDA<1>
IDE_PDA<2>
OUT
OUT
6 38 69
6 38 69
B
V5 SATA2RXN
V4 SATA2RXP SATA IDE
9 NC_SATA_C_R2D_C_N V1 SATA2TXN DCS1* T1 IDE_PDCS1_L OUT 6 38 69
69
9 NC_SATA_C_R2D_C_P V2 SATA2TXP DCS3* R4 IDE_PDCS3_L OUT 6 38 69
69
W7 SATA_CLKN DIOR* R2 IDE_PDIOR_L OUT 6 38 69
W6 SATA_CLKP DIOW* N1 IDE_PDIOW_L OUT 6 38 69

64 63 60 53
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0 DDACK* P3 IDE_PDDACK_L OUT 6 38 69
52 51 46 44 42 30 29 28 27 26
U4 SATARBIAS* IDEIRQ P4 IDE_IRQ14 IN 6 38 69
1
R2311 U5 SATARBIAS IORDY P2 IDE_PDIORDY 6 38 69
IN
10K
5% DDREQ R1 IDE_PDDREQ IN 6 38 69
1/20W
MF
201 25 6 SB_GPIO10_CL1 AB15 ALERT*/GPIO10
2
6 LAN_ENERGY_DET AD18 ENERGY_DETECT/GPIO13
43 25 6 BOOTROM_OVR_EN_L AC24 NETDETECT/GPIO14
HDA SB Enet, Disk, FSB, LPC
A HDA_BIT_CLK 24.000MHZ CLOCK W/INTERNAL WEAK PD

SYNC_MASTER=M70

A
HDA_RST#

HDA_SDIN[0-2] INTEGRATED PDs PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
HDA_SDOUT INTEGRATED PD I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
ACZ_SYNC INTEGRATED PD
D 051-7230 B.0.0

NONE 23 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U2300
TP_PCIE_A_D2R_N M22 PERN1 SB_ICH8M DMI0RXN N20 DMI_N2S_N<0> IN 6 16 67
TP_PCIE_A_D2R_P M21 PERP1 BGA DMI0RXP N19 DMI_N2S_P<0> 6 16 67

IN
(2 OF 6)
TP_PCIE_A_R2D_C_N L23 PETN1 DMI0TXN P22 DMI_S2N_N<0> OUT 6 16 67
Spares OMIT
TP_PCIE_A_R2D_C_P L24 PETP1 DMI0TXP P21 DMI_S2N_P<0> OUT 6 16 67
(x2-capable,
pull HDA_SYNC TP_PCIE_B_D2R_N L19 PERN2 DMI1RXN T21 DMI_N2S_N<1> IN 6 16 67
DIRECT MEDIA INTERFACE

high for x2) TP_PCIE_B_D2R_P L20 PERP2 DMI1RXP T22 DMI_N2S_P<1> IN 6 16 67
TP_PCIE_B_R2D_C_N K21 PETN2 DMI1TXN R24 DMI_S2N_N<1> OUT 6 16 67
TP_PCIE_B_R2D_C_P K22 PETP2 DMI1TXP R23 DMI_S2N_P<1>
PCI_EXPRESS
OUT 6 16 67
D TP_PCIE_EXCARD_D2R_N J20 PERN3 DMI2RXN R20 DMI_N2S_N<2> IN 6 16 67

D
ExpressCard TP_PCIE_EXCARD_D2R_P J19 PERP3 DMI2RXP R19 DMI_N2S_P<2> IN 6 16 67
TP_PCIE_EXCARD_R2D_C_N J24 PETN3 DMI2TXN U23 DMI_S2N_N<2> OUT 6 16 67
TP_PCIE_EXCARD_R2D_C_P J23 PETP3 DMI2TXP U24 DMI_S2N_P<2> OUT 6 16 67
TP_PCIE_FW_D2R_N G19 PERN4 DMI3RXN U20 DMI_N2S_N<3> IN 6 16 67
FireWire TP_PCIE_FW_D2R_P G20 PERP4 DMI3RXP U19 DMI_N2S_P<3> IN 6 16 67
TP_PCIE_FW_R2D_C_N H22 PETN4 DMI3TXN V22 DMI_S2N_N<3> OUT 6 16 67
TP_PCIE_FW_R2D_C_P H21 PETP4 DMI3TXP V21 DMI_S2N_P<3> OUT 6 16 67
70 36 6 IN PCIE_E_D2R_N F22 PERN5 DMI_CLKN N23 SB_CLK100M_DMI_N IN 6 29 30 71
PCIe Mini Card
70 36 6 IN PCIE_E_D2R_P F21 PERP5 DMI_CLKP N24 SB_CLK100M_DMI_P IN 6 29 30 71
(AirPort)
70 36 6 OUT PCIE_E_R2D_C_N G24 PETN5
CHOOSE 1GB or 2GB CONFIG 70 36 6 PCIE_E_R2D_C_P G23 PETP5 DMI_ZCOMP V18 R2413 PP1V5_S0_SB_VCC1_5_B 6 23 26 27 72
OUT 24.9
CHOOSE DRAM VENDOR
49 44 43 36 28 27 26 25 8 7 6 PP3V3_S5 DMI_IRCOMP V19 6 DMI_IRCOMP_R 1 2
72 60 58 57 56 51
Ethernet TP_PCIE_ENET_D2R_N E20 PERN6/GLAN_RXN 1% 1/20W MF 201
Yukon-PCIE TP_PCIE_ENET_D2R_P E19 PERP6/GLAN_RXP INT PD USBP0N E2 USB2_EXTA_N BI 6 9 39 69

5 8 6 External A
DRAM_SPD_11 DRAM_2GB1 Nineveh-GLCI TP_PCIE_ENET_R2D_C_N E24 PETN6/GLAN_TXN INT PD USBP0P E3 USB2_EXTA_P BI 6 9 39 69
RP2407 RP2406 RP2406 R2442 R2440 TP_PCIE_ENET_R2D_C_P E23 PETP6/GLAN_TXP INT PD USBP1N F3 USB2_AIRPORT_N 6 9 36 69
10K 10K BI
10K 10K 10K AirPort (PCIe Mini-Card)
5% 5% INT PD USBP1P F4 USB2_AIRPORT_P BI 6 9 36 69
5% 5% 5% 1/20W 1/20W
1/32W 1/32W 1/32W MF MF 69 49 6 BI SPI_SCLK_R C20 SPI_CLK INT PU INT PD USBP2N D1 TP_USB2_3G_N BI 9 69
4X0201 4X0201 4X0201 201 201 External D / WWAN
4 1 3 2 2 69 49 6 SPI_CE_R_L<0> D21 SPI_CS0* INT PD USBP2P D2 TP_USB2_3G_P 9 69
7 5 6 8 BI BI
EHCI0
69 43 6 SPI_CE_R_L<1> C21 SPI_CS1* INT PU INT PD USBP3N G3 USB2_CAMERA_N BI 6 9 60 69
RP2407 RP2405 RP2405 RP2407 SPI Camera
10K 10K 10K 10K INT PD USBP3P G2 USB2_CAMERA_P BI 6 9 60 69
69 49 6 BI SPI_SI_R D22 SPI_MOSI INT PU
5% 5% 5% 5% INT PD USBP4N F1 USB_IR_N BI 6 7 9 40 69
1/32W 1/32W 1/32W 1/32W 69 49 43 6 BI SPI_SO D19 SPI_MISO INT PU IR
4X0201 4X0201 4X0201 4X0201 INT PD USBP4P F2 USB_IR_P BI 6 7 9 40 69
C 39 13 9 7 6 EXTAUSB_OC_L
2 4 3 1
Y13 OC0*
INT PD
INT PD
USBP5N
USBP5P
H3
H4
USB2_WSPRING_N
USB2_WSPRING_P
BI 6 7 9 40 69
6 7 9 40 69
Wellspring Trackpad/Keyboard
C
IN BI
13 7 6 OUT SB_GPIO40 AB12 OC1*/GPIO40 INT PD USBP6N H1 NC_USB_BT_N BI 9 69
Bluetooth
13 7 6 IN USB_EXTD_OC_L AA12 OC2*/GPIO41 INT PD USBP6P H2 NC_USB_BT_P BI 9 69
36 13 7 6 WOW_EN AD14 OC3*/GPIO42 USB INT PD USBP7N J2 NC_USB2_EXTB_N 9 69

OUT BI
External B
W10 J3
EHCI1
13 7 6 OUT PM_LATRIGGER_L OC4*/GPIO43 INT PD USBP7P NC_USB2_EXTB_P BI 9 69
13 7 6 OUT EXTGPU_LVDS_EN AC12 OC5*/GPIO29 INT PD USBP8N K1 TP_USB_EXCARD_N BI 9 69

ExpressCard
13 7 6 OUT SB_GPIO30 AA11 OC6*/GPIO30 INT PD USBP8P K2 TP_USB_EXCARD_P BI 9 69
13 9 7 6 IN EXTBUSB_OC_L AB11 OC7*/GPIO31 INT PD USBP9N K4 TP_USB_EXTC_N BI 9 69

External C
6 EXCARD_OC_L AA13 OC8* INT PD USBP9P K3 TP_USB_EXTC_P BI 9 69
6 USB_EXTC_OC_L AB13 OC9*

R2414 NOTE: USBP[0-9]P/N have internal 15K pull-downs.
1 USBRBIAS* C1
DRAM_SPD_2 DRAM_1GB1 R2406 22.6
1 USBRBIAS C2 69 6 USB_RBIAS 1 2
R2443 R2441 100K
10K 10K 5% 1%
5% 5% 1/20W 1/20W
1/20W 1/20W MF MF
MF MF 201 201
201 201
2
2 2
NOTE: GNT[0-3]# have internal 20K pull-ups

enabled only when PCIRST# = 0 and PWROK = 1
If used, ensure GNT2# is not low when PWROK
rises, or PCIe ports 5 & 6 will be disabled.
U2300
9 BI NC_PCI_AD<0> A20 AD0 SB_ICH8M REQ0* A7 PCI_FW_REQ_L IN 6 24 70
9 NC_PCI_AD<1> A19 AD1 BGA INT PU GNT0* D7 PCI_FW_GNT_L 6 70

BI OUT
(3 OF 6) MAKE_BASE=TRUE
9 BI NC_PCI_AD<2> A16 AD2 REQ1*/GPIO50 E16 PCI_REQ1_L IN 6 24 70
SB BOOT BIOS SELECT
B 9
9
BI
BI
NC_PCI_AD<3>
NC_PCI_AD<4>
B18
B15
AD3
AD4
OMIT
INT PU GNT1*/GPIO51
REQ2*/GPIO52
C16
A18
TP_SB_GPIO51
PCI_REQ2_L IN 6 24 70
1
B
9 NC_PCI_AD<5> A22 AD5 INT PU GNT2*/GPIO53 A17 TP_SB_GPIO53 R2415 I/F GNT0#
BI 1K
9 BI NC_PCI_AD<6> B17 AD6 REQ3*/GPIO54 C12 5%
1/20W
9 BI NC_PCI_AD<7> C17 AD7 INT PU GNT3*/GPIO55 D11 TP_SB_GPIO55 MF LPC 1
201
NC_PCI_AD<8> 2
9 BI F15 AD8
R2415 pull-down on GNT0#
9 BI NC_PCI_AD<9> A14 AD9 C/BE0* D16 NC_PCI_C_BE_L<0> BI 9 SPI 0
selects SPI ROM by default.
9 BI NC_PCI_AD<10> A13 AD10 C/BE1* C13 NC_PCI_C_BE_L<1> BI 9
9 NC_PCI_AD<11> C14 AD11 PCI C/BE2* D12 NC_PCI_C_BE_L<2> 9 NOTE: GNT0# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
BI BI
9 BI NC_PCI_AD<12> E13 AD12 C/BE3* C15 NC_PCI_C_BE_L<3> BI 9 SPI_CS1# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)
9 BI NC_PCI_AD<13> F14 AD13
9 BI NC_PCI_AD<14> E14 AD14 IRDY* F11 PCI_IRDY_L BI 6 24 70
IDE_RESET_L OUT 6 38
9 BI NC_PCI_AD<15> C9 AD15 PAR C8 NC_PCI_PAR BI 9 70
64 63 60
9 BI NC_PCI_AD<16> B11 AD16 PCIRST* C5 TP_PCI_RST_L OUT 6 9 26 25 23 22 21 19 16 13 8 7 6 PP3V3_A_S0
53 52 51 46 44 42 30 29 28 27
9 BI NC_PCI_AD<17> F13 AD17 DEVSEL* D14 PCI_DEVSEL_L BI 6 24 70
9 NC_PCI_AD<18> A11 AD18 PERR* A10 PCI_PERR_L 6 24 70 70 24 6 PCI_FRAME_L

RP2403 4 5 10K 4X0201
BI BI
70 9 NC_PCI_AD<19> D13 AD19 PLOCK* F12 PCI_LOCK_L 6 24 70 70 24 6 PCI_IRDY_L RP2402 3 6 10K 4X0201
BI BI
70 9 NC_PCI_AD<20> A12 AD20 SERR* A5 PCI_SERR_L 6 24 70 70 24 6 PCI_TRDY_L
RP2402 1 8 10K 4X0201
BI BI
9 NC_PCI_AD<21> B9 AD21 STOP* B14 PCI_STOP_L 6 24 70 70 24 6 PCI_STOP_L
RP2403 3 6 10K 4X0201
BI BI
9 NC_PCI_AD<22> E8 AD22 TRDY* E11 PCI_TRDY_L 6 24 70 70 24 6 PCI_SERR_L RP2400 3 6 10K 4X0201
BI BI
9 NC_PCI_AD<23> F10 AD23 FRAME* A15 PCI_FRAME_L 6 24 70 70 24 6 PCI_DEVSEL_L
RP2403 2 7 10K 4X0201
BI BI
9 NC_PCI_AD<24> D9 AD24 70 24 6 PCI_PERR_L
RP2402 2 7 10K 4X0201
BI
9 NC_PCI_AD<25> C10 AD25 PLTRST* AC22 PLT_RST_L 6 7 28 60 64 70 24 6 PCI_LOCK_L RP2403 1 8 10K 4X0201
BI OUT
9 BI NC_PCI_AD<26> D10 AD26 PCICLK C11 PCI_CLK33M_SB IN 6 30 71 RP2401 3 6 10K 4X0201
70 24 6 PCI_FW_REQ_L
9 BI NC_PCI_AD<27> A9 AD27 INT PU PME* C3 TP_PCI_PME_L
70 24 6 PCI_REQ1_L R2431 1 2 10K 201
SB PCI, PCIe, DMI, USB
9 NC_PCI_AD<28> A8 AD28
BI PCI_REQ2_L R2433 1 2
A 9
9
BI NC_PCI_AD<29>
NC_PCI_AD<30>
D8
B3
AD29
AD30
70 24 6
70 24 6 INT_PIRQA_L RP2400 4 5
10K
10K
201
4X0201
SYNC_MASTER=M70

A
BI
9 NC_PCI_AD<31> A3 AD31 70 24 6 INT_PIRQB_L
RP2401 4 5 10K 4X0201
BI
INTERRUPT I/F 70 24 6 INT_PIRQC_L
RP2401 2 7 10K 4X0201 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
70 24 6 BI INT_PIRQA_L A6 PIRQA* PIRQE*/GPIO2 A4 INT_PIRQE_L BI 6 24 70 RP2402 4 5 10K 4X0201 AGREES TO THE FOLLOWING
70 24 6 INT_PIRQD_L
70 24 6 BI INT_PIRQB_L B8 PIRQB* PIRQF*/GPIO3 A2 INT_PIRQF_L BI 6 24 70
70 24 6 INT_PIRQE_L
RP2400 2 7 10K 4X0201 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
70 24 6 BI INT_PIRQC_L C7 PIRQC* PIRQG*/GPIO4 E10 DVI_HOTPLUG_DET IN 6 61 62 Provide a pull-down on this GPIO if not used.
70 24 6 INT_PIRQF_L
RP2400 1 8 10K 4X0201 II NOT TO REPRODUCE OR COPY IT
70 24 6 BI INT_PIRQD_L B12 PIRQD* PIRQH*/GPIO5 F9 ODD_PWR_EN_L OUT 6 24 RP2401 1 8 10K 4X0201 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
24 6 ODD_PWR_EN_L
FireWire INT*
Changed pullups from 8.2K to 10K, since not critical. SIZE DRAWING NUMBER REV.
D 051-7230 B.0.0

NONE 24 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
64 63 60 53
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0
52 51 46 44 42 30 29 28 27 26
44 43 36 28 27 26 25 24 8 7 6 PP3V3_S5
72 60 58 57 56 51 49
1 NO_REBOOT_MODE 6 5 5 8
R2500 7 7 1
1K R2510 RP2501 RP2501 RP2500 RP2500
1 RP2500 RP2405 1K
5%
1 R2553 10K 10K 10K 10K
1/20W
MF
R2550 10K 10K 10K 5%
1/20W 5% 5% 5% 5%
201 100K 5% 5% 5% MF 1/32W 1/32W 1/32W 1/32W
2 5% 1/20W 1/32W 1/32W 201 4X0201 4X0201 4X0201 4X0201
2
1/20W
MF
2
MF
201 2
4X0201
2
4X0201 OMIT U2300 3 4 4 1
1 2 201
7 6 69 44 29 6 BI SMBUS_SB_SCL AD21 SMBCLK SB_ICH8M SATA0GP/GPIO21 W8 6 RSVD_EXTGPU_LVDS_EN
R2502
D 10K
5% RP2501
7
RP2500
6
RP2501
8
RP2502
8.2K
RP2502
8.2K
69 44 29 6 BI
BI
SMBUS_SB_SDA
NC_CLINK_WLAN_RESET_L
AA17
AA16
SMBDATA
LINKALERT*
BGA
(4 OF 6)
SATA1GP/GPIO19
SATA2GP/GPIO36
AC4
AD4
6 SATA_B_DET_L
6 SB_GPIO36
D
1/20W
MF
10K 10K 10K 5% 5% 69 44 6 SMBUS_SB_ME_SCL AB16 SMLINK0 SATA3GP/GPIO37 AB7 SB_CRT_TVOUT_MUX_L 6 63
5% 5% 5% 1/32W 1/32W BI SMB SATA GPIO OUT
201
2 1/32W 1/32W 1/32W 4X0201 4X0201 69 44 6 SMBUS_SB_ME_SDA AC16 SMLINK1
4X0201 4X0201 4X0201 BI Y7 SB_CLK14P3M_TIMER
2 3 CLK14 IN 6 30 71
2 3 1
25 6 IN PM_RI_L AD15 RI* CLK48 E5 SB_CLK48M_USBCTLR IN 6 30 71
CLOCKS
43 41 6 OUT PM_SUS_STAT_L D4 SUS_STAT*/LPCPD* SUSCLK B5 SUS_CLK_SB OUT 6 42
41 28 6 IN PM_SYSRST_L AC13 SYS_RESET*

SLP_S3* AB17 PM_SLP_S3_L OUT 6 7 36 37 41 42 51 55
16 6 IN PM_BMBUSY_L AD7 BMBUSY*/GPIO0 SLP_S4* AD20 TP_PM_SLP_S4_L

SLP_S5* W16 PM_SLP_S5_L OUT 6 41 42
43 25 6 IN FRANKCARD_GPIO AA18 SMBALERT*/GPIO11
S4_STATE*/GPIO26 AC21 PM_S4_STATE_L OUT 6 36 41 58
30 29 6 OUT PM_STPPCI_L AD19 STP_PCI*/GPIO15
30 29 6 OUT PM_STPCPU_L AC15 STP_CPU*/GPIO25 PWROK AB19 PM_SB_PWROK IN 6 9 25 28
NOTE: DPRSLPVR HAS INT 20K PD ENABLED

43 41 6 BI PM_CLKRUN_L AA7 CLKRUN*/GPIO32 DPRSLPVR/GPIO16 AA9 PM_DPRSLPVR OUT 6 16 52 66
AT BOOT/RESET FOR STRAPPING FUNCTION
36 7 6 IN PCIE_WAKE_L AD17 WAKE* BATLOW* AB24 PM_BATLOW_L IN 6 25 41
PM_LAN_ENABLE must remain deasseted
43 41 6 BI INT_SERIRQ W9 SERIRQ
until VccCL3_3, VccLAN3_3 and VccLAN1_05
6 PM_THRM_L AB8 THRM* SYS GPIO POWER MGT INT PU PWRBTN* D5 PM_PWRBTN_L IN 6 41
have been up for at least 1ms.
28 9 6 IN VR_PWRGD_CK505 AB14 VRMPWRGD LAN_RST* W13 PM_LAN_ENABLE IN 6 41
TP_SB_TP7 AC19 TP7 RSMRST* AB21 PM_RSMRST_L IN 6 41
25 6 IN PCI_PME_FW_L AA5 TACH1/GPIO1 INT PU CK_PWRGD F7 CLK_PWRGD OUT 6 29

1 1
TP_SB_GPIO6 Y5 TACH2/GPIO6 INT PU See note below
R2524 R2525
100K 10K
41 6 IN SMC_RUNTIME_SCI_L AB5 TACH3/GPIO7 INT PU CLPWROK C4 PM_SB_PWROK IN 6 9 25 28 5% 5%
1/20W 1/20W
41 13 7 6 IN SMC_WAKE_SCI_L W12 GPIO8 MF MF
201
GPIO SLP_M* AB18 TP_PM_SLP_M_L 2 2 201
C 6
NC_SB_GPIO17
SB_GPIO18
Y6
AD6
TACH0/GPIO17
GPIO18
INT PU
CL_CLK0 C19 CLINK_NB_CLK 6 16 70

PP3V3_A_S0 53 60 63 64
6 7 8 13 16 19 21 22 23 24 25
26 27 28 29 30 42 44 46 51 52
C
BI
TP_SB_GPIO20 AC7 GPIO20 INT PD CL_CLK1 W14 NC_CLINK_WLAN_CLK BI 1
62 6 SST8051_UPDATE_L Y8 SCLOCK/GPIO22 R2526
OUT 3.24K
NC_SB_GPIO27 AD22 QRT_STATE0/GPIO27 CL_DATA0 D20 CLINK_NB_DATA BI 6 16 70 1%
1/20W
25 6 FWH_MFG_MODE Y14 QRT_STATE1/GPIO28 CL_DATA1 AA14 NC_CLINK_WLAN_DATA BI MF
NC_SB_SATA_CLKREQ_L AB9 SATACLKREQ*/GPIO35 CONTOLLER LINK 2 201

6 SB_SLOAD AC5 SLOAD/GPIO38 CL_VREF0 E18 70 6 SB_CLINK_VREF0
62 6 OUT SST8051_SW_RESET_L AB6 SDATAOUT0/GPIO39 CL_VREF1 AA15 SB_CLINK_VREF1
TMDS_SW_RESET_L AC6 SDATAOUT1/GPIO48 1
61 6 OUT
INT PU CL_RST* Y16 CLINK_NB_RESET_L 6 16 70 C2500 1 R2527
OUT 453
6 SB_SPKR AD2 SPKR INT PD
0.1UF 1%
10%
MEM_LED/GPIO24 AD23 ARB_DETECT_L BI 6 25 6.3V 1/20W
X5R
2 MF
16 6 NB_SB_SYNC_L AA8 MCH_SYNC*
IN MISC 201 2 201
TP_SB_TP3 AD16 TP3 INT PU
WOL_EN/GPIO9 AC18 6 WOL_EN
Test access required
for XOR chain testing. 1
R2523
100K
NOTE: ICH CLPWROK input must be PWRGD signal for 5%
1/20W PP3V3_S5 6 7 8 24 25 26 27 28 36 43 44
PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M, MF 49 51 56 57 58 60 72
201
PP1V05_S0M, PP0V9_S3M and PP0V9_S0M. 2
1
If ME/AMT is not used, short CLPWROK to PWROK.
R2528
3.24K
1%
1/20W
MF
2 201
B C2501 1
1
R2529 B
0.1UF 453
1%
10%
6.3V 1/20W
X5R
2 MF
201
201 2
LAYOUT NOTE:
PLACE R2511-16 WHERE PHYSICALLY ACCESSIBLE R2531 53 60 63 64
PP3V3_A_S0 6 7 8 13 16 19 21 22 23 24 25
10K 26 27 28 29 30 42 44 46 51 52
25 6 PCI_PME_FW_L 1 2
1%
44 43 36 28 27 26 25 24 8 7 6 PP3V3_S5 1/20W
72 60 58 57 56 51 49 MF
201
1 1
R2511 1 R2515
10K R2514 10K R2536 PP3V3_S5 6 7 8 24 25 26 27 28 36 43 44
5% 47K 5% 10K 49 51 56 57 58 60 72
1/20W 5% 1/20W 25 6 PM_RI_L 1 2
MF 1/20W MF
201 MF 201 1%
2 201
2 1/20W
2 MF
FWH_MFG_MODE 6 25 201 R2544
8.2K
FRANKCARD_GPIO 6 25 43 41 25 6 PM_BATLOW_L 1 2
ARB_DETECT_L 6 25 5%
1/20W
ARB_ONLY R2545 MF
201
SB Pwr Mgt, GPIO, Clink
1 10K
R2516 LAN_PHYPC 1 2
A 0
5%
1/20W
23 6
1%
1/20W
SYNC_MASTER=M70

A
MF MF R2598
201 201 10K
2 23 6 SB_GPIO10_CL1 1 2 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1% AGREES TO THE FOLLOWING
1/20W
R2546 MF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
100K 201
43 23 6 BOOTROM_OVR_EN_L 1 2 II NOT TO REPRODUCE OR COPY IT
1% III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/20W
MF
201 SIZE DRAWING NUMBER REV.
D 051-7230 B.0.0

NONE 25 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D U2300 6 uA S0-G3 27 23 8 7 6
72 59 57 44 43 42 41 40 39 28
PP3V42_G3H W15 VCCRTC U2300 K12 PP1V05_S0 6 7 8 10 11 12 1130 mA
13 14 18
19 21 23 26 27 30 42 54 72
D
AA1 SB_ICH8M
BGA
L7 SB_ICH8M K13
AA2 L8 1 mA 72 27 6 PP5V_S0_SB_V5REF D15 BGA K14
(5 OF 6)
AA6 M11 R6 V5REF (6 OF 6) K15
OMIT
AB20 M12 L12
AB3 M13 1 mA S0-S5 72 27 6 PP5V_S5_SB_V5REF_SUS J6 V5REF_SUS L15
AB4 M16 OMIT M14
AC11 M19 657 mA 72 27 26 24 23 6 PP1V5_S0_SB_VCC1_5_B H17 M15
VCC1_05
AC14 M20 H18 N15
AC17 M23 J17 VCCCORE P14
AC2 M24 J18 P15
AC20 N11 K17 R10
AC23 N12 K18 R12
VCC1_5_B
AC8 N13 L17 R15
AD5 N14 L18 VCCA3GP T10
B10 N16 M17 T11
B13 N2 M18 T12
B16 N21 N17 T13
B19 N22 N18 T14
B22 N5 P17 T15
B24 P10 P18
B4 P11 R17 VCCDMIPLL P24 PP1V5_S0_SB_VCCDMIPLL 6 27 72 23 mA
B7 P12 R18
D17 P13 T18 U17 PP1V25_S0 6 7 8 16 18 19 21 50 mA
27 51
57 72
D3 P16 VCC_DMI U18
E1 P19 47 mA 72 27 6 PP1V5_S0_SB_VCCSATAPLL AC1 VCCSATAPLL
C E12
E15
P20
P23 11 8 7 6
72 54 27 26 22 12
PP1V5_S0 G14 V_CPU_IO
U15
U16
PP1V05_S0 6 7 8 10 11 12 13114mA
18 19 21 23 26 27 30 42 54 72 C
E21 P6 G15 RINGPCI
42 44 46 51 52 53 60 63 64
24 25 26
E22 P9 G10 PP3V3_A_S0 6 7 8 13 16
19 21 22 23
72 54 27 28 29 30
E4 R11 11 8 7 6 PP1V5_S0 G6 G11
27 26 22 12
E6 R13 H5 USBCORE G9
E9 R14 H6 VCCPPCI H10
(VCC1_5_A total)
F16 R16 H11
F19 R21 M7 H12
F20 R22 M8 RINGIDE 44 46 51 52
(VCC3_3 total)
24 25 26 27
1080 mA J5 PP3V3_A_S0 6 7 8 13 16
VCC1_5_A
F23 R9 19 21
28 29
22
30
23
42
J7
VCC3_3
53 60 63 64
F24 T16 11 8 7 6 PP1V5_S0 N7
72 54 27 26 22 12 K5 442 mA
F5 T17 P7 ARX VCCPIDE K6
G1 T19 R7
K7
G12 T2
L6
G21 T20 11 8 7 6 PP1V5_S0 N8
72 54 27 26 22 12 44 46 51 52
24 25 26 27
G22 T23 P8 ATX U7 PP3V3_A_S0 6 7 8 13 16
19 21 22 23
28 29 30 42
G4 T24 R8 VCCPCORE U8 53 60 63 64
H14 T5 V8
T6
H19 T7 SATA
44 46
24 25
51
26
52
27
U6 VCCSATABG U2 PP3V3_A_S0 6 7 8 13 16
H20 T8 19 21
28 29
22
30
23
42
53 60 63 64
H23 T9 VCC3GBG V24 PP3V3_A_S0 6 7 8 13 16
V10 19 21
24 25
22
26
23
53 60 63 64
H24 U10 RINGCORE 27 28 29 30 42 44 46 51 52 NOTE:
VSS V9 51 52 53 60 63 64
H7 VSS U11 VCCHDA AA10 PP3V3_A_S0 6 7 8 13 16 19 21 32
22 mA
23 VccHDA and VccSusHDA can be 1.5V or 3.3V
24 25 26 27 28 29 30 42 44 46
H8 U12 W17 RINGCPU depending on VIO of HD Audio interface.
VCCSUSHDA Y10 PP3V3_S5 6 7 8 24 25 26 27 11 mA43S0,
28 36 44
H9 U13 49 51 56 57 58 60 172mA S3-S5
Current figures provided assume 1.5V.
J1 U14 G8 NC_VCCSUS1_05_INTERNAL_REG1
B J11 U21
10 mA 12 11 8 7 6
72 54 27 26 22
PP1V5_S0 G5 VCCUSBPLL VCCSUS1_05 V16 NC_VCCSUS1_05_INTERNAL_REG2 B
J12 U22
VCCSUS1_5
NC_VCCLAN1_05_INTERNAL_REG1 G13
J13 U3 VCCLAN1_05 USB G7 NC_VCCSUS1_5_INTERNAL_REG1
NC_VCCLAN1_05_INTERNAL_REG2 H13
J14 U9
J15 V11 V15 NC_VCCSUS1_5_INTERNAL_REG2
51 46 44 42 30 29
2219
21 mA
19 16S0,
13 8 7 6 PP3V3_A_S0 H15 RINGSUSEXT
J16 V17 28 27
63 26 M1
mA63
64
25 24 23
& WOL
60 53 52 VCCCL3_3
H16 60 72
43 44 49
J21 V20 F6 PP3V3_S5 6 7 8 24 25
VCCAUBG 26 27 28 36
J22 V23 51 56 57 58
43 44 49 51
23 mA 12 11 8 7 6 PP1V5_S0 A21 VCCGLANPLL J10 PP3V3_S5 6 7 8 24 25
J4 V3 72 54 27 26 22 26 27
56 57
28
58
36
60
J8 72
K11 V6 80 mA 26 24 23 6 PP1V5_S0_SB_VCC1_5_B F17
72 27 J9
K16 V7 G17
(VCCSUS3_3 total)
VCCGLAN1_5
K10
K19 W1 G18
K8
K20 W2
VCCSUS3_3
VCCPUSB K9
K23 W5 52 51 46 44 42
1 mA 19 16 13 8 7 6 PP3V3_A_S0 C24 VCCGLAN3_3 L10
K24 Y12 30 29 28 27 26 25 24 23 22 21
64 63 60 53
117 mA S0,
L9
L1 Y15 44 mA S3-S5
M10
L11 Y18 NC_VCCCL1_05_INTERNAL_REG E17 VCCCL1_05
M9
L13 Y21
N10
L14 Y24
6 VCCCL1_5V F18 VCCCL1_5 N9
L16 Y3
72
43 44 49 51
L21 Y4 PLACE CLOSE TO F18 V12 PP3V3_S5 6 7 8 24 25
OMIT 53 52 51 46 26 27 28 36
28 27 26 25 56 57 58 60
L22 Y9 C2600 1
16 13 8 7 6 PP3V3_A_S0 G16 VCCLAN3_3 VCCPSUS V13
24 23 22 21 19 19 mA S0,
L4 1uF 44 42 30 29
V14
64 63 60
A1 10%
6.3V 51 mA M1 & WOL
2
A24 CERM
402
SB Power & Ground
VSS_NCTF AD1
A AD24
SYNC_MASTER=M70

A
D 051-7230 B.0.0

NONE 26 73
Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
64 63 60 53 52 51
44 42 30 29 28 27 26 25 24
22 21 19 16 13 8 7 6 PP3V3_A_S0
8
PP5V_S0
23
46
ICH V5REF BYPASS ICH VCCSUS3_3 BYPASS
6 PLACEMENT NOTE:
7
22
(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT) L2702 MAY HAVE CHANGE TO 1.0UH PART ICH CORE/VCC1_05 BYPASS (ICH SUSPEND 3.3V PWR)
40 PLACE CAPS AT EDGE OF SB
43 2 3 (ICH CORE 1.05V PWR)
47
51 R2702 D2702 L2702 VOLTAGE=1.5V PLACE C2718,C2702 NEAR SB K12..T15 44 43 36 28 27 26 25 24 8 7 6
72 60 58 57 56 51 49
PP3V3_S5
52 10UH-100MA MIN_LINE_WIDTH=0.5MM
53
100 2 HN2S02JE MIN_NECK_WIDTH=0.25MM
63
SOT-665 PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21
NC
72
1/20W 72 54 27 26 22 12 11 8 7 6 PP1V5_S0 1 2 PP1V5_S0_SB_VCCSATAPLL 23 26 27 30 42 54 72
MF 4
201 0805
1 5% OMIT PLACEMENT NOTE:
1 C2735 1 C2717 1 C2718 1 C2702 CRITICAL
1
1 C2731
PP5V_S0_SB_V5REF 6 26 72
C2716 PLACEHOLDER PLACE CAP NEAR PINS 0.1UF
VOLTAGE=5V 10UF 0.1UF 0.022UF 0.022UF 330UF FOR 270UF V12..V14 AND F6 10%
6.3V
MIN_LINE_WIDTH=0.3MM 20% 10% 10% 10% 20% 2 X5R
OMIT MIN_NECK_WIDTH=0.25MM PLACEMENT NOTE: 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 2.5V 201
POLY
1 C2703 PLACE < 2.54MM OF SB ON SECONDARY OR 603 201 201 201 CASE-C2-HF
D 1UF
10% PLACEMENT NOTE: 3.56MM ON PRIMARY NEAR PIN AC1 D
2 6.3V
CERM PLACE C2703 < 2.54MM OF PINS D15,R6 OF SB
402
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
ICH VCC_PAUX/VCCLAN3_3 BYPASS ICH USB/VCCSUS3_3 BYPASS
ICH V5REF_SUS BYPASS
(ICH LAN I/F BUFFER 3.3V PWR) (ICH SUSPEND USB 3.3V PWR)
(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)
64 63 60 53
44 43 36 28 27 26 25 24 8 7 6 PP3V3_S5 25 24 23 22 21 19 16 13 8 7 6PP3V3_A_S0 44 43 36 28 27 26 25 24 8 7 6 PP3V3_S5
55
51
72 60 58 57 56 51 49 ICH VCC3_3 BYPASS 52 51 46 44 42 30 29 28 27 26 72 60 58 57 56 51 49
8
6 PP5V_S5 (ICH IO BUFFER 3.3V PWR)
7
39
54
56
VCCPCORE DOES NOT REQUIRE DECOUPLING PER INTEL RECOMMENDATIONS PLACEMENT NOTE: 1 C2719
PLACE CAP UNDER SB NEAR PIN G16 0.1UF
2
58
72 R2701 1
D2702 10%
6.3V 1 C2734 1 C2733
10 2 X5R PLACEMENT NOTE:
2 HN2S02JE 201 0.1UF 0.022UF
1/20W SOT-665 PLACE CAPS NEAR PINS
NC
MF 10% 10%
201 6.3V 6.3V
5 J10..N9 2 X5R 2 X5R
1
5%
201 201
PP5V_S5_SB_V5REF_SUS 6 26 72
VOLTAGE=5V
ICH VCCHDA BYPASS
1 C2704 COMBINED VCC1_5_A, ARX AND ATX DECOUPLING PER INTEL RECOMMENDATIONS (ICH INTEL HDA CORE 3.3V/1.5V PWR)
0.1UF PLACEMENT NOTE:
10% ICH VCC1_5A/ARX/ATX BYPASS
6.3V 64 63 60 53
PP3V3_A_S0
2 X5R PLACE C2704 < 2.54MM OF PIN J6 OF SB 25 24 23 22 21 19 16 13 8 7 6
201 (ICH LOGIC&IO/[ARX]/[ATX] 1.5V PWR) 52 51 46 44 42 30 29 28 27 26
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
72 54 27 26 22 12 11 8 7 6 PP1V5_S0 PLACEMENT NOTE:
72 54 27 26 22 12 11 8 7 6 PP1V5_S0 PLACE < 2.54MM OF SB ON SECONDARY 1 C2721
OR 3.56MM ON PRIMARY NEAR PIN AA10 0.1UF
10%
26 22 12 11 8 7 6 PP1V5_S0 72 54 27 26 22 12 11 8 7 6 PP1V5_S0 2 6.3V
X5R
72 54 27 CRITICAL 201
ICH VCCA3GP(VCC1_5_B BYPASS
L2700
C FERR-330-OHM-1.5A (ICH IO,LOGIC 1.5V PWR)
0805-1 PLACEMENT NOTE:
1 C2710
0.1UF
C
PLACE CAP NEAR PINS 10%
1 2 PP1V5_S0_SB_VCC1_5_B 6.3V
6 23 24 26 27 72 2 X5R
VOLTAGE=1.5V T6..U6, N7..R7, N8..R8 OF SB 201
MIN_LINE_WIDTH=0.5MM ICH V_CPU_IO BYPASS
L2700 MAY HAVE CHANGE TO 0.5UH PART MIN_NECK_WIDTH=0.25MM
OMIT OMIT (ICH CPU I/O 1.05V PWR)
CRITICAL
1
C2700 1 C2705 1 C2706 PP1V05_S0
220UF 10UF 10UF 21 19 18 14 13 12 11 10 8 7 6
72 54 42 30 27 26 23
20% 20% 20% ICH USB CORE/VCC1_5_A BYPASS
6.3V 6.3V
2 2.5V 2 X5R 2 X5R
POLY PLACEMENT NOTE: (ICH USB CORE 1.5V PWR)
CASE-B2-HF 603 603
PLACE NEAR PINS U15,U16 OF SB PP1V5_S0
72 54 27 26 22 12 11 8 7 6
PLACEMENT NOTE:
PLACE C2700 & C2705-07 < 2.54MM OF SB
ON SECONDARY SIDE OR 3.56MM ON PRIMARY PLACEMENT NOTE:
DISTRIBUTED BETWEEN H17..T18,
1 C2723 1 C2722 1 C2724 PLACE < 2.54MM OF SB ON SECONDARY OR
1 C2712
0.1UF 0.1UF 4.7UF 0.1UF
ALSO SHARE WITH F17,G17,G18 10% 10% 20% 3.56MM ON PRIMARY NEAR PINS G6..H6 10%
2 6.3V
6.3V 6.3V 6.3V
2 X5R 2 X5R CERM 2 X5R
201 201 603 201
VOLTAGE=1.5V
72
54 27 26 22 12 11 8 7 6 PP1V5_S0
1
C2732 ICH IDE/VCC3_3 BYPASS
PLACEMENT NOTE: 2.2uF (ICH IDE I/O 3.3V PWR)
20%
6.3V
PLACE CAPS < 2.54MM OF SB ON SECONDARY 2 CERM1 ICH VCCUSBPLL BYPASS 64 63 60 53
PP3V3_A_S0 VCCCL3_3 DOES NOT REQUIRE DECOUPLING PER INTEL RECOMMENDATIONS
603 25 24 23 22 21 19 16 13 8 7 6
OR 3.56MM ON PRIMARY NEAR PIN A21 (ICH USB PLL 1.5V PWR) 52 51 46 44 42 30 29 28 27 26
72 54 27 26 22 12 11 8 7 6 PP1V5_S0 PLACEMENT NOTE: 1 C2725

B PLACEMENT NOTE:
1 C2715
0.1UF
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PINS J5..L6
0.1UF
10%
6.3V
B
10% 2 X5R
PLACE C2715 NEAR PIN G5 OF SB 6.3V 201
2 X5R
201
64 63 60 53
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0
52 51 46 44 42 30 29 28 27 26
PLACEMENT NOTE: ICH PCI/VCC3_3 BYPASS

ICH VCC3_3/VCCHDA BYPASS
PLACE < 2.54MM OF SB ON SECONDARY 1 C2738 (ICH PCI I/O 3.3V PWR)
(ICH INTEL HDA CORE 3.3V PWR)
OR 3.56MM ON PRIMARY NEAR PIN U2 0.1UF
10% 64 63 60 53
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0
2 6.3V
X5R
52 51 46 44 42 30 29 28 27 26 44 43 36 28 27 26 25 24 8 7 6 PP3V3_S5
72 60 58 57 56 51 49
201
PLACEMENT NOTE:
PLACEMENT NOTE: 1 C2726 1 C2727 1 C2728 PLACE < 2.54MM OF SB ON SECONDARY 1 C2741
DISTRIBUTE IN PCI SECTION OF SB 0.1UF 0.1UF 0.1UF
27 26 22 12 11 8 7 6 PP1V5_S0 10% 10% 10% OR 3.56MM ON PRIMARY NEAR PIN Y10 0.1UF
6.3V 6.3V 6.3V 10%
72 54 NEAR PINS G9..H12 2 X5R 2 X5R 2 X5R
L2703 ICH VCCDMIPLL BYPASS 201 201 201
6.3V
2 X5R
R2700 1.0UH-0.5A-0.675A (ICH DMI PLL 1.5V PWR) 201
72 6 1
1 PP1V5_S0_SB_VCCDMIPLL_F
2 1 2 PP1V5_S0_SB_VCCDMIPLL 6 26 72
VOLTAGE=1.5V 1007 VOLTAGE=1.5V
5% MIN_LINE_WIDTH=0.5MM MIN_LINE_WIDTH=0.5MM
1/20W MIN_NECK_WIDTH=0.20MM OMIT MIN_NECK_WIDTH=0.2MM
MF
201 1 C2701 1 C2708
0.01UF 10UF
PLACEMENT NOTE: 10% 20%
2 10V
X5R 2 6.3V
X5R
PLACE CAPS < 2.54MM OF SB ON 201 603
SECONDARY SIDE OR 3.56MM ON PRIMARY NEAR PIN P24 ICH VCCRTC BYPASS
(ICH RTC 3.3V PWR)
SB Decoupling
PP3V42_G3H PP1V5_S0_SB_VCC1_5_B PP1V5_S0_SB_VCC1_5_B SYNC_MASTER=M70 SYNC_DATE=02/01/2007
A 43 42 41 40 39 28 26 23 8 7 6
72 59 57 44
72 27 26 24 23 6
MAKE_BASE=TRUE
6 23 24 26 27 72

A
64 63 60 53
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0 72 57 51 26 21 19 18 16 8 7 6 PP1V25_S0
52 51 46 44 42 30 29 28 27 26 C2744 1 C2729 1 1 C2730 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1UF 0.1UF 0.1UF AGREES TO THE FOLLOWING
10% 10% 10%
10V 2 6.3V 2 2 6.3V I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
PLACEMENT NOTE: PLACEMENT NOTE: X5R X5R X5R
402-1 201 201 II NOT TO REPRODUCE OR COPY IT
PLACE CAP < 2.54MM OF SB ON SECONDARY 1 C2737 PLACE < 2.54MM OF SB ON SECONDARY 1 C2739 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
OR 3.56MM ON PRIMARY NEAR PIN V24 0.1UF OR 3.56MM ON PRIMARY NEAR PIN U17,U18 1UF
10% 10%
6.3V 10V
2 X5R 2 X5R SIZE DRAWING NUMBER REV.
201 402-1 PLACEMENT NOTE:
PLACE CAPS NEAR PIN W15 OF SB D 051-7230 B.0.0

NONE 27 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP3V42_G3H 6 7 8 23 26 27 28 39 40 41 42
43 44 57 59 72
42 41 40 39 28 27 26 23 8 7 6
72 59 57 44 43
PP3V42_G3H Platform Reset Connections
Unbuffered R2886
PLT_RST_L 1
100 2 NB_RESET_L
64 60 28 24 7 6 IN 6 16
MAKE_BASE=TRUE
D
5%
1/20W
MF
D
201
R2800 R2887
20K 1
0 2 TMDS_HW_RESET_L 6 61 62
1 2 SB_RTC_RST_L OUT 6 23
5%
5% OMIT 1/20W
1/20W MF
MF
201
1 C2805 R2885 201
1
1UF
10% 0 AIRPORT_RST_L 6
R2806 2 6.3V
CERM
1 2 7 36
1M 402 5%
1/20W
5%
1/20W MF
MF 201
2 201
PLT_RST_L 6 7 24 28 60 64
SB_SM_INTRUDER_L OUT 6 23
64 63 60 53
25 24 23 22 21 19 16 13 8 7 6
52 51 46 44 42 30 29 28 27 26
PP3V3_A_S0 PLT_RST_L 6 7 24 28 60 64
Buffered
CRITICAL
5 TC7SZ08AFEF
2 SOT665 R2881
A
4 PLT_RST_BUF_L 1
0 2 DEBUG_RESET_L
U2880Y 6 6 43
1 5% Linda Card represents 3 loads
B
1
R2880
1/20W
MF R2883
3 201 100
C2880 1 5%
100K 1 2 SMC_LRESET_L 6 41
0.1UF 1/20W 5%
10% MF 1/20W
6.3V 2 MF
X5R 2 201
SB RTC Crystal Circuit 201 201
C R2810 C2808
10PF
C
SB_RTC_X1 1
0 2 6 SB_RTC_X1_R 1 2
23 6
5%
1/20W 5%
25V 49 44 43 36 27 26 25 24 8 7 6 PP3V3_S5
R28091 MF
201
CRITICAL NPO
72 60 58 57 56 51
10M Y2800 1 201

5%
1/20W 32.768K R28971
3.2X1.5X.6-SM
C2809 10K
10 13
MF1
201 2 2 5%
197S0187 10PF 1/20W
MF
SB_RTC_X2 1 2
R2896 201
7
23 6
I59 2
1K
6
5%
25V IN XDP_DBRESET_L 2 1 PM_SYSRST_L PM_SYSRST_L OUT 6 25 28 41
NPO MAKE_BASE=TRUE
201 5%
1/20W
OMIT
1
MF
201 R2898
100K
This part is never stuffed,1/16W
5%
it provides a set of pads MF-LF
Silk: "SYS RST"
402 2
on the board to short or
to solder a reset button. Place R2898 pads on bottom side
near board edge
B 64 63 60 53 52
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0 B
51 46 44 42 30 29 28 27 26
C2811 1
0.1UF 64 63 60 53
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0
10% 52 51 46 44 42 30 29 28 27 26
6.3V 2
X5R
201
5 CRITICAL C2807 1 1
0.1UF
10%
R2811
VCC 6.3V 2 1.8K
X5R 5%
VR_PWRGD_CK505 4
U2803 A 2 201 1/20W
MF
25 9 6 OUT Y TC7SH00FEF 2 201
SON B 1 VR_PWRGD_CK505_L CRITICAL
MAKE_BASE=TRUE IN 6 28 52 TC7SZ08AFEF 5
GND SOT665 2 VR_PWRGOOD_DELAYIN 6 9 16 52
A
R28031 3 25 9 6 OUT PM_SB_PWROK 4
Y U2801 1
100K R2812 B ALL_SYS_PWRGD IN 6 41 51 52
5%
1/20W 1
MF 3
201 2 10K
5%
1/20W
MF
201 2
52 28 6 OUT
VR_PWRGD_CK505_L
SB Misc
SYNC_MASTER=M70 SYNC_DATE=01/09/2007
A
D 051-7230 B.0.0

NONE 28 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP3V3_A_S0 53 60 63 64
6 7 8 13 16 19 21 22 23 24 25
26 27 28 29 30 42 44 46 51 52
Silego recommend to remove L2903,R2900,C2907,C2910
R2901,L2902,C2916,C2911,C2914 and R2902
1 C2909
0.1UF
10%
2 6.3V
X5R
201
D D
CRITICAL
L2901
53 52 51 46 44 42 30 29
19 16 13 8 7 6 PP3V3_A_S0 FERR-120-OHM-1.5A
28 27 26 25 24 23 22 21
64 63 60 1 2 PP3V3_S0_CK505_VDD_CPU_SRC
0402-LF MIN_LINE_WIDTH=0.5mm
OMIT MIN_NECK_WIDTH=0.2mm OMIT
C2900 1 VOLTAGE=3.3V
C2901 1 1 C2902 1 C2903 1 C2904 1 C2905 1 C2906
1 C2912 1 C2913
0.1UF 0.1UF
1UF 10UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 10% 10%
10%
6.3V 2
20%
6.3V 2
10%
6.3V
10%
6.3V
10%
6.3V
10%
6.3V
10%
6.3V 2 6.3V
X5R 2 6.3V
X5R
CERM X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 201 201
402 603 201 201 201 201 201
1 C2908 1 C2915
0.1UF 0.1UF
10% 10%
2 6.3V
X5R 2 6.3V
X5R
201 201
CRITICAL
Y2901
43
61
67
49
12
17
28
35
3
SM-2.5X2.0MM
14.318MHZ-35PPF-20PF (EACH POWER PIN PLACED ONE 0.1UF)
VDD_PCI
VDD_48
VDD_REF
VDD_CPU
VDD_SRC
1 3
(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)
2 4
1 C2989 1 C2990
C 5%
20PF 20PF
5%
C
25V
2 NP0-C0G 2 25V
NP0-C0G PCI_STOP* 56 PM_STPPCI_L IN 6 25 30 (FROM ICH8M GPIO15 STPPCI* )
201 201 U2900 CPU_STOP* 55 PM_STPCPU_L IN 6 25 30 (FROM ICH8M GPIO25 STPCPU* )
38 SLG2AP101
VDD_A QFN CPU_0* 44 FSB_CLK_CPU_N 6 10 30 71
39 OUT
VSS_A
CPU_0 45 FSB_CLK_CPU_P OUT 6 10 30 71 (CPU HOST 133/167MHZ)
CK505_XTAL_IN 51 XTAL_IN
CPU_1_MCH* 41 FSB_CLK_NB_N OUT 6 14 30 71
6 CK505_XTAL_OUT 50 XTAL_OUT
CPU_1_MCH 42 FSB_CLK_NB_P OUT 6 14 30 71 (GMCH HOST 133/167MHZ)
64 63 60 53
PP3V3_A_S0 36 XDP_CLK_N
25 24 23 22 21 19 16 13 8 7 6
52 51 46 44 42 30 29 28 27 26 CK505_FSB_TEST_MODE 8 FS_B/TEST_MODE CPU_ITP*/SRC_10* OUT 6 7 13 30 66 71
30 6 IN
CPU_ITP/SRC_10 37 XDP_CLK_P OUT 6 7 13 30 66 71 (ITP HOST 133/167MHZ)
1
R2903(FW PCI 33MHZ) 9 OUT NC_CK505_PCI1_CLK 57 PCI_1 SRC_0*/LCD_CLK* 11 NB_CLK100M_DPLLSS_N OUT 6 9 16 30 71
10K
5%
1/20W
(TPM LPC 33MHZ) 9 OUT NC_CK505_PCI2_CLK 58 PCI_2 SRC_0/LCD_CLK 10 NB_CLK100M_DPLLSS_P OUT 6 9 16 30 71 (GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)
MF (SMC LPC 33MHZ) 71 30 6 OUT CK505_PCI3_CLK 63 PCI_3
2 201 SRC_1* 14 NC_CK505_SRC1_N OUT 9
(PCI SLOT) NC_CK505_PCI4_CLK 64 PCI_4
(PORT80 LPC 33MHZ)
9 OUT
BI CK505_PCI5_FCTSEL1 65 PCI_5/FCT_SEL SRC_1 13 NC_CK505_SRC1_P OUT 9 (SLOT F - GPU PCI-E 100 MHZ )
(NO INT PD) CLKREQ_1* 9 NC_CK505_SRC_CLKREQ1_L IN 9
CK505_PCIF0_CLK 68 PCIF_0/ITP_EN (INT PU)

30 6 OUT
(NO INT PU) SRC_2* 16 SB_CLK100M_DMI_N OUT 6 24 30 71
(ICH8M PCI 33MHZ) CK505_PCIF1_CLK 1 PCIF_1
30 6
71 OUT
SRC_2 15 SB_CLK100M_DMI_P OUT 6 24 30 71 (ICH8M DMI 100 MHZ )
(PULL UP PIN 68 TO ENABLE ITP HOST CLK)
IN SMBUS_SB_SCL 47 SCL
(ICH SM BUS) SRC_3* 19 NC_CK505_SRC3_N OUT 9
SMBUS_SB_SDA 48 SDA
69 44 25 6 BI
SRC_3 18 NC_CK505_SRC3_P OUT 9 (SLOT D - 4 LANE PCI-E FOR EXPRESSCARD)
CLKREQ_3* 59 NC_CK505_SRC_CLKREQ3_L IN 9
(INT PU)
SRC_4* 22 NC_CK505_SRC4_N OUT 9
SRC_4 21 NC_CK505_SRC4_P 9 (ICH SATA 100 MHZ)

B 5 VSS_48 CLKREQ_4*
(INT PU)
20 NC_CK505_SRC_CLKREQ4_L
OUT
IN 9 (FROM ICH8M GPIO35) B
46 VSS_CPU SRC_5* 24 NB_CLK100M_PCIE_N OUT 6 16 30 71
62 SRC_5 23 NB_CLK100M_PCIE_P OUT 6 16 30 71 (GMCH G_CLKIN 100 MHZ )

VSS_PCI CLKREQ_5* 60 NB_CLKREQ_L IN 6 16 (FROM GMCH CLK_REQ*)
66 (INT PU)
SRC_6* 27 PCIE_CLK100M_MINI_N OUT 6 30 36 71
52 VSS_REF
SRC_6 26 PCIE_CLK100M_MINI_P OUT 6 30 36 71 (WIRELESS PCI-E 100 MHZ )
31 VSS_SRC CLKREQ_6* 25 CK505_SRC_CLKREQ6_L IN 6 7 36
(INT PU)
SRC_7* 30 NC_CK505_SRC7_N
69 THRM_PAD
SRC_7 29 NC_CK505_SRC7_P
OUT
OUT
9
9
(DB400 SRC )
CLKREQ_7* 40 NC_CK505_PGMODE 9
(INT PU)
SRC_8* 32 NC_CK505_SRC8_N OUT 9 (SLOT E )
SRC_8 33 NC_CK505_SRC8_P OUT 9
CLKREQ_8* 34 NC_CK505_SRC_CLKREQ8_L IN 9
(INT PU)
DOT_96*/27M_SS 7 NB_CLK96M_DOT_N
DOT_96/27M 6 NB_CLK96M_DOT_P
OUT
OUT
6 9 16 30 71
6 9 16 30 71
(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)
(INT PD)
CKPWRGD/PD* 2 CLK_PWRGD IN 6 25
48M/FS_A 4 CK505_USB48_FSA OUT 6 30 (FROM ICH8M)

REF_0/FS_C/TEST_SEL 54 CK505_CLK14P3M_TIMER
GPU_STOP* 53 NC_GPU_STOP_L
OUT 6 30
(ICH8M USB 48MHZ)
BI 9
(ICH8M,SIO,LPC REF. 14.318MHZ)
Clock (CK505)
A FCTSEL1 PIN 6 PIN 7 PIN 10 PIN 11
A
0 DOT96T DOT96C 100MT_SST 100MC_SST * FOR INT. GRAPHIC SYSTEM
27M NON 27M THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 SPREAD SPREAD SRCT0 SRCC0 * FOR EXT. GRAPHIC SYSTEM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
D 051-7230 B.0.0

NONE 29 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CK505_USB48_FSA
R3032
1
33
2 SB_CLK48M_USBCTLR
CLK Termination
29 6 IN OUT 6 25 71
5%
1/20W
MF
201
R3033 71 30 29 10 6 IN FSB_CLK_CPU_P FSB_CLK_CPU_P OUT 6 10 29 30 71

2.2K MAKE_BASE=TRUE
1 2 CK505_FSA 6 30 71
5%
(CPU HOST 133/167MHZ)
1/20W 71 30 29 10 6 IN FSB_CLK_CPU_N FSB_CLK_CPU_N OUT 6 10 29 30 71
MF MAKE_BASE=TRUE
D
201
D
R3034 71 30 29 14 6 IN FSB_CLK_NB_P FSB_CLK_NB_P OUT 6 14 29 30 71
33 MAKE_BASE=TRUE
29 6 IN CK505_CLK14P3M_TIMER 1 2 SB_CLK14P3M_TIMER OUT 6 25 71
5%
(GMCH HOST 133/167MHZ)
1/20W 71 30 29 14 6 IN FSB_CLK_NB_N FSB_CLK_NB_N OUT 6 14 29 30 71
MF MAKE_BASE=TRUE
201
R3035
1
10K
2 CK505_FSC
71 66 30 29 13 7 6 IN XDP_CLK_P XDP_CLK_P
MAKE_BASE=TRUE
OUT 6 7 13 29 30 66 71 CLKREQ Controls
6 30 71
5%
(ITP HOST 133/167MHZ)
1/20W 71 66 30 29 13 7 6 IN XDP_CLK_N XDP_CLK_N OUT 6 7 13 29 30 66 71 64 63 60
MF MAKE_BASE=TRUE 25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0
201 53 52 51 46 44 42 29 28 27 26
PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 30 29 16 9 6 IN NB_CLK100M_DPLLSS_P NB_CLK100M_DPLLSS_P OUT 6 9 16 29 30 71

23 26 27 30 42 54 72 71
NOSTUFF
MAKE_BASE=TRUE
R3046
1 (Int Gfx LVDS 100MHz) PM_STPPCI_L
10K
1 2
5%
R3080 29 25 6
1/20W 201
1K 30 29 16 9 6 IN NB_CLK100M_DPLLSS_N NB_CLK100M_DPLLSS_N OUT 6 9 16 29 30 71 MF
5% 71 MAKE_BASE=TRUE
1/20W
MF R3047
(TO MCH FS_A) R3081 2 201 29 25 6 PM_STPCPU_L
10K
1 2
5%
1K 1/20W 201
66 16 13 7 6 OUT NB_BSEL<0> 1 2 71 30 29 24 6 IN SB_CLK100M_DMI_P SB_CLK100M_DMI_P OUT 6 24 29 30 71 MF
MAKE_BASE=TRUE
5%
1/20W
MF
(ICH8M DMI 100MHZ)
201 R3082 71 30 29 24 6 IN SB_CLK100M_DMI_N SB_CLK100M_DMI_N OUT 6 24 29 30 71
0 MAKE_BASE=TRUE
71 30 6 CK505_FSA 1 2 CPU_BSEL<0> IN 6 10 66
5%
1/20W
(TO ICH8M USB 48MHZ) R30831 MF
201
(FROM CPU FS_A)
1K
C 5%
1/20W
MF
201 2
C
71 30 29 16 6 IN NB_CLK100M_PCIE_P NB_CLK100M_PCIE_P OUT 6 16 29 30 71

MAKE_BASE=TRUE
(GMCH PEG/DMI 100MHZ)

PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21 71 30 29 16 6 IN NB_CLK100M_PCIE_N NB_CLK100M_PCIE_N OUT 6 16 29 30 71
23 26 27 30 42 54 72 MAKE_BASE=TRUE
1
R3084
1K 71 36 30 29 6 IN PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_P OUT 6 29 30 36 71
5% MAKE_BASE=TRUE
1/20W
(TO MCH FS_B) MF (WIRELESS PCI-E MINI 100MHZ)
R3085 2 201 71 36 30 29 6 IN PCIE_CLK100M_MINI_N PCIE_CLK100M_MINI_N OUT 6 29 30 36 71
1K MAKE_BASE=TRUE
66 16 13 7 6 OUT NB_BSEL<1> 1 2
5%
1/20W
MF
201 R3086
0
29 6 OUT CK505_FSB_TEST_MODE 1 2 CPU_BSEL<1> IN 6 10 66
NOSTUFF 5%
1/20W
R3087 1 MF
201
(FROM CPU FS_B)
1K
5%
1/20W
MF
201 2
71 30 29 16 9 6 IN NB_CLK96M_DOT_P NB_CLK96M_DOT_P OUT 6 9 16 29 30 71

MAKE_BASE=TRUE
29 6 BI CK505_PCI5_FCTSEL1
(Int GFX DOT 96MHZ)
71 30 29 16 9 6 NB_CLK96M_DOT_N NB_CLK96M_DOT_N 6 9 16 29 30 71
B IN
MAKE_BASE=TRUE
OUT
1
R3066
B
PP1V05_S0 6 7 8 10 11 12 13 14 18 19 21
R3038
23 26 27 30 42 54 72 10K
33 5%
1 NOSTUFF 29 6 IN CK505_PCIF0_CLK 1 2 PCI_CLK33M_LPCPLUS OUT 6 43 (PORT80 LPC 33MHZ) 1/20W
R3088 5%
MAKE_BASE=TRUE 71 MF
1K 1/20W 2 201
5% MF R3039
1/20W 201 33
(TO MCH FS_C) MF 71 29 6 IN CK505_PCIF1_CLK 1 2 PCI_CLK33M_SB OUT 6 24
71
(TO ICH8M PCI 33MHZ)
R3089 2 201 5%
MAKE_BASE=TRUE
1K 1/20W
66 16 13 7 6 OUT NB_BSEL<2> 1 2 MF
201
5%
1/20W R3030
MF
R3090 33
201
0
71 29 6 IN CK505_PCI3_CLK 1 2 PCI_CLK33M_SMC OUT 6 41
71
(TO SMC PCI 33MHZ)
71 30 6 CK505_FSC 1 2 CPU_BSEL<2> IN 6 10 66 5%
1/20W
5% MF
1/20W 201
(ICH8M 14.318MHZ) R30911 MF
201
(FROM CPU FS_C)
1K
5%
1/20W
MF
201 2
FS_C FS_B FS_A CPU

0 0 0 266M NOSTUFF R3082, R3086, R3090 Clock Termination
A 0 0 1 133M FOR MANUAL CPU FREQUENCY SYNC_MASTER=M70

A
0 1 1 166M
* 0 1 0 200M CPU speed is currently set to 200MHz PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1 1 0 400M II NOT TO REPRODUCE OR COPY IT
1 1 1 Resrvd SIZE DRAWING NUMBER REV.
1 0 1 100M D
1 0 0 333M
051-7230 B.0.0

NONE 30 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C3130 2 1 0.1UF
10% 6.3V X5R 201
72 55 32 31 8 6 PP0V9_S3
72 55 32 31 8 6 PP0V9_S3 72 55 32 31 8 6 PP0V9_S3 72 55 32 31 8 6 PP0V9_S3
51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3
C3100 2 1 0.1UF C3110 2 1 C3120 2 1 0.1UF
72 68 55
0.1UF
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
10% 6.3V X5R 201 10% 6.3V X5R 201 10% 6.3V X5R 201
72
31 21 18 16 8 7 6 PP1V8_S3 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 VDD VDDL VDDQ VREF
68 55 51 35 34 32 72 68 55 72 68 55 68
31
NC R7 RFU DQ15 B9 MEM_A_DQ<63> 17
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
68
NC R3 RFU DQ14 B1 MEM_A_DQ<62> 17
31
68 33 31 17 MEM_A_A<13> R8 NC/A13 DQ13 D9 MEM_A_DQ<61> 17
31
VDD VDDL VDDQ VREF VDD VDDL VDDQ VREF VDD VDDL VDDQ VREF MEM_A_A<12> R2 D1 MEM_A_DQ<60> 68
68 33 31 17 A12 DQ12 17 31
NC R7 RFU DQ15 B9 MEM_A_DQ<15> 17 31 68 NC R7 RFU DQ15 B9 MEM_A_DQ<31> 17 31 68 NC R7 RFU DQ15 B9 MEM_A_DQ<47> 17 31 68 OMIT 68
68
68 33 31 17 MEM_A_A<11> P7 A11 DQ11 D3 MEM_A_DQ<59> 17
D 33 31 17 MEM_A_A<13>
NC R3 RFU
R8 NC/A13
DQ14
DQ13
B1
D9
MEM_A_DQ<14>
MEM_A_DQ<13>
17 31 68
31 17 MEM_A_A<13>
NC R3 RFU
R8 NC/A13
DQ14
DQ13
B1
D9
MEM_A_DQ<30>
MEM_A_DQ<29>
17 31 68
MEM_A_A<13>
NC R3 RFU
R8 NC/A13
DQ14
DQ13
B1
D9
MEM_A_DQ<46>
MEM_A_DQ<45>
17 31 68
68 33 31
17 31 68
17 MEM_A_A<10> M2 A10/AP DQ10 D7 MEM_A_DQ<58>
31
D
68
33 31 17 MEM_A_A<12> R2 A12 DQ12 D1 MEM_A_DQ<12>
68 33
31 17 MEM_A_A<12> R2 A12 DQ12 D1 MEM_A_DQ<28> MEM_A_A<12> R2 A12 DQ12 D1 MEM_A_DQ<44>
68 33 31
17 31 68
17 MEM_A_A<9>
MEM_A_A<8>
P3
P8
A9 U3130 DQ9 C2
C8
MEM_A_DQ<57>
MEM_A_DQ<56>
68
17
31
68 OMIT 68 33 OMIT OMIT 68 33 31 17 A8 DQ8
33 31 17
68
MEM_A_A<11> P7 A11 DQ11 D3 MEM_A_DQ<11> 31 17
68 33
MEM_A_A<11> P7 A11 DQ11 D3 MEM_A_DQ<27> MEM_A_A<11> P7 A11 DQ11 D3 MEM_A_DQ<43> 17 31 68
68 33 31 17 MEM_A_A<7> P2 A7
64MX16 DQ7 F9 MEM_A_DQ<55> 68
17
33 31 17 MEM_A_A<10> M2 A10/AP DQ10 D7 MEM_A_DQ<10> 31 17 MEM_A_A<10> M2 A10/AP DQ10 D7 MEM_A_DQ<26> MEM_A_A<10> M2 A10/AP DQ10 D7 MEM_A_DQ<42> 17 31 68
MEM_A_A<6> N7 FBGA F1 MEM_A_DQ<54>
31
68 68 33 68 33 31 17 A6 DQ6 17
33 31 17
68
MEM_A_A<9>
MEM_A_A<8>
P3
P8
A9 U3100 DQ9 C2
C8
MEM_A_DQ<9>
MEM_A_DQ<8>
31 17
68 33
MEM_A_A<9>
MEM_A_A<8>
P3
P8
A9 U3110 DQ9 C2
C8
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_A<9>
MEM_A_A<8>
P3
P8
A9 U3120 DQ9 C2
C8
MEM_A_DQ<41>
MEM_A_DQ<40>
17 31 68
68 33 31 17 MEM_A_A<5> N3 A5
MT47H64M16
DQ5 H9 MEM_A_DQ<53>
31
68
17 31
33 31 17 A8 DQ8 31 17 A8 DQ8 A8 DQ8 17 31 68 68
68
33 31 17 MEM_A_A<7> P2 A7
64MX16 DQ7 F9 MEM_A_DQ<7>
68 33
31 17 MEM_A_A<7> P2 A7
64MX16 DQ7 F9 MEM_A_DQ<23> MEM_A_A<7> P2 A7
68 33 31
17 31 68
17 MEM_A_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_A_DQ<52> 68
17
31
68 FBGA 68 33 FBGA FBGA 68 33 31 17 MEM_A_A<3> N2 A3 DQ3 H3 MEM_A_DQ<51> 17
33 31 17 MEM_A_A<6> N7 A6 DQ6 F1 MEM_A_DQ<6> 31 17 MEM_A_A<6> N7 A6 DQ6 F1 MEM_A_DQ<22> MEM_A_A<6> N7 A6 DQ6 F1 MEM_A_DQ<38> 17 31 68 31
68 MT47H64M16 68 33 MT47H64M16 MT47H64M16 68 33 31 17 MEM_A_A<2> M7 A2 DQ2 H7 MEM_A_DQ<50> 68
17 31
33 31 17 MEM_A_A<5> N3 A5 DQ5 H9 MEM_A_DQ<5> 31 17 MEM_A_A<5> N3 A5 DQ5 H9 MEM_A_DQ<21> MEM_A_A<5> N3 A5 DQ5 H9 MEM_A_DQ<37> 17 31 68 68
68
68 68 33 68 33 31 17 MEM_A_A<1> M3 A1 Bit swizzle per byte? DQ1 G2 MEM_A_DQ<49> 17
33 31 17 MEM_A_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_A_DQ<4> 31 17 MEM_A_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_A_DQ<20> MEM_A_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_A_DQ<36> 17 31 68 31
68 68 33 68 33 31 17 MEM_A_A<0> M8 A0 DQ0 G8 MEM_A_DQ<48> 17
33 31 17 MEM_A_A<3> N2 A3 DQ3 H3 MEM_A_DQ<3> 31 17 MEM_A_A<3> N2 A3 DQ3 H3 MEM_A_DQ<19> MEM_A_A<3> N2 A3 DQ3 H3 MEM_A_DQ<35> 17 31 68 31
68 68 33 68
33 31 17 MEM_A_A<2> M7 A2 DQ2 H7 MEM_A_DQ<2> 31 17 MEM_A_A<2> M7 A2 DQ2 H7 MEM_A_DQ<18> MEM_A_A<2> M7 A2 DQ2 H7 MEM_A_DQ<34> 17 31 68
68 68 33 68 33 31 17 MEM_A_BS<2> L1 NC/BA2 LDQS F7 MEM_A_DQS_P<6> 68
17
33 31 17 MEM_A_A<1> M3 A1 Bit swizzle per byte? DQ1 G2 MEM_A_DQ<1> 31 17 MEM_A_A<1> M3 A1 Bit swizzle per byte? DQ1 G2 MEM_A_DQ<17> MEM_A_A<1> M3 A1 Bit swizzle per byte? DQ1 G2 MEM_A_DQ<33> 17 31 68 31
68 68 33 68 33 31 17 MEM_A_BS<1> L3 BA1 LDQS* E8 MEM_A_DQS_N<6>
33 31 17 MEM_A_A<0> M8 A0 DQ0 G8 MEM_A_DQ<0> 31 17 MEM_A_A<0> M8 A0 DQ0 G8 MEM_A_DQ<16> MEM_A_A<0> M8 A0 DQ0 G8 MEM_A_DQ<32> 17 31 68
68
68 68 33 68 33 31 17 MEM_A_BS<0> L2 BA0 UDQS B7 MEM_A_DQS_P<7> 31
17
UDQS* A8 MEM_A_DQS_N<7> 68
17
33 31 17 MEM_A_BS<2> L1 NC/BA2 LDQS F7 MEM_A_DQS_P<0> 31 68
17 17 MEM_A_BS<2> L1 NC/BA2 LDQS F7 MEM_A_DQS_P<2> MEM_A_BS<2> L1 NC/BA2 LDQS F7 MEM_A_DQS_P<4> 17 31 68 31
68 68 33 31 68 33 31 16 MEM_CLK_P<0> J8 CK
33 31 17 MEM_A_BS<1> L3 BA1 LDQS* E8 MEM_A_DQS_N<0> 17 MEM_A_BS<1> L3 BA1 LDQS* E8 MEM_A_DQS_N<2> MEM_A_BS<1> L3 BA1 LDQS* E8 MEM_A_DQS_N<4> 17 31 68
68 68 33 31 68 33 31 16 MEM_CLK_N<0> K8 CK*
33 31 17 MEM_A_BS<0> L2 BA0 UDQS B7 MEM_A_DQS_P<1> 17 MEM_A_BS<0> L2 BA0 UDQS B7 MEM_A_DQS_P<3> MEM_A_BS<0> L2 BA0 UDQS B7 MEM_A_DQS_P<5> 17 31 68
68 68 33 31 68 33 31 16 MEM_CKE<0> K2 CKE
UDQS* A8 MEM_A_DQS_N<1> 17 31 68 UDQS* A8 MEM_A_DQS_N<3> 17 31 68 UDQS* A8 MEM_A_DQS_N<5> 17 31 68
68 33 31 16 MEM_CS_L<0> L8 CS*
33 31 16 MEM_CLK_P<0> J8 CK 68 33 31 16 MEM_CLK_P<0> J8 CK 68 33 31 16 MEM_CLK_P<0> J8 CK
68 NC E2 NC
33 31 16 MEM_CLK_N<0> K8 CK* 68 33 31 16 MEM_CLK_N<0> K8 CK* 68 33 31 16 MEM_CLK_N<0> K8 CK*
68 68 33 31 16 6 MEM_ODT<0> K9 ODT NC A2 NC
33 31 16 MEM_CKE<0> K2 CKE 68 33 31 16 MEM_CKE<0> K2 CKE 68 33 31 16 MEM_CKE<0> K2 CKE
68
33 31 16 MEM_CS_L<0> L8 CS* 68 33 31 16 MEM_CS_L<0> L8 CS* 68 33 31 16 MEM_CS_L<0> L8 CS*
68 68 33 31 17 MEM_A_RAS_L K7 RAS*
NC E2 NC NC E2 NC NC E2 NC
68 33 31 17 MEM_A_CAS_L L7 CAS*
31 16 6 MEM_ODT<0> K9 ODT NC A2 NC 68 33 31 16 6 MEM_ODT<0> K9 ODT NC A2 NC 68 33 31 16 6 MEM_ODT<0> K9 ODT NC A2 NC
68 33 68 33 31 17 MEM_A_WE_L K3 WE*
C 33 31 17
68
33 31 17
MEM_A_RAS_L
MEM_A_CAS_L
K7 RAS*
L7 CAS*
68 33 31 17
68 33 31 17
MEM_A_RAS_L
MEM_A_CAS_L
K7 RAS*
L7 CAS*
68 33 31 17
68 33 31 17
MEM_A_RAS_L
MEM_A_CAS_L
K7 RAS*
L7 CAS*
68 31 17 MEM_A_DM<7> B3 UDM C
68 68 31 17 MEM_A_DM<6> F3 LDM
33 31 17 MEM_A_WE_L K3 WE* 68 33 31 17 MEM_A_WE_L K3 WE* 68 33 31 17 MEM_A_WE_L K3 WE*
68
VSS VSSDL VSSQ
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
68 31 17 MEM_A_DM<1> B3 UDM 68 31 17 MEM_A_DM<3> B3 UDM 68 31 17 MEM_A_DM<5> B3 UDM
68 31 17 MEM_A_DM<0> F3 LDM 68 31 17 MEM_A_DM<2> F3 LDM 68 31 17 MEM_A_DM<4> F3 LDM
C3170 2 1 0.1UF
VSS VSSDL VSSQ VSS VSSDL VSSQ VSS VSSDL VSSQ PP0V9_S3
72 55 32 31 8 6
10% 6.3V X5R 201
51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3
A3
E3
J3
N1
P9
J7
A7
B2
A3
E3
J3
N1
P9
J7
A7
B2
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
B8
D2
D8
E7
F2
F8
H2
H8
B8
D2
D8
E7
F2
F8
H2
H8
72 68 55
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
VDD VDDL VDDQ VREF
NC R7 RFU DQ15 B9 MEM_A_DQ<63> 17 31 68
NC R3 RFU DQ14 B1 MEM_A_DQ<62> 17 31 68
68 33 31 17 MEM_A_A<13> R8 NC/A13 DQ13 D9 MEM_A_DQ<61> 17 31 68
68 33 31 17 MEM_A_A<12> R2 A12 DQ12 D1 MEM_A_DQ<60> 17 31 68

72 55 32 31 8 6 PP0V9_S3 72 55 32 31 8 6 PP0V9_S3 72 55 32 31 8 6 PP0V9_S3 OMIT
68 33 31 17 MEM_A_A<11> P7 A11 DQ11 D3 MEM_A_DQ<59> 17 31 68
C3140 2 1 C3150 2 1 0.1UF C3160 2 1 0.1UF
0.1UF 68 33 31 17 MEM_A_A<10> M2 A10/AP DQ10 D7 MEM_A_DQ<58> 17 31 68
10% 6.3V X5R 201 10% 6.3V X5R 201 10% 6.3V X5R 201 68 33 31 17 MEM_A_A<9>
MEM_A_A<8>
P3
P8
A9 U3170 DQ9 C2
C8
MEM_A_DQ<57>
MEM_A_DQ<56>
17 31 68
68 33 31 17 A8 DQ8 17 31 68
72
32 31 21 18 16 8 7 6 PP1V8_S3
68 55 51 35 34
51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3
72 68 55
51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3
72 68 55 68 33 31 17 MEM_A_A<7> P2 A7
64MX16 DQ7 F9 MEM_A_DQ<55> 17 31 68

68 33 31 17 A6 DQ6 17 31 68
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
N3 MT47H64M16
68 33 31 17 MEM_A_A<5> A5 DQ5 H9 MEM_A_DQ<53> 17 31 68
VDD VDDL VDDQ VREF VDD VDDL VDDQ VREF VDD VDDL VDDQ VREF 68 33 31 17 MEM_A_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_A_DQ<52> 17 31 68
NC R7 RFU DQ15 B9 MEM_A_DQ<15> 17 31 68 NC R7 RFU DQ15 B9 MEM_A_DQ<31> 17 31 68 NC R7 RFU DQ15 B9 MEM_A_DQ<47> 17 31 68 MEM_A_A<3> N2 A3 DQ3 H3 MEM_A_DQ<51> 17 31 68
NC R3 RFU DQ14 B1 MEM_A_DQ<14> 17 31 68 NC R3 RFU DQ14 B1 MEM_A_DQ<30> 17 31 68 NC R3 RFU DQ14 B1 MEM_A_DQ<46> 17 31 68 MEM_A_A<2> M7 A2 DQ2 H7 MEM_A_DQ<50> 17 31 68
31 17 MEM_A_A<13> R8 NC/A13 DQ13 D9 MEM_A_DQ<13> 17 31 MEM_A_A<13> R8 NC/A13 DQ13 D9 MEM_A_DQ<29> 31 17 MEM_A_A<13> R8 NC/A13 DQ13 D9 MEM_A_DQ<45> 17 31 68 MEM_A_A<1> M3 A1 DQ1 G2 MEM_A_DQ<49> 17 31 68
B 68 33
31 17
68 33
MEM_A_A<12> R2 A12
OMIT
DQ12 D1 MEM_A_DQ<12>
68
17 31
68
MEM_A_A<12> R2 A12
OMIT
DQ12 D1 MEM_A_DQ<28>
68 33
17 31 MEM_A_A<12>
68
R2 A12
OMIT
DQ12 D1 MEM_A_DQ<44> 17 31 68 MEM_A_A<0> M8 A0
Bit swizzle per byte?
DQ0 G8 MEM_A_DQ<48> 17 31 68 B
31 17 MEM_A_A<11> P7 A11 DQ11 D3 MEM_A_DQ<11> 17 31 MEM_A_A<11> P7 A11 DQ11 D3 MEM_A_DQ<27> 17 31 MEM_A_A<11> P7 A11 DQ11 D3 MEM_A_DQ<43> 17 31 68
68 33 68 68
31 17 MEM_A_A<10> M2 A10/AP DQ10 D7 MEM_A_DQ<10> 17 31 MEM_A_A<10> M2 A10/AP DQ10 D7 MEM_A_DQ<26> 17 31 MEM_A_A<10> M2 A10/AP DQ10 D7 MEM_A_DQ<42> 17 31 68 MEM_A_BS<2> L1 NC/BA2 LDQS F7 MEM_A_DQS_P<6> 17 31 68
68 33 68 68
31
68
17
33
MEM_A_A<9> P3
P8
A9 U3140 DQ9 C2
C8
MEM_A_DQ<9> 17 31
68
MEM_A_A<9> P3
P8
A9 U3150 DQ9 C2
C8
MEM_A_DQ<25> 17 31 MEM_A_A<9>
68
P3
P8
A9 U3160 DQ9 C2
C8
MEM_A_DQ<41> 17 31 68 MEM_A_BS<1> L3 BA1
L2 BA0
LDQS* E8 MEM_A_DQS_N<6> 17 31 68
31 17 MEM_A_A<8> A8 DQ8 MEM_A_DQ<8> 17 31 MEM_A_A<8> A8 DQ8 MEM_A_DQ<24> 17 31 MEM_A_A<8> A8 DQ8 MEM_A_DQ<40> 17 31 68 MEM_A_BS<0> UDQS B7 MEM_A_DQS_P<7> 17 31 68
68
31
33
17 MEM_A_A<7> P2 A7
68
17 31 MEM_A_A<7> P2 A7
68
17 31 MEM_A_A<7> P2 A7
64MX16 DQ7 F9 MEM_A_DQ<39> 17 31 68 UDQS* A8 MEM_A_DQS_N<7> 17 31 68
68 33
68
68
N7 FBGA F1 MEM_CLK_P<1> J8 CK
31 17 A6 DQ6 17 31 A6 DQ6 17 31 MEM_A_A<6> A6 DQ6 MEM_A_DQ<38> 17 31 68
68 33
N3 MT47H64M16 68
N3 MT47H64M16 68
N3 MT47H64M16
31 17 MEM_A_A<5> A5 DQ5 H9 MEM_A_DQ<5> 17 31 MEM_A_A<5> A5 DQ5 H9 MEM_A_DQ<21> 17 31 MEM_A_A<5> A5 DQ5 H9 MEM_A_DQ<37> 17 31 68 MEM_CLK_N<1> K8 CK*
68 33 68 68
31 17 MEM_A_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_A_DQ<4> 17 31 MEM_A_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_A_DQ<20> 17 31 MEM_A_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_A_DQ<36> 17 31 68 MEM_CKE<1> K2 CKE
68 33 68 68
31 17 MEM_A_A<3> N2 A3 DQ3 H3 MEM_A_DQ<3> 17 31 MEM_A_A<3> N2 A3 DQ3 H3 MEM_A_DQ<19> 17 31 MEM_A_A<3> N2 A3 DQ3 H3 MEM_A_DQ<35> 17 31 68 MEM_CS_L<1> L8 CS*
68 33 68 68
31 17 MEM_A_A<2> M7 A2 DQ2 H7 MEM_A_DQ<2> 17 31 MEM_A_A<2> M7 A2 DQ2 H7 MEM_A_DQ<18> 17 31 MEM_A_A<2> M7 A2 DQ2 H7 MEM_A_DQ<34> 17 31 68 NC E2 NC
68 33 68 68
31 17 MEM_A_A<1> M3 A1 Bit swizzle per byte? DQ1 G2 MEM_A_DQ<1> 17 31 MEM_A_A<1> M3 A1 Bit swizzle per byte? DQ1 G2 MEM_A_DQ<17> 17 31 MEM_A_A<1> M3 A1 Bit swizzle per byte? DQ1 G2 MEM_A_DQ<33> 17 31 68 MEM_ODT<1> K9 ODT NC A2 NC
68 33 68 68
31 17 MEM_A_A<0> M8 A0 DQ0 G8 MEM_A_DQ<0> 17 31 MEM_A_A<0> M8 A0 DQ0 G8 MEM_A_DQ<16> 17 31 MEM_A_A<0> M8 A0 DQ0 G8 MEM_A_DQ<32> 17 31 68
68 33 68 68
68 33 31 17 MEM_A_RAS_L K7 RAS*
31 17 MEM_A_BS<2> L1 NC/BA2 LDQS F7 MEM_A_DQS_P<0> 17 31 MEM_A_BS<2> L1 NC/BA2 LDQS F7 MEM_A_DQS_P<2> 17 31 MEM_A_BS<2> L1 NC/BA2 LDQS F7 MEM_A_DQS_P<4> 17 31 68 MEM_A_CAS_L L7 CAS*
68 33 68 68
31 17 MEM_A_BS<1> L3 BA1 LDQS* E8 MEM_A_DQS_N<0> 17 31 MEM_A_BS<1> L3 BA1 LDQS* E8 MEM_A_DQS_N<2> 17 31 MEM_A_BS<1> L3 BA1 LDQS* E8 MEM_A_DQS_N<4> 17 31 68 MEM_A_WE_L K3 WE*
68 33 68 68
31 17 MEM_A_BS<0> L2 BA0 UDQS B7 MEM_A_DQS_P<1> 17 31 MEM_A_BS<0> L2 BA0 UDQS B7 MEM_A_DQS_P<3> 17 31 MEM_A_BS<0> L2 BA0 UDQS B7 MEM_A_DQS_P<5> 17 31 68
68 33 68 68
UDQS* A8 MEM_A_DQS_N<1> 17 31 68 UDQS* A8 MEM_A_DQS_N<3> 17 31 68 UDQS* A8 MEM_A_DQS_N<5> 17 31 68 MEM_A_DM<7> B3 UDM
31 16 MEM_CLK_P<1> J8 CK 68 33 31 16 MEM_CLK_P<1> J8 CK 68 33 31 16 MEM_CLK_P<1> J8 CK 68 31 17 MEM_A_DM<6> F3 LDM
68 33
31 16 MEM_CLK_N<1> K8 CK* 68 33 31 16 MEM_CLK_N<1> K8 CK* 68 33 31 16 MEM_CLK_N<1> K8 CK* VSS VSSDL VSSQ
68 33
31 16 MEM_CKE<1> K2 CKE 68 33 31 16 MEM_CKE<1> K2 CKE 68 33 31 16 MEM_CKE<1> K2 CKE
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
68 33
31 16 MEM_CS_L<1> L8 CS* 68 33 31 16 MEM_CS_L<1> L8 CS* 68 33 31 16 MEM_CS_L<1> L8 CS*
68 33
68
16 6 MEM_ODT<1> K9 ODT NC A2 NC 68 33 31 16 6 MEM_ODT<1> K9 ODT NC A2 NC 68 33 31 16 6 MEM_ODT<1> K9 ODT NC A2 NC
33 31 DDR2 DRAM Channel A
MEM_A_RAS_L K7 RAS* MEM_A_RAS_L K7 RAS* MEM_A_RAS_L K7 RAS*
A 31 17
68 33
31 17
68 33
MEM_A_CAS_L L7 CAS*
68 33 31 17
68 33 31 17 MEM_A_CAS_L L7 CAS*
68 33 31 17
68 33 31 17 MEM_A_CAS_L L7 CAS*

SYNC_DATE=(MASTER)
A
31 17 MEM_A_WE_L K3 WE* 68 33 31 17 MEM_A_WE_L K3 WE* 68 33 31 17 MEM_A_WE_L K3 WE*
68 33
31 17 MEM_A_DM<1> B3 UDM 68 31 17 MEM_A_DM<3> B3 UDM 68 31 17 MEM_A_DM<5> B3 UDM AGREES TO THE FOLLOWING
68
31 17 MEM_A_DM<0> F3 LDM 68 31 17 MEM_A_DM<2> F3 LDM 68 31 17 MEM_A_DM<4> F3 LDM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
68
VSS VSSDL VSSQ VSS VSSDL VSSQ VSS VSSDL VSSQ II NOT TO REPRODUCE OR COPY IT
A3
E3
J3
N1
P9
J7
A7
B2
A3
E3
J3
N1
P9
J7
A7
B2
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
B8
D2
D8
E7
F2
F8
H2
H8
B8
D2
D8
E7
F2
F8
H2
H8
D 051-7230 B.0.0

NONE 31 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
72 55 32 31 8 6 PP0V9_S3 C3230 2 1 0.1UF
10% 6.3V X5R 201
72 55 32 31 8 6 PP0V9_S3 72 55 32 31 8 6 PP0V9_S3 72 55 32 31 8 6 PP0V9_S3

51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3
72 68 55
C3200 2 1 0.1UF C3210 2 1 0.1UF C3220 2 1 0.1UF
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
10% 6.3V X5R 201 10% 6.3V X5R 201 10% 6.3V X5R 201
72
31 21 18 16 8 7 6 PP1V8_S3 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3 VDD VDDL VDDQ VREF
68 55 51 35 34 32 72 68 55 72 68 55
68
NC R7 RFU DQ15 B9 MEM_B_DQ<63> 17
32
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
NC R3 RFU DQ14 B1 MEM_B_DQ<62>
68
17 32
68
32
68 33 32 17 MEM_B_A<13> R8 NC/A13 DQ13 D9 MEM_B_DQ<61> 17
VDD VDDL VDDQ VREF VDD VDDL VDDQ VREF VDD VDDL VDDQ VREF MEM_B_A<12> R2 D1 MEM_B_DQ<60> 68
68 33 32 17 A12 DQ12 17
NC R7 RFU DQ15 B9 MEM_B_DQ<15> 17 32 68 NC R7 RFU DQ15 B9 MEM_B_DQ<31> 17 32 68 NC R7 RFU DQ15 B9 MEM_B_DQ<47> 17 32 68 32
68 33 32 17 MEM_B_A<11> P7 A11 OMIT DQ11 D3 MEM_B_DQ<59>
D 33 32 17 MEM_B_A<13>
NC R3 RFU
R8 NC/A13
DQ14
DQ13
B1
D9
MEM_B_DQ<14>
MEM_B_DQ<13>
17 32 68
17 32 MEM_B_A<13>
NC R3 RFU
R8 NC/A13
DQ14
DQ13
B1
D9
MEM_B_DQ<30>
MEM_B_DQ<29>
17 32 68
MEM_B_A<13>
NC R3 RFU
R8 NC/A13
DQ14
DQ13
B1
D9
MEM_B_DQ<46>
MEM_B_DQ<45>
17 32 68
68 33 32
17 32 68
17 MEM_B_A<10> M2 A10/AP DQ10 D7 MEM_B_DQ<58> 68
17
32
D
68
33 32 17 MEM_B_A<12> R2 A12 DQ12 D1 MEM_B_DQ<12>
68
17 32 MEM_B_A<12> R2 A12 DQ12 D1 MEM_B_DQ<28> MEM_B_A<12> R2 A12 DQ12 D1 MEM_B_DQ<44>
68 33 32
17 32 68
17 MEM_B_A<9>
MEM_B_A<8>
P3
P8
A9 U3230 DQ9 C2
C8
MEM_B_DQ<57>
MEM_B_DQ<56> 68
68 68 68 33 32 17 A8 DQ8 17
33 32 17
68
MEM_B_A<11> P7 A11 OMIT DQ11 D3 MEM_B_DQ<11> 17 32
68
MEM_B_A<11> P7 A11 OMIT DQ11 D3 MEM_B_DQ<27> MEM_B_A<11> P7 A11 OMIT DQ11 D3 MEM_B_DQ<43> 17 32 68
68 33 32 17 MEM_B_A<7> P2 A7
64MX16 DQ7 F9 MEM_B_DQ<55>
32
33 32 17 MEM_B_A<10> M2 A10/AP DQ10 D7 MEM_B_DQ<10> 17 32 MEM_B_A<10> M2 A10/AP DQ10 D7 MEM_B_DQ<26> MEM_B_A<10> M2 A10/AP DQ10 D7 MEM_B_DQ<42> 17 32 68
MEM_B_A<6> N7 FBGA F1 MEM_B_DQ<54> 68
68 68 68 33 32 17 A6 DQ6 17
33 32 17
68
MEM_B_A<9>
MEM_B_A<8>
P3
P8
A9 U3200 DQ9 C2
C8
MEM_B_DQ<9>
MEM_B_DQ<8>
17 32
68
MEM_B_A<9>
MEM_B_A<8>
P3
P8
A9 U3210 DQ9 C2
C8
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_A<9>
MEM_B_A<8>
P3
P8
A9 U3220 DQ9 C2
C8
MEM_B_DQ<41>
MEM_B_DQ<40>
17 32 68
68 33 32 17 MEM_B_A<5> N3 A5
MT47H64M16
DQ5 H9 MEM_B_DQ<53>
32
68
17 32
33 32 17 A8 DQ8 17 32 A8 DQ8 A8 DQ8 17 32 68 68
68
33 32 17 MEM_B_A<7> P2 A7
68
17 32 MEM_B_A<7> P2 A7
64MX16 DQ7 F9 MEM_B_DQ<23> MEM_B_A<7> P2 A7
68 33 32
17 32 68
17 MEM_B_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_B_DQ<52> 32
17
68
68 FBGA 68 FBGA FBGA 68 33 32 17 MEM_B_A<3> N2 A3 DQ3 H3 MEM_B_DQ<51> 17
33 32 17 MEM_B_A<6> N7 A6 DQ6 F1 MEM_B_DQ<6> 17 32 MEM_B_A<6> N7 A6 DQ6 F1 MEM_B_DQ<22> MEM_B_A<6> N7 A6 DQ6 F1 MEM_B_DQ<38> 17 32 68 32
68 MT47H64M16 68 MT47H64M16 MT47H64M16 68 33 32 17 MEM_B_A<2> M7 A2 DQ2 H7 MEM_B_DQ<50> 17 32
33 32 17 MEM_B_A<5> N3 A5 DQ5 H9 MEM_B_DQ<5> 17 32 MEM_B_A<5> N3 A5 DQ5 H9 MEM_B_DQ<21> MEM_B_A<5> N3 A5 DQ5 H9 MEM_B_DQ<37> 17 32 68 68
32
68
68 68 68 33 32 17 MEM_B_A<1> M3 A1 Bit swizzle per byte? DQ1 G2 MEM_B_DQ<49> 17
33 32 17 MEM_B_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_B_DQ<4> 17 32 MEM_B_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_B_DQ<20> MEM_B_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_B_DQ<36> 17 32 68 68
68 68 68 33 32 17 MEM_B_A<0> M8 A0 DQ0 G8 MEM_B_DQ<48> 17
33 32 17 MEM_B_A<3> N2 A3 DQ3 H3 MEM_B_DQ<3> 17 32 MEM_B_A<3> N2 A3 DQ3 H3 MEM_B_DQ<19> MEM_B_A<3> N2 A3 DQ3 H3 MEM_B_DQ<35> 17 32 68 32
68 68
33 32 17 MEM_B_A<2> M7 A2 DQ2 H7 MEM_B_DQ<2> 17 32 MEM_B_A<2> M7 A2 DQ2 H7 MEM_B_DQ<18> MEM_B_A<2> M7 A2 DQ2 H7 MEM_B_DQ<34> 17 32 68
68 68 68 33 32 17 MEM_B_BS<2> L1 NC/BA2 LDQS F7 MEM_B_DQS_P<6> 68
17
33 32 17 MEM_B_A<1> M3 A1 Bit swizzle per byte? DQ1 G2 MEM_B_DQ<1> 32 17 MEM_B_A<1> M3 A1 Bit swizzle per byte? DQ1 G2 MEM_B_DQ<17> MEM_B_A<1> M3 A1 Bit swizzle per byte? DQ1 G2 MEM_B_DQ<33> 17 32 68 32
68 68 33 68 33 32 17 MEM_B_BS<1> L3 BA1 LDQS* E8 MEM_B_DQS_N<6> 17
33 32 17 MEM_B_A<0> M8 A0 DQ0 G8 MEM_B_DQ<0> 17 32 MEM_B_A<0> M8 A0 DQ0 G8 MEM_B_DQ<16> MEM_B_A<0> M8 A0 DQ0 G8 MEM_B_DQ<32> 17 32 68 32
68 68 68 33 32 17 MEM_B_BS<0> L2 BA0 UDQS B7 MEM_B_DQS_P<7> 68 17 32
68
68
UDQS* A8 MEM_B_DQS_N<7> 17
33 32 17 MEM_B_BS<2> L1 NC/BA2 LDQS F7 MEM_B_DQS_P<0> 17 32 MEM_B_BS<2> L1 NC/BA2 LDQS F7 MEM_B_DQS_P<2> MEM_B_BS<2> L1 NC/BA2 LDQS F7 MEM_B_DQS_P<4> 17 32 68 32
68 68 68 33 32 16 MEM_CLK_P<3> J8 CK
33 32 17 MEM_B_BS<1> L3 BA1 LDQS* E8 MEM_B_DQS_N<0> 17 32 MEM_B_BS<1> L3 BA1 LDQS* E8 MEM_B_DQS_N<2> MEM_B_BS<1> L3 BA1 LDQS* E8 MEM_B_DQS_N<4> 17 32 68
68 68 68 33 32 16 MEM_CLK_N<3> K8 CK*
33 32 17 MEM_B_BS<0> L2 BA0 UDQS B7 MEM_B_DQS_P<1> 17 32 MEM_B_BS<0> L2 BA0 UDQS B7 MEM_B_DQS_P<3> MEM_B_BS<0> L2 BA0 UDQS B7 MEM_B_DQS_P<5> 17 32 68
68 68 68 33 32 16 MEM_CKE<3> K2 CKE
UDQS* A8 MEM_B_DQS_N<1> 17 32 68 UDQS* A8 MEM_B_DQS_N<3> 17 32 68 UDQS* A8 MEM_B_DQS_N<5> 17 32 68
68 33 32 16 MEM_CS_L<2> L8 CS*
33 32 16 MEM_CLK_P<3> J8 CK 68 33 32 16 MEM_CLK_P<3> J8 CK 68 33 32 16 MEM_CLK_P<3> J8 CK
68 NC E2 NC
33 32 16 MEM_CLK_N<3> K8 CK* 68 33 32 16 MEM_CLK_N<3> K8 CK* 68 33 32 16 MEM_CLK_N<3> K8 CK*
68 68 33 32 16 6 MEM_ODT<2> K9 ODT NC A2 NC
33 32 16 MEM_CKE<3> K2 CKE 68 33 32 16 MEM_CKE<3> K2 CKE 68 33 32 16 MEM_CKE<3> K2 CKE
68
33 32 16 MEM_CS_L<2> L8 CS* 68 33 32 16 MEM_CS_L<2> L8 CS* 68 33 32 16 MEM_CS_L<2> L8 CS*
68 68 33 32 17 MEM_B_RAS_L K7 RAS*
68 33 32 17 MEM_B_CAS_L L7 CAS*
32 16 6 MEM_ODT<2> K9 ODT NC A2 NC 68 33 32 16 6 MEM_ODT<2> K9 ODT NC A2 NC 68 33 32 16 6 MEM_ODT<2> K9 ODT NC A2 NC
68 33 68 33 32 17 MEM_B_WE_L K3 WE*
C 33 32 17
68
33 32 17
MEM_B_RAS_L
MEM_B_CAS_L
K7 RAS*
L7 CAS*
68 33 32 17
68 33 32 17
MEM_B_RAS_L
MEM_B_CAS_L
K7 RAS*
L7 CAS*
68 33 32 17
68 33 32 17
MEM_B_RAS_L
MEM_B_CAS_L
K7 RAS*
L7 CAS*
68 32 17 MEM_B_DM<7> B3 UDM C
68 68 32 17 MEM_B_DM<6> F3 LDM
33 32 17 MEM_B_WE_L K3 WE* 68 33 32 17 MEM_B_WE_L K3 WE* 68 33 32 17 MEM_B_WE_L K3 WE*
68
VSS VSSDL VSSQ
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
68 32 17 MEM_B_DM<1> B3 UDM 68 32 17 MEM_B_DM<3> B3 UDM 68 32 17 MEM_B_DM<5> B3 UDM
68 32 17 MEM_B_DM<0> F3 LDM 68 32 17 MEM_B_DM<2> F3 LDM 68 32 17 MEM_B_DM<4> F3 LDM
PP0V9_S3 C3270 2 1 0.1UF
VSS VSSDL VSSQ VSS VSSDL VSSQ VSS VSSDL VSSQ 72 55 32 31 8 6
10% 6.3V X5R 201
51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3
A3
E3
J3
N1
P9
J7
A7
B2
A3
E3
J3
N1
P9
J7
A7
B2
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
B8
D2
D8
E7
F2
F8
H2
H8
B8
D2
D8
E7
F2
F8
H2
H8
72 68 55
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
VDD VDDL VDDQ VREF
NC R7 RFU DQ15 B9 MEM_B_DQ<63> 17 32 68
NC R3 RFU DQ14 B1 MEM_B_DQ<62> 17 32 68
68 33 32 17 MEM_B_A<13> R8 NC/A13 DQ13 D9 MEM_B_DQ<61> 17 32 68
68 33 32 17 MEM_B_A<12> R2 A12 DQ12 D1 MEM_B_DQ<60> 17 32 68

72 55 32 31 8 6 PP0V9_S3 72 55 32 31 8 6 PP0V9_S3 72 55 32 31 8 6 PP0V9_S3
68 33 32 17 MEM_B_A<11> P7 A11 OMIT DQ11 D3 MEM_B_DQ<59> 17 32 68
C3240 2 1 0.1UF C3250 2 1 0.1UF C3260 2 1 0.1UF 68 33 32 17 MEM_B_A<10> M2 A10/AP DQ10 D7 MEM_B_DQ<58> 17 32 68
10% 6.3V X5R 201 10% 6.3V X5R 201 10% 6.3V X5R 201
68 33 32 17 MEM_B_A<9>
MEM_B_A<8>
P3
P8
A9 U3270 DQ9 C2
C8
MEM_B_DQ<57>
MEM_B_DQ<56>
17 32 68
68 33 32 17 A8 DQ8 17 32 68
72
32 31 21 18 16 8 7 6 PP1V8_S3
68 55 51 35 34
51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3
72 68 55
51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3
72 68 55 68 33 32 17 MEM_B_A<7> P2 A7
64MX16 DQ7 F9 MEM_B_DQ<55> 17 32 68
MEM_B_A<6> N7 FBGA F1 MEM_B_DQ<54>

68 33 32 17 A6 DQ6 17 32 68
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
A1
E1
J9
M9
R1
J1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J2
N3 MT47H64M16
33 32 17 MEM_B_A<5> A5 DQ5 H9 MEM_B_DQ<53> 17 32 68
68
VDD VDDL VDDQ VREF VDD VDDL VDDQ VREF VDD VDDL VDDQ VREF 68 33 32 17 MEM_B_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_B_DQ<52> 17 32 68
NC R7 RFU DQ15 B9 MEM_B_DQ<15> 17 32 68 NC R7 RFU DQ15 B9 MEM_B_DQ<31> 17 32 68 NC R7 RFU DQ15 B9 MEM_B_DQ<47> 17 32 68 MEM_B_A<3> N2 A3 DQ3 H3 MEM_B_DQ<51> 17 32 68
NC R3 RFU DQ14 B1 MEM_B_DQ<14> 17 32 68 NC R3 RFU DQ14 B1 MEM_B_DQ<30> 17 32 68 NC R3 RFU DQ14 B1 MEM_B_DQ<46> 17 32 68 MEM_B_A<2> M7 A2 DQ2 H7 MEM_B_DQ<50> 17 32 68
32 17 MEM_B_A<13> R8 NC/A13 DQ13 D9 MEM_B_DQ<13> 17 32 MEM_B_A<13> R8 NC/A13 DQ13 D9 MEM_B_DQ<29> 17 32 MEM_B_A<13> R8 NC/A13 DQ13 D9 MEM_B_DQ<45> 17 32 68 MEM_B_A<1> M3 A1 DQ1 G2 MEM_B_DQ<49> 17 32 68
B 68
32
68
33
17
33
MEM_B_A<12> R2 A12 DQ12 D1 MEM_B_DQ<12>
68
17 32
68
MEM_B_A<12> R2 A12 DQ12 D1 MEM_B_DQ<28>
68
17
68
32 MEM_B_A<12> R2 A12 DQ12 D1 MEM_B_DQ<44> 17 32 68 MEM_B_A<0> M8 A0
Bit swizzle per byte?
DQ0 G8 MEM_B_DQ<48> 17 32 68 B
32 17 MEM_B_A<11> P7 A11 OMIT DQ11 D3 MEM_B_DQ<11> 17 32 MEM_B_A<11> P7 A11 OMIT DQ11 D3 MEM_B_DQ<27> 17 32 MEM_B_A<11> P7 A11 OMIT DQ11 D3 MEM_B_DQ<43> 17 32 68
68 33 68 68
32 17 MEM_B_A<10> M2 A10/AP DQ10 D7 MEM_B_DQ<10> 17 32 MEM_B_A<10> M2 A10/AP DQ10 D7 MEM_B_DQ<26> 17 32 MEM_B_A<10> M2 A10/AP DQ10 D7 MEM_B_DQ<42> 17 32 68 MEM_B_BS<2> L1 NC/BA2 LDQS F7 MEM_B_DQS_P<6> 17 32 68
68 33 68 68
32 17
68 33
MEM_B_A<9> P3
P8
A9 U3240 DQ9 C2
C8
MEM_B_DQ<9> 17 32
68
MEM_B_A<9> P3
P8
A9 U3250 DQ9 C2
C8
MEM_B_DQ<25> 17
68
32 MEM_B_A<9> P3
P8
A9 U3260 DQ9 C2
C8
MEM_B_DQ<41> 17 32 68 MEM_B_BS<1> L3 BA1
L2 BA0
LDQS* E8 MEM_B_DQS_N<6> 17 32 68
32 17 MEM_B_A<8> A8 DQ8 MEM_B_DQ<8> 17 32 MEM_B_A<8> A8 DQ8 MEM_B_DQ<24> 17 32 MEM_B_A<8> A8 DQ8 MEM_B_DQ<40> 17 32 68 MEM_B_BS<0> UDQS B7 MEM_B_DQS_P<7> 17 32 68
68 33
32 17 MEM_B_A<7> P2 A7
68
17 32 MEM_B_A<7> P2 A7
68
17 32 MEM_B_A<7> P2 A7
64MX16 DQ7 F9 MEM_B_DQ<39> 17 32 68 UDQS* A8 MEM_B_DQS_N<7> 17 32 68
68 33
68
68
N7 FBGA F1 MEM_CLK_P<4> J8 CK
32 17 A6 DQ6 17 32 A6 DQ6 17 32 MEM_B_A<6> A6 DQ6 MEM_B_DQ<38> 17 32 68
68 33
N3 MT47H64M16 68
N3 MT47H64M16 68
N3 MT47H64M16
32 17 MEM_B_A<5> A5 DQ5 H9 MEM_B_DQ<5> 17 32 MEM_B_A<5> A5 DQ5 H9 MEM_B_DQ<21> 17 32 MEM_B_A<5> A5 DQ5 H9 MEM_B_DQ<37> 17 32 68 MEM_CLK_N<4> K8 CK*
68 33 68 68
32 17 MEM_B_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_B_DQ<4> 17 32 MEM_B_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_B_DQ<20> 17 32 MEM_B_A<4> N8 A4 (2 OF 2) DQ4 H1 MEM_B_DQ<36> 17 32 68 MEM_CKE<4> K2 CKE
68 33 68 68
32 17 MEM_B_A<3> N2 A3 DQ3 H3 MEM_B_DQ<3> 17 32 MEM_B_A<3> N2 A3 DQ3 H3 MEM_B_DQ<19> 17 32 MEM_B_A<3> N2 A3 DQ3 H3 MEM_B_DQ<35> 17 32 68 MEM_CS_L<3> L8 CS*
68 33 68 68
32 17 MEM_B_A<2> M7 A2 DQ2 H7 MEM_B_DQ<2> 17 32 MEM_B_A<2> M7 A2 DQ2 H7 MEM_B_DQ<18> 17 32 MEM_B_A<2> M7 A2 DQ2 H7 MEM_B_DQ<34> 17 32 68 NC E2 NC
68 33 68 68
32 17 MEM_B_A<1> M3 A1 Bit swizzle per byte? DQ1 G2 MEM_B_DQ<1> 17 32 MEM_B_A<1> M3 A1 Bit swizzle per byte? DQ1 G2 MEM_B_DQ<17> 17 32 MEM_B_A<1> M3 A1 Bit swizzle per byte? DQ1 G2 MEM_B_DQ<33> 17 32 68 MEM_ODT<3> K9 ODT NC A2 NC
68 33 68 68
32 17 MEM_B_A<0> M8 A0 DQ0 G8 MEM_B_DQ<0> 17 32 MEM_B_A<0> M8 A0 DQ0 G8 MEM_B_DQ<16> 17 32 MEM_B_A<0> M8 A0 DQ0 G8 MEM_B_DQ<32> 17 32 68
68 33 68 68
68 33 32 17 MEM_B_RAS_L K7 RAS*
32 17 MEM_B_BS<2> L1 NC/BA2 LDQS F7 MEM_B_DQS_P<0> 17 32 MEM_B_BS<2> L1 NC/BA2 LDQS F7 MEM_B_DQS_P<2> 17 32 MEM_B_BS<2> L1 NC/BA2 LDQS F7 MEM_B_DQS_P<4> 17 32 68 MEM_B_CAS_L L7 CAS*
68 33 68 68
32 17 MEM_B_BS<1> L3 BA1 LDQS* E8 MEM_B_DQS_N<0> 17 32 MEM_B_BS<1> L3 BA1 LDQS* E8 MEM_B_DQS_N<2> 17 32 MEM_B_BS<1> L3 BA1 LDQS* E8 MEM_B_DQS_N<4> 17 32 68 MEM_B_WE_L K3 WE*
68 33 68 68
32 17 MEM_B_BS<0> L2 BA0 UDQS B7 MEM_B_DQS_P<1> 17 32 MEM_B_BS<0> L2 BA0 UDQS B7 MEM_B_DQS_P<3> 17 32 MEM_B_BS<0> L2 BA0 UDQS B7 MEM_B_DQS_P<5> 17 32 68
68 33 68 68
UDQS* A8 MEM_B_DQS_N<1> 17 32 68 UDQS* A8 MEM_B_DQS_N<3> 17 32 68 UDQS* A8 MEM_B_DQS_N<5> 17 32 68 MEM_B_DM<7> B3 UDM
32 16 MEM_CLK_P<4> J8 CK 68 33 32 16 MEM_CLK_P<4> J8 CK 68 33 32 16 MEM_CLK_P<4> J8 CK 68 32 17 MEM_B_DM<6> F3 LDM
68 33
32 16 MEM_CLK_N<4> K8 CK* 68 33 32 16 MEM_CLK_N<4> K8 CK* 68 33 32 16 MEM_CLK_N<4> K8 CK* VSS VSSDL VSSQ
68 33
32 16 MEM_CKE<4> K2 CKE 68 33 32 16 MEM_CKE<4> K2 CKE 68 33 32 16 MEM_CKE<4> K2 CKE
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
68 33
32 16 MEM_CS_L<3> L8 CS* 68 33 32 16 MEM_CS_L<3> L8 CS* 68 33 32 16 MEM_CS_L<3> L8 CS*
68 33
68
16 6 MEM_ODT<3> K9 ODT NC A2 NC 68 33 32 16 6 MEM_ODT<3> K9 ODT NC A2 NC 68 33 32 16 6 MEM_ODT<3> K9 ODT NC A2 NC
33 32 DDR2 DRAM Channel B
MEM_B_RAS_L K7 RAS* MEM_B_RAS_L K7 RAS* MEM_B_RAS_L K7 RAS*
A 32 17
68 33
32 17
68 33
MEM_B_CAS_L L7 CAS*
68 33 32 17
68 33 32 17 MEM_B_CAS_L L7 CAS*
68 33 32 17
68 33 32 17 MEM_B_CAS_L L7 CAS*

SYNC_DATE=(MASTER)
A
32 17 MEM_B_WE_L K3 WE* 68 33 32 17 MEM_B_WE_L K3 WE* 68 33 32 17 MEM_B_WE_L K3 WE*
68 33
32 17 MEM_B_DM<1> B3 UDM 68 32 17 MEM_B_DM<3> B3 UDM 68 32 17 MEM_B_DM<5> B3 UDM AGREES TO THE FOLLOWING
68
32 17 MEM_B_DM<0> F3 LDM 68 32 17 MEM_B_DM<2> F3 LDM 68 32 17 MEM_B_DM<4> F3 LDM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
68
VSS VSSDL VSSQ VSS VSSDL VSSQ VSS VSSDL VSSQ II NOT TO REPRODUCE OR COPY IT
A3
E3
J3
N1
P9
J7
A7
B2
A3
E3
J3
N1
P9
J7
A7
B2
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
B8
D2
D8
E7
F2
F8
H2
H8
B8
D2
D8
E7
F2
F8
H2
H8
D 051-7230 B.0.0

NONE 32 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
One cap for each side of every RPAK, one cap for every two discrete resistors
BOMOPTION shown at the top of each group applies to every part below it
MEM CLOCK TERMINATION 72 55 8 7 6 PP0V9_S0
Place one resistor at each end of Y split 68 32 16 6 MEM_ODT<3> RP3300 56 1 8

IN
68 31 16 MEM_CLK_N<0> 68 32 17 MEM_B_RAS_L RP3300 56 2 7 5% 1/32W 4X0201
IN 1 1
MEM_B_BS<1> RP3300 56 3 6 5% 1/32W 4X0201 C3300 C3301
68 32 17 IN
1 1 0.1UF 0.1UF
R3390 R3391 68 32 17 IN MEM_B_BS<2> RP3300 56 4 5 5% 1/32W 4X0201 10% 10%
200 200 5% 1/32W 4X0201
6.3V
2 X5R
6.3V
2 X5R
5% 5%
D 1/20W
MF
2 201
1/20W
MF
2 201
201 201
D
68 31 16 MEM_CLK_P<0>
RP3301 NC 56 1 8
68 32 17 MEM_B_A<12> RP3301 56 2 7 5% 1/32W 4X0201

IN 1 1
RP3301 56 3 6 5% 1/32W 4X0201 C3302 C3303
RP3301 5% 1/32W 4X0201
0.1UF 0.1UF
68 32 17 IN MEM_B_A<13> 56 4 5 10%
6.3V
10%
6.3V
5% 1/32W 4X0201 2 X5R 2 X5R
201 201
68 31 16 MEM_CLK_N<1>
1 1 RP3302 56 1 8
R3392 R3393 68 31 17 IN MEM_A_BS<1>
RP3302 5% 1/32W 4X0201
200 200 68 31 17 IN MEM_A_A<2> 56 2 7
1 1
5%
1/20W
5%
1/20W MEM_A_A<10>
RP3302 56 3 6 5% 1/32W 4X0201 C3304 C3305
68 31 17 IN 0.1UF 0.1UF
MF MF
MEM_A_A<3>
RP3302 56 4 5 5% 1/32W 4X0201 10% 10%
2 201 2 201 68 31 17 IN
5% 1/32W 4X0201 2
6.3V 6.3V
2 X5R
MEM_CLK_P<1> X5R
68 31 16 201 201
68 31 17 MEM_A_A<4>
RP3303 56 1 8
IN
68 31 17 MEM_A_A<11>
RP3303 56 2 7 5% 1/32W 4X0201
IN 1 1
MEM_A_A<12>
RP3303 56 3 6 5% 1/32W 4X0201 C3306 C3307
68 31 17 IN
68 32 16 MEM_CLK_N<3> RP3303 5% 1/32W 4X0201
0.1UF 0.1UF
56 4 5 10%
6.3V
10%
1 1 5% 1/32W 4X0201 2 X5R 2 6.3V

X5R
R3394 R3395 201 201
200 200
5% 5%
1/20W
MF
1/20W
MF 68 31 17 MEM_A_A<7>
RP3304 56 1 8
IN
2 201 2 201 68 31 17 MEM_A_A<13>
RP3304 56 2 7 5% 1/32W 4X0201
IN 1 1
68 32 16 MEM_CLK_P<3> RP3304 56 3 6 5% 1/32W 4X0201 C3308 C3309
68 31 17 IN MEM_A_A<8> 0.1UF 0.1UF
68 31 17 MEM_A_A<9>
RP3304 56 4 5 5% 1/32W 4X0201 10% 10%
IN 6.3V 6.3V
5% 1/32W 4X0201 2 X5R 2 X5R
201 201
C C
68 32 16 MEM_CLK_N<4>
68 31 17 MEM_A_A<6>
RP3305 56 1 8
IN
1 1 RP3305 56 2 7 5% 1/32W 4X0201 1 C3310 1 C3311
R3396 R3397 68 31 17 IN MEM_A_A<5>
RP3305 56 5% 1/32W 4X0201 0.1UF 0.1UF
200 200 68 31 17 IN MEM_A_A<0> 3 6
10% 10%
5%
1/20W
5%
1/20W 68 31 17 MEM_A_CAS_L
RP3305 56 4 5 5% 1/32W 4X0201
2 6.3V 2 6.3V
IN X5R X5R
MF MF 5% 1/32W 4X0201 201 201
2 201 2 201
68 32 16 MEM_CLK_P<4>
68 31 16 6 MEM_ODT<1>
RP3306 56 1 8
IN
68 31 17 MEM_A_WE_L
RP3306 56 2 7 5% 1/32W 4X0201
IN
68 31 17 MEM_A_RAS_L
RP3306 56 3 6 5% 1/32W 4X0201 1 C3312 1 C3313
IN
68 31 17 MEM_A_BS<2>
RP3306 56 4 5 5% 1/32W 4X0201 0.1UF 0.1UF
IN 10% 10%
5% 1/32W 4X0201 6.3V
2 X5R 2 6.3V
X5R
201 201
68 32 16 MEM_CS_L<2>
RP3307 56 1 8
IN
68 32 17 MEM_B_A<1>
RP3307 56 2 7 5% 1/32W 4X0201
IN 1 1
RP3307 56 3 6 5% 1/32W 4X0201 C3314 C3315
68 32 17 IN MEM_B_A<2> 0.1UF 0.1UF
68 32 16 MEM_CS_L<3>
RP3307 56 4 5 5% 1/32W 4X0201 10% 10%
IN 6.3V 6.3V
5% 1/32W 4X0201 2 X5R 2 X5R
201 201
68 32 17 MEM_B_A<4>
RP3308 56 1 8
IN
68 32 17 MEM_B_A<8>
RP3308 56 2 7 5% 1/32W 4X0201
IN 1 1
RP3308 56 3 6 5% 1/32W 4X0201 C3316 C3317
68 32 17 IN MEM_B_A<6> 0.1UF 0.1UF
68 32 17 MEM_B_A<3>
RP3308 56 4 5 5% 1/32W 4X0201 10% 10%
B IN
5% 1/32W 4X0201 2
6.3V
X5R
201
6.3V
2 X5R
201
B
68 32 17 MEM_B_A<0>
RP3309 56 1 8
IN
68 32 17 MEM_B_A<9>
RP3309 56 2 7 5% 1/32W 4X0201
IN 1 1
RP3309 56 3 6 5% 1/32W 4X0201 C3318 C3319
68 32 17 IN MEM_B_A<7> 0.1UF 0.1UF
68 32 17 MEM_B_A<11>
RP3309 56 4 5 5% 1/32W 4X0201 10% 10%
IN 6.3V 6.3V
5% 1/32W 4X0201 2 X5R 2 X5R
201 201
68 32 17 MEM_B_A<10>
RP3310 56 1 8
IN
68 32 16 MEM_CKE<4>
RP3310 56 2 7 5% 1/32W 4X0201
IN 1 1
RP3310 56 3 6 5% 1/32W 4X0201 C3320 C3321
68 32 16 6 IN MEM_ODT<2> 0.1UF 0.1UF
68 32 17 MEM_B_A<5>
RP3310 56 4 5 5% 1/32W 4X0201 10% 10%
IN 6.3V 6.3V
5% 1/32W 4X0201 2 X5R 2 X5R
201 201
68 32 17 MEM_B_CAS_L RP3311 56 1 8
IN
68 32 17 MEM_B_WE_L RP3311 56 2 7 5% 1/32W 4X0201
IN 1 1
MEM_CKE<3> RP3311 56 3 6 5% 1/32W 4X0201 C3322 C3323
68 32 16 IN
RP3311 5% 1/32W 4X0201
0.1UF 0.1UF
68 32 17 IN MEM_B_BS<0> 56 4 5 10% 10%
5% 1/32W 4X0201 2 6.3V
X5R 2 6.3V
X5R
201 201
68 31 16 MEM_CS_L<0> RP3312 56 1 8
IN
68 31 16 6 MEM_ODT<0> RP3312 56 2 7 5% 1/32W 4X0201
Memory Active Termination
IN
68 31 16 MEM_CKE<1> RP3312 56 3 6 5% 1/32W 4X0201
IN 1 1
RP3312 C3324 C3325
A 68 31 16
68 31 17
IN MEM_CKE<0>
MEM_A_A<1> RP3313
56
56
4
1
5
8
5% 1/32W
5% 1/32W
4X0201
4X0201 0.1UF
10%
0.1UF
10%
A
IN 6.3V 6.3V
68 31 17 MEM_A_BS<0> RP3313 56 3 6 5% 1/32W 4X0201 2 X5R 2 X5R
IN 201 201
68 31 16 MEM_CS_L<1> RP3313 56 4 5 5% 1/32W 4X0201 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
IN
RP3313 NC56 2 7 5% 1/32W 4X0201 AGREES TO THE FOLLOWING
5% 1/32W 4X0201 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
LAYOUT NOTE:PLACE ONE CAP CLOSE TO EVERY TWO PULLUP RESISTORS TERMINATED III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TO PP0V9_S0_MEM_TERM
D 051-7230 B.0.0

NONE 33 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3
72 68 55 OMIT OMIT OMIT
1 C3490 1 C3491 1 C3492
10UF 10UF 10UF
20% 20% 20%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
603 603 603
D 51 35 34 32 31 21 18 16 8 7 6
72 68 55
PP1V8_S3 35 34 32 31 21 18 16 8 7 6PP1V8_S3
72 68 55 51
D
OMIT OMIT OMIT OMIT OMIT OMIT
C3400 1 C3410 1 C3420 1 C3430 1 C3440 1 C3450
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF

1 C3401 1 C3411 1 C3421 1 C3431 1 C3441 1 C3451
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
OMIT OMIT
1 C3412 1 C3442
2.2UF 2.2UF
2 CAPS ALONG PACKAGE EDGE 20% 20% 2 CAPS ALONG PACKAGE EDGE
2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF
C C
1 C3404 1 C3414 1 C3424 1 C3434 1 C3444 1 C3454
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF

1 C3405 1 C3415 1 C3425 1 C3435 1 C3445 1 C3455
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
OMIT OMIT
1 C3416 1 C3446
2.2UF 2.2UF
20% 20%
6.3V 6.3V
2 CERM 2 CERM
402-LF 402-LF
COLUMN OF THREE CAPS BETWEEN PACKAGES COLUMN OF THREE CAPS BETWEEN PACKAGES
B APPROXIMATE CAP ARRANGEMENT

B
TWO 0402 CAPS ALONG PACKAGE EDGE
THREE 0603 CAPS SPREAD TO COVER ALL 8 PARTS
DDR2 BYPASSING 1
A SYNC_MASTER=MEMORY

A
COLUMN OF THREE 0402 CAPS BETWEEN PACKAGES SIZE DRAWING NUMBER REV.
D 051-7230 B.0.0

NONE 34 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
51 35 34 32 31 21 18 16 8 7 6 PP1V8_S3
72 68 55 OMIT OMIT OMIT
1 C3590 1 C3591 1 C3592
10UF 10UF 10UF
20% 20% 20%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
603 603 603
D 51 35 34 32 31 21 18 16 8 7 6
72 68 55
PP1V8_S3 51 35 34 32 31 21 18 16 8 7 6
72 68 55
PP1V8_S3 D
1 C3500 1 C3510 1 C3520 1 C3530 1 C3540 1 C3550
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF

1 C3501 1 C3511 1 C3521 1 C3531 1 C3541 1 C3551
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
OMIT OMIT
1 C3512 1 C3542
2.2UF 2.2UF
2 CAPS ALONG PACKAGE EDGE 20% 20% 2 CAPS ALONG PACKAGE EDGE
2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF
C C
1 C3504 1 C3514 1 C3524 1 C3534 1 C3544 1 C3554
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF

1 C3505 1 C3515 1 C3525 1 C3535 1 C3545 1 C3555
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
OMIT OMIT
1 C3516 1 C3546
2.2UF 2.2UF
20% 20%
6.3V 6.3V
2 CERM 2 CERM
402-LF 402-LF
COLUMN OF THREE CAPS BETWEEN PACKAGES COLUMN OF THREE CAPS BETWEEN PACKAGES
B B
APPROXIMATE CAP ARRANGEMENT
TWO 0402 CAPS ALONG PACKAGE EDGE
THREE 0603 CAPS SPREAD TO COVER ALL 8 PARTS
DDR2 BYPASSING 2
A SYNC_MASTER=MEMORY

A
COLUMN OF THREE 0402 CAPS BETWEEN PACKAGES D 051-7230 B.0.0

NONE 35 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
CRITICAL
Q4101
FDC638P
SM-LF
M93 WIRELESS AIRPORT & BT CONNECTOR
6
5
44 43 36 28 27 26 25 24 8 7 6 PP3V3_S5 4
72 60 58 57 56 51 49 2 72 7 6 PP3V3_S3_AP_AUX
44 43 36 28 27 26 25 24 8 7 6 PP3V3_S5 1
72 60 58 57 56 51 49 MIN_LINE_WIDTH=0.2MM
OMIT MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.3V
R4104
1 C4108 1 C4107 1 C4109 1 C4110

100K 2
1/20W
1 C4111 3 0.1UF 0.1UF 10UF 0.1UF

201
10% 10% 20% 10%

5%
MF
33000PF 2 6.3V 2 6.3V 2 6.3V 2 6.3V

10% X5R X5R X5R X5R
2 6.3V 201 201 603 201
72 60 58 51 48 44 42 8 7 6 PP3V3_S3
1
X5R
R4105 201 C4112
6 PM_WLAN_EN_L 2
100K 1 PM_WLAN_EN_L_SS
2
6
5%
0.01UF
C Q4102 D 6 Q4102 D 3
1/20W
MF
201
10V
201
10%
C
X5R
SSM6N15FE SSM6N15FE
SOT563 SOT563
CRITICAL
L4101
90-OHM-100MA
2 G
1 S 5 G S 4
PM_SLP_S3_L 1210-4SM1
55 51 42 41 37 25 7 6 SYM_VER-1
42 41 9 6
SMC_ADAPTER_EN PM_WLAN_EN_L2
6 70 36 24 6 PCIE_E_D2R_N 1 4
CRITICAL
OUT
J4100
D 6 CPB6330-0101F
Q4103 70 36 24 6 OUT PCIE_E_D2R_P 2 3
F-ST-SM
SSM6N15FE 31 32
44 43 36 28 27 26 25 24 8 7 6PP3V3_S5 SOT563
72 60 58 57 56 51 49
CRITICAL
L4100 1 2
R4106
NOSTUFF
100K 2
90-OHM-100MA
2 G 1210-4SM1 PCIE_E_D2R_N_F 3 4 CK505_SRC_CLKREQ6_L
S 1 7 6
1/20W
OUT 6 7 29
SYM_VER-1
201
7
5%
MF
6 PCIE_E_D2R_P_F 5 6 PCIE_WAKE_L 6 7 25
PCIE_CLK100M_MINI_P 1 4 IN
71 30 29 6 IN 7 8 AIRPORT_RST_L 6 7 28
PM_WLAN_EN_L1 IN
6
R4101 201 1/20W
1
7
6 PCIE_CLK100M_MINI_P_F 9 10 MF 5%
WOW_EN PCIE_CLK100M_MINI_N 2 3 7 6 PCIE_CLK100M_MINI_N_F 11 12 7
SMB_AIRPORT_CONN_CLK 1
0 2 SMBUS_SMC_A_S3_SCL
24 13 7 6 71 30 29 6 6 6 7 40 41 44 71
IN BI
13 14 7
6 SMB_AIRPORT_CONN_DATA 1
0 2 SMBUS_SMC_A_S3_SDA
Q4103 D 3 BI 6 7 40 41 44 71
CRITICAL 15 16
SSM6N15FE L4103 R4102 201 1/20W
MF 5%
SOT563 90-OHM-100MA 17 18
1210-4SM1
SYM_VER-1 19 20
69 24 9 6 USB2_AIRPORT_P 4 1 69 6 USB2_AIRPORT_P_F 21 22
BI
5 G S 4 23 24
25 26
69 24 9 6 USB2_AIRPORT_N 3 2 69 6 USB2_AIRPORT_N_F
BI 27 28
B PM_S4_STATE_L
29 30 B
58 41 25 6 CRITICAL
L4102
90-OHM-100MA
33 34
1210-4SM1
C4100 SYM_VER-1
70 36 24 6 PCIE_E_R2D_C_N 1 2 0.1UF 6 PCIE_E_R2D_N 1 4 76 PCIE_E_R2D_C_N_F

IN X5R 201
10% 6.3V
C4101 6 PCIE_E_R2D_P 2 3 76 PCIE_E_R2D_C_P_F

70 36 24 6 PCIE_E_R2D_C_P 1 2 0.1UF
IN X5R 201
10% 6.3V
PLACE FILTERS NEAR CONNECTOR
70 36 24 6 PCIE_E_D2R_N PCIE_E_D2R_N 6 24 36 70
PLACE C4100,C4101 < 250 MILS FROM SB
MAKE_BASE=TRUE
70 36 24 6 PCIE_E_D2R_P
70 36 24 6 PCIE_E_R2D_C_N
PCIE_E_D2R_P
PCIE_E_R2D_C_N MAKE_BASE=TRUE
MAKE_BASE=TRUE
6 24 36 70
6 24 36 70
APN:516S0580
70 36 24 6
PCIE_E_R2D_C_P PCIE_E_R2D_C_P 6 24 36 70
MAKE_BASE=TRUE
Wireless M93 Connector

A
D 051-7230 B.0.0

NONE 36 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Micro DVI, USB, to RIO Hatch Assembly
CRITICAL
J4200
54102
F-ST-SM
63 7 6 HDMI_HOST 1 2 PP5V_S0_DVIPORT 6 7 63 72
C 63 7 6 DVI_HOST 3
5
4
6 VGA_VSYNC 6 7 63
Audio Connector C
7 8 VGA_HSYNC 6 7 63
67 63 7 6 TMDS_TX_CONN_CLK_N 9 10
67 63 7 6 TMDS_TX_CONN_CLK_P 11 12 72 64 59 56 50 45 8 7 6 PPBUS_G3H CRITICAL

13 14 J4260
63 7 6 TMDS_TX_CONN_N<0> 15 16 TMDS_DDC_SDA 6 7 61 62 63 67
QT500166-L020
M-ST-SM
6 TMDS_TX_CONN_P<0> TMDS_DDC_SCL
63 7
17 18 6 7 61 62 63 67
69 23 9 7 6 HDA_SYNC 1 2 HDA_SDIN0 6 7 9 23 69
19 20 IN OUT
3 4
63 7 6 TMDS_TX_CONN_N<1> 21 22 VGA_B 6 7 63 67
5 6
69 23 9 7 6 IN HDA_SDOUT AUD_MIC_CLK IN 6 7 60
6 TMDS_TX_CONN_P<1>
63 7
23 24
69 23 9 6 HDA_RST_L 7 8
25 26 VGA_G IN
6 7 63 67
55 51 42 41 36 25 7 6 PM_SLP_S3_L 9 10 AUD_MIC_DATA 6 7 60
TMDS_TX_CONN_N<2> 27 28 IN OUT
63 7 6
11 12
63 7 6 TMDS_TX_CONN_P<2> 29 30 VGA_R 6 7 63 67
13 14
31 32
HDA_BIT_CLK IN 6 7 9 23 69
15 16
33 34 TMDS_HTPLG 6 7 61 63
69 39 7 6 USB2_EXTA_F_P 35 36 PP5V_S3_USB2_EXTA_F 6 7 39 72
69 39 7 6 USB2_EXTA_F_N 37 38
39 40
516S0350
B B
516S0632
Hatch and Audio Connectors


SYNC_DATE=(MASTER)
A
D 051-7230 B.0.0

NONE 37 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
63 62 61 51 47 38 8 6 PP3V3_B_S0
OMIT
1 C4400
10UF
20% CRITICAL
6.3V
2 X5R
603 J4400
AXK740327G
F-ST-SM
41
69 38 23 6 IDE_IRQ14
1 2
1
38 6 IDE_RESET_BUF_L
3 4 IDE_PDD<7> 6 23 69
R4400
5 6
10K
69 23 6 IDE_PDD<8> IDE_PDD<6> 6 23 69 5%
7 8 1/20W
69 23 6 IDE_PDD<9> IDE_PDD<5> 6 23 69 MF
9 10 2 201
C 69 23
69 23
6 IDE_PDD<10>
6 IDE_PDD<11>
11 12
IDE_PDD<4>
IDE_PDD<3>
6 23 69
6 23 69
C
13 14
69 23 6 IDE_PDD<12> 15 16 IDE_PDD<2> 6 23 69
69 23 6 IDE_PDD<13> 17 18 IDE_PDD<1> 6 23 69
69 23 6 IDE_PDD<14> 19 20 IDE_PDD<0> 6 23 69
69 23 6 IDE_PDD<15>
21 22 IDE_PDDREQ 6 23 69
69 23 6 IDE_PDIOW_L
23 24 IDE_PDIOR_L 6 23 69
25 26
69 38 23 6 IDE_PDIORDY 27 28 IDE_PDDACK_L 6 23 69
69 38 23 6 IDE_IRQ14
29 30 IDE_PDA<1> 6 23 69 62 61 51 47 38 8 6PP3V3_B_S0
63
NC31 32 IDE_PDA<0> 6 23 69
1
69 23 6 IDE_PDA<2> 33 34 IDE_PDCS1_L 6 23 69 R4401
35 36 NC 4.7K
69 23 6 IDE_PDCS3_L 1%
37 38 1/20W
MF
39 40 2 201
69 38 23 6 IDE_PDIORDY
42
PP3V3_B_S0 6 8 38 47 51 61 62 63
1
R4402
100K
B 5%
1/20W
MF
1
5 MC74VHC1G09
B
2
201
B SC70
4
U4400Y IDE_RESET_BUF_L
24 6 IDE_RESET_L 2
A
6 38
516S0594
3
3.3V GPIO54 is 5V tolerant.
PATA HDD CONNECTOR

A
D 051-7230 B.0.0

NONE 38 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
USB 2.0 CONNECTOR
CRITICAL
PP5V_S3_USB2_EXTA_F
L4602 MIN_LINE_WIDTH=0.6MM
FERR-120-OHM-3A VOLTAGE=5V
CONNECT TO 5V S5 or S3 PER LAYOUT 0603
CRITICAL
C4610 1 ROUTE USB DATA LINES AS DIFFERENTIAL PAIRS
72 58 56 55 54 51 27 8 7 6 PP5V_S5 100UF CRITICAL
20%
OMIT 6.3V 2
POLY
L4600
90-OHM-100MA
1 C46131 C4612 B2-HF 1210-4SM1
SYM_VER-1 PP5V_S3_USB2_EXTA_F 6 67 7 37 39 72
10uF 0.1UF 37 39 72
20%
6.3V
10%
6.3V 69 39 9 6 USB2_MUXED_EXTA_N 1 4 USB2_EXTA_F_N 6 7 37 69
2 X5R
603
2 X5R
201
USB2_EXTA_F_P 6
CONNECT TO RIO CONNECTOR J4200
7 37 69
69 39 9 6 USB2_MUXED_EXTA_P 2 3
1 C4602
U4600 CRITICAL 0.01UF
1
TPS2023DG4 10%
SOI D4600 2 10V
X5R
2 IN_0 OUT_0 8 PP5V_S3_USB2_EXTA SC-75 201
CRITICAL MIN_LINE_WIDTH=0.6MM
3 OUT_1 7 MIN_NECK_WIDTH=0.2MM RCLAMP0502B
IN_1 VOLTAGE=5V
3
LAYOUT NOTE:C4602 IS AN EMC BY-PASS CAP FOR J4200
C 4 EN*
OUT_2 6
5
C
OC*
GND
1
R4650
PM_SLP_S4_LS5V 6 EXTAUSB_OC_F_L 2
1K 1 EXTAUSB_OC_L
58 6 6 7 9 13 24
5%
1/20W
MF
C4650 1
201 0.47UF
10%
6.3V
CERM-X5R 2
402
CURRENT LIMIT TO 1.5A CONTINUOUS
B B
USB/SMC MUX USB2_MUXED_EXTA_P 6 9 39 69
USB2_MUXED_EXTA_N 6 9 39 69
43 42 41 40 28 27 26 23 8 7 6 PP3V42_G3H
72 59 57 44
R4675
100
1 2 72 6 PP3V42_G3H_SMCUSBMUX_R
5% MIN_NECK_WIDTH=0.2 mm
1/20W
MF 1 C4675 VOLTAGE=3.42V
1
201
0.1UF R4677
10%
6.3V 10K
2 X5R 5%
PLACE C4675 NEAR U4675 201 1/20W
9
MF
2 201
VCC
43 42 41 6 SMC_RX_L 1 D+A CRITICAL D+ 3

6 SMC_TX_L D- 5
43 42 41 7 D-A
U4675
PI3USB10LP
69 24 9 6 USB2_EXTA_P 2 D+B TQFN
69 24 9 6 USB2_EXTA_N 6 D-B
8 OE* SEL 10 USB_DEBUGPRT_EN_L 6 41

USB EXTERNAL CONNECTORS
A GND SEL=0 CHOOSE SMC
A
4
SEL=1 CHOOSE USB NOTICE OF PROPRIETARY PROPERTY

D 051-7230 B.0.0

NONE 39 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D IPD Connector D
PP5V_S3_TOPCASE_F 6 7 40
OMIT
1 C4801 1 C4800
0.1UF 2.2UF
10% 20%
6.3V 6.3V
2 X5R 2 CERM
6 PP3V42_G3H_IPD_F
201 402-LF
40 7
CRITICAL
72 40 7 6 PP5V_S0_KBDLED_F J4800
51338-0249
F-ST-SM
25 26
1 2 SMC_LID 6 7 41 42
41 7 6 SMC_SYS_LED 3 4
5 6
71 44 41 36 7 6 BI SMBUS_SMC_A_S3_SCL 7 8
71 44 41 36 7 6 BI SMBUS_SMC_A_S3_SDA 9 10 SMC_SYS_KBDLED 6 7 41
11 12
13 14 USB_IR_N BI 6 7 9 24 69
C R4831
15
17
16
18
USB_IR_P BI 6 7 9 24 69 C
10K
57 42 LSOC_PRESS_H 2 1 LSOC_PRESS_H_R 19 20 USB2_WSPRING_N BI 6 7 9 24 69
5% 42 41 40 7 6 SMC_ONOFF_L 21 22 USB2_WSPRING_P BI 6 7 9 24 69
1/20W
MF 23 24
201
27 28
1 C4831
0.1UF
10%
6.3V
2 X5R
201 516S0591
CRITICAL
L4810
Power Button Inverter
FERR-600-OHM-0.5A
B 72 60 58 8 7 6 PP5V_S3 1 2 PP5V_S3_TOPCASE_F 6 7 40
42 41 40 39 28 27 26 23 8 7 6
72 59 57 44 43
PP3V42_G3H B
SM
MIN_LINE_WIDTH=0.2mm
MIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3V R4830 1
1 C4810 5%
1M
0.01UF 1/20W
10% MF
10V
2 X5R 201 2
201
SMC_ONOFF_H 6 42 57
Q4830
SSM3K15FV D 3 Inverted to drive SMC_RESET logic
CRITICAL SOD-VESM
L4812
600-OHM-300MA
63 53 52 51 47 43 27 22 8 7 6 PP5V_S0 1 2 PP5V_S0_KBDLED_F 6 7 40 72
72
0402
MIN_LINE_WIDTH=0.30 MM 1 G S 2
VOLTAGE=5V
1 C4812
0.01UF 42 41 40 7 6 SMC_ONOFF_L
10%
10V
2 X5R
201
CRITICAL
L4813
600-OHM-300MA
6 PP3V42_G3H PP3V42_G3H_IPD_F 6
1 2
42 41 40 39 28 27 26 23 8 7
72 59 57 44 43
0402
7 40
IPD Connector
VOLTAGE=3.42V
A 1 C4813
0.01UF NOTICE OF PROPRIETARY PROPERTY
A
10%
10V
2 X5R
201 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
D 051-7230 B.0.0

NONE 40 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
OMIT U4900
SMC
25 6 OUT PM_LAN_ENABLE B12 P10 HS82117 P60 L13 SMC_PM_G2_EN OUT 6 56 58
9 NC_SMC_RSTGATE_L A13 P11 LGA P61 K12 SMC_ADAPTER_EN OUT 6 9 36 42
52 51 28 6 IN ALL_SYS_PWRGD A12 P12 (1 OF 3) P62 K11 NC_SMC_P62 9
56 42 6 IN RSMRST_PWRGD B13 P13 P63 J12 NC_SMC_P63 9
9 NC_SMC_P14 D11 P14 P64 K13 NC_SMC_P64 9
D 25 6 OUT PM_RSMRST_L C13 P15 P65 J10 PM_LAN_PWRGD IN 6 42 D

52 6 OUT IMVP_VR_ON C12 P16 P66 J11 SMC_PROCHOT_3_3_L IN 6 42
25 6 OUT PM_PWRBTN_L D10 P17 P67 H12 NC_SMC_P67 9
9 NC_SMC_P20 D13 P20 P70 N10 SMC_BATTPACK_STAT IN 6 42
9 NC_SMC_P21 E11 P21 P71 M11 SMC_ACIN_VSENSE IN 6 45
9 NC_SMC_P22 D12 P22 P72 L10 SMC_GPU_ISENSE IN 6 53
9 NC_SMC_P23 F11 P23 P73 N11 SMC_GPU_VSENSE IN 6 45
9 OUT NC_SMC_BATT_TRICKLE_EN_L E13 P24 P74 N12 SMC_DCIN_ISENSE IN 6 59
42 6 OUT SMC_BATT_CHG_EN E12 P25 P75 M13 SMC_PBUS_VSENSE IN 6 45
9 NC_SMC_P26 F13 P26 P76 N13 SMC_BATT_ISENSE IN 6 59
9 NC_SMC_P27 E10 P27 P77 L12 SMC_PBUS_ISENSE IN 6 59
43 23 6 BI LPC_AD<0> A9 P30 P80 A7 SMC_WAKE_SCI_L OUT 6 7 13 25 PP3V3_S5_AVREF_SMC

72 42 6
43 23 6 BI LPC_AD<1> D9 P31 P81 B6 NC_SMC_P81 9 PP3V42_G3H
43 42 40 39 28 27 26 23 8 7 6
72 59 57 44
43 23 6 BI LPC_AD<2> C8 P32 P82 C7 PM_CLKRUN_L OUT 6 25 43
43 23 6 BI LPC_AD<3> B7 P33 P83 D5 PM_SUS_STAT_L IN 6 25 43
43 23 6 IN LPC_FRAME_L A8 P34 P84 A6 SMC_TX_L OUT 6 39 41 42 43 C4902 1 1

C4903 1 C4904 1 C4905
28 6 IN SMC_LRESET_L D8 P35 P85 B5 SMC_RX_L IN 6 39 41 42 43 22UF 0.1UF 0.1UF 0.1UF
20% 10% 10% 10%
71 30 6 IN PCI_CLK33M_SMC D7 P36 P86 C6 (OC) SMBUS_SMC_MGMT_SCL BI 6 44 48 71 6.3V 6.3V 6.3V 6.3V
CERM
2 2 X5R 2 X5R
2 X5R
43 25 6 BI INT_SERIRQ D6 P37 805 201 201 201
P90 J4 SMC_ONOFF_L IN 6 7 40 42 PLACEMENT_NOTE=Place C4907 close to U4900 pin E1
9 NC_SMC_GFX_THROTTLE_L D4 P40 P91 G3 SMC_BC_ACOK IN 6 42 50 59
9 NC_SMC_P41 A5 P41 P92 H2 SMC_BS_ALRT_L IN 6 7 42 50 6 SMC_VCL

R4999
71 48 44 6 BI SMBUS_SMC_MGMT_SDA (OC) B4 P42 P93 G1 PM_SLP_S3_L IN 6 7 25 36 37 42 51 55 4.7
1 2 72 6 PP3V3_S5_SMC_AVCC
9 NC_SMC_P43 A1 P43 P94 H4 PM_S4_STATE_L IN 6 25 36 58 MIN_LINE_WIDTH=0.25 MM C4907 1
M12
H10
L11
5% MIN_NECK_WIDTH=0.20 MM
NC_SMC_P44 C2 P44 P95 G4 PM_SLP_S5_L
B1
M1
E1
9 IN 6 25 42 1/20W VOLTAGE=3.3V
0.47UF
MF 1 C4900 10%
9 NC_SMC_ENRGYSTR_LDO_EN B2 P45 P96 F4 SMC_SUS_CLK IN 6 42 201 6.3V
C 9 NC_SMC_P46
SMC_SYS_KBDLED
C1
C3
P46
P47
P97 F1 (OC) SMBUS_SMC_0_S0_SDA BI 6 7 44 46 71
2
0.1UF
10%
6.3V AVCC VCC VCL AVREF
CERM-X5R
402
2
1 1
C
40 7 6 OUT X5R
201 OMIT U4900 R4905 R4904
SMC_TX_L G2 NC E5 10K 10K
43 42 41 39 6 OUT P50 PLACEMENT_NOTE=Place R4999 close to U4900 pin M12
PLACEMENT_NOTE=Place C4900 close to U4900 pin M12
HS82117 NC 5%
1/20W
5%
1/20W
43 42 41 39 6 IN SMC_RX_L F3 P51 LGA MF MF
201
71 46 44 7 6 BI SMBUS_SMC_0_S0_SCL (OC) E4 P52 (3 OF 3) 2 2 201
MD1 D1 SMC_MD1 IN 6 43
MD2 H1 6 SMC_KBC_MDE
43 42 6 IN SMC_RESET_L D3 RES*
42 6 SMC_XTAL A3 XTAL
42 6 SMC_EXTAL A2 EXTAL NMI E3 SMC_NMI IN 6 43
ETRST H3 SMC_TRST_L IN 6 43
AVSS L9 1 1
VSS R4902 R4998
10K 10K
5% 5%
1/20W 1/20W
D2
L3
F10
B11
C5
MF MF
201 201
OMIT 2 2
U4900 2
(DEBUG_SW_1) 9 NC_SMC_PA0 N3 PA0 HS82117 PE0 K1 SMC_CASE_OPEN IN 6 42
(DEBUG_SW_2) 9 NC_SMC_PA1 N1 PA1 LGA PE1 J3 SMC_TCK IN 6 42 43 XW4900

SM
28 25 6 OUT PM_SYSRST_L (OC) M3 PA2 (2 OF 3) PE2 K2 SMC_TDI IN 6 42 43
39 6 USB_DEBUGPRT_EN_L (OC) M2 PA3 PE3 J1 SMC_TDO 6 42 43

1
OUT OUT
16 6 BI PM_EXTTS_L<0> (OC) N2 PA4 PE4 K4 SMC_TMS IN 6 42 43
B 16 6
50 42 7 6
BI
BI
PM_EXTTS_L<1>
SYS_ONEWIRE
(OC)
(OC)
L1
K3
PA5
PA6
PF0 K5 NC_SMC_PF0 9 GND_SMC_AVSS 6 42 45 53 59
B
PF1 N5 SMC_SYS_LED OUT 6 7 40
25 6 OUT PM_BATLOW_L (OC) L2 PA7
PF2 M6 SMC_LID IN 6 7 40 42
(DEBUG_SW_3) 9 NC_SMC_PB0 B8 PB0 PF3 L5 SMC_PF3 6 42
25 6 OUT SMC_RUNTIME_SCI_L C9 PB1 PF4 M5 NC_BATT_ISET 9
42 6 IN SMC_ODD_DETECT B9 PB2 PF5 N4 NC_SMC_BATT_VSET 9
9 NC_ISENSE_CAL_EN A10 PB3 PF6 L4 NC_SYS_ISET 9
9 NC_SMC_EXCARD_CP C10 PB4 PF7 M4 NC_SMC_SYS_VSET 9
9 NC_SMC_EXCARD_PWR_EN B10 PB5

PG0 M8 NC_SMC_PG0 9
9 NC_EXCARD_OC_L C11 PB6
PG1 N7 SMC_SMS_INT IN 6 9 48
9 NC_SMC_GFX_OVERTEMP_L A11 PB7
PG2 K8 (OC) SMBUS_SMC_BSA_SDA BI 6 7 44 50 59 71
47 6 OUT SMC_FAN_0_CTL G11 PC0 PG3 K7 (OC) SMBUS_SMC_BSA_SCL BI 6 7 44 50 59 71
9 NC_SMC_FAN_1_CTL G13 PC1 PG4 K6 (OC) SMBUS_SMC_A_S3_SDA BI 6 7 36 40 44 71
9 NC_SMC_FAN_2_CTL F12 PC2 PG5 N6 (OC) SMBUS_SMC_A_S3_SCL BI 6 7 36 40 44 71
9 NC_SMC_FAN_3_CTL H13 PC3 PG6 M7 (OC) SMBUS_SMC_B_S3_SDA BI 6 7 44 60
47 6 IN SMC_FAN_0_TACH G10 PC4 PG7 L6 (OC) SMBUS_SMC_B_S3_SCL BI 6 7 44 60
9 NC_SMC_FAN_1_TACH G12 PC5

PH0 E2 SMC_PROCHOT OUT 6 42
9 NC_SMC_FAN_2_TACH H11 PC6
PH1 F2 SMC_THRMTRIP OUT 6 42
9 NC_SMC_FAN_3_TACH J13 PC7
PH2 J2 NC_SMC_FWE 9
48 6 IN SMS_X_AXIS M10 PD0 PH3 A4 NC_ALS_GAIN 9
48 6 IN SMS_Y_AXIS N9 PD1 PH4 B3 NC_SMC_ENRGYSTR_LDO_PGOOD 9
48 6 IN SMS_Z_AXIS K10 PD2 PH5 C4 SMS_ONOFF_L OUT 6 48
9 NC_SMC_ANALOG_ID L8 PD3
9 NC_SMC_TEST_DAC1 M9 PD4
SMC
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
NC_SMC_TEST_DAC2 N8
A 9
9 NC_SMC_TEST_DAC3 K9
PD5
PD6
If SMS interrupt is not used, pull up to SMC rail.
SYNC_MASTER=M70

A
9 NC_ALS_RIGHT L7 PD7
D 051-7230 B.0.0

NONE 41 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SMC Reset Button / Brownout Detect SMC 1.05V to 3.3V Level Shifting
42 41 40 39 28 27 26 23 8 7 6
72 59 57 44 43
PP3V42_G3H
64 63 60 53 52
PP3V3_A_S0
C5000 1 CRITICAL2 1
R5000
24 23 22 21 19 16 13 8 7 6
51 46 44 30 29 28 27 26 25
0.1UF 1K
10%
6.3V 2
VDD 5%
1/20W PP1V05_S0
X5R
201 U5000 MF
19 18 14 13 12 11 10 8 7 6
72 54 30 27 26 23 21 1
R5078
RN5VD30A-F 2 201
D SMC_MANUAL_RST_L 5 CD
SOT23-5
OUT 1 SMC_RESET_L 6 41 43
470
5%
1/20W
D
OUT PP3V42_G3H 6 7 8 23 26 27 28 39 40 41 42
1
R5070 MF
NOSTUFF NC 4 NC 43 44 57 59 72
3.3K 2 201
1 GND
R5001 C5001 1 3 PP3V3_S3 6 7 8 36 44 48 51 58 60 72
5%
1/20W 6 41
Silk: "SMC RST" 0
5% 0.01UF MF
SMC_PROCHOT_3_3_L
Place R5001 on bottom side 10% 2 201
1/16W
MF-LF 10V 2
X5R 56 41 6 RSMRST_PWRGD R5094 1 2 100K
near board edge 2402 201 3
42 41 40 7 6 SMC_ONOFF_L R5095 1 2 100K 5
Q5077
BC847BV-X-F
43 41 39 6 SMC_TX_L R5080 1 2 10K 6 CPU_PROCHOT_BUF SOT563
Q5030 D 6 43 41 39 6 SMC_RX_L R5081 1 2 100K 4
SSM6N15FE
SOT563
43 41 6 SMC_TMS R5097 1 2 10K R5071 6
Q5077
SMC_TDO R5085 1 3.3K 2
43 41 6 2 10K 66 52 42 10 6 1 2 BC847BV-X-F
2 G S 1 43 41 6 SMC_TDI R5086 1 2 10K CPU_PROCHOT_L 5% 6 CPU_PROCHOT_L_R SOT563
43 41 6 SMC_TCK R5087 1 2 10K
1/20W
MF 1
57 40 LSOC_PRESS_H SMC_MANUAL_RST_L1 6 201
41 6 PM_LAN_PWRGD R5090 1 2 10K
Q5030 D 3
SMC_PF3 R5091 1 2 10K
SSM6N15FE 41 6
SOT563
50 41 7 6 SYS_ONEWIRE R5082 1 2 2.0K
50 42 41 7 6 SMC_BS_ALRT_L R5083 1 2 470K
5 G S 4
Q5030 will pull down SMC_ODD_DETECT R5049 1 2 10K
41 6
SMC_ONOFF_H SMC_MANUAL_RST_L in the event

57 40 6
of a keyboard SMC Reset 59 50 41 6 SMC_BC_ACOK R50841 2 10K
generated when left shift,option,and control
and the power button is depressed.
SMC_LID R5073 100K
C 41 40 7 6 1 2
C
R5006 1 2 100K PM_SLP_S5_L 6 25 41
R5092 1 2 10K SMC_CASE_OPEN 6 41
R5096 1 2 10K SMC_ADAPTER_EN 6 9 36 41
SMC Crystal Circuit R5093 1 2 10K SMC_BATT_CHG_EN 6 41
Debug Power Button C5020

15PF
SMC_ONOFF_L OUT 41 6 SMC_XTAL 1 2
6 7 40 41 42
NOSTUFF 5%
25V
3
1 CRITICAL NPO
R5010
4
0
Y5020
20MHZ
201
2
5%
Silk: "PWR BTN" SM-2.5X2.0MM
C5021
1
1/16W
MF-LF 15PF
2 402 SMC_EXTAL 1 2
Place on bottom side 41 6
5%
SMC 3.3V to 1.05V Level Shifting
near board edge APN: 197S0231 25V
NPO
201 CPU_PROCHOT_L 6 10 42 52 66 PM_THRMTRIP_L 6 10 16 23 66
Q5001 D 6 Q5001 D 3
SSM6N15FE SSM6N15FE
B SOT563 SOT563
B
Battery Pack Status
2 G S 1 5 G S 4
SMC_PROCHOT 41 6 SMC_THRMTRIP SMC_BS_ALRT_L R5098 1 SMC_BATTPACK_STAT

41 6 50 42 41 7 6 2 0 6 41
1 C5098
0.01UF
10%
2
10V
X5R
201
SMC AVREF Supply GND_SMC_AVSS 6 41 42 45 53 59
VR5065
42 41 40 39 28 27 26 23 8 7 6 PP3V42_G3H REF3333 PP3V3_S5_AVREF_SMC 6 41 72
72 59 57 44 43 SOT23-3 MIN_LINE_WIDTH=0.4 MM
1 IN OUT 2 MIN_NECK_WIDTH=0.2 MM
CRITICAL VOLTAGE=3.3V
GND 3.3V TO PBUS LEVEL SHIFTING
3 1 C5067
0.01UF
10% R5075
OMIT 2 10V
X5R 1
470K 2 PBUS_SMC_VSENSE_EN_L
PPBUS_R_G3H
1 C5065 C5066 1 201 72 59 55 54 53 52 8 7 6
1%
6 45 59
ENABLE VSENSE IN S0 ONLY

0.47UF 10uF 1/20W
10%
2 6.3V
CERM-X5R
402
20%
6.3V 2
X5R
603
MF
201 SMC SUPPORT
GND_SMC_AVSS Q5002 D 6 SYNC_MASTER=M70 SYNC_DATE=01/09/2007
A MIN_LINE_WIDTH=0.4 MM
VOLTAGE=0V
6 41 42 45 53 59
SSM6N15FE
SOT563 NOTICE OF PROPRIETARY PROPERTY
A
2 G S 1 AGREES TO THE FOLLOWING
R5011 55 51 41 37 36 25 7 6 IN PM_SLP_S3_L
SUS_CLK_SB 1
0 2 SMC_SUS_CLK
25 6 OUT 6 41 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
5%
1/20W SIZE DRAWING NUMBER REV.
MF
201
D 051-7230 B.0.0
APPLE INC.
R5011 CLOSE TO SB SCALE
NONE
SHT
42
OF
73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
LPC+SPI Connector SPI_CS MUX
Pullup to internal ROM on S5 PP3V42_G3H 6 7 8 23 26 27 28 39 40 41 42
C CRITICAL
LPCPLUS PP3V3_S5 24
6 7
8
25
43 44 57 59 72
C
J5100 LPCPLUS 1
26
27
55909-0374 R5151 28
36
M-ST-SM 44
31 32
20K 49
1 LPCPLUS
42 41 40 39 28 27 26 23 8 7 6 PP3V42_G3H 5%
51
56 C5150
72 59 57 44 43 1/20W 57
63 53 52 51 47 40 27 22 8 7 6 PP5V_S0 MF 58 0.1UF
72 60 10%
Place R5102 close to J5100 201 2 72
1 2 PCI_CLK33M_LPCPLUS 6 30 71 2
6.3V
IN R5102 X5R
5
41 23 6 LPC_AD<0> 3 4 LPC_AD<2> 6 23 41 47 201
BI BI 1 2 SPI_A_SCLK_R
Place R5101 close to J5100 6 IN 6 49 VCC
41 23 6 BI LPC_AD<1> 5 LPC_AD<3> BI 6 23 41 69
R5101 7 8
5%
1/20W
U5150
47 MF NC7SB3157P6X
SPI_A_SI_R 1 2 SPI_EXT_A_SI_R 9 10 BOOTROM_OVR_EN_L SPI_INT_CE_L<0> 1 B1 BOOTROM_OVR_EN_L
69 49 6 IN 6
IN 6 23 25 43 201 49 6 OUT MICROPAK S 6 IN 6 23 25 43
5% 69 49 24 6 SPI_SO 11 12 SPI_EXT_A_SCLK_R
6 CRITICAL
OUT
1/20W
13 14 LPCPLUS
MF 41 23 6 IN LPC_FRAME_L 6 SPI_EXT_CE_L<0> 3 B0 A 4 SPI_CE_L<0> IN 6 49 69
201
41 25 6 PM_CLKRUN_L 15 16 INT_SERIRQ 6 25 41
OUT BI GND
SMC_TMS 17 18 PM_SUS_STAT_L
2
42 41 6 OUT IN 6 25 41
28 6 DEBUG_RESET_L 19 20 SMC_TDI 6 41 42
IN IN
42 41 6 SMC_TDO 21 22 SMC_TCK 6 41 42
OUT IN
41 6 SMC_TRST_L 23 24 SMC_RESET_L 6 41 42
IN OUT
41 6 SMC_MD1 25 26 SMC_NMI 6 41
OUT OUT
42 41 39 6 SMC_TX_L 27 28 SMC_RX_L 6 39 41 42
Place halfway between SPIROM and J5100
IN OUT
29 30 FRANKCARD_GPIO 6 25
OUT
33 34
516S0573
B B
NO STUFF
R5152
15
1 2 SPI_CE_R_L<1> IN 6 24 69
5%
1/20W
MF
201
Place within 0.5" of SB
LPC+SPI Debug Connector

A SYNC_MASTER=M70

A
D 051-7230 B.0.0

NONE 43 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ICH8-M SMBus Connections SMC "0" SMBus Connections SMC "A" SMBus Connections
NOTE: SMC RMT bus remains powered and may be active in S3 state
64 63 60 53 64 63 60 53
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0 25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0 72 60 58 51 48 44 42 36 8 7 6 PP3V3_S3
52 51 46 44 42 30 29 28 27 26 52 51 46 44 42 30 29 28 27 26
ICH8-M R52001 1
R5201 Clock Chip SMC R5250 1 1
R5251 HEAT SPREADER SMC R52701 1
R5271 IPD
8.2K 8.2K 8.2K 8.2K 8.2K 8.2K
U2300 5% 5% SLG2AP101: U2900 U4900 5% 5% J5500 U4900 5% 5%
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W J4800
(MASTER) MF MF (Write: 0xD2 Read: 0xD3) (MASTER) MF MF (MASTER) MF MF
201
2 2
201 201
2 2
201 201
2 2
201 Front ALS (Write: 0x53 Read: 0x52)
71 TMP106 (Write: 0x93 Read: 0x92)
D 44 29 25 6
69
SMBUS_SB_SCL SMBUS_SB_SCL
MAKE_BASE=TRUE
SMBUS_SB_SCL 6 25 29 44
69
46 44 41 7 6
71
SMBUS_SMC_0_S0_SCL 71 46 44 41 7
6 SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL 71
6 7
41 44 46
41 40 36 7 6
71 44
SMBUS_SMC_A_S3_SCL 44 41 40 36 7
6 SMBUS_SMC_A_S3_SCL
71 MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SCL 44 71
6 7 36
40 41 D
44 29 25 6 SMBUS_SB_SDA SMBUS_SB_SDA SMBUS_SB_SDA 6 25 29 44 46 44 41 7 6 SMBUS_SMC_0_S0_SDA 71 46 44 41 7
6 SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDA 71
6 7 41 40 36 7 6 SMBUS_SMC_A_S3_SDA 44 41 40 36 7
6 SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SDA 44 71
6 7 36
69 MAKE_BASE=TRUE 69 71 MAKE_BASE=TRUE 41 44 46 71 44 MAKE_BASE=TRUE 40 41
CPU Temp M93 Wireless Card

TMP401: U5520 J4100
(Write: 0x98 Read: 0x99) (Write: 0x90 Read: 0x91)
44 71
71 SMBUS_SMC_A_S3_SCL 6 7 36
SMBUS_SMC_0_S0_SCL 6 7 41 40 41
44 46
44 71
71
SMBUS_SMC_A_S3_SDA 6 7 36
SMBUS_SMC_0_S0_SDA 6 7 41 40 41
44 46
Power Supply Temp

TMP106: U5550
(Write: 0x98 Read: 0x99)
SMC "Battery A" SMBus Connections
71
SMBUS_SMC_0_S0_SCL 6 7 41
44 46
71 42 41 40 39 28 27 26 23 8 7 6 PP3V42_G3H
SMBUS_SMC_0_S0_SDA 6 7 41 72 59 57 43
44 46
SMC R52801 1
R5281 Battery
2.2K 2.2K
U4900 5% 5% J6950
1/20W 1/20W
C SMC "B" SMBus Connections (MASTER)

71
MF
201 2
MF
2 201
(Write: 0x?? Read: 0x??)
C
59 50 44 41 7
50 44 41 7 6 SMBUS_SMC_BSA_SCL 6 SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SCL 6 7 41 44 50 59
71 59 71
71 MAKE_BASE=TRUE
59 50 44 41 7
72 60 58 51 48 44 42 36 8 7 6 PP3V3_S3 50 44 41 7 6 SMBUS_SMC_BSA_SDA 6 SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SDA 6 7 41 44 50 59
71 59 MAKE_BASE=TRUE 71
SMC R5260 1 1
R5261 Top ALS
U4900
8.2K
5% 5%
8.2K
J9050
Charger
1/20W 1/20W U7900
(MASTER) MF MF (Write: 0x52 Read: 0x53)
201 2 2 201 (Write: 0x?? Read: 0x??)
60 44 41 7
60 44 41 7 6 SMBUS_SMC_B_S3_SCL 6 SMBUS_SMC_B_S3_SCL SMBUS_SMC_B_S3_SCL 6 7 41 44 60
MAKE_BASE=TRUE SMBUS_SMC_BSA_SCL 6 7 41 44 50 59
60 44 41 7 71
60 44 41 7 6 SMBUS_SMC_B_S3_SDA 6 SMBUS_SMC_B_S3_SDA SMBUS_SMC_B_S3_SDA 6 7 41 44 60
MAKE_BASE=TRUE SMBUS_SMC_BSA_SDA 6 7 41 44 50 59
71
ICH8-M ME SMBus Connections SMC "Management" SMBus Connections

72 60 58 51 48 44 42 36 8 7 6 PP3V3_S3
49 43 36 28 27 26 25 24 8 7 6 PP3V3_S5
72 60 58 57 56 51
SMC R5230 1 1
R5231 SMS
ICH8-M R52101 1
R5211 8.2K 8.2K
B U2300
100K
5% 5%
100K
U4900
(MASTER)
5%
1/20W
MF
5%
1/20W
MF
KXPS5-2050: U5900
(Write: 0x30 Read: 0x31)
B
1/20W 1/20W 201 2 2 201
(MASTER) MF MF
201 2 2 201 48
48 44 41 6
71
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SCL 6 41
44
MAKE_BASE=TRUE 71
69 44 25 6 SMBUS_SB_ME_SCL SMBUS_SB_ME_SCL 48
71
SMBUS_SMC_MGMT_SDA SMBUS_SMC_MGMT_SDA SMBUS_SMC_MGMT_SDA 6 41
44
MAKE_BASE=TRUE 71
69 44 25 6 SMBUS_SB_ME_SDA SMBUS_SB_ME_SDA
MAKE_BASE=TRUE
SMBUS CONNECTIONS
A SYNC_MASTER=M70

A
D 051-7230 B.0.0

NONE 44 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ACIN VOLTAGE SENSE

D D
72 59 6 PPVDCIN_G3H_PRE MAX 16.5V + 10% ACIN = 3.0V SMC_PBUS_VSENSE
R5300 and R5301 VALUES CHOSEN FOR RC FILTER @ 4.53KOHM THEVENIN RESISTANCE
1
R5300
27.4K
1%
1/20W
MF
2 201
SMC_ACIN_VSENSE 6 41
1
R5301 1 C5300
5.36K 0.22UF
1% 10%
1/20W 6.3V
MF 2 CERM-X5R
2 201 402
GND_SMC_AVSS 6 41 42 45 53 59
PLACE C5300 NEAR SMC
C C
GPU VOLTAGE SENSE
R5310
4.53K2
72 65 53 22 18 8 7 6 PPVCORE_S0_NB_GFX 1 SMC_GPU_VSENSE 6 41
1%
1/20W
MF
201 1 C5310
0.22UF
10%
2 6.3V
CERM-X5R
B 402
GND_SMC_AVSS 6 41 42 45 53 59
B
PLACE R5310.C5310 NEAR SMC
PBUS VOLTAGE SENSE
PPBUS_G3H
D
S
PBUS_S0_SMC_VSENSE NOMINAL 8.4V PBUS = 3.0V SMC_PBUS_VSENSE

3
2
72 64 59 56 50 37 8 7 6 6
Q5350
SSM3J15FV R5350 and R5351 VALUES CHOSEN FOR RC FILTER @ 4.53KOHM THEVENIN RESISTANCE
SOT-723
G
1
R5350
470K PULLUP ON SMC SUPPORT PAGE 12.7K
1
1%
1/20W
MF
2 201
59 42 6 PBUS_SMC_VSENSE_EN_L Voltage Sensors

SMC_PBUS_VSENSE 6
A DRIVEN LOW IN S0
41 SYNC_MASTER=M70

A
1
R5351 1 C5350
6.98K 0.22UF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1% 10% PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1/20W AGREES TO THE FOLLOWING
MF 2 6.3V
CERM-X5R
2 201 402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
GND_SMC_AVSS 6 41 42 45 53 59
PLACE C5350 NEAR SMC SIZE DRAWING NUMBER REV.
D 051-7230 B.0.0

NONE 45 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REMOTE TEMP AT HEAT SPREADER

D D
CRITICAL
J5500
SM04B-SURK-LF
F-RT-SM
5
1
2 SMBUS_SMC_0_S0_SCL 4471
6 7
BI 41
3 SMBUS_SMC_0_S0_SDA 4641 44 46 71
BI 6
7
4 PP3V3_A_S0 53 60 63 64
6 7 8 13 16 19 21 22 23 24 25
26 27 28 29 30 42 44 46 51 52
6
APN:518S0354
CPU THERMAL DIODE

C C
53 60 63 64
PP3V3_A_S0 6 7 8 13 16 19 21 22 23 24 25
26 27 28 29 30 42 44 46 51 52
C5522 1 1
R5520 1R5521
0.1UF 10K 10K
10% 5% 5%
6.3V 2 1/20W 1/20W
X5R MF MF
201
2 201 2 201
R5525
CPU_THERMD_P 1
499 2
66 10 6 OUT
1% PLACE C5522 NEAR U5520 VDD
1/20W
MF
201 1 C5520 8
(TO CPU INTERNAL THERMAL DIODE) 470PF VDD
10% CRITICAL
2 16V
X5R-X7R A0 4 THRM_CPU_ALERT_L
R5526 201
6 THRM_CPU_DXP 1 DXP U5520 A1 3 6 THRM_CPU_THM_L
499 2 DXN TMP421
66 10 6 CPU_THERMD_N 1 2 6 THRM_CPU_DXN
SCL 7
IN SMBUS_SMC_0_S0_SCL BI
1% SOT23-8 6 7 41 44 46 71
1/20W SDA 6 SMBUS_SMC_0_S0_SDA BI 6 7 41 44 46 71

MF
201 ADDR= 1001 100B
1. ROUTE DXP AND DXN DIFFERENTIALLY GND
5
2. ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR
3. 5 MIL TRACE WIDTHS AND 5 MIL SPACING BETWEEN THE GAURD
(Write: 0x9E Read: 0x9F)
B B
LOCAL TEMP NEAR POWER SUPPLIES

53 60 63 64
PP3V3_A_S0 6 7 8 13 16 19 21 22 23 24 25
26 27 28 29 30 42 44 46 51 52
C5550 1
0.1UF
10%
6.3V 2
X5R
201
5
V+
U5550
HPA00330AI
SOT563
71 46 44 41 7 6 BI SMBUS_SMC_0_S0_SDA 6 SDA ADD0
4
CRITICAL
SMBUS_SMC_0_S0_SCL 1 SCL 3
71 46 44 41 7 6 BI ALERT TEMPERATURE SENSORS
A GND
2
A
(Write: 0x90 Read: 0x91) NOTICE OF PROPRIETARY PROPERTY
D 051-7230 B.0.0

NONE 46 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C
FAN CONNECTOR C
63 53 52 51 43 40 27 22 8 7 6
72
PP5V_S0
63 62 61 51 38 8 6 PP3V3_B_S0
CRITICAL
R5660 1 J5600
SM04B-SURK-LF
47K
5% NC
F-RT-SM
5
1/20W
R5665 MF
201 2
1 5V DC
41 6 SMC_FAN_0_TACH 1 47K2 7
6 FAN_RT_TACH 2 TACH
5% 3
1/20W
MF 4 MOTOR CONTROL
201 GND
NC 6
R5661 1
100K 518S0354
5% Q5660
1
1/20W
MF SSM3K15FV
G
201 2 SOD-VESM
FAN_RT_PWM
D
7 6
3
2
41 6 SMC_FAN_0_CTL
B B
Fan
A
D 051-7230 B.0.0

NONE 47 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
SUDDEN MOTION SENSOR
72 60 58 51 44 42 36 8 7 6 PP3V3_S3 APN:338S0354
SMS_MOT_EN 1 C5900
C R59001 1
R5901 0.1UF C
13
14
1
10K 0 10%
5% 5% VDD 2 6.3V
X5R
1/20W 1/20W 201
MF MF
201 2 2 201 U5900
KXPS5-2050
LGA SMS_X_AXIS
X 7 OUT 6 41
2 CRITICAL Y 8 SMS_Y_AXIS OUT 6 41

CS*
3
Z 9 SMS_Z_AXIS OUT 6 41
ADDR/SDI
71 44 41 6 BI SMBUS_SMC_MGMT_SCL 5 SCL/SCLK FF/MOT 11 SMC_SMS_INT OUT 6 9 41
41 6 IN SMS_ONOFF_L 6 ENABLE SDA/SDO 4 SMBUS_SMC_MGMT_SDA

BI 6 41 44 71
6 SMS_MOT_EN 12 MOT_ENABLE
SMS_MOT_DIS GND
1 1
R5902 R5903
10
0
5%
1 C5901 1 C5902 1 C5903 100K
5%
1/20W 33000PF 33000PF 33000PF 1/20W
MF 10% 10% 10% MF
2 201 2 6.3V
X5R
6.3V
2 X5R
6.3V
2 X5R 2 201
201 201 201
I2C addresses: Desired orientation when Desired orientation when

ADDR low => 0x30, 0x31 placed on board top-side: placed on board bottom-side:
ADDR high => 0x32, 0x33 Package Top Top-through View
B Alias SCL/SDA to GND if using analog outputs only 1

+Y +Y
1 B
+X +X
+Z (up) +Z (dn)
Sudden Motion Sensor (SMS)

A SYNC_MASTER=M76_MLB

A
D 051-7230 B.0.0

NONE 48 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
SPI ROM D
44 43 36 28 27 26 25 24 8 7 6 PP3V3_S5
72 60 58 57 56 51
1
R6100
3.3K 1
5% R6101
1/20W
MF 3.3K
201 5%
2
1/20W
MF
201
2
1
C6100
R619x close to SB 0.1UF
10%
R618x close to U6100 6.3V
X5R 2
R6193 R6180 201
15 47
69 24 6 IN SPI_SI_R 1 2 SPI_A_SI_R 1 2
8
5% 5%
1/20W 1/20W VCC R6114
MF MF CRITICAL
201 201 15
5D Q2
R6190 R6181 6 SPI_A_INT_SI
U6100 69 6 SPI_A_SO_R 1 2 SPI_SO OUT 6 24 43 69
15 47 5%
69 24 6 IN SPI_SCLK_R 1 2 SPI_A_SCLK_R 1 2 6 SPI_A_INT_CLK 6C M25P32 1/20W SPI_SO also driven by debug card
MF
5% 201 5% VFQFPN 201
1/20W 1/20W 1 S*
MF MF OMIT
201
R6191 6 SPI_A_INT_WP_L 3 W*/VPP
15 PLACEMENT_NOTE=Place R6114 within 12.7mm of U6100
69 24 6 IN SPI_CE_R_L<0> 1 2 SPI_CE_L<0> 43 6 IN SPI_INT_CE_L<0>
6 SPI_A_INT_HOLD_L 7 HOLD*
5%
C 1/20W
MF
201
VSS
4
THM
PAD
9
C
PLACEMENT_NOTE=Place R6180 within 12.7mm of U6100
OUT 6 43 69
OUT 6 43 69 TO DEBUG CONNECTOR

OUT 6 43 69 note: mux for CE_L<0> on debug connector page.
There is a 10K pullup on SPI_INT_CE_L<0> at the mux output.
There is an option to connect SPI_INT_CE_L<0> directly to SPI_CE_L<0>
B B
SPI ROMs
A SYNC_MASTER=WFERRY

A
D 051-7230 B.0.0

NONE 49 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
DC-JACK INTERFACE R6905
CRITICAL
D6901
HN2S02FU
SOT-363 D
47
5%
PPBUS_G3H
1/8W
CRITICAL 72 7 6 PP18V5_DCIN
VOLTAGE=18.5V
MF-LF
805
6 1 PPDCIN_G3H 6 7 8 57 72
J6980 MIN_LINE_WIDTH=0.6 MM
1 2 PPDCIN_G3H_R
WTB-PWR-M82 MIN_NECK_WIDTH=0.2 mm 5 2
VOLTAGE=18.5V
M-RT-SM 1 C6902
1 0.01UF 59 50 6 BATT_POS_F1 2 PPVBATT_G3H_R 4 3
10%
2 2 25V
X7R
CRITICAL R6940
3 402 F6900 10 VOLTAGE=18.5V
4
6AMP-24V 5%
1206-1 1/8W
MF-LF
5 1 2 805 PP18V5_G3H 6 7 8 59 72
1
518S0507 R6902 6
ONEWIRE_PWR_EN_L1 2 R6904
1K 47K
5% Q6910 5% 2
1/16W
MF-LF
SSM6N15FE
D 3
R6911 2 1/16W
MF-LF
402
SOT563 100K 402
S
SMC_BC_ACOK1 2 6 SMC_BC_ACOK_ONEWIRE_R 5%
59 42 41 6 1/16W SOT-723
MF-LF SSM3J15FV
1 C6907 402 6 ONEWIRE_PWR_EN_L_DIV 1 Q6940
0.001UF G
6 ADAPTER_SENSE 10% 5 G S 4
2 50V
CERM D
402
3
SYS_ONEWIRE6 SYS_ONEWIRE_BILAT
4 S
1
3 D
6
42 41 7 6
S
72 6 PP18V5_DCIN_ONEWIRE
Q6920
G 5
SSM6N15FE Q6920 VOLTAGE=18.5V
C SOT563 2
SSM6N15FE 1
SOT563 R6932
1
R6901 1
R6933 C
24.3K 24.3K 100K
1% 1% 5%
OneWire OVP 1/16W

MF-LF
2 402
1
5%
R6903
200K
1/16W
1
10%
C6930
0.1UF
5
1/16W
MF-LF
2 402
1/20W
MF
2 201
ONEWIRE_EN MF-LF 6 ONEWIRE_DCIN_DIV

6
2 402 2 25V
X5R
1
402 V+
Q6999 6 ONEWIRE_OV 4
SSM3K15FV 3 D
SOD-VESM ONEWIRE_ESD
1
R6931
CRITICAL V- 3 6 100K
5%
1
R6906 U6990 2 1/20W
MF
1
R6900 200K LM397 201
100K
1 C6903 5%
1/16W SOT23-5
2
5% 0.001UF G 1 MF-LF
1/16W 10% 2 S
MF-LF 2 50V 2 402
CERM
2 402 402
B B
BATTERY INTERFACE
CRITICAL
J6900
WTB-PWR-M82 L6900
M-RT-SM FERR-50-OHM
1 7 6 BATT_POS 1 2 BATT_POS_F 6 50 59
2 2 SM-LF
3
C6900
0.01UF
4 10%
1 25V
5 X7R
402
6
7 SMC_BS_ALRT_L 6 7 41 42
8 SMBUS_SMC_BSA_SDA 6 7 41 44 59 71
9 SMBUS_SMC_BSA_SCL 6 7 41 44 59 71 DC-In & Battery Connectors
A
518S0540
D 051-7230 B.0.0

NONE 50 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
S0 FETS & POWER SEQUENCING & PGOOD

D D
CRITICAL
Q7000
FDM6296
CRITICAL
Q7001
FDC655BN
1.05V S0 RUN/SS CONTROL
MICROFET3X3 3 PP5V_S0 6 7 8 22 27 40 43 47
51 52 53 63 72
44 43 36 28 27 26 25 24 8 7 6
72 60 58 57 56 51 49
PP3V3_S5 1 SOT6
D
PP3V3_A_S0 53 60 63 64
6 7 8 13 16 19 21 22 23 24 25
26 27 28 29 30 42 44 46 51 52
2 2
R7030 R7031
72 58 56 55 54 51 39 27 8 7 6 PP5V_S5 5
D S
1
5V S0 FET 5
6 G 3 3.3V S0 FET 100K
5%
1/20W
330
5%
1/20W
S MF MF
G C7003 MOSFET FDM6296 4
MOSFET FDC655BN 64 63 60 53
PP3V3_A_S0 2
201
1 1V05S0_RUNSS_BUF2 201
1 1V05S0_RUNSS
C7004 25 24 23 22 21 19 16 13 8 7 6 6 54
0.0022UF 52 51 46 44 42 30 29 28 27 26
4
10%
CHANNEL N-TYPE 0.0022UF
CHANNEL N-TYPE
50V 10%
CERM
RDS(ON) 15 mOhm @4.5V 50V D 6
6 P5VS0_EN
402
1 2
CERM
402
RDS(ON) 33 mOhm @4.5V Q7007 1 C7030
LOADING 4.061 A 1 2 SSM6N15FE 0.022UF
CRITICAL LOADING 1.063 A SOT563
10%
Q7002 2 6.3V
X5R
FDC655BN
44 43 36 28 27 26 25 24 8 7 6
72 60 58 57 56 51 49
PP3V3_S5 1 SOT6
D
PP3V3_B_S0 6 8 38 47 61 62 63 2 G S 1 201
2 51 6 RUNSS_GATE_D_L
5
6
S
G 3 3.3V S0 FET
4
C7006 MOSFET FDC655BN
0.0022UF
10%
50V
CHANNEL N-TYPE 1.25V S0 RUN/SS CONTROL
CERM
402
RDS(ON) 33 mOhm @4.5V R7041 R7040
6 P3V3S0_EN 1 2 100K 330
LOADING .776 A
C 5%
1/20W
MF
201
5%
1/20W
MF
201
C
46 44 42 30 29 28
21 19 16 13 8 7 6 PP3V3_A_S0 2 1 1V25S0_RUNSS_BUF2 1 1V25S0_RUNSS 6 57
27 26 25 24 23 22
64 63 60 53 52 51
72 58 56 55 54 51 39 27 8 7 6 PP5V_S5 72 CRITICAL
OMIT
55
34
31
Q7004 D 3
1 18 FDC655BN PP1V8_S0
C7000 8
6
7
PP1V8_S3 1 SOT6
D
6 7 8 19 22 51 61 72
Q7006 1 C7040
1UF 16 2 SSM6N15FE
2 6.3V 21
32 SOT563 0.01UF
10% 35 5 10%
72 60 58 48 44 42 36 8 7 6 PP3V3_S3 CERM
402
68
6
S
G 3 1.8V S0 FET 5 G S 4
2 10V
X5R
201
4
53 52 51 47 43 40 27 22 8 7 6 PP5V_S0 2 1 MOSFET FDC655BN 51 6 RUNSS_GATE_D_L
72 63
C7005
R7001 1
R7002 1
R7000 0.0022UF CHANNEL N-TYPE
23
30.9K 4.87K 100K 10%
1%
1/20W
1% 5% 50V
CERM RDS(ON) 33 mOhm @4.5V
MF
201
1/20W
MF
2 201
1/20W
MF
2 201
VDD
U7000
ISL6130IRZA
6 P1V8S0_EN
402
1 2 LOADING 1.120 A 1.5V S0 RUN/SS CONTROL
QFN
55 6 PGOOD_1V8S3 20 UVLO_A GATE_A 2 R7050 R7051
6 S0PWRGD_5V_DIV 12 UVLO_B GATE_B 5 10K
5%
330
5%
64 63 60 53
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0 2 1 6 S0PWRGD_3V3_DIV 17 UVLO_C GATE_C 6 1/20W 1/20W
52 51 46 44 42 30 29 28 27 26 MF MF
6 S0PWRGD_1V8_DIV 14 UVLO_D GATE_D 7 6 RUNSS_GATE_D 201
1V5S0_RUNSS_BUF2 201
1V5S0_RUNSS
R7003 1
R7004 64 63 60 53
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0 2 1 1 6 54
28.7K 7.5K
CRITICAL 52 51 46 44 42 30 29 28 27 26
1% 1% DLY_ON_A 21 TP_DLY_ON_A
1/20W 1/20W
TP_DLY_ON_B 56 55 54 51 39 27 8 7 6PP5V_S5 D 3
MF MF DLY_ON_B 8 72 58
201
2 201
6 S0SEQ_BEGIN 1 ENABLE_1
TP_DLY_ON_C 1 Q7007 1 C7050
DLY_ON_C 16 R7061 SSM6N15FE 1000PF
DLY_ON_D 15 TP_DLY_ON_D 470K SOT563 10%
5% 2 16V
X7R
1/20W
B 72 61 51 22 19 8 7 6 PP1V8_S0 2 1 NC
19 NC DLY_OFF_A6 18 DLY_OFF_A MF
2 201 5 G S 4
201
B
NC DLY_OFF_B6 13 DLY_OFF_B
51 6 RUNSS_GATE_D_L
1
R7006 DLY_OFF_C 3 DLY_OFF_C
R7005 NC 11 ENABLE_2*
6
22.1K
1%
13.7K NC 22 DLY_OFF_D 4 6 DLY_OFF_D
1% NOSTUFF NOSTUFF D 6
1/20W 1/20W SYSRST* NOSTUFF
MF
201
MF RESET0* 24 1 C7024
1 C7021 1 C7022 1 C7023 Q7006
2 201 RESET1* 9 0.01UF 0.01UF 0.022UF SSM6N15FE
0.01UF 10% 10% 10% SOT563
THML 10%
10V 2 10V
X5R 2 10V
X5R 2 6.3V
X5R
GND PAD 2 X5R 201 201 201
201 2 G S 1
25
10
55 42 41 37 36 25 7 6 PM_SLP_S3_L 1 2
R7007 ~26MS
47
5%
1/20W
MF
201 DEASSERTED 160MS
AFTER UVLO_D VALID
PP3V3_A_S0 53 60 63 64
6 7 8 13 16 19 21 22 23 24 25
26 27 28 29 30 42 44 46 51 52
1
1 C7001
R7012 0.1UF
10%
100K
5% 2 6.3V
X5R
1/20W
6
MF 201
2 201
PGOOD_SEQUENCER VDD
1 RESET*CRITICAL
SENSE 5 PP1V25_S0
PGOOD_1V05S0 U7002.3 has int 90K pull-up U7002 6 7 8 16 18 19 21 26 27 57 72
54 TPS3808-1.25V S0 FETS & Power Sequencing

6 ALL_SYS_PWRGD_AND 3 MR* SOT23-6 CT 4 ALL_SYSPWRGD_DLY 6
54 PGOOD_1V5S0 MAKEBASE=TRUE
A GND 1 C7002
1000PF A
2
10% NOTICE OF PROPRIETARY PROPERTY
2 16V
X7R
NO STUFF NO STUFF 201 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
R7013 R7014 AGREES TO THE FOLLOWING
0
5%
0
5%
1/20W 1/20W ALL_SYS_PWRGD 6 28 41 52 II NOT TO REPRODUCE OR COPY IT
MF MF
201 201 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
57 6 PGOOD_1V25S0 2 1 2 1
STUFF R7013,R7014 and UNSTUFF U7002,C7001,C7002 D 051-7230 B.0.0

TO USE WIRE-AND OF ALL PGOODs INSTEAD OF TPS3808 APPLE INC. SCALE SHT OF
NONE 51 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1 2 IMVP6_PVCC
VOLTAGE=5V OMIT
1 C7100
R7100 1UF
0 10%
63 53 51 47 43 40 27 22 8 7 6 PP5V_S0 5% 6.3V
CERM
72 1/16W 2
MF-LF 402
402
1 2 72 6 PP5V_S0_IMVP6_VDD
OMIT MIN_LINE_WIDTH=0.25 MM
C7101
IMVP6 CPU VCORE REGULATOR

1
R7101 1UF VOLTAGE=5V
0 10%
5% 6.3V
1/16W CERM
2 402
MF-LF
D
402
D
72 59 55 54 53 52 42 8 7 6 PPBUS_R_G3H 1 2 72 6 PPVIN_S5_IMVP6_VIN
R7102 1 C7102 VOLTAGE=18.5V
0 0.22UF
5% 10%
1/16W 16V
MF-LF X7R
2 603
66 25 16 6 IN
PM_DPRSLPVR 402
VOLTAGE=3.3V
64 63 60
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0 1 2 72 6 PP3V3_S0_IMVP6_3V3
53 51 46 44 42 30 29 28 27 26
R7103 C7103
1
0 1UF 72 59 55 54 53 52 42 8 7 6 PPBUS_R_G3H
5% 10%
1/20W 10V
X5R
MF 2 402-1 CRITICAL CRITICAL
201
1 1 1 C7152 1 C7153
18
20
27
52 6 GND_IMVP6_SGND C7150 C7151 1UF 1UF
VIN VDD VCCP 47UF 47UF 10%
25V
10%
25V
20% 20%
X5R X5R
CRITICAL 2 10.0V 2 10.0V 2 603 2 603
66 12 11 6 CPU_VID<6> 34 VID6 POLY POLY
CASE-B2-1 CASE-B2-1
66 12 11 6 CPU_VID<5> 33 VID5 BOOT 22 IMVP6_BOOT 1 2 IMVP6_BOOT_RC 6 5
66 12 11 6 CPU_VID<4> 32 VID4
U7100
QFN C7104
CPU_VID<3> 31 R7104 1
ISL6261CRZ
1 1 66 12 11 6 VID3 0.22UF
PLACE R7110 WITH NO STUB R7111 R7110 30
0 10%
12 11 6 CPU_VID<2> VID2 5%
16V
ON PM_DPRSLPVR 499 499 66 1/16W 4
X7R
1% 1% 66 12 11 6 CPU_VID<1> 29 VID1 MF-LF 2 603
1/20W 1/20W 402
MF MF 66 12 11 6 CPU_VID<0> 28 VID0 LGATE 26 52 IMVP6_LGATE CRITICAL
2 201 2 201
Q7100
66 23 16 10 6 IN CPU_DPRSTP_L 37 DPRSTP* RJK0305DPB
VSSP 25 (GND)
66 6 IMVP_DPRSLPVR 36 DPRSLPVR 1 2 3 LFPAK
CRITICAL
C NO STUFF
R7115 51 41 28 6 IN ALL_SYS_PWRGD
1
2
FDE
PGD_IN UGATE 23 52 IMVP6_UGATE
L7100
SM-IHLP PPVCORE_S0_CPU
C
52 65
6 7 8
0 (IMVP6_PHASE) 1 2
11 12
72
5% PHASE 24 IMVP6_PHASE
1/20W 39 3V3
66 MF
42 CPU_PROCHOT_L 0.36UH-30A-1.2M-OHM
10
1
201
2
28 6 OUT VR_PWRGD_CK505_L 38 CLK_EN*
6
41 6 FROM SMC IMVP_VR_ON 35 VR_ON
IN
PWM FREQ. = 300kHz
OUT VR_PWRGOOD_DELAY 40 PGOOD
1 2
28 16 9 6
6 IMVP6_VR_TT 4 VR_TT* 5 5
MAX CURRENT = 30A
R7116 NC 5 NTC CRITICAL CRITICAL
C7111 147K
0.015uF 1%
VSUM 17 IMVP6_VSUM
10%
16V
1/20W
MF 52 6 IMVP6_SOFT 6 SOFT
IMVP6_OCSET 4
Q7150 4
Q7151
X7R
201 OCSET 7 52
RJK0303DPB RJK0303DPB
402 1 2 52 6 IMVP6_RBIAS 3 RBIAS VO 16 PPVCORE_S0_CPU (IMVP6_VO) NO STUFF LFPAK LFPAK
1
DROOP 14 IMVP6_DROOP
C7141
52 6 IMVP6_VDIFF 11 VDIFF 1000PF
2
10%
DFB 15 52 IMVP6_DFB 1 2
16V 1 2 3 1 2 3
1 X7R
52 IMVP6_FB 10 FB VSEN 12
R7140 R7141 1 C7140 201
806 6.34K 330PF 1
52 IMVP6_COMP 9 COMP RTN 13 1% 1%
R7142
1/20W 10%
1/20W
52 6 IMVP6_VW 8 VW MF MF 2 16V 20K
1
C7120 1 2 2
201 201
X7R 1%
IMVP6_VSEN_N
IMVP6_VSEN_P
1/20W
180PF 201
MF
5% R7124 21 NC 201
50V 2
CERM
1K C7130
2 1% (IMVP6_VO)
402 1/20W VSS TPAD 1000PF 1
41
MF
R7146
19
201 10%
16V 1 7.68K
IMVP6_VDIFF_RC 6 52 6 IMVP6_COMP_R 1 2 X7R R7143 1%
52 66 6 201 66 6
1 1 2
3.57K 1/16W
R7120 1
1% MF-LF
2.21K R7122 1/20W

MF
2
402
B 1%
1/20W
MF
15K
1%
1/20W
1 C7124
0.01UF
10%
C7131
1000PF 1
C7142
0.12UF
1
C7143
0.01UF
1
R7145
2
201
IMVP6_VO_R 6
B
2
201 MF 10V 10% 10% 10%
4.53K
201 52 6 GND_IMVP6_SGND 1%
2 X5R 16V 10.0V 10V 1
(IMVP6_FB) 2 201 X7R CERM-X5R X5R 1/20W
2 402 2 201 MF
201
1 2
201 CRITICAL
R7130 R7144
1
100 10KOHM-5%
R7121 1 2
1%
1/20W
0603-LF
374K MF
1% (IMVP6_VW) 2 201 2
1/20W
MF
C7132 ERT-J1VR103J
2
201 330PF (IMVP6_VSUM)
10%
1 16V
1
C7122 1
C7123 R7123 R7134 X7R
(IMVP6_VO)
IMVP6_FB_RC 52
56PF 1000PF 6.04K 100 2 201
5% 10% 1
25V 16V 1%
NP0-C0G X7R 1/20W
1 C7121 2 201 2 201 MF 1%
1/20W 1 2
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
201
270PF 2 MF
10% 201
50V 1 1
2
X7R-CERM 2
C7133 R7131 R7132
402 OMIT 0.1UF 0 0
XW7100 10%
5%
1/20W
5%
1/20W
SM 6.3V
MF MF
X5R
NOTE 1: C7132,C7133 = 27.4 OHM FOR VALIDATING CPU ONLY. 1
201 2
201
2 201
CPU_VCCSENSE_P 6 11 66 MIN_LINE_WIDTH MIN_NECK_WIDTH
CPU_VCCSENSE_N 6 11 66
52
IMVP6_OCSET 0.25 MM 0.20 MM
52 6
IMVP6_VSUM 0.25 MM 0.20 MM
52 6
GND_IMVP6_SGND 0.50 MM 0.20 MM
72 65 52 12 11 8 7 6
PPVCORE_S0_CPU 0.25 MM 0.20 MM
IMVP6_DROOP
52 6
52
IMVP6_DFB
0.25 MM
0.25 MM
0.20 MM
0.20 MM
IMVP6 CPU VCore Regulator
IMVP6_SOFT
A 52 6
52 6
IMVP6_RBIAS
0.25 MM
0.25 MM
0.20 MM
0.20 MM
SYNC_MASTER=POWER

A
52 6
IMVP6_VDIFF 0.25 MM 0.20 MM
MIN_LINE_WIDTH MIN_NECK_WIDTH
52
IMVP6_FB 0.25 MM 0.20 MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
52 6
IMVP6_PHASE 1.5 MM 0.20 MM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
52
IMVP6_COMP 0.25 MM 0.20 MM AGREES TO THE FOLLOWING
52 6
IMVP6_BOOT 0.25 MM 0.20 MM
52 6
IMVP6_VW 0.25 MM 0.20 MM I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
52
IMVP6_UGATE 1.5 MM 0.20 MM
52 6
IMVP6_PVCC 0.25 MM 0.20 MM II NOT TO REPRODUCE OR COPY IT
52
IMVP6_LGATE 1.5 MM 0.20 MM
52 6
IMVP6_COMP_R 0.25 MM 0.20 MM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
IMVP6_COMP_RC 0.25 MM 0.20 MM
52
IMVP6_FB_RC 0.25 MM 0.20 MM
52 6
IMVP6_VDIFF_RC 0.25 MM 0.20 MM D 051-7230 B.0.0

NONE 52 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RENDER VCORE POWER SUPPLY

D D
72 59 55 54 52 42 8 7 6 PPBUS_R_G3H
R72111 CRITICAL
1K 1 C7202 1 C7201
R7210 1%
5 1
C7200
10 1/20W 0.01UF 1UF
5% MF 10%
25V
10%
16V
47UF
1/16W 201 2 2 X7R CRITICAL 2 X5R
20%
MF-LF D 2 10.0V
402 603-1
53 52 51 47 43 40 27 22 8 7 6 PP5V_S0 1
402
2GCORE_VCC
Q7200 POLY
CASE-B2-1
72 63 53 6 GCORE_VDC_DIV 4
SI7110DN
G PWRPK-1212-8
1 1 C7211
R7212 100PF S
64 63 60 53
25 24 23 22 21 19 16 13 8 7 6
52 51 46 44 42 30 29 28 27 26
PP3V3_A_S0
C7212 1 1 C7213
340K
1%
5%
25V
CERM 1 2 3
CRITICAL PWM FREQ. =400kHz
CRITICAL
4.7UF
10%
6.3V
1UF
10%
6.3V
1/20W
MF
201 2
2 201
L7200
R7200
0.002
MAX CURRENT = 13A (inductor limit)
X5R-CERM CERM 0.82UH 1%
1/4W
1 1 603 2 2 603-1
D7210 IHLP2525CZ-SM MF-LF
R7217 R7213 SOD-323 (GCORE_SW) 1206
30K 10K 1 2 1 2 PPVCORE_S0_NB_GFX 6 7 8 18 22 45 53 65 72
5% 1% 1 2GCORE_BST_D
1/20W 1/20W
MF MF
201 201
20
24
2 2 B0530WS-X-F
R7214 5
649K
53 16 9 6 GFX_VR_EN 53 16 9 6 GFX_VR_EN30 EN PVCC VCC 53 6 16 GCORE_RT
RT 1 2
NO STUFF 1
1% CRITICAL
R7209 6 GCORE_PWRGD 31 PWRGD 1/20W D
53 6 13 GCORE_RAMP
RAMP MF Q7201
100K 63 60 53
9 LLINE
201
C 5%
1/20W
MF
44 42 30
25 24 23
13 8 7 6
22 21 19 16
29 28 27 26
PP3V3_A_S0
53 6 GCORE_LLINE
23 GCORE_BST
R7215
0
4 G
SI7108DNS
PWRPK-1212-8 C
201 2 52 51 4664
R7216 1 U7200 BST
53 1 2
S
53 GCORE_CLIM 8 CLIM 5%
1 C7214
1.8K ADP3209 1/16W
1UF 1 2 3
5% 53 6 GCORE_CSFB 12 CSFB MF-LF
1/20W ST 5 GCORE_ST 402 10%
6.3V
MF LFCSP
201 2 2 CERM
603-1
( 2 OF 2 ) DRVH
53 22 GCORE_DRVH
PLACE RC CLOSE TO SMC
CRITICAL DRVL
53 19 GCORE_DRVL
41 6 SMC_GPU_ISENSE 1 2 53 6 GCORE_PMON 6 PMON
53 6 GCORE_PMONFS 7 PMONFS
R7290 53 6 21 GCORE_SW
SW
C7290 1 1
200K
1%
R7219
0.22UF 1 187K GCORE_COMP 3 COMP
20%
1/20W
MF R7218 1%
53
R7224 R7222
6.3V 201 113K 215K 110K
X5R 2 1%
1/20W
MF 1 2 1 2 GCORE_SW_R
402 1 1 FBRTN
1/20W
MF 2 201 R7220 GCORE_FBRTN 1% 1%
GND_SMC_AVSS 201 2 309K 1/16W 1/16W
59 45 42 41 6 1% MF-LF MF-LF
1/20W GCORE_RPM 15 RPM CSCOMP
53 10 GCORE_CSCOMP 402 402
MF
201 NO STUFF
2 53 6 GCORE_VRPM 14 VRPM R7225 R7226
CSREF 11 (GCORE_CSREF)
72 63 53 0 0
52 51 47 43 40 27 22 8 7 6 PP5V_S0 6 GCORE_VARFREQ 32 VARFREQ (GCORE_CSCOMP) 1 2 1 2
R7219 sets maximum current measured by PMON
5% 5%
Rpmonfs = (Imax x 0.008 Ohm)/1.1uA NO STUFF C7230 1/20W 1/20W
1 25 VID4 470PF MF MF
Imax = 12.8A, Rpmonfs = 93.1KOhms R7250 201 201
10K 26 VID3 FB 2 53 GCORE_FB 1 2
5%
1/20W 27 VID2 10% 1
MF 28 VID1 50V R7230
201 2 CERM 1K R7228
29 VID0 402 1% 100
1/20W 53 GCORE_FB_R 1 2
1 SS 4 GCORE_SS
53 MF
R7251 (GCORE_CSCOMP) 201 5%
(GCORE_FB) 2 1/20W
B 10K
5%
1/20W
GND PGND THRM_PAD
NO STUFF
MF
201 B
17
18
33
1 C7234
MF
201
R7232 1 C7231 1 C7232 1 C7233 1
2 33.2K 470PF
1% 100PF 100PF 22PF 10% OMIT
1/20W 5% 5% 5% 50V CRITICAL
MF
25V
2 CERM
25V
2 CERM
25V
2 NP0-C0G 2 402
CERM 1 C7281
GND 2 201 201 201 201 R7231 10UF
1
C7280
20K 20%
6.3V
330UF
22 16 6 GFX_VID<3> (GCORE_COMP) 1 2 GCORE_COMP_R 6 2 X5R
20%
603 2 2.5V
22 16 6 GFX_VID<2> (GCORE_CSFB) 5% POLY
1/20W CASE-C2-SM-1
22 16 6 GFX_VID<1> (GCORE_LLINE) MF R7229
201 100
22 16 6 GFX_VID<0> (GCORE_FBRTN) 1 2
(GCORE_ST) 5%
53 6 GND_GCORE_PGND 1/20W
C7240 1 C7241 1 C7242 1 (GCORE_CSREF) 1 C7244 MF
201
OMIT
1000PF 1000PF 0.012UF 220PF
NOTE: VID<4> is tied to GND 10%
16V
10%
16V XW7200 10%
25V C7243 10%
25V
R7291
1 0
X7R X7R 1 2 X7R 1000PF X7R-CERM 1 2 PPVCORE_S0_NB_GFX
201 2 201 2 402 2 10% 2 201 6 7 8 18 22 45 53 65 72
4 3 2 1 0 VOLTAGE 16V
SM 5%
X7R 1/20W
VID
VID
0
0
0
0
0
0
0
0
0
1
1.250V
1.225V
Each step is 0.025V 2 201
MF
201
ROUTE AS DIFF PAIR TO NB GFX VCC AND GND
VID 0 0 0 1 0 1.200V R7292 FOR REMOTE SENSING
VID 0 0 0 1 1 1.175V 0
1 2
VID 0 0 1 0 0 1.150V
5%
VID 0 0 1 0 1 1.125V 1/20W
MIN_LINE_WIDTH MIN_NECK_WIDTH MF
VID 0 0 1 1 0 1.100V GCORE_SW 0.6 MM 0.20 MM
201
53 6 I103
VID 0 0 1 1 1 1.075V GCORE_BST 0.3 MM 0.20 MM
53 I104
VID 0 1 0 0 0 1.050V GCORE_DRVH 0.6 MM 0.20 MM
VID 0 1 0 0 1 1.025V
53
53
GCORE_DRVL 0.6 MM 0.20 MM
I105
I106
MIN_LINE_WIDTH MIN_NECK_WIDTH Render VCore Supplies
VID 0 1 0 1 0 1.000V GCORE_BST_D 0.3 MM 0.20 MM GCORE_CSCOMP 0.3 MM 0.20 MM
A VID
VID
0
0
1
1
0
1
1
0
1
0
0.975V
0.950V
53 6
53 6
GND_GCORE_PGND 0.6 MM 0.20 MM
I107
I108
53
53 6
GCORE_CSFB 0.3 MM 0.20 MM
I115
I117

SYNC_DATE=(MASTER)
A
53 6
GCORE_VDC_DIV 0.3 MM 0.20 MM I110 53 6
GCORE_LLINE 0.3 MM 0.20 MM I118
VID 0 1 1 0 1 0.925V GCORE_RAMP 0.3 MM 0.20 MM GCORE_RT 0.3 MM 0.20 MM
53 6 I111 53 6 I119 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
VID 0 1 1 1 0 0.900V GCORE_CLIM 0.3 MM 0.20 MM GFX_VR_EN 0.3 MM 0.20 MM PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
53 I112 53 16 9 6 I120 AGREES TO THE FOLLOWING
VID 0 1 1 1 1 0.875V GCORE_SS 0.3 MM 0.20 MM GCORE_COMP 0.3 MM 0.20 MM
53 I113 53 I121 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
53 6
GCORE_ST 0.3 MM 0.20 MM
I114 53
GCORE_FB 0.3 MM 0.20 MM
I122 II NOT TO REPRODUCE OR COPY IT
53 6
GCORE_SW_R 0.6 MM 0.20 MM I235 53 6
GCORE_FBRTN 0.3 MM 0.20 MM I123 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
53 6
GCORE_PMON 0.3 MM 0.20 MM I124
GCORE_PMONFS 0.3 MM 0.20 MM SIZE DRAWING NUMBER REV.
53 6 I125
53 6
GCORE_RPM
GCORE_VRPM
0.3 MM 0.20 MM I229 D 051-7230 B.0.0
0.3 MM 0.20 MM
53 6 I230 APPLE INC. SCALE SHT OF
53
GCORE_FB_R 0.3 MM 0.20 MM I236
NONE 53 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
1.5V/1.05V POWER SUPPLY
State PM_SLP_S3_L PP1V5_S0 PP1V05_S0
S0 HIGH 1.5V 1.05V
S3/S5/G3Hot LOW 0.0V 0.00V
C C
R7361
3.3
5%
1/16W
MF-LF
402
PP5V_S5 Routing Note:
6 1V51V05S0_V5FILT 1 2 6 7 8 27 39 51 55 56 58 72
OMIT The discharge path (VO2) should have
1
Routing Note: C7305 1 C7301 Placement Note: a dedicated trace to the output cap;
1UF 10UF
20% R7361,C7305 close to U7300 pin 15. separate from the output voltage
The discharge path (VO1) should have 10%
2 10V 2 6.3V C7301 close to U7600 pin 16. sensing trace,
a dedicated trace to the output cap; X5R X5R
OMIT 402-1 603
separate from the output voltage GND_1V51V05S0_SGND
1 C7351 sensing trace,
54 6
10UF 72 59 55 54 53 52 42 8 7 6 PPBUS_R_G3H
20%
2 6.3V
X5R
603 PPBUS_R_G3H 6 7 8 42 52 53 54 55 59 72
CRITICAL
CRITICAL
Q7360 CRITICAL
CRITICAL 5 SI7212DN C7381 PWM FREQ. = 360 kHz
C7341
5
1
PWM FREQ. = 300 kHz 1
1UF 1
C7340 Q7320
PWRPK-1212-8
1UF C7380 MAX CURRENT = 3.3A
D 10% 47UF
MAX CURRENT = 9.9A 47UF C7324 R7324 R7364 C7364 (OCP setting limited)
15
16
10% SI7110DN D 16V 20%
16V 20% X5R 10.0V
(OCP setting limited) 2 X5R 2 10.0V
PWRPK-1212-8 0.1UF 0 0 0.1UF 2 603-1 POLY
603-1 POLY 10% 5% 5% 10% 4 G CASE-B2-1
14 13 12 11 10 8 7 6 PP1V05_S0 CASE-B2-1 G 4 16V 1/16W V5FILT V5IN 1/16W 16V S
19 18
72 42 30 27 26 23 21 CRITICAL X5R
402 MF-LF MF-LF X5R
402 CRITICAL PP1V5_S0 6 7 8 11 12
402 1 VO1 SYM(1 OF 2) VO2 6 402 22 26 27 72
3
L7320
S
2 1 1V05S0_VBST_RC 1 2 1V05S0_VBST 22
CRITICAL
VBST1 VBST2 9 1V5S0_VBST 1 2 1V5S0_VBST_RC 2 1 L7360
1.0UH-22A-10M-OHM 3 2 1 MIN_LINE_WIDTH=0.6 mm 1V05S0_VH 21 DR_VH1
U7300 DR_VH2 101V5S0_VH MIN_LINE_WIDTH=0.6 mm
4.7UH-5.5A
MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
1V05S0_LL 20 LL1 TPS51124 LL2 111V5S0_LL MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
mm
mm
1 2
B <Rc> SM-IHLP
CRITICAL 5
1V05S0_VL 19 DR_VL1 QFN DR_VL2 121V5S0_VL MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
mm
mm CRITICAL
IHLP-2525
CRITICAL
1
NO STUFF B
NO STUFF 1 Q7321 Q7360 C7392
OMIT <Ra>
1 C7329 R7327 6 1V05S0_TRIP 17 TRIP1 TRIP2 6 141V5S0_TRIP
SI7212DN
1
330UF
1 C7350 R7367 1 C7369
7.68K SI7108DNS 1V05S0_VFB 2 VFB1 VFB2 5 1V5S0_VFB 10UF 20K 100PF
6
100PF 1%
1/20W PWRPK-1212-8
D
24 PGOOD1 PGOOD2 7
PWRPK-1212-8 20%
2 2.5V 20% 2 1% 5%
5% MF CRITICAL D POLY 6.3V
2 X5R 1/20W 2 25V
25V MF CERM
2 CERM
201
2 201
1
C7352 G 4 1
R7325 51 6 1V05S0_RUNSS23 EN1 TONSEL 4 NC
CASE-C2-SM-1
603 201 201
330UF
20%
S
6.81K 51 6 1V5S0_RUNSS8 EN2 1
R7365 2 G
2 2.5V 1% S
POLY 1/20W GND PGND THRM_PAD 15.4K
<Rd> CASE-C2-SM-1 MF 1% <Rb>
1
3 2 1
2 201 1/20W 1
1
R7328 MF R7368
18
13
25
2 201 20.5K
20K 1%
1% 1/20W
1/20W 1 2 MF
MF
2 201 2 201
XW7300
SM
54 6 GND_1V51V05S0_SGND
Vout = 0.758V * (1 + Rc / Rd) Routing Note:
Vout = 0.758V * (1 + Ra / Rb)
put 6 vias under the thermal
pad (pin 25)
51 PGOOD_1V05S0 PGOOD_1V5S0 51
Note: pu on PGOOD page
Note: pu on PGOOD page
1.5V/1.05V Supplies
A
D 051-7230 B.0.0

NONE 54 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
1.8V/0.9V POWER SUPPLY
State PM_S4_STATE_L PM_SLP_S3_L PP1V8_S3 PP0V9_S0
S0 HIGH HIGH 1.8V 0.9V
S3 HIGH LOW 1.8V 0.0V
S5/G3Hot LOW LOW 0.0V 0.0V
Vout = 0.75V * (1 + Ra / Rb)
<Rb> NO STUFF
1 2 6 1V8S3_VDDQSET 1 2
R7522 <Ra> C7503
20K
1%
1/20W
100PF
R7521 5% Routing Note:
MF 28K 25V
C 201 1%
1/20W
MF
201
CERM
201
CONNECT VDDQSNS TO C7542 PIN1
using separate trace. C
1 2
72 55 32
1 2 31
8 6 PP0V9_S3
C7540
0.033UF
10%
16V
X5R
402 72
56
51
1 2 6 1V8S3_V5FILT 1 2 PP5V_S5 27
6 7
OMIT 8
C7500 R7507 1 C7502

39
54
58
4.7 10UF
1UF 5%
1/16W 20%
10% MF-LF 2 6.3V
10V 402 X5R
X5R 603
402-1
72 55 32 31 8 6 PP0V9_S3
OMIT
PP0V9_S0
72 33 8 7 6
1V8S3_VBST1 2
1 C7511
2.2UF
1V8S3_VBST_RC
20% 72 59 54 53 52 42 8 7 6 PPBUS_R_G3H
23
24
14
22
15
6.3V
R7500 2 CERM
9
2
1 CRITICAL CRITICAL
R7510 0 402-LF 5 CRITICAL 1 C7531
8.25K 5% 1
C7530 1
C7532 1UF
1%
1/20W
VDDQSET VTTREF VLDOIN VTT V5FILT VBST V5IN VDDQSNS VTTSNS 1/16W
MF-LF Q7520 47UF 47UF 10%
MF 402 SI7110DN 20% 20% 2 25V PWM FREQ. = 400 kHz
2 201 Routing Note: C7509 D
PWRPK-1212-8 2 10.0V
POLY
2 10.0V
POLY
X5R
603
CONNECT VTTSNS TO C7507 PIN1 1 0.1uF
10%
CASE-B2-1 CASE-B2-1
MAX CURRENT = 11A
using separate trace. 16V 4
X5R G CRITICAL
(inductor limited)
B 51 42 41 37 36 25 7 6
58
PM_SLP_S3_L
1V8S3_RUNSS
10
11
S3
S5
PGOOD 13 2
402
S
L7520 B
CRITICAL DRVH 21 1V8S3_DRVH
MIN_NECK_WIDTH=0.2 mm 1 2 3 1.0UH-22A-10M-OHM VOLTAGE=1.8V
U7500
SYM (1 OF 2) LL 20 1V8S3_LL MIN_LINE_WIDTH=0.6 mm
1 2
MIN_NECK_WIDTH=0.2 mm PP1V8_S3 6 7 8 16 18 21 31 32 34 35 51
68 72
SM-IHLP
6 COMP TPS51116 5
QFN 19 1V8S3_DRVL
CRITICAL
DRVL 1
6 1V8S3_CS 16 CS CRITICAL OMIT C7543
Routing Note:
MODE 4 D CRITICAL 1
C7542 1 C7541 330UF
20%
Q7521 330UF 10UF
20% 2 2.5V
Connect CS_GND to NC0 7 NC 20% POLY
Q7521 PIN1,2.3 4 G SI7108DNS 2 2.5V
POLY 2 6.3V
X5R CASE-C2-HF
using Kelvin connection. NC1 12 NC PWRPK-1212-8 CASE-C2-HF 603
S
OMIT OMIT
THRM_PAD CS_GND GND PGND VTTGND
Placement Note:
1 C7507 1 C7508 1 2 3
Placement Note:
10UF 10UF
25
17
18
PLACE C7507,C7508 GND NEAR PIN 1 20% 20% PLACE C7543 NEAR NB
2 6.3V
X5R 2 6.3V
X5R
603 603 (GND)
6 GND_1V8S3_SGND 1 2 PGOOD_1V8S3 6 51
Routing Note: XW7500
SM
put 6 vias under the thermal pad Placement Note:
PLACE XW7500, NEAR C7542 PIN 2
GND_1V8S3_CSGND 1 2
6
1.8V/0.9V Supplies
XW7501 SYNC_MASTER=M70 SYNC_DATE=01/09/2007
A SM

A
D 051-7230 B.0.0

NONE 55 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
5V/3.3V POWER SUPPLY

D D
State SMC_PM_G2_EN PP3V3_G3H PP5V_S5 PP3V3_S5
G3H LOW 3.3V 0.0V 0.0V
S0/S3/S5 HIGH 3.3V 5.0V 3.3V
Vout = 1V * (1 + Ra / Rb)
5.106V = 1V * (1 + 20K / 4.87K)
<Ra> <Rb>
GND_5V3V3S5_SGND 6 56
R7667 R7668
1
20K 2 1
4.87K2
NO STUFF 1% 1%
C7667 1/20W
MF
1/20W
MF
100PF 201 201
1 2 5VS5_FB
5% R7610 C7600 Routing Note:

C 25V
CERM
201
0
5%
1
0.001UF
10%
The discharge path (VO2) should have
a dedicated trace to the output cap;
C
1/16W 50V
MF-LF 2 CERM separate from the output voltage
Routing Note: 402 402
1 25V3V3S5_VREF sensing trace,
The discharge path (VO1) should have 5V3V3S5_V5FILT 6 56
a dedicated trace to the output cap; GND_5V3V3S5_SGND
56 6
5V3V3S5_TONSEL
1
2
3
5
4
6
7
8
VO1
COMP1
VFB1
VREF2
VFB2
COMP2
VO2
GND
PPBUS_G3H Routing Note:
put 6 vias under the thermal pad 72 64 59 56 50 45 37 8 7 6
PPBUS_G3H
1 CRITICAL 1 C7681 33 PWPD CRITICAL
C7680 1UF
(pin 33)
U7600 CRITICAL
47UF
20% 10% RSMRST_PWRGD
32 SKIPSEL
TPS51120 EN5 9 NC RSMRST_PWRGD 6 41 42 56
1 C7641
1UF
C7640
2 16V
56 42 41 6
2 10.0V X5R 6 LLP 10%
47UF
POLY
603-1 C7660 31 TONSEL EN3 10 NC C7620 16V 20%
CASE-B2-1
5 0.1UF R7660
0 30 PGOOD1
SYM (2 OF 3)
PGOOD2 11
R7620
0 0.1UF 5
2 X5R
603-1
10.0V
POLY
CASE-B2-1
10% 5% 5% 10%
16V 1/16W 6 SMC_PM_G2_EN29 16V
X5R
402 MF-LF 41 EN1 EN2 12 SMC_PM_G2_EN 1/16W
MF-LF X5R
402
CRITICAL D 402 58 56 402 D
Q7660 2 1 5VS5_VBST_RC
1 2 28
5VS5_VBST VBST1 VBST2 13 3V3S5_VBST 1 2 3V3S5_VBST_RC2 1
PWM FREQ. = 280 kHz SI7110DN
PWRPK-1212-8 G 4 MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
mm
27 DRVH1
5VS5_DRVH
mm DRVH2
MIN_LINE_WIDTH=0.6
143V3S5_DRVH
MIN_NECK_WIDTH=0.2
mm
mm 4 G
CRITICAL
Q7620 PWM FREQ. = 430 kHz
MAX CURRENT = 6.0A S
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
mm
26 LL1
mm5VS5_LL LL2 153V3S5_LL
MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
mm
mm S
SI7110DN
PWRPK-1212-8
MAX CURRENT = 7.8A
(inductor limited) MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm
(OCP setting limited)
3 2 1 MIN_NECK_WIDTH=0.2 25 DRVL1
5VS5_DRVL
mm DRVL2 163V3S5_DRVL MIN_NECK_WIDTH=0.2 mm 1 2 3
PP5V_S5 PP3V3_S5
V5FILT
1 2 1 2
PGND1
5VS5_VREG 21 VREG5
VREG3
PGND2
72 58 55 54 51 39 27 8 7 6 6 7 8 24 25 26 27 28 36 43 44
49 51 57 58 60 72
CRITICAL
B B
VIN
5VS5_CS 23 CS1
3V3S5_CS 18 CS2
CRITICAL
VOLTAGE=5V
MIN_LINE_WIDTH=0.6 mm L7660
3.3UH-6.5A
5 5
L7620 VOLTAGE=3.3V
24
22
20
19
17
MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
IHLP 2.2UH-14A
D D IHLP2525CZ-SM1
OMIT CRITICAL CRITICAL
CRITICAL CRITICAL CRITICAL CRITICAL
1 C7690
10UF
1
C7691 1
C7692 Q7661 G 4 4 G Q7621 1
C7652 1
C7651 1
OMIT
C7650
20% 150UF 150UF 150UF 150UF 10UF
20% 20% SI7110DN SI7110DN
2 6.3V
X5R 2 6.3V 2 6.3V PWRPK-1212-8 S 6 S
PWRPK-1212-8 20% 20% 20%
603 POLY
CASE-B2-HF
POLY
CASE-B2-HF 6 2 6.3V
POLY 2 6.3V
POLY 2 6.3V
X5R
6
3 2 1 1 2 3 CASE-B2-HF CASE-B2-HF 603
R7605
5.90K
1 1
R7603
7.15K
1% 1%
1/20W 1/20W
MF MF
201 2 2 201
5V3V3S5_V5FILT 6 56
8 7 6
72 64 59 56 50 45 37
PPBUS_G3H
R7601
4.7
5V3V3S5_VREG3
5%
1/16W
TABLE_ALT_HEAD
MF-LF
PART NUMBER ALTERNATE FOR
PART NUMBER
BOM OPTION REF DES COMMENTS: 402
1 2
TABLE_ALT_ITEM
128S0093 128S0092 ? C7682,C7680 KEMET T520V336M016ATE0457650

TABLE_ALT_ITEM
1 C7602
1UF 1 C7604
OMIT
1 C7605 1 C7603
OMIT
Placement Note: 5V/3.3V Supplies
128S0093 128S0092 ? C7640 KEMET T520V336M016ATE0457650
10% 10UF 1UF 10UF R7601,C7605 close to U7600 pin 20.
A 2 16V
X5R
603-1 2
20%
6.3V
X5R
10%
2 10V
X5R
20%
2 6.3V
X5R
C7602 close
C7604 close
to U7600
to U7600
pin 22.
pin 21. NOTICE OF PROPRIETARY PROPERTY
A
603 402-1 603
C7603 CLOSE TO U7600 PIN 19.
R7605,R7603 close to U7600. PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1 2 GND_5V3V3S5_SGND 6 56 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
XW7601
SM
MIN_LINE_WIDTH=0.3 mm II NOT TO REPRODUCE OR COPY IT
D 051-7230 B.0.0

NONE 56 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.425V G3H SUPPLY

D Supply needs to guarantee 3.31V delivered to SMC VRef generator D
72 50 8 7 6 PPDCIN_G3H D7790
SOD-323
6 P3V42G3H5_BOOST 2 1
B0530WS-X-F
R77951 1
100K
5%
C7791 PWM FREQ. = ???
0.22uF
3
1/20W CRITICAL
MF
201 2
VIN
10%
6.3V
CERM-X5R
2
L7790 MAX CURRENT = 0.3A
U7790 402 33UH-0.39A
LT1934 PP3V42_G3H 6 7 8 23 26 27 28 39 40 41 42
43 44 59 72
DFN
1 BOOST SW 2 72 6 PP3V42G3H_SW S1024AS-SM
CRITICAL MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm <Ra>
Q7730 will pull down
6 P3V42G3H_SHDN_L 4 SHDN FB 6
VOLTAGE=3.42V
1 C7792 1R7791
THRML
10PF 665K
P3V42G3H_SHDN_L in the event 5% 1% CRITICAL
GND PAD 2 25V 1/20W
of a keyboard SMC Reset Q7730 D 6 NPO
201 MF 1
C7793
7
5
generated when left shift,option,and control SSM6N15FE 2 201 100UF
SOT563 20%
and the power button is depressed. P3V42G3H_FB <Rb> 2 6.3V
POLY
CRITICAL B2-HF
1
2 G S 1 C7790 2 R7792
P3V42G3H_SHDN_L1 6 5.6UF D7791 383K
42 40 LSOC_PRESS_H 20%
SOD-323 1%
25V 1/20W
POSCAP
CASE-B2-SM-HF
B0530WS-X-F MF
Q7730 D 3 1 2 201
SSM6N15FE
C SOT563
C
5 G S 4 C7730
1
Vout = 1.25V * (1 + Ra / Rb)
0.22UF
10% 2
42 40 6 SMC_ONOFF_H 6.3V
CERM-X5R
402
1.25V S0 REGULATOR
44 43 36 28 27 26 25 24 8 7 6 PP3V3_S5
72 60 58 56 51 49
CRITICAL
NO STUFF 1
C7751
11
10
1
R7755
3
47UF
Continuous
0 20%
5% SVIN PVIN 4V
CERM-X5R 2
1/20W U7750 0805-1
B MF
2 201
6 P1V25S0_RT 15 RT
LTC3412A
QFN
B
1V25S0_RUNSS 1 PGOOD 12 PGOOD_1V25S0 6 51
51 6 RUN/SS
CRITICAL
6 P1V25S0_ITH 13 ITH 4 CRITICAL
6 P1V25S0_MODE 16 SYNC/MODE 5 L7750
1 SW 8 2.2UH-3.25A PP1V25_S0
R7753 6 7 8 16 18 19 21 26 27 51 72
8.25K 1 14 VFB 9 P1V25S0_SW

1%
R7756 MIN_LINE_WIDTH=0.6 mm Vout = 1.2516V
Burst
1/20W 0 THERM MIN_NECK_WIDTH=0.25 mm IHLP1616BZ-SM
MF 5%
201 1/20W SGND PGND PAD <Ra> 1 C7750 3.0A max output
2
6
7
17
MF
2.2NF
6 P1V25S0_ITH_RC 2
201 R7750 1 10% (Switcher limit)
47K 10V
1 2 X5R CRITICAL
R7754 1%
1/20W
201
C7755 1 CRITICAL
1 C7753 C7754 1 309K MF
1 C7756
1% 201 2
47UF
2.2NF 22PF 1/20W
20% 47UF
10% 5% 4V 20%
MF 2
2 X5R
10V 25V
NP0-C0G 2
2
201 XW7750 CERM-X5R
0805-1
4V
2 CERM-X5R
201 201 SM 0805-1
6 GND_P1V2S3_SGND 1 2
VOLTAGE=0V
MIN_NECK_WIDTH=0.2 mm P1V25S0_VFB
<Rb>
R7751 1
60.4K
1%
1/20W
MF
201 2
P1V25S0_VFB_DIV 3.42V/1.25V Switcher

<Rc> SYNC_MASTER=M70 SYNC_DATE=01/09/2007
A R7752 1
23.2K NOTICE OF PROPRIETARY PROPERTY
A
1%
1/20W
MF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
201 2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
Vout = 0.8V * (1 + Ra / (Rb + Rc)) III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
D 051-7230 B.0.0

NONE 57 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
S3 FETS & S3/S5 CONTROL
5V/3.3V S5 RUN/SS CONTROL 1.8V S3 RUN/SS CONTROL
R7870
100K
5%
1/20W
MF
201
58 41 36 25 6 IN PM_S4_STATE_L 1 2 1V8S3_RUNSS OUT 55
MAKE_BASE=TRUE
C 58 56 41 6 IN
SMC_PM_G2_EN
MAKE_BASE=TRUE
SMC_PM_G2_EN OUT 6 41 56 58
C
SMC_PM_G2_EN
1 C7870
OUT 6 41 56 58
0.47UF
10%
6.3V
2 CERM-X5R
1
R7856 402
10K
5%
1/20W
MF
201 2
CRITICAL
Q7865
FDC638P
SM-LF
PP5V_S3 6 7 8 40 60 72
6
5
B
72 58 56 55 54 51 39 27 8 7 6 PP5V_S5 4
2
1
5V S3 FET B
MOSFET FDC638P
R7805 3 C7801 CHANNEL P-TYPE
100K 0.0022uF
5%
1/20W
MF
10%
50V RDS(ON) 48 mOhm @4.5V
201 CERM
72 58 56 55 54 51 39 27 8 7 6
PP5V_S5 1 2 PM_SLP_S4_LS5V 1 2 6 P5VS3_EN_L
402
1 2 LOADING 0.051 A
R7806
10K
5%
1/20W CRITICAL
MF
D 6 201 Q7866
Q7860 FDC638P
SSM6N15FE SM-LF PP3V3_S3 6 7 8 36 42 44 48 51 60 72
SOT563
6
58 41 36 25 6 IN
PM_S4_STATE_L
2 G S 1 72 60
43 36
8 7 6
28 27 26 25 24
57 56 51 49 44
PP3V3_S5 4
5
2
3.3V S3 FET
1
1 MOSFET FDC638P
R7807
100K 3 CHANNEL P-TYPE
5%
1/20W R7808 C7802
MF
201 10K 0.01UF RDS(ON) 65 mOhm @2.5V
2 5% 10%
1/20W
MF
10V
X5R LOADING 0.098 A
201 201
1 2 6 P3V3S3_EN_L 1 2 S3 FET & S3/S5 Control
A
D 051-7230 B.0.0

NONE 58 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
PBUS SUPPLY / BATTERY CHARGER CRITICAL
Q7900 Q7901
AO4409
SOI
AO4409
SOI PBUS CURRENT SENSOR
PPVDCIN_G3H_PRE2 PPBUS_G3H
8
72 64 59 56 50 45 37 8 7 6
6 PP18V5_G3H PPVDCIN_G3H_PRE
3
72 50 8 7 72 45 6
6 7
6 7
MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.6 MM
2
CRITICAL MIN_NECK_WIDTH=0.2 MM
D
S
D
D
D R7981 C7980
1
1 1 1
D7910
7
SOD-323 21 0.1UF
10%
G
B0530WS-X-F 1% V+ 16V
1/16W 2 X5R
C7900 1 R79001 MF-LF
4
2 R7999
0.1UF 100K 100K
402 2 U7980 402
5% 6 CHGR_SGATE_DIV 2 1 LTC6102AP
10% 1/20W DFN
25V 2 MF
5%
X5R
R79621
57 44 43 42 2
402 201 2 26 23 8 7 6 PP3V42_G3H MIN_NECK_WIDTH=0.2 MM 1/20W -INF VREG 6 6 PBUS_ISENSE_VREG
41 40 39 28 27
72 59
MF PLACE C CLOSE TO SMC
1
62K 201 CRITICAL
1 C7960 5% 6 PBUS_ISENSE_IN_NEG 1 -INS OUT 4 SMC_PBUS_ISENSE 6 41
R7960 0.1UF 1/20W
MF
57.6K 5
10%
2 25V
201 2 72 59 55 54 53 52 42 8 7 6 PPBUS_R_G3H 8 +IN SHDN 3
1
1 C7989
1%
1/20W CHGR_AMON 1 X5R
402
R7989 0.22UF
MF VCC THM 4.53K 20%
6.3V
201 2 46 V- PAD 1% 2 X5R
CHGR_LOWCURRENT_GATE 1/20W 402
MF
9
3 GND 2 201 GND_SMC_AVSS 6
6 CHGR_LOWCURRENT_REF 41 42 45 53 59
CRITICAL
R79611
2 U7960
59 6 CHGR_DCIN TL331
1.82K SOT23-5
1%
1/20W
C7910 1 MF
201 2 PBUS_SMC_VSENSE_EN_L
0.1UF XW7920
45 42 6
10%
25V 2
R7923 SM LTC6102 DISABLED WHEN SHDN=1
X5R R7901 2
10 1 1 2
LTC6102 ENABLED WHEN SHDN=0
402 62K 72 6 PPVDCIN_G3H_PRE_0 CRITICAL
6 CHGR_SGATE 2 1 C7924 5% MIN_LINE_WIDTH=0.2MM
1
MIN_LINE_WIDTH=0.2 MM 5% 0.047UF 1 1/20W MIN_NECK_WIDTH=0.2MM
MF R7920
1/20W 10%
16V R7921 201 0.02
MF 10 0.5%
1 2CHGR_VDD 1 62 CHGR_VDDP 201 CERM
5% 1W
1 402
R7910 R7940
2 1/20W
MF
XW7921
SM
MF
2 0612
30.1K
1% C7941 4.7
5%
1 C7940 1
201
2 1
PPVDCIN_G3H_PRE_R 2
1/20W
72 59 57
23 8 7 6 PP3V42_G3H 1UF 1/16W 1UF
MF 44 43 42 41 40 39 28 27 26 10% MF-LF 10% MIN_LINE_WIDTH=0.2MM
2 10V
10V 402
C 201 2
(CHGR_ACIN) C7947
1UF
1 X5R
402-1
X5R
402-1
KELVIN CONNECTION
C
10% MIN_LINE_WIDTH=0.6 MM
10V 2
R79111 TO CURRENT SENSOR U7980
19
20
X5R C7995 C7996 MIN_NECK_WIDTH=0.2 MM 72 6 PP18V5_S5_CHGR_SW_R
9.76K 402-1
1% 0.1UF 1 1 0.1UF CRITICAL CRITICAL
1/20W VDD VDDP 10% 10%
MF
201 2 12 VHST AGATE 1 6 CHGR_AGATE
CRITICAL 25V
X5R
25V
X5R
1
C7920 1
C7921 1 C7922 1 C7923
402 402 22UF 22UF 1UF 1UF CRITICAL
71 59 50
7 6 SMBUS_SMC_BSA_SCL
11 SCL U7900 CSIP 6 28 CHGR_CSIP 2 2
20%
25V
20%
25V
10%
25V
10%
25V
pullups offpage 44 41
SMBUS_SMC_BSA_SDA
10 SDA
QFN
CSIN 6 27 CHGR_CSIN
2
POLY 2 POLY 2 X5R 2 X5R R7980
ISL6258
71 59 50 44 41 7 6
CASE-D2-LF CASE-D2-LF 603 603 0.0022
OMIT GND_CHGR_SGND 6 59 1 PPBUS_R_G3H 6 7 8 42 52 53 54 55 59 72
CHGR_BGATE
5
59 6 16
BGATE
4 VREF 1%
NC DCIN 2 CHGR_DCIN 6 59
D
1/4W
3 ACIN CRITICAL MF-LF
BOOT 6 25 CHGR_BOOT Q7920
FDM6296
CRITICAL
1206
TO SYSTEM
CHGR_ICOMP 5 CHGR_UGATE
G
ICOMP UGATE 24 MICROFET3X3 1 2 PPBUS_G3H 6 7 8 37 45 50 56 59 64 72
CHGR_VCOMP 7 VCOMP PHASE 23 CHGR_PHASE
C7925
S
C7942 1 6 CHGR_VNEG 8 VNEG 1
F7900 CRITICAL
1
2
3
LGATE 21 CHGR_LGATE 0.1UF CRITICAL
33000PF 6 CHGR_CSOP 18 CSOP 10%
25V 7AMP-24V R7930
10% TRKL* 13 NC 1206 0.01
6.3V
X5R 2 6 CHGR_CSON 17 CSON
CHGR_AMON 59
X5R
402 2 L7900 0.5%
201 R79451 C7943
AMON 9 6 4.7UH-7.5A MIN_LINE_WIDTH=0.6 MM 1W
MF MIN_LINE_WIDTH=0.6 MM
29 THRM_PAD
56.2K 15 CHGR_BMON MIN_NECK_WIDTH=0.2 MM 0612 MIN_NECK_WIDTH=0.2 MM
BMON 2 1 PPVBAT_G3H_CHGR_REG PPVBAT_G3H_CHGR_OUT
1% 0.1UF 72 6 1 2 6 59 72
1/16W ACOK 14 SMC_BC_ACOK 6 41 42 50 59 MIN_LINE_WIDTH=0.6 MM
1 C7944 1 2 IHLP4040CZ-SM
6 AGND
PGND
MF-LF MIN_NECK_WIDTH=0.2 MM
0.01UF 402 2 CRITICAL CRITICAL 1 C7935
5
10%
10V 6 CHGR_VCOMP_R 10%
C7930 1
C7931 1UF
16V 10%
D
2 X5R CRITICAL 47UF 47UF 2 25V
26
22
X5R
201 C7945 1 402
Q7921 20%
10.0V
20%
2 10.0V
X5R
603
0.001UF FDM6296 POLY POLY
4
10%
G
MICROFET3X3 CASE-B2-1 CASE-B2-1 2
GND_CHGR_SGND 50V
59 6
CERM 2 XW7930
402
S
SM
2
1 2
XW7931
B
1
2
3
B XW7900
1 C7926
1000PF
1 SM
R79461
3.01K
SM 10%
16V
2 X7R
PWM FREQ. = 400 kHz PPVBAT_G3H_CHRGR_REG_0 6 72
1
1%
1/16W 201
MAX CURRENT = ??A R79311 72 6 PPVBAT_G3H_CHRGR_REG_R
MF-LF 10 MIN_LINE_WIDTH=0.2MM
402 2 5% MIN_NECK_WIDTH=0.2MM
6 CHGR_VNEG_R GND_CHGR_SGND (??? limited) 1/20W

MF R79471
201 2
10
C7946 1 5%
1/20W
470PF MF
10% (CHGR_CSOP) (CHGR_CSOP) 201 2
50V
CERM 2
402 (CHGR_CSON)
44 41 7 6
71 59 50
SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SCL 6 7 41 44 50 59 71
44 41 7 6
71 59 50
SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SDA 6 7 41 44 50 59 71
ACOK pullup/down on SMC page

SMC_BC_ACOK
50 42 41 6
59
MAKE_BASE=TRUE
SMC_BC_ACOK 6 41 42 50 59
AMON PULLDOWN LOGIC
PLACE RC CLOSE TO SMC
CHGR_AMON 6 59
BATTERY CHARGING
59 6
CHGR_BMON 1 2 SMC_BATT_ISENSE 6 41 CRITICAL
1NO STUFF Q7950
R7971
0
1
72
39 28 27 26 23 8 7 6
59 57 44 43 42 41 40
PP3V42_G3H R7975
1M AO4409 TO BATTERY
5%
1/20W
C7972 5%
SOI
MF 0.68UF 1/20W MIN_NECK_WIDTH=0.2 MM
Q7970 BATT_POS_F 6
7 8
201 1
10% R7974 MF
PPVBAT_G3H_CHGR_OUT 50
3
6.3V
2 201
72 59 6
2 CERM 1M SSM6N15FE D 6
PBUS Supply/Battery Charger
1 2
402 5% SOT563
1 C7950 1 C7951
5 6
S
D
GND_SMC_AVSS 1/20W
A 6 41 42 45 53 59 MF
201 2 0.01UF
10%
2 10V
0.1UF
10%
2 16V
A
G
PLACE RC CLOSE TO SMC X5R X5R NOTICE OF PROPRIETARY PROPERTY
6 CHGR_VDD
CHGR_AMON 1 2 SMC_DCIN_ISENSE 59
G S 1 201 402
4
59 6 6 41 2
R7970 1 C7971 Q7970 D 3 CHGR_VDD_L AGREES TO THE FOLLOWING
0
5%
1/20W
0.68UF
10% R79731 SSM6N15FE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MF
201 2 6.3V
CERM
1M SOT563
CHGR_BGATE 6 II NOT TO REPRODUCE OR COPY IT
5% 59
402 1/20W III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
MF
GND_SMC_AVSS 6 41 42 45 53 59 201 2
5 G S 4 SIZE DRAWING NUMBER REV.
CHGR_VDD_R
D 051-7230 B.0.0

NONE 59 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
72 58
28 27 26 25 24 8 7 6 PP3V3_S5 CRITICAL
57 56 51 49 44 43 36
1 Q9003
R9002 FDC638P
5%
100K
1/20W
SM-LF
6 PP3V3_LCDVDD_SW
LCD + CAMERA CONNECTOR
MF 72 6
2 201 5 VOLTAGE=3.3V
R9023 4
2 OMIT
CRITICAL
D LCDVDD_PWREN_L
10K 1 1 C9011 1 C9012 L9007 D
2
6
C9040 1
5% 0.1UF 10UF 90-OHM-100MA
0.1UF Q9004 1/20W 10% 20% 1210-4SM1
SYM_VER-1
10% SSM3K15FV D MF 2 6.3V 2 6.3V
6.3V 2
X5R SOD-VESM
3 201
LCDVDD_PWREN_L_R
3 X5R
201
X5R
603 69 24 9 6 BI USB2_CAMERA_N 1 4 L9052
201 6
240-OHM-0.2A-0.8-OHM
C9013 2 3 44 41 7 6 SMBUS_SMC_B_S3_SDA 1 2 6 I2C_TOP_ALS_SDA_F
0.0033UF 69 24 9 6 BI USB2_CAMERA_P 0201
1 2 CRITICAL
5
TC7SZ08AFEF
SOT665 1 G S 2
L9005 L9051
PLT_RST_L 2 10% 240-OHM-0.2A-0.8-OHM
24 7 6
64 28
IN A 50V FERR-120-OHM-1.5A
4
LVDS_VDD_GATED_EN CERM SMBUS_SMC_B_S3_SCL 1 2 6 I2C_TOP_ALS_SCL_F
U9040Y 402 58 40 8 7 6 PP5V_S3 1 2 44 41 7 6
15 6 LVDS_VDD_EN 1 72 0201
IN B 0402-LF
1
3 C9016 1 1 C9052 CRITICAL
R9014 1000PF
10%
10PF C9051 1
J9000
100K 16V
5%
25V 10PF
1% X7R 2 2 NPO 20347-130E-11
1/20W CRITICAL 201 201
5%
25V F-RT-SM
MF 2
2 201
L9004 NPO
201
38
FERR-120-OHM-1.5A
1 2 1
0402-LF 2
C9015 1 3
1000PF VOLTAGE=5V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 72 7 6 PP5V_S3_CAMERA_F 4
10%
16V USB2_CAMERA_F_P 5
PLACE FILTERS AND CAPS NEAR PINS ON CONNECTOR X7R 2 69 7 6
201 69 7 6 USB2_CAMERA_F_N 6 CAMERA I/F
7
L9008 VOLTAGE=3.3V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 72 7 6 PP3V3_LCDVDD_SW_F 8
120-OHM-0.3A-EMI 9 LCD I/F
64 63 53
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0 1 2 (LVDS DDC POWER) VOLTAGE=3.3V MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 72 7 6 PP3V3_S0_LCD_F 10
C 52 51 46 44 42 30 29 28 27 26
0402-LF 11
12
C
C9010 1
67 6 LVDS_A_DATA_F_N<0> 13
1000PF
LVDS REFERENCE CURRENT,2.37K OHM PULL DOWN RESISTOR NEEDED 10% 67 6 LVDS_A_DATA_F_P<0> 14
16V 2
X7R 67 6 LVDS_A_DATA_F_N<1> 15
201
R9013 67 6 LVDS_A_DATA_F_P<1> 16
LVDS_IBG 2.37K2
1 67 6 LVDS_A_DATA_F_N<2> 17
67 15 6
1% 67 6 LVDS_A_DATA_F_P<2> 18
1/20W
MF 7 6 LVDS_A_CLK_F_N 19
201
7 6 LVDS_A_CLK_F_P 20
PLACE NEAR NB 21
7 6 LCDBKLT_RTN<1> 22
64
1 LCDBKLT_RTN<2> 23
R9008 R9009
7 6
1 64
10K 7 6 LCDBKLT_RTN<3> 24
10K 5% 64
LCDBKLT_RTN<4> 25
5% 1/20W 7 6
1/20W MF 64
26
MF 2 201 7 6 LCDBKLT_RTN<5>
2 201
64
15 7 6 LVDS_DDC_CLK 7 6 LCDBKLT_RTN<6> 27
BI 64
15 7 6 LVDS_DDC_DATA 28
BI
7 6 PPVOUT_S0_LCDBKLT 29
72 64
30
31
32
CRITICAL
33
67 15 7 LVDS_A_DATA_N<0>
L9010 34
BI 2 3
67 15 7 LVDS_A_DATA_P<0> 35
BI
B 1
1210-4SM1
SYM_VER-2
4
36
37 B
90-OHM-100MA
39
CRITICAL
LVDS_A_DATA_N<1>
L9011
67 15 7
67 15 7
BI
BI LVDS_A_DATA_P<1>
2 3 518S0433
1 SYM_VER-2
4
1210-4SM1
90-OHM-100MA
MIC CONNECTOR CRITICAL
67 15 7 6 LVDS_A_DATA_N<2>
L9012
BI 2 3
LVDS_A_DATA_P<2>
CRITICAL L9050 67 15 7 6 BI
J9050 240-OHM-0.2A-0.8-OHM
1 4
GS03067-11131-7F 1 2 PP3V3_S3 6 7 8 36 42 44 48 51 58 72
1210-4SM1
SYM_VER-2
F-RT-SM MIN_LINE_WIDTH=0.20MM 90-OHM-100MA
7 MIN_NECK_WIDTH=0.20MM 0201
VOLTAGE=3.3V
CRITICAL
1 PP3V3_S3_MIC_F L9006
2 NC L9030 90-OHM-100MA
1210-4SM1
3 NC 240-OHM-0.2A-0.8-OHM 67 15 6 LVDS_A_CLK_N 1 SYM_VER-2 4
BI
4 6 AUD_MIC_DATA_F 1 2 AUD_MIC_DATA 6 7 37 67 15 6 BI LVDS_A_CLK_P
5 6 AUD_MIC_CLK_F 0201
2 3
6 GND_MIC_F L9031 LVDS,Camera Conn. and ALS Conn.
240-OHM-0.2A-0.8-OHM
8 1 2 AUD_MIC_CLK SYNC_MASTER=GPU SYNC_DATE=06/23/2006
A L9053
240-OHM-0.2A-0.8-OHM 0201
6 7 37

A
1 2
MIN_LINE_WIDTH=0.20MM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
MIN_NECK_WIDTH=0.20MM 0201 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1 AGREES TO THE FOLLOWING
C9050
0.01UF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
10%
APN:518S0356 10V
X5R
201
2
1 C9053
NO STUFF 1
C9030
10PF
1 NO STUFF
C9031
10PF
0.01UF 5% 5% SIZE DRAWING NUMBER REV.

10% 25V 25V
2 2 NPO
2 10V NPO
X5R
201
201 201
D 051-7230 B.0.0

NONE 60 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL CRITICAL
L9206 L9201
FERR-120-OHM-1.5A FERR-120-OHM-1.5A R9207 R9237
49.9 49.9
61 51 22 19 8 7 6 PP1V8_S0 1 2 PP1V8_S0_ANALOG_TMDS_F 72 61 51 22 19 8 7 6 PP1V8_S0 1 2 PP1V8_S0_TMDS_F 6 61 72 67 63 61 6 TMDS_TX_P<0> 1 62 TMDS_TX<0> 1 2 TMDS_TX_N<0> 6 61 63 67
72 VOLTAGE=1.8V VOLTAGE=1.8V
0402-LF MIN_LINE_WIDTH=0.5MM 0402-LF MIN_LINE_WIDTH=0.5MM 1% 1%
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM 1/20W 1/20W
OMIT OMIT MF MF
1C9207 1 C9208 1C9209 1 C9210 1C9211 1 C9212 201 1 C9222 201
1 C9236 1 C9237 1C9238 1C9239 1 C9240 1 C9213
0.1UF 1000PF 0.1UF 1000PF 0.1UF 1000PF 1000PF
1000PF 1000PF 0.1UF 0.1UF 10UF 10% 10% 10% 10% 10% 10% 10UF 10%
6.3V 16V 6.3V 16V 6.3V 16V
10%
16V
10%
16V
10%
6.3V
10%
6.3V
20%
6.3V 2 X5R 2 X7R 2 X5R 2 X7R 2 X5R 2 X7R
20%
6.3V 2 16V
X7R
2 X7R 2 X7R 2 X5R 2 X5R 2 X5R 201 201 201 201 201 201 2 X5R 201
201 201 201 201 603 603
D ONE 0.1UF AND 1000PF FOR EACH PIN

ONE 0.1UF AND 1000PF FOR EACH PIN
R9208 R9238 D
CRITICAL 49.9 49.9
67 63 61 6 TMDS_TX_P<1> 1 2 6 TMDS_TX<1> 1 2 TMDS_TX_N<1> 6 61 63 67
L9203 1C9250 1 C9251 1C9252 1 C9253 1C9261 1 C9262 1% 1%
FERR-120-OHM-1.5A 0.1UF 1000PF 0.1UF 1000PF 0.1UF 1000PF 1/20W 1/20W
10% 10% 10% 10% 10% 10% MF MF
47 38 8 6 PP3V3_B_S0 1 2 PP3V3_S0_ANALOG_SDVO_F 6 61 72 2
6.3V
2
16V
2 6.3V 2 16V 2 6.3V 2 16V 201 1 C9223 201
63 62 61 51 X5R X7R X5R X7R X5R X7R
VOLTAGE=3.3V
0402-LF MIN_LINE_WIDTH=0.3MM
201 201 201 201 201 201 1000PF
10%
2 16V
X7R
1 1C9231 1 CRITICAL 201
C9230 C9214
1000PF 0.1UF 1000PF
L9200
10% 10% 10% FERR-120-OHM-1.5A
2 16V
X7R 2 6.3V
X5R 2 16V
X7R
201 201 201 72 61 51 22 19 8 7 6 PP1V8_S0 1 2 PP1V8_S0_ANALOG_SDVO_F 6 61 72
VOLTAGE=1.8V
R9209 R9239
MIN_NECK_WIDTH=0.2MM 49.9 49.9
OMIT 67 63 61 6 TMDS_TX_P<2> 1 2 6 TMDS_TX<2> 1 2 TMDS_TX_N<2> 6 61 63 67
1 C9200 1 C9201 1C9202 1
C9204 1%
1/20W
1%
1/20W
CRITICAL 1000PF 1000PF 0.1UF 10UF MF MF
10% 10% 10% 20% 201 201
L9204 16V
2 X7R
16V
2 X7R 2 X5R
6.3V
2
6.3V
X5R
1 C9224
FERR-120-OHM-1.5A 201 201 201 603 1000PF
10%
61 51 22 19 8 7 6 PP1V8_S0 1 2 PP1V8_S0_PVCC1_TMDS_F 6 61 72 2 16V
X7R
72 VOLTAGE=1.8V
0402-LF 201
MIN_NECK_WIDTH=0.2MM ONE 1000PF FOR EACH PIN
1 C9232 1 C9254 1C9233 1C9206
1000PF
10%
1000PF
10%
0.1UF
10%
0.1UF
10%
R9210 R9240
49.9 49.9
2 16V
X7R 2 16V
X7R 2 6.3V
X5R 2 6.3V
X5R 67 63 61 6 TMDS_TX_CLK_P 1 2 6 TMDS_TX_CLK 1 2 TMDS_TX_CLK_N 6 61 63 67
201 201 201 201 1% 1%
1/20W 1/20W
MF MF
201 1 C9225 201
1000PF
10%
TWO 0.1UF AND 1000PF FOR EACH PIN
2 16V
C CRITICAL
L9205
X7R
201 C
FERR-120-OHM-1.5A
72 61 51 22 19 8 7 6 PP1V8_S0 1 2 PP1V8_S0_PVCC2_TMDS_F 6 61 72
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.2MM 72 61 6 PP3V3_S0_ANALOG_SDVO_F PP3V3_B_S0 6 8 38 47 51 61 62 63
1 C9234 1 C9235 1C9255 1C9256 OMIT
72 61 6 PP1V8_S0_ANALOG_SDVO_F
1000PF
10%
1000PF
10%
0.1UF
10%
0.1UF
10%
1C9221 1 C9205
2 X7R
16V 16V
2 X7R 2 X5R
6.3V
2 X5R
6.3V
72 61 6 PP1V8_S0_PVCC2_TMDS_F 0.1UF 10UF
10% 20%
201 201 201 201 6.3V 6.3V
2 X5R 2 X5R
72 61 6 PP1V8_S0_PVCC1_TMDS_F 201 603
TWO 0.1UF AND 1000PF FOR EACH PIN 72 61 6 PP1V8_S0_ANALOG_TMDS_F

CRITICAL
72 61 6 PP1V8_S0_TMDS_F PP3V3_S0_SPVCC_TMDS_F 6 61 72
L9207 PP3V3_B_S0
FERR-120-OHM-1.5A 6 8 38 47 51 61 62 63
NO STUFF
33
38
43
48
50
56
17
31
21
27
32
37
64
62
PP3V3_B_S0 1 2 PP3V3_S0_SPVCC_TMDS_F
51 47 38 8 6 6 61 72
R9254
2
9
63 62 61 VOLTAGE=3.3V PP1V8_S0_ANALOG_SDVO_F 1C9290
0402-LF 72 61 6
0.1UF 0
2 1
OVCC
PVCC1
PVCC2
SPVCC
AVCC3_3
HDAVCC
1 10%
1 C9257 1 C9258 1C9259 1C9260 R9204 VCC SVCC AVCC1_8 6.3V
2 X5R 5%
MCH SDVO CHANNEL R,G,B,CLK SIGNAL TO TMDS CHIP 360 1/20W
1000PF 1000PF 0.1UF 0.1UF PLACE THESE CAPS NEAR NB 201
CRITICAL MF
10% 10% 10% 10% 5%
67 15 6 IN PEG_R2D_C_N<0> 1/20W TC7SZ08AFEF 5 201
2 16V 2 16V 2 6.3V 2 6.3V MF CRITICAL 2
X7R X7R X5R X5R PEG_R2D_C_P<0> SOT665 TMDS_HW_RESET_L
201 201 201 201 67 15 6 IN 2 201
TMDS_TX_N<0> 22 TX0-
U9200 RESET* 1 TMDS_RST_L 4
A 6 28 62
PEG_R2D_C_N<1>
67 63 61 6 OUT YU9290
67 15 6 IN
67 63 61 6 OUT TMDS_TX_P<0> 23 TX0+ SIL1392 B
1 TMDS_SW_RESET_L 6 25
TWO 0.1UF AND 1000PF FOR EACH PIN 67 15 6 IN PEG_R2D_C_P<1> QFN SDSCL 7 SDVO_CTRLCLK BI 6 16 61
67 63 61 6 TMDS_TX_N<1> 25 TX1- 3
PEG_R2D_C_N<2> OUT SDVO_CTRLDATA
67 15 6 IN SDSDA 6 BI 6 16 61
67 63 61 6 OUT TMDS_TX_P<1> 26 TX1+
67 15 6 IN PEG_R2D_C_P<2>
HOST SERIAL DATA CONFIGURATION A1 8 ADDRESS=0X70
67 63 61 6 OUT TMDS_TX_N<2> 28 TX2- ADDRESS=0X72 IF A1 IS PULLED HIGH
67 15 6 PEG_R2D_C_N<3> RECEIVER CORE /PROGRAMMING
B 67 15 6
IN
IN PEG_R2D_C_P<3>
67 63 61 6 OUT TMDS_TX_P<2> 29 TX2+
(int pulldown)
HTPLG 42 DVI_HOTPLUG_DET 6 24 61 62
B
67 63 61 6 OUT TMDS_TX_CLK_N 19 TXC-
SDADDC 12 TMDS_DDC_SDA BI 6 7 37 62 63 67
1 1 1 1 1 1 1 1 67 63 61 6 OUT TMDS_TX_CLK_P 20 TXC+
C9241 C9242 C9243 C9244 C9245 C9246 C9247 C9248 TO TMDS CONNECTOR
SCLDDC 11 TMDS_DDC_SCL BI 6 7 37 62 63 67
10% 10% 10% 10% 10% 10% 10% 10%
6 TMDS_EXT_SWING 16 EXT_SWING I2C MASTER
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 13 NC
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R (int pullup) SDAROM
201 201 201 201 201 201 201 201 TMDS_SDR_N 52
67 6 SDR-
(int pullup) SCLROM 14 NC PP3V3_B_S0 6 8 38 47 51 61 62 63
67 6 TMDS_SDR_P 51 SDR+
62 61 24 6 DVI_HOTPLUG_DET
67 6 TMDS_SDG_N 55 SDG- SPDIF/HDASDO 34 NC
"Place R9250 near U2300.F12"
67 6 TMDS_SDG_P 54 SDG+ HDASYNC 40 NC
1
R9250 AUDIO HDABCLK 39 NC R92511
100K 67 6 TMDS_SDB_N 58 SDB- 4.7K
5%
DIFFERENTIAL HDASDI 36 NC 5%
1/20W 67 6 TMDS_SDB_P 57 SDB+ 1/20W
MF SIGNAL DATA HDARST* 35 TMDS_HDARST_L MF
2
201 C9219 201
2
67 6 TMDS_SDC_N 61 SDC-
0.1UF
10% 6.3V
C9220 TMDS_LSCL TMDS_LSCL
X5R 201
67 6 TMDS_SDC_P 60 SDC+ LSCL/DCEN 4 6 61 62
0.1UF MAKE_BASE=TRUE
10% 6.3V
1 2 X5R 201 TMDS_LSDA TMDS_LSDA
67 15 6 OUT PEG_D2R_N<1> 67 6 TMDS_INT_N 47 SDI- LOCAL I2C LSDA/PREEMP 3 6 61 62
1 2 MAKE_BASE=TRUE
67 15 6 OUT PEG_D2R_P<1> 67 6 TMDS_INT_P 46 SDI+
TMDS_LINT_L
TMDS CHIP SDVO INPUT INTERRUPT SIGNAL TO MCH LINT* 15 6 62
6 TMDS_EXT_RES 49 EXT_RES
NO STUFF1 1NO STUFF
63 62 61 51 47 38 8 6 PP3V3_B_S0 R9253 R9252
44 TEST 0 0
1 1
FACTORY TEST MODE 5% 5%
R9201 R9202 R92031 1/20W
MF
1/20W
MF
2.94K 2.94K 1K
SPGND
201
1% 1% 1% 2 2 201
PLACE R9200,U9201 CLOSE TO
RIO CONN J4200
1/20W
MF
201
1/20W
MF
201
1/20W
MF
201 2
GND SGND AGND THRM_PAD SDVO/TMDS Tx
2 2
SYNC_MASTER=GRAPHIC SYNC_DATE=06/06/2005
A A
5
10
41
45
53
59
63
18
24
30
65
CRITICAL 61 16 6 BI SDVO_CTRLCLK BI
5 U9201 61 16 6 BI SDVO_CTRLDATA BI NOTICE OF PROPRIETARY PROPERTY
R9200 74LVC1G17DRL
SOT-553
10K 2 4 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
6 IN TMDS_HTPLG 1 2TMDS_HTPLG_R DVI_HOTPLUG_DET_BUF 6 62 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
7 AGREES TO THE FOLLOWING
37 5%
63 5.5V TOL INPUT NC 3.3V ACTIVE OUTPUT
1/20W I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MF 1 1
201 1 3 R9211 R9212 II NOT TO REPRODUCE OR COPY IT
9.09K 9.09K
R9200 INSURES ESD DIODE 1 1% 1% III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
R9213 1/20W 1/20W
CURRENT IS SMALL MF MF
270K 201 2 201 2 SIZE DRAWING NUMBER REV.
5%
1/20W
MF
201 2
D 051-7230 B.0.0

NONE 61 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SST8051 microcontroller for HDCP support
D PP3V3_B_S0 6 8 38 47 51 61 62 63 D
SST8051
CRITICAL
L9300
FERR-120-OHM-1.5A
61 51 47 38 8 6PP3V3_B_S0 1 2
63 62 SST8051 6 PP3V3_S0_HDCP_F
1 MIN_LINE_WIDTH=0.30MM
C9341 MIN_NECK_WIDTH=0.20MM 0402-LF
0.1UF VOLTAGE=3.3V SST8051
10% SST8051 SST8051 CRITICAL
6.3V
X5R 2 1 C9302 1 C9301 1 C9300
201 0.01UF 0.1UF 10UF
10% 10% 20%
10V 6.3V 6.3V
2 X5R 2 X5R 2 X5R
DVI_HOTPLUG_DET_BUF 201 201 603
62 61 6
CRITICAL
SST8051
SST8051 U9340
R93401 1
8 74LVC2G132
US8
1
R9306
10K A 4.7K
5% SST8051 7 5%
1/20W CRITICAL 132 Y 1/20W
MF MF
201 2 U9340 2
B
SST8051 1 2 201
8 74LVC2G132 1 SST8051 SST8051 SST8051
6 DVI_HPDET_RC 5
A
US8 4 R9302 R9303 R93041 1
R9305
SST8051 SST8051 3 2.2K 2.2K
2.2K 2.2K
35
132 Y DVI_HOTPLUG_DET_DEL_L 5% 5%
6
C9340 1 1/20W 1/20W 5% 5%
6 MF MF 1/20W 1/20W
1UF B
201 2 2 201 MF MF
10% VDD 201 2
6.3V
2 4 6 DVI_HOTPLUG_DET_INT_L 7 (INT0#)P3.2 OMIT P0.0(AD0) 34 2 201
CERM
CRITICAL
2
603-1 TMDS_LINT_L 8 33
(INT1#)P3.3 P0.1(AD1) 6 SST8051_DDC_EN
61 6
U9300
G
TP_SST8051_RXD 5 (RXD)P3.0 P0.2(AD2) 32
62 6 SST8051_P34_AUDIO_CONFIG 9 (T0)P3.4
SST89V54RD P0.3(AD3) 31
WQFN
D
NC 10 (T1)P3.5 P0.4(AD4) 30 NC TMDS_DDC_SCL BI 6 7 37 61 63 67
10MS RC GENERATES ONE-SHOT LOW PULSE ON SST8051
6
1
C INT0# TO ALLOW PART TO WAKE UP
SST8051
NC 12 (RD#)P3.7
NC 11 (WR#)P3.6
P0.5(AD5)
P0.6(AD6)
29
28 Q9300 C
AND XTAL TO START C9390 TP_SST8051_TXD 6 (TXD)P3.1 P0.7(AD7) 27 SSM6N15FE
SOT563
22PF
2 1
P1.0(T2) 36 SST8051_UPDATE_L 6 25 62
5% OMIT P1.1(T2_EX) 37 DVI_HOTPLUG_DET_BUF 6 61 62
25V
5
NP0-C0G 1 SST8051_DVI_HOTPLUG_DET
201 Y9390 P1.2(ECI) 38
G
2 14.318MHZ-35PPF-20PF P1.3(CEX0) 39 NC
SST8051 SM-2.5X2.0MM
C9391 4 P1.4(CEX1/SS*) 40 6 SST8051_DDC_CLK
3
D
22PF 6 SST8051_XTAL1 14 XTAL1 (CEX2/MOSI)P1.5 1 6 SST8051_DDC_DATA TMDS_DDC_SDA BI 6 7 37 61 63 67
SST8051
3
4
1 2 6 SST8051_XTAL2 13 XTAL2 (CEX3/MISO)P1.6 2
5% (CEX4/SCK)P1.7 3 Q9300
25V 6 SST8051_RST 4 RST SSM6N15FE
SOT563
NP0-C0G
63 62 61 51 47 38 8 6 PP3V3_B_S0 201 A8(P2.0) 16 NC
SST8051
1 62 6 SST8051_EA_L 26 EA* A9(P2.1) 17 NC
C9326 18
0.1UF A10(P2.2) NC
10%
6.3V NC 25 ALE/PROG* A11(P2.3) 19 NC TMDS_LSCL BI 6 61
2 X5R
A12(P2.4) 20 NC
201
62 25 6 SST8051_UPDATE_L 24 PSEN* P2.5(A13) 21 SST8051_P25_AUDIO_CONFIG 6 62
P2.6(A14) 22 NC
CRITICAL SST8051 P2.7(A15) 23 NC TMDS_LSDA 6 61
5
BI
VCC THRM_PAD VSS
TMDS_HW_RESET_L 2 A
61 28 6
U9325
41
15
Y 4
TC7SH00FEF
25 6 SST8051_SW_RESET_L 1 B SON
GND SST8051
1
R9325
3
B 1%
10K B
1/20W
MF
2 201
NO STUFF
R9350
0
62 6 SST8051_DVI_HOTPLUG_DET 1 2 DVI_HOTPLUG_DET 6 24 61
5%
1/20W
MF
201
PP3V3_B_S0 6 8 38 47 51 61 62 63
R9351
0
62 61 6 DVI_HOTPLUG_DET_BUF 1 2
62 25 6 SST8051_UPDATE_L SST8051_UPDATE_L 6 25 62
MAKE_BASE=TRUE SST8051 5%
1/20W
1
SST8051_UPDATE_L pulled up to 10K at SB R9330 MF
201
4.7K
1%
1/20W STUFFING OPTION CHOOSES RAW OR CONTROLLER OUTPUT
MF
2 201 OF DVI_HOTPLUG_DET
63 62 61 51 47 38 8 6 PP3V3_B_S0
AUDIO CONFIG OPTIONS

SST8051
62 6 SST8051_P25_AUDIO_CONFIG P25 P34 OPTION
R93011
10K 0 0 HD AUDIO
1%
1/20W
MF
0 1 SPDIF HDCP uController
201 2 1 0 NO AUDIO
SYNC_MASTER= SYNC_DATE=
A 62 6 SST8051_P34_AUDIO_CONFIG 1 1 RESERVED
A
62 6 SST8051_EA_L SST8051
1
R9333 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
4.7K AGREES TO THE FOLLOWING
1%
1/20W I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MF
2 201 II NOT TO REPRODUCE OR COPY IT
D 051-7230 B.0.0

NONE 62 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NB VIDEO ALIASES
67 63 15 6 CRT_TVO_IREF CRT_TVO_IREF 676 63 15 6 CRT_BLUE CRT_BLUE 6 15 63 67
MAKE_BASE=TRUE 15 63 67 MAKE_BASE=TRUE
67 63 15 6 TV_A_DAC TV_A_DAC 6 15 63 67
67 63 15 6 TV_B_DAC TV_B_DAC 6 15 63 6
CRT_GREEN CRT_GREEN 6 15 63 67
MAKE_BASE=TRUE 67 MAKE_BASE=TRUE
67 63 15 6 TV_C_DAC TV_C_DAC 6 15 63 67
MAKE_BASE=TRUE
67 63 15 6 CRT_RED CRT_RED
MAKE_BASE=TRUE
6 15 63 67
Video Connectors
67 63 15 6 CRT_HSYNC_R CRT_HSYNC_R 6 15 63 67
MAKE_BASE=TRUE
D 67 63 15 6 CRT_VSYNC_R CRT_VSYNC_R
MAKE_BASE=TRUE
6 15 63 67
D
TMDS(MICRO DVI) INTERFACE
EXTERNAL VIDEO (VGA) INTERFACE
Isolation required for DVI power switch
A 1.3K OHM 1% RESISTOR IS REQUIRED BETWEEN CRT_IREF CRITICAL
AND GROUND F9404 L9444
0.5AMP-13.2V 600-OHM-300MA
R9469 53 52 51 47 43 40 27 22 8 7 6 PP5V_S0 1 2 72 6 PP5V_S0_TMDS_FUSE 1 2 PP5V_S0_DVIPORT 6 7 37 72
PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR CONNECTOR
CRT_TVO_IREF 1
1.3K 2 72 VOLTAGE=5V VOLTAGE=5V 0402 VOLTAGE=5V
67 63 15 6 MIN_LINE_WIDTH=0.30 MM MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20 MM SM-LF MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.25 MM
1%
1/20W 1 C9404 PP3V3_B_S0 6 8 38 47 51 61 62 63
MF
201 0.1UF
10%
2 16V
X5R
1 C9460
402 0.1UF
10%
2 6.3V
X5R
53 52 51 46 44 42 30 29 CRITICAL 201
19 16 13 8 7 6 PP3V3_A_S0 U9404
28 27 26 25 24 23 22 21 8 SN74LVC2G125DCU
64 63 60
D9401 R9460 VCC
US
R9470
1SS418 CRT_HSYNC_R 1
39 2 6 CRT_HSYNC_LS_R 5 3 6 CRT_HSYNC_LS 1
39 2 VGA_HSYNC
1 1 SOD-723
67 63 15 6 A
125 Y 6 7 37
R9466 R9467 5%
1/20W GND
5%
1/20W NOSTUFF
2.2K
5%
2.2K
5%
2 1 PP5V_S0_DVIPORT_D 6 72 MF
201
7 MF
201 1 C9442
VOLTAGE=5V 4
1/20W 1/20W MIN_LINE_WIDTH=0.2 MM 33PF
MF MF MIN_NECK_WIDTH=0.2 MM 5%
2 201 2 201 2 25V
NP0-C0G
201
PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR THE CONNECTOR
15 TV_DCONSEL<0> R94621 1
R9463
C 1K
5%
1K
5%
CRITICAL
U9404
8 SN74LVC2G125DCU
C
15 6 TV_DCONSEL<1> 1/20W
MF
1/20W
MF R9461 VCC
US
R9471
2012 2 201 CRT_VSYNC_R 1
39 2 6 CRT_VSYNC_LS_R 2 6 6 CRT_VSYNC_LS 1
39 2 VGA_VSYNC
67 63 15 6
5%
A
125 Y
5%
6 7 37
1/20W GND 1/20W NOSTUFF

MF 1 MF
61 37 7 6 BI TMDS_HTPLG 201 4 201 1 C9443
63 62 61 51 47 38 8 6 PP3V3_B_S0 37 7 6 HDMI_HOST 33PF
5%
2 25V
1
R9480 1
R9481 1 C9410 NP0-C0G
201
10K 100K 1000PF
5% 5% 10%
16V
1/20W 1/20W 2 X7R
MF MF 201
2 201 2 201
37 7 6 DVI_HOST
67 62 61 37 7 6 BI TMDS_DDC_SDA
NOSTUFF
1 C9411 CRITICAL
100PF
5%
2 25V
L9405
90-OHM-100MA
CERM 1210-4SM1
201 TMDS_TX_P<2> 6 61 67
2 3
SB_CRT_TVOUT_MUX_L 67 62 61 37 7 6 BI TMDS_DDC_SCL
25 6
TMDS_TX_N<2> 6 61 67
NOSTUFF
1 4
PLACE U9401 NEAR NB
1 C9412 SYM_VER-1
PLACE R9450 R9451 CLOSE TO NB 100PF CRITICAL

5%
25V TMDS_TX_CONN_P<2>
67 63 15 6TV_A_DAC 53 52 51 46 44 42 30
22 21 19 16 13 8 7 6 PP3V3_A_S0
2 CERM
201
37 7 6 L9407
90-OHM-100MA
67 63 15 6CRT_BLUE 29 28 27 26 25 24 23
64 63 60 1210-4SM1
TMDS_TX_CONN_N<2> TMDS_TX_P<1> 6 61 67
37 7 6
2 3
C9439 TMDS_TX_CONN_P<1>
B 1
R9450
150
1
R9451
150
1
0.1UF
These nets connect TMDS_TX_N<1> 6 61 67
B
16
to RIO connector 1 4
1% 1% 10%
1/20W 1/20W 2 6.3V J4200 TMDS_TX_CONN_N<1> SYM_VER-1
VCC X5R 37 7 6
MF MF 201
2 201 2 201 U9401 VGA_B 6 7 37 67
TMDS_TX_CONN_P<0> CRITICAL
FSAV430 37 7 6
GND
VOLTAGE=0V
DQFN L9406
90-OHM-100MA
1 S OE* 15 TMDS_TX_CONN_N<0> 1210-4SM1
GND 37 7 6 TMDS_TX_P<0> 6 61 67
VOLTAGE=0V
2 1B1
CRITICAL 4B1 14 NC VGA_G 2 3
6 7 37 67
3 1B2 4B2 13 NC
FL9400
210MHZ
67 37 7 6
TMDS_TX_CONN_CLK_P
TMDS_TX_N<0> 6 61 67
1 MEA2010P-SM 8 1 4
4 1A 4A 12 NC 67 37 7 6
TMDS_TX_CONN_CLK_N SYM_VER-1
PLACE R9452 R9453 CLOSE TO NB
5 2B1 3B1 11
67 6 EXT_C_R 2 7 VGA_R 6 7 37 67
CRITICAL
67 63 15 6 TV_B_DAC
67 63 15 6 CRT_GREEN 6 2B2 3B2 10 67 6 EXT_Y_G 3 6 L9404
300-OHM-100MA
2 1210-4SM 3
TMDS_TX_CLK_P 6 61 67
7 2A 3A 9
EXT_COMPVID_B 4 5
1 1 GND THMPAD 1 4
TMDS_TX_CLK_N 6 61 67
R9452 R9453
150 150
8
17
SYM_VER-1
1%
1/20W
1%
1/20W
CRITICAL
MF MF
2 201 2 201
GND
VOLTAGE=0V
GND
VOLTAGE=0V
DVI CONNECTIONS
A PLACE R9454 R9455 CLOSE TO NB
A
67 63 15 6 TV_C_DAC
CRT_RED
Place components near J4200 NOTICE OF PROPRIETARY PROPERTY
67 63 15 6
1
R9454 1
R9455
unless otherwise noted THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
150 150
1% 1% II NOT TO REPRODUCE OR COPY IT
1/20W 1/20W
MF MF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
2 201 2 201
GND SIZE DRAWING NUMBER REV.
GND
VOLTAGE=0V
D 051-7230 B.0.0
VOLTAGE=0V
NONE 63 73
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
D D
LED Backlight Driver
CRITICAL
CRITICAL
L9750 D9750
72 59 56 50 45 37 8 7 6 PPBUS_G3H 22UH-2.5A SM PPVOUT_S0_LCDBKLT 6 7 60 72
1 2 PPVOUT_S0_LCDBKLT_SW 1 2 MIN_NECK_WIDTH=0.2 mm
IHLP2525CZ-SM
MIN_LINE_WIDTH=0.5 mm VOLTAGE=35V
63 60 53 MIN_NECK_WIDTH=0.2 mm
25 24 23 22 21 19 16 13 8 7 6 PP3V3_A_S0 SWITCH_NODE=TRUE PD3S140XF
52 51 46 44 42 30 29 28 27 26 1
C9755 1
C9756 1
C9757 1
C9758
PLT_RST_L input ensures backlight 4.7UF 4.7UF 4.7UF 4.7UF
10% 10% 10% 10%
50V 50V 50V 50V
ENA does not glitch during RESET. 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM 2 X7R-CERM
5 TC7SZ08AFEF 1206 1206 1206 1206
15 9 6 LCDBKLT_PWREN 2 SOT665
IN A
4
U9740Y
60 28 24 7 6 PLT_RST_L 1
IN B
1 C9751 1 C9750
4
3
C9740 1 1UF 10UF
10% 10%
0.1UF 25V
2 X5R 2
25V VIN
10% X5R
CRITICAL
6.3V 603 1206-1
X5R 2
201 U9750 R97551
OZ9956ALN f=500KHz 1M
1%
C 6 LCDBKLT_ENA
>2V = ON, <1V = OFF
1 ENA
QFN
SW 18
1/20W
MF
201 2 R9771
C
1
15 9 6 IN LCDBKLT_PWM_UNBUF 20 PWM ISEN1 10 6 LCDBKLT_RTN_RC<1> 1 2 LCDBKLT_RTN<1> 6 7 60
MIN_LINE_WIDTH=0.25 mm MIN_LINE_WIDTH=0.25 mm
100Hz - 20KHz MIN_NECK_WIDTH=0.2 mm 5%
1/20W
6 LCDBKLT_ISET 8 ISET ISEN2 11 6 LCDBKLT_RTN_RC<2> MF
MIN_LINE_WIDTH=0.25 mm 201
ILED[A] = 1500/R9766 MIN_NECK_WIDTH=0.2 mm
6 LCDBKLT_RT 5 RT ISEN3 12 6 LCDBKLT_RTN_RC<3> R9772
FOP[Mhz] = 50000/R9764 MIN_NECK_WIDTH=0.2 mm
1
1 2 LCDBKLT_RTN<2> 6 7 60
6 LCDBKLT_SSTCMP 9 SSTCMP ISEN4 14 6 LCDBKLT_RTN_RC<4> MIN_LINE_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.25 mm 5% MIN_NECK_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm 1/20W
MF
R97661 1
R9762 6 LCDBKLT_VREF 3 VREF ISEN5 15 6 LCDBKLT_RTN_RC<5> 201
75K 10K
C9763 1 MIN_LINE_WIDTH=0.25 mm
0.001UF MIN_NECK_WIDTH=0.2 mm
1%
1/20W
1%
1/20W 10%
50V NC 2 NC1 ISEN6 16 6 LCDBKLT_RTN_RC<6> R9773
MF MF CERM 2 MIN_LINE_WIDTH=0.25 mm 1
201 2 2 201 402 NC 7 NC2 MIN_NECK_WIDTH=0.2 mm 1 2 LCDBKLT_RTN<3> 6 7 60
NC 17 NC3 OVP 6 6 LCDBKLT_OVP 5% MIN_NECK_WIDTH=0.2 mm
6 LCDBKLT_SSTCMP_RC 1/20W
NC 19 NC4 OVP Threshold: 37.9V MF
1
THRML 201
R9764 C9762 1 1 C9760 GNDA PAD R97561
100K 78.7K R9774
13
21
1% 0.01UF 1UF 1%
1/20W 20% 10% 1/20W 1
16V 10V 1 2 LCDBKLT_RTN<4>
MF CERM 2 2 X5R MF 6 7 60
2 201 402 402-1 201 2 MIN_LINE_WIDTH=0.25 mm
1/20W
6 GND_LCDBKLT_GNDA XW9750 MF
201
MIN_LINE_WIDTH=0.5 mm SM
VOLTAGE=0V 1 2
R9775
1
1/20W
B MF
201 B
R9776
1
1/20W
MF
201
C9771 1 C9772 1 C9773 1 C9774 1 C9775 1 C9776 1

1000PF 1000PF 1000PF 1000PF 1000PF 1000PF
10% 10% 10% 10% 10% 10%
16V 16V 16V 16V 16V 16V
X7R 2 X7R 2 X7R 2 X7R 2 X7R 2 X7R 2
201 201 201 201 201 201
Place R9771-R9776,C9771-C9776 close to J9000
LED Backlight Driver

SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
A
D 051-7230 B.0.0

NONE 64 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ADDITIONAL CPU VCORE HF DECOUPLING ADDITIONAL GPU VCORE HF DECOUPLING

40x 1uF 0402
18x 1uF 0402
72 52 12 11 8 7 6 PPVCORE_S0_CPU 72 53 45 22 18 8 7 6 PPVCORE_S0_NB_GFX
OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT
D LAYOUT NOTE:
OMIT
CRITICAL
OMIT
CRITICAL
OMIT
CRITICAL
OMIT
CRITICAL
OMIT
CRITICAL
OMIT
CRITICAL
OMIT
CRITICAL
OMIT
CRITICAL
OMIT
CRITICAL
OMIT
CRITICAL
1 C9980
2.2UF
20%
1 C9981
2.2UF
20%
1 C9982
2.2UF
20%
1 C9983
2.2UF
20%
1 C9984
2.2UF
20%
1 C9985
2.2UF
20%
1 C9986
2.2UF
20%
1 C9987
2.2UF
20%
1 C9988
2.2UF
20%
1 C9989
2.2UF
20%
D
C9900 C9901 C9902 C9903 C9904 C9905 C9906 C9907 C9908 C9909 6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
6.3V
2 CERM
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
CERM CERM CERM CERM CERM CERM CERM CERM CERM CERM
OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT

1 C9990 1 C9991 1 C9992 1 C9993 1 C9994 1 C9995 1 C9996 1 C9997
20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT OMIT 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF
LAYOUT NOTE:
C9910 C9911 C9912 C9913 C9914 C9915 C9916 C9917 C9918 C9919
PLACE ON OPPOSITE SIDE OF CPU 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
C C
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
B B
Additional CPU/GPU Decoupling

A SYNC_MASTER=

SYNC_DATE=
A
D 051-7230 B.0.0

NONE 65 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FSB (Front-Side Bus) Constraints CPU / FSB Net Properties
TABLE_PHYSICAL_RULE_HEAD
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP NET_TYPE
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

FSB_55S ISL3,ISL10 Y =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD
FSB_COMMON FSB_55S FSB_COMMON FSB_ADS_L 10 14

FSB_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
FSB_COMMON FSB_55S FSB_COMMON FSB_BNR_L 10 14
FSB_DSTB_55S * =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR FSB_COMMON FSB_55S FSB_COMMON FSB_BPRI_L 10 14
FSB_COMMON FSB_55S FSB_COMMON FSB_BREQ0_L 10 14
FSB_COMMON FSB_55S FSB_COMMON FSB_DBSY_L 10 14
FSB_COMMON FSB_55S FSB_COMMON FSB_DEFER_L 10 14
FSB_COMMON FSB_55S FSB_COMMON FSB_DPWR_L 10 14

TABLE_SPACING_RULE_HEAD
FSB_COMMON FSB_55S FSB_COMMON FSB_DRDY_L 10 14
D SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_SPACING_RULE_ITEM
FSB_COMMON FSB_55S FSB_COMMON FSB_HIT_L 10 14 D
FSB_4MIL * 0.100 MM ? FSB_COMMON FSB_55S FSB_COMMON FSB_HITM_L 10 14
FSB_COMMON FSB_55S FSB_COMMON FSB_LOCK_L 10 14

FSB_9MIL * 0.228 MM ?
FSB_COMMON FSB_55S FSB_COMMON FSB_RS_L<2..0> 10 14
FSB_DATA * =FSB_4MIL ? FSB_COMMON FSB_55S FSB_COMMON FSB_TRDY_L 10 14

FSB_CPURST_L FSB_55S FSB_COMMON FSB_CPURST_L 6 10 13 14

FSB_DATA2DATA * =FSB_4MIL ?
FSB_DATA_GROUP0 FSB_55S FSB_DATA FSB_D_L<15..0> 10 14

FSB_DSTB * =FSB_9MIL ?
FSB_DATA_GROUP0 FSB_55S FSB_DATA FSB_DINV_L<0> 10 14
FSB_DATA2DSTB * =FSB_9MIL ? FSB_DSTB0 FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_P<0> 10 14

FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_N<0> 10 14

FSB_ADDR * =FSB_4MIL ?

FSB_ADDR2ADDR * =FSB_4MIL ? FSB_DINV_L<1>
FSB_DATA_GROUP1 FSB_55S FSB_DATA 10 14
FSB_ADSTB * =FSB_9MIL ? FSB_DSTB1 FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_P<1> 10 14

FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_N<1> 10 14

FSB_ADDR2ADSTB * =FSB_9MIL ?

FSB_COMMON * =FSB_4MIL ?
TABLE_SPACING_ASSIGNMENT_HEAD
FSB_DSTB2 FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_P<2> 10 14
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_N<2> 10 14

TABLE_SPACING_ASSIGNMENT_ITEM
FSB_ADDR FSB_ADDR * FSB_ADDR2ADDR FSB_DATA_GROUP3 FSB_55S FSB_DATA FSB_D_L<63..48> 10 14


FSB_ADDR FSB_ADSTB * FSB_ADDR2ADSTB
FSB_DSTB3 FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_P<3> 10 14
FSB_DATA FSB_DATA * FSB_DATA2DATA FSB_DSTB_55S FSB_DSTB FSB_DSTB_L_N<3> 10 14

FSB_DATA FSB_DSTB * FSB_DATA2DSTB FSB_ADDR_GROUP0 FSB_55S FSB_ADDR FSB_A_L<16..3> 10 14
FSB_ADDR_GROUP0 FSB_55S FSB_ADDR FSB_REQ_L<4..0> 10 14
C All FSB signals with impedance requirements are 55-ohm single-ended.

Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs.
FSB_ADSTB0 FSB_55S FSB_ADSTB FSB_ADSTB_L<0> 10 14 C
Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs. FSB_ADDR_GROUP1 FSB_55S FSB_ADDR FSB_A_L<35..17> 10 14
DSTB complementary pairs are spaced 1:1 and routed as differential pairs. FSB_ADSTB1 FSB_55S FSB_ADSTB FSB_ADSTB_L<1> 10 14
Design Guide recommends each strobe/signal group is routed on the same layer. CPU_IERR_L CPU_55S CPU_IERR_L 6 10
Design Guide recommends FSB signals be routed only on internal layers. CPU_FERR_L CPU_55S CPU_FERR_L 6 10 23
CPU_PROCHOT_L CPU_55S CPU_2TO1 CPU_PROCHOT_L 6 10 42 52

NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1.
CPU_PWRGD CPU_55S CPU_PWRGD 6 10 13 23
NOTE: Design Guide allows closer spacing if signal lengths can be shortened.
CPU_FROM_SB CPU_55S CPU_INTR 6 10 23
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.2 & 4.3 CPU_FROM_SB CPU_55S CPU_NMI 6 10 23
CPU_FROM_SB CPU_55S CPU_A20M_L 6 10 23
CPU_FROM_SB CPU_55S CPU_DPSLP_L 6 10 23
CPU_FROM_SB CPU_55S CPU_IGNNE_L 6 10 23
CPU_INIT_L CPU_55S CPU_INIT_L 6 10 23
CPU_FROM_SB CPU_55S CPU_SMI_L 6 10 23
CPU_FROM_SB CPU_55S CPU_STPCLK_L 6 10 23
PM_THRMTRIP_L CPU_55S CPU_2TO1 PM_THRMTRIP_L 6 10 16 23 42
FSB_CPUSLP_L CPU_55S FSB_CPUSLP_L 10 14
PM_DPRSLPVR CPU_55S CPU_2TO1 PM_DPRSLPVR 6 16 25 52
(See above) CPU_55S CPU_2TO1 IMVP_DPRSLPVR 6 52
CPU_BSEL0 CPU_55S CPU_2TO1 CPU_BSEL<0> 6 10 30
(See above) CPU_55S CPU_2TO1 NB_BSEL<0> 6 7 13 16 30
CPU Signal Constraints CPU_BSEL1 CPU_55S CPU_2TO1 CPU_BSEL<1> 6 10 30
ALLOW ROUTE
(See above) CPU_55S CPU_2TO1 NB_BSEL<1> 6 7 13 16 30

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
CPU_BSEL2 CPU_55S CPU_2TO1 CPU_BSEL<2> 6 10 30
CPU_27P4S * Y =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE 7 MIL 7 MIL (See above) CPU_55S CPU_2TO1 NB_BSEL<2> 6 7 13 16 30
B CPU_55S * Y =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

CPU_DPRSTP_L CPU_55S CPU_2TO1 CPU_DPRSTP_L 6 10 16 23 52

B
CPU_GTLREF CPU_55S CPU_GTLREF CPU_GTLREF 6 10

CPU_70D * Y =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF
CPU_COMP CPU_55S CPU_COMP CPU_COMP<3> 6 10
NOTE: 7 mil gap is for VCCSense pair, which CPU_COMP CPU_27P4S CPU_COMP CPU_COMP<2> 6 10
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT Intel says to route with 7 mil spacing without CPU_COMP CPU_55S CPU_COMP CPU_COMP<1> 6 10
specifying a target differential impedance. CPU_COMP CPU_27P4S CPU_COMP CPU_COMP<0> 6 10

CPU_2TO1 * =2:1_SPACING ?
XDP_TDI CPU_55S CPU_ITP XDP_TDI 6 7 10 13

CPU_COMP * 25 MIL ?
XDP_TDO CPU_55S CPU_ITP XDP_TDO 6 7 10 13
CPU_GTLREF * 25 MIL ? XDP_TMS CPU_55S CPU_ITP XDP_TMS 6 7 10 13

DG recommends at least 25 mils, >50 mils preferred
XDP_TCK CPU_55S CPU_ITP XDP_TCK 6 7 10 13

CPU_ITP * =2:1_SPACING ?
XDP_TRST_L CPU_55S CPU_ITP XDP_TRST_L 6 7 10 13
CPU_VCCSENSE * 25 MIL ? XDP_BPM_L CPU_55S CPU_ITP XDP_BPM_L<4..0> 6 7 10 13

XDP_BPM_L5 CPU_55S CPU_ITP XDP_BPM_L<5> 6 7 10 13

CPU_THERMD * 25 MIL ? XDP_CLK_P
CLK_FSB_100D CLK_FSB 6 7 13 29 30 71
CLK_FSB_100D CLK_FSB XDP_CLK_N 6 7 13 29 30 71
Most CPU signals with impedance requirements are 55-ohm single-ended. (FSB_CPURST_L) CPU_55S CPU_ITP XDP_CPURST_L 6 7 13
Some signals require 27.4-ohm single-ended impedance.

CPU_55S CPU_2TO1 CPU_VID<6..0> 6 11 12 52
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 CPU_55S CPU_2TO1 IMVP6_VID<6..0> 12
CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_P 6 11 52
CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_N 6 11 52
CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_P 6 52
CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_N 6 52
CPU_70D CPU_THERMD CPU_THERMD_P

CPU_70D CPU_THERMD CPU_THERMD_N
6 10 46
6 10 46
CPU/FSB Constraints
A SYNC_MASTER=T9

A
D 051-7230 B.0.0

NONE 66 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI-Express / DMI Bus Constraints
NET_TYPE
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

PEG_R2D PCIE_100D PCIE_R2D PEG_R2D_P<15..0>
DMI_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PCIE_100D PCIE_R2D PEG_R2D_N<15..0>
PCIE_100D PCIE_R2D PEG_R2D_C_P<15..0> 6 15 61
TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
PCIE_100D PCIE_R2D PEG_R2D_C_N<15..0> 6 15 61

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
PEG_D2R PCIE_100D PCIE_D2R PEG_D2R_P<15..0> 6 15 61
PCIE * 20 MIL ? DMI_N2S_2_DMI_N2S * 0.228 MM ? PCIE_100D PCIE_D2R PEG_D2R_N<15..0> 6 15 61

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
PCIE_100D PCIE_D2R PEG_D2R_C_P<15..0>

PCIE_R2D_2_PCIE_R2D * 0.228 MM ? DMI_S2N_2_DMI_S2N * 0.228 MM ? PEG_D2R_C_N<15..0>
PCIE_100D PCIE_D2R
D PCIE_D2R_2_PCIE_D2R * 0.228 MM ?
DMI_N2S_2_DMI_S2N * 0.300 MM ?
DMI_N2S DMI_100D DMI_N2S DMI_N2S_P<3..0> 6 16 24

D
PCIE_R2D_2_PCIE_D2R * 0.300 MM ? DMI_100D DMI_N2S DMI_N2S_N<3..0> 6 16 24
TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
DMI_S2N DMI_100D DMI_S2N DMI_S2N_P<3..0> 6 16 24
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET DMI_100D DMI_S2N DMI_S2N_N<3..0> 6 16 24
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_R2D PCIE_R2D * PCIE_R2D_2_PCIE_R2D DMI_N2S DMI_N2S * DMI_N2S_2_DMI_N2S LVDS_A_CLK LVDS_100D LVDS LVDS_A_CLK_P 6 15 60
LVDS_A_CLK LVDS_100D LVDS LVDS_A_CLK_N 6 15 60

PCIE_D2R PCIE_D2R * PCIE_D2R_2_PCIE_D2R DMI_S2N DMI_S2N * DMI_S2N_2_DMI_S2N
LVDS_A_DATA LVDS_100D LVDS LVDS_A_DATA_P<2..0> 6 7 15 60
PCIE_R2D PCIE_D2R * PCIE_R2D_2_PCIE_D2R DMI_N2S DMI_S2N * DMI_N2S_2_DMI_S2N LVDS_A_DATA LVDS_100D LVDS LVDS_A_DATA_N<2..0> 6 7 15 60
LVDS_A_DATA LVDS_100D LVDS LVDS_A_DATA_F_P<2..0> 6 60
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET LVDS_A_DATA LVDS_100D LVDS LVDS_A_DATA_F_N<2..0> 6 60
LVDS_A_DATA3 LVDS_100D LVDS NC_LVDS_A_DATA_P3 9

PCIE_R2D PWR * BUS2PWR_GND
LVDS_A_DATA3 LVDS_100D LVDS NC_LVDS_A_DATA_N3 9
PCIE_R2D GND * BUS2PWR_GND LVDS_B_CLK LVDS_100D LVDS NC_LVDS_B_CLK_P 9 15

LVDS_B_CLK LVDS_100D LVDS NC_LVDS_B_CLK_N 9 15

PCIE_D2R PWR * BUS2PWR_GND
LVDS_B_DATA LVDS_100D LVDS LVDS_B_DATA_P<2..0>
PCIE_D2R GND * BUS2PWR_GND LVDS_B_DATA LVDS_100D LVDS LVDS_B_DATA_N<2..0>

LVDS_B_DATA3 LVDS_100D LVDS NC_LVDS_B_DATA_P3 9

DMI_N2S PWR * BUS2PWR_GND
LVDS_B_DATA3 LVDS_100D LVDS NC_LVDS_B_DATA_N3 9
DMI_N2S GND * BUS2PWR_GND LVDS_IBG LVDS LVDS_IBG 6 15 60

DMI_S2N PWR * BUS2PWR_GND CRT_TVO_IREF CRT CRT_TVO_IREF 6 15 63

CRT_RED CRT_50S CRT CRT_RED 6 15 63

DMI_S2N GND * BUS2PWR_GND
CRT_GREEN CRT_50S CRT CRT_GREEN 6 15 63
LVDS PWR * BUS2PWR_GND CRT_BLUE CRT_50S CRT CRT_BLUE 6 15 63

CRT_SYNC CRT_55S CRT_SYNC CRT_HSYNC_R 6 15 63

LVDS GND * BUS2PWR_GND
CRT_SYNC CRT_55S CRT_SYNC CRT_VSYNC_R 6 15 63
C TMDS PWR * BUS2PWR_GND

TV_A_DAC
TV_B_DAC
CRT_50S
CRT_50S
TVDAC
TVDAC
TV_A_DAC
TV_B_DAC
6 15 63
6 15 63
C
TMDS GND * BUS2PWR_GND
TV_C_DAC CRT_50S TVDAC TV_C_DAC 6 15 63
EXT_COMPVID_B CRT_50S CRT EXT_COMPVID_B 6 63
EXT_Y_G CRT_50S CRT EXT_Y_G 6 63
EXT_C_R CRT_50S CRT EXT_C_R 6 63
VGA_R CRT_50S CRT VGA_R 6 7 37 63
VGA_G CRT_50S CRT VGA_G 6 7 37 63
VGA_B CRT_50S CRT VGA_B 6 7 37 63
PCIE_100D PCIE_R2D TMDS_SDB_P 6 61
PCIE_100D PCIE_R2D TMDS_SDB_N 6 61
PCIE_100D PCIE_R2D TMDS_SDC_P 6 61
PCIE_100D PCIE_R2D TMDS_SDC_N 6 61
Video Signal Constraints PCIE_100D PCIE_R2D TMDS_SDG_P 6 61

PCIE_100D PCIE_R2D TMDS_SDG_N 6 61

ON LAYER? PCIE_100D PCIE_R2D TMDS_SDR_P 6 61
LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PCIE_100D PCIE_R2D TMDS_SDR_N 6 61
TMDS_100D TMDS TMDS_TX_CLK_P 6 61 63

CRT_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD
TMDS_100D TMDS TMDS_TX_CLK_N 6 61 63
CRT_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCIE_100D PCIE_D2R TMDS_INT_P 6 61
PCIE_100D PCIE_D2R TMDS_INT_N 6 61

TMDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
TMDS_100D TMDS TMDS_TX_CONN_CLK_P 6 7 37 63
TMDS_100D TMDS TMDS_TX_CONN_CLK_N 6 7 37 63

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TMDS_100D TMDS TMDS_CONN_P<3..0>
LVDS * 20 MIL ? TMDS_100D TMDS TMDS_CONN_N<3..0>
TMDS_100D TMDS TMDS_TX_P<3..0> 6 61 63

CRT * 25 MIL ? DG Says 40 mil spacing minimum
B CRT_2CRT * 20 MIL ?
TMDS_100D
SMB_55S
TMDS
SMB
TMDS_TX_N<3..0>
TMDS_DDC_SCL
6 61 63
6 7 37 61 62 63
B
SMB_55S SMB TMDS_DDC_SDA 6 7 37 61 62 63

CRT_SYNC * 25 MIL ? DG Says 30 mil spacing minimum
CRT_SYNC2SYNC * 20 MIL ?
TVDAC * 25 MIL ? DG Says 40 mil spacing minimum

TVDAC_2TVDAC * 20 MIL ?
LVDS2LVDS * 0.300 MM ?
TMDS * 20 MIL ?
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

CRT CRT * CRT_2CRT

CRT_SYNC CRT_SYNC * CRT_SYNC2SYNC

TVDAC TVDAC * TVDAC_2TVDAC

LVDS LVDS * LVDS2LVDS
LVDS signals are 100-ohm +/- 20% differential impedence.

CRT & TVDAC signal single-ended impedence varies by location:
- 37.5-ohm +/- 15% from GMCH to first termination resistor.
- 50-ohm +/- 15% from first to second termination resistor.
- 55-ohm +/- 15% from second termination resistor to connector. NB Constraints
CRT_HSYNC/CRT_VSYNC signals are 55-ohm +/- 15% single-ended impedence.
A SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 8.1 - 8.3.
SYNC_MASTER=T9

A
D 051-7230 B.0.0

NONE 67 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DDR2 Memory Bus Constraints Memory Net Properties
NET_TYPE
MEM_45S * =45_OHM_SE =45_OHM_SE =45_OHM_SE =45_OHM_SE =STANDARD =STANDARD

MEM_87D MEM_CLK MEM_CLK_P<2..0> 16 31 33
MEM_55S ISL3,ISL10 =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD MEM_87D MEM_CLK MEM_CLK_N<2..0> 16 31 33
MEM_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MEM_45S MEM_CTRL MEM_CKE<1..0> 16 31 33
MEM_45S MEM_CTRL MEM_CS_L<1..0> 16 31 33

MEM_87D * =87_OHM_DIFF =87_OHM_DIFF =87_OHM_DIFF =87_OHM_DIFF =87_OHM_DIFF =87_OHM_DIFF
MEM_45S MEM_CTRL MEM_ODT<1..0> 6 16 31 33
MEM_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

MEM_A_CMD MEM_55S MEM_CMD MEM_A_A<13..0> 17 31 33
TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
MEM_A_CMD MEM_55S MEM_CMD MEM_A_BS<2..0> 17 31 33
D SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

MEM_A_CMD MEM_55S MEM_CMD MEM_A_RAS_L 17 31 33 D
MEM_CLK2MEM * =2.28:1_SPACING ? MEM_CLK GND * GND_P2MM MEM_A_CMD MEM_55S MEM_CMD MEM_A_CAS_L 17 31 33
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_A_CMD MEM_55S MEM_CMD MEM_A_WE_L 17 31 33

MEM_CTRL2CTRL * =1:1_SPACING ? MEM_CMD GND * GND_P2MM
MEM_A_DQ_BYTE0 MEM_55S MEM_DATA MEM_A_DQ<7..0> 17 31

MEM_CTRL2MEM * =2.28:1_SPACING ? MEM_CTRL GND * GND_P2MM
MEM_CMD2CMD * =1:1_SPACING ? MEM_DATA GND * GND_P2MM MEM_A_DQ_BYTE2 MEM_55S MEM_DATA MEM_A_DQ<23..16> 17 31


MEM_CMD2MEM * =2.28:1_SPACING ? MEM_DQS GND * GND_P2MM
MEM_DATA2DATA * =1:1_SPACING ? MEM_CLK PP1V8_MEM * PWR_P2MM MEM_A_DQ_BYTE5 MEM_55S MEM_DATA MEM_A_DQ<47..40> 17 31


MEM_DATA2MEM * =2.28:1_SPACING ? MEM_CTRL PP1V8_MEM * PWR_P2MM
MEM_DQS2MEM * =2.28:1_SPACING ? MEM_DATA PP1V8_MEM * PWR_P2MM

MEM_A_DM0 MEM_55S MEM_DATA MEM_A_DM<0> 17 31
MEM_2OTHER * 25 MIL ? MEM_DQS PP1V8_MEM * PWR_P2MM MEM_A_DM1 MEM_55S MEM_DATA MEM_A_DM<1> 17 31


MEM_CMD PP1V8_MEM * PWR_P2MM

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_A_DM3 MEM_55S MEM_DATA MEM_A_DM<3> 17 31

MEM_CLK * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_A_DM5 MEM_55S MEM_DATA MEM_A_DM<5> 17 31
MEM_CTRL * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK NB_STATIC * PWR_P2MM

MEM_CMD * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CTRL NB_STATIC * PWR_P2MM

MEM_A_DQS0 MEM_85D MEM_DQS MEM_A_DQS_P<0> 17 31

MEM_DATA * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA NB_STATIC * PWR_P2MM MEM_85D MEM_DQS MEM_A_DQS_N<0> 17 31

MEM_DQS * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS NB_STATIC * PWR_P2MM
TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM
MEM_85D MEM_DQS MEM_A_DQS_N<1> 17 31
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CMD NB_STATIC * PWR_P2MM MEM_A_DQS2 MEM_85D MEM_DQS MEM_A_DQS_P<2> 17 31
C MEM_CLK
MEM_CLK
MEM_CLK
MEM_CTRL
*
*
MEM_CLK2MEM
MEM_CLK2MEM
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE
SPACING_RULE_SET
MEM_A_DQS3 MEM_85D
MEM_85D
MEM_DQS
MEM_DQS
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
17 31
17 31
C
MEM_DQS MEM_CLK * MEM_DQS2MEM

MEM_CLK MEM_CMD * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS MEM_CTRL * MEM_DQS2MEM MEM_85D MEM_DQS MEM_A_DQS_N<4> 17 31
MEM_CLK MEM_DATA * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS MEM_CMD * MEM_DQS2MEM

MEM_CLK MEM_DQS * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DQS MEM_DATA * MEM_DQS2MEM MEM_A_DQS6 MEM_85D MEM_DQS MEM_A_DQS_P<6> 17 31


MEM_DQS MEM_DQS * MEM_DQS2MEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_A_DQS7 MEM_85D MEM_DQS MEM_A_DQS_P<7> 17 31
Need to support MEM_*-style wildcards! MEM_85D MEM_DQS MEM_A_DQS_N<7> 17 31

MEM_CMD MEM_CLK * MEM_CMD2MEM
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD
MEM_87D MEM_CLK MEM_CLK_P<5..3> 16 32 33

MEM_CMD MEM_CTRL * MEM_CMD2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
MEM_87D MEM_CLK MEM_CLK_N<5..3> 16 32 33
MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_CLK PWR * BUS2PWR_GND

MEM_45S MEM_CTRL MEM_CKE<4..3> 16 32 33
MEM_CMD MEM_DATA * MEM_CMD2MEM MEM_CLK GND * BUS2PWR_GND MEM_45S MEM_CTRL MEM_CS_L<3..2> 16 32 33

MEM_45S MEM_CTRL MEM_ODT<3..2> 6 16 32 33

MEM_CMD MEM_DQS * MEM_CMD2MEM MEM_CTRL PWR * BUS2PWR_GND
MEM_B_CMD MEM_55S MEM_CMD MEM_B_A<13..0> 17 32 33

MEM_CTRL GND * BUS2PWR_GND
MEM_B_CMD MEM_55S MEM_CMD MEM_B_BS<2..0> 17 32 33

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM
MEM_CMD PWR * BUS2PWR_GND MEM_B_CMD MEM_55S MEM_CMD MEM_B_RAS_L 17 32 33

MEM_CTRL MEM_CLK * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_B_CMD MEM_55S MEM_CMD MEM_B_CAS_L 17 32 33

MEM_CMD GND * BUS2PWR_GND
MEM_B_CMD MEM_55S MEM_CMD MEM_B_WE_L 17 32 33

MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA PWR * BUS2PWR_GND

MEM_B_DQ_BYTE0 MEM_55S MEM_DATA MEM_B_DQ<7..0> 17 32

MEM_CTRL MEM_CMD * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM
MEM_DATA GND * BUS2PWR_GND MEM_B_DQ_BYTE1 MEM_55S MEM_DATA MEM_B_DQ<15..8> 17 32
MEM_CTRL MEM_DATA * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_DQS PWR * BUS2PWR_GND

MEM_CTRL MEM_DQS * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM
B TABLE_SPACING_ASSIGNMENT_HEAD
MEM_DQS GND * BUS2PWR_GND MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_55S
MEM_55S
MEM_DATA
MEM_DATA
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
17 32
17 32
B
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_B_DQ_BYTE6 MEM_55S MEM_DATA MEM_B_DQ<55..48> 17 32

MEM_DATA MEM_CLK * MEM_DATA2MEM
MEM_B_DM0 MEM_55S MEM_DATA MEM_B_DM<0> 17 32

MEM_DATA MEM_CTRL * MEM_DATA2MEM
MEM_DATA MEM_CMD * MEM_DATA2MEM MEM_B_DM2 MEM_55S MEM_DATA MEM_B_DM<2> 17 32


MEM_DATA MEM_DATA * MEM_DATA2DATA
MEM_DATA MEM_DQS * MEM_DATA2MEM MEM_B_DM5 MEM_55S MEM_DATA MEM_B_DM<5> 17 32
MEM_B_DQS0 MEM_85D MEM_DQS MEM_B_DQS_P<0> 17 32
MEM_85D MEM_DQS MEM_B_DQS_N<0> 17 32

I93 PP0V9_S3M_MEM_NBVREFB NET_SPACING_TYPE=NB_STATIC 8 16 21
I95
PP0V9_S3M_MEM_NBVREFA NET_SPACING_TYPE=NB_STATIC 8 16 21 MEM_85D MEM_DQS MEM_B_DQS_N<5> 17 32 Memory Constraints
NB_VCCSM_LF1 NET_SPACING_TYPE=NB_STATIC
A I94
NB_VCCSM_LF2 NET_SPACING_TYPE=NB_STATIC
6 18
6 18 MEM_B_DQS7
MEM_85D
MEM_85D
MEM_DQS
MEM_DQS
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
17 32
17 32
SYNC_MASTER=T9

A
I96
I97
NB_VCCSM_LF3 NET_SPACING_TYPE=NB_STATIC 6 18 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
I98 NB_VCCSM_LF4 NET_SPACING_TYPE=NB_STATIC 6 18
I99
NB_VCCSM_LF5 NET_SPACING_TYPE=NB_STATIC 6 18 II NOT TO REPRODUCE OR COPY IT
I101
NB_VCCSM_LF6 NET_SPACING_TYPE=NB_STATIC 6 18

I103 NB_VCCSM_LF7 NET_SPACING_TYPE=NB_STATIC 6 18
I102
PP1V8_S3 NET_SPACING_TYPE=PP1V8_MEM 6 7 8 16 18 21 31 32 34 35 51
D 051-7230 B.0.0
55 72
GND NET_SPACING_TYPE=GND 68 73
NONE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
Disk Interface Constraints ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
ON LAYER? IDE_PDD IDE_55S IDE IDE_PDD<15..0> 6 23 38
IDE_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD IDE_PDA IDE_55S IDE IDE_PDA<2..0> 6 23 38
IDE_PDCS IDE_55S IDE IDE_PDCS1_L 6 23 38

SATA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
IDE_PDCS IDE_55S IDE IDE_PDCS3_L 6 23 38
SATA_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF IDE_CNTL IDE_55S IDE IDE_PDIOW_L 6 23 38
IDE_PDIOR_L IDE_55S IDE IDE_PDIOR_L 6 23 38

IDE_CNTL IDE_55S IDE IDE_PDDACK_L 6 23 38

IDE_CNTL IDE_55S IDE IDE_PDDREQ 6 23 38
IDE * =1.8:1_SPACING ? IDE_PDIORDY IDE_55S IDE IDE_PDIORDY 6 23 38
D SATA * 20 MIL ?
IDE_IRQ14
IDE_RST_L
IDE_55S
IDE_55S
IDE
IDE
IDE_IRQ14
ODD_RST_5VTOL_L
6 23 38
D
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.7 & 10.9 SATA_A_R2D SATA_100D SATA NC_SATA_A_R2D_C_P 9 23
SATA_100D SATA NC_SATA_A_R2D_C_N 9 23
HD Audio Interface Constraints SATA_100D SATA SATA_A_R2D_P

SATA_100D SATA SATA_A_R2D_N

ON LAYER? SATA_A_D2R SATA_100D GND NC_SATA_A_D2R_P 9
HDA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD SATA_100D GND NC_SATA_A_D2R_N 9
SATA_100D SATA SATA_A_D2R_C_P

SATA_100D SATA SATA_A_D2R_C_N

SATA_B_R2D SATA_100D SATA NC_SATA_B_R2D_C_P 9 23
HDA * =1.8:1_SPACING ? SATA_100D SATA NC_SATA_B_R2D_C_N 9 23
SATA_100D SATA SATA_B_R2D_P

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1 SATA_100D SATA SATA_B_R2D_N
SATA_A_D2R SATA_100D GND NC_SATA_B_D2R_P 9
SATA_100D GND NC_SATA_B_D2R_N

USB 2.0 Interface Constraints SATA_100D SATA SATA_B_D2R_C_P
9
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SATA_100D SATA SATA_B_D2R_C_N
ON LAYER?
SATA_C_R2D SATA_100D SATA NC_SATA_C_R2D_C_P 9 23

USB_60S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
SATA_100D SATA NC_SATA_C_R2D_C_N 9 23
USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SATA_100D SATA SATA_C_R2D_P
SATA_100D SATA SATA_C_R2D_N
SATA_A_D2R SATA_100D GND NC_SATA_C_D2R_P 9

SATA_100D GND NC_SATA_C_D2R_N 9
USB * 20 MIL ? SATA_100D SATA SATA_C_D2R_C_P

SATA_100D SATA SATA_C_D2R_C_N

USB_2CLK * 25 MIL ?
C TABLE_SPACING_ASSIGNMENT_HEAD
SATA_RBIAS
HDA_BIT_CLK
SATA_55S
HDA_55S HDA
SATA_RBIAS
HDA_BIT_CLK 6 7 9 23 37
C
HDA_55S HDA HDA_BIT_CLK_R 6 23
USB PWR * BUS2PWR_GND HDA_SYNC HDA_55S HDA HDA_SYNC 6 7 9 23 37

HDA_55S HDA HDA_SYNC_R 6 23

USB GND * BUS2PWR_GND
HDA_RST_L HDA_55S HDA HDA_RST_L 6 9 23 37
HDA_55S HDA HDA_RST_L_R 6 23
HDA_SDIN0 HDA_55S HDA HDA_SDIN0 6 7 9 23 37
HDA_55S HDA HDA_SDIN_CODEC

HDA_SDOUT HDA_55S HDA HDA_SDOUT 6 7 9 23 37
HDA_55S HDA HDA_SDOUT_R 6 23
USB_EXTA USB_90D USB USB2_EXTA_P

Internal Interface Constraints USB_90D USB USB2_EXTA_N
6 9 24 39
6 9 24 39
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP USB_90D USB USB2_MUXED_EXTA_N 6 9 39
ON LAYER?
USB_90D USB USB2_MUXED_EXTA_P 6 9 39

SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
USB_MINI USB_90D USB USB2_AIRPORT_P 6 9 24 36
SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_90D USB USB2_AIRPORT_N 6 9 24 36
USB_EXTD USB_90D USB TP_USB2_3G_P 9 24

USB_90D USB TP_USB2_3G_N 9 24

USB_CAMERA USB_90D USB USB2_CAMERA_P 6 9 24 60
SMB * =3:1_SPACING ? USB_90D USB USB2_CAMERA_N 6 9 24 60

USB_BT USB_90D USB NC_USB_BT_P 9 24

SPI * =1.8:1_SPACING ?
USB_90D USB NC_USB_BT_N 9 24
USB_TPAD USB_90D USB USB2_WSPRING_P 6 7 9 24 40

SOURCE: Santa Platform DG, Rev 1.0 (#21112), Section 10.17
USB_90D USB USB2_WSPRING_N 6 7 9 24 40
USB_IR USB_90D USB USB_IR_P 6 7 9 24 40
B USB_90D USB USB_IR_N 6 7 9 24 40 B

USB_EXTB USB_90D USB NC_USB2_EXTB_P 9 24
USB_90D USB NC_USB2_EXTB_N 9 24
USB_EXCARD USB_90D USB TP_USB_EXCARD_P 9 24
USB_90D USB TP_USB_EXCARD_N 9 24
USB_EXTC USB_90D USB TP_USB_EXTC_P 9 24
USB_90D USB TP_USB_EXTC_N 9 24
USB_90D USB USB2_AIRPORT_P_F 6 36
USB_90D USB USB2_AIRPORT_N_F 6 36
USB_90D USB USB2_CAMERA_F_P 6 7 60
USB_90D USB USB2_CAMERA_F_N 6 7 60
USB_90D USB USB2_EXTA_F_P 6 7 37 39
USB_90D USB USB2_EXTA_F_N 6 7 37 39
USB2_3G_F_P
USB2_3G_F_N
USB_RBIAS USB_60S USB_RBIAS 6 24
SMB_SB_SCL SMB_55S SMB SMBUS_SB_SCL 6 25 29 44
SMB_SB_SDA SMB_55S SMB SMBUS_SB_SDA 6 25 29 44
SMB_SB_ME_SCL SMB_55S SMB SMBUS_SB_ME_SCL 6 25 44
SMB_SB_ME_SDA SMB_55S SMB SMBUS_SB_ME_SDA 6 25 44
SPI_SCLK SPI_55S SPI SPI_SCLK_R 6 24 49
SPI_55S SPI SPI_SCLK

SPI_55S SPI SPI_A_SCLK_R 6 43 49
SPI_55S SPI SPI_B_SCLK_R SB Constraints (1 of 2)

SPI_SI SPI_55S SPI SPI_SI_R 6 24 49
A SPI_55S
SPI_55S
SPI
SPI
SPI_SI
SPI_A_SI_R 6 43 49
SYNC_MASTER=T9

A
SPI_55S SPI SPI_B_SI_R
SPI_SO SPI_55S SPI SPI_SO 6 24 43 49 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
SPI_55S SPI SPI_A_SO_R 6 49
SPI_55S SPI SPI_B_SO
SPI_55S SPI SPI_B_SO_R
SPI_CE_L0 SPI_55S SPI SPI_CE_R_L<0> 6 24 49
SPI_55S SPI SPI_CE_L<0> 6 43 49 SIZE DRAWING NUMBER REV.

SPI_CE_R_L<1>
SPI_CE_L1 SPI_55S
SPI_55S
SPI
SPI SPI_CE_L<1>
6 24 43
D 051-7230 B.0.0

NONE 69 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI Bus Constraints
NET_TYPE
PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD

PCI_AD PCI_55S PCI PCI_AD<18..0> 9
PCI_AD19 PCI_55S PCI NC_PCI_AD<19> 9 24
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PCI_AD20 PCI_55S PCI NC_PCI_AD<20> 9 24

PCI_AD PCI_55S PCI PCI_AD<31..21> 9

PCI * =2:1_SPACING ?
PCI_AD PCI_55S PCI NC_PCI_PAR 9 24
PCIE_R2D * =PCIE ? PCI_C_BE_L PCI_55S PCI PCI_C_BE_L<3..0> 9

PCI_CNTL PCI_55S PCI PCI_IRDY_L 6 24

PCIE_D2R * =PCIE ? PCI_DEVSEL_L
PCI_CNTL PCI_55S PCI 6 24
D PCIE_9MIL * 0.228 MM ?
PCI_CNTL PCI_55S PCI PCI_PERR_L 6 24 D

PCI_LOCK_L PCI_55S PCI PCI_LOCK_L 6 24

PCIE_12MIL * 0.300 MM ? PCI_SERR_L
PCI_CNTL PCI_55S PCI 6 24
PCI_CNTL PCI_55S PCI PCI_STOP_L 6 24
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET PCI_CNTL PCI_55S PCI PCI_TRDY_L 6 24

PCI_CNTL PCI_55S PCI PCI_FRAME_L 6 24

PCIE_R2D PCIE_R2D * PCIE_9MIL
PCI_FW_REQ_L PCI_55S PCI PCI_FW_REQ_L 6 24
PCIE_D2R PCIE_D2R * PCIE_9MIL PCI_FW_GNT_L PCI_55S PCI PCI_FW_GNT_L 6 24

PCI_REQ1_L PCI_55S PCI PCI_REQ1_L 6 24

PCIE_D2R PCIE_R2D * PCIE_12MIL
PCI_GNT1_L PCI_55S PCI PCI_GNT1_L
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.18.1 & 10.19 PCI_REQ2_L PCI_55S PCI PCI_REQ2_L 6 24
PCI_GNT2_L PCI_55S PCI PCI_GNT2_L
Platform LAN (Nineveh) Constraints INT_PIRQA_L PCI_55S PCI INT_PIRQA_L 6 24
INT_PIRQB_L PCI_55S PCI INT_PIRQB_L 6 24

ON LAYER? INT_PIRQC_L PCI_55S PCI INT_PIRQC_L 6 24
LAN_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD INT_PIRQD_L PCI_55S PCI INT_PIRQD_L 6 24
INT_PIRQE_L PCI_55S PCI INT_PIRQE_L 6 24

ENET_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
INT_PIRQF_L PCI_55S PCI INT_PIRQF_L 6 24
GLAN_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

PCIE_A_R2D PCIE_100D PCIE_R2D PCIE_A_R2D_C_P
PCIE_100D PCIE_R2D PCIE_A_R2D_C_N
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PCIE_A_D2R PCIE_100D PCIE_D2R PCIE_A_D2R_P
PCIE_100D PCIE_D2R PCIE_A_D2R_N

ENET_CLK * =2.5:1_SPACING ?
PCIE_B_R2D PCIE_100D PCIE_R2D PCIE_B_R2D_C_P
ENET_GLAN * 20 MILS ? PCIE_100D PCIE_R2D PCIE_B_R2D_C_N
PCIE_B_D2R PCIE_100D PCIE_D2R PCIE_B_D2R_P

ENET_LAN * =1.5:1_SPACING ?
PCIE_100D PCIE_D2R PCIE_B_D2R_N
C ENET_MDI * 25 MILS ?
DG says 30 mils min separation. PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D_C_N
C
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30 PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
Controller Link (AMT) Constraints PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
ON LAYER? PCIE_FW_D2R_P
CLINK_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCIE_FW_D2R_N

PCIE_MINI_R2D PCIE_100D PCIE_R2D PCIE_E_R2D_C_P 6 24 36

CLINK_12MIL * =STANDARD 12 MILS 5 MILS 300 MILS =STANDARD =STANDARD
PCIE_100D PCIE_R2D PCIE_E_R2D_C_N 6 24 36
PCIE_MINI_D2R PCIE_100D PCIE_D2R PCIE_E_D2R_P 6 24 36
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT PCIE_100D PCIE_D2R PCIE_E_D2R_N 6 24 36

PCIE_ENET_R2D_C_P
CLINK * =1.8:1_SPACING ?
PCIE_ENET_R2D_C_N
CLINK_VREF * 12 MILS ? PCIE_ENET_D2R_P

PCIE_ENET_D2R_N
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30
GLAN_COMP GLAN_COMP 6 23
ENET_KBIAS NINEVEH_KBIAS_P
ENET_RBIAS NINEVEH_RBIAS
(PCIE_ENET_R2D) GLAN_100D ENET_GLAN ENET_GLAN_R2D_P
GLAN_100D ENET_GLAN ENET_GLAN_R2D_N
(PCIE_ENET_D2R) GLAN_100D ENET_GLAN ENET_GLAN_D2R_C_P
GLAN_100D ENET_GLAN ENET_GLAN_D2R_C_N
ENET_LAN LAN_55S ENET_LAN LAN_RSTSYNC
ENET_LAN LAN_55S ENET_LAN LAN_R2D<2..0>
ENET_LAN LAN_55S ENET_LAN LAN_D2R<2..0>
B ENET_GLAN_CLK LAN_55S ENET_CLK ENET_GLAN_CLK_R B
LAN_55S ENET_CLK ENET_GLAN_CLK
ENET_MDI0 ENET_100D ENET_MDI ENET_MDI_P<0>
ENET_100D ENET_MDI ENET_MDI_N<0>
CLINK_NB CLINK_55S CLINK CLINK_NB_CLK 6 16 25
CLINK_NB CLINK_55S CLINK CLINK_NB_DATA 6 16 25
CLINK_NB_RESET_L CLINK_55S CLINK CLINK_NB_RESET_L 6 16 25
CLINK_WLAN CLINK_55S CLINK CLINK_WLAN_CLK

CLINK_WLAN CLINK_55S CLINK CLINK_WLAN_DATA
CLINK_WLAN_RESET_L CLINK_55S CLINK CLINK_WLAN_RESET_L
NB_CLINK_VREF CLINK_12MIL CLINK_VREF NB_CLINK_VREF 6 16
SB_CLINK_VREF0 CLINK_12MIL CLINK_VREF SB_CLINK_VREF0 6 25
SB_CLINK_VREF1 CLINK_12MIL CLINK_VREF SB_CLINK_VREF1 6 25
SB Constraints (2 of 2)
A SYNC_MASTER=T9

A
D 051-7230 B.0.0

NONE 70 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Clock Signal Constraints Clock Net Properties
NET_TYPE
CLK_FSB_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

CK505_CPU CLK_FSB_100D CLK_FSB FSB_CLK_CPU_P 6 10 29 30 71
CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF CK505_CPU CLK_FSB_100D CLK_FSB FSB_CLK_CPU_N 6 10 29 30 71
CK505_NB CLK_FSB_100D CLK_FSB FSB_CLK_NB_P 6 14 29 30 71

CLK_MED_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
CK505_NB CLK_FSB_100D CLK_FSB FSB_CLK_NB_N 6 14 29 30 71
CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD CK505_ITP CLK_FSB_100D CLK_FSB XDP_CLK_P 6 7 13 29 30 66 71
CK505_ITP CLK_FSB_100D CLK_FSB XDP_CLK_N 6 7 13 29 30 66 71

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT CK505_PCIF0 CLK_MED_55S CLK_MED CK505_PCIF0_CLK_ITPEN
D CLK_FSB * 25 MIL ?
CK505_PCIF1
CK505_PCI1
CLK_MED_55S
CLK_MED_55S
CLK_MED
CLK_MED
CK505_PCIF1_CLK
CK505_PCI1_CLK
6 29 30
D
CLK_PCIE * 20 MIL ? CK505_PCI2 CLK_MED_55S CLK_MED CK505_PCI2_CLK
CK505_PCI3 CLK_MED_55S CLK_MED CK505_PCI3_CLK 6 29 30

CLK_MED * 20 MIL ?
CK505_PCI4 CLK_MED_55S CLK_MED CK505_PCI4_CLK
CLK_SLOW * 10 MIL ? CK505_PCI5 CLK_MED_55S CLK_MED CK505_PCI5_CLK_FCTSEL
(CPU_BSEL0) CLK_MED_55S CLK_MED CK505_48M_FSA

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 14.1 - 14.6
(CPU_BSEL2) CLK_MED_55S CLK_MED CK505_REF0_FSC
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CK505_DOT96 CLK_PCIE_100D CLK_PCIE NB_CLK96M_DOT_P 6 9 16 29 30 71

CLK_PCIE_100D CLK_PCIE NB_CLK96M_DOT_N 6 9 16 29 30 71

* * BGA BGA_P1MM
CK505_LVDS CLK_PCIE_100D CLK_PCIE NB_CLK100M_DPLLSS_P 6 9 16 29 30 71
MEM_CLK * BGA BGA_P2MM CLK_PCIE_100D CLK_PCIE NB_CLK100M_DPLLSS_N 6 9 16 29 30 71

CK505_SRC1 CLK_PCIE_100D CLK_PCIE CK505_SRC1_P

CLK_FSB * BGA BGA_P2MM
CLK_PCIE_100D CLK_PCIE CK505_SRC1_N
CLK_PCIE * BGA BGA_P2MM CK505_SRC2 CLK_PCIE_100D CLK_PCIE SB_CLK100M_DMI_P 6 24 29 30 71
CLK_PCIE_100D CLK_PCIE SB_CLK100M_DMI_N 6 24 29 30 71

CLK_MED * BGA BGA_P2MM
FSB_DSTB FSB_DSTB BGA BGA_P3MM CLK_PCIE_100D CLK_PCIE CK505_SRC3_N

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CK505_SRC5 CLK_PCIE_100D CLK_PCIE NB_CLK100M_PCIE_P 6 16 29 30 71
CLK_PCIE_100D CLK_PCIE NB_CLK100M_PCIE_N 6 16 29 30 71

CLK_FSB PWR * BUS2PWR_GND
CK505_SRC6 CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_P 6 29 30 36 71
CLK_FSB GND * BUS2PWR_GND CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_N 6 29 30 36 71


CLK_PCIE PWR * BUS2PWR_GND
C CLK_PCIE GND * BUS2PWR_GND
CK505_SRC8 CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE
CK505_SRC8_P
CK505_SRC8_N
C
CLK_MED PWR * BUS2PWR_GND
CLK_MED GND * BUS2PWR_GND (CK505_CPU) CLK_FSB_100D CLK_FSB FSB_CLK_CPU_P 6 10 29 30 71
(CK505_CPU) CLK_FSB_100D CLK_FSB FSB_CLK_CPU_N 6 10 29 30 71
(CK505_NB) CLK_FSB_100D CLK_FSB FSB_CLK_NB_P 6 14 29 30 71
(CK505_NB) CLK_FSB_100D CLK_FSB FSB_CLK_NB_N 6 14 29 30 71
(CK505_ITP) CLK_FSB_100D CLK_FSB XDP_CLK_P 6 7 13 29 30 66 71
(CK505_ITP) CLK_FSB_100D CLK_FSB XDP_CLK_N 6 7 13 29 30 66 71
(CK505_PCIF0) CLK_MED_55S CLK_MED PCI_CLK33M_LPCPLUS 6 30 43
(CK505_PCIF1) CLK_MED_55S CLK_MED PCI_CLK33M_SB 6 24 30
(CK505_PCI1) CLK_MED_55S CLK_MED PCI_CLK33M_FW

(CK505_PCI2) CLK_MED_55S CLK_MED PCI_CLK33M_TPM
(CK505_PCI3) CLK_MED_55S CLK_MED PCI_CLK33M_SMC 6 30 41
CK505 PCI4 is project-specific

CK505 PCI5 is project-specific
(CPU_BSEL0) CLK_MED_55S CLK_MED SB_CLK48M_USBCTLR 6 25 30
(CPU_BSEL2) CLK_MED_55S CLK_MED SB_CLK14P3M_TIMER 6 25 30
(CPU_BSEL0) CLK_MED_55S CLK_MED CK505_FSA 6 30
(CPU_BSEL2) CLK_MED_55S CLK_MED CK505_FSC 6 30
(CK505_DOT96) CLK_PCIE_100D CLK_PCIE NB_CLK96M_DOT_P 6 9 16 29 30 71
(CK505_DOT96) CLK_PCIE_100D CLK_PCIE NB_CLK96M_DOT_N 6 9 16 29 30 71
(CK505_LVDS) CLK_PCIE_100D CLK_PCIE NB_CLK100M_DPLLSS_P 6 9 16 29 30 71
(CK505_LVDS) CLK_PCIE_100D CLK_PCIE NB_CLK100M_DPLLSS_N 6 9 16 29 30 71
B (CK505_SRC1)
(CK505_SRC1)
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE
PEG_CLK100M_P
PEG_CLK100M_N
B
(CK505_SRC2) CLK_PCIE_100D CLK_PCIE SB_CLK100M_DMI_P 6 24 29 30 71
(CK505_SRC2) CLK_PCIE_100D CLK_PCIE SB_CLK100M_DMI_N 6 24 29 30 71
(CK505_SRC3) CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_EXCARD_P

(CK505_SRC3) CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_EXCARD_N
(CK505_SRC4) SATA_100D GND SB_CLK100M_SATA_P
(CK505_SRC4) SATA_100D GND SB_CLK100M_SATA_N
(CK505_SRC5) CLK_PCIE_100D CLK_PCIE NB_CLK100M_PCIE_P 6 16 29 30 71
(CK505_SRC5) CLK_PCIE_100D CLK_PCIE NB_CLK100M_PCIE_N 6 16 29 30 71
(CK505_SRC6) CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_P 6 29 30 36 71
(CK505_SRC6) CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_N 6 29 30 36 71
CK505 SRC7 is project-specific
(CK505_SRC8) CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_ENET_P

(CK505_SRC8) CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_ENET_N
SMC SMBus Net Properties

NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
SMBUS_SMC_A_S3_SCL SMB_55S SMB SMBUS_SMC_A_S3_SCL 6 7 36 40 41 44
SMBUS_SMC_A_S3_SDA SMB_55S SMB SMBUS_SMC_A_S3_SDA 6 7 36 40 41 44
SMBUS_SMC_B_S0_SCL SMB_55S SMB SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA SMB_55S SMB SMBUS_SMC_B_S0_SDA Clock & SMC Constraints
SMBUS_SMC_0_S0_SCL SMB_55S SMB SMBUS_SMC_0_S0_SCL 6 7 41 44 46
A SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMB_55S
SMB_55S
SMB
SMB
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
6 7 41 44 46
6 7 41 44 50 59
SYNC_MASTER=T9

A
SMBUS_SMC_BSA_SDA SMB_55S SMB SMBUS_SMC_BSA_SDA 6 7 41 44 50 59
SMBUS_SMC_MGMT_SCL SMB_55S SMB SMBUS_SMC_MGMT_SCL 6 41 44 48 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
SMBUS_SMC_MGMT_SDA SMB_55S SMB SMBUS_SMC_MGMT_SDA 6 41 44 48
D 051-7230 B.0.0

NONE 71 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I1
PPBUS_G3H NET_SPACING_TYPE=PWR 6 7 8 37 45 50 56 59 64
I2 PPBUS_R_G3H NET_SPACING_TYPE=PWR 6 7 8 42 52 53 54 55 59
I3
PPDCIN_G3H NET_SPACING_TYPE=PWR 6 7 8 50 57
I4
PPDCIN_G3H_R NET_SPACING_TYPE=PWR 6 50
I5
PPVBATT_G3H_R NET_SPACING_TYPE=PWR 6 50
I6
PPVBAT_G3H_CHGR_OUT NET_SPACING_TYPE=PWR 6 59
I7 PPVBAT_G3H_CHGR_REG NET_SPACING_TYPE=PWR 6 59
I8 PPVBAT_G3H_CHRGR_REG_R NET_SPACING_TYPE=PWR 6 59
I10 PPVBAT_G3H_CHRGR_REG_0 NET_SPACING_TYPE=PWR 6 59
I9
PPVCORE_S0_CPU NET_SPACING_TYPE=PWR 6 7 8 11 12 52 65
I12
PPVCORE_S0_NB_GFX NET_SPACING_TYPE=PWR 6 7 8 18 22 45 53 65
PPVDCIN_G3H_PRE NET_SPACING_TYPE=PWR 6 45 59
D
I11
I13
PPVDCIN_G3H_PRE_R NET_SPACING_TYPE=PWR 6 59 D
I14
PPVDCIN_G3H_PRE_0 NET_SPACING_TYPE=PWR 6 59
I16
PPVDCIN_G3H_PRE2 NET_SPACING_TYPE=PWR 6 59
I15
PPVIN_S5_IMVP6_VIN NET_SPACING_TYPE=PWR 6 52
I18
PPVOUT_S0_LCDBKLT NET_SPACING_TYPE=PWR 6 7 60 64
I17
PPVOUT_S0_LCDBKLT_SW NET_SPACING_TYPE=PWR 6 64
I19
PP0V9_S0 NET_SPACING_TYPE=PWR 6 7 8 33 55
I21 PP0V9_S3 NET_SPACING_TYPE=PWR 6 8 31 32 55


I20
PP1V5_S0 NET_SPACING_TYPE=PWR 6 7 8 11 12 22 26 27 54
I23
PP1V5_S0_NB_QDAC NET_SPACING_TYPE=PWR 6 22 PWR * =STANDARD ?
I100
PP1V5_S0_NB_VCCD_CRT NET_SPACING_TYPE=PWR 6 19 22
BUS2PWR_GND * 0.228 MM ?
I101 PP1V5_S0_NB_VCCD_QDAC NET_SPACING_TYPE=PWR 6 19 22
I22
PP1V5_S0_NB_VCCDMIPLL NET_SPACING_TYPE=PWR
I24
PP1V5_S0_NB_VCCDMIPLL_F NET_SPACING_TYPE=PWR
I25 PP1V5_S0_SB_VCCDMIPLL NET_SPACING_TYPE=PWR 6 26 27
I26
PP1V5_S0_SB_VCCDMIPLL_F NET_SPACING_TYPE=PWR 6 27
I28
PP1V5_S0_SB_VCCSATAPLL NET_SPACING_TYPE=PWR 6 26 27
I27
PP1V5_S0_SB_VCC1_5_B NET_SPACING_TYPE=PWR 6 23 24 26 27
I30 PP1V8_S0 NET_SPACING_TYPE=PWR 6 7 8 19 22 51 61
I29
PP1V8_S0_ANALOG_SDVO_F NET_SPACING_TYPE=PWR 6 61
I31 PP1V8_S0_ANALOG_TMDS_F NET_SPACING_TYPE=PWR 6 61
I33 PP1V8_S0_NB_VCCTXLVDS NET_SPACING_TYPE=PWR 6 19 22
I32 PP1V8_S0_PVCC1_TMDS_F NET_SPACING_TYPE=PWR 6 61
I35
PP1V8_S0_PVCC2_TMDS_F NET_SPACING_TYPE=PWR 6 61
I34 PP1V8_S0_TMDS_F NET_SPACING_TYPE=PWR 6 61
I36 PP1V8_S3 6 7 8 16 18 21 31 32 34 35 51
55 68
C I38
I37
PP1V8_S3M_NB_VCCSMCK
PP1V8_S3_NB_VCCSMCK_RC
NET_SPACING_TYPE=PWR
6 19 21
6 21
C
I39 PP1V05_S0 NET_SPACING_TYPE=PWR 6 7 8 10 11 12 13 14 18 19 21
23 26 27 30 42 54
I41
PP1V05_S0_NB_VCCPEG NET_SPACING_TYPE=PWR 6 15 19 21
I40
PP1V25_S0 NET_SPACING_TYPE=PWR 6 7 8 16 18 19 21 26 27 51 57
I43
PP1V25_S0M_NB_VCCA_HPLL NET_SPACING_TYPE=PWR 6 19 21
I42
PP1V25_S0_NB_DPLL NET_SPACING_TYPE=PWR 6 22
I44
PP1V25_S0_NB_PEGPLL NET_SPACING_TYPE=PWR 6 19 21
I46
PP1V25_S0_NB_PEGPLL_RC NET_SPACING_TYPE=PWR 6 21
I45
PP1V25_S0_NB_VCCA_DPLLA NET_SPACING_TYPE=PWR 6 19 22
I48
PP1V25_S0_NB_VCCA_DPLLB NET_SPACING_TYPE=PWR 6 19 22
I47
PP3V3_LCDVDD_SW NET_SPACING_TYPE=PWR 6 60
I49
PP3V3_LCDVDD_SW_F NET_SPACING_TYPE=PWR 6 7 60
I50 PP3V3_S0 NET_SPACING_TYPE=PWR 7
I52
PP3V3_S0_ANALOG_SDVO_F NET_SPACING_TYPE=PWR 6 61
I51
PP3V3_S0_CK505_VDDA NET_SPACING_TYPE=PWR 6
I54
PP3V3_S0_CK505_VDDA_R NET_SPACING_TYPE=PWR 6
I53
PP3V3_S0_CK505_VDD_CPU_SRC NET_SPACING_TYPE=PWR 6 29
I55
PP3V3_S0_CK505_VDD_PCI NET_SPACING_TYPE=PWR 6
I57
PP3V3_S0_CK505_VDD_REF NET_SPACING_TYPE=PWR 6
I56
PP3V3_S0_CK505_VDD48 NET_SPACING_TYPE=PWR 6
I59 PP3V3_S0_IMVP6_3V3 NET_SPACING_TYPE=PWR 6 52
I58
PP3V3_S0_LCD_F NET_SPACING_TYPE=PWR 6 7 60
I60
PP3V3_S0_NBCORE_FOLLOW_R NET_SPACING_TYPE=PWR 6 21
I62 PP3V3_S0_NB_CRTDAC_F NET_SPACING_TYPE=PWR 6 22
I61
PP3V3_S0_NB_TVDAC NET_SPACING_TYPE=PWR 6 22
PP3V3_S0_NB_TVDAC_F NET_SPACING_TYPE=PWR 6 22
B I63
I65
PP3V3_S0_NB_TVDAC_FOLLOW NET_SPACING_TYPE=PWR 6 22 B
I64 PP3V3_S0_NB_VCCA_CRTDAC NET_SPACING_TYPE=PWR 6 19 22
I67
PP3V3_S0_NB_VCCA_DAC_BG NET_SPACING_TYPE=PWR 6 19 22
I66
PP3V3_S0_NB_VCCA_TVDACA NET_SPACING_TYPE=PWR 6 19 22
I68
PP3V3_S0_NB_VCCA_TVDACB NET_SPACING_TYPE=PWR 6 19 22
I70 PP3V3_S0_NB_VCCA_TVDACC NET_SPACING_TYPE=PWR 6 19 22
I69
PP3V3_S0_SPVCC_TMDS_F NET_SPACING_TYPE=PWR 6 61
I72
PP3V3_S3 NET_SPACING_TYPE=PWR 6 7 8 36 42 44 48 51 58 60
I71 PP3V3_S3_AP_AUX NET_SPACING_TYPE=PWR 6 7 36
I73
PP3V3_S3_TOPCASE_F NET_SPACING_TYPE=PWR
I74 PP3V3_S5 NET_SPACING_TYPE=PWR 6 7 8 24 25 26 27 28 36 43 44
49 51 56 57 58 60
I76
PP3V3_S5_AVREF_SMC NET_SPACING_TYPE=PWR 6 41 42
I75
PP3V3_S5_SMC_AVCC NET_SPACING_TYPE=PWR 6 41
I78
PP3V42G3H_SW NET_SPACING_TYPE=PWR 6 57
I77
PP3V42_G3H NET_SPACING_TYPE=PWR 6 7 8 23 26 27 28 39 40 41 42
43 44 57 59
I79 PP3V42_G3H_SMC_F NET_SPACING_TYPE=PWR
I81
PP3V42_G3H_SMCUSBMUX_R NET_SPACING_TYPE=PWR 6 39
I80
PP4V5_AUDIO_ANALOG NET_SPACING_TYPE=PWR
I83 PP5V_S0 NET_SPACING_TYPE=PWR 6 7 8 22 27 40 43 47 51 52 53
63
I82
PP5V_S0_AUDIO NET_SPACING_TYPE=PWR
I84 PP5V_S0_AUDIO_AMP NET_SPACING_TYPE=PWR
I86
PP5V_S0_DVIPORT NET_SPACING_TYPE=PWR 6 7 37 63
I85 PP5V_S0_DVIPORT_D NET_SPACING_TYPE=PWR 6 63
PP5V_S0_IMVP6_VDD NET_SPACING_TYPE=PWR
I87
PP5V_S0_KBDLED_F NET_SPACING_TYPE=PWR
6 52
6 7 40
M82 Power and Ground Nets
I89
PP5V_S0_SB_V5REF
A I88
I91
PP5V_S0_TMDS_FUSE
6 26 27
6 63

SYNC_DATE=(MASTER)
A
I90 PP5V_S0_3G_F NET_SPACING_TYPE=PWR
I92
PP5V_S3 NET_SPACING_TYPE=PWR 6 7 8 40 58 60 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
I94
PP5V_S3_CAMERA_F NET_SPACING_TYPE=PWR 6 7 60 AGREES TO THE FOLLOWING
I93
PP5V_S3_IR_F NET_SPACING_TYPE=PWR I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
I96
PP5V_S3_USB2_EXTA NET_SPACING_TYPE=PWR 6 39 II NOT TO REPRODUCE OR COPY IT
I95 PP5V_S3_USB2_EXTA_F NET_SPACING_TYPE=PWR 6 7 37 39 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I97 PP5V_S5 NET_SPACING_TYPE=PWR 6 7 8 27 39 51 54 55 56 58
I98 PP5V_S5_SB_V5REF_SUS NET_SPACING_TYPE=PWR 6 26 27
I99 PP18V5_DCIN NET_SPACING_TYPE=PWR 6 7 50 D 051-7230 B.0.0

PP18V5_DCIN_ONEWIRE NET_SPACING_TYPE=PWR
I102 6 50
I103
PP18V5_G3H NET_SPACING_TYPE=PWR 6 7 8 50 59
NONE 72 73
I104
PP18V5_S5_CHGR_SW_R NET_SPACING_TYPE=PWR 6 59
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
M82 Board-Specific Spacing & Physical Constraints

TABLE_BOARD_INFO
BOARD LAYERS BOARD AREAS BOARD UNITS ALLEGRO

(MIL or MM) VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,ISL12,ISL13,BOTTOM NO_TYPE,BGA MM 15.5.1
TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_HEAD
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM
DEFAULT * Y 0.100 MM 0.076 MM 30 MM 0 MM 0 MM DEFAULT * 0.1 MM ?

TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM
STANDARD * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT STANDARD * =DEFAULT ?
D ALLOW ROUTE
BGA_P1MM * 0.1 MM ?
D
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM
BGA_P2MM * 0.2 MM ?
27P4_OHM_SE * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM
BGA_P3MM * 0.3 MM ?
27P4_OHM_SE ISL2,ISL4,ISL5 Y 0.215 MM 0.215 MM
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD
27P4_OHM_SE ISL10,ISL11,ISL13 Y 0.215 MM 0.215 MM SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

1:1_SPACING * 0.1 MM ?
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM
ON LAYER? 1.5:1_SPACING * 0.15 MM ?

45_OHM_SE * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM
1.8:1_SPACING * 0.18 MM ?
45_OHM_SE TOP,BOTTOM Y 0.290 MM 0.290 MM TABLE_SPACING_RULE_ITEM
45_OHM_SE ISL2,ISL4,ISL5 Y 0.091 MM 0.091 MM TABLE_SPACING_RULE_ITEM
2.28:1_SPACING * 0.228 MM ?
2.5:1_SPACING * 0.25 MM ?
ALLOW ROUTE
PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM
50_OHM_SE * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD
50_OHM_SE TOP,BOTTOM Y 0.235 MM 0.235 MM TABLE_SPACING_RULE_HEAD
GND * =STANDARD ?
PP1V8_MEM * =STANDARD ?
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_HEAD
ON LAYER? SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
C 55_OHM_SE * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

GND_P2MM * 0.2 MM 1000
C
55_OHM_SE TOP,BOTTOM Y 0.190 MM 0.190 MM TABLE_SPACING_RULE_ITEM
PWR_P2MM * 0.2 MM 1000
55OHM SE ON INTERNAL LAYERS NOT ACHIEVABLE IN M82 STACKUP
55_OHM_SE ISL2,ISL4,ISL5 Y 0.070 MM 0.070 MM USING 50OHM SE
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD
55_OHM_SE ISL10,ISL11,ISL13 Y 0.070 MM 0.070 MM SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

NB_STATIC * =STANDARD ?
ON LAYER?
70_OHM_DIFF * Y =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

70_OHM_DIFF TOP,BOTTOM Y 0.310 MM 0.310 MM 0.130 MM 0.130 MM

70_OHM_DIFF ISL2,ISL4,ISL5 Y 0.132 MM 0.132 MM 0.200 MM 0.200 MM

ON LAYER?



B PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
B


ON LAYER?



ON LAYER?



100_OHM_DIFF Y 0.065 MM 0.065 MM 0.280 MM 0.280 MM

ISL10,ISL11,ISL13
M82 Rule Definitions
A SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP

A
1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM
D 051-7230 B.0.0

NONE 73 73
8 7 6 5 4 3 2 1

Aliases Resolved: Schem, MLB, M82 PVT

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8 7 6 5 4 3 2 1

NOTICE OF PROPRIETARY PROPERTY A

DRAWING SIZE DRAWING NUMBER

2.0 GHz SLG2AP101

MEM Active Conn Supplies

SIL1392 NB-GMCH U3150

HEAT-PIPE/FIN Temp Sensor J5500 PG 46

A B 0 BSA MGMT ADC Fan Ser

DMI CLnk 0 SPI

E-NET CLnk 1 PCI HDA

Pg 35 System Block Diagram

NOTICE OF PROPRIETARY PROPERTY

SIZE DRAWING NUMBER REV.

APPLE INC. SCALE SHT OF

01 17 1V5S0_RUNSS 1.5V PP1V5_S0_REG

PP1V8_S3_FET =PP1V8_S0_FET 16 PM_SLP_S3_L

NOTICE OF PROPRIETARY PROPERTY

APPLE INC. SCALE SHT OF

BOMs BOMOPTION Groups

630-7886 PCBA,MLB,1.6GHZ,MI 2GB,SS CAP,M82 EEE_XSC,M82_COMMON,M82_MICRON,CPU_PRQ_1_6GHZ,M82_SS_CAP M82_COMMON ALTERNATE,COMMON,M82_COMMON1,M82_COMMON2,M82_COMMON3

630-9024 PCBA,MLB,1.6GHZ,HY 2GB,SS CAP,M82 EEE_YMS,M82_COMMON,M82_HYNIX,CPU_PRQ_1_6GHZ,M82_SS_CAP M82_COMMON1 ISL6258,BOOTROM_DEVEL,SMC_PRGRM

630-9133 PCBA,MLB,1.8GHZ,MI 2GB,SS CAP,M82 EEE_Z80,M82_COMMON,M82_MICRON,CPU_PRQ_1_8GHZ,M82_SS_CAP M82_COMMON2 SMS_MOT_DIS,LPCPLUS,XDP,DRAM_2GB

630-9134 PCBA,MLB,1.8GHZ,HY 2GB,SS CAP,M82 EEE_Z81,M82_COMMON,M82_HYNIX,CPU_PRQ_1_8GHZ,M82_SS_CAP M82_COMMON3

D 630-9204 PCBA,MLB,1.6GHZ,HY 2GB,MU CAP,M82 EEE_ZU5,M82_COMMON,M82_HYNIX,CPU_PRQ_1_6GHZ,M82_MU_CAP

630-9206 PCBA,MLB,1.6GHZ,MI 2GB,MU CAP,M82 EEE_ZU7,M82_COMMON,M82_MICRON,CPU_PRQ_1_6GHZ,M82_MU_CAP M82_HYNIX_LP DRAM_HYNIX_LP,DRAM_SPD_2

630-9207 PCBA,MLB,1.6GHZ,MI 2GB,TY CAP,M82 EEE_ZU8,M82_COMMON,M82_MICRON,CPU_PRQ_1_6GHZ,M82_TY_CAP M82_SS_CAP SS_CAP_1UF,SS_CAP_2_2UF,SS_CAP_10UF

630-9208 PCBA,MLB,1.8GHZ,HY 2GB,MU CAP,M82 EEE_ZU9,M82_COMMON,M82_HYNIX,CPU_PRQ_1_8GHZ,M82_MU_CAP M82_MU_CAP MU_CAP_1UF,MU_CAP_2_2UF,MU_CAP_10UF

630-9209 PCBA,MLB,1.8GHZ,HY 2GB,TY CAP,M82 EEE_ZUA,M82_COMMON,M82_HYNIX,CPU_PRQ_1_8GHZ,M82_TY_CAP M82_TY_CAP TY_CAP_1UF,TY_CAP_2_2UF,TY_CAP_10UF

630-9210 PCBA,MLB,1.8GHZ,MI 2GB,MU CAP,M82 EEE_ZUB,M82_COMMON,M82_MICRON,CPU_PRQ_1_8GHZ,M82_MU_CAP

630-9211 PCBA,MLB,1.8GHZ,MI 2GB,TY CAP,M82 EEE_ZUC,M82_COMMON,M82_MICRON,CPU_PRQ_1_8GHZ,M82_TY_CAP

SST89V54RD MICROCONTROLLER U9300 CRITICAL SST8051_BLANK

333S0406 4 MICRON,DRAM,64M16,8x12.5 U3140,U3150,U3160,U3170 CRITICAL DRAM_MICRON

333S0406 4 MICRON,DRAM,64M16,8x12.5 U3200,U3210,U3220,U3230 CRITICAL DRAM_MICRON

333S0406 4 MICRON,DRAM,64M16,8x12.5 U3240,U3250,U3260,U3270 CRITICAL DRAM_MICRON

333S0411 4 HYNIX,DRAM,64M16,8x13 U3100,U3110,U3120,U3130 CRITICAL DRAM_HYNIX

333S0411 4 HYNIX,DRAM,64M16,8x13 U3140,U3150,U3160,U3170 CRITICAL DRAM_HYNIX

333S0411 4 HYNIX,DRAM,64M16,8x13 U3200,U3210,U3220,U3230 CRITICAL DRAM_HYNIX

333S0411 4 HYNIX,DRAM,64M16,8x13 U3240,U3250,U3260,U3270 CRITICAL DRAM_HYNIX

333S0415 4 HYNIX,DRAM,64M16,8x13,LP U3100,U3110,U3120,U3130 CRITICAL DRAM_HYNIX_LP

333S0415 4 HYNIX,DRAM,64M16,8x13,LP U3140,U3150,U3160,U3170 CRITICAL DRAM_HYNIX_LP

333S0415 4 HYNIX,DRAM,64M16,8x13,LP U3200,U3210,U3220,U3230 CRITICAL DRAM_HYNIX_LP

333S0415 4 HYNIX,DRAM,64M16,8x13,LP U3240,U3250,U3260,U3270 CRITICAL DRAM_HYNIX_LP

353S1938 1 IC,ISL6258,REV2,BAT CHGR, 28P QFN U7900 CRITICAL ISL6258

SIZE DRAWING NUMBER REV.

APPLE INC. SCALE SHT OF

1UF 0402 CAPACITOR VENDOR TABLES FOR ACOUSTICS

Acoustic Cap BOM Config Tables

NOTICE OF PROPRIETARY PROPERTY

SIZE DRAWING NUMBER REV.

APPLE INC. SCALE SHT OF

I95 TRUE BATT_POS 57 58 60 72

I613 TRUE PM_RI_L 25 I592 TRUE PP3V42_G3H_SMCUSBMUX_R 39 72

I656 TRUE RUNSS_GATE_D_L 51 I633 TRUE SMBUS_SMC_0_S0_SCL 71

66 NOTICE OF PROPRIETARY PROPERTY

I639 TRUE SMBUS_SMC_BSA_SDA

Power Supply NO_TESTs I507 TRUE SMC_LID 6 40 41 42 I732 TRUE VGA_R

TRUE SMC_SYS_LED 6 40 41 FUNC TEST - AIRPORT

I510 TRUE USB2_WSPRING_N 6 9 24 40 69 I741 TRUE CK505_SRC_CLKREQ6_L 6 7

I516 TRUE SMBUS_SMC_A_S3_SCL 6 7 36 40 41 44 71

I519 TRUE USB_IR_N 6 7 9 24 40 69

I521 TRUE USB_IR_P 6 7 9 24 40 69

I676 TRUE PP5V_S0_KBDLED_F 6 7 40 72

I734 TRUE LSOC_H_R 6