K36C MLB schematic overview

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
A 0000729452 ENGINEERING RELEASED 2009-05-21
APR/29/2009
D
K36C MLB SCHEMATIC (.csa) Date
D
(.csa) Date
Page Contents Page

TABLE_TABLEOFCONTENTS_HEAD
Contents
45 08/17/2008
TABLE_TABLEOFCONTENTS_HEAD
1
1
Table of Contents K36BH_MLB
08/22/2007
TABLE_TABLEOFCONTENTS_ITEM
38 SATA Connectors K36B_MLB
46 08/17/2008
2
2
System Block Diagram K36B_MLB
08/17/2008
39 External USB Connectors K36B_MLB
48 07/17/2008
3
3
Power Block Diagram K36B_MLB
08/17/2008
40 Front Flex Support K36B_MLB
49 08/17/2008
4
4
CONFIGURATION OPTIONS K36B_MLB
08/17/2008
41 SMC K36B_MLB
50 08/17/2008
5
5
Revision History K36B_MLB TABLE_TABLEOFCONTENTS_ITEM
42 SMC Support K36B_MLB
51 08/17/2008
6
6
JTAG Scan Chain K36B_MLB
08/17//2008
43 LPC+SPI Debug Connector K36B_MLB
52 08/17/2008
7
7
FUNC TEST K36B_MLB
08/17/2008
44 SMBUS CONNECTIONS K36B_MLB
53 08/17/2008
8
8
Power Aliases K36B_MLB TABLE_TABLEOFCONTENTS_ITEM
45 VOLTAGE SENSING K36B_MLB
54 08/17/2008
9
9
SIGNAL ALIAS K36B_MLB TABLE_TABLEOFCONTENTS_ITEM
46 Current Sensing K36B_MLB
55 08/17/2008
10
10
CPU FSB K36B_MLB
08/18/2008
47 Thermal Sensors K36B_MLB
56 08/17/2008
11
11
CPU Power & Ground K36B_MLB
08/17/2008
48 Fan K36B_MLB
58 08/17/2008
12
12
CPU Decoupling K36B_MLB
08/17/2008
49 GEYSER K36B_MLB
59 08/17/2008
C
13
13
eXtended Debug Port(MiniXDP) M99_MLB
01/08/2008
50
61
SMS K36B_MLB
081/17/2008
C
14
14
MCP CPU Interface K36B_MLB
08/17/2008
51 SPI ROM K36B_MLB
62 08/29/2008
15
15
MCP Memory Interface K36B_MLB
08/17/2008
52 AUDIO: CODEC K36A_MLB
66 08/29/2008
16
16
MCP Memory Misc K36B_MLB
08/17/2008
53 AUDI0: SPEAKER AMP K36A_MLB
67 08/29/2008
17
17
MCP PCIe Interfaces K36B_MLB
08/17/2008
54 AUDIO: JACK K36A_MLB
68 08/29/2008
18
18
MCP Ethernet & Graphics K36B_MLB
08/17/2008
55 AUDIO: JACK TRANSLATORS K36A_MLB
69 08/17/2008
19
19
MCP PCI & LPC K36B_MLB
08/17/2008
56 DC-In & Battery Connectors RAYMOND
70 08/17/2008
20
20
MCP SATA & USB K36B_MLB
08/17/2008
57 PBUS Supply/Battery Charger K36B_MLB
72 08/17/2008
21
21
MCP HDA & MISC K36B_MLB
08/17/2008
58 5V/3.3V SUPPLY K36B_MLB
73 08/17/2008
22
22
MCP Power & Ground K36B_MLB
08/17/2008
59 1.8V/0.9V DDR2 SUPPLY K36B_MLB
74 08/17/2008
23
24
MCP79 A01 Silicon Support K36B_MLB
08/17/2008
60 IMVP6 CPU VCore Regulator K36B_MLB
75 08/17/2008
24
25
MCP Standard Decoupling K36B_MLB
08/17/2008
61 MCP VCORE REGULATOR K36B_MLB
76 08/17/2008
25
26
MCP Graphics Support K36B_MLB
08/17/2008
62 CPU VTT(1.05V) SUPPLY K36B_MLB
77 08/17/2008
26
28
SB Misc K36B_MLB
08/17/2008
63 MISC POWER SUPPLIES K36B_MLB
78 08/17/2008
27
29
FSB/DDR2 VREF MARGINING K36B_MLB
08/17/2008
64 POWER SEQUENCING K36B_MLB
79 08/17/2008
28
31
DDR2 SO-DIMM Connector A K36B_MLB
08/17/2008
65 POWER FETS K36B_MLB
90 08/17/2008
29
32
DDR2 SO-DIMM Connector B K36B_MLB
08/17/2008
66 INVERTER,LVDS K36B_MLB
93 08/17/2008
30
33
Memory Active Termination
08/17/2008
67 TMDS ALIASES K36B_MLB
B TABLE_TABLEOFCONTENTS_ITEM
31
34
Right Clutch Connector
K36B_MLB
K36B_MLB
08/17/2008
68
94
MINI-DVI CONNECTOR K36B_MLB
08/17/2008
B
100 08/17/2008
32
37
Ethernet PHY (RTL8211CL) SUMA
03/20/2008
69 CPU/FSB Constraints K36B_MLB
101 08/17/2008
33
38
Ethernet & AirPort Support SUMA
04/04/2008
70 Memory Constraints K36B_MLB
102 08/17/2008
34
39
ETHERNET CONNECTOR SUMA
04/04/2008
71 MCP Constraints 1 K36B_MLB
103 08/17/2008
35
41
FireWire LLC/PHY(FW643E) K36B_MLB
08/17/2008
72 MCP Constraints 2 K36B_MLB
104 08/17/2008
36
42
FireWire Port Power K36B_MLB
08/17/2008
73 Ethernet Constraints K36B_MLB
105 08/17/2008
37
43
FireWire Ports K36B_MLB
(MASTER)
74 FireWire Constraints K36B_MLB
106 08/17/2008
75 SMC Constraints K36B_MLB
109 08/17/2008
76 K36B RULE DEFINITIONS K36B_MLB
A A
DRAWING TITLE
Schematic / PCB #’s SCHEM,MLB,K36C

DRAWING NUMBER SIZE
Apple Inc. 051-8089 D

REVISION
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION R
A.0.0
051-8089 1 SCHEM,MLB,K36C SCH CRITICAL NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
820-2496 1 PCBF,MLB,K36B PCB CRITICAL PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 109
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 1 OF 76
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U1000
J1300
INTEL CPU
XDP CONN
2.X OR 3.X GHZ
PG 12
PENRYN
PG 9
FSB
D 64-Bit
J6950
D
800/1067/1333 MHz
PG 13
DC/BATT POWER SUPPLY
J3100,3200 PG 60
MAIN
GPIOs FSB INTERFACE
MEMORY 2 UDIMMs
DDR2-800MHZ DIMM
PG 14 J5520
PG 25,26
TEMP SENSOR
PG 41
Misc
CLK
PG 24
U6100
SYNTH POWER SENSE
PG 45
SPI
J4501 Boot ROM J5601
SATA SPI FAN CONN AND CONTROL

PG 52 PG 48,49
Conn 3GHZ. PG 20
PG 38
HD
J4500 NVIDIA U4900
B,0 BSB ADC Fan Ser
SATA J5100
Conn 3GHZ. SATA MCP79 SMC Prt

LPC Conn
PG 38 PG 19 LPC Port80,serial
C ODD
PG 18
PG 41
PG 43 C
U1400
J9001
LVDS PWR
CONN LVDS OUT CTRL
PG 71
RGB OUT
J4810 J5800 J4501 J9001 J4600,4601
DP OUT TRACKPAD/ EXTERNAL

J9401
Bluetooth IR CAMERA
KEYBOARD USB
HDMI OUT Connectors
PG 40 PG 40 PG 40 PG 40
MINI DVI PG 39
CONN DVI OUT
(UP TO 12 DEVICES)
9
8
TMDS OUT
PG 71
7
USB
PG 19
PG 17
6
5
4
3
2
UP TO 20 LANES3
1
0
PCI-E
PG 16
B B
SMB
PG 20 SMB
CONN
RGMII PCI HDA PG 44
(UP TO FOUR PORTS) DIMM’s
PG 17
PG 18 PG 20
U6200
U4100 Audio
PCI-E Codec
FIREWIRE PG 53
FW643E
PG 35
J4300 U6801 U6801 U6610,6620,6630

U3700
A FW PORT GB
E-NET
HEADPHONE Line Out Speaker
SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 A
Conn Amp Amp Amps PAGE TITLE
88E1116
PG 37
PG 31
PG 55 PG 56 PG 57 System Block Diagram
DRAWING NUMBER SIZE

J3400 J3900 REVISION
MINI PCI-E J6800,6801,6802,6803

R
A.0.0
E-NET NOTICE OF PROPRIETARY PROPERTY: BRANCH
AirPort Audio
Conn PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
PG 28 Conns THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PG 33
PG 59 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
2 OF 109
<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
IV ALL RIGHTS RESERVED
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
K36C POWER SYSTEM ARCHITECTURE D6905

02
PPVIN_G3H_P3V42G3H SHDN*
3.425V G3HOT PP3V42_G3H_REG
03 SMC PWRGD 04
D6905 PBUS_VSENSE VIN LT3470 VOUT RN5VD30A-F SMC_RESET_L
U6990 U5000
7A FUSE V Q5315
D 01 PPVBAT_G3H_CHGR_REG PPBUS_G3H D
02 22
VIN
CPUVTTS0_EN PPCPUVTT_S0_REG
EN_PSV VOUT
CHGR_EN (S0) (8A MAX CURRENT)
(S5)
CPUVTT 09-1
(1.05V) R7955 PWRBTN*
6A FUSE ENABLES PP1V05_S0_FET
AC DCIN(16.5V) TPS51117 MCP79
ADAPTER
IN
A VIN
VOUT
U5403 U7600
LPC_RESET0* LPC_RESET_L
29-1
SMC_BATT_ISENSE PGOOD
RSMRST*
PBUS SUPPLY/
SMC_DCIN_ISENSE
BATTERY CHARGER A CPUVTTS0_PGOOD
CPUPWRGD
30
CPU_PWRGD
ISL6258A SMC_CPU_VSENSE
U7000 01 02 CPU VCORE
V MCP_PS_PWRGD PS_PWRGD
29
J6950 VIN
VOUT A SMC_CPU_ISENSE
PPVCORE_S0_CPU_REG
(44A MAX CURRENT)
26
U2850
CPU_RESET#
U1400
ISL9504B
IMVP_VR_ON VR_ON
3S2P Q7050
BATT_POS_F PPVBAT_G3H_CHGR_OUT PGOOD VR_PWRGOOD_DELAY 28
(9 TO 12.6V) 25 U7400
C CPU C
CHGR_BGATE PPBUS_G3H 4.6V AUDIO PWRGOOD
IN MAX8902A PP4V6_AUDIO_ANALOG
1.05V (S5) U6201
EN EN OVT RESET*
TPS62510
07 PP1V05_S5_REG U1000
MCP79 11 11-1
PVIN U7750
VOUT
08 32
P3V3S3_EN RC P1V05_S5_EN PG
PM_SLP_S4_L DELAY
02 09
SMC P16 P1V05_S5_PGOOD
SLP_S3# 15 U4900 04-1 Q7800 ENTRIP1 VIN

5V PP5VRT_S0_REG PP5VLT_S3_REG
11-3
EN1
(RT)
VOUT1
(4A MAX CURRENT)
17
U1400 RC DDRREG_EN P60
SMC_PM_G2_EN
DELAY (S5) PP3V3_S5_REG PP3V3_S5
ENTRIP2 VOUT2
(4A MAX CURRENT)
06
RC EN2 3.3V
PCI_RESET0# DELAY Q7910
TPS51125
05 PP3V3_S3_FET
31
U7200 13
RC 11-2 P5VLTS3_EN PGOOD VREG3
11-1
DELAY
P3V3S3_EN
P5V3V3_PGOOD
Q7930 SMC 10
18 24 PM_RSMRST_L
B PP3V3_S0_FET ALL_SYS_PWRGD
RSMRST_OUT(P15)
PWRGD(P12) 99ms DLY
B
IMVP_VR_ON
15 09-1
RSMRST_PWRGD
IMVP_VR_ON(P16) 25
RSMRST_IN(P13)
Q3805 P3V3S0_EN
PM_SLP_S3_L 1.5V (S0) SMC_LRESET_L
SMC_ONOFF_L
PVIN Q3810 PWR_BUTTON(P90)
PM_WLAN_EN_L
16 16-3 TPS62510
PP1V5_S0_FET
19-1
P3V3_ENET_FET P17(BTN_OUT) PM_PWRBTN_L
P1V5S0_EN EN U7740 VOUT RST* SMC_RESET_L
P1V5_S0_PGOOD
P3V3ENET_EN_L
P5V3V3_PGOOD SLP_S5_L
Q3805 SLP_S5_L(P95)
MCPCORES0_PGOOD SLP_S4_L
AP_PWR_EN P1V5_S0_PGOOD SLP_S4_L(P94)
PP1V8_S0_FET
1.8V S0 PP1V8_S0_REG
21 CPUVTTS0_PGOOD SLP_S3_L
SMC_ADAPTER_EN FL7700 P5V_LT_S3_PGOOD
SLP_S3_L(P93)
04-1
02 S3 TO S0
S0PGOOD_PWROK U4900
FETS PP1V5_S0_FET R5490 PP1V5_S0
21
=DDRREG_EN
VIN
1.8V PP1V8_S3_REG
14 (Q7901 & Q7971)
S5 VOUT1
(12A MAX CURRENT) RST*
PM_SLP_S3_L =DDRVTT_EN
S3 0.9V VOUT2 PP3V3_S0 SEL
PP0V9_S0_REG
PP1V8_S0
(1A MAX CURRENT) ADJ1
RC P1V5S0_EN 16-2 TPS51116 PP1V05_S0
16-3 ADJ2 LTC2909
A DELAY P1V05S0_EN
(S0)
U7300
R5490 20 U7870 PAGE TITLE
RC MCPDDR_EN
P3V3S0_EN
16-2 MCP_CORE
VOUT2
PPVCORE_S0_MCP_REG_R PPVCORE_S0_MCP Power Block Diagram
DELAY 16-2 MCPCORES0_EN EN2 (23A MAX CURRENT) DRAWING NUMBER SIZE
(S0)
CPUVTTS0_EN PP5VLT_S3 12 REVISION
RC
DELAY 16-3 PBUSVSENS_EN 16-2 11-2 P5VLTS3_EN EN1
5V (LT)
VOUT1
PP5VLT_S3_REG R
A.0.0
(4.5A MAX CURRENT) NOTICE OF PROPRIETARY PROPERTY: BRANCH
(S0)
VIN
PGOOD1 PP5V_LT_S3_PGOOD PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
RC MCPCORES0_EN P5VRTS0_EN_L 16-1 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
SN0802043
DELAY 16-4 (S0) U7500 MCPCORES0_PGOOD
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 3 OF 109
02 PGOOD2
8 7 6 5 4 3 2 1
PAGE_BORDER=TRUE
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
(NONE)
D
BOM OPTION TABLE_5_HEAD
D
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM
341S2420 1 IC,SMC,HS8/2117,9X9MM,TLP,HF,BLANK U4900 CRITICAL SMC_PROG

TABLE_5_ITEM
341S2418 1 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM_PROG

TABLE_5_ITEM
341S2093 1 IC, CYPRESS, CY7C63833 U4800 CRITICAL

TABLE_5_ITEM
338S0654 1 IC,FW643E,1394B PHY/OHCI LINK/PCI-E,127 U4100 CRITICAL

TABLE_5_HEAD
ALTERNATES OPTION
TABLE_5_ITEM
826-4393 1 LBL,P/N LABEL,PCB,28MMX6MM [EEE:9WN] CRITICAL TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
TABLE_ALT_ITEM
TABLE_5_HEAD 128S0093 128S0218 ALL ALTERNATE PER CYNDI

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_ALT_ITEM
TABLE_5_ITEM
152S0694 152S0138 ALL ALTERNATE PER CYNDI
337S3777 1 PDC,SLGFF,2.13,,25W,1066,R0,3M,BGA,P7450 U1000 CRITICAL TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 152S0796 152S0685 ALL ALTERNATE PER CYNDI
TABLE_ALT_ITEM
C
TABLE_5_ITEM
C 338S0702 1 IC,GMCP,MCP79,35X35MM,BGA1437,B03 U1400 CRITICAL 152S0778
157S0058
152S0693
157S0055
ALL
ALL
ALTERNATE PER CYNDI
TABLE_ALT_ITEM
ALTERNATE PER CYNDI

TABLE_ALT_ITEM
TABLE_5_HEAD
516S0727 516S0588 ALL
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_ALT_ITEM
TABLE_5_ITEM
518S0704 518S0392 ALL
338S0694 1 IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P U3700 CRITICAL
TABLE_5_HEAD

TABLE_5_ITEM
514-0665 1 CONN,RCPT,MINI-DVI,32P,R/A J9401 CRITICAL

TABLE_5_ITEM
514-0666 1 CONN,RCPT,3.5MM AUDIO IN,R/A J6750 CRITICAL

TABLE_5_ITEM
514-0667 1 CONN,RCPT,3.5MM AUDIO OUT,R/A J6700 CRITICAL

TABLE_5_ITEM
514-0668 1 CONN,RCPT,RJ45,NO FILTER,8P J3900 CRITICAL

TABLE_5_ITEM
514-0669 1 CONN,RCPT,USB,4P,MIDPLANE J4600 CRITICAL

TABLE_5_ITEM
514-0669 1 CONN,RCPT,USB,4P,MIDPLANE J4601 CRITICAL
B B
BOARD STACK-UP AND CONSTRUCTION
Top SIGNAL
2 GROUND
3 SIGNAL(High Speed)
4 SIGNAL(High Speed)
5 GROUND
6 POWER
7 POWER
8 GROUND
A 9 SIGNAL(High Speed) A
PAGE TITLE
10 SIGNAL(High Speed) CONFIGURATION OPTIONS

DRAWING NUMBER SIZE
11 GROUND Apple Inc. 051-8089

REVISION
D
R
A.0.0
BOTTOM SIGNAL NOTICE OF PROPRIETARY PROPERTY:
BRANCH
PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

4 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Revision History
*****2008/08/21*****
PAGE 61:
- U7500 PIN V5DRV1 LINK TO PP5V_S0_MCPREG_VCC. *****2008/08/25***** *****2008/10/31*****
- U7500 PIN TONSEL LINK TO GND DIRECTLY. CHANGE CSA BASE ON WILL’S SUGGESTION. PAGE 41:
PAGE 9: - U4100 CHANGE FROM 338S0523 TO 338S0654
PAGE 64:
- ADD GMUX_JTAG_TMS AND GMUX_JTAG_TDI IN MISC NC MCP79 ALIASES.
- R7859 CHANGE TO 100 OHM.
PAGE 18: *****2008/11/01*****
- R7879 CHANGE TO 100K OHM. - NETNAME ENET_INTR_L CHANGE TO TP_ENET_INTR_L.
PAGE 65: PAGE 4:
- ENET_PWRDWN_L CHANGE TO TP_ENET_PWRDWN_L
- BOM change U1400 CHANGE FROM 338S0678 TO 338S0702
- DELETE 1.05V S0 FET CIRCUIT. PAGE 19:
PAGE 57: *****2008/11/05*****
D - R7011 CHANGE TO 9.31K OHM, 1%
- DELETE R1987,R1988,R1995,R1970,R1971,R1972,R1973,R1996,R1997,R1998,R1999,R1978,R1979
(FOLLOW M97 DESIGN).
PAGE 62:
- C6210 CHANGE FROM 127S0062 TO 127S0108
D
*****2008/08/22***** - NET DPMUX_LOWPWR_L SYNC M97 NETNAME AUD_IPHS_SWITCH_EN PAGE 68:
PAGE 7: - NET LVDSMUX_SEL_IG_L SYNC M97 NETNAME - C6832, C6833 CHANGE FROM 127S0062 TO 127S0108
- ADD SMC_EXCARD_PWR_EN TEST_POINT PAGE 45:
- NET DPMUX_SEL_IG_L SYNC M97 NETNAME
- DELETE L4502, NET SATA_HDD_D2R_UF_P / SATA_HDD_D2R_UF_N
PAGE 8: PAGE 28:
- L4501 / Fl4520 / FL4525 CHANGE FROM 155S0303 TO 155S0371
- ADD =PP3V42_G3H_RTC_D LINK TO =PP3V42_G3H_REG - REMOVE NET DIMM_OVERTEMPA_L
PAGE 102:
PAGE 14: PAGE 29: - DELETE PHYSICAL/SPACING SETTING OF SATA_HDD_D2R_UF_P / SATA_HDD_D2R_UF_N
- R1410 CHANGE TO 49.9 OHM - REMOVE NET DIMM_OVERTEMPA_L
- CHANGE R1440 TO 150_5% AND NO STUFF PAGE 42: *****2008/11/06*****
- ADD SMC_EXCARD_PWR_EN TO TP_SMC_EXCARD_PWR_EN - U5413 CHANGE FROM 353S1432 TO 353S2220
PAGE 26:
- ADD SMC_RSTGATE_L TO TP_SMC_RSTGATE_L - R7417 CHANGE FROM 5.36K(114S0289) TO 4.42K(114S0280)
- R2872 CHANGE TO 0OHM
- RTC FOLLOW M97 DESIGN AND USE SUPERCAP SOLUTION - ADD ALS_GAIN TO NC_ALS_GAIN *****2008/11/12*****
- ADD ESTARLDO_EN TO NC_ESTARLDO_EN - U1000 CHANGE FROM 373S3646 TO 373S3702
- MCP S0 PWRGD FOLLOW M97 DESIGN
PAGE 29: - ADD SMC_ANALOG_ID TO NC_SMC_ANALOG_ID
- ADD SMC_SYS_KBDLED TO NC_SMC_SYS_KBDLED *****2008/11/19*****
- PULL R3240 DOWN TO GND. PULL R3241 HIGH - J6950 CHANGE FROM 516S0620 TO 516S0735
PAGE 32,33,34 - ADD R5054 10KOHM LINK SMC_GPU_ISENSE PULL DOWN TO GND.
- J9401 CHANGE FROM 514-0517 TO 514-0665
- FOLLOW M97 DESIGN - ADD R5055 10KOHM LINK SMC_NB_MISC_ISENSE PULL DOWN TO GND. - J6750 CHANGE FROM 514-0519 TO 514-0666
PAGE 39: PAGE 43:
- J6700 CHANGE FROM 514-0521 TO 514-0667
- R5142 CHANGE TO NO STUFF.
- D4600/D4601/PIN-6 CONNECT TO USB VBUS (FOLLOW M97D) - J3900 CHANGE FROM 514-0523 TO 514-0668
PAGE 46:
PAGE 44: - R5416 CHANGE TO 4.53K AND DELETE BOM OPTION. - J4600, J4601 CHANGE FROM 514-0527 TO 514-0669
- R5270/R5271 = 1K (FOLLOW M97D) - R5417 CHANGE TO 4.53K AND DELETE BOM OPTION. - U3700 CHANGE FROM 338S0570 TO 338S0694
- R5280/R5281 = 1K (FOLLOW M97D) - R5418 CHANGE TO 4.53K AND DELETE BOM OPTION. *****2008/11/26*****
PAGE 68: PAGE 57: - PAGE 61 NOTE : CORRECT REFERENCE TO R5164 AND R5144
- CHANGE C9411, C9412 TO 220PF - NETNAME FROM CHGR LOWCURRENT REF CHANGE TO CHGR_LOWCURRENT_REF
- J3400 CHANGE TO 516S0729
- NETNAME FROM CHGR LOWCURRENT GATE CHANGE TO CHGR_LOWCURRENT_GATE
- CHANGE R9462, R9463 TO 2.7KOHM PAGE :
- ADD C9480 0.1UF_16V_0402 FROM GND_CHASSIS_TMDS_DOWN TO GND - REMOVE R7884 AND C7884 *****2008/12/12*****
- R5144 and R5164 changed to 10K 5% 0402 (116S0090)
C - CHANGE R9460,R9461 TO 0OHM,
- CHANG C9442 AND C9443 TO 47PF
PAGE 66:
- REMOVE J9001 PIN 20 AND PIN21 NET. *****2008/12/17*****
C
- U4900 symbol update
*****2008/08/23***** *****2008/09/02*****
MODIFY ALL NOSTUFF TO NO STUFF. PAGE 45: *****2008/12/20*****
- CHANGE ODD CONNECTOR FROM 516S0720 TO 516S0719 - R5156, R5157, R5158 change from 0 to 33 ohm, 5%, 0402(116s0030)
PAGE 6:
- REMOVE ETHERNET CIRCUIT. *****2008/09/27*****
PAGE 8: PAGE 9:
- ADD =PP3V3_S5_P3V3ENETFET LINK TO PP3V3_S5 - ADD STANDOFF 860-0964 X 4
- ADD =PP1V05_ENET_PHY LINK TO PP1V2R1V05_ENET. - ADD STANDOFF 860-0723 X 1
PAGE 9:
- ADD STANDOFF 860-0749 X 1
- ADD =RTL8211_ENSWRE LINK TO GND.
PAGE 29:
- ADD =PP3V3_ENET_PHY_VDDREG LINK TO TP_PP3V3_ENET_PHY_VDDREG. - REMOVE BOMOPTION TABLE OF R2903/R2905/R2909/R2911
- ADD =RTL8211_REGOUT LINK TO NC_RTL8211_REGOUT.
PAGE 66:
- =P3V3ENET_EN_L LINK TO PM_SLP_RMGT_L
- C6601/C6603 CHANGE TO APN 128S0135, and REMOVE BOMOPTION OMIT
- =P1V05ENET_EN LINK TO PM_SLP_RMGT_L
- C6605 CHANGE TO APN 128s0148, HF APN 128s0221, and REMOVE BOMOPTION OMIT
PAGE 10:
PAGE 68:
- CHANGE XDP_TDO_CONN TO XDP_TDO - C6830/C6831 CHANGE TO APN 128S0220, and REMOVE BOMOPTION OMIT
PAGE 13:
PAGE 72:
- XDP FOLLOW M98 DESIGN. CONNECTOR FROM 516S0625 CHANGE TO 998-1571.
- R7272 CHANGE FROM 57.6K 1%(114s0389) TO 75K 1%(114s0399)
PLAGE 23:
- DELETE R2400~R2413 FOR MCP A01 VERSION. *****2008/10/20*****
PAGE 31: PAGE 29:
- REMOVE R3400, R3401 - ADD R2903/R2905 BOMOTION AND CHANGE VALUE TO 200 OHM
- L3401 FROM NO STUFF CHANGE TO STUFF. PAGE 50:
PAGE 39 - REMOVE ALT TABLE
- DELETE R4699. PAGE 74:
- R4690 FROM NO STUFF CHANGE TO STUFF. - REMOVE ALT TABLE
PAGE 94:
PAGE 41: - REMOVE K36 BOM OPTION TABLE AND ALT TABLE
- SMC_NB_DDR_ISENSE CHANGE TO SMC_MCP_DDR_ISENSE
- SMC_NB_CORE_ISENSE CHANGE TO SMC_MCP_CORE_ISENSE *****2008/10/22*****
PAGE 46:
PAGE 12:
- SMC_NB_DDR_ISENSE CHANGE TO SMC_MCP_DDR_ISENSE
- C1200 ~ C1219 CHANGE TO 138S0580
B - SMC_NB_CORE_ISENSE CHANGE TO SMC_MCP_CORE_ISENSE
- R5417 ADD BOM OPTION FOR NO STUFF
- R5416 ADD BOM OPTION FOR NO STUFF
PAGE 28:
- C2870 CHANGE TO 138S0614 B
PAGE 37:
PAGE 50: - ADD R3731 (116s0026 22 ohm 5% 0402) FOR EMI 125MHZ NOISE
- ADD C5926 (10UF,20%.0603) TO =PP3V3_S3_SMS - TP_RTL8211_CLK125 CHANGE TO RTL8211_CLK125
PAGE 63: PAGE 48:
- REMOVE USB_PWR_EN_S3 - C4803 CHANGE TO 138S0614
PAGE 66: PAGE 66:
- REMOVE R9010, R9011 - C6605 CHANGE TO HF APN 128S0221
PAGE 70:
*****2008/08/24*****
- C7040/C7041/C7047 CHANGE TO 138S0614
PAGE 6: PAGE 90:
- R0602 BOMOPTION FROM JTAG_1DEV CHANGE TO NO STUFF. - L9002 CHANGE TO 116S0004(0ohm,5%,0402)
PAGE 13: - C9003 CHANGE TO 116S0004(0ohm,5%,0402)
- XDP FOLLOW M97 DESIGN. CONNECTOR FROM 998-1571 CHANGE TO 516S0625.
PAGE 18: *****2008/10/24*****
- R1860 AND R1861 CHANGE TO PAGE 68.
PAGE 19:
PAGE 25: - R1950/R1951/R1952/1953 CHANGE TO 116s0004 (0 OHM,5%,0402)
- C2504-C2507 FROM 138S0578(402) CHANGE TO 138S0614(402-1) PAGE 28:
- C2516-C2517 FROM 138S0578(402) CHANGE TO 138S0614(402-1) - R2825/R2826 CHANGE TO 116s0004 (0 OHM,5%,0402)
PAG3 35: PAGE 34:
- J3400 516S0635 CHANGE TO HF APN 516S0729
- R4150 FROM 118S0343 (0201) CHANGE TO 116S0056(0402)
PAGE 52:
PAGE 58: - ADD C5250/C5251/C5270/C5271/C5260/C5261/C5280/C5281 131S1104 (22pF,5%,0402) NO STUFF
- C7281, C7241, C7272 FROM 138S0555(603) CHANGE TO 138S0615(603-1) - TEXT "ALS" CHANGE TO "MINI-PCIE"
- C7280, C7240 FROM 128S0092(POLY) CHANGE TO 128S0128(POLY-TANT)
- I2C_ALS_SCL CHANGE TO I2C_MINI_PCIE_SCL
- C7291, C7292, C7252, C7251 FROM 128S0115(POLY,CASE-B2) CHANGE TO
128S0222(POLY,CASE-B2-SM) - I2C_ALS_SDA CHANGE TO I2C_MINI_PCIE_SDA
- Q7260, Q7261 FROM 376S0512 CHANGE TO 376S0652 (H-F) PAGE 67:
PAGE 59: - J6700 514-0604 CHANGE TO HF APN 514-0521
- Q7320 FROM 376S0512 CHANGE TO 376S0652 (H-F) - J6750 514-0603 CHANGE TO HF APN 514-0519
- Q7321 FROM 376S0511 CHANGE TO 376S0651 (H-F) PAGE 69:
- C7321 FROM 128S0111(POLY) CHANGE TO 128S0218 (POLY,CASE-D2E-SM) - J6950 516S0620 CHANGE TO HF APN 516S0735
A - C7343 FROM 128S0073 CHANGE TO 128S0233.
PAGE 60: *****2008/10/25***** SYNC_MASTER=K36B_MLB A
- XW7400 ADD BOMOPTION OMIT. PAGE 52: PAGE TITLE
- Q7400, Q7402 FROM 376S0472 CHANGE TO 376S0617.
PAGE 61:
- STUFF C5250/C5251/C5270/C5271/C5260/C5261/C5280/C5281
Revision History
*****2008/10/28***** DRAWING NUMBER SIZE
- L7500 FROM 152S0869 CHANGE TO 152S0685.
- Q7500 FROM 376S0512 CHANGE TO 376S0652.
PAGE 34:
- J3400 516S0729 CHANGE TO 516S0635
- C7560 FROM 128S0092 CHANGE TO 128S0218. REVISION
PAGE 62: *****2008/10/30*****
R
A.0.0
- Q7620 FROM 376S0512 CHANGE TO 376S0652. PAGE 69: NOTICE OF PROPRIETARY PROPERTY: BRANCH
- C7601 FROM 138S0578 CHANGE TO 138S0614. - J6950 516S0735 CHANGE TO 516S0620
5 OF 109
NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping. <CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
1.05V TO 3.3V LEVEL TRANSLATOR (K36B: ON ICT FIXTURE)
=PP3V3_S0_XDP
13 8
13 12 11 10 8
=PP1V05_S0_CPU To XDP connector
From XDP connector U1000 and/or level translator
JTAG_ALLDEV JTAG_ALLDEV
69 13 10 7 6 XDP_TCK
CPU
1 C0601 1 C0602 IN
XDP_TDI XDP
0.1UF 0.1UF 69 13 10 7 IN
20%
10V
20%
10V 69 13 10 7 6 IN XDP_TMS R0603
2 CERM 2 CERM
XDP_TRST_L XDP_TDO 1
0 2 XDP_TDO_CONN
402 402 69 13 10 7 6 IN 69 10 OUT 7 13
5%
1/16W
MF-LF
402 XDP connector
JTAG_ALLDEV
R06011
10K
5%
1/16W
MF-LF
402 2
11
1 From XDP connector
VCCA VCCB
U0600 or via level translator U1400
C 69 13 10 7 6 XDP_TCK 2
NLSV4T244
A1
UQFN
B1 10 JTAG_MCP_TCK MAKE_BASE=TRUE 7 13 21
MCP XDP
C
NO STUFF 3 A2 B2 9 JTAG_MCP_TDI MAKE_BASE=TRUE 7 13 21
R06021 69 13 10 7 6 XDP_TMS 4 A3 B3 8 JTAG_MCP_TMS MAKE_BASE=TRUE 7 13 21

R0604
JTAG_ALLDEV 0
0 69 13 10 7 6 XDP_TRST_L 5 A4 B4 7 JTAG_MCP_TRST_L 7 13 21 21 JTAG_MCP_TDO 1 2 JTAG_MCP_TDO_CONN OUT 7 13
5% MAKE_BASE=TRUE
1/16W 5%
MF-LF
402 2 JTAG_LVL_TRANS_EN_L 12 OE*
1/16W
MF-LF
402
XDP connector
GND
6
B B
A SYNC_MASTER=K36B_MLB SYNC_DATE=08/17//2008 A
PAGE TITLE
JTAG Scan Chain

DRAWING NUMBER SIZE

REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
6 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Functional Test Points
#J5601 Fan Connectors # J4501 SATA HD System LED and IR #J1300 XDP # J5100 LPC+SPI Connector
TRUE PP3V42_G3H
D I12
I15
TRUE
TRUE
PP5VRT_S0
FAN_RT_PWM
7 8
48
I284
I283
TRUE
TRUE
SATA_HDD_R2D_P
SATA_HDD_R2D_N
38
38
71
71
I199
I198
TRUE
TRUE
XDP_BPM_L<5>
XDP_BPM_L<4>
10 13 69
10 13 69
I227
I228 TRUE PP5VRT_S0

7 8
7 8
D
TRUE FAN_RT_TACH 48 I282 TRUE SATA_HDD_D2R_C_N 38 71
I196 TRUE XDP_BPM_L<3> 10 13 69 I226 TRUE LPC_AD<0> 19 41 43 72
I16
TRUE GND I281 TRUE SATA_HDD_D2R_C_P 38 71
I197 TRUE XDP_BPM_L<2> 10 13 69 I225 TRUE LPC_AD<1> 19 41 43 72
I157
I280 TRUE PP5V_S0_HDD_FLT Need 4 TP 38 TRUE XDP_BPM_L<1> 10 13 69 I224 TRUE SPI_ALT_MOSI 43
#J6950 Battery/Lid Connector TRUE SYS_LED_ANODE_L 38
I195
TRUE XDP_BPM_L<0> 10 13 69 I223 TRUE SPI_ALT_MISO 43
I279 I193
TRUE TRUE LPC_FRAME_L
I285 TRUE SMC_BS_ALRT_L_F 56 I278
IR_RX_OUT 38 40
I194 TRUE TP_XDP_OBSFN_B0 13 I222
PM_CLKRUN_L
19 41 43 72
TRUE SMBUS_BATT_SCL_F 56 I277 TRUE PP5V_S3_IR_CONN 38 TRUE TP_XDP_OBSFN_B1 13 I221 TRUE 19 41 43

I286 I192
GND Need 4 TP TRUE SMC_TMS
I288 TRUE SMBUS_BATT_SDA_F 56 I276 TRUE I191 TRUE TP_XDP_OBSDATA_B0 13 I219 41 42 43
TRUE DEBUG_RESET_L
I287 TRUE PPVBAT_G3H_CONN_F 56
#J3400 Airport I190 TRUE TP_XDP_OBSDATA_B1 13 I220 26 43
TRUE SMC_TDO
I289 TRUE SMC_LID_F 56
I188 TRUE TP_XDP_OBSDATA_B2 13 I217 41 42 43
TRUE TRUE SMC_TRST_L

I291 TRUE GND_SMC_LID_F 56 I274
PCIE_WAKE_L 17 31
I189 TRUE TP_XDP_OBSDATA_B3 13 I218 41 43
TRUE TRUE SMC_MD1

I290 TRUE PP3V42_G3H_LIDSWITCH_F 56 I275
MINI_CLKREQ_L 17 31
I186 TRUE XDP_PWRGD 13 I216
SMC_TX_L
41 43
TRUE GND Need 6 TP I273 TRUE PCIE_CLK100M_MINI_N 17 31 71

TRUE XDP_OBS20 13 I215 TRUE 39 41 42 43
I292 I187
TRUE PCIE_CLK100M_MINI_P PM_LATRIGGER_L TRUE LPC_CLK33M_LPCPLUS 26 43 72
I272 17 31 71
TRUE 13 19 I214
#J6900 MagSafe DC Power Jack I271 TRUE PCIE_MINI_D2R_N 17 31 71
I185
TRUE JTAG_MCP_TCK 6 13 21 I213 TRUE LPC_AD<2> 19 41 43 72
I183
PCIE_MINI_D2R_P TRUE LPC_AD<3>
I294 TRUE PP18V5_DCIN_FUSE Need 2 TP 56 I269 TRUE 17 31 71
I184 TRUE SMBUS_MCP_0_DATA 13 21 44 72 I212 19 41 43 72
PCIE_MINI_R2D_N TRUE SPIROM_USE_MLB

I293 TRUE ADAPTER_SENSE 56 I270 TRUE 31 71
I182 TRUE SMBUS_MCP_0_CLK 13 21 44 72 I211 43
TRUE PCIE_MINI_R2D_P XDP_TCK TRUE SPI_ALT_CLK

I295 TRUE GND Need 2 TP I267 31 71
I181 TRUE 6 10 13 69 I209 43
TRUE PP3V3_WLAN Need 4 TP 31 PPCPUVTT_S0 TRUE SPI_ALT_CS_L

I268 I180 TRUE 7 8 I210 43
#J9000 INVERTER Connector I266 TRUE PP1V5_S0_R Need 3 TP 7 8

I178 TRUE PP3V3_S0 7 8 I207 TRUE LPC_SERIRQ 19 41 43
MINI_RESET TRUE LPC_PWRDWN_L

I297 TRUE PPBUS_ALL_INV_CONN Need 2 TP 66 I264 TRUE 31
I179 TRUE JTAG_MCP_TDO_CONN 6 13 I208 19 41 43
PP3V3_S3_AIRPORT_CONN TRUE SMC_TDI

I296 TRUE INV_GND 66 I265 TRUE 31 I177 TRUE JTAG_MCP_TRST_L 6 13 21 I206 41 42 43
TRUE I2C_MINI_PCIE_SCL TRUE SMC_TCK

I298 TRUE PP5V_INV_F 66 I263 31 44 I175 TRUE MCP_DEBUG<0> 13 19 72 I203 41 42 43
TRUE I2C_MINI_PCIE_SDA TRUE MCP_DEBUG<1> TRUE SMC_RESET_L

I299 TRUE INV_BKLIGHT_PWM_L Need 4 TP 66 I262 31 44
I176 13 19 72 I204 41 42 43
TRUE USB2_AIRPORT_N TRUE SMC_NMI

I261 31 72
I173 TRUE MCP_DEBUG<2> 13 19 72 I205 41 43
#J9001 LCD + CAMERA CONNECTOR I259 TRUE USB2_AIRPORT_P 31 72 TRUE MCP_DEBUG<3> 13 19 72 I202 TRUE SMC_RX_L 39 41 42 43
C I300 TRUE PP3V3_LCDVDD_SW_F 66 I260 TRUE GND Need 6 TP

I174
I172 TRUE JTAG_MCP_TDI

JTAG_MCP_TMS
6 13 21 I201 TRUE
TRUE
LPCPLUS_GPIO
GND Need 2 TP
18 43 C
I301 TRUE PP3V3_S0_LCD_F 66 I171 TRUE 6 13 21 I200
TRUE LVDS_IG_DDC_CLK 18 66
# Other Func Test Points TRUE MCP_DEBUG<4> 13 19 72
I303 I170
I302 TRUE LVDS_IG_DDC_DATA 18 66 I258 TRUE ALL_SYS_PWRGD 26 41 64 I169 TRUE MCP_DEBUG<5> 13 19 72
I305 TRUE LVDS_IG_A_DATA_N<0> 18 66 71 I256 TRUE PPVCORE_S0_CPU 8 I168 TRUE MCP_DEBUG<6> 13 19 72
I304 TRUE LVDS_IG_A_DATA_P<0> 18 66 71 I257 TRUE PPCPUVTT_S0 7 8 I167 TRUE MCP_DEBUG<7> 13 19 72
I306 TRUE LVDS_IG_A_DATA_N<1> 18 66 71 I255 TRUE PPVCORE_S0_MCP_R 8 I165 TRUE FSB_CLK_ITP_P 13 14 69
I307 TRUE LVDS_IG_A_DATA_P<1> 18 66 71 I254 TRUE PPVCORE_S0_MCP 8 I166 TRUE FSB_CLK_ITP_N 13 14 69
TRUE LVDS_IG_A_DATA_N<2> 18 66 71 I253 TRUE PP0V9_S0 8 I163 TRUE XDP_CPURST_L 13 69

I308
I309 TRUE LVDS_IG_A_DATA_P<2> 18 66 71 I252 TRUE PP1V05_S0 7 8 I164 TRUE XDP_DBRESET_L 10 13 26
I310 TRUE LVDS_IG_A_CLK_F_N 66 I251 TRUE PP1V5_S0_R 7 8 I162 TRUE XDP_TDO_CONN 6 13
TRUE LVDS_IG_A_CLK_F_P 66 I250 TRUE PP1V8_S0 8 TRUE XDP_TRST_L 6 10 13 69

I311 I161
I313 TRUE USB2_CAMERA_CONN_P 66 72 I248 TRUE PP1V8_S0_R 8

I160 TRUE XDP_TDI 6 10 13 69
I312 TRUE USB2_CAMERA_CONN_N 66 72 I249 TRUE PP1V05_S0_MCP_PEX_AVDD 8 24

I159 TRUE XDP_TMS 6 10 13 69
I315 TRUE PP5V_S3_CAMERA_F 66 I246 TRUE PP1V05_S0 7 8

I158 TRUE GND Need 8 TP
I314 TRUE GND I247 TRUE PP1V05_S0_MCP_SATA_AVDD 8 24
I245 TRUE PP1V05_S0 7 8
# J6701 MIC CONNECTOR I244 TRUE PP5VRT_S0 7 8
I316 TRUE MIC_LO_CONN 54 I243 TRUE PP3V3_S0 7 8
I317 TRUE MIC_HI_CONN 54 I242 TRUE PP1V0_FW 8
I318 TRUE MIC_SHLD_CONN 54 55 I240 TRUE PP1V8_S3 8
I241 TRUE PP3V3_S3 8

#J6702 Left SPEAKER CONNECTOR I238 TRUE PP5VLT_S3 8
TRUE SPKRCONN_L_P_OUT 53 54 I239 TRUE PPVTT_S3_DDR_BUF 8

I319
I320 TRUE SPKRCONN_L_N_OUT 53 54 I237 TRUE PP1V05_S5_REG 8
I235 TRUE PP3V3_S5 8

#J6703 Right SUB SPEAKER CONNECTOR TRUE PP3V42_G3H
B I321 TRUE SPKRCONN_SUB_P_OUT 53 54
I236
I234 TRUE PP18V5_G3H

7 8
8
B
I322 TRUE SPKRCONN_SUB_N_OUT 53 54 I233 TRUE PPBUS_G3H 8
TRUE SPKRCONN_R_P_OUT 53 54 I232 TRUE PPBUS_G3H_CPU_ISNS 8

I323
SPKRCONN_R_N_OUT TRUE PP3V3_ENET_PHY
I324 TRUE 53 54 I230 8
I231 TRUE PP1V2R1V05_ENET 8

# J5800 GEYSER AND DIMM0 REMOTE TEMP SENSORS I229 TRUE PPVP_FW 8
I326 TRUE TPAD_GND_F 49
I325 TRUE CONN_TPAD_ONOFF_FLTR_L 49
I328 TRUE CONN_TPAD_USB_P 49 72
I327 TRUE CONN_TPAD_USB_N 49 72
I329 TRUE SMC_LID_LC 49
I330 TRUE PP5V_S3_TPAD_F 49
#J5520 CPU/MCP Thermal Sensor

I331 TRUE CPUTHMSNS_D2_P 47
I332 TRUE CPUTHMSNS_D2_N 47
I334 TRUE MCPTHMSNS_D2_P 47
I333 TRUE MCPTHMSNS_D2_N 47
#J4810 BLUETOOTH
I335 TRUE PP3V3_S3_BT_F_CONN 40
I336 TRUE USB2_BT_F_N_CONN 40 72
I337 TRUE USB2_BT_F_P_CONN 40 72
I338 TRUE GND_BT_F_CONN 40
A TRUE
#J4500 SATA ODD
SATA_ODD_R2D_UF_P 38 71
I340 PAGE TITLE
I339
I342
TRUE
TRUE
SATA_ODD_R2D_UF_N
SATA_ODD_D2R_C_N
38 71
38 71
FUNC TEST
DRAWING NUMBER SIZE
TRUE SATA_ODD_D2R_C_P 38 71
I341
TRUE PP3V3_S0 Need 4 TP 7 8 Apple Inc. 051-8089 D

I343
REVISION
TRUE SMC_ODD_DETECT
I345
GND
38 41 R
A.0.0
I344 TRUE Need 6 TP
7 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
"S0,S0M" RAILS "S3" RAILS 56 =PP3V42_G3H_REG

"G3H" RAILSPP3V42_G3H 7
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=3.42V
58 =PP5VRT_S0_REG PP5VRT_S0 7 59 =PP1V8_S3_REG PP1V8_S3 7 MAKE_BASE=TRUE
60 =PPVCORE_S0_CPU_REG PPVCORE_S0_CPU 7 MIN_LINE_WIDTH=0.30 MM MIN_LINE_WIDTH=1.5 mm
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.25 mm =PPVIN_S5_SMCVREF 42
(CPU VCORE PWR) MIN_NECK_WIDTH=0.3 MM VOLTAGE=5V VOLTAGE=1.8V
=PP3V42_G3H_SMBUS_SMC_BSA
VOLTAGE=0.9V MAKE_BASE=TRUE MAKE_BASE=TRUE 44
MAKE_BASE=TRUE
=PP5V_S0_HDD 38 =PP3V42_G3H_PWRCTL 64
=PPVCORE_S0_CPU 11 12
=PP5V_S0_LPCPLUS 43 =PP1V8_S3_P1V8S0FET 65 =PP3V42_G3H_CHGR 57
=PPVCORE_S0_CPU_VSENSE 45
D
=PP5V_S0_FAN_RT
=PP5V_S0_CPU_IMVP
48
60
=PP1V8_S3_MEM 28 29
=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_LIDSWITCH
39
56
D
=PP5V_S0_ODD 38 =PP3V42_G3H_BMON_ISNS 46
65 21 =PP3V3_S3_FET PP3V3_S3 7
65 62 =PPCPUVTT_S0_REG PPCPUVTT_S0 7 =PP5V_S0_TMDS 68 MIN_LINE_WIDTH=0.6 mm =PP3V3_S5_SMC 41 42 50
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 MM =PP5V_S0_LCD 66 VOLTAGE=3.3V =PP3V3_S5_LPCPLUS 43
VOLTAGE=1.05V MAKE_BASE=TRUE
MAKE_BASE=TRUE =PP5V_S0_CPUVTTS0 62 =PP3V42_G3H_RTC_D 26
=PP3V3_S3_SMBUS_SMC_A_S3 44
=PP1V05_S0_CPU 6 10 11 12 13 =PP5V_S0_AUDIO 52 55
=PP3V3_S3_PDCISENS 59
=PP1V05_S0_MCP_FSB 14 22 24 =PP5V_S0_AUDIO_AMP 53
=PP3V3_S3_SMBUS_SMC_MGMT 44
=PP1V05_S0_SMC_LS 42 56 =PP18V5_DCIN_CONN PP18V5_G3H 7
=PP3V3_S3_VREFMRGN 27 MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.3 MM
=PP3V3_S3_WLAN 31 VOLTAGE=18.5V
MAKE_BASE=TRUE
=PP3V3_S3_AIRPORT_AUX 31
=PP18V5_G3H_CHGR 57
=PP3V3_S3_BT 40
=PP3V3_S3_SMS 50
57 =PPBUS_G3H PPBUS_G3H 7
VOLTAGE=12.6V
MAKE_BASE=TRUE
61 =PPMCPCORE_S0_REG PPVCORE_S0_MCP_R 7
MIN_LINE_WIDTH=0.6 MM
46 =PPVCORE_S0_MCP_REG_R MIN_NECK_WIDTH=0.2 MM
=PPVIN_S0_MCPCORES0
VOLTAGE=1.05V 61
(MCP VCORE REG. OUTPUT) MAKE_BASE=TRUE =PPVIN_S0_MCPREG_VIN 61
=PPVCORE_S0_MCP_VSENSE 45
=PPVIN_S5_1V8S3_0V9S0 59
=PPVIN_S5_3V3S5 58
65 63 =PP3V3_S0_FET PP3V3_S0 7 =PPVIN_S0_5VRTS0 58

MIN_LINE_WIDTH=0.30MM =PPVIN_S3_5VLTS3
MIN_NECK_WIDTH=0.20MM 61
VOLTAGE=3.3V =PPBUS_G3HRS5
24 22 =PPVCORE_S0_MCP PPVCORE_S0_MCP 7 MAKE_BASE=TRUE 45
61 46 MIN_LINE_WIDTH=0.6 MM 61 =PP5VLT_S3_REG PP5VLT_S3 7
(MCP VCORE AFTER SENSE RES) MIN_NECK_WIDTH=0.2 MM =PP3V3_S0_XDP 6 13 MIN_LINE_WIDTH=0.6 MM =PPBUS_S5_INV 66
VOLTAGE=1.05V MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE =PP3V3_S0_MCP 21 22 24 VOLTAGE=5V =PPBUS_S5_FWPWRSW 36
MAKE_BASE=TRUE
=PP3V3_S0_MCP_DAC_UF 25 =PPBUS_G3H_CPU_ISNS_R 46
C 59 =PP0V9_S0_REG PP0V9_S0 7
=PP3V3_S0_MCP_VPLL_UF
=PP3V3_S0_ODD
25
38
=PP5V_S3_EXTUSB 39
C
MIN_LINE_WIDTH=0.4 mm =PP5V_S3_IR 38 40
MIN_NECK_WIDTH=0.2 mm =PP3V3_S0_LPCPLUS
VOLTAGE=0.9V =PP5V_S3_CAMERA 66
MAKE_BASE=TRUE =PP3V3_S0_SMBUS_SMC_0_S0 44
=PP5V_S3_VTTCLAMP 65 46 =PPBUS_G3H_CPU_ISNS PPBUS_G3H_CPU_ISNS 7
=PPVTT_S0_VTTCLAMP 65 =PP3V3_S0_SMBUS_SMC_B_S0 44 MIN_LINE_WIDTH=0.6MM
=PP5V_S3_MCPDDRFET 65 MIN_NECK_WIDTH=0.3MM
=PP3V3_S0_SMBUS_MCP_0 44 VOLTAGE=12.6V
=PP0V9_S3M_MEM_TERM 30 =PP5V_S3_SYSLED 42 MAKE_BASE=TRUE
=PP3V3_S0_FAN_RT 48
=PPVIN_S0_CPUVTTS0
=PP5V_S3_TPAD 49 62
=PP3V3_S0_AUDIO 52 54 55
=PP5V_S3_1V8S3_0V9S0 59 =PPVIN_S5_CPU_IMVP 60
=PP3V3_S0_IMVP 60
=PP5V_S3_AUDIO
65 =PP1V05_S0_FET PP1V05_S0 7 =PP3V3_S0_TMDS 68
=PP5V_S3_AUDIO_AMP
MIN_NECK_WIDTH=0.2 MM =PP3V3_S0_LCD 66
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V05_S0_MCP_PEX_DVDD 8 24
=PP3V3_S0_MCP_GPIO
=PP3V3_S0_HDCPROM
18 19 21
25
"ENET" RAILS
=PP1V05_S0_MCP_AVDD_UF 24 =PP3V3_S0_MCP_PLL_UF 24
=PP3V3_ENET_FET PP3V3_ENET_PHY
33 7
=PP1V05_S0_MCP_PLL_UF 24 =PP3V3R1V5_S0_MCP_HDA 21 24 MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
=PP1V05_S0_MCP_SATA_DVDD =PP3V3_S0_SMC VOLTAGE=3.3V
8 24 42 MAKE_BASE=TRUE
=PP1V05_S0_MCP_HDMI_VDD 18 25 =PP3V3_S0_MCPTHMSNS 47 =PP3V3_ENET_MCP_RMGT 18 24
=PP1V05_S0_VMON 64 =PP3V3_S0_CPUTHMSNS 47
59 27 =PPVTT_S3_DDR_BUF PPVTT_S3_DDR_BUF 7 =PP3V3_ENET_PHY 32
=PP5VR3V3_S0_MCPCOREISNS 46 MIN_LINE_WIDTH=0.3 MM
=PPSPD_S0_MEM 28 29 VOLTAGE=0.9V =PP1V05_ENET_FET PP1V2R1V05_ENET
63 =PP1V5_S0_FET PP1V5_S0_R 7
=PP3V3_S0_PWRCTL MAKE_BASE=TRUE 33 7
MIN_LINE_WIDTH=0.5 mm 64 MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V =PP3V3_S0_VMON 64 VOLTAGE=1.05V
MAKE_BASE=TRUE MAKE_BASE=TRUE
=PP3V3_S0_MCPDDRISNS 46
=PP1V5_S0_CPU
=PP1V5_S0_AIRPORT
11 12
31
=PP3V3_S0_CPUVTTISNS
=PP3V3_FW_P1V0FW
46
63
"S5" RAILS =PP1V05_ENET_MCP_PLL_MAC
=PP1V05_ENET_MCP_RMGT 18 24
24
=PP3V3_FW_PHY 37 =PP1V05_ENET_PHY 32
B 46 =PP1V8_S0
(DDR PWR AFTER SENSE RES.)
PP1V8_S0
7 =PP3V3_FW_FWPHY 35 37
63 =PP1V05_S5_REG PP1V05_S5_REG
7 B
VOLTAGE=1.8V MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP1V8R1V5_S0_MCP_MEM 16 24 36 =PPBUS_S5_FW_FET PPVP_FW 7
=PP1V05_S5_MCP_VDD_AUXC 22 24 VOLTAGE=12.6V MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE MIN_LINK_WIDTH=0.4 MM
=PP1V05_ENET_P1V05ENETFET 33 =PPVP_FW_PHY_CPS_FET 37
=PP1V8_S0_FET PP1V8_S0_R =PPVP_FW_PORT1 37

65 7
(DDR PWR REG. OUTPUT) MIN_NECK_WIDTH=0.2MM
VOLTAGE=1.8V
MAKE_BASE=TRUE
=PP1V8_S0_VMON 64
=PP1V8_S0_FET_R 46 58 =PP3V3_S5_REG PP3V3_S5 7

MIN_LINE_WIDTH=1.5 mm
=PP3V3R1V8_S0_MCP_IFP_VDD 18 25 MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE
"FW" RAILS =PP3V3_S5_MCP_GPIO
=PP3V3_S5_ROM
18 20
43 51
=PP3V3_S5_LCD 66
63 =PP1V0_FW_REG PP1V0_FW 7 =PP3V3_S5_MCP 22 24

MIN_NECK_WIDTH=0.2MM =PP3V3_S5_MCPPWRGD 26
VOLTAGE=1.0V
MAKE_BASE=TRUE =PP3V3_S5_AIRPORT_AUX
PEX & SATA AVDD/DVDD aliases =PP1V0_FW_FWPHY 35 =PP3V3_S5_P3V3ENETFET
=PP3V3_S5_PWRCTL
33
64
=PP1V05_S0_MCP_PEX_AVDD0 17 =PP3V3_S5_P1V05ENETFET 33
206 mA (A01)
24 7 PP1V05_S0_MCP_PEX_AVDD =PP1V05_S0_MCP_PEX_AVDD1 17 =PP3V3_S5_P3V3S3FET 65
MAKE_BASE=TRUE
=PP3V3_S5_P3V3S0FET 65
206 mA (A01)
=PP1V05_S0_MCP_PEX_DVDD0 17 =PP3V3_S5_P1V05S5 63
57 mA (A01) =PP3V3_FW_LATEVG
24 8 =PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_PEX_DVDD1 17 36 37
A 206 mA (A01)
SYNC_MASTER=K36B_MLB A
24 7 PP1V05_S0_MCP_SATA_AVDD =PP1V05_S0_MCP_SATA_AVDD0 20
PAGE TITLE
MAKE_BASE=TRUE
127 mA (A01)
=PP1V05_S0_MCP_SATA_AVDD1 20
127 mA (A01)
Power Aliases
DRAWING NUMBER SIZE
24 8 =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_SATA_DVDD0 20
43 mA (A01) Apple Inc. 051-8089 D
127 mA (A01) =PP1V05_S0_MCP_SATA_DVDD1 20 REVISION
R
A.0.0
8 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU FSB FREQUENCY STRAPS

PCI-E ALIASES LVDS ALIASES UNUSED EXPRESS CARD LANE BSEL<2..0> FSB MHZ
UNUSED GPU LANES UNUSED LVDS SIGNALS
0 0 0 266
17 =PEG_D2R_N<15:0> NC_PEG_D2R_N<15:0> 71 18 LVDS_IG_A_DATA_P<3> NC_LVDS_IG_A_DATA_P3 0 0 1 133
NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE 71 17 PCIE_EXCARD_D2R_P TP_PCIE_EXCARD_D2RP 69 10 IN CPU_BSEL<0:2> =MCP_BSEL<0:2> OUT 14 0 1 0 200
MAKE_BASE=TRUE MAKE_BASE=TRUE 0 1 1 (166)
17 =PEG_D2R_P<15:0> NC_PEG_D2R_P<15:0> 71 18 LVDS_IG_A_DATA_N<3> NC_LVDS_IG_A_DATA_N3 71 17 PCIE_EXCARD_D2R_N TP_PCIE_EXCARD_D2RN 1 0 0 333
NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE
MAKE_BASE=TRUE
1 0 1 100
1 1 0 (400)
17 =PEG_R2D_C_N<15:0> NC_PEG_R2D_C_N<15:0> 71 18 LVDS_IG_B_CLK_P NC_LVDS_IG_B_CLKP 71 17 PCIE_EXCARD_R2D_C_P TP_PCIE_EXCARD_R2D_CP 1 1 1 (RSVD)
NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
17 =PEG_R2D_C_P<15:0> NC_PEG_R2D_C_P<15:0> 71 18 LVDS_IG_B_CLK_N NC_LVDS_IG_B_CLKN 71 17 PCIE_EXCARD_R2D_C_N TP_PCIE_EXCARD_R2D_CN
NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
17 PCIE_EXCARD_PRSNT_L TP_PCIE_EXCARD_PRSNT_L
17 PEG_PRSNT_L TP_PEG_PRSNT_L 71 18 LVDS_IG_B_DATA_P<3:0> NC_LVDS_IG_B_DATA_P<3:0> MAKE_BASE=TRUE
MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE EXCARD_CLKREQ_L TP_EXCARD_CLKREQ_L
D 17 PEG_CLKREQ_L TP_PEG_CLKREQ_L
MAKE_BASE=TRUE
71 18 LVDS_IG_B_DATA_N<3:0> NC_LVDS_IG_B_DATA_N<3:0>
NO_TEST=TRUE MAKE_BASE=TRUE
17
71 17 PCIE_CLK100M_EXCARD_P
MAKE_BASE=TRUE
TP_PCIE_CLK100M_EXCARDP
MAKE_BASE=TRUE
D
PEG_CLK100M_P TP_PEG_CLK100MP 71 17 PCIE_CLK100M_EXCARD_N TP_PCIE_CLK100M_EXCARDN
71 17
MAKE_BASE=TRUE MAKE_BASE=TRUE
HDA PULL-DOWN
71 17 PEG_CLK100M_N TP_PEG_CLK100MN
MAKE_BASE=TRUE MISC NC MCP79 ALIASES
17 EXTGPU_PWR_EN TP_EXTGPU_PWR_EN AUD_IPHS_SWITCH_EN
MAKE_BASE=TRUE 19
17 EXTGPU_RESET_L TP_EXTGPU_RESET_L 14 CPU_PECI_MCP TP_CPU_PECI_MCP USB ALIASES

MAKE_BASE=TRUE
GMUX_JTAG_TDI TP_GMUX_JTAG_TDI
MAKE_BASE=TRUE
UNUSED USB PORTS R0977
1
19
MAKE_BASE=TRUE
USB_EXTC_P TP_USB_EXTCP
20K
5%
19 GMUX_JTAG_TMS TP_GMUX_JTAG_TMS 72 20
MAKE_BASE=TRUE 1/16W
MAKE_BASE=TRUE USB_EXTC_N TP_USB_EXTCN
ETHERNET ALIASES 16 MCP_MEM_RESET_L TP_MCP_MEM_RESET_L
MAKE_BASE=TRUE
72 20
72 20 USB_EXTD_P TP_USB_EXTDP MAKE_BASE=TRUE

MF-LF
2 402
MAKE_BASE=TRUE
72 20 USB_EXTD_N TP_USB_EXTDN
33 =P3V3ENET_EN PM_SLP_RMGT_L 21
SO-DIMM ALIASES 72 20 USB_EXCARD_P TP_USB_EXCARDP MAKE_BASE=TRUE
MAKE_BASE=TRUE LAN ALIASES
MAKE_BASE=TRUE UNUSED ADDRESS PINS 72 20 USB_EXCARD_N TP_USB_EXCARDN
33 =P1V05ENET_EN MAKE_BASE=TRUE 18 MCP_MII_RXER
31 =USB_MINI_P USB_MINI_P 20 72
32 =PP3V3_ENET_PHY_VDDREG PP3V3_ENET_PHY_VDDREG 28 MEM_A_A<15> TP_MEM_A_A15 MAKE_BASE=TRUE 18 MCP_MII_COL 1
MAKE_BASE=TRUE 31 =USB_MINI_N USB_MINI_N 20 72 R0930
=RTL8211_REGOUT NC_RTL8211_REGOUT
MAKE_BASE=TRUE 29 MEM_B_A<15> TP_MEM_B_A15 MAKE_BASE=TRUE 18 MCP_MII_CRS
32
MAKE_BASE=TRUE
MAKE_BASE=TRUE 1
47K
1 R0931 5%
32 =RTL8211_ENSWREG R0932 1/16W
47K MF-LF
47K 5% 2 402
5% 1/16W
1/16W MF-LF
MF-LF 2 402
TRACKPAD(WELLSPRING) 2 402
49 =USB2_TPAD_P USB_TPAD_P 20 72
MAKE_BASE=TRUE
49 =USB2_TPAD_N USB_TPAD_N 20 72
MAKE_BASE=TRUE
BLUETOOTH DP HOTPLUG PULL-DOWN

18 DP_HOTPLUG_DET
=USB2_BT_P USB_BT_P
C 40
40 =USB2_BT_N
MAKE_BASE=TRUE
USB_BT_N
MAKE_BASE=TRUE
20 72
20 72 1
R0940 C
20K
5%
1/16W
MF-LF
2 402
CPU HEATSINK STANDOFF SCREW HOLE FW PULL-DOWN

Screw Holes Z0903
OMIT
Z0904
OMIT 17 PCIE_FW_PRSNT_L
STDOFF-4.2OD3.95H-5.52R3.37-6B STDOFF-4.2OD3.95H-5.52R3.37-7SQB 1
1 1 R0955
0
BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GND 5%
1/16W
MF-LF
Z0906 OMIT Z0903 USE SAME Z0913 NON SHAPE OF A HOOF SYMBOL 2 402
5R2P3-7SQBNP FOR LAYOUT PLACEMENT

1 BUT, NEED CHANGE TO HIGH STANDOFF SYMBOL
OMIT OMIT
=GND_BATT_CHGND Z0921 MCP_SAFE_MODE SIGNAL TO SUPPORT
SATA,LVDS CONNECTOR CHASSIS GND
56
=GND_CHASSIS_AUDIO_JACK
Z0905 STDOFF-4.5OD3.95H-1.1-3.2-TH
54
STDOFF-4.5OD3.95H-1.1-3.2-TH ROM FAILURE OVERRIDE
28 =GND_CHASSIS_DIPDIMM_LEFT 1
OMIT 1
R0920
55 =GND_CHASSIS_AUDIO_MIC
Z0907 66 =GND_CHASSIS_LVDS
0
6P5R2P6-7SQB 21 MCP_SPKR 1 2 SMC_MCP_SAFE_MODE IN 41
1 29 28 =GND_CHASSIS_DIPDIMM_CENTER 5%
1/16W
29 =GND_CHASSIS_DIPDIMM_RIGHT MF-LF
34 =GND_CHASSIS_RJ45 402
68 =GND_CHASSIS_TMDS_UPPER MCP_TV_DAC_RSET 18 71
DIP DIMM CONNECTOR CHASSIS GND 37 =GND_CHASSIS_FW_UPPER MCP_TV_DAC_VREF 18 71
OMIT R09411
B Z0910
5R2P3-7SQB
68 =GND_CHASSIS_TMDS_DOWN
37 =GND_CHASSIS_FW_DOWN 124
1%
1 C0940
0.01UF
B
OMIT OMIT 1/16W
10%
1
Z0901 Z0912
MF-LF
402
2
16V
2 CERM
5R2P3-7SQBNP 402
1 STDOFF-4.2OD2.15H-1.2-3.2-TH
DIP DIMM CONNECTOR CHASSIS GND 1
OMIT
Z0909
5R2P3-7SQB
1
55 54 53 52 =GND_AUDIO_CODEC GND_AUDIO_CODEC 1 2
MAKE_BASE=TRUE
DCIN CONNECTOR CHASSIS GND OMIT XW0901
OMIT OMIT Z0913 SM
Z0902 Z0911
5R2P3-7B STDOFF-4.2OD3.95H-5.52R3.37-6B 53 =GND_AUDIO_AMP GND_AUDIO_AMP
MAKE_BASE=TRUE
1 2
7X7R2P3-5B
1 1 1 XW0902
SM
I/O CONNECTOR CHASSIS GND

OMIT
Z0908
5P0R2P3-7BLB
1
(EMI PAD FOR INVERTER GONNECTOR)
A TABLE_5_HEAD
SYNC_MASTER=K36B_MLB A
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION ZS0920 PAGE TITLE
860-0964 4 THERMAL STANDOFF Z0903,Z0904,Z0905,Z0921 ? STANDOFF

TABLE_5_ITEM
66 INVT_CHGND 1 EMI-SPRING
CLIP-SM-M42 SIGNAL ALIAS
TABLE_5_ITEM
DRAWING NUMBER SIZE
860-0723 1 STANDOFF WIRELESS Z0912 ? STANDOFF
TABLE_5_ITEM
REVISION
860-0749 1 STANDOFF W/THRU HOLES,WIRELESS Z0913 ? STANDOFF R
A.0.0
9 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
69 14 BI FSB_A_L<3> J4 A3* U1000 ADS* H1 FSB_ADS_L BI 14 69
69 14 BI FSB_A_L<4> L5 A4* PENRYN BNR* E2 FSB_BNR_L BI 14 69
FSB_A_L<5> L4 FCBGA G5 FSB_BPRI_L

69 14 BI A5* BPRI* BI 14 69
1 OF 4 =PP1V05_S0_CPU 6 8 11 12 13
69 14 BI FSB_A_L<6> K5 A6*
69 14 BI FSB_A_L<7> M3 A7* DEFER* H5 FSB_DEFER_L BI 14 69
69 14 BI FSB_A_L<8> N2 A8* DRDY* F21 FSB_DRDY_L BI 14 69
69 14 BI FSB_A_L<9> J1 A9* DBSY* E1 FSB_DBSY_L BI 14 69

R10001
54.9
69 14 BI FSB_A_L<10> N3 A10* 1%
ADDR GROUP0
1/16W
69 14 BI FSB_A_L<11> P5 A11* BR0* F1 FSB_BREQ0_L BI 14 69 MF-LF
402 2
CONTROL
69 14 BI FSB_A_L<12> P2 A12*
D 69 14
69 14
BI
BI
FSB_A_L<13>
FSB_A_L<14>
L2
P4
A13*
A14*
IERR*
INIT*
D20
B3
69 CPU_IERR_L
CPU_INIT_L IN 14 69
D
69 14 BI FSB_A_L<15> P1 A15*
69 14 BI FSB_A_L<16> R1 A16* LOCK* H4 FSB_LOCK_L BI 14 69
69 14 BI FSB_ADSTB_L<0> M1 ADSTB0*
RESET* C1 FSB_CPURST_L IN 13 14 69
69 14 BI FSB_REQ_L<0> K3 REQ0* RS0* F3 FSB_RS_L<0> IN 14 69
69 14 BI FSB_REQ_L<1> H2 REQ1* RS1* F4 FSB_RS_L<1> IN 14 69
69 14 BI FSB_REQ_L<2> K2 REQ2* RS2* G3 FSB_RS_L<2> IN 14 69
69 14 BI FSB_REQ_L<3> J3 REQ3* TRDY* G2 FSB_TRDY_L IN 14 69
69 14 BI FSB_REQ_L<4> L1 REQ4*
HIT* G6 FSB_HIT_L BI 14 69
69 14 BI FSB_A_L<17> Y2 A17* HITM* E4 FSB_HITM_L BI 14 69 OMIT

69 14 BI FSB_A_L<18> U5 A18* 69 14 BI FSB_D_L<0> E22 D0* U1000 D32* Y22 FSB_D_L<32> BI 14 69
69 14 BI FSB_A_L<19> R3 A19* BPM0* AD4 XDP_BPM_L<0> BI 7 13 69

1 69 14 BI FSB_D_L<1> F24 D1* PENRYN D33* AB24 FSB_D_L<33> BI 14 69
69 14 FSB_A_L<20> W6 A20* BPM1* AD3 XDP_BPM_L<1> 7 13 69

R1001 69 14 FSB_D_L<2> E26 D2* FCBGA D34* V24 FSB_D_L<34> 14 69
BI BI 54.9 BI BI
FSB_A_L<21> U4
XDP/ITP SIGNALS AD1 XDP_BPM_L<2> FSB_D_L<3> V26 FSB_D_L<35>
69 14 BI A21* BPM2* BI 7 13 69 1% 69 14 BI G22 D3* 2 OF 4 D35* BI 14 69
ADDR GROUP1
1/16W
69 14 BI FSB_A_L<22> Y5 A22* BPM3* AC4 XDP_BPM_L<3> BI 7 13 69 MF-LF 69 14 BI FSB_D_L<4> F23 D4* D36* V23 FSB_D_L<36> BI 14 69
402 2
69 14 BI FSB_A_L<23> U1 A23* PRDY* AC2 XDP_BPM_L<4> BI 7 13 69 69 14 BI FSB_D_L<5> G25 D5* D37* T22 FSB_D_L<37> BI 14 69
69 14 BI FSB_A_L<24> R4 A24* PREQ* AC1 XDP_BPM_L<5> BI 7 13 69 69 14 BI FSB_D_L<6> E25 D6* D38* U25 FSB_D_L<38> BI 14 69
69 14 BI FSB_A_L<25> T5 A25* TCK AC5 XDP_TCK IN 6 7 10 13 69 69 14 BI FSB_D_L<7> E23 D7* D39* U23 FSB_D_L<39> BI 14 69
69 14 BI FSB_A_L<26> T3 A26* TDI AA6 XDP_TDI IN 6 7 10 13 69 69 14 BI FSB_D_L<8> K24 D8* D40* Y25 FSB_D_L<40> BI 14 69
69 14 BI FSB_A_L<27> W2 A27* TDO AB3 XDP_TDO OUT 6 10 69 69 14 BI FSB_D_L<9> G24 D9* D41* W22 FSB_D_L<41> BI 14 69
DATA GRP 0
DATA GRP 2
69 14 BI FSB_A_L<28> W5 A28* TMS AB5 XDP_TMS IN 6 7 10 13 69 69 14 BI FSB_D_L<10> J24 D10* D42* Y23 FSB_D_L<42> BI 14 69
69 14 BI FSB_A_L<29> Y4 A29* TRST* AB6 XDP_TRST_L IN 6 7 10 13 69 69 14 BI FSB_D_L<11> J23 D11* D43* W24 FSB_D_L<43> BI 14 69
69 14 BI FSB_A_L<30> U2 A30* DBR* C20 XDP_DBRESET_L OUT 7 13 26 69 14 BI FSB_D_L<12> H22 D12* D44* W25 FSB_D_L<44> BI 14 69
1
C 69 14 BI FSB_A_L<31>
FSB_A_L<32>
V4
W3
A31* R1002
68
69 14 BI FSB_D_L<13>
FSB_D_L<14>
F26 D13* D45* AA23
AA24
FSB_D_L<45>
FSB_D_L<46>
BI 14 69 C
69 14 BI A32* 5% 69 14 BI K22 D14* D46* BI 14 69
1/16W
69 14 FSB_A_L<33> AA4 A33* THERMAL MF-LF 69 14 FSB_D_L<15> H23 D15* D47* AB25 FSB_D_L<47> 14 69
BI BI BI
402 2
69 14 BI FSB_A_L<34> AB2 A34* 69 14 BI FSB_DSTB_L_N<0> J26 DSTBN0* DSTBN2* Y26 FSB_DSTB_L_N<2> BI 14 69
69 14 BI FSB_A_L<35> AA3 A35* PROCHOT* D21 CPU_PROCHOT_L OUT 14 42 60 69 69 14 BI FSB_DSTB_L_P<0> H26 DSTBP0* DSTBP2* AA26 FSB_DSTB_L_P<2> BI 14 69
69 14 BI FSB_ADSTB_L<1> V1 ADSTB1* THERMDA A24 CPU_THERMD_P OUT 47 69 14 BI FSB_DINV_L<0> H25 DINV0* DINV2* U22 FSB_DINV_L<2> BI 14 69
THERMDC B25 CPU_THERMD_N OUT 47
69 14 IN CPU_A20M_L A6 A20M*
OUT CPU_FERR_L PM_THRMTRIP_L FSB_D_L<16> FSB_D_L<48>
69 14 A5 FERR* THERMTRIP* C7 14 42 69 69 14 N22 D16* D48* AE24 14 69
OUT BI BI
69 14 IN CPU_IGNNE_L C4 IGNNE* 69 14 BI FSB_D_L<17> K25 D17* D49* AD24 FSB_D_L<49> BI 14 69
ICH
69 14 BI FSB_D_L<18> P26 D18* D50* AA21 FSB_D_L<50> BI 14 69

H CLK
69 14 IN CPU_STPCLK_L D5 STPCLK* 69 14 BI FSB_D_L<19> R23 D19* D51* AB22 FSB_D_L<51> BI 14 69
69 14 IN CPU_INTR C6 LINT0 69 14 BI FSB_D_L<20> L23 D20* D52* AB21 FSB_D_L<52> BI 14 69
69 14 IN CPU_NMI B4 LINT1 BCLK0 A22 FSB_CLK_CPU_P IN 14 69 69 14 BI FSB_D_L<21> M24 D21* D53* AC26 FSB_D_L<53> BI 14 69
69 14 IN CPU_SMI_L A3 SMI* BCLK1 A21 FSB_CLK_CPU_N IN 14 69 69 14 BI FSB_D_L<22> L22 D22* D54* AD20 FSB_D_L<54> BI 14 69
69 14 BI FSB_D_L<23> M23 D23* D55* AE22 FSB_D_L<55> BI 14 69
DATA GRP 1
DATA GRP 3
TP_CPU_RSVD_M4 M4 RSVD0 69 14 BI FSB_D_L<24> P25 D24* D56* AF23 FSB_D_L<56> BI 14 69
TP_CPU_RSVD_N5 N5 RSVD1 69 14 BI FSB_D_L<25> P23 D25* D57* AC25 FSB_D_L<57> BI 14 69
TP_CPU_RSVD_T2 T2 RSVD2 69 14 BI FSB_D_L<26> P22 D26* D58* AE21 FSB_D_L<58> BI 14 69
TP_CPU_RSVD_V3 V3 RSVD3 69 14 BI FSB_D_L<27> T24 D27* D59* AD21 FSB_D_L<59> BI 14 69

RESERVED
TP_CPU_RSVD_B2 B2 RSVD4 69 14 BI FSB_D_L<28> R24 D28* D60* AC22 FSB_D_L<60> BI 14 69
TP_CPU_RSVD_F6 F6 RSVD5 69 14 BI FSB_D_L<29> L25 D29* D61* AD23 FSB_D_L<61> BI 14 69
TP_CPU_RSVD_D2 D2 RSVD6 69 14 BI FSB_D_L<30> T25 D30* D62* AF22 FSB_D_L<62> BI 14 69
TP_CPU_RSVD_D22 D22 RSVD7 1 69 14 BI FSB_D_L<31> N25 D31* D63* AC23 FSB_D_L<63> BI 14 69
TP_CPU_RSVD_D3 D3 RSVD8 R1005 69 14 BI FSB_DSTB_L_N<1> L26 DSTBN1* DSTBN3* AE25 FSB_DSTB_L_N<3> BI 14 69

1K
CPU JTAG Support 1%
1/16W
69 14 BI FSB_DSTB_L_P<1> M26 DSTBP1* DSTBP3* AF24 FSB_DSTB_L_P<3> BI 14 69
B R1090
MF-LF
2 402
69 14 BI FSB_DINV_L<1> N24 DINV1* DINV3* AC20 FSB_DINV_L<3> BI 14 69
B
54.9
69 13 10 7 6 XDP_TMS 1 2 CPU_GTLREF
69 27 AD26 GTLREF COMP0 R26 69 CPU_COMP<0>
MISC
1% CPU_TEST1 C23 TEST1 COMP1 U26 69 CPU_COMP<1>
1/16W
R1091 MF-LF 1 CPU_TEST2 D25 TEST2 COMP2 AA1 69 CPU_COMP<2>
54.9 402 R1006
69 13 10 7 6 XDP_TDI 1 2 2.0K TP_CPU_TEST3 C24 TEST3 COMP3 Y1 69 CPU_COMP<3>
1%
1% 1/16W CPU_TEST4 AF26 TEST4
1/16W MF-LF
MF-LF R1092 402 NO STUFF TP_CPU_TEST5 AF1 TEST5 DPRSTP* E5 CPU_DPRSTP_L IN 14 60 69 R1023 1 R1021 1
402 54.9 2
69 10 6 XDP_TDO 1 2 C1014 1 TP_CPU_TEST6 A26 TEST6 DPSLP* B5 CPU_DPSLP_L IN 14 69 54.9 54.9
1% 1%
PLACEMENT_NOTE=Place R1092 near ITP connector (if present) 1% NO STUFF 0.1uF TP_CPU_TEST7 C3 TEST7 DPWR* D24 FSB_DPWR_L 14 69 1/16W 1/16W
1/16W 10% IN
16V MF-LF MF-LF
OUT CPU_BSEL<0> CPU_PWRGD
MF-LF B22 BSEL0 PWRGOOD D6
402 R1010 X5R 2 69 9 IN 13 14 69 402 2 402 2
402
OUT CPU_BSEL<1> FSB_CPUSLP_L
0 69 9 B23 BSEL1 SLP* D7 14 69
1 2 IN
OUT CPU_BSEL<2> CPU_PSI_L
69 9 C21 BSEL2 PSI* AE6 60
OUT 1 1
NO STUFF 5% NO STUFF R1022 R1020
1/16W
R1093 R10111 MF-LF
402
1
R1012 27.4
1%
27.4
1%
54.9 1K 1K PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU. 1/16W 1/16W
69 13 10 7 6 XDP_TCK 1 2 5% 5% MF-LF MF-LF
1/16W 1/16W PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU. 2
402
2
402
1% MF-LF MF-LF
R1094 1/16W 402
2 2
402 PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.
MF-LF
649 402
69 13 10 7 6 XDP_TRST_L 1 2 PLACEMENT_NOTE (all 4 resistors):
1%
1/16W Place within 12.7mm of CPU
MF-LF
402
A SYNC_MASTER=K36B_MLB SYNC_DATE=08/18/2008 A
PAGE TITLE
CPU FSB
DRAWING NUMBER SIZE
SYNC FROM T18 Apple Inc. 051-8089 D

REVISION
CHANGE CPU FROM SOCKET TO BGA SYMBOL

R
A.0.0
10 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
A4 P6
(CPU CORE POWER) A8 P21

OMIT
A11 P24
=PPVCORE_S0_CPU 8 11 12
A14
U1000 R2
A16
PENRYN
44 A (SV Design Target) R5
FCBGA
41 A (SV HFM) A19 R22
D A7 AB20 30.4 A (SV LFM) A23

4 OF 4
R25 D
A9 OMIT AB7 23 A (LV Design Target) AF2 T1
A10 AC7 B6 T4
U1000
A12 AC9 B8 T23
PENRYN
A13 FCBGA AC12 B11 T26
A15 AC13 B13 U3
3 OF 4
A17 AC15 B16 U6
A18 AC17 B19 U21
A20 AC18 B21 U24
B7 AD7 B24 V2
B9 AD9 C5 V5
B10 AD10 C8 V22
B12 AD12 C11 V25
B14 AD14 C14 W1
B15 AD15 C16 W4
B17 AD17 C19 W23
B18 AD18 C2 W26
B20 AE9 C22 Y3
VCC
C9 AE10 C25 Y6
C10 AE12 D1 Y21
C12 AE13 D4 Y24
C13 AE15 D8 AA2
C15 AE17 D11 AA5

C17 AE18 D13 AA8
C18 AE20 D16 AA11
D9 AF9 D19 AA14
C D10
D12
AF10
AF12
D23
D26
AA16
AA19
C
D14 AF14 E3 AA22
D15 VCC AF15 E6 AA25
D17 AF17 E8 AB1

D18 AF18 E11 AB4
AF20
(CPU IO POWER 1.05V)
E7 E14 VSS VSS AB8
E9 =PP1V05_S0_CPU 6 8 10 12 13 E16 AB11
E10 G21 E19 AB13
V6
4500 mA (before VCC stable)
E12 E21 AB16
J6
2500 mA (after VCC stable)
E13 E24 AB19
E15 K6 F5 AB23
E17 M6 F8 AB26
E18 J21 F11 AC3
E20 K21 F13 AC6
F7 M21 F16 AC8
VCCP
F9 N21 F19 AC11
F10 N6 F2 AC14
F12 R21 F22 AC16
F14 R6 F25 AC19
F15 T21 G4 AC21
F17 T6 G1 AC24
F18 V21
NEED 1.5V POWER SOURCE G23 AD2
(CPU INTERNAL PLL POWER 1.5V)
F20 W21 G26 AD5
AA7 (BR1#) =PP1V5_S0_CPU 8 12 H3 AD8
AA9 B26 H6 AD11
VCCA 130 mA
AA10 C26 H21 AD13
B AA12 H24 AD16 B

AA13 VID0 AD6 CPU_VID<0> OUT 60 69 J2 AD19
AA15 VID1 AF5 CPU_VID<1> OUT 60 69 J5 AD22
AA17 VID2 AE5 CPU_VID<2> OUT 60 69 J22 AD25
=PPVCORE_S0_CPU 8 11 12
AA18 VID3 AF4 CPU_VID<3> OUT 60 69 J25 AE1
AA20 VID4 AE3 CPU_VID<4> OUT 60 69 K1 AE4
1
AB9 VID5 AF3 CPU_VID<5> OUT 60 69
R1100 K4 AE8
100
AC10 VID6 AE2 CPU_VID<6> OUT 60 69 1% K23 AE11
1/16W
AB10 MF-LF K26 AE14
2
402
AB12 L3 AE16
AB14 VCCSENSE AF7 CPU_VCCSENSE_P OUT 60 69 L6 AE19
AB15 L21 AE23
PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.
AB17 PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs. L24 AE26
AB18 VSSSENSE AE7 CPU_VCCSENSE_N OUT 60 69 M2 A2
M5 AF6
1 M22 AF8
R1101
100 M25 AF11
1%
1/16W N1 AF13
MF-LF
402 N4 AF16
2
N23 AF19
N26 AF21
P3 A25
B1 (Socket-P KEY) AF25
PAGE TITLE
CPU Power & Ground

SYNC FROM T18 DRAWING NUMBER
051-8089
SIZE
D
Apple Inc.
CHANGE CPU FROM SOCKET TO BGA SYMBOL R
REVISION
A.0.0
11 OF 109
Current numbers from Merom for Santa Rosa EMTS, doc #20905. <CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU VCore HF and Bulk Decoupling

6x 330uF. 32x 22uF 0805 (20 stuffed)
PLACEMENT_NOTE (C1200-C1219):
11 8 =PPVCORE_S0_CPU
Place inside socket cavity on secondary side.
D CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
D
1 1 1 1 1 1 1 1 1 1
C1200 C1201 C1202 C1203 C1204 C1205 C1206 C1207 C1208 C1209
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
805 805 805 805 805 805 805 805 805 805
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 C1210 1 C1211 1 C1212 1 C1213 1 C1214 1 C1215 1 C1216 1 C1217 1 C1218 1 C1219
22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF 22UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
805 805 805 805 805 805 805 805 805 805
PLACEMENT_NOTE (C1240-C1243):
Place on secondary side.
CRITICAL CRITICAL CRITICAL CRITICAL

1 1 1 1
C1240 C1241 C1242 C1243
330UF 330UF 330UF 330UF
20% 20% 20% 20%
3 2 2.0V 3 2 2.0V 3 2 2.0V 3 2 2.0V
POLY-TANT POLY-TANT POLY-TANT POLY-TANT
D2T-SM2 D2T-SM2 D2T-SM2 D2T-SM2
C C
VCCA (CPU AVdd) DECOUPLING

1x 10uF, 1x 0.01uF
11 8 =PP1V5_S0_CPU
PLACEMENT_NOTE=PLACE C1250 C1251 NEAR CPU PIN B26.
1 1
C1250 C1251
10uF 0.01UF
20% 10%
6.3V 16V
X5R 2 2 CERM
603 402
B B
VCCP (CPU I/O) DECOUPLING
1x 330uF, 6x 0.1uF 0402
13 11 10 8 6 =PP1V05_S0_CPU
PLACEMENT_NOTE=PLACE C1260 BETWEEN CPU & MCP79.
CRITICAL
C1260 1 1 C1261 1 C1262 1 C1263 1 C1264 1 C1265 1 C1266
330UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20%
2.0V 10V 10V 10V 10V 10V 10V
2 3 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
POLY-TANT
D2T-SM2 402 402 402 402 402 402
PAGE TITLE
CPU Decoupling
SYNC FROM T18 DRAWING NUMBER
051-8089
SIZE
D
Apple Inc. REVISION
R
A.0.0
12 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Mini-XDP Connector
NOTE: This is not the standard XDP pinout.
D Use with 920-0620 adapter board to support CPU, MCP debugging.

D
MCP79-specific pinout
8 6 =PP3V3_S0_XDP
12 11 10 8 6 =PP1V05_S0_CPU XDP_CONN
J1300
6-1747769-0
XDP CRITICAL
F-ST-SM
R1315 1 64
54.9 62
1%
1/16W
MF-LF
402
2
1 2
69 10 7 XDP_BPM_L<5> OBSFN_A0 3 4 OBSFN_C0 JTAG_MCP_TDO_CONN 6 7

BI IN
69 10 7 XDP_BPM_L<4> OBSFN_A1 5 6 OBSFN_C1 JTAG_MCP_TRST_L 6 7 21
BI OUT
7 8
69 10 7 XDP_BPM_L<3> OBSDATA_A0 9 10 OBSDATA_C0 MCP_DEBUG<0> 7 19 72

BI BI
IN BI
13 14

IN BI
IN BI
19 20
C 7 TP_XDP_OBSFN_B0 OBSFN_B0 21 22 OBSFN_D0 JTAG_MCP_TDI OUT 6 7 21
C
7 TP_XDP_OBSFN_B1 OBSFN_B1 23 24 OBSFN_D1 JTAG_MCP_TMS 6 7 21
OUT
25 26
7 TP_XDP_OBSDATA_B0 OBSDATA_B0 27 28 OBSDATA_D0 MCP_DEBUG<4> 7 19 72

BI
BI
31 32

BI
XDP 35 36
7 TP_XDP_OBSDATA_B3 OBSDATA_B3 OBSDATA_D3 MCP_DEBUG<7> BI 7 19 72
R1399 37 38
1K 39 40
69 14 10 IN CPU_PWRGD 1 2 7 XDP_PWRGD PWRGD/HOOK0 ITPCLK/HOOK4 FSB_CLK_ITP_P IN 7 14 69
41 42 XDP
5% 7 XDP_OBS20 HOOK1 ITPCLK#/HOOK5 FSB_CLK_ITP_N IN 7 14 69
1/16W
MF-LF VCC_OBS_AB 43 44 VCC_OBS_CD R1303
402
45 46
1K
19 7 IN PM_LATRIGGER_L HOOK2 RESET#/HOOK6 69 7 XDP_CPURST_L 1 2 FSB_CPURST_L IN 10 14 69
21 7 6 JTAG_MCP_TCK HOOK3 47 48 DBR#/HOOK7 XDP_DBRESET_L 7 10 26 5% PLACEMENT_NOTE=Place close to CPU to minimize stub.

OUT OUT 1/16W
49 50 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. MF-LF
402
72 44 21 7 SMBUS_MCP_0_DATA SDA 51 52 TDO XDP_TDO_CONN 6 7
BI IN
72 44 21 7 SMBUS_MCP_0_CLK SCL 53 54 TRSTn XDP_TRST_L 6 7 10 69
BI OUT
TCK1 55 56 TDI XDP_TDI 6 7 10 69
NC OUT
69 10 7 6 XDP_TCK TCK0 57 58 TMS XDP_TMS 6 7 10 69
OUT OUT
59 60 XDP_PRESENT#
XDP XDP
C1300 1
61
1
C1301
0.1uF 0.1uF
10% 63 10%
16V 16V
2 2
X5R X5R
402 516S0625 402
B B
Direction of XDP module

Please avoid any obstructions
on even-numbered side of J1300
A SYNC_MASTER=M99_MLB SYNC_DATE=01/08/2008 A
PAGE TITLE
eXtended Debug Port(MiniXDP)

DRAWING NUMBER SIZE

REVISION
R
A.0.0
13 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(1 OF 11)
69 10 BI FSB_DSTB_L_P<0> T40 CPU_DSTBP0# CPU_D0# Y43 FSB_D_L<0> BI 10 69
69 10 BI FSB_DSTB_L_N<0> U40 CPU_DSTBN0# CPU_D1# W42 FSB_D_L<1> BI 10 69
69 10 BI FSB_DINV_L<0> V41 CPU_DBI0# CPU_D2# Y40 FSB_D_L<2> BI 10 69
CPU_D3# W41 FSB_D_L<3> BI 10 69

69 10 BI FSB_DSTB_L_P<1> W39 CPU_DSTBP1#
CPU_D4# Y39 FSB_D_L<4> BI 10 69
69 10 BI FSB_DSTB_L_N<1> W37 CPU_DSTBN1#
CPU_D5# V42 FSB_D_L<5> BI 10 69
69 10 BI FSB_DINV_L<1> V35 CPU_DBI1#
CPU_D6# Y41 FSB_D_L<6> BI 10 69
D 69 10
69 10
BI
BI
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
N37
L36
CPU_DSTBP2#
CPU_DSTBN2#
CPU_D7#
CPU_D8#
Y42
P42
FSB_D_L<7>
FSB_D_L<8>
BI
BI
10 69
10 69
D
69 10 BI FSB_DINV_L<2> N35 CPU_DBI2# CPU_D9# U41 FSB_D_L<9> BI 10 69
CPU_D10# R42 FSB_D_L<10> BI 10 69

69 10 BI FSB_DSTB_L_P<3> M39 CPU_DSTBP3#
CPU_D11# T39 FSB_D_L<11> BI 10 69
69 10 BI FSB_DSTB_L_N<3> M41 CPU_DSTBN3#
CPU_D12# T42 FSB_D_L<12> BI 10 69
69 10 BI FSB_DINV_L<3> J41 CPU_DBI3#
CPU_D13# T41 FSB_D_L<13> BI 10 69
CPU_D14# R41 FSB_D_L<14> BI 10 69

69 10 BI FSB_A_L<3> AC34 CPU_A3#
CPU_D15# T43 FSB_D_L<15> BI 10 69
69 10 BI FSB_A_L<4> AE38 CPU_A4#
CPU_D16# W35 FSB_D_L<16> BI 10 69
CPU_D17# AA37 FSB_D_L<17> BI 10 69
69 10 BI FSB_A_L<6> AC37 CPU_A6#
CPU_D18# W33 FSB_D_L<18> BI 10 69
CPU_D19# W34 FSB_D_L<19> BI 10 69
CPU_D20# AA36 FSB_D_L<20> BI 10 69
69 10 BI FSB_A_L<9> AB35 CPU_A9#
CPU_D21# AA34 FSB_D_L<21> BI 10 69
69 10 BI FSB_A_L<10> AF35 CPU_A10#
CPU_D22# AA38 FSB_D_L<22> BI 10 69
69 10 BI FSB_A_L<11> AG35 CPU_A11#
CPU_D23# AA35 FSB_D_L<23> BI 10 69
69 10 BI FSB_A_L<12> AG39 CPU_A12#
CPU_D24# U38 FSB_D_L<24> BI 10 69
69 10 BI FSB_A_L<13> AE33 CPU_A13#
CPU_D25# U36 FSB_D_L<25> BI 10 69
69 10 BI FSB_A_L<14> AG37 CPU_A14#
CPU_D26# U35 FSB_D_L<26> BI 10 69
69 10 BI FSB_A_L<15> AG38 CPU_A15#
CPU_D27# U33 FSB_D_L<27> BI 10 69
69 10 BI FSB_A_L<16> AG34 CPU_A16#
CPU_D28# U34 FSB_D_L<28> BI 10 69
69 10 BI FSB_A_L<17> AN38 CPU_A17#
CPU_D29# W38 FSB_D_L<29> BI 10 69
69 10 BI FSB_A_L<18> AL39 CPU_A18#
CPU_D30# R33 FSB_D_L<30> BI 10 69
69 10 BI FSB_A_L<19> AG33 CPU_A19#
CPU_D31# U37 FSB_D_L<31> BI 10 69
69 10 BI FSB_A_L<20> AL33 CPU_A20#
CPU_D32# N34 FSB_D_L<32> BI 10 69
69 10 BI FSB_A_L<21> AJ33 CPU_A21#
CPU_D33# N33 FSB_D_L<33> BI 10 69
C 69 10
69 10
BI
BI
FSB_A_L<22>
FSB_A_L<23>
AN36
AJ35
CPU_A22#
CPU_A23#
CPU_D34#
CPU_D35#
R34
R35
FSB_D_L<34>
FSB_D_L<35>
BI 10 69 C
FSB
BI 10 69
69 10 BI FSB_A_L<24> AJ37 CPU_A24#
CPU_D36# P35 FSB_D_L<36> BI 10 69
69 10 BI FSB_A_L<25> AJ36 CPU_A25#
CPU_D37# R39 FSB_D_L<37> BI 10 69
69 10 BI FSB_A_L<26> AJ38 CPU_A26#
CPU_D38# R37 FSB_D_L<38> BI 10 69
69 10 BI FSB_A_L<27> AL37 CPU_A27#
CPU_D39# R38 FSB_D_L<39> BI 10 69
69 10 BI FSB_A_L<28> AL34 CPU_A28#
CPU_D40# L37 FSB_D_L<40> BI 10 69
69 10 BI FSB_A_L<29> AN37 CPU_A29#
CPU_D41# L39 FSB_D_L<41> BI 10 69
69 10 BI FSB_A_L<30> AJ34 CPU_A30#
CPU_D42# L38 FSB_D_L<42> BI 10 69
69 10 BI FSB_A_L<31> AL38 CPU_A31#
CPU_D43# N36 FSB_D_L<43> BI 10 69
69 10 BI FSB_A_L<32> AL35 CPU_A32#
CPU_D44# N38 FSB_D_L<44> BI 10 69
69 10 BI FSB_A_L<33> AN34 CPU_A33#
CPU_D45# J39 FSB_D_L<45> BI 10 69
69 10 BI FSB_A_L<34> AR39 CPU_A34#
CPU_D46# J38 FSB_D_L<46> BI 10 69
69 10 BI FSB_A_L<35> AN35 CPU_A35#
CPU_D47# J37 FSB_D_L<47> BI 10 69
69 10 BI FSB_ADSTB_L<0> AE36 CPU_ADSTB0# CPU_D48# L42 FSB_D_L<48> BI 10 69
69 10 BI FSB_ADSTB_L<1> AK35 CPU_ADSTB1# CPU_D49# M42 FSB_D_L<49> BI 10 69
CPU_D50# P41 FSB_D_L<50> BI 10 69
69 10 BI FSB_REQ_L<0> AC38 CPU_REQ0# CPU_D51# N41 FSB_D_L<51> BI 10 69
69 10 BI FSB_REQ_L<1> AA33 CPU_REQ1# CPU_D52# N40 FSB_D_L<52> BI 10 69
69 10 BI FSB_REQ_L<2> AC39 CPU_REQ2# CPU_D53# M40 FSB_D_L<53> BI 10 69

24 22 14 8 =PP1V05_S0_MCP_FSB
69 10 BI FSB_REQ_L<3> AC33 CPU_REQ3# CPU_D54# H40 FSB_D_L<54> BI 10 69
69 10 BI FSB_REQ_L<4> AC35 CPU_REQ4# CPU_D55# K42 FSB_D_L<55> BI 10 69

1 1 1
R1410 R1415 R1416 CPU_D56# H41 FSB_D_L<56> 10 69
BI
54.9 62 62
1% 5% 5% 69 10 BI FSB_ADS_L AD42 CPU_ADS# CPU_D57# L41 FSB_D_L<57> BI 10 69
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF 69 10 BI FSB_BNR_L AD43 CPU_BNR# CPU_D58# H43 FSB_D_L<58> BI 10 69
402 2 402 2 2 402
69 10 BI FSB_BREQ0_L AE40 CPU_BR0# CPU_D59# H42 FSB_D_L<59> BI 10 69
B 69 42 10 IN PM_THRMTRIP_L 69 10 BI
69 FSB_BREQ1_L
FSB_DBSY_L
AL32
AD39
CPU_BR1#
CPU_DBSY#
CPU_D60#
CPU_D61#
K41
J40
FSB_D_L<60>
FSB_D_L<61>
BI
BI
10 69
10 69
B
69 10 IN CPU_FERR_L 69 10 BI FSB_DRDY_L AD41 CPU_DRDY# CPU_D62# H39 FSB_D_L<62> BI 10 69
69 10 BI FSB_HIT_L AB42 CPU_HIT# CPU_D63# M43 FSB_D_L<63> BI 10 69
69 10 BI FSB_HITM_L AD40 CPU_HITM#

69 10 IN FSB_LOCK_L AC43 CPU_LOCK# CPU_BPRI# AA41 FSB_BPRI_L OUT 10 69
69 10 OUT FSB_TRDY_L AE41 CPU_TRDY# CPU_DEFER# AA40 FSB_DEFER_L OUT 10 69
NO STUFF NO STUFF NO STUFF

9 OUT CPU_PECI_MCP E41 CPU_PECI
R1420
1
R1421
1 1
R1422 BCLK_OUT_CPU_P G42 FSB_CLK_CPU_P OUT 10 69
69 60 42 10 OUT CPU_PROCHOT_L AJ41 CPU_PROCHOT#
1K 1K 1K BCLK_OUT_CPU_N G41 FSB_CLK_CPU_N OUT 10 69
5% 5% 5% AG43 CPU_THERMTRIP#
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF AH40 CPU_FERR# BCLK_OUT_ITP_P AL43 FSB_CLK_ITP_P OUT 7 13 69
402 2 402 2
2 402 BCLK_OUT_ITP_N AL42 FSB_CLK_ITP_N OUT 7 13 69
9 IN =MCP_BSEL<2> (MCP_BSEL<2>) F42 CPU_BSEL2

BCLK_OUT_NB_P AL41 69 FSB_CLK_MCP_P
9 IN =MCP_BSEL<1> (MCP_BSEL<1>) D42 CPU_BSEL1
BCLK_OUT_NB_N AK42 69 FSB_CLK_MCP_N
9 IN =MCP_BSEL<0> (MCP_BSEL<0>) F41 CPU_BSEL0
Loop-back clock for delay matching.
69 10 OUT FSB_RS_L<0> AC41 CPU_RS0# BCLK_IN_N AK41
69 10 OUT FSB_RS_L<1> AB41 CPU_RS1# BCLK_IN_P AJ40
69 10 OUT FSB_RS_L<2> AC42 CPU_RS2#
R1430 1 1
R1435 24 PP1V05_S0_MCP_PLL_FSB CPU_A20M# AF41 CPU_A20M_L OUT 10 69 =PP1V05_S0_MCP_FSB 8 14 22 24
49.9 49.9 270 mA (A01) 206 mA AG27 +V_DLL_DLCELL_AVDD CPU_IGNNE# AH39 CPU_IGNNE_L OUT 10 69 NO STUFF
1% 1%
1/16W 1/16W 20 mA AH27 +V_PLL_MCLK CPU_INIT# AH42 CPU_INIT_L OUT 10 69
1
R1440
MF-LF MF-LF
402
2 2
402 29 mA AG28 +V_PLL_FSB CPU_INTR AF42 CPU_INTR OUT 10 69 150
5%
15 mA AH28 +V_PLL_CPU CPU_NMI AG41 CPU_NMI OUT 10 69 1/16W
MF-LF
CPU_SMI# AH41 CPU_SMI_L
A 69 MCP_BCLK_VML_COMP_VDD AM39 BCLK_VML_COMP_VDD
CPU_PWRGD AH43 CPU_PWRGD
OUT 10 69
2
402
10 13 69
MCP_BCLK_VML_COMP_GND AM40 OUT PAGE TITLE
69 BCLK_VML_COMP_GND
CPU_RESET# H38 FSB_CPURST_L OUT 10 13 69
MCP CPU Interface
69 MCP_CPU_COMP_VCC AM43 CPU_COMP_VCC CPU_SLP# AM33 FSB_CPUSLP_L OUT 10 69 DRAWING NUMBER SIZE
1 1
69 MCP_CPU_COMP_GND AM42 CPU_COMP_GND CPU_DPSLP# AN33 CPU_DPSLP_L OUT 10 69
R1431 R1436 CPU_DPWR# AM32 FSB_DPWR_L OUT 10 69 REVISION
49.9 49.9
1%
1/16W
1%
1/16W
CPU_STPCLK# AG42 CPU_STPCLK_L OUT 10 69
R
A.0.0
MF-LF MF-LF CPU_DPRSTP# AN32 CPU_DPRSTP_L OUT 10 60 69 NOTICE OF PROPRIETARY PROPERTY: BRANCH
402 402
2 2
14 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
U1400 U1400
MCP79-TOPO-B MCP79-TOPO-B
BGA BGA
(2 OF 11) (3 OF 11)
70 28 BI MEM_A_DQ<63> AL8 MDQ0_63 MDQS0_7_P AL10 MEM_A_DQS_P<7> BI 28 70 70 29 BI MEM_B_DQ<63> AT4 MDQ1_63 MDQS1_7_P AT2 MEM_B_DQS_P<7> BI 29 70
70 28 BI MEM_A_DQ<62> AL9 MDQ0_62 MDQS0_7_N AL11 MEM_A_DQS_N<7> BI 28 70 70 29 BI MEM_B_DQ<62> AT3 MDQ1_62 MDQS1_7_N AT1 MEM_B_DQS_N<7> BI 29 70
70 28 BI MEM_A_DQ<61> AP9 MDQ0_61 MDQS0_6_P AR8 MEM_A_DQS_P<6> BI 28 70 70 29 BI MEM_B_DQ<61> AV2 MDQ1_61 MDQS1_6_P AY2 MEM_B_DQS_P<6> BI 29 70
70 28 BI MEM_A_DQ<60> AN9 MDQ0_60 MDQS0_6_N AR9 MEM_A_DQS_N<6> BI 28 70 70 29 BI MEM_B_DQ<60> AV3 MDQ1_60 MDQS1_6_N AY1 MEM_B_DQS_N<6> BI 29 70
D 70 28
70 28
BI
BI
MEM_A_DQ<59>
MEM_A_DQ<58>
AL6
AL7
MDQ0_59
MDQ0_58
MDQS0_5_P
MDQS0_5_N
AW7
AW8
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
BI
BI
28 70
28 70
70 29
70 29
BI
BI
MEM_B_DQ<59>
MEM_B_DQ<58>
AR4
AR3
MDQ1_59
MDQ1_58
MDQS1_5_P
MDQS1_5_N
BB6
BA6
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
BI
BI
29 70
29 70
D
70 28 BI MEM_A_DQ<57> AN6 MDQ0_57 MDQS0_4_P AP13 MEM_A_DQS_P<4> BI 28 70 70 29 BI MEM_B_DQ<57> AU2 MDQ1_57 MDQS1_4_P BA10 MEM_B_DQS_P<4> BI 29 70
70 28 BI MEM_A_DQ<56> AN7 MDQ0_56 MDQS0_4_N AR13 MEM_A_DQS_N<4> BI 28 70 70 29 BI MEM_B_DQ<56> AU3 MDQ1_56 MDQS1_4_N AY11 MEM_B_DQS_N<4> BI 29 70
70 28 BI MEM_A_DQ<55> AR6 MDQ0_55 MDQS0_3_P AV25 MEM_A_DQS_P<3> BI 28 70 70 29 BI MEM_B_DQ<55> AY4 MDQ1_55 MDQS1_3_P BB33 MEM_B_DQS_P<3> BI 29 70
70 28 BI MEM_A_DQ<54> AR7 MDQ0_54 MDQS0_3_N AW25 MEM_A_DQS_N<3> BI 28 70 70 29 BI MEM_B_DQ<54> AY3 MDQ1_54 MDQS1_3_N BA33 MEM_B_DQS_N<3> BI 29 70
70 28 BI MEM_A_DQ<53> AV6 MDQ0_53 MDQS0_2_P AU30 MEM_A_DQS_P<2> BI 28 70 70 29 BI MEM_B_DQ<53> BB3 MDQ1_53 MDQS1_2_P BB37 MEM_B_DQS_P<2> BI 29 70
70 28 BI MEM_A_DQ<52> AW5 MDQ0_52 MDQS0_2_N AU29 MEM_A_DQS_N<2> BI 28 70 70 29 BI MEM_B_DQ<52> BC3 MDQ1_52 MDQS1_2_N BA37 MEM_B_DQS_N<2> BI 29 70
70 28 BI MEM_A_DQ<51> AN10 MDQ0_51 MDQS0_1_P AT35 MEM_A_DQS_P<1> BI 28 70 70 29 BI MEM_B_DQ<51> AW4 MDQ1_51 MDQS1_1_P BA43 MEM_B_DQS_P<1> BI 29 70
70 28 BI MEM_A_DQ<50> AR5 MDQ0_50 MDQS0_1_N AU35 MEM_A_DQS_N<1> BI 28 70 70 29 BI MEM_B_DQ<50> AW3 MDQ1_50 MDQS1_1_N AY42 MEM_B_DQS_N<1> BI 29 70
70 28 BI MEM_A_DQ<49> AU6 MDQ0_49 MDQS0_0_P AU39 MEM_A_DQS_P<0> BI 28 70 70 29 BI MEM_B_DQ<49> BA3 MDQ1_49 MDQS1_0_P AT42 MEM_B_DQS_P<0> BI 29 70
70 28 BI MEM_A_DQ<48> AV5 MDQ0_48 MDQS0_0_N AT39 MEM_A_DQS_N<0> BI 28 70 70 29 BI MEM_B_DQ<48> BB2 MDQ1_48 MDQS1_0_N AT43 MEM_B_DQS_N<0> BI 29 70
70 28 BI MEM_A_DQ<47> AU7 MDQ0_47 70 29 BI MEM_B_DQ<47> BB5 MDQ1_47

70 28 BI MEM_A_DQ<46> AU8 MDQ0_46 70 29 BI MEM_B_DQ<46> BA5 MDQ1_46
MEMORY PARTITION 0
MEMORY PARTITION 1
70 28 BI MEM_A_DQ<45> AW9 MDQ0_45 70 29 BI MEM_B_DQ<45> BA8 MDQ1_45
70 28 BI MEM_A_DQ<44> AP11 MDQ0_44 70 29 BI MEM_B_DQ<44> BC8 MDQ1_44
70 28 BI MEM_A_DQ<43> AW6 MDQ0_43 70 29 BI MEM_B_DQ<43> BB4 MDQ1_43
70 28 BI MEM_A_DQ<42> AY5 MDQ0_42 MRAS0# AV17 MEM_A_RAS_L OUT 28 30 70 70 29 BI MEM_B_DQ<42> BC4 MDQ1_42 MRAS1# AW16 MEM_B_RAS_L OUT 29 30 70
70 28 BI MEM_A_DQ<41> AU9 MDQ0_41 MCAS0# AP17 MEM_A_CAS_L OUT 28 30 70 70 29 BI MEM_B_DQ<41> BA7 MDQ1_41 MCAS1# BA15 MEM_B_CAS_L OUT 29 30 70
70 28 BI MEM_A_DQ<40> AV9 MDQ0_40 MWE0# AR17 MEM_A_WE_L OUT 28 30 70 70 29 BI MEM_B_DQ<40> AY8 MDQ1_40 MWE1# BA16 MEM_B_WE_L OUT 29 30 70
70 28 BI MEM_A_DQ<39> AU11 MDQ0_39 70 29 BI MEM_B_DQ<39> BA9 MDQ1_39

70 28 BI MEM_A_DQ<38> AV11 MDQ0_38 70 29 BI MEM_B_DQ<38> BB10 MDQ1_38
70 28 BI MEM_A_DQ<37> AV13 MDQ0_37 70 29 BI MEM_B_DQ<37> BB12 MDQ1_37
70 28 BI MEM_A_DQ<36> AW13 MDQ0_36 70 29 BI MEM_B_DQ<36> AW12 MDQ1_36
70 28 BI MEM_A_DQ<35> AR11 MDQ0_35 70 29 BI MEM_B_DQ<35> BB8 MDQ1_35
70 28 BI MEM_A_DQ<34> AT11 MDQ0_34 MBA0_2 AP23 MEM_A_BA<2> OUT 28 30 70 70 29 BI MEM_B_DQ<34> BB9 MDQ1_34 MBA1_2 BB29 MEM_B_BA<2> OUT 29 30 70
70 28 BI MEM_A_DQ<33> AR14 MDQ0_33 MBA0_1 AP19 MEM_A_BA<1> OUT 28 30 70 70 29 BI MEM_B_DQ<33> AY12 MDQ1_33 MBA1_1 BB18 MEM_B_BA<1> OUT 29 30 70
C 70 28 BI MEM_A_DQ<32>
MEM_A_DQ<31>
AU13
AR26
MDQ0_32 MBA0_0 AW17 MEM_A_BA<0> OUT 28 30 70 70 29 BI MEM_B_DQ<32>
MEM_B_DQ<31>
BA12
BC32
MDQ1_32 MBA1_0 BB17 MEM_B_BA<0> OUT 29 30 70 C
70 28 BI MDQ0_31 70 29 BI MDQ1_31
70 28 BI MEM_A_DQ<30> AU25 MDQ0_30 70 29 BI MEM_B_DQ<30> AW32 MDQ1_30
70 28 BI MEM_A_DQ<29> AT27 MDQ0_29 70 29 BI MEM_B_DQ<29> BA35 MDQ1_29
70 28 BI MEM_A_DQ<28> AU27 MDQ0_28 70 29 BI MEM_B_DQ<28> AY36 MDQ1_28
70 28 BI MEM_A_DQ<27> AP25 MDQ0_27 70 29 BI MEM_B_DQ<27> BA32 MDQ1_27
MA0_14 AR23 MEM_A_A<14> OUT 28 30 70 MA1_14 BA29 MEM_B_A<14> OUT 29 30 70
70 28 BI MEM_A_DQ<26> AR25 MDQ0_26 70 29 BI MEM_B_DQ<26> BB32 MDQ1_26
MA0_13 AU15 MEM_A_A<13> OUT 28 30 70 MA1_13 BA14 MEM_B_A<13> OUT 29 30 70
MA0_12 AN23 MEM_A_A<12> OUT 28 30 70 MA1_12 AW28 MEM_B_A<12> OUT 29 30 70
70 28 BI MEM_A_DQ<24> AR27 MDQ0_24 70 29 BI MEM_B_DQ<24> AY35 MDQ1_24
MA0_11 AW21 MEM_A_A<11> OUT 28 30 70 MA1_11 BC28 MEM_B_A<11> OUT 29 30 70
70 28 BI MEM_A_DQ<23> AP29 MDQ0_23 70 29 BI MEM_B_DQ<23> BC36 MDQ1_23
MA0_10 AN19 MEM_A_A<10> OUT 28 30 70 MA1_10 BA17 MEM_B_A<10> OUT 29 30 70
70 28 BI MEM_A_DQ<22> AR29 MDQ0_22 70 29 BI MEM_B_DQ<22> AW36 MDQ1_22
MA0_9 AV21 MEM_A_A<9> OUT 28 30 70 MA1_9 BB28 MEM_B_A<9> OUT 29 30 70
MA0_8 AR22 MEM_A_A<8> OUT 28 30 70 MA1_8 AY28 MEM_B_A<8> OUT 29 30 70
70 28 BI MEM_A_DQ<20> AR31 MDQ0_20 70 29 BI MEM_B_DQ<20> AY40 MDQ1_20
70 28 BI MEM_A_DQ<19> AV27 MDQ0_19 70 29 BI MEM_B_DQ<19> BA36 MDQ1_19
MA0_6 AP21 MEM_A_A<6> OUT 28 30 70 MA1_6 AY27 MEM_B_A<6> OUT 29 30 70
70 28 BI MEM_A_DQ<18> AN29 MDQ0_18 70 29 BI MEM_B_DQ<18> BB36 MDQ1_18
70 28 BI MEM_A_DQ<17> AV29 MDQ0_17 70 29 BI MEM_B_DQ<17> BA38 MDQ1_17
MA0_4 AN21 MEM_A_A<4> OUT 28 30 70 MA1_4 BA26 MEM_B_A<4> OUT 29 30 70
70 28 BI MEM_A_DQ<16> AN31 MDQ0_16 70 29 BI MEM_B_DQ<16> AY39 MDQ1_16
MA0_3 AV19 MEM_A_A<3> OUT 28 30 70 MA1_3 BB26 MEM_B_A<3> OUT 29 30 70
70 28 BI MEM_A_DQ<15> AU31 MDQ0_15 70 29 BI MEM_B_DQ<15> BB40 MDQ1_15
70 28 BI MEM_A_DQ<14> AR33 MDQ0_14 70 29 BI MEM_B_DQ<14> AW40 MDQ1_14
MA0_1 AT19 MEM_A_A<1> OUT 28 30 70 MA1_1 BB25 MEM_B_A<1> OUT 29 30 70
70 28 BI MEM_A_DQ<13> AV37 MDQ0_13 70 29 BI MEM_B_DQ<13> AV42 MDQ1_13
70 28 BI MEM_A_DQ<12> AW37 MDQ0_12 70 29 BI MEM_B_DQ<12> AV41 MDQ1_12
70 28 BI MEM_A_DQ<11> AT31 MDQ0_11 70 29 BI MEM_B_DQ<11> BA40 MDQ1_11
70 28 BI MEM_A_DQ<10> AV31 MDQ0_10 70 29 BI MEM_B_DQ<10> BC40 MDQ1_10
MEM_A_DQ<9> AT37
MEMORY MEM_B_DQ<9> AW42
MEMORY
70 28 BI MDQ0_9 70 29 BI MDQ1_9
MEM_A_DQ<8> AU37
CONTROL MEM_B_DQ<8> AW41
CONTROL
70 28 BI MDQ0_8 70 29 BI MDQ1_8
MEM_A_DQ<7> AW39
0A MEM_B_DQ<7> AT40
1A
70 28 BI MDQ0_7 70 29 BI MDQ1_7
MCLK0A_2_P AW33 TP_MEM_A_CLK2P MCLK1A_2_P BA42 TP_MEM_B_CLK2P
B 70 28
70 28
BI
BI
MEM_A_DQ<6>
MEM_A_DQ<5>
AV39
AR37
MDQ0_6
MDQ0_5
MCLK0A_2_N AV33 TP_MEM_A_CLK2N
70 29
70 29
BI
BI
MEM_B_DQ<6>
MEM_B_DQ<5>
AT41
AP41
MDQ1_6
MDQ1_5
MCLK1A_2_N BB42 TP_MEM_B_CLK2N B
70 28 BI MEM_A_DQ<4> AR38 MDQ0_4 MCLK0A_1_P BA24 MEM_A_CLK_P<1> OUT 28 70 70 29 BI MEM_B_DQ<4> AN40 MDQ1_4 MCLK1A_1_P BB22 MEM_B_CLK_P<1> OUT 29 70
70 28 BI MEM_A_DQ<3> AV38 MDQ0_3 MCLK0A_1_N AY24 MEM_A_CLK_N<1> OUT 28 70 70 29 BI MEM_B_DQ<3> AU40 MDQ1_3 MCLK1A_1_N BA22 MEM_B_CLK_N<1> OUT 29 70
70 28 BI MEM_A_DQ<2> AW38 MDQ0_2 70 29 BI MEM_B_DQ<2> AU41 MDQ1_2

MCLK0A_0_P BB20 MEM_A_CLK_P<0> OUT 28 70 MCLK1A_0_P BA19 MEM_B_CLK_P<0> OUT 29 70
70 28 BI MEM_A_DQ<1> AR35 MDQ0_1 70 29 BI MEM_B_DQ<1> AR41 MDQ1_1
MCLK0A_0_N BC20 MEM_A_CLK_N<0> OUT 28 70 MCLK1A_0_N AY19 MEM_B_CLK_N<0> OUT 29 70
70 28 BI MEM_A_DQ<0> AP35 MDQ0_0 70 29 BI MEM_B_DQ<0> AP42 MDQ1_0
70 28 OUT MEM_A_DM<7> AN5 MDQM0_7 MCS0A_1# AT15 MEM_A_CS_L<1> OUT 28 30 70 70 29 OUT MEM_B_DM<7> AT5 MDQM1_7 MCS1A_1# BB14 MEM_B_CS_L<1> OUT 29 30 70
70 28 OUT MEM_A_DM<6> AU5 MDQM0_6 MCS0A_0# AR18 MEM_A_CS_L<0> OUT 28 30 70 70 29 OUT MEM_B_DM<6> BA2 MDQM1_6 MCS1A_0# BB16 MEM_B_CS_L<0> OUT 29 30 70
70 28 OUT MEM_A_DM<5> AR10 MDQM0_5 70 29 OUT MEM_B_DM<5> AY7 MDQM1_5

70 28 OUT MEM_A_DM<4> AN13 MDQM0_4 MODT0A_1 AP15 MEM_A_ODT<1> OUT 28 30 70 70 29 OUT MEM_B_DM<4> BA11 MDQM1_4 MODT1A_1 BB13 MEM_B_ODT<1> OUT 29 30 70
70 28 OUT MEM_A_DM<3> AN27 MDQM0_3 MODT0A_0 AV15 MEM_A_ODT<0> OUT 28 30 70 70 29 OUT MEM_B_DM<3> BB34 MDQM1_3 MODT1A_0 AY15 MEM_B_ODT<0> OUT 29 30 70
70 28 OUT MEM_A_DM<2> AW29 MDQM0_2 70 29 OUT MEM_B_DM<2> BB38 MDQM1_2

70 28 OUT MEM_A_DM<1> AV35 MDQM0_1 MCKE0A_1 AU23 MEM_A_CKE<1> OUT 28 30 70 70 29 OUT MEM_B_DM<1> AY43 MDQM1_1 MCKE1A_1 AY31 MEM_B_CKE<1> OUT 29 30 70
70 28 OUT MEM_A_DM<0> AR34 MDQM0_0 MCKE0A_0 AT23 MEM_A_CKE<0> OUT 28 30 70 70 29 OUT MEM_B_DM<0> AR42 MDQM1_0 MCKE1A_0 BB30 MEM_B_CKE<0> OUT 29 30 70
PAGE TITLE
MCP Memory Interface

DRAWING NUMBER SIZE

REVISION
R
A.0.0
15 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(4 OF 11)
TP_MEM_A_CLK5P AU33 MCLK0B_2_P MCLK1B_2_P BA41 TP_MEM_B_CLK5P
MEMORY CONTROL 0B
MEMORY CONTROL 1B
TP_MEM_A_CLK5N AU34 MCLK0B_2_N MCLK1B_2_N BB41 TP_MEM_B_CLK5N
D TP_MEM_A_CLK4P BB24 MCLK0B_1_P MCLK1B_1_P AY23 TP_MEM_B_CLK4P
TP_MEM_A_CLK4N BC24 MCLK0B_1_N MCLK1B_1_N BA23 TP_MEM_B_CLK4N
TP_MEM_A_CLK3P BA21 MCLK0B_0_P MCLK1B_0_P BA20 TP_MEM_B_CLK3P

TP_MEM_A_CLK3N BB21 MCLK0B_0_N MCLK1B_0_N AY20 TP_MEM_B_CLK3N
TP_MEM_A_CS_L<2> AU17 MCS0B_0# MCS1B_0# BC16 TP_MEM_B_CS_L<2>

TP_MEM_A_CS_L<3> AR15 MCS0B_1# MCS1B_1# BA13 TP_MEM_B_CS_L<3>
TP_MEM_A_ODT<2> AN17 MODT0B_0 MODT1B_0 AY16 TP_MEM_B_ODT<2>

TP_MEM_A_ODT<3> AN15 MODT0B_1 MODT1B_1 BC13 TP_MEM_B_ODT<3>
TP_MEM_A_CKE<2> AV23 MCKE0B_0 MCKE1B_0 BA30 TP_MEM_B_CKE<2>

TP_MEM_A_CKE<3> AN25 MCKE0B_1 MCKE1B_1 BA31 TP_MEM_B_CKE<3>
24 PP1V05_S0_MCP_PLL_CORE
24 16 8 =PP1V8R1V5_S0_MCP_MEM
87 mA (A01) 17 mA T27 +V_PLL_XREF_XS
12 mA U28 +V_PLL_DP
1
R1610 19 mA U27 +V_PLL_CORE
40.2 MRESET0# AY32 MCP_MEM_RESET_L 9
1% 39 mA T28 +V_VPLL
1/16W TP or NC for DDR2.
MF-LF
402 2
70 MCP_MEM_COMP_VDD AN41 MEM_COMP_VDD

70 MCP_MEM_COMP_GND AM41 MEM_COMP_GND =PP1V8R1V5_S0_MCP_MEM 8 16 24
+VDD_MEM1 AM17 4771 MA (A01, DDR2)

R1611 1 +VDD_MEM2 AM19
C 40.2
1%
1/16W
AA22
AP12
GND1
GND2
+VDD_MEM3
+VDD_MEM4
AM21
AM23
C
MF-LF
402
2 G30 AM25
GND3 +VDD_MEM5
P10 GND4 +VDD_MEM6 AM27
T10 GND5 +VDD_MEM7 AM29
T6 GND6 +VDD_MEM8 AN16
V10 GND7 +VDD_MEM9 BC29
V34 GND8 +VDD_MEM10 AN20
W5 GND9 +VDD_MEM11 AN24
AA39 GND10 +VDD_MEM12 AT17
AB22 GND11 +VDD_MEM13 AP16
AB7 GND12 +VDD_MEM14 AN22
AD22 GND13 +VDD_MEM15 AP20
AE20 GND14 +VDD_MEM16 AP24
AF24 GND15 +VDD_MEM17 AV16
AG24 GND16 +VDD_MEM18 AR16
AH35 GND17 +VDD_MEM19 AR20
AK7 GND18 +VDD_MEM20 AR24
AM28 GND19 +VDD_MEM21 AW15
AT25 GND20 +VDD_MEM22 AP22
AP30 GND21 +VDD_MEM23 AP18
AR36 GND22 +VDD_MEM24 AU16
AU10 GND23 +VDD_MEM25 AN18
F28 GND24 +VDD_MEM26 AU24
BC21 GND25 +VDD_MEM27 AT21
AY9 GND26 +VDD_MEM28 AY29
B BC9
D34
GND27
GND28
+VDD_MEM29
+VDD_MEM30
AV24
AU20
B
F24 GND29 +VDD_MEM31 AU22
G32 GND30 +VDD_MEM32 AW27
H31 GND31 +VDD_MEM33 BC17
K7 GND32 +VDD_MEM34 AV20
M38 GND33 +VDD_MEM35 AY17
M6 GND35 +VDD_MEM37 AM15
M7 GND36 +VDD_MEM38 AU18
N39 GND38 +VDD_MEM40 AY26
N8 GND39 +VDD_MEM41 AW19
P33 GND40 +VDD_MEM42 AW24
P34 GND41 +VDD_MEM43 BC25
P37 GND42 +VDD_MEM44 AL30
P4 GND43 +VDD_MEM45 AM31
P40 GND44
P7 GND45 GND55 T33
R36 GND46 GND56 T34
R40 GND47 GND57 T35
R43 GND48 GND58 T37
R5 GND49 GND59 T38
T18 GND50 GND60 T7

T20 GND51 GND61 T9
AK11 GND52 GND62 U18
A T24
T26
GND53
GND54
GND63
GND64
U20
U22
PAGE TITLE
MCP Memory Misc

DRAWING NUMBER SIZE

REVISION
R
A.0.0
16 OF 109
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number). <CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(5 OF 11)
9 IN =PEG_D2R_P<0> F7 PE0_RX0_P PE0_TX0_P C5 =PEG_R2D_C_P<0> OUT 9
9 IN =PEG_D2R_N<0> E7 PE0_RX0_N PE0_TX0_N D4 =PEG_R2D_C_N<0> OUT 9
9 IN =PEG_D2R_P<1> D7 PE0_RX1_P PE0_TX1_P C4 =PEG_R2D_C_P<1> OUT 9
9 IN =PEG_D2R_N<1> C7 PE0_RX1_N PE0_TX1_N B4 =PEG_R2D_C_N<1> OUT 9
9 IN =PEG_D2R_P<2> E6 PE0_RX2_P PE0_TX2_P A4 =PEG_R2D_C_P<2> OUT 9
9 IN =PEG_D2R_N<2> F6 PE0_RX2_N PE0_TX2_N A3 =PEG_R2D_C_N<2> OUT 9
9 =PEG_D2R_P<3> E5 PE0_RX3_P PE0_TX3_P B3 =PEG_R2D_C_P<3> 9
D 9
IN
IN =PEG_D2R_N<3> F5 PE0_RX3_N PE0_TX3_N B2 =PEG_R2D_C_N<3>
OUT
OUT 9 D
9 IN =PEG_D2R_P<4> E4 PE0_RX4_P PE0_TX4_P C1 =PEG_R2D_C_P<4> OUT 9
9 IN =PEG_D2R_N<4> E3 PE0_RX4_N PE0_TX4_N D1 =PEG_R2D_C_N<4> OUT 9
9 IN =PEG_D2R_P<5> C3 PE0_RX5_P PE0_TX5_P D2 =PEG_R2D_C_P<5> OUT 9
9 IN =PEG_D2R_N<5> D3 PE0_RX5_N PE0_TX5_N E1 =PEG_R2D_C_N<5> OUT 9
9 IN =PEG_D2R_P<6> G5 PE0_RX6_P PE0_TX6_P E2 =PEG_R2D_C_P<6> OUT 9
9 IN =PEG_D2R_N<6> H5 PE0_RX6_N PE0_TX6_N F2 =PEG_R2D_C_N<6> OUT 9
9 IN =PEG_D2R_P<7> J7 PE0_RX7_P PE0_TX7_P F3 =PEG_R2D_C_P<7> OUT 9
PCI EXPRESS
9 IN =PEG_D2R_N<7> J6 PE0_RX7_N PE0_TX7_N F4 =PEG_R2D_C_N<7> OUT 9
9 IN =PEG_D2R_P<8> J5 PE0_RX8_P PE0_TX8_P G3 =PEG_R2D_C_P<8> OUT 9
9 IN =PEG_D2R_N<8> J4 PE0_RX8_N PE0_TX8_N H4 =PEG_R2D_C_N<8> OUT 9
9 IN =PEG_D2R_P<9> L11 PE0_RX9_P PE0_TX9_P H3 =PEG_R2D_C_P<9> OUT 9
9 IN =PEG_D2R_N<9> L10 PE0_RX9_N PE0_TX9_N H2 =PEG_R2D_C_N<9> OUT 9
9 IN =PEG_D2R_P<10> L9 PE0_RX10_P PE0_TX10_P H1 =PEG_R2D_C_P<10> OUT 9
9 IN =PEG_D2R_N<10> L8 PE0_RX10_N PE0_TX10_N J1 =PEG_R2D_C_N<10> OUT 9
9 IN =PEG_D2R_P<11> L7 PE0_RX11_P PE0_TX11_P J2 =PEG_R2D_C_P<11> OUT 9
9 IN =PEG_D2R_N<11> L6 PE0_RX11_N PE0_TX11_N J3 =PEG_R2D_C_N<11> OUT 9
9 IN =PEG_D2R_P<12> N11 PE0_RX12_P PE0_TX12_P K2 =PEG_R2D_C_P<12> OUT 9
9 IN =PEG_D2R_N<12> N10 PE0_RX12_N PE0_TX12_N K3 =PEG_R2D_C_N<12> OUT 9
9 IN =PEG_D2R_P<13> N9 PE0_RX13_P PE0_TX13_P L4 =PEG_R2D_C_P<13> OUT 9
9 IN =PEG_D2R_N<13> P9 PE0_RX13_N PE0_TX13_N L3 =PEG_R2D_C_N<13> OUT 9
9 IN =PEG_D2R_P<14> N7 PE0_RX14_P PE0_TX14_P M4 =PEG_R2D_C_P<14> OUT 9
9 IN =PEG_D2R_N<14> N6 PE0_RX14_N PE0_TX14_N M3 =PEG_R2D_C_N<14> OUT 9
9 IN =PEG_D2R_P<15> N5 PE0_RX15_P PE0_TX15_P M2 =PEG_R2D_C_P<15> OUT 9
9 IN =PEG_D2R_N<15> N4 PE0_RX15_N PE0_TX15_N M1 =PEG_R2D_C_N<15> OUT 9
C 9 IN PEG_PRSNT_L C9
Int PU
PE0_PRSNT_16#
PE0_REFCLK_P
PE0_REFCLK_N
E11
D11
PEG_CLK100M_P
PEG_CLK100M_N
OUT
OUT
9 71
9 71
C
Int PU
31 7 IN MINI_CLKREQ_L D5 PEB_CLKREQ#/GPIO_49 PE1_REFCLK_P G11 PCIE_CLK100M_MINI_P OUT 7 31 71
31 IN PCIE_MINI_PRSNT_L D9 PEB_PRSNT# Int PU PE1_REFCLK_N F11 PCIE_CLK100M_MINI_N OUT 7 31 71
Int PU
35 IN FW_CLKREQ_L E8 PEC_CLKREQ#/GPIO_50 PE2_REFCLK_P J11 PCIE_CLK100M_FW_P OUT 35 71
9 IN PCIE_FW_PRSNT_L C10 PEC_PRSNT# Int PU PE2_REFCLK_N J10 PCIE_CLK100M_FW_N OUT 35 71
Int PU
9 IN EXCARD_CLKREQ_L M15 PED_CLKREQ#/GPIO_51 PE3_REFCLK_P G13 PCIE_CLK100M_EXCARD_P OUT 9 71
9 IN PCIE_EXCARD_PRSNT_L B10 PED_PRSNT# Int PU PE3_REFCLK_N F13 PCIE_CLK100M_EXCARD_N OUT 9 71
Int PU
TP_PE4_CLKREQ_L L16 PEE_CLKREQ#/GPIO_16 PE4_REFCLK_P J13 TP_PCIE_CLK100M_PE4P
TP_PE4_PRSNT_L L18 PEE_PRSNT#/GPIO_46 PE4_REFCLK_N H13 TP_PCIE_CLK100M_PE4N
Int PU
Int PU
TP_MCP_GPIO_17 M16 PEF_CLKREQ#/GPIO_17 PE5_REFCLK_P L14 TP_PCIE_CLK100M_PE5P
9 OUT EXTGPU_PWR_EN M18 PEF_PRSNT#/GPIO_47 PE5_REFCLK_N K14 TP_PCIE_CLK100M_PE5N
Int PU
Int PU
9 IN PEG_CLKREQ_L M17 PEG_CLKREQ#/GPIO_18 PE6_REFCLK_P N14 TP_PCIE_CLK100M_PE6P
9 OUT EXTGPU_RESET_L M19 PEG_PRSNT#/GPIO_48 PE6_REFCLK_N M14 TP_PCIE_CLK100M_PE6N
Int PU
31 7 IN PCIE_WAKE_L F17 PE_WAKE# Int PU (S5) PEX_RST0# K11 PCIE_RESET_L OUT 26
71 31 7 IN PCIE_MINI_D2R_P K9 PE1_RX0_P PE1_TX0_P D8 PCIE_MINI_R2D_C_P OUT 31 71
71 31 7 IN PCIE_MINI_D2R_N J9 PE1_RX0_N PE1_TX0_N C8 PCIE_MINI_R2D_C_N OUT 31 71
71 35 IN PCIE_FW_D2R_P H9 PE1_RX1_P PE1_TX1_P B8 PCIE_FW_R2D_C_P OUT 35 71
B 71 35 IN PCIE_FW_D2R_N G9 PE1_RX1_N PE1_TX1_N A8 PCIE_FW_R2D_C_N OUT 35 71

B
71 9 IN PCIE_EXCARD_D2R_P F9 PE1_RX2_P PE1_TX2_P A7 PCIE_EXCARD_R2D_C_P OUT 9 71
71 9 IN PCIE_EXCARD_D2R_N E9 PE1_RX2_N PE1_TX2_N B7 PCIE_EXCARD_R2D_C_N OUT 9 71
TP_PCIE_PE4_D2RP H7 PE1_RX3_P PE1_TX3_P B6 TP_PCIE_PE4_R2D_CP

TP_PCIE_PE4_D2RN G7 PE1_RX3_N PE1_TX3_N C6 TP_PCIE_PE4_R2D_CN
8 =PP1V05_S0_MCP_PEX_DVDD0
T17 +DVDD0_PEX1 +AVDD0_PEX1 Y12 =PP1V05_S0_MCP_PEX_AVDD0 8
W19 +DVDD0_PEX2 +AVDD0_PEX2 AA12
U17 +DVDD0_PEX3 +AVDD0_PEX3 AB12

V19 +DVDD0_PEX4 +AVDD0_PEX4 M12
W16 +DVDD0_PEX5 +AVDD0_PEX5 P12
W17 +DVDD0_PEX6 +AVDD0_PEX6 R12
W18 +DVDD0_PEX7 +AVDD0_PEX7 N12

U16 +DVDD0_PEX8 +AVDD0_PEX8 T12
+AVDD0_PEX9 U12
8 =PP1V05_S0_MCP_PEX_DVDD1 T19 +DVDD1_PEX1 +AVDD0_PEX10 AC12

U19 +DVDD1_PEX2 +AVDD0_PEX11 AD12
+AVDD0_PEX12 V12
+AVDD0_PEX13 W12
24 PP1V05_S0_MCP_PLL_PEX T16 +V_PLL_PEX

84 mA (A01) +AVDD1_PEX1 M13 =PP1V05_S0_MCP_PEX_AVDD1 8
+AVDD1_PEX2 N13
71 MCP_PEX_CLK_COMP A11 PEX_CLK_COMP +AVDD1_PEX3 P13
NO STUFF
A 1
R1710
2.37K
1%
PAGE TITLE
2
1/16W
MF-LF
402
MCP PCIe Interfaces
DRAWING NUMBER SIZE
PLACEMENT_NOTE=Place within 12.7mm of U1400 IF PE0 INTERFACE IS NOT USED, GROUND DVDD0_PEX AND AVDD0_PEX.
IF PE1 INTERFACE IS NOT USED, GROUND DVDD1_PEX AND AVDD1_PEX Apple Inc. 051-8089 D
REVISION
R
A.0.0
17 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(6 OF 11) =PP3V3_ENET_MCP_RMGT 8 18 24
+3.3V_DUAL_RMGT1 J24 83 mA (A01)

+3.3V_DUAL_RMGT2 K24
LAN
D +V_DUAL_RMGT1 U23
=PP1V05_ENET_MCP_RMGT 8 24
131 mA (A01)
+V_DUAL_RMGT2 V23
32 IN ENET_RXD<0> C23 RGMII_RXD0 Network Interface Select

73 32 IN ENET_RXD<1> B23 RGMII_RXD1 MII_VREF E28 MCP_MII_VREF IN 24
73 32 IN ENET_RXD<2> E24 RGMII_RXD2 B24 ENET_TXD<0>

Interface ENET_TXD<0>
RGMII_TXD0 OUT 32 73
73 32 IN ENET_RXD<3> A24 RGMII_RXD3
RGMII_TXD1 C24 ENET_TXD<1> OUT 32 73
ENET_CLK125M_RXCLK A23 C25 ENET_TXD<2>

RGMII 1
73 32 IN RGMII_RXC/MII_RXCLK RGMII_TXD2 OUT 32 73
73 32 IN ENET_RX_CTRL C22 RGMII_RXCTL/MII_RXDV RGMII_TXD3 D25 ENET_TXD<3> OUT 32 73

MII 0
9 IN MCP_MII_RXER F23 MII_RXER/GPIO_36 RGMII_TXC/MII_TXCLK D24 ENET_CLK125M_TXCLK OUT 32 73
9 IN MCP_MII_COL B26 MII_COL/GPIO_20/MSMB_DATA RGMII_TXCTL/MII_TXEN C26 ENET_TX_CTRL OUT 32 73 NOTE: All Apple products set strap to
24 18 8 =PP3V3_ENET_MCP_RMGT
9 IN MCP_MII_CRS B22 MII_CRS/GPIO_21/MSMB_CLK MII, RGMII products will enable
RGMII_MDC D21 ENET_MDC OUT 32 73
feature via software. This
R1810
1 TP_ENET_INTR_L J22 RGMII_INTR/GPIO_35 RGMII_MDIO C21 ENET_MDIO BI 32 73
avoids a leakage issue since
49.9
1% RGMII_PWRDWN/GPIO_37 G23 TP_ENET_PWRDWN_L MCP79 requires a S5 pull-up.
1/16W
MF-LF 24 PP1V05_ENET_MCP_PLL_MAC T23 +V_DUAL_MACPLL
402
2 5 mA (A01) BUF_25MHZ E23 MCP_CLK25M_BUF0_R 33 73
OUT
73 MCP_MII_COMP_VDD C27 MII_COMP_VDD =PP3V3_S0_MCP_GPIO 8 19 21
73 MCP_MII_COMP_GND B27 MII_COMP_GND MII_RESET# J23 ENET_RESET_L OUT 32 73
R1860 R1861
1
PP3V3_S0_MCP_DAC 25 100K 100K
R1811 1 +V_RGB_DAC J32 103 mA 206 mA (A01) 5% 5%
1/16W 1/16W
49.9 MF-LF MF-LF
+V_TV_DAC K32 103 mA
1%
NO_TEST=TRUE NC_MCP_RGB_DAC_RSET C39 402 402
2
1/16W RGB_DAC_RSET
MF-LF
402 TP_MCP_RGB_DAC_VREF B38 RGB_DAC_VREF
2
DDC_CLK0 B31 MCP_DDC_CLK0
DDC_DATA0 A31 MCP_DDC_DATA0
DACS
C B39 NC_MCP_RGB_RED NO_TEST=TRUE
C
RGB_DAC_RED
RGB_DAC_GREEN A39 NC_MCP_RGB_GREEN NO_TEST=TRUE
RGB ONLY
OUT MCP_TV_DAC_RSET
71 9 E36 TV_DAC_RSET
RGB_DAC_BLUE B40 NC_MCP_RGB_BLUE NO_TEST=TRUE
OUT MCP_TV_DAC_VREF
71 9 A35 TV_DAC_VREF
RGB_DAC_HSYNC A40 NC_MCP_RGB_HSYNC NO_TEST=TRUE
RGB_DAC_VSYNC A41 NC_MCP_RGB_VSYNC NO_TEST=TRUE
TV / Component
C / Pr TV_DAC_RED A36 CRT_IG_R_C_PR OUT 68 71
20 8 =PP3V3_S5_MCP_GPIO
Y / Y TV_DAC_GREEN B36 CRT_IG_G_Y_Y OUT 68 71
26 IN MCP_CLK27M_XTALIN C38 XTALIN_TV
R1820 1 MCP_CLK27M_XTALOUT D38
Comp / Pb TV_DAC_BLUE C36 CRT_IG_B_COMP_PB OUT 68 71
47K 26 OUT XTALOUT_TV
5% TV_DAC_HSYNC/GPIO_44 D36 CRT_IG_HSYNC OUT 68 71
1/16W TV DAC Disable:
MF-LF TV_DAC_VSYNC/GPIO_45 C37 CRT_IG_VSYNC OUT 68 71
402 2
Okay to float all TV_DAC signals.
BI
LPCPLUS_GPIO E16 GPIO_6/FERR*/IGPU_GPIO_6 IFPA_TXC_P B35 LVDS_IG_A_CLK_P OUT 66 71 Okay to float XTALIN_TV and XTALOUT_TV.
67 IN DP_IG_CA_DET B15 GPIO_7/NFERR*/IGPU_GPIO_7 IFPA_TXC_N C35 LVDS_IG_A_CLK_N OUT 66 71 DDC_CLK0/DDC_DATA0 pull-ups still required.
43 7
IFPA_TXD0_P B32 LVDS_IG_A_DATA_P<0> OUT 7 66 71

Interface Mode 66 OUT LVDS_IG_BKL_PWM G39 LCD_BKL_CTL/GPIO_57
IFPA_TXD0_N A32 LVDS_IG_A_DATA_N<0> OUT 7 66 71
66 OUT LVDS_IG_BKL_ON E37 LCD_BKL_ON/GPIO_59
IFPA_TXD1_P D32 LVDS_IG_A_DATA_P<1> OUT 7 66 71
LVDS_IG_PANEL_PWR
FLAT PANEL
66 F40 LCD_PANEL_PWR/GPIO_58
OUT C32 LVDS_IG_A_DATA_N<1>
MCP Signal TMDS/HDMI DisplayPort IFPA_TXD1_N OUT 7 66 71
IFPA_TXD2_P D33 LVDS_IG_A_DATA_P<2> OUT 7 66 71

=MCP_HDMI_TXC_P/N TMDS_IG_TXC_P/N DP_IG_ML_P/N<3> 67 OUT MCP_HDMI_TXC_P D35 HDMI_TXC_P/ML0_LANE3_P
IFPA_TXD2_N C33 LVDS_IG_A_DATA_N<2> OUT 7 66 71
=MCP_HDMI_TXD_P/N<0> TMDS_IG_TXD_P/N<0> DP_IG_ML_P/N<2> 67 OUT MCP_HDMI_TXC_N E35 HDMI_TXC_N/ML0_LANE3_N
IFPA_TXD3_P B34 LVDS_IG_A_DATA_P<3> OUT 9 71
=MCP_HDMI_TXD_P/N<1> TMDS_IG_TXD_P/N<1> DP_IG_ML_P/N<1>
67 OUT MCP_HDMI_TXD_P<0> G35 HDMI_TXD0_P/ML0_LANE2_P IFPA_TXD3_N C34 LVDS_IG_A_DATA_N<3> OUT 9 71
=MCP_HDMI_TXD_P/N<2> TMDS_IG_TXD_P/N<2> DP_IG_ML_P/N<0>
67 OUT MCP_HDMI_TXD_N<0> F35 HDMI_TXD0_N/ML0_LANE2_N WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases
=MCP_HDMI_DDC_CLK TMDS_IG_DDC_CLK DP_IG_DDC_CLK
67 MCP_HDMI_TXD_P<1> F33 HDMI_TXD1_P/ML0_LANE1_P
B =MCP_HDMI_DDC_DATA
=MCP_HDMI_HPD
TMDS_IG_DDC_DATA
TMDS_IG_HPD
DP_IG_DDC_DATA
DP_IG_HPD
67
OUT
OUT MCP_HDMI_TXD_N<1> G33 HDMI_TXD1_N/ML0_LANE1_N
IFPB_TXC_P
IFPB_TXC_N
L31
K31
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
OUT
OUT
9 71
9 71
B
67 OUT MCP_HDMI_TXD_P<2> J33 HDMI_TXD2_P/ML0_LANE0_P
DP_IG_AUX_CH_P/N TP_DP_IG_AUX_CHP/N DP_IG_AUX_CH_P/N
67 OUT MCP_HDMI_TXD_N<2> H33 HDMI_TXD2_N/ML0_LANE0_N IFPB_TXD4_P J29 LVDS_IG_B_DATA_P<0> OUT 9 71
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used. IFPB_TXD4_N H29 LVDS_IG_B_DATA_N<0> OUT 9 71
NOTE: 20K pull-down required on DP_HOTPLUG_DET. OUT TP_DP_IG_AUX_CHP D43 DP_AUX_CH0_P IFPB_TXD5_P L29 LVDS_IG_B_DATA_P<1> OUT 9 71
OUT TP_DP_IG_AUX_CHN C43 DP_AUX_CH0_N IFPB_TXD5_N K29 LVDS_IG_B_DATA_N<1> OUT 9 71

NOTE: HDMI port requires level-shifting. IFP interface can
IFPB_TXD6_P L30 LVDS_IG_B_DATA_P<2> OUT 9 71
be used to provide HDMI or dual-channel TMDS without
9 IN DP_HOTPLUG_DET C31 HPLUG_DET2/GPIO_22 IFPB_TXD6_N K30 LVDS_IG_B_DATA_N<2> OUT 9 71
level-shifters.
67 IN MCP_HDMI_HPD F31 HPLUG_DET3 IFPB_TXD7_P N30 LVDS_IG_B_DATA_P<3> OUT 9 71
IFPB_TXD7_N M30 LVDS_IG_B_DATA_N<3> OUT 9 71

25 8 =PP3V3R1V8_S0_MCP_IFP_VDD
190 mA (A01, 1.8V) M27 +VDD_IFPA
M26 +VDD_IFPB DDC_CLK2/GPIO_23 C30 LVDS_IG_DDC_CLK OUT 7 66
25 PP3V3_S0_MCP_VPLL
DDC_DATA2/GPIO_24 B30 LVDS_IG_DDC_DATA BI 7 66
16 mA (A01) 8 mA M28 +V_PLL_IFPAB
8 mA M29 +V_PLL_HDMI
DDC_CLK3 D31 =MCP_HDMI_DDC_CLK OUT 67
25 8 =PP1V05_S0_MCP_HDMI_VDD T25 +VDD_HDMI DDC_DATA3 E31 =MCP_HDMI_DDC_DATA BI 67
95 mA (A01)
71 25 OUT MCP_HDMI_RSET J31 HDMI_RSET IFPAB_RSET E32 MCP_IFPAB_RSET OUT 25 71
71 25 OUT MCP_HDMI_VPROBE J30 HDMI_VPROBE IFPAB_VPROBE G31 MCP_IFPAB_VPROBE OUT 25 71
1
R1850
10K
5%
1/16W
MF-LF
402
2
A GPIO 57-59 ( IF LCD PANEL IS USED):

IN MCP79 THESE PINS HAVE UNDOCUMENTED PULL HIGH
PAGE TITLE
(~10K TO 3.3V). TO ENSURE PINS ARE LOW
BY DEFAULT, PULL DOWN(1K OR SRONGER) MUST BE USED
MCP Ethernet & Graphics
DRAWING NUMBER SIZE

REVISION
R
A.0.0
18 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400 21 18 8 =PP3V3_S0_MCP_GPIO
MCP79-TOPO-B
BGA
(7 OF 11)
72 19 PCI_REQ0_L T2 PCI_REQ0# PCI_GNT0# R3 TP_PCI_GNT0_L

19 MCP_RS232_SOUT_L R1989 8.2K 1 2
72 19 PCI_REQ1_L V9 PCI_REQ1#/FANRPM2 PCI_GNT1#/FANCTL2 U10 TP_PCI_GNT1_L 5% 1/16W MF-LF 402
19 OUT CRTMUX_SEL_TV_L T3 PCI_REQ2#/GPIO_40/RS232_DSR# PCI_GNT2#/GPIO_41/RS232_DTR# R4 GMUX_JTAG_TMS OUT 9 72 19 PCI_REQ0_L R1990 8.2K 1 2
5% 1/16W MF-LF 402
9 OUT AUD_IPHS_SWITCH_EN U9 PCI_REQ3#/GPIO_38/RS232_CTS# PCI_GNT3#/GPIO_39/RS232_RTS# U11 GMUX_JTAG_TDI OUT 9
72 19 PCI_REQ1_L R1991 8.2K 1 2
19 IN MCP_RS232_SIN_L T4 PCI_REQ4#/GPIO_52/RS232_SIN# PCI_GNT4#/GPIO_53/RS232_SOUT# P3 MCP_RS232_SOUT_L OUT 19 5% 1/16W MF-LF 402
D 72 13 7 BI MCP_DEBUG<0> AC3 PCI_AD0 PCI_CBE0# AA3 TP_PCI_C_BE_L<0>

19 CRTMUX_SEL_TV_L R1992 8.2K 1 2
5% 1/16W MF-LF 402 D
19 MCP_RS232_SIN_L R1994 8.2K 1 2
72 13 7 BI MCP_DEBUG<1> AE10 PCI_AD1 PCI_CBE1# AA6 TP_PCI_C_BE_L<1> 5% 1/16W MF-LF 402
72 13 7 BI MCP_DEBUG<2> AC4 PCI_AD2 PCI_CBE2# AA11 TP_PCI_C_BE_L<2>
72 13 7 BI MCP_DEBUG<3> AE11 PCI_AD3 PCI_CBE3# W10 TP_PCI_C_BE_L<3>
72 13 7 BI MCP_DEBUG<4> AB3 PCI_AD4
72 13 7 BI MCP_DEBUG<5> AC6 PCI_AD5 PCI_DEVSEL# AA9 TP_PCI_DEVSEL_L
72 13 7 BI MCP_DEBUG<6> AB2 PCI_AD6 PCI_FRAME# Y4 TP_PCI_FRAME_L
72 13 7 BI MCP_DEBUG<7> AC7 PCI_AD7 PCI_IRDY# AA10 TP_PCI_IRDY_L
TP_PCI_AD<8> AC8 PCI_AD8 PCI_PAR Y1 TP_PCI_PAR
TP_PCI_AD<9> AA2 PCI_AD9 PCI_PERR#/GPIO_43/RS232_DCD# AB9 TP_PCI_PERR_L
TP_PCI_AD<10> AC9 PCI_AD10 PCI_SERR# AA7 TP_PCI_SERR_L
TP_PCI_AD<11> AC10 PCI_AD11 PCI_STOP# Y2 TP_PCI_STOP_L
PCI
TP_PCI_AD<12> AC11 PCI_AD12
PCI_PME#/GPIO_30 T1 PM_LATRIGGER_L OUT 7 13
TP_PCI_AD<13> AA1 PCI_AD13
Int PU (S5)
TP_PCI_AD<14> AA5 PCI_AD14
TP_PCI_AD<15> Y5 PCI_AD15
TP_PCI_AD<16> W3 PCI_AD16 PCI_RESET0# R10 MEM_VTT_EN_R OUT 26
TP_PCI_AD<17> W6 PCI_AD17 PCI_RESET1# R11 TP_PCI_RESET1_L

TP_PCI_AD<18> W4 PCI_AD18
TP_PCI_AD<20> V3 PCI_AD20
PCI_CLK0 R6 TP_PCI_CLK0
PCI_CLK1 R7 TP_PCI_CLK1
TP_PCI_AD<22> V2 PCI_AD22
PCI_CLK2 R8 72 PCI_CLK33M_MCP_R
TP_PCI_AD<24> U3 PCI_AD24 1
TP_PCI_AD<25> W11 PCI_AD25 R1910
C TP_PCI_AD<26>
TP_PCI_AD<27>
U2
U5
PCI_AD26
22
5%
1/16W
C
PCI_AD27 MF-LF
402
TP_PCI_AD<28> U1 PCI_AD28 2
PLACEMENT_NOTE=Place close to pin R8
TP_PCI_AD<29> U6 PCI_AD29 PCI_CLKIN R9 72 PCI_CLK33M_MCP
TP_PCI_AD<30> T5 PCI_AD30
TP_PCI_AD<31> U7 PCI_AD31
TP_PCI_INTW_L P2 PCI_INTW#
TP_PCI_INTX_L N3 PCI_INTX#
LPC_FRAME# AD4 LPC_FRAME_R_L R1960 22 1 2 LPC_FRAME_L OUT 7 41 43 72
TP_PCI_INTY_L N2 PCI_INTY# 5% 1/16W MF-LF 402
LPC_PWRDWN#/GPIO_54/EXT_NMI# AE12 LPC_PWRDWN_L OUT 7 41 43
TP_PCI_INTZ_L N1 PCI_INTZ#
LPC_RESET0# AE5 LPC_RESET_L OUT 26 72
LPC
TP_PCI_TRDY_L Y3 PCI_TRDY#
LPC_AD0 AD3 LPC_AD_R<0> R1950 0 1 2 LPC_AD<0> BI 7 41 43 72
5% 1/16W MF-LF 402
43 41 7 IN PM_CLKRUN_L AD11 PCI_CLKRUN#/GPIO_42 LPC_AD1 AD2 LPC_AD_R<1> R1951 0 1 2 LPC_AD<1> BI 7 41 43 72
5% 1/16W MF-LF 402
LPC_AD2 AD1 LPC_AD_R<2> R1952 0 1 2 LPC_AD<2> BI 7 41 43 72
5% 1/16W MF-LF 402
35 IN FW_PME_L AE2 LPC_DRQ1#/GPIO_19 Int PU LPC_AD3 AD5 LPC_AD_R<3> R1953 0 1 2 LPC_AD<3> BI 7 41 43 72
5% 1/16W MF-LF 402
TP_LPC_DRQ0_L AE1 LPC_DRQ0# Int PU
43 41 7 BI LPC_SERIRQ AE6 LPC_SERIRQ Int PU LPC_CLK0 AE9 LPC_CLK33M_SMC_R OUT 26 72
1
U24 GND65 GND98 Y26 R1961
10K
U26 GND66 GND99 Y27 5%
1/16W
U39 GND67 GND100 AB18 MF-LF
402
U4 H34 2
GND68 GND101
U8 GND69 GND102 AB20 Strap for Boot ROM Selection (See HDA_SDOUT)
V16 GND70 GND103 AB21
B V17 GND71 GND104 AB23 B


GND

V4 GND81 GND114 AC22
W20 GND84 GND117 AB33
W22 GND85 GND118 AC5
W24 GND86 GND119 AD16
Y16 GND90 GND123 AD20
Y24 AD33
A Y25
GND96
GND97
GND129
GND130 AD34 SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 A
PAGE TITLE
MCP PCI & LPC

DRAWING NUMBER SIZE

REVISION
R
A.0.0
19 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400
MCP79-TOPO-B
BGA
(8 OF 11) External A
71 38 OUT SATA_HDD_R2D_C_P AJ7 SATA_A0_TX_P USB0_P C29 USB_EXTA_P BI 39 72
71 38 OUT SATA_HDD_R2D_C_N AJ6 SATA_A0_TX_N USB0_N D29 USB_EXTA_N BI 39 72
AirPort (PCIe Mini-Card)

71 38 IN SATA_HDD_D2R_N AJ5 SATA_A0_RX_N USB1_P C28 USB_MINI_P BI 9 72
71 38 IN SATA_HDD_D2R_P AJ4 SATA_A0_RX_P USB1_N D28 USB_MINI_N BI 9 72
External D
D USB2_P A28 USB_EXTD_P BI 9 72 D
USB2_N B28 USB_EXTD_N BI 9 72
71 38 OUT SATA_ODD_R2D_C_P AJ11 SATA_A1_TX_P Camera

71 38 OUT SATA_ODD_R2D_C_N AJ10 SATA_A1_TX_N USB3_P F29 USB_CAMERA_P BI 66 72
USB3_N G29 USB_CAMERA_N BI 66 72
71 38 IN SATA_ODD_D2R_N AJ9 SATA_A1_RX_N IR

71 38 IN SATA_ODD_D2R_P AK9 SATA_A1_RX_P USB4_P K27 USB_IR_P BI 40 72
USB4_N L27 USB_IR_N BI 40 72
Geyser Trackpad/Keyboard
USB5_P J26 USB_TPAD_P BI 9 72
TP_SATA_C_R2D_CP AK2 SATA_B0_TX_P USB5_N J27 USB_TPAD_N BI 9 72
TP_SATA_C_R2D_CN AJ3 SATA_B0_TX_N Bluetooth

USB6_P F27 USB_BT_P BI 9 72
TP_SATA_C_D2RN AJ2 SATA_B0_RX_N USB6_N G27 USB_BT_N BI 9 72
TP_SATA_C_D2RP AJ1 SATA_B0_RX_P External B
SATA
USB7_P D27 USB_EXTB_P
USB
BI 39 72
USB7_N E27 USB_EXTB_N BI 39 72
ExpressCard
TP_SATA_D_R2D_CP AM4 SATA_B1_TX_P USB8_P K25 USB_EXCARD_P BI 9 72 =PP3V3_S5_MCP_GPIO 8 18
TP_SATA_D_R2D_CN AL3 SATA_B1_TX_N USB8_N L25 USB_EXCARD_N BI 9 72
External C
TP_SATA_D_D2RN AL4 SATA_B1_RX_N USB9_P H25 USB_EXTC_P BI 9 72
1
1
R2053
TP_SATA_D_D2RP AK3 SATA_B1_RX_P USB9_N J25 USB_EXTC_N 9 72
R2051 8.2K
BI 8.2K 5%
5% 1/16W
1/16W MF-LF
USB10_P F25 TP_USB_10P MF-LF
2
402
402
USB10_N G25 TP_USB_10N 2
1
R2052
C TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN
AN1
AM1
SATA_C0_TX_P
SATA_C0_TX_N USB11_P K23 TP_USB_11P R2050 1
8.2K
8.2K
5%
C
1/16W
USB11_N L23 TP_USB_11N 5% MF-LF
1/16W 402
TP_SATA_E_D2RN AM2 SATA_C0_RX_N MF-LF
2
402
TP_SATA_E_D2RP AM3 SATA_C0_RX_P 2
USB_OC0#/GPIO_25 L21 USB_EXTA_OC_L IN 39
USB_OC1#/GPIO_26 K21 USB_EXTB_OC_L IN 39
USB_OC2#/GPIO_27/MGPIO J21 USB_EXTC_OC_L IN

TP_SATA_F_R2D_CP AP3 SATA_C1_TX_P USB_OC3#/GPIO_28/MGPIO H21 EXCARD_OC_L IN 42
TP_SATA_F_R2D_CN AP2 SATA_C1_TX_N
+V_PLL_USB L28 PP3V3_S0_MCP_PLL_USB 24

TP_SATA_F_D2RN AN3 SATA_C1_RX_N
19 mA (A01)
TP_SATA_F_D2RP AN2 SATA_C1_RX_P
USB_RBIAS_GND A27 72 MCP_USB_RBIAS_GND
1
R2060
TP_MCP_SATALED_L E12 SATA_LED# GND131 AD35 806
1%
GND132 AD37 1/16W
MF-LF
GND133 AD38 402
24 PP1V05_S0_MCP_PLL_SATA AE16 +V_PLL_SATA 2
GND134 AE22
84 mA (A01) AE24
GND135
8 =PP1V05_S0_MCP_SATA_DVDD0
GND136 AE39
43 mA (A01) AF19 +DVDD0_SATA1
GND137 AE4
AG16 +DVDD0_SATA2
GND138 AD6
AG17 +DVDD0_SATA3
GND139 AF16
AG19 +DVDD0_SATA4
GND140 AF17
GND141 AF18
=PP1V05_S0_MCP_SATA_DVDD1
B 8 AH17
AH19
+DVDD1_SATA1
+DVDD1_SATA2
GND142 AF20 B
GND143 AF22
8 =PP1V05_S0_MCP_SATA_AVDD0 GND144 AF26
127 mA (A01) AJ12 +AVDD0_SATA1 GND145 AF27

AN11 +AVDD0_SATA2 GND146 AF28
AK12 +AVDD0_SATA3 GND147 AF33
AK13 +AVDD0_SATA4 GND148 AF34
AL12 +AVDD0_SATA5 GND149 AF37
AM11 +AVDD0_SATA6 GND150 AF40
AM12 +AVDD0_SATA7 GND151 AG18
AN12 +AVDD0_SATA8 GND152 AG20
AL13 +AVDD0_SATA9 GND153 AG22
GND154 AG26
8 =PP1V05_S0_MCP_SATA_AVDD1 AN14 +AVDD1_SATA1 GND155 AG36

AL14 +AVDD1_SATA2 GND156 AG40
AM13 +AVDD1_SATA3 GND157 AH18
AM14 +AVDD1_SATA4 GND158 AH20
GND159 AH22
71 MCP_SATA_TERMP AE3 SATA_TERMP GND160 AH24
1
R2010
2.49K
1%
1/16W
MF-LF
402
2
PAGE TITLE
MCP SATA & USB

DRAWING NUMBER SIZE

REVISION
R
A.0.0
20 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
U1400 =PP3V3R1V5_S0_MCP_HDA 8 21 24
MCP79-TOPO-B
BGA 7 mA (A01)
(9 OF 11)
J16 1
+V_DUAL_HDA1 R2160
+V_DUAL_HDA2 K16 8.2K
5%
1/16W
HDA
D MF-LF
2 402 R2170
22
72 52 IN HDA_SDIN0 G15 HDA_SDATA_IN0 HDA_SDATA_OUT F15 72 21 HDA_SDOUT_R 1 2 HDA_SDOUT OUT 52 72
Int PD 5%
1/16W
MF-LF
BIOS Boot Select
R2171 402
22
TP_MLB_RAM_SIZE J14 HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK HDA_BITCLK E15 72 21 HDA_BIT_CLK_R 1 2 HDA_BIT_CLK OUT 52 72 I/F HDA_SDOUT LPC_FRAME#
Int PD 5%
1/16W
MF-LF
402 R2172 LPC 0 0
22
TP_MLB_RAM_VENDOR J15 HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA HDA_RESET* K15 72 21 HDA_RST_R_L 1 2 HDA_RST_L OUT 52 72
24 21 8 =PP3V3R1V5_S0_MCP_HDA
Int PD 5%
PCI 0 1
1/16W
MF-LF
1 R2173 402 SPI0 1 0
R2110 22
49.9 HDA_SYNC L15 72 21 HDA_SYNC_R 1 2 HDA_SYNC OUT 52 72
1%
1/16W 5%
1/16W
SPI1 1 1
MF-LF
402 MF-LF
2 402
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
72 MCP_HDA_PULLDN_COMP A15 HDA_PULLDN_COMP HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK K17 MCP_GPIO_4 OUT 21
HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA L17 AUD_I2C_INT_L IN 21 R1961 and R2160 selects SPI0 ROM by

24 PP1V05_S0_MCP_PLL_NV default, LPC+ debug card pulls
37 mA (A01) 20 mA AE18 +V_PLL_NV_H SLP_S3* G17 PM_SLP_S3_L OUT 33 36 41 64 LPC_FRAME# high for SPI1 ROM override.
17 mA AE17 +V_PLL_SP_SPREF SLP_RMGT* J17 PM_SLP_RMGT_L OUT 9
NOTE: MCP79 does not support FWH, only
SLP_S5* H17 PM_SLP_S4_L OUT 41 42 64
LPC ROMs. So Apple designs will
26 22 PP3V3_G3_RTC not use LPC for BootROM override.
43 OUT =SPI_CS1_R_L_USE_MLB L24 GPIO_1/PWRDN_OK/SPI_CS1
THERM_DIODE_P B11 MCP_THMDIODE_P OUT 47
42 41 36 33 IN SMC_ADAPTER_EN L26 GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L NOTE: MCP79 rev A01 does not support
THERM_DIODE_N C11 MCP_THMDIODE_N OUT 47
=PP3V3_S0_MCP 8 22 24 SPI1 option.
1 1
R2120 R2121 TP_SB_A20GATE K13 A20GATE Int PU BOOT_MODE_SAFE
C 49.9K
1%
1/16W
49.9K
1%
1/16W
TP_MCP_KBDRSTIN_L L13 KBRDRSTIN* Int PU MCP_VID0/GPIO_13 L20 MCP_VID<0> OUT 21 61 1
R2180 C
MF-LF
402
MF-LF
402
41 IN SMC_WAKE_SCI_L C19 SIO_PME* Int PU (S5) MCP_VID1/GPIO_14 M20 MCP_VID<1> OUT 21 61 10K
5%
BUF_SIO_CLK Frequency
2 2
41 IN SMC_RUNTIME_SCI_L C18 EXT_SMI/GPIO_32* Int PU (S5) MCP_VID2/GPIO_15 M21 MCP_VID<2> OUT 21 61 1/16W
MF-LF Frequency
2
402 HDA_SYNC
SM_INTRUDER_L B20 INTRUDER*
SPKR C13 9 MCP_SPKR
24 MHz 1
BOOT_MODE_USER
TP_MCP_LID_L M25 LID* Int PU (S5) 1
41 IN PM_BATLOW_L M24 LLB* Int PU (S5) SMB_CLK0 L19 SMBUS_MCP_0_CLK OUT 7 13 44 72
R2181 14.31818 MHz 0
10K
SMB_DATA0 K19 SMBUS_MCP_0_DATA BI 7 13 44 72 5%
MISC
1/16W
69 60 IN PM_DPRSLPVR M22 CPU_DPRSLPVR SMB_CLK1/MSMB_CLK G21 SMBUS_MCP_1_CLK OUT 44 72 MF-LF
402
SMB_DATA1/MSMB_DATA F21 SMBUS_MCP_1_DATA BI 44 72
2
41 IN PM_PWRBTN_L C16 PWRBTN* Int PU (S5) SMB_ALERT*/GPIO_64 M23 AP_PWR_EN OUT 21 31 33 SPI Frequency Select
26 IN PM_SYSRST_DEBOUNCE_L D16 RSTBTN* Int PU
B12 MEM_EVENT_L
Frequency SPI_DO SPI_CLK
FANRPM0/GPIO_60 IN 21 28 29 41
RTC_RST_L C20 RTC_RST*
FANCTL0/GPIO_61 A12 ODD_PWR_EN_L OUT 38
FANRPM1/GPIO_63 D12 SMC_IG_THROTTLE_L 21 42

31 MHz 0 0
41 IN PM_RSMRST_L D20 PWRGD_SB
FANCTL1/GPIO_62 C12 ARB_DETECT 21
26 IN MCP_PS_PWRGD E20 PS_PWRGD 42 MHz 0 1
26 IN MCP_CPU_VLD C17 CPU_VLD CPUVDD_EN D17 MCP_CPUVDD_EN OUT 26 25 MHz 1 0
13 7 6 IN JTAG_MCP_TDI E19 JTAG_TDI Int PU

C14 SPI_CS0_R_L
1 MHz 1 1
SPI_CS0/GPIO_10 OUT 43 72
6 OUT JTAG_MCP_TDO F19 JTAG_TDO
SPI_CLK/GPIO_11 D13 SPI_CLK_R OUT 43 72
13 7 6 IN JTAG_MCP_TMS J19 JTAG_TMS Int PU NOTE: Straps not provided on this page.
SPI_DI/GPIO_8 C15 SPI_MISO IN 43
13 7 6 IN JTAG_MCP_TRST_L J18 JTAG_TRST*
SPI_DO/GPIO_9 B14 SPI_MOSI_R OUT 43 72
13 7 6 IN JTAG_MCP_TCK G19 JTAG_TCK
B R21591
10K 26 IN MCP_CLK25M_XTALIN A16 XTALIN SUS_CLK/GPIO_34 B18 PM_CLK32K_SUSCLK_R OUT 26 72
B
5%
1/16W 26 OUT MCP_CLK25M_XTALOUT B16 XTALOUT BUF_SIO_CLK AE7 TP_MCP_BUF_SIO_CLK
MF-LF
402
2
26 IN RTC_CLK32K_XTALIN A19 XTALIN_RTC TEST_MODE_EN K22 MCP_TEST_MODE_EN
26 OUT RTC_CLK32K_XTALOUT B19 XTALOUT_RTC PKG_TEST L22
R21221 R2150 1 1
R2163 1
R2190
100K 10K 10K 1K
5% 5% 5% 1%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
402 2 402 2 2 402 2 402
=PP3V3_S0_MCP_GPIO 8 18 19
HDA Output Caps 1 1 1 1

For EMI Reduction on HDA interface =PP3V3_S3_FET 8 65
R2143 R2140 R2141 R2142
10K 10K 10K 10K
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
HDA_SDOUT_R 21 72
1 2 402 2 402 2 402 2 402
HDA_BIT_CLK_R 21 72
R2146
100K AUD_I2C_INT_L 21
5%
HDA_RST_R_L 21 72 1/16W MEM_EVENT_L 21 28 29 41
MF-LF
HDA_SYNC_R 21 72 402 SMC_IG_THROTTLE_L 21 42
2
MCP_GPIO_4 21 MCP_VID<0> 21 61
A C2170
10PF
1
C2172
10PF
1 AP_PWR_EN 21 31 33
ARB_DETECT 21
MCP_VID<1>
MCP_VID<2>
21 61
21 61
5% 5% PAGE TITLE
50V
CERM
402
2
50V
CERM
402
2
1
R2147
1
R2155
1
R2156
1
R2157
MCP HDA & MISC
DRAWING NUMBER SIZE
100K 22K 22K 22K
1
C2171 1
C2173
5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W Apple Inc. 051-8089 D
10PF 10PF MF-LF MF-LF MF-LF MF-LF REVISION
2
5%
50V
2
5%
50V
2
402
2
402
2
402
2
402 R
A.0.0
CERM CERM
402 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
21 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
U1400 U1400
MCP79-TOPO-B MCP79-TOPO-B
BGA BGA
(11 OF 11) 61 46 24 8 =PPVCORE_S0_MCP (10 OF 11) =PP1V05_S0_MCP_FSB 8 14 24
AH26 GND161 GND253 AV40 23065 mA (A01, 1.2V) AA25 +VDD_CORE1 +VTT_CPU1 R32 1139 mA 1182 mA (A01)
AH33 GND162 GND254 BA1 16996 mA (A01, 1.0V) AC23 +VDD_CORE2 +VTT_CPU2 AC32
AH34 GND163 GND255 BA4 U25 +VDD_CORE3 +VTT_CPU3 E40

AH37 GND164 GND256 AW31 AH12 +VDD_CORE4 +VTT_CPU4 J36
AH38 GND165 GND257 AY6 AG10 +VDD_CORE5 +VTT_CPU5 N32
AJ39 GND166 GND258 L35 AG5 +VDD_CORE6 +VTT_CPU6 T32
D AJ8 GND167 GND259 BC33 Y21 +VDD_CORE7 +VTT_CPU7 U32 D

AK10 GND168 GND260 BC37 Y23 +VDD_CORE8 +VTT_CPU8 V32
AK33 GND169 GND261 BC41 AA16 +VDD_CORE9 +VTT_CPU9 W32
AK34 GND170 GND262 AY14 AA26 +VDD_CORE10 +VTT_CPU10 P31
AK37 GND171 GND263 BC5 AA27 +VDD_CORE11 +VTT_CPU11 AF32
AK4 GND172 GND264 C2 AA28 +VDD_CORE12 +VTT_CPU12 AE32
AK40 GND173 GND265 D10 AC16 +VDD_CORE13 +VTT_CPU13 AH32
AL36 GND174 GND266 D14 AC17 +VDD_CORE14 +VTT_CPU14 AJ32
AL40 GND175 GND267 D15 AC18 +VDD_CORE15 +VTT_CPU15 AK31
AL5 GND176 GND268 D18 AC19 +VDD_CORE16 +VTT_CPU16 AK32

AM10 GND177 GND269 D19 AC20 +VDD_CORE17 +VTT_CPU17 AD32
AM16 GND178 GND270 D22 AC21 +VDD_CORE18 +VTT_CPU18 AL31
AM18 GND179 GND271 D23 AA17 +VDD_CORE19 +VTT_CPU19 AB32
AM20 GND180 GND272 D26 AC24 +VDD_CORE20 +VTT_CPU20 B41
AM22 GND181 GND273 D30 AC25 +VDD_CORE21 +VTT_CPU21 B42
AM24 GND182 GND274 D37 AC26 +VDD_CORE22 +VTT_CPU22 C40
AM26 GND183 GND275 D6 AC27 +VDD_CORE23 +VTT_CPU23 C41
AM30 GND184 GND276 E13 AC28 +VDD_CORE24 +VTT_CPU24 C42
AM34 GND185 GND277 E17 AD21 +VDD_CORE25 +VTT_CPU25 D39
AM35 GND186 GND278 E21 AD23 +VDD_CORE26 +VTT_CPU26 D40
AM37 GND187 GND279 E25 W27 +VDD_CORE27 +VTT_CPU27 D41
AM38 GND188 GND280 E29 V25 +VDD_CORE28 +VTT_CPU28 E38
POWER
AM5 GND189 GND281 E33 AA18 +VDD_CORE29 +VTT_CPU29 E39
AM6 GND190 GND282 F12 AE19 +VDD_CORE30 +VTT_CPU30 F37
C AP26
AN28
GND193
GND194
GND285
GND286
F8
G10
AE25
AE26
+VDD_CORE33
+VDD_CORE34
+VTT_CPU33
+VTT_CPU34
G36
G37 C
AN30 GND195 GND287 G12 AE27 +VDD_CORE35 +VTT_CPU35 G38
AN39 GND196 GND288 G14 AE28 +VDD_CORE36 +VTT_CPU36 H35
AN4 GND197 GND289 G16 AF10 +VDD_CORE37 +VTT_CPU37 H37

Y7 GND198 GND290 BC12 AF11 +VDD_CORE38 +VTT_CPU38 J34
AP10 GND199 GND291 G22 AA19 +VDD_CORE39 +VTT_CPU39 J35
AU26 GND200 GND292 G24 AF2 +VDD_CORE40 +VTT_CPU40 K33
AP14 GND201 GND293 AW20 AF21 +VDD_CORE41 +VTT_CPU41 K34
AU14 GND202 GND294 G34 AF23 +VDD_CORE42 +VTT_CPU42 K35
AP28 GND203 GND295 G4 AF25 +VDD_CORE43 +VTT_CPU43 L32
GND

AP36 GND206 GND298 G8 AF7 +VDD_CORE46 +VTT_CPU46 M31
AP37 GND207 GND299 H11 AH23 +VDD_CORE47 +VTT_CPU47 M32
AP4 GND208 GND300 H15 AF9 +VDD_CORE48 +VTT_CPU48 M33
AP40 GND209 GND301 AW35 AA20 +VDD_CORE49 +VTT_CPU49 N31
AP7 GND210 GND302 H23 AG11 +VDD_CORE50 +VTT_CPU50 P32

AW23 GND211 GND303 AN8 AG12 +VDD_CORE51 +VTT_CPU51 Y32
AR28 GND212 GND304 G40 AG21 +VDD_CORE52 +VTT_CPU52 AA32
AR32 GND213 GND305 J12 AG23 +VDD_CORE53
AR40 GND214 GND306 J8 AG25 +VDD_CORE54 +VTT_CPUCLK AG32 43 mA
AT10 GND215 GND307 K10 AG3 +VDD_CORE55
AR12 GND216 GND308 K12 AG4 +VDD_CORE56
AT13 GND217 GND309 K18 AA21 +VDD_CORE57
=PP3V3_S0_MCP 8 21 24
+3.3V_1 AD10 450 mA (A01)
B AT6 GND220 GND312 K4 AG8 +VDD_CORE60
+3.3V_2
+3.3V_3
AE8
AB10
B
+3.3V_4 AD9
AT9 GND222 GND314 K8 AH1 +VDD_CORE62
+3.3V_5 Y10
AY21 GND223 GND315 AU1 AH10 +VDD_CORE63
+3.3V_6 AB11
AY22 GND224 GND316 L40 AH11 +VDD_CORE64
+3.3V_7 AA8
L12 GND225 GND317 L43 W26 +VDD_CORE65
+3.3V_8 Y9
AU12 GND226 GND318 L5 AH2 +VDD_CORE66
AU28 GND227 GND319 M10 AA23 +VDD_CORE67
AP33 GND228 GND320 M34 W28 +VDD_CORE68
AU32 GND229 GND321 M35 AH25 +VDD_CORE69 =PP3V3_S5_MCP 8 24
AR30 GND230 GND322 M37 AH21 +VDD_CORE70 +3.3V_DUAL1 G18 16 mA 266 mA (A01)
AU36 GND231 GND323 Y28 AH3 +VDD_CORE71 +3.3V_DUAL2 H19
AU38 GND232 GND324 Y33 AH4 +VDD_CORE72 +3.3V_DUAL3 J20
AU4 GND233 GND325 Y34 AH5 +VDD_CORE73 +3.3V_DUAL4 K20
G28 GND234 GND326 Y35 AH6 +VDD_CORE74
F20 GND235 GND327 Y37 AH7 +VDD_CORE75 +3.3V_DUAL_USB1 G26 250 mA
AV28 GND236 GND328 Y38 AH9 +VDD_CORE76 +3.3V_DUAL_USB2 H27
AV32 GND237 GND329 AB17 AA24 +VDD_CORE77 +3.3V_DUAL_USB3 J28
AV36 GND238 GND330 AB16 W21 +VDD_CORE78 +3.3V_DUAL_USB4 K28
AV4 GND239 GND331 AN26 W23 +VDD_CORE79
AV7 GND240 GND332 AD7 W25 +VDD_CORE80
AW11 GND241 GND333 M11 AF12 +VDD_CORE81
=PP1V05_S5_MCP_VDD_AUXC 8 24
G20 GND242 GND334 AA4
+VDD_AUXC1 T21 105 mA (A01)
AR43 GND243 GND335 AB19 26 21 PP3V3_G3_RTC
+VDD_AUXC2 U21
AW43 GND244 GND336 AY13 10 uA (G3) A20 +VBAT +VDD_AUXC3 V21
AY10 P11
A AV12
GND245
GND246
GND337
GND338 Y6
80 uA (S0)
AY30 GND247 GND339 T11 PAGE TITLE
AY33 GND248 GND340 V11 MCP Power & Ground
AY34 GND249 GND341 Y11 DRAWING NUMBER SIZE
AY37 GND250 GND342 AH16
AY38 GND251 GND343 T22 REVISION
AY41 GND252
R
A.0.0
22 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
B B
PAGE TITLE
MCP79 A01 Silicon Support

DRAWING NUMBER SIZE

REVISION
R
A.0.0
24 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP Core Power NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
61 46 22 8 =PPVCORE_S0_MCP
23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)
C2500 1 C2501 1 C2502 1 C2503 1 1 C2504 1 C2505 1 C2506 1 C2507 1 C2508 1 C2509 1 C2510 1 C2511 1 C2512 1 C2513
(No IG vs. EG data) 4.7UF 4.7UF 4.7UF 4.7UF 1UF 1UF 1UF 1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 10% 10% 10% 10% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
X5R 2 X5R 2 X5R 2 X5R 2 2 X5R 2 X5R 2 X5R 2 X5R 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402-1 402-1 402-1 402-1 402 402 402 402 402 402
D MCP PCIE (DVDD) Power MCP SATA (DVDD) Power

L2570 NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF) D
30-OHM-5A Apple: 5x 2.2uF 0402 (11 uF)
8 =PP1V05_S0_MCP_PEX_DVDD 8 =PP1V05_S0_MCP_SATA_DVDD 8 =PP1V05_S0_MCP_AVDD_UF PP1V05_S0_MCP_PEX_AVDD 7 8
1 2
57 mA (A01) 43 mA (A01) 333 mA (A01) MIN_NECK_WIDTH=0.2 MM 206 mA (A01)
VOLTAGE=1.05V
0603
1 1 1 1 1 1 1 1 1 1 1 1
C2515 C2516 C2517 C2518 C2519 C2520 C2521 C2570 C2571 C2572 C2573 C2574
4.7UF 1UF 1UF 0.1uF 0.1uF 4.7UF 0.1uF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 10% 10% 20% 20% 20% 20% 20% 20% 20% 20% 20%
4V 10V 10V 10V 10V 4V 10V 6.3V 6.3V 6.3V 6.3V 6.3V
X5R 2 2 X5R 2 X5R 2 CERM 2 CERM X5R 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402-1 402-1 402 402 402 402 402-LF 402-LF 402-LF 402-LF 402-LF
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

MCP 1.05V AUX Power MCP 1.05V RMGT Power
L2575 Apple: 2x 2.2uF 0402 (4.4 uF)
=PP1V05_S5_MCP_VDD_AUXC =PP1V05_ENET_MCP_RMGT 30-OHM-5A PP1V05_S0_MCP_SATA_AVDD
22 8 18 8 7 8
1 2
105 mA (A01) 131 mA (A01) MIN_NECK_WIDTH=0.2 MM 127 mA (A01)
VOLTAGE=1.05V
0603
1 1 1 1 1 1
C2525 C2526 C2528 C2529 C2575 C2576
0.1uF 0.1uF 4.7uF 0.1uF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20%
10V 10V 4V 10V 6.3V 6.3V
2 CERM 2 CERM X5R 2 2 CERM 2 CERM 2 CERM
402 402 402 402 402-LF 402-LF
MCP FSB (VTT) Power NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
L2580
Apple: 7x 2.2uF 0402 (15.4 uF) 30-OHM-1.7A
22 14 8 =PP1V05_S0_MCP_FSB 8 =PP1V05_S0_MCP_PLL_UF PP1V05_S0_MCP_PLL_FSB 14
1 2
1182 mA (A01) 562 mA (A01) MIN_NECK_WIDTH=0.2 MM 270 mA (A01)
VOLTAGE=1.05V
0402
C 1 C2530
2.2UF
1 C2531
2.2UF
1 C2532
2.2UF
1 C2533
2.2UF
1 C2534
2.2UF
1 C2535
2.2UF
1 C2536
2.2UF
C2580
4.7UF
1 1 C2581
0.1UF
C
20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 4V 10V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM X5R 2 2 CERM
402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402-LF 402 402
MCP Memory Power

L2582
=PP1V8R1V5_S0_MCP_MEM 30-OHM-1.7A PP1V05_S0_MCP_PLL_PEX
16 8 17
1 2
4771 MA (A01, DDR2) MIN_NECK_WIDTH=0.2 MM 84 mA (A01)
VOLTAGE=1.05V
0402
C2540 1 1 C2541 1 C2542 1 C2543 1 C2544 1 C2545 1 C2546 1 C2547 1 C2548 1 C2549 C2582 1 1 C2583
4.7UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 4.7UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
4V 10V 10V 10V 10V 10V 10V 10V 10V 10V 4V 10V
X5R 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM X5R 2 2 CERM
402 402 402 402 402 402 402 402 402 402 402 402
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP 3.3V Power NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF) L2584
L2555 Apple: 1x 2.2uF 0402 (2.2 uF) 30-OHM-1.7A PP1V05_S0_MCP_PLL_SATA
Apple: 4x 2.2uF 0402 (8.8 uF) 30-OHM-1.7A 20
22 21 8 =PP3V3_S0_MCP 8 =PP3V3_S0_MCP_PLL_UF PP3V3_S0_MCP_PLL_USB 20
1 2
1 2
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 84 mA (A01)
450 mA (A01) 19 mA (A01) MIN_NECK_WIDTH=0.2 MM 19 mA (A01) 0402
VOLTAGE=1.05V
VOLTAGE=3.3V
0402
1 1 1 1 1
C2584 1 1 C2585
C2550 C2551 C2552 C2553 C2555 4.7UF 0.1UF
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 20% 20%
20% 20% 20% 20% 20% 4V 10V
6.3V 6.3V 6.3V 6.3V 6.3V X5R 2 2 CERM
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 402 402
402-LF 402-LF 402-LF 402-LF 402-LF
B B
L2586
MCP 3.3V AUX/USB Power NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) MCP 3.3V Ethernet Power NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) 30-OHM-1.7A PP1V05_S0_MCP_PLL_CORE 16
Apple: 1x 2.2uF 0402 (2.2 uF) Apple: 1x 2.2uF 0402 (2.2 uF) MIN_LINE_WIDTH=0.4 MM
22 8 =PP3V3_S5_MCP 24 18 8 =PP3V3_ENET_MCP_RMGT 1 2
MIN_NECK_WIDTH=0.2 MM 87 mA (A01)
VOLTAGE=1.05V
0402
266 mA (A01) 83 mA (A01)
1 C2560 1 C2564 C2586 1 1 C2587
2.2UF 2.2UF 4.7UF 0.1UF
20% 20% 20% 20%
6.3V 6.3V 4V 10V
2 CERM 2 CERM X5R 2 2 CERM
402-LF 402-LF 402 402
L2588
MCP 3.3V/1.5V HDA Power NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) 30-OHM-1.7A PP1V05_S0_MCP_PLL_NV 21
Apple: 1x 2.2uF 0402 (2.2 uF) MIN_LINE_WIDTH=0.4 MM
21 8 =PP3V3R1V5_S0_MCP_HDA 1 2
MIN_NECK_WIDTH=0.2 MM 37 mA (A01)
VOLTAGE=1.05V
7 mA (A01) 0402
1 C2562 C2588 1 1 C2589 1 C2590

2.2UF 4.7UF 0.1UF 0.1UF
2
20%
6.3V MCP79 Ethernet VRef 20%
4V
2 2
20%
10V
2
20%
10V
CERM X5R CERM CERM
402-LF 402 402 402
24 18 8 =PP3V3_ENET_MCP_RMGT
R2591 1
1.47K
1%
A L2595
1/16W
MF-LF
402 2 SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 A
PAGE TITLE
30-OHM-1.7A
8 =PP1V05_ENET_MCP_PLL_MAC
5 mA (A01) 1 2
PP1V05_ENET_MCP_PLL_MAC
18
5 mA (A01)
MCP_MII_VREF OUT 18
MCP Standard Decoupling
VOLTAGE=1.05V DRAWING NUMBER SIZE
0402
R2590 1 1
C2591 051-8089 D
C2595 1 1 C2596 1.47K
1%
0.1UF Apple Inc. REVISION
4.7UF 0.1UF 1/16W
20%
20%
4V
2 2
20%
10V MF-LF
402 2
2
10V
CERM
R
A.0.0
X5R CERM 402
402 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
25 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) L2650 Apple: 2x 2.2uF 0402 (4.4 uF)
Apple: 1x 2.2uF 0402 (2.2 uF) 30-OHM-1.7A
8 =PP3V3_S0_MCP_DAC_UF 1 2 PP3V3_S0_MCP_DAC 18
18 8 =PP3V3R1V8_S0_MCP_IFP_VDD MIN_LINE_WIDTH=0.4 MM
206 mA (A01) 0402 MIN_NECK_WIDTH=0.2 MM
206 mA (A01)
190 mA (A01, 1.8V) VOLTAGE=3.3V
1 C2610 1 C2650 1 C2651
2.2UF 2.2UF 2.2UF
20% 20% 20%
6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM
402-LF 402-LF 402-LF
18 8 =PP1V05_S0_MCP_HDMI_VDD
95 mA (A01)
C 1
C
C2615 1
C2616
4.7UF 0.1UF
20%
4V
X5R
402
2 2
20%
10V
CERM
402
HDCP ROM
WF: Open question on which packge option(s) nVidia can support.
8 =PP3V3_S0_HDCPROM
C2690 1 R26901
0.1UF 8
NO STUFF 10K
5%
20%
10V
2
VCC 1/16W
MF-LF
CERM
402 U2695 402
2
71 18 MCP_HDMI_RSET 71 18 MCP_IFPAB_RSET AT24C08
SOIC
71 18 MCP_HDMI_VPROBE 71 18 MCP_IFPAB_VPROBE NO STUFF 1 A0 SDA 5 =I2C_HDCPROM_SDA BI 44
NO STUFF 1
R2620 NO STUFF 1
R2630
2
A1 SCL 6 =I2C_HDCPROM_SCL IN 44
C2620 1
1K C2630 1 1K 3
A2
0.1UF 1% 0.1UF 1%
20%
1/16W
20%
1/16W WP 7 25 HDCPROM_WP
MF-LF MF-LF
10V
CERM 2
2 402
10V
CERM 2
2 402
GND
402 402 4
4
NO STUFF
VCC
B U2690
AT24C01B
B
SOT23
3
SDA
25 HDCPROM_WP 5
WP
SCL 1
GND
2
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

L2640 NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
30-OHM-1.7A
Apple: ???
8 =PP3V3_S0_MCP_VPLL_UF 1 2 PP3V3_S0_MCP_VPLL 18
16 mA (A01) 0402 MIN_NECK_WIDTH=0.2 MM 16 mA (A01)
VOLTAGE=3.3V
C2640 1 1 C2641
4.7UF 0.1uF
20% 20%
6.3V 10V
CERM 2 2 CERM
603 402
PAGE TITLE
MCP Graphics Support

DRAWING NUMBER SIZE
SYNC FROM T18 Apple Inc. 051-8089 D
REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT R
REVISION
A.0.0
REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672 NOTICE OF PROPRIETARY PROPERTY: BRANCH
26 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RTC Power Sources

Platform Reset Connections
LPC Reset (Unbuffered)
1
VIN
U2870 R2881
MIC5232-2.8YD5 PLACEMENT_NOTE=Place close to U1400 33
TSOT-23-5 72 19 IN LPC_RESET_L 1 2 DEBUG_RESET_L OUT 7 43
D 8 =PP3V42_G3H_RTC_D 3 EN VOUT 5 PP3V3_G3_RTC

21 22
5%
1/16W
MF-LF R2883 D
MIN_NECK_WIDTH=0.2 mm 402 33
VOLTAGE=3.3V 1 2 SMC_LRESET_L 41
1 C2870 NC 4 1 C2871
1
R2801 C2801 5% PLACEMENT_NOTE=Place close to U1400
OUT
1UF NC 0.47UF 1%
100 10% 1
PLACE C2872 CLOSE MCP
1/16W
MF-LF
10% 10% 1/16W 1UF
6.3V 402
2 10V
X5R
GND 2 10V
X5R MF-LF
402-1 402 2 402 CERM 2
2
G3_RTC_L 402
1
C2800
0.08F
2%
2 3.3V
XHHG
SM
PCIE Reset (Unbuffered)
R2892
0
17 IN PCIE_RESET_L 1 2 BKLT_PLT_RST_L OUT 66
RTC Crystal C2810

12pF
5%
1/16W
21
MF-LF
RTC_CLK32K_XTALOUT 1 2 R2891 402
IN 0
1 2 MINI_RESET_L OUT 31
1 R2810
5%
50V
CERM
402
MCP 27MHZ CRYSTAL C2820
5%
1/16W
MF-LF
R2811 0 12pF 402 R2871
10M 1 2 RTC_CLK32K_XTALOUT_R MCP_CLK27M_XTALOUT 1 2 0
18
5% CRITICAL IN 1 2 PCA9557D_RESET_L OUT 27
5%
4
1/16W
MF-LF
402 2
1/16W
MF-LF
Y2810 5%
50V
5%
1/16W
402 MF-LF
32.768K C2811 CERM
402 R2872 402
12pF NO STUFF 0
1
7X1.5X1.4-SM 1 2 FW_RESET_L OUT 35
21 OUT RTC_CLK32K_XTALIN 1 2
R28211 R2820 5%
10M 0 1/16W
5% 1 2 MCP_CLK27M_XTALOUT_R
C 50V
CERM
5%
1/16W
MF-LF 5% CRITICAL
MF-LF
402 C
3
402 402 2 1/16W
4
MF-LF
402 Y2820 NC
C2815
2
MCP 25MHz Crystal 12pF
27MHZ
SM-2 NC
C2821
21
1
IN
MCP_CLK25M_XTALOUT 1 2 12pF
MCP_CLK27M_XTALIN 1 2
18 OUT
5%
50V
R2815 CERM 5%
50V
0 402
CERM
1 2 MCP_CLK25M_XTALOUT_R 402
NO STUFF 5%
1/16W
R28161 MF-LF CRITICAL R2870
402 3 33
MEM_VTT_EN_R MEM_VTT_EN =DDRVTT_EN
4
10M Y2815 NC 19 IN 1 2
OUT 59 65
5% MAKE_BASE=TRUE
1/16W 25.0000M 2 5%
MF-LF SM-3.2X2.5MM
NC 1/16W
C2816
1
402 MF-LF
2 12pF 402
MCP_CLK25M_XTALIN 1 2
21 OUT R2825
5%
PLACEMENT_NOTE=Place close to U1400 22
50V 72 19 IN LPC_CLK33M_SMC_R 1 2 LPC_CLK33M_SMC OUT 41 72
CERM 5%
402 1/16W
MF-LF R2826
402 0
1 2 LPC_CLK33M_LPCPLUS OUT 7 43 72
Reset Button PLACEMENT_NOTE=Place close to U1400 5%

1/16W
MF-LF
402
1 C2826
10PF
5%
41 IN PM_SYSRST_L 2 50V
CERM
NO STUFF 402
XDP R2829
R2898 R2899 10K pull-up to 3.3V S0 inside MCP 22
72 21 IN PM_CLK32K_SUSCLK_R 1 2 PM_CLK32K_SUSCLK OUT 41 72
0 33
13 10 7 IN XDP_DBRESET_L 1 2 1 2 PM_SYSRST_DEBOUNCE_L OUT 21 PLACEMENT_NOTE=Place close to U1400 5%
1/16W
B 5%
1/16W
MF-LF R28901
NO STUFF 5%
1/16W
MF-LF 1
NO STUFF
C2899
MF-LF
402 B
402 0 402
1UF
5% 10%
1/16W 10V
MF-LF SILK_PART=SYS RST 2
X5R
402 2 402
MCP S0 PWRGD
8 =PP3V3_S5_MCPPWRGD
1 C2850
0.1UF
20%
10V
2 CERM
402
5 TC7SZ08AFEAPE
64 41 7 IN ALL_SYS_PWRGD 2
A
SOT665
U2850Y
4 MCP_PS_PWRGD OUT 21
60 IN VR_PWRGOOD_DELAY 1
B
PAGE TITLE
SYNC FROM T18 SB Misc

R2853 DRAWING NUMBER SIZE
CHANGE RESET BUTTOM TO RESET PADS MCP_CPUVDD_EN 21 IN
1
0
2 MCP_CPU_VLD OUT 21 Apple Inc. 051-8089 D
REMOVE UNUSED PCIE RESET SIGNALS PLACEMENT_NOTE=Place close to U1400 5%
1/16W
R
REVISION
A.0.0
REMOVE R2824 AND NET PCI_CLK33M_SLOT_A MF-LF
402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
CHANGE RTC POWER SOURCE FROM COIN CELL TO SUPER CAPS THE INFORMATION CONTAINED HEREIN IS THE
ALIAS MEM_VTT_EN TO =DDRVTT_EN I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
28 OF 109
CHANGE Y2810 AND U2850 TO SMALLER PARTS III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PP3V3_S3_VREFMRGN
- =PP3V3_S5_VREFMRGN
Voltage divider resistor values at op-amp outputs not yet finalized.
- =PPVTT_S3_DDR_BUF

- =I2C_VREFDACS_SCL
- =I2C_VREFDACS_SDA
BOM OPTION TO SELECT VREF SOURCE
- =I2C_PCA9557D_SCL
- =I2C_PCA9557D_SDA =PPVTT_S3_DDR_BUF
59 8
D BOM options provided by this page: 10mA max load D

VREFMRGN AND NO VERFMRGN
R2903 NO_VREFMRGN
1
0 2
5%
1/16W
MF-LF MEM_VREF_A
VREFMRGN B1
U2902 402
28
C2
1 C2903 V+
MAX4253
UCSP R2904 VREFMRGN MIN_NECK_WIDTH=0.25 mm
0.1UF 100
20% VREFMRGN C1 VREFMRGN_DQ_SODIMMA_BUF 1 2
10V 1%
2 CERM C3 C4 Place close to J3100.1
=PP3V3_S3_VREFMRGN 402 V- 1/16W
8 27 VREFMRGN_DQ_SODIMMA_EN MF-LF
B4 402
VREFMRGN VREFMRGN R2905 NO_VREFMRGN
R2901
2
1 C2900 1 C2901 1
0 2
2.2UF 0.1UF 100K VREFMRGN
20% 20% 5% 5%
6.3V 10V 1/16W 1/16W
2 CERM 2 CERM
MF-LF MF-LF MEM_VREF_B
1
402-LF 402 402 402
A2
B1 U2902 MIN_LINE_WIDTH=0.25 mm
29
V+
MAX4253
UCSP
R2906 VREFMRGN MIN_NECK_WIDTH=0.25 mm
100
VREFMRGN VREFMRGN A1 VREFMRGN_DQ_SODIMMB_BUF 1 2
8 U2900
1%
A3 A4 1/16W Place close to J3200.1
V- VREFMRGN_DQ_SODIMMB_EN MF-LF
VDD B4
27
402
44 IN =I2C_VREFDACS_SCL 6 SCL MSOP VOUTA 1 VREFMRGN_DQ_SODIMM
R2902
2
DAC5574
44 BI =I2C_VREFDACS_SDA 7 SDA VOUTB 2
100K VREFMRGN
9 A0 VOUTC 4 VREFMRGN_CPUFSB 5%
1/16W
MF-LF
ADDR=0x98(WR)/0x99(RD)
1
10 A1 VOUTD 5
C NC 402
C
GND
3
B1
U2904
C2
MAX4253
VREFMRGN V+ UCSP
1 C2905 VREFMRGN C1
0.1UF
20% C3 C4 NC
2 10V V-
CERM B4
402
B B
A2
B1 U2904
VREFMRGN V+
MAX4253 R2914 VREFMRGN
UCSP
1 C2902 100
16
VREFMRGN VREFMRGN A1 VREFMRGN_CPUFSB_BUF 1 2 CPU_GTLREF

0.1UF OUT 10 69
20% VCC 1%
2 10V A3 A4 1/16W Place close to U1000.AD26
CERM
402 U2901 V-
B4
27 VREFMRGN_CPUFSB_EN MF-LF
402
PCA9557
QFN 6
P0 R2913
2
NC VREFMRGN_CPUFSB_EN
3 A0 P1 7 27
100K VREFMRGN
4 A1 P2 9 5%
ADDR=0x30(WR)/0x31(RD) NC VREFMRGN_DQ_SODIMMA_EN 1/16W
5 A2 P3 10 27 MF-LF
1
402
P4 11
NC VREFMRGN_DQ_SODIMMB_EN
P5 12 27
44 IN =I2C_PCA9557D_SCL 1 SCL P6 13
NC
44 =I2C_PCA9557D_SDA 2 SDA P7 14
BI NC TABLE_5_HEAD
PCA9557D_RESET_L PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

RESET* 15 26
THRM IN TABLE_5_ITEM
PAD GND 114S0149 1 RES, MTL FILM, 200, 1%, 0402, SM, LF R2903 VREFMRGN
17
TABLE_5_ITEM
114S0149 1 RES, MTL FILM, 200, 1%, 0402, SM, LF R2905 VREFMRGN
PAGE TITLE
FSB/DDR2 VREF MARGINING

DRAWING NUMBER SIZE

REVISION
R
A.0.0
29 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
29 28 8 =PP1V8_S3_MEM DIP DIMM CONN201 =GND_CHASSIS_DIPDIMM_CENTER 9
29
=PP1V8_S3_MEM 8 28 29
27 MEM_VREF_A 1 2
VREF
3 CRITICAL VSS0 4 MEM_A_DQ<4>
VSS1 DQ4 15 70
1 C3100 C3101
1 70 15 MEM_A_DQ<3> 5
DQ0
J3100 DQ5
6 MEM_A_DQ<1> 15 70
2.2UF
20%
0.1UF 20% 70 15 MEM_A_DQ<6> 7
DQ1
F-RT-TH4 VSS2
8
DDR2-SODIMM-STD
4V
2 X5R 2 10V 9 10 MEM_A_DM<0>
CERM VSS4 DM0 15 70
402 402 70 15 MEM_A_DQS_N<0> 11 12
DQS0* VSS5
MEM_A_DQS_P<0> 13 14 MEM_A_DQ<5>
70 15 DQS0 DQ6 15 70
15 16 MEM_A_DQ<0>
VSS6 DQ7 15 70
70 15 MEM_A_DQ<7> 17 18
DQ2 VSS7
70 15 MEM_A_DQ<2> 19 20 MEM_A_DQ<13> 15 70
DQ3 DQ12
21 22 MEM_A_DQ<9> 15 70
VSS8 DQ13
D 70 15 MEM_A_DQ<12> 23
25
DQ8 VSS9
24
26
D
70 15 MEM_A_DQ<8> DQ9 DM1 MEM_A_DM<1> 15 70
27 28
VSS10 VSS11
70 15 MEM_A_DQS_N<1> 29 30 MEM_A_CLK_P<0> 15 70
DQS1* CK0
MEM_A_DQS_P<1> 31 32 MEM_A_CLK_N<0>
70 15 DQS1 CK0* 15 70
33 34
VSS12 VSS13
70 15 MEM_A_DQ<15> 35 36 MEM_A_DQ<10> 15 70
DQ10 DQ14
70 15 MEM_A_DQ<14> 37 38 MEM_A_DQ<11> 15 70
DQ11 DQ15
39 40
VSS14 VSS15
KEY
41 42
VSS16 VSS17
MEM_A_DQ<24> 43 44 MEM_A_DQ<29>
70 15 DQ16 DQ20 15 70
MEM_A_DQ<25> 45 46 MEM_A_DQ<28>
70 15 DQ17 DQ21 15 70
47 48
VSS18 VSS19
70 15 MEM_A_DQS_N<3> 49 50 MEM_EVENT_L 21 29 41
DQS2* NC0
70 15 MEM_A_DQS_P<3> 51 DQS2 DM2
52 MEM_A_DM<3> 15 70
53 54
VSS21 VSS22
70 15 MEM_A_DQ<31> 55 56 MEM_A_DQ<26> 15 70
DQ18 DQ22
70 15 MEM_A_DQ<30> 57 58 MEM_A_DQ<27> 15 70
DQ19 DQ23
59 60
VSS23 VSS24
70 15
70 15
MEM_A_DQ<19>
MEM_A_DQ<17>
61
63
65
DQ24
DQ25
DQ28
DQ29
62
64
66
MEM_A_DQ<18>
MEM_A_DQ<21>
15 70
15 70
Page Notes
VSS25 VSS26 Power aliases required by this page:
70 15 MEM_A_DM<2> 67 68 MEM_A_DQS_N<2> 15 70 - =PP1V8_S3_MEM
DM3 DQS3*
NC 69 70 MEM_A_DQS_P<2> - =PPSPD_S0_MEM (2.5V - 3.3V)
NC1 DQS3 15 70
71 72
VSS27 VSS28
MEM_A_DQ<23> 73 74 MEM_A_DQ<16> Signal aliases required by this page:
70 15 DQ26 DQ30 15 70
C 70 15 MEM_A_DQ<22> 75
77
DQ27 DQ31
76
78
MEM_A_DQ<20> 15 70
- =I2C_MEM_SCL
- =I2C_MEM_SDA C
VSS29 VSS30
MEM_A_CKE<0> 79 80 MEM_A_CKE<1> BOM options provided by this page:
70 30 15 CKE0 NC/CKE1 15 30 70
81 82 (NONE)
VDD0 VDD1
NC 83 84 NC MEM_A_A<15> 9
NC2 NC/A15
70 30 15 MEM_A_BA<2> 85 86 NC MEM_A_A<14> 15 30 70
BA2 NC/A14
87 88
VDD2 VDD3
70 30 15
70 30 15
MEM_A_A<12>
MEM_A_A<9>
89
91
93
A12
A9
A11
A7
90
92
94
MEM_A_A<11>
MEM_A_A<7>
15 30 70
15 30 70
DDR2 Bypass Caps
70 30 15 MEM_A_A<8> A8 A6 MEM_A_A<6> 15 30 70 (For return current)
95 VDD4 VDD5
96
97 98 29 28 8 =PP1V8_S3_MEM
70 30 15 MEM_A_A<5> A5 A4 MEM_A_A<4> 15 30 70
70 30 15 MEM_A_A<3> 99 100 MEM_A_A<2> 15 30 70

A3 A2
70 30 15 MEM_A_A<1> 101 102 MEM_A_A<0> 15 30 70
A1 A0
103 104
1 C3121
VDD6 VDD7 4.7uF
MEM_A_A<10> 105 106 MEM_A_BA<1> 20%
70 30 15 A10/AP BA1 15 30 70 6.3V
107 108 2 CERM
70 30 15 MEM_A_BA<0> BA0 RAS* MEM_A_RAS_L 15 30 70 603
70 30 15 MEM_A_WE_L 109 110 MEM_A_CS_L<0> 15 30 70
WE* S0*
111 VDD8 VDD9
112
MEM_A_CAS_L 113 114 MEM_A_ODT<0>
70 30 15 CAS* ODT0 15 30 70
70 30 15 MEM_A_CS_L<1> 115 116 MEM_A_A<13> 15 30 70

NC/S1* NC/A13
117 118
1 C3110 1 C3111 1 C3112 1 C3113
VDD10 VDD11 0.1UF 0.1UF 0.1UF 0.1UF
70 30 15 MEM_A_ODT<1> 119 120 NC 20% 20% 20% 20%
NC/ODT1 NC3
121 122 2 10V
CERM
10V
2 CERM 2 10V
CERM
10V
2 CERM
VSS31 VSS32 402 402 402 402
MEM_A_DQ<36> 123 124 MEM_A_DQ<32>
70 15 DQ32 DQ36 15 70
70 15 MEM_A_DQ<37> 125 126 MEM_A_DQ<33> 15 70

DQ33 DQ37
B 70 15 MEM_A_DQS_N<4>
127
129
VSS33
DQS4*
VSS34
DM4
128
130 MEM_A_DM<4> 15 70
1 C3114 1 C3115 1 C3116 1 C3117
B
70 15 MEM_A_DQS_P<4> 131
DQS4 VSS35
132 0.1UF 0.1UF 2.2UF 2.2UF
20% 20% 20% 20%
133 134 MEM_A_DQ<34> 15 70 2 10V 10V
2 CERM
6.3V
2 CERM 2 6.3V
VSS36 DQ38 CERM CERM
MEM_A_DQ<39> 135 136 MEM_A_DQ<35> 402 402 402-LF 402-LF
70 15 DQ34 DQ39 15 70
MEM_A_DQ<38> 137 138

70 15 DQ35 VSS37
139 140 MEM_A_DQ<44>
VSS38 DQ44 15 70
70 15 MEM_A_DQ<40> 141 142 MEM_A_DQ<45> 15 70

DQ40 DQ45 1 C3118 1 C3119 1 C3120
MEM_A_DQ<41> 143 144
70 15 DQ41 VSS39 2.2UF 2.2UF 2.2UF
145 146 MEM_A_DQS_N<5> 15 70
20% 20% 20%
VSS40 DQS5* 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM
MEM_A_DM<5> 147 148 MEM_A_DQS_P<5>
70 15 DM5 DQS5 15 70 402-LF 402-LF 402-LF
149 150
VSS41 VSS42
70 15 MEM_A_DQ<47> 151 152 MEM_A_DQ<43> 15 70
DQ42 DQ46
MEM_A_DQ<42> 153 154 MEM_A_DQ<46>
70 15
155
DQ43 DQ47
156
15 70
The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,
VSS43 VSS44
70 15 MEM_A_DQ<56> 157
DQ48 DQ52
158 MEM_A_DQ<61> 15 70
when they get cheaper.
70 15 MEM_A_DQ<60> 159 160 MEM_A_DQ<57> 15 70
DQ49 DQ53
161 162
VSS45 VSS46
NC 163 164 MEM_A_CLK_P<1>
NC_TEST CK1 15 70
165 166 MEM_A_CLK_N<1>
VSS47 CK1* 15 70
70 15 MEM_A_DQS_N<7> 167 168

DQS6* VSS48
70 15 MEM_A_DQS_P<7> 169
171
DQS6 DM6
170
172
MEM_A_DM<7> 15 70
DDR2-800
VSS49 VSS50
70 15 MEM_A_DQ<59> 173
DQ50 DQ54
174 MEM_A_DQ<58> 15 70 R3140
10K
MEM_A_DQ<63> 175 176 MEM_A_DQ<62> 1 2
70 15 DQ51 DQ55 15 70 28 MEM_A_SA0
177 178
VSS51 VSS52 5%
A 70 15 MEM_A_DQ<48>
MEM_A_DQ<53>
179
181
DQ56 DQ60
180
182
MEM_A_DQ<52>
MEM_A_DQ<49>
15 70
1/16W
MF-LF
402 SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 A
70 15 DQ57 DQ61 15 70 PAGE TITLE
183
VSS53 VSS54
184 R3141
10K DDR2 SO-DIMM Connector A
70 15 MEM_A_DM<6> 185 186 MEM_A_DQS_N<6> 15 70 MEM_A_SA1 1 2
DM7 DQS7* 28
187 188 DRAWING NUMBER SIZE
VSS55 DQS7 MEM_A_DQS_P<6> 15 70 5%
MEM_A_DQ<50> 189 190 1/16W
MF-LF Apple Inc. 051-8089 D
70 15 DQ58 VSS56
191 192 402 REVISION
MEM_A_DQ<55> DQ59 DQ62 MEM_A_DQ<51>
29 8 =PPSPD_S0_MEM 70 15
193 194 MEM_A_DQ<54>
15 70
15 70
R
A.0.0
VSS57 DQ63
NOTICE OF PROPRIETARY PROPERTY:
1 C3130 1 C3131 44 =I2C_SODIMMA_SDA 195
SDA VSS58
196 BRANCH
2.2UF
20%
0.1UF
20% 44 =I2C_SODIMMA_SCL 197
SCL SA0
198 MEM_A_SA0 28
4V 10V 199 200 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
2 X5R 2 CERM VDDSPD SA1 MEM_A_SA1
402 402
28
31 OF 109
202=GND_CHASSIS_DIPDIMM_LEFT SHEET
516-0135 ADDR=0xA0(WR)/0xA1(RD)
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
29 28 8 =PP1V8_S3_MEM DIP DIMM CONN 201 =GND_CHASSIS_DIPDIMM_RIGHT 9 =PP1V8_S3_MEM 8 28 29
MEM_VREF_B 1 2
VREF
CRITICAL VSS0
27
3 4 MEM_B_DQ<0> 15 70
VSS1 DQ4
1 C3200 1 C3201 70 15 MEM_B_DQ<5> 5
DQ0
J3200 DQ5
6 MEM_B_DQ<4> 15 70
2.2UF
20%
0.1UF
20% 70 15 MEM_B_DQ<1> 7
DQ1
F-RT-TH4
VSS2
8
DDR2-SODIMM-STD
2 4V
X5R 2 10V
CERM
9
VSS4 DM0
10 MEM_B_DM<0> 15 70
402 402 MEM_B_DQS_N<0> 11 12
70 15 DQS0* VSS5
70 15 MEM_B_DQS_P<0> 13 14 MEM_B_DQ<3> 15 70
DQS0 DQ6
15 16 MEM_B_DQ<2> 15 70
VSS6 DQ7
MEM_B_DQ<6> 17 18
70 15 DQ2 VSS7
MEM_B_DQ<7> 19 20 MEM_B_DQ<8>
70 15 DQ3 DQ12 15 70
D 70 15 MEM_B_DQ<12>
21
23
VSS8
DQ8
DQ13
VSS9
22
24
MEM_B_DQ<13> 15 70
D
MEM_B_DQ<14> 25 26 MEM_B_DM<1>
70 15 DQ9 DM1 15 70
27 VSS10
28
VSS11
70 15 MEM_B_DQS_N<1> 29 30 MEM_B_CLK_P<0> 15 70
DQS1* CK0
70 15 MEM_B_DQS_P<1> 31 32 MEM_B_CLK_N<0> 15 70
DQS1 CK0*
33 34
VSS12 VSS13
MEM_B_DQ<11> 35 36 MEM_B_DQ<10>
70 15 DQ10 DQ14 15 70
MEM_B_DQ<9> 37 38 MEM_B_DQ<15>
70 15 DQ11 DQ15 15 70
39 40
VSS14 VSS15
KEY
41 42
VSS16 VSS17
70 15 MEM_B_DQ<22> 43 44 MEM_B_DQ<21> 15 70
DQ16 DQ20
70 15 MEM_B_DQ<19> 45 46 MEM_B_DQ<17> 15 70
DQ17 DQ21
47 48
VSS18 VSS19
MEM_B_DQS_N<2> 49 50 MEM_EVENT_L
70 15 DQS2* NC0 21 28 41
70 15 MEM_B_DQS_P<2> 51 52 MEM_B_DM<2> 15 70
DQS2 DM2
53 54
VSS21 VSS22
70 15
70 15
MEM_B_DQ<18>
MEM_B_DQ<23>
55
57
59
DQ18
DQ19
DQ22
DQ23
56
58
60
MEM_B_DQ<16>
MEM_B_DQ<20>
15 70
15 70
Page Notes
VSS23 VSS24 Power aliases required by this page:
70 15 MEM_B_DQ<24> 61 62 MEM_B_DQ<30> 15 70 - =PP1V8_S3_MEM
DQ24 DQ28
MEM_B_DQ<28> 63 64 MEM_B_DQ<26> - =PPSPD_S0_MEM (2.5V - 3.3V)
70 15 DQ25 DQ29 15 70
65 66
VSS25 VSS26
MEM_B_DM<3> 67 68 MEM_B_DQS_N<3> Signal aliases required by this page:
70 15 DM3 DQS3* 15 70
69 70 MEM_B_DQS_P<3> - =I2C_MEM_SCL
NC NC1 DQS3 15 70
71 72 - =I2C_MEM_SDA
VSS27 VSS28
MEM_B_DQ<29> 73 74 MEM_B_DQ<27>
C 70 15
70 15 MEM_B_DQ<25> 75
DQ26
DQ27
DQ30
DQ31
76 MEM_B_DQ<31>
15 70
15 70
(NONE) C
77 78
VSS29 VSS30
MEM_B_CKE<0> 79 80 MEM_B_CKE<1> NOTE: This page does not supply VREF.
70 30 15 CKE0 NC/CKE1 15 30 70
81 82 The reference voltage must be provided
VDD0 VDD1
83 84 NC MEM_B_A<15> by another page.
NC NC2 NC/A15 9
70 30 15 MEM_B_BA<2> 85 86 NC MEM_B_A<14> 15 30 70
BA2 NC/A14
87 88
70 30 15
70 30 15
MEM_B_A<12>
MEM_B_A<9>
89
91
VDD2
A12
A9
VDD3
A11
A7
90
92
MEM_B_A<11>
MEM_B_A<7>
15 30 70
15 30 70
DDR2 Bypass Caps
70 30 15 MEM_B_A<8> 93 94 MEM_B_A<6> 15 30 70
(For return current)
A8 A6
95 96 29 28 8 =PP1V8_S3_MEM
VDD4 VDD5
70 30 15 MEM_B_A<5> 97 98 MEM_B_A<4> 15 30 70
A5 A4
70 30 15 MEM_B_A<3> 99 A3 A2
100 MEM_B_A<2> 15 30 70
70 30 15 MEM_B_A<1> 101 102 MEM_B_A<0> 15 30 70

1 C3221
A1 A0
103
VDD6 VDD7
104 4.7uF
20%
70 30 15 MEM_B_A<10> 105 106 MEM_B_BA<1> 15 30 70
6.3V
2 CERM
A10/AP BA1
MEM_B_BA<0> 107 108 MEM_B_RAS_L 603
70 30 15 BA0 RAS* 15 30 70
70 30 15 MEM_B_WE_L 109 WE* S0*

110 MEM_B_CS_L<0> 15 30 70
111 112
VDD8 VDD9
70 30 15 MEM_B_CAS_L 113 CAS* ODT0
114 MEM_B_ODT<0> 15 30 70
70 30 15 MEM_B_CS_L<1> 115 NC/S1* NC/A13

116 MEM_B_A<13> 15 30 70
1 C3210 1 C3211 1 C3212 1 C3213
117 VDD10 VDD11
118 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20%
70 30 15 MEM_B_ODT<1> 119
NC/ODT1 NC3
120 NC 2 10V
CERM
10V
2 CERM 2 10V
CERM
10V
2 CERM
121 122 402 402 402 402
VSS31 VSS32
MEM_B_DQ<39> 123 124 MEM_B_DQ<35>
70 15 DQ32 DQ36 15 70
MEM_B_DQ<34> 125 126 MEM_B_DQ<36>
70 15 DQ33 DQ37 15 70
B 127
129
VSS33 VSS34
128
130
B
70 15 MEM_B_DQS_N<4> DQS4* DM4 MEM_B_DM<4> 15 70
1 C3214 1 C3215 1 C3216 1 C3217
70 15 MEM_B_DQS_P<4> 131 DQS4 VSS35
132 0.1UF 0.1UF 2.2UF 2.2UF
20% 20% 20% 20%
133 VSS36 DQ38
134 MEM_B_DQ<33> 15 70 2 10V
CERM
10V
2 CERM 6.3V
2 CERM 2 6.3V
CERM
MEM_B_DQ<37> 135 136 MEM_B_DQ<38> 402 402 402-LF 402-LF
70 15 DQ34 DQ39 15 70
70 15 MEM_B_DQ<32> 137 138

DQ35 VSS37
139 140 MEM_B_DQ<40> 15 70
VSS38 DQ44
MEM_B_DQ<45> 141 142 MEM_B_DQ<41>
70 15
MEM_B_DQ<44> 143
DQ40 DQ45
144
15 70 1 C3218 1 C3219 1 C3220
70 15 DQ41 VSS39 2.2UF 2.2UF 2.2UF
145 146 MEM_B_DQS_N<5> 20% 20% 20%
VSS40 DQS5* 15 70 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM
70 15 MEM_B_DM<5> 147 148 MEM_B_DQS_P<5> 15 70 402-LF 402-LF 402-LF
DM5 DQS5
149 150
VSS41 VSS42
MEM_B_DQ<42> 151 152 MEM_B_DQ<46>
70 15 DQ42 DQ46 15 70
70 15 MEM_B_DQ<43> 153 154 MEM_B_DQ<47> 15 70

DQ43 DQ47
155 156 The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,
VSS43 VSS44
70 15 MEM_B_DQ<49> 157 DQ48 DQ52
158 MEM_B_DQ<52> 15 70 when they get cheaper.
70 15 MEM_B_DQ<53> 159 DQ49 DQ53
160 MEM_B_DQ<48> 15 70
161 162
VSS45 VSS46
NC 163 164 MEM_B_CLK_P<1> 15 70
NC_TEST CK1
165 166 MEM_B_CLK_N<1> 15 70
VSS47 CK1*
MEM_B_DQS_N<6> 167 168 =PPSPD_S0_MEM
70 15 DQS6* VSS48 29 28 8
MEM_B_DQS_P<6> 169 170 MEM_B_DM<6> 1 DDR2-800
70 15
171
DQS6 DM6
172
15 70
R3241
VSS49 VSS50 10K
70 15 MEM_B_DQ<55> 173 174 MEM_B_DQ<54> 15 70 5%
DQ50 DQ54 1/16W
MEM_B_DQ<50> 175 176 MEM_B_DQ<51> MF-LF
70 15 DQ51 DQ55 15 70
177 178 2 402
MEM_B_SA0
A 70 15 MEM_B_DQ<60> 179
VSS51
DQ56
VSS52
DQ60
180 MEM_B_DQ<63> 15 70
29
29
J3201_SA1 SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 A
70 15 MEM_B_DQ<61> 181 182 MEM_B_DQ<59> 15 70
PAGE TITLE
DQ57 DQ61
183
185
VSS53 VSS54
184
186
1
R3240
10K
DDR2 SO-DIMM Connector B
70 15 MEM_B_DM<7> DM7 DQS7* MEM_B_DQS_N<7> 15 70 5% DRAWING NUMBER SIZE
1/16W
=PPSPD_S0_MEM
187
VSS55 DQS7
188 MEM_B_DQS_P<7> 15 70 MF-LF
2 402
29 28 8
70 15 MEM_B_DQ<57> 189 190 REVISION
DQ58 VSS56
70 15 MEM_B_DQ<56> 191
DQ59 DQ62
192 MEM_B_DQ<58> 15 70
R
A.0.0
1 C3230
2.2UF
1 C3231
0.1UF
193
195
VSS57 DQ63
194
196
MEM_B_DQ<62> 15 70 NOTICE OF PROPRIETARY PROPERTY: BRANCH
20% 20% 44 =I2C_SODIMMB_SDA SDA VSS58 THE INFORMATION CONTAINED HEREIN IS THE
4V 10V 197 198 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
2 X5R 2 CERM 44 =I2C_SODIMMB_SCL SCL SA0 MEM_B_SA0 29 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
Resistor prevents pwr-gnd short
402 402 199
VDDSPD SA1
200 J3201_SA1 29 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
32 OF 109
SHEET
516-0135 202=GND_CHASSIS_DIPDIMM_CENTER 9
28
ADDR=0XA2(WR)/0XA3(RD) III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
One cap for each side of every RPAK, one cap for every two discrete resistors
BOMOPTION shown at the top of each group applies to every part below it
8 =PP0V9_S3M_MEM_TERM
MEM_A_CS_L<0> RP3300 47 2 7
70 28 15 IN
5% 1/16W SM-LF
D 70 28 15
70 29 15
IN
IN
MEM_A_CS_L<1>
MEM_B_CS_L<0>
R3301
RP3301
47
47
1
2
2
7 5% 1/16WMF-LF402
1 C3300
0.1UF
20%
1 C3301
0.1UF
20%
D
RP3302 47 4 5 5% 1/16W SM-LF 10V 10V
70 29 15 IN MEM_B_CS_L<1> 2 CERM 2 CERM
5% 1/16W SM-LF 402 402
MEM_A_CKE<0> RP3303 47 1 8
70 28 15 IN
RP3304 47 4 5 5% 1/16W SM-LF
70 28 15 IN MEM_A_CKE<1>
5% 1/16W SM-LF
1 C3302 1 C3303
MEM_B_CKE<0> RP3305 47 1 8 0.1UF 0.1UF
70 29 15 IN
5% 1/16WSM-LF 20% 20%
70 29 15 IN
MEM_B_CKE<1> R3327 47 1 2 10V
2 CERM 2
10V
CERM
5% 1/16WMF-LF402 402 402
70 28 15 MEM_A_ODT<0> RP3300 47 1 8
IN
MEM_A_ODT<1> R3309 47 1 2 5% 1/16W SM-LF 1 C3304 1 C3305
70 28 15 IN
RP3301 5% 1/16WMF-LF402 0.1UF 0.1UF
70 29 15 IN MEM_B_ODT<0> 47 3 6 20%
10V
20%
10V
R3311 5% 1/16WSM-LF 2 CERM 2 CERM
70 29 15 IN MEM_B_ODT<1> 47 1 2
5% 1/16WMF-LF402 402 402
70 28 15 IN MEM_A_A<14..0> RP3307 47 2 7
0
5% 1/16W SM-LF
1 C3306 1 C3307
1
RP3308 47 4 5 0.1UF 0.1UF
5% 1/16W SM-LF 20% 20%
2
RP3307 47 1 8 10V 10V
2 CERM 2 CERM
RP3308 47 3 6 5% 1/16WSM-LF 402 402
3
RP3307 47 3 6 5% 1/16W SM-LF
4
RP3308 47 2 7 5% 1/16W SM-LF
5
RP3304 47 1 8 5% 1/16W SM-LF
6
RP3307 47 4 5 5% 1/16W SM-LF 1 C3308 1 C3309
C 7
8
RP3308 47 1 8 5% 1/16W SM-LF 0.1UF
20%
10V
0.1UF
20%
10V
C
RP3303 47 4 5 5% 1/16W SM-LF 2 CERM 2 CERM
9
402 402
RP3309 47 5% 1/16W SM-LF
10 1 8
5% 1/16W SM-LF
LAYOUT NOTE:PLACE ONE CAP CLOSE TO EVERY TWO PULLUP RESISTORS TERMINATED
RP3304 47
11 2 7
5% 1/16W SM-LF
TO PP0V9_S0_MEM_TERM
12
RP3303 47 3 6
R3325 5% 1/16W SM-LF
13 47 1 2
5% 1/16WMF-LF402
1 C3310 1 C3311
14
RP3304 47 3 6 0.1UF 0.1UF
5% 1/16W SM-LF 20% 20%
10V 10V
2 CERM 2 CERM
402 402
70 28 15 IN MEM_A_BA<2..0> RP3309 47 2 7
0
RP3300 47 4 5 5% 1/16W SM-LF
1
RP3303 47 5% 1/16W SM-LF
2 2 7
5% 1/16W SM-LF
1 C3312 1 C3313
0.1UF 0.1UF
20% 20%
10V 10V
2 CERM 2 CERM
402 402
MEM_A_RAS_L RP3300 47 3 6
70 28 15 IN
MEM_A_CAS_L RP3309 47 4 5 5% 1/16W SM-LF
70 28 15 IN
RP3309 47 3 6 5% 1/16W SM-LF
70 28 15 IN MEM_A_WE_L
5% 1/16W SM-LF 1 C3314 1 C3315
0.1UF 0.1UF
20% 20%
10V 10V
2 CERM 2 CERM
402 402
B 1 C3316 1 C3317
B
RP3311 0.1UF 0.1UF
70 29 15 IN MEM_B_A<0> 47 3 6 20%
10V
20%
10V
RP3310 47 3 6 5% 1/16W SM-LF 2 CERM 2
70 29 15 IN MEM_B_A<3> 402
CERM
402
RP3311 47 2 7 5% 1/16W SM-LF
70 29 15 IN MEM_B_A<2>
MEM_B_A<10> R3335 5% 1/16W SM-LF
70 29 15 IN 47 1 2
5% 1/16WMF-LF402
MEM_B_A<4> RP3311 47 1 8
70 29 15 IN
RP3310 47 2 7 5% 1/16W SM-LF
70 29 15 IN MEM_B_A<5>
70 29 15 MEM_B_A<6> RP3306 47 4 5 5% 1/16W SM-LF 1 C3318 1 C3319
IN
RP3306 5% 1/16W SM-LF 0.1UF 0.1UF
70 29 15 IN MEM_B_A<7> 47 3 6 20%
10V
20%
10V
RP3310 47 1 8 5% 1/16W SM-LF 2 CERM 2 CERM
70 29 15 IN MEM_B_A<8> 402 402
RP3305 47 4 5 5% 1/16W SM-LF
70 29 15 IN MEM_B_A<9>
RP3310 47 4 5 5% 1/16W SM-LF
70 29 15 IN MEM_B_A<1>
RP3306 47 2 7 5% 1/16W SM-LF
70 29 15 IN MEM_B_A<11>
RP3305 47 3 6 5% 1/16W SM-LF
70 29 15 IN MEM_B_A<12>
70 29 15 MEM_B_A<13> RP3301 47 4 5 5% 1/16W SM-LF 1 C3320 1 C3321
IN
RP3306 5% 1/16W SM-LF 0.1UF 0.1UF
70 29 15 IN MEM_B_A<14> 47 1 8 20%
10V
20%
10V
5% 1/16W SM-LF 2 CERM 2 CERM
402 402
70 29 15 IN MEM_B_BA<2..0> RP3302 47 1 8
0
1
RP3311 47 4 5 5% 1/16WSM-LF 1 C3322 1 C3323
RP3305 5% 1/16W SM-LF 0.1UF 0.1UF
2 47 2 7 20%
10V
20%
10V
5% 1/16W SM-LF 2 CERM 2 CERM
402 402
A RP3301
70 29 15 IN MEM_B_RAS_L 47 1 8 PAGE TITLE
70 29 15 IN MEM_B_CAS_L RP3302
RP3302
47
47
2
3
7
6
5% 1/16WSM-LF
5% 1/16WSM-LF
1 C3324
0.1UF
1 C3325
0.1UF
Memory Active Termination
70 29 15 IN MEM_B_WE_L 20% 20% DRAWING NUMBER SIZE
5% 1/16W SM-LF 10V
2 CERM 2
10V
CERM
402 402
REVISION
R
A.0.0
33 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AIRPORT
D D
750 mA nominal max

1000 mA peak Q3450
L3404 FDC606P_G
FERR-120-OHM-1.5A SOT-6
6
0402-LF VOLTAGE=3.3 V
5
MIN_LINK_WIDTH=1 MM
S
2 1
4
31 PP3V3_WLAN_F =PP3V3_S3_AIRPORT_AUX 8 31
1
1
R3451
G
C3422 1 C3421 1 1 C3420 C3451 1
0.1uF 0.1uF 10uF 0.033UF 10K
5%
3
20% 20% 20% 10% 1/16W
10V 10V 6.3V 16V
CERM 2 CERM 2 2 X5R C3450 X5R 2 MF-LF
402 402 603
0.1UF 402 R3450 2 402
1 2
100K
P3V3WLAN_S5 1 2 PM_WLAN_EN_L IN 33
PLACE C3422 NEAR J3400 PLACE C3420 AND C3421 NEAR Q3450 10%
5%
1/16W
16V MF-LF
X5R 402
402
=PP1V5_S0_AIRPORT 8
1 C3404 1 C3405 1 C3406

7 PP3V3_WLAN 0.1UF 0.1UF 0.1UF
MIN_NECK_WIDTH=0.5 MM 20% 20% 20%
MIN_LINE_WIDTH=1 MM 2 10V
CERM
10V
2 CERM 2 10V
CERM
C VOLTAGE=3.3 V 402 402 402
C
PP3V3_WLAN_F 31
CRITICAL
=PP3V3_S3_WLAN 8
17 7 OUT PCIE_WAKE_L
J3400
ASOB226-S45B-7F
1
R3453
F-ST-SM 33K
31 OUT MINI_CLKREQ_CONN_L 5%
54 1/16W
IT IS CO-LAY FUNCTION U3402 5 MF-LF
402
2
74LVC1G17DRL
1 2 TC7SZ08AFEAPE 5 SOT-553
3 4
SOT665
A
2 PP3V3_WLAN_BUF 4 2
5 6
7 MINI_RESET 4
U3401
Y NC PP3V3_WLAN_RC
1
7 8 B
3 1
71 17 7 PCIE_CLK100M_MINI_N
IN 9 10 3 NC 1
C3453 1 R3454
11 12 62K
MINI_RESET_L 26
1UF 5%
PCIE_CLK100M_MINI_P 13 14 IN 10%
71 17 7 IN 6.3V 1/16W
CERM 2 MF-LF
15 16 402
402 2
17 KEY 18
19 20
21 22 275 mA peak
L3405
23 24 206 mA nominal max 2 1
71 17 7 OUT PCIE_MINI_D2R_N 7 PP3V3_S3_AIRPORT_CONN =PP3V3_S3_AIRPORT_AUX 8 31
71 17 7 PCIE_MINI_D2R_P 25 26 FERR-120-OHM-1.5A
OUT 0402-LF
27 28
PLACEMENT_NOTE=PLACE CLOSE TO J3400. 29 30 I2C_MINI_PCIE_SCL
C3452 1
C3431 IN 7 44
0.1uF
71 17 PCIE_MINI_R2D_C_N 1 2 0.1uF 71 7 PCIE_MINI_R2D_N 31 32 I2C_MINI_PCIE_SDA 7 44
20%
IN BI 10V
PCIE_MINI_R2D_C_P 1 2
10% 16V X5R 402 PCIE_MINI_R2D_P 33 34 CERM 2
71 17 IN 0.1uF 71 7
402
10% 16V X5R 402 35 36 USB2_AIRPORT_N
B C3430 37
39
38
40
72 7 USB2_AIRPORT_P B
PLACEMENT_NOTE=PLACE CLOSE TO J3400.
17 PCIE_MINI_PRSNT_L 7 MINI_CLKREQ_L
41 42 17
43 44
45 46
47 48
CRITICAL Q3401 D 6
Q3401 D 3
49 50 SSM6N15FEAPE SSM6N15FEAPE
51 52
L3402
90-OHM
SOT563 SOT563
DLP0NS
SYM_VER-1
4 3 =USB_MINI_N
53 BI 9 2 G S 1
5 G S 4
1 2 =USB_MINI_P 9 33 21 AP_PWR_EN
BI
31 MINI_CLKREQ_CONN_L
CONNECT TO M35 MODULE
OLD:516S0406 (FOXCONN ONLY)

NEW:516S0635 (FOXCONN & ACON)
PAGE TITLE
Right Clutch Connector

DRAWING NUMBER SIZE

REVISION
R
A.0.0
34 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP1V05_ENET_PHY 8
(221mA typ - 1000base-T)

D 1 1
( 7mA typ - Energy Detect) D
C3710 C3711 1
WF: Marvell numbers, update for Realtek
0.1UF 0.1UF CRITICAL
10% 10%
16V 16V
X5R 2 X5R 2 L3715
402 402 FERR-120-OHM-1.5A
8 =PP3V3_ENET_PHY 0402-LF
(43mA typ - 1000base-T)

(19mA typ - Energy Detect) 1 1 C3700 1 C3701 1
C3702 2
WF: Marvell numbers, update for Realtek 0.1UF 0.1UF 0.1UF
CRITICAL 10% 10% 10%
16V 16V 16V
PP1V05_ENET_PHYAVDD
L3705 2 X5R 2 X5R 2
X5R MIN_LINE_WIDTH=0.6 MM
FERR-120-OHM-1.5A 402 402 402 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
1 1 1
0402-LF C3714 C3715 C3716
0.1UF 0.1UF 0.1UF
10% 10% 10%
16V 16V 16V
2
X5R 2 X5R 2 X5R 2
402 402 402
PP3V3_ENET_PHYAVDD
VOLTAGE=3.3V
1 1
C3705 C3706
0.1UF 0.1UF
10% 10% =PP3V3_ENET_PHY_VDDREG
16V 16V 9
2 X5R 2 X5R
402 402
If internal switcher is used, must place 1x 22uF &
1x 0.1uF caps within 5mm of U3700 pins 44 & 45.
NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

R3750 1 1
R3751 R3752 1
4.7K 4.7K 4.7K =RTL8211_REGOUT
41
15
21
37
44
45
28
36
10
40
9
3
NO STUFF 5% 5% 5%
1/16W 1/16W 1/16W If internal switcher is used, must place inductor within 5mm
R3720 1 1
AVDD33
DVDD33
VDDREG
FB12
DVDD12
AVDD12
R3799 MF-LF
402 2
MF-LF
402
MF-LF
402 2 of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.
10K 4.7K 2
C Alias to =PP3V3_ENET_PHY for internal switcher.

5%
1/16W
MF-LF
5%
1/16W
MF-LF
OMIT
CRITICAL
If internal switcher is not used, VDDREG and REGOUT can float. C
Alias to GND for external 1.05V supply. 402 2 2 402
39
U3700 48
9 IN =RTL8211_ENSWREG ENSWREG RTL8211CLGR REGOUT
TQFP
R3796
73 18 IN ENET_CLK125M_TXCLK 1 0 2 73 ENET_CLK125M_TXCLK_R 22
TXC RXC 19 73 ENET_CLK125M_RXCLK_R R3790 22 1 2 ENET_CLK125M_RXCLK OUT 18 73
5% 1/16W MF-LF 402
5%
1/16W
402
MF-LF 73 18 IN ENET_TXD<0> 23
TXD[0] RXD[0] 14 ENET_RXD_R<0> R3791 22 1 2 ENET_RXD<0> OUT 18
5% 1/16W MF-LF 402
PLACE R3796 CLOSE TO U1400, PIN D24 73 18 IN ENET_TXD<1> 24
TXD[1] RXD[1]/TXDLY 16 ENET_RXD_R<1> R3792 22 1 2 ENET_RXD<1> OUT 18 73
RGMII/MII 5% 1/16W MF-LF 402
73 18 IN ENET_TXD<2> 25
TXD[2] RXD[2]/AN0 17 ENET_RXD_R<2> R3793 22 1 2 ENET_RXD<2> OUT 18 73
5% 1/16W MF-LF 402
73 18 IN ENET_TXD<3> 26
TXD[3] RXD[3]/AN1 18 ENET_RXD_R<3> R3794 22 1 2 ENET_RXD<3> OUT 18 73
5% 1/16W MF-LF 402
73 18 IN ENET_TX_CTRL 27
TXCTL RXCTL 13 ENET_RXCTL_R R3795 22 1 2 ENET_RX_CTRL OUT 18 73
5% 1/16W MF-LF 402
ENET_MDC 30 1 ENET_MDI_P<0>
73 18 IN MDC MDI+[0] BI 34 73
WF: Verify that ENET_RESET_L does not assert when WOL is active. 31 MANAGEMENT 2
73 18 BI ENET_MDIO MDIO MDI-[0] ENET_MDI_N<0> BI 34 73
If true, RC and 0-ohm resistor should be removed.
4 ENET_MDI_P<1>
If false, ENET_RESET_L should be removed. R3700 MDI+[1] BI 34 73
5 ENET_MDI_N<1>
0 29 MDI-[1] BI 34 73
73 18 IN ENET_RESET_L 1 2 RTL8211_PHYRST_L PHYRSTB* RESET MEDIA DEPENDENT
5%
NO STUFF MDI+[2] 8 ENET_MDI_P<2> 34 73
BI
1/16W 9
402
1
C3727 MDI-[2] ENET_MDI_N<2> BI 34 73
MF-LF 0.1UF 46
20%
RTL8211_RSET RSET REFERENCE 11
10V MDI+[3] ENET_MDI_P<3> BI 34 73
2 CERM 12
402 MDI-[3] ENET_MDI_N<3> BI 34 73
B 1
RTL8211_CLK125 32
CLK125
PHY_AD0/LED0
B
R3730
1
R3731 CLOCK LED0/PHYAD0 34 RTL8211_PHYAD0
2.49K 22 RTL8211_CLK25M_CKXTAL1 42 35 RTL8211_PHYAD1
1% 5% 33 IN CKXTAL1 LED LED1/PHYAD1
1/16W 1/16W 43 38
MF-LF MF-LF TP_RTL8211_CKXTAL2 CKXTAL2 LED2/RXDLY RTL8211_RXDLY
402
2 2 402 RXDLY/LED2
GND NO STUFF
C3790 1 R3755 1 R3756 1 1
R3757
20
33
47
10PF 4.7K 4.7K 4.7K
5%
5% 5% 5%
50V 1/16W 1/16W 1/16W
CERM 2 MF-LF MF-LF MF-LF
402 402 2 402 2 2
402
Reserved for EMI

per RealTek request.
A SYNC_MASTER=SUMA SYNC_DATE=03/20/2008 A
PAGE TITLE
Ethernet PHY (RTL8211CL)

DRAWING NUMBER SIZE

REVISION
R
A.0.0
Configuration Settings: NOTICE OF PROPRIETARY PROPERTY: BRANCH
PHYAD = 01 (PHY Address 00001) PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
AN[1:0] = 11 (Full auto-negotiation)
RXDLY = 0 (RXCLK transitions with data)
37 OF 109
TXDLY = 0 (No TXCLK Delay)
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V ENET FET CRITICAL

@ 2.5V Vgs: Q3810
Rds(on) = 90mOhm max NTR4101P
SOT-23-HF
I(max) = 1.7A (85C)
8 =PP3V3_S5_P3V3ENETFET 2 S D 3 =PP3V3_ENET_FET 8
D 1
G D
R3800 1 C3811
1
10K 0.033UF
10%
5% 16V
1/16W 2 X5R
MF-LF 402 C3810
402
2 R3810 0.01UF
100K
P3V3ENET_EN_L 1 2 P3V3ENET_SS 2 1
5%
1/16W 10%
MF-LF 16V
Q3801 D 3
402 CERM
402
SSM6N15FEAPE
SOT563
5 G S 4
9 IN =P3V3ENET_EN
MOBILE:
Recommend aliasing PM_SLP_RMGT_L and

=P3V3ENET_EN. Nets separated on
ARB for alternate power options.
WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))
NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
PM_WLAN_EN_L OUT 31
C Pull-up is with power FET.

1.05V ENET FET C
Q3805 D 6
SSM6N15FEAPE
SOT563 8 =PP1V05_ENET_P1V05ENETFET
1.8V Vgs
2 G S 1 C3840 1
3
31 21 AP_PWR_EN AC_OR_S0_L 0.1UF CRITICAL
IN 20%
10V
2
D
CERM
D 3 6 D
R3840 402 Q3840
Q3805 Q3801 =PP3V3_S5_P1V05ENETFET 1
20.0K
2 P1V05ENET_SS 1 G SI2312BDS
8
SSM6N15FEAPE SSM6N15FEAPE SOT23
SOT563 SOT563 1% S
1/16W
MF-LF
Q3841 D 6
R3842 1 402 2
5 G S S G 2 69.8K SSM6N15FEAPE
4 1
1% SOT563 =PP1V05_ENET_FET 8
1/16W
42 41 36 21 IN SMC_ADAPTER_EN MF-LF
402
2
R3841 2 G S 1
1
C3841
10K 0.01UF
P1V05ENET_EN_L 1 2 10%
16V
64 41 36 21 IN PM_SLP_S3_L 2 CERM
1%
1/16W 402
MF-LF
Q3841 D 3
402 P1V05ENET_EN_L_RC
SSM6N15FEAPE
SOT563
5 G S 4
B 9 IN =P1V05ENET_EN
B
Non-ARB:
Recommend aliasing PM_SLP_RMGT_L and

=P1V05ENET_EN. Nets separated on
ARB for alternate power options.
RTL8211 25MHz Clock

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.
A Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
SYNC_MASTER=SUMA SYNC_DATE=04/04/2008 A
PAGE TITLE
R3895
22
Ethernet & AirPort Support
73 18 IN MCP_CLK25M_BUF0_R 1 2 RTL8211_CLK25M_CKXTAL1 OUT 32 DRAWING NUMBER SIZE
5%
1/16W Apple Inc. 051-8089 D
MF-LF REVISION
402
PLACEMENT_NOTE=Place close to U1400
R
A.0.0
38 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
- COPY THIS PAGE FROM K36 CSA.39
D D
PLACE ONE CAP EACH NEAR PINS 3 AND 4 OF T3901 AND T3902
ENET_CONN_CTAP
1 C3900 1 C3901 1 C3902 1 C3903

0.1UF
10%
0.1UF
10%
0.1UF
10% 10%
0.1UF ETHERNET CONNECTOR
16V 16V 16V 16V
2 X5R 2 X5R 2 X5R 2 X5R
402 402 402 402
OMIT
CRITICAL CRITICAL
T3901 J3900
ENET_MDI_P<1> 1 SM 12 ENET_MDI_TRAN_P<1> RJ45-MG3-K36
73 32 BI F-RT-TH
9
73 32 ENET_MDI_N<1> 2 11 ENET_MDI_TRAN_N<1> SYM_VER-1

BI
3 10
R3903
ENET_CENTER_TAP<1> 1 2 75
1
2
ENET_MDI_TRAN_P_0
ENET_MDI_TRAN_N_0
TX 1% 1/16W MF-LF 402 3 ENET_MDI_TRAN_P_1
4
TLA-6T213HF
9 ENET_CENTER_TAP<3> 1
R3902
2 75
4
5
ENET_MDI_TRAN_N_1
C 1% 1/16W MF-LF 402 6

ENET_MDI_TRAN_P_2
ENET_MDI_TRAN_N_2
C
73 32 ENET_MDI_P<3> 5 8 ENET_MDI_TRAN_P<3> 7 ENET_MDI_TRAN_P_3
BI
8 ENET_MDI_TRAN_N_3
73 32 ENET_MDI_N<3> 6 7 ENET_MDI_TRAN_N<3>
BI
RX 10
CRITICAL
514-0523
1
T3902
SM 12 ENET_MDI_TRAN_N<2>
73 32 BI ENET_MDI_N<2>
73 32 BI ENET_MDI_P<2> 2 11 ENET_MDI_TRAN_P<2>
3 10
R3901
ENET_CENTER_TAP<2> 1 2 75
TX 1% 1/16W MF-LF 402
4
TLA-6T213HF
9 ENET_CENTER_TAP<0> 1
R3900
2 75
1% 1/16W MF-LF 402
73 32 BI ENET_MDI_N<0> 5 8 ENET_MDI_TRAN_N<0>
73 32 BI ENET_MDI_P<0> 6 7 ENET_MDI_TRAN_P<0>
RX
ENET_BOB_SMITH_CAP
CRITICAL
1 C3910
1000PF
B 10%
2KV
2 CERM
B
1206
9 =GND_CHASSIS_RJ45
A SYNC_MASTER=SUMA SYNC_DATE=04/04/2008 A
PAGE TITLE
ETHERNET CONNECTOR
DRAWING NUMBER SIZE

REVISION
R
A.0.0
39 OF 109
IV ALL RIGHTS RESERVED<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
7 mA I/O =PP3V3_FW_FWPHY 8 35 37
138 mA
C4120 1 C4121 1 C4122 1 C4123 1 C4124 1
1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10%
6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2
CERM CERM CERM CERM CERM
402 402 402 402 402
L4130
120-OHM-0.3A-EMI
D 114 mA FireWire PHY PP3V3_FW_FWPHY_VDDA 1 2 D
MIN_LINE_WIDTH=0.4 MM 0402-LF
VOLTAGE=3.3V
C4130 1 C4131 1 C4132 1
1UF 1UF 1UF
10% 10% 10%
6.3V 2 6.3V 2 6.3V 2
CERM CERM CERM
402 402 402
L4110 L4135
120-OHM-0.3A-EMI 120-OHM-0.3A-EMI
=PP1V0_FW_FWPHY 1 2 PP1V0_FW_FWPHY_AVDD 25 mA PCIe SerDes 17 mA PCIe SerDes PP3V3_FW_FWPHY_VP25 1 2
8
0402-LF MIN_LINE_WIDTH=0.4 MM MIN_LINE_WIDTH=0.4 MM 0402-LF
135 mA MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V VOLTAGE=3.3V
1 C4110 1 C4111 C4135 1 C4136 1
1UF 1UF 1UF 1UF
10% 10% 10% 10%
2 6.3V
CERM 2 6.3V
CERM
6.3V 2
CERM
6.3V 2
CERM
402 402 402 402
110 mA Digital Core 0 mA VReg PWR
1 C4100 1 C4101 1 C4102 1 C4103 1 C4104 1 C4105 1 C4106 C4141 1 1 C4140

1UF 1UF 1UF 1UF 1UF 1UF 1UF 0.1UF 1UF
10% 10% 10% 10% 10% 10% 10% 20% 10%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
6.3V
2 CERM 6.3V
2 CERM 2 6.3V
CERM
10V
CERM 2
6.3V
2 CERM
402 402 402 402 402 402 402 402 402
C PLACEMENT_NOTE=Place C4170 close to U1400

C
PLACEMENT_NOTE=Place C4171 close to U1400
B12
C13
E10
H12
M12
N11
C12
G12
L11
A12
L10
K12
C4170
A1
B1
E2
H2
K2
L1
N3
C1
F1
J1
L3
M2
D5
D6
D8
L5
L6
L9
1 10%
2 16V PCIE_FW_R2D_C_N 17 71
IN
0.1UF X5R 402
VDD10 VDD33 VDDH VP VP25 VREG_PWR C4171
1 10%
2 16V PCIE_FW_R2D_C_P IN 17 71
B13 ATBUSB N8 PCIE_FW_R2D_N 0.1UF X5R 402
NC PCIE_RXD0N 71
A13 ATBUSH CRITICAL N7 PCIE_FW_R2D_P

PCIE_RXD0P 71
NC
A11 ATBUSN
U4100 PCIE_TXD0N N5 71 PCIE_FW_D2R_C_N C4175
1 10%
2 16V PCIE_FW_D2R_N
NC 0.1UF OUT 17 71
FW643E PCIE_TXD0P N6 71 PCIE_FW_D2R_C_P X5R 402
37 IN =FW_PHY_DS0 F12 DS0 (IPD) NT-19 C41761 10%
2 16V PCIE_FW_D2R_P
=FW_PHY_DS1 E12 DS1 BGA OUT 17 71
37 IN (IPD) NT-20 PCIE_CLK100M_FW_N 0.1UF X5R 402
OMIT REFCLKN N9 IN 17 71
37 IN =FW_PHY_DS2 E13 DS2 (IPD) NT-21 PCI EXPRESS PHY PLACEMENT_NOTE=PLACE C4175 CLOSE TO U4100
REFCLKP N10 PCIE_CLK100M_FW_P IN 17 71 PLACEMENT_NOTE=PLACE C4176 CLOSE TO U4100
74 37 BI FW_P0_TPA_N B8 TPA0N
74 37 BI FW_P0_TPA_P A8 TPA0P
NT-4 (IPU) TCK M4 TP_FW643_TCK
74 37 BI FW_P1_TPA_N B5 TPA1N
NT-3 (IPU) TDI N2 TP_FW643_TDI
74 37 BI FW_P1_TPA_P A5 TPA1P TEST CONTROLLER M1 TP_FW643_TDO
=PP3V3_FW_FWPHY 8 35 37
FW_P2_TPA_N B3 (IPU) TDO

37 BI TPA2N
NT-1 (IPU) TMS M3 TP_FW643_TMS
37 BI FW_P2_TPA_P A3 TPA2P 1394 PHY FW643_LDO
74 37 BI FW_P0_TPB_N B9 TPB0N NT-2 (IPU) TRST* N1 FW643_TRST_L R41651 1
R4166
74 37 BI FW_P0_TPB_P A9 TPB0P 10K 10K
5% 5%
74 37 BI FW_P1_TPB_N B6 TPB1N 1/16W 1/16W
MF-LF MF-LF
74 37 BI FW_P1_TPB_P A6 TPB1P 402 2 2 402
NT-10 (IPD) WAKE* C2 FW_PME_L OUT 19
37 BI FW_P2_TPB_N B4 TPB2N
37 =PPVP_FW_PHY_CPS FIXME!!! - TYPO IN SYMBOL REGCTL REGCLT D13 FW643_REGCTL
37 BI FW_P2_TPB_P A4 TPB2P
POWER MANAGEMENT VAUX_DETECT E1 FW643_VAUX_DETECT
R41601 37 BI FW_P0_TPBIAS B7 TPBIAS0 NT-12 (IPD) VAUX_DISABLE D2 TP_FW643_VAUX_ENABLE
B 390K
5%
1/16W
37
37
BI
BI
FW_P1_TPBIAS
FW_P2_TPBIAS
C3 TPBIAS1
A2 TPBIAS2
NT-13 (OD) CLKREQN L2 FW_CLKREQ_L OUT 17 1
R4164
10K
B
MF-LF 5%
402 2 1/16W
FW643_R0 B11 R0 MF-LF
FW643_TPCPS B10 TPCPS 2 402
NT-16 (IPD) SCIFCLK G2 TP_FW643_SCIFCLK
SCIF NT-14 (IPD) SCIFDAIN G1 TP_FW643_SCIFDAIN
C4150 TP_FW643_NAND_TREE K1 NAND_TREE NT-OUT
R4150 NT-17 SCIFDOUT H1 TP_FW643_SCIFDOUT
22PF FW643_REXT L8 REXT
1 2 390 NOTE: NT-xx notes show NT-15 (IPD) SCIFMC F2 TP_FW643_SCIFMC
FW_CLK24P576M_XO 1 2 FW_CLK24P576M_XO_R F13 XO
FW_CLK24P576M_XI G13 NAND tree order.
5% CRITICAL 5%
1/16W
XI NT-9
50V
Y4150 MF-LF
1
CERM 402 TP_FW643_SE M13 SE (IPD)

402 NC 24.576MHZ R41611 1
R4170 SERIAL EEPROM NT-7 SCL N12 FW643_SCL
2
SM-3.2X2.5MM TP_FW643_SM N13 SM (IPD)

C4151 NC 2.94K 191 CONTROLLER NT-6 SDA M11 TP_FW643_SDA
4
1% 1% TP_FW643_MODE_A J2 MODE_A (IPD) NT-18

3
22PF 1/16W 1/16W

TP_FW643_CE L13
1 2 MF-LF MF-LF CE (IPD)
402 2 2 402 TP_FW643_FW620_L D12 FW620* (IPU) MISCELLANEOUS
5% TP_FW643_JASI_EN D1 JASI_EN (IPD) NT-11
50V
CERM TP_FW643_AVREG A10 AVREG CHIP RESET NT-5 PERST* N4 FW_RESET_L 26
402 IN
TP_FW643_VBUF H13 VBUF
FW643_PU_RST_L K13 FW_RESET* (IPU) NT-8 1
R4163
10K
TP_FW643_OCR10_CTL J12 OCR_CTL_V10 5%
R41621 1 C4162 NC
J13 OCR_CTL_V12 (Reserved)
1/16W
MF-LF
470K 0.33UF 2 402
5% 10% VSS VREG_VSS
1/16W 6.3V
MF-LF 2 CERM-X5R
B2
D4
D7
D9
D10
E4
E5
E9
F4
F6
F7
F8
F10
G4
G6
G7
G8
G10
H4
H6
H7
H8
H10
J4
J5
J9
J10
K4
K5
K7
K8
K9
L7
K6
K10
L12
402 2 402
PAGE TITLE
FireWire LLC/PHY(FW643E)
DRAWING NUMBER SIZE

REVISION
R
A.0.0
41 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PPBUS_S5_FWPWRSW (system supply for bus power)
- =PP3V3_FW_LATEVG_ACTIVE
- =PPVP_FW_SUMNODE (power passthru summation node)
Signal aliases required by this page: FireWire Port Power Switch
(NONE)
CRITICAL CRITICAL
BOM options provided by this page: D4260
Q4260 CRITICAL
- FW_PORT_FAULT_PU PWRDI5
NDS9407 F4260
D 8 =PPBUS_S5_FWPWRSW
SOI-HF
8
1.5A-24V
1 2
2
=PPBUS_S5_FW_FET
D
3
PPBUS_FW_FWPWRSW_F PPBUS_FW_FWPWRSW_D 3 8
7 MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
2 MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 1
6 VOLTAGE=12.6V 1812L15024HF VOLTAGE=12.6V
1
R4260 1 PDS540XF
470K C4260 1 5
5% 0.01uF
1/16W 20%
MF-LF 16V
CERM 2 4
2 402 402
FWPWR_EN_L_DIV
1
R4261
330K
5%
1/16W
MF-LF
2 402
FWPWR_EN_L
Enables port power when machine
is running or on AC. Q4261 D 6
SSM6N15FEAPE Q4261 D 3
SOT563 SSM6N15FEAPE
SOT563
2 G S 1
SMC_ADAPTER_EN 5 G S 4
42 41 33 21 IN
64 41 33 21 IN PM_SLP_S3_L
FW_PORTPWR_EN_FET
C C
Q4262
SSM3K15FV D 3
SOD-VESM-HF
1 G S 2
36 FW_PORTPWR_EN
Late-VG Event Detection

37 8 =PP3V3_FW_LATEVG
37 PP2V4_FW_LATEVG
B R42111 1
R4212 1 C4210
0.1UF
1
R4219 B
10K 10K 20% 2.0M
5% 1% 5%
1/16W 1/16W 2 10V
CERM 1/16W
MF-LF MF-LF 402 MF-LF
402 2 2 402 2 402
2 U4210 D4219
P2V4_FWLATEVG_RC 4 LMC7211 SOD-123
V+ SM-HF
1 LATEVG_EVENT_L 2 1 FW_PORTPWR_EN 36
FWLATEGV_3V_REF 3 V- MBR0540XXH 1 C4219

5 0.33UF
1 10%
C4211 1 R4213 2 10V
CERM-X5R
100pF 80.6K 603
5% 1%
50V 1/16W
CERM 2 MF-LF
402 2 402 R4210
1
200K 2
FWLATEVG_3V_REF Hysteresis:
1%
1/16W
2.95V when port power is on
MF-LF
402
2.81V on late Vg event and port power is off
PAGE TITLE
FireWire Port Power

DRAWING NUMBER SIZE

REVISION
R
A.0.0
42 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
8 =PP3V3_FW_PHY
- =PPVP_FW_PORT1
- =PP3V3_FW_LATEVG
R43811 R43821 R43801
10K 10K 10K
1% 1% 1%
1/16W 1/16W 1/16W
- =GND_CHASSIS_FW_PORT1 MF-LF MF-LF MF-LF
402 2 402 2 402 2
- =GND_CHASSIS_FW_EMI_R
(NONE)
FireWire PHY Config Straps FWPHY_DS0
MAKE_BASE=TRUE
=FW_PHY_DS0 35
D
D NOTE: This page is expected to contain
Configures PHY for:
FWPHY_DS2
MAKE_BASE=TRUE
=FW_PHY_DS2 35
the necessary aliases to map the FWPHY_DS1 =FW_PHY_DS1 35

FireWire TPA/TPB pairs to their - 1-port Portable Power Class (0) MAKE_BASE=TRUE
appropriate connectors and/or to
OUT
properly terminate unused signals.
(NONE)
NOTE: FireWire TPA/TPB pairs are NOT
constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints 35 FW_P0_TPBIAS NC_FW0_TPBIAS MAKE_BASE=TRUE
to apply to entire TPA/TPB XNets. 35 FW_P2_TPBIAS NC_FW2_TPBIAS MAKE_BASE=TRUE
74 35 FW_P0_TPA_N NC_FW0_TPAN MAKE_BASE=TRUE
1394b implementation based on Apple FW_P0_TPA_P NC_FW0_TPAP MAKE_BASE=TRUE
74 35
FireWire Design Guide (FWDG 0.6, 5/14/03) FW_P2_TPA_N NC_FW2_TPAN MAKE_BASE=TRUE
BSS8402DW
35
35 FW_P2_TPA_P NC_FW2_TPAP MAKE_BASE=TRUE
Q4300
SOT-363
(SYM-VER2)
74 35 FW_P0_TPB_N NC_FW0_TPBN MAKE_BASE=TRUE
FW_P0_TPB_P NC_FW0_TPBP MAKE_BASE=TRUE
Termination 74 35
35 FW_P2_TPB_N
FW_P2_TPB_P
NC_FW2_TPBN MAKE_BASE=TRUE
NC_FW2_TPBP MAKE_BASE=TRUE
Place close to FireWire PHY =PPVP_FW_PHY_CPS_FET
35
D
PPVP_FW_CPS
3
=PPVP_FW_PHY_CPS 35
FW_P1_TPBIAS MAKE_BASE=TRUE
35
R43111 Cable Power
G
470K
5%
C
5
C 1 C4360
1/16W
MF-LF
402 2
0.33UF
10% CRITICAL
2 6.3V
CERM-X5R
402 L4310
CPS_EN_L_DIV FERR-250-OHM NOTE: TRACE PPVP_FW_PORT1 MUST HANDLE UP TO 1A
8 =PPVP_FW_PORT1 1 2 PPVP_FW_PORT1_F
SM MIN_LINE_WIDTH=0.5 mm
R43121 "Snapback" & "Late VG" Protection VOLTAGE=33V
330K
5%
1/16W
MF-LF
1 C4314
402 2 37 36 PP2V4_FW_LATEVG DP4310 0.01UF
10%
CPS_EN_L BAV99DW-X-G 2 50V
SOT-363 X7R
C4311 1 5
402
6 0.01uF
10%
D 50V 2 3
1 X7R
R4360 R43611 Q4300 402
4 CRITICAL
56.2 56.2 DP4310
1% 1% 2 G BSS8402DW
1/16W
MF-LF
2 402
1/16W
MF-LF
402 2
35 8 =PP3V3_FW_FWPHY
S
SOT-363
(SYM-VER1)
C4310 1
0.01uF
BAV99DW-X-G
SOT-363
2
CRITICAL
FL4320 PORT 1
74 35 FW_P1_TPA_P FW_PORT1_TPA_P 37
1 10%
50V 2
TCM2010-100-4P
MAKE_BASE=TRUE X7R
6 SM J4300
74 35 FW_P1_TPA_N FW_PORT1_TPA_N 37
402
1 1 8
1394A-MG3-K36
MAKE_BASE=TRUE F-RT-TH
74 35 FW_P1_TPB_P FW_PORT1_TPB_P 37
MAKE_BASE=TRUE 37 FW_PORT1_TPA_P 74 FW_PORT_A_P 6
TPA+
74 35 FW_P1_TPB_N FW_PORT1_TPB_N 37 2 7
MAKE_BASE=TRUE 37 FW_PORT1_TPA_N 74 FW_PORT_A_N 5
TPA-
1 37 FW_PORT1_TPB_P 3 6 74 FW_PORT_B_P 4
TPB+
R4362 R43631
B 56.2
1%
56.2
1%
37 FW_PORT1_TPB_N
5
74 FW_PORT_B_N 3
TPB- B
1/16W 1/16W 4
MF-LF MF-LF 1
2 402 402 2 POWER
2
GROUND
FW_PORT1_TPB_C
DP4311 C4316 1
7 8
BAV99DW-X-G 0.01uF
SOT-363 10%
1 50V 2
1 C4364 R4364
4.99K
2 X7R
402 =GND_CHASSIS_FW_UPPER 9
220pF 1%
DP4311
5% 1/16W 6 BAV99DW-X-G
2 25V
CERM MF-LF
402 2
C4312 1 SOT-363 =GND_CHASSIS_FW_DOWN 9
402 0.01uF 1 5
10%
50V 2
X7R 3
402 C4313 1
0.01uF 4
10%
50V 2
X7R
402
Late-VG Protection
R4390
Power
332 2
A 36 8 =PP3V3_FW_LATEVG 1
1%
PP2V4_FW_LATEVG
36 37
SYNC_MASTER=K36B_MLB SYNC_DATE=(MASTER) A
1/16W VOLTAGE=2.4V PAGE TITLE
MF-LF
402 3 CRITICAL ESD and late-VG rail
for snap-back diodes
FireWire Ports
D4390 (Common to all ports)
DRAWING NUMBER SIZE
MMBZ5227BLT1H
PP2V4_FWLATEVG needs to be biased SOT23 REVISION
1
to at least 2.1V for FW signal integrity
R
A.0.0
and should be biased to 2.4V for margin NOTICE OF PROPRIETARY PROPERTY: BRANCH
R4390 should be 390 Ohms max for a 3.3V rail THE INFORMATION CONTAINED HEREIN IS THE
43 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
Q4590
FDC606P_G PP5V_SW_ODD
6
SOT-6
MIN_LINE_WIDTH=0.6mm
5
MIN_NECK_WIDTH=0.4mm
VOLTAGE=5V
D
=PP5V_S0_ODD
2
8
1
R45961
ODD Power Control NOTE: 3.3V must be S0 if 5V is S3 or S5 to 1 C4595
G
10K 0.068UF
ensure the drive is unpowered in S3/S5. 5% 10%
1/16W
3
10V
38 8 =PP3V3_S0_ODD MF-LF
402 2 R4595
2 CERM
402
C4596
100K 2 0.01UF
1
ODD_PWR_EN_LS5V_L 1 ODD_PWR_SS 1 2
R4597
D 10K
5%
5%
1/16W
MF-LF
10%
16V
D
1/16W
MF-LF
Q4596 D 6 402 CERM
402
402 2 SSM6N15FEAPE
SOT563
ODD_PWR_EN
2 G S 1
Q4596 D 3
SSM6N15FEAPE
SOT563
5 G S 4
21 IN ODD_PWR_EN_L
SATA ODD Port

CRITICAL
J4500
2-1775184-0
M-ST-SM FL4520
90-OHM-100MA
PLACEMENT_NOTE=Place C4521 next to C4520
NC DLP11S PLACEMENT_NOTE=Place C4520 close to MCP79
SYM_VER-1
CRITICAL
3 4 SATA_ODD_R2D_UF_P 1 2 C4520 SATA_ODD_R2D_C_P IN 20 71
0.01UF 10% 16V CERM 402
2 SATA_ODD_R2D_UF_N 1 1 2 C4521 SATA_ODD_R2D_C_N IN 20 71

38 8 =PP3V3_S0_ODD 10% 16V CERM 402
0.01UF
71 7 SATA_ODD_D2R_C_P PLACEMENT_NOTE=Place FL4520 close to J4500
C R45901
SATA_ODD_D2R_C_N
PLACEMENT_NOTE=Place C4525 next to C4526 FL4525
90-OHM-100MA
C
33K PLACEMENT_NOTE=Place C4526 close to J4500 DLP11S
5% SATA_ODD_R2D_N SYM_VER-1
1/16W
MF-LF SATA_ODD_R2D_P C4525 1 2 71 SATA_ODD_D2R_UF_N 4 3 SATA_ODD_D2R_N OUT 20 71
402 2 10% 16V CERM 402
0.01UF
C4526 1 2 71 SATA_ODD_D2R_UF_P 1 2 SATA_ODD_D2R_P OUT 20 71
0.01UF 10% 16V CERM 402

NC CRITICAL
516S0719
41
PLACEMENT_NOTE=PLACE FL4525 CLOSE TO J4500

SATA CONNECTOR
7
OUT SMC_ODD_DETECT
Indicates disc presence
PLACE L4501 NEAR J4501 VALUE=3900PF IN REFERENCE SCHEM
CRITICAL CAPS TO BE SAME DISTANCE
FROM SB WITHIN EACH PAIR
518S0390 L4501
DLP11S C4503
90-OHM-100MA
2
1 2 SATA_HDD_R2D_UF_P SATA_HDD_R2D_C_P IN
CRITICAL
71 20
0.01UF
J4501 402 C4501
2
20247-019E
F-ST-SM
4 3 SATA_HDD_R2D_UF_N SATA_HDD_R2D_C_N IN 20 71
20 SYM_VER-1 0.01UF
402
1
2 71 7 SATA_HDD_R2D_P
3 71 7 SATA_HDD_R2D_N C4500
1
4
SATA_HDD_D2R_N OUT 20 71
5 SATA_HDD_D2R_C_N
71 7 0.01UF
402 C4502
B 6
B
1
71 7 SATA_HDD_D2R_C_P SATA_HDD_D2R_P OUT

7 L4590 FERR-70-OHM-4A
71 20
8 7 1
PP5V_S0_HDD_FLT 2 =PP5V_S0_HDD
0.01UF
402
8
9 NC 0603 NO STUFF
10 NO STUFF
11
1 C4590
0.1UF
1 C4591
10UF
12 10% 20%
2 16V 2 6.3V
13 X5R X5R
402 603
14
15
16
17 NC
18 NC
19 NC
21 SYSTEM (SLEEP) LED FILTER

R4522
10
7 SYS_LED_ANODE_L 1 2 SYS_LED_ANODE 42
5%
1/16W
1 C4522
0.01UF
MF-LF
402
10%
2 16V
CERM
402 PLACE R4522 AND C4522 NEAR J4501
A IR_RX_OUT OUT 7 40
PAGE TITLE
(TO IR RECEIVER)R4550 SATA Connectors

7 PP5V_S3_IR_CONN
100 1 2 =PP5V_S3_IR 8 40 DRAWING NUMBER SIZE
5%
1/16W Apple Inc. 051-8089 D
MF-LF
1 C4550
4.7UF
402 R
REVISION
A.0.0
20% PLACE R4550 AND C4550 NEAR J4501
6.3V NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 CERM
603 THE INFORMATION CONTAINED HEREIN IS THE
45 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Port Power Switch Left USB Port A

PLACEMENT_NOTE=NEAR J4600
CRITICAL CRITICAL
L4605
U4690 FERR-220-OHM-2.5A
TPS2064DGN
8 =PP5V_S3_EXTUSB 2 IN OUT1 7 PP5V_S3_RTUSB_A_ILIM 1 2 PP5V_S3_RTUSB_A_F
MSOP MIN_LINE_WIDTH=0.5 mm
0603
MIN_LINE_WIDTH=0.5 mm OMIT
MIN_NECK_WIDTH=0.5 mm MIN_NECK_WIDTH=0.5 mm
USB_EXTA_OC_L 8 VOLTAGE=5V VOLTAGE=5V
20 OUT OC1*
3 6 PP5V_S3_RTUSB_B_ILIM
C4605 1
CRITICAL
EN1 OUT2 0.01uF
20 OUT USB_EXTB_OC_L 5
OC2*
20%
16V
CRITICAL J4600
4 VOLTAGE=5V CERM 2
L4600 USB-K36-MG3
64 IN =USB_PWR_EN EN2 402 F-RT-TH
90-OHM
DLP0NS 5
GND TPAD SYM_VER-1
1 9 CRITICAL CRITICAL 72 USB2_EXTA_MUXED_N 4 72 3 USB2_EXTA_F_N VBUS

1
C4690 1 1 C4691 2 D-
10UF 0.1UF C4695 1 1
C4696 C4617 1 1
C4616
20% 20% 10UF 100UF 10UF 100UF 72 USB2_EXTA_MUXED_P 1 72 2 USB2_EXTA_F_P 3 D+
6.3V 10V 20% 20% 20% 20%
X5R 2 2 CERM 6.3V 6.3V 4 GND
603 402 X5R 2 2 6.3V X5R 2 2 6.3V
POLY-TANT POLY-TANT
603 CASE-B2-SM 603 CASE-B2-SM
2 5 3 4 6
NC
IO
NC
IO
6 VBUS 514-0527
C 1 GND C
D4600
RCLAMP0502N
SLP1210N6
CRITICAL CRITICAL
We can add protection to 5V if we want, but leaving NC for now
L4615
FERR-220-OHM-2.5A
1 2 Place L4600 and L4605 at connector pin
PP5V_S3_RTUSB_B_F
0603 MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
1
C4615
USB/SMC Debug Mux 0.01uF
20%
16V
2 CERM
402 OMIT
8 =PP3V42_G3H_SMCUSBMUX CRITICAL
SMC_DEBUG_YES
SMC_DEBUG_YES J4601
1
1
R4650 USB-K36-MG3
C4650 10K
F-RT-TH
0.1UF CRITICAL 5
20%
10V
5%
1/16W L4610
90-OHM
CERM 2 MF-LF
DLP0NS
2 402
402 VBUS
SYM_VER-1 1
4 3 2 D-
USB_EXTB_N USB2_EXTB_F_N
9
72 20 72
BI
72 USB2_EXTB_F_P 3 D+
VCC
4 GND
43 42 41 7 SMC_RX_L 5 M+SMC_DEBUG_YESY+ 1 72 20 USB_EXTB_P 1 2
IN BI
SMC_TX_L 4 M- Y- 2
43 42 41 7 OUT U4650 6
B USB_EXTA_P 7 D+
PI3USB102ZLE
TQFN
2 5 3 4
514-0527 B
NC
IO
NC
IO
72 20 BI
72 20 USB_EXTA_N 6 D- 6 VBUS
BI
CRITICAL
1 GND
8 OE* SEL 10 USB_DEBUGPRT_EN_L IN 41
GND SEL=0 Choose SMC

SEL=1 Choose USB
D4610
3
RCLAMP0502N
SLP1210N6
CRITICAL
SMC_DEBUG_NO
R4651
0
1 2
5%
1/16W
MF-LF
402
SMC_DEBUG_NO
R4652
Left USB Port B
0
1 2
5%
1/16W
MF-LF
402
PAGE TITLE
External USB Connectors

DRAWING NUMBER SIZE

REVISION
R
A.0.0
46 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
IR CTRL BLUETOOTH
38 8 =PP5V_S3_IR
PLACE L4810 NEAR J4800
1
C4801 PLACE C4810 C4811 NEAR 120-OHM-0.3A-EMI
L4810
L4810
0.1UF
10% 8 =PP3V3_S3_BT 1 2
16V
2 X7R-CERM 0402-LF
402
1 C4810 1 C4811
10UF
20%
0.1UF
20%
2 6.3V
10V
2 CERM
X5R
603 402
16
NET_SPACING_TYPE=USB
DIFFERENTIAL_PAIR=USB2_IR VDD
72 20 NET_PHYSICAL_TYPE=USB_90D USB_IR_P 14 P1_0/D+ P0_0 7
BI
C 72 20 BI
DIFFERENTIAL_PAIR=USB2_IR
USB_IR_N 15
18
P1_1/D- P0_1 6
5
CRITICAL
J4810 C
IR_VREF_FILTER P1_2/VREG P0_2/INT0
NET_PHYSICAL_TYPE=USB_90D
NET_SPACING_TYPE=USB
20 4
PLACE L4800 NEAR J4810 78171-0004
P1_3/SSEL P0_3/INT1 CRITICAL M-RT-SM
5
1
C4803
23 P1_4/SCLK P0_4/INT2 3
L4812
1UF
24 P1_5/SMOSI P0_5/TIO0 2 IR_RX_OUT_RC
R4800 SB HAS INTERNAL 15K PULL-DOWNS 90-OHM
DLP0NS
10% 25 P1_6/MISO P0_6/TIO1 1 100 SYM_VER-1 7 PP3V3_S3_BT_F_CONN1
10V 1 2 IR_RX_OUT
2 IN 7 38 4 3 2
X5R 26 P1_7 OMIT P0_7 32 9 =USB2_BT_N 72 7 USB2_BT_F_N_CONN
402-1 5%
U4800 1/16W
MF-LF
72 7 USB2_BT_F_P_CONN 3 TO M13D SLOT
7 GND_BT_F_CONN 4
21 P3_0 CY7C63833 P2_0 9 1
C4804 402
9 =USB2_BT_P 1 2
QFN
22 P3_1 P2_1 8 0.001UF
10%
CRITICAL 50V 6
2
CERM
27 10 402
P/N 338S0375
28 11
518S0521
29 12
NC NC
30 17
31 19
THRM_PAD VSS
120-OHM-0.3A-EMI
L4811
33
13
1 2
0402-LF
PLACE L4811 NEAR J4810
CYPRESS ’ENCORE II’ USB CONTROLLER
B B
PAGE TITLE
Front Flex Support

DRAWING NUMBER SIZE

REVISION
R
A.0.0
48 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
42 PP3V3_S5_AVREF_SMC
50 42 8 =PP3V3_S5_SMC
D D
C4902 1 1 C4903 1 C4904 1 C4905 1 C4906
22UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20%
6.3V 10V 10V 10V 10V
CERM 2 2 CERM 2 CERM 2 CERM 2 CERM
805 402 402 402 402
SMC_EXCARD_PWR_EN
U4900 SMC_PM_G2_EN
PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
42 P10 H8S2117 P60 OUT 64
42 OUT SMC_RSTGATE_L P11 LGA-HF P61 NC SMC_VCL

ALL_SYS_PWRGD P12 (1 OF 3) P62 R4999
64 26 7 IN NC 4.7
64 RSMRST_PWRGD P13 OMIT P63 1 2 PP3V3_S5_SMC_AVCC
IN NC MIN_LINE_WIDTH=0.25 MM C4907 1
P14 P64 SMC_ADAPTER_EN 21 33 36 42 5% MIN_NECK_WIDTH=0.20 MM
NC OUT 1/16W VOLTAGE=3.3V
0.47UF
PM_RSMRST_L P15 P65 MF-LF C4920 1 10%
21 OUT NC 402 6.3V
2
60 IMVP_VR_ON P16 P66 SMC_PROCHOT_3_3_L 42 0.1UF CERM-X5R
OUT IN 20% 402
PM_PWRBTN_L SMC_BIL_BUTTON_L 10V AVCC VCC VCL AVREF
21 OUT P17 P67 IN 42 CERM 2 1 1
402 R4909 R4901
42 OUT ESTARLDO_EN P20 P70 SMC_CPU_ISENSE IN 46
U4900 NC NC 10K 10K
P21 P71 SMC_CPU_VSENSE 45
PLACEMENT_NOTE=PLACE R4999 CLOSE TO U4900 PINS M12 H8S2117 5%
1/16W
5%
1/16W
NC IN
PLACEMENT_NOTE=PLACE C4920 CLOSE TO U4900 PINS M12 LGA-HF MF-LF MF-LF
P22 P72 SMC_GPU_ISENSE 402 2 2 402
42
NC IN
(3 OF 3)
NC P23 P73 SMC_GPU_VSENSE IN 42
OMIT MD1 SMC_MD1 IN 7 43
42 SMC_P24 P24 P74 SMC_DCIN_ISENSE IN 46
MD2 SMC_KBC_MDE
P25 P75 SMC_PBUS_VSENSE 45 43 42 7 SMC_RESET_L RES*
NC IN IN
42 SMC_P26 P26 P76 SMC_BATT_ISENSE IN 46
42 SMC_XTAL XTAL
P27 P77 SMC_NB_MISC_ISENSE 42
NC IN
42 SMC_EXTAL EXTAL NMI SMC_NMI IN 7 43
72 43 19 7 BI LPC_AD<0> P30 P80 SMC_WAKE_SCI_L OUT 21
72 43 19 7 BI LPC_AD<1> P31 P81 NC

72 43 19 7 BI LPC_AD<2> P32 P82 PM_CLKRUN_L OUT 7 19 43
ETRST SMC_TRST_L IN 7 43
C 72 43 19 7
72 43 19 7
BI
IN
LPC_AD<3>
LPC_FRAME_L
P33
P34
P83
P84
LPC_PWRDWN_L
SMC_TX_L
IN
OUT
7 19 43
7 39 41 42 43 AVSS 1 1 1
NO STUFF C
26 IN SMC_LRESET_L P35 P85 SMC_RX_L IN 7 39 41 42 43 VSS R4902 R4998 R4903
10K 10K 0
72 26 IN LPC_CLK33M_SMC P36 P86 (OC) SMB_MGMT_CLK BI 44 5% 5% 5%
1/16W 1/16W 1/16W
43 19 7 BI LPC_SERIRQ P37 XW4900 MF-LF MF-LF MF-LF
P90 SMC_ONOFF_L IN 42 49 SM
2 402 2 402 2 402
NC P40 P91 SMC_BC_ACOK IN 42 56 57 2 1
42 SMC_P41 P41 P92 SMC_BS_ALRT_L IN 42 56
44 BI SMB_MGMT_DATA (OC) P42 P93 PM_SLP_S3_L IN 21 33 36 64
50 OUT SMS_ONOFF_L P43 P94 PM_SLP_S4_L IN 21 42 64
NC P44 P95 PM_SLP_S5_L IN 42 NOTE: P94 and P95 are shorted, P95 could be spare.
GND_SMC_AVSS 42 45 46
NC P45 P96 PM_CLK32K_SUSCLK IN 26 72
42 OUT SMC_GFX_THROTTLE_L P46 P97 (OC) SMB_0_S0_DATA BI 44
42 OUT SMC_SYS_KBDLED P47
43 42 41 39 7 OUT SMC_TX_L P50

43 42 41 39 7 IN SMC_RX_L P51
44 BI SMB_0_S0_CLK (OC) P52
SMC_PA0
U4900 SMC_CASE_OPEN
(DEBUG_SW_1) 42 PA0 H8S2117 PE0 IN 42
(DEBUG_SW_2) SMC_PA1
42 PA1 LGA-HF PE1 SMC_TCK IN 7 42 43
26 OUT PM_SYSRST_L (OC) PA2 (2 OF 3) PE2 SMC_TDI IN 7 42 43
39 OUT USB_DEBUGPRT_EN_L (OC) PA3 OMIT PE3 SMC_TDO OUT 7 42 43
29 28 21 BI MEM_EVENT_L (OC) PA4 PE4 SMC_TMS IN 7 42 43
B 56 42 BI
42 SMC_PA5
SYS_ONEWIRE
(OC)
(OC)
PA5
PA6
PF0 NC B
PF1 SMC_SYS_LED OUT 42
21 OUT PM_BATLOW_L (OC) PA7
PF2 SMC_LID IN 42 49 56
NC PB0 PF3 NC
21 SMC_RUNTIME_SCI_L PB1 PF4
OUT NC
38 7 IN SMC_ODD_DETECT PB2 PF5 SMC_MCP_SAFE_MODE OUT 9
42 OUT SMC_PB3 PB3 PF6 NC

42 IN SMC_EXCARD_CP PB4 PF7 NC
NC PB5
PG0 NC
42 IN SMC_EXCARD_OC_L PB6
PG1 =SMC_SMS_INT IN 42 NOTE: SMS Interrupt can be active high or low, rename net accordingly.
42 IN SMC_GFX_OVERTEMP_L PB7
PG2 (OC) SMB_BSA_DATA BI 44 If SMS interrupt is not used, pull up to SMC rail.
48 OUT SMC_FAN_0_CTL PC0 PG3 (OC) SMB_BSA_CLK BI 44
42 OUT SMC_FAN_1_CTL PC1 PG4 (OC) SMB_A_S3_DATA BI 44
42 OUT SMC_FAN_2_CTL PC2 PG5 (OC) SMB_A_S3_CLK BI 44
42 OUT SMC_FAN_3_CTL PC3 PG6 (OC) SMB_B_S0_DATA BI 44
48 IN SMC_FAN_0_TACH PC4 PG7 (OC) SMB_B_S0_CLK BI 44
42 IN SMC_FAN_1_TACH PC5
PH0 SMC_PROCHOT OUT 42
PH1 SMC_THRMTRIP OUT 42
PH2 SMC_FWE IN 42
50 IN SMS_X_AXIS PD0 PH3 ALS_GAIN OUT 42
50 SMS_Y_AXIS PD1 PH4

IN NC
50 SMS_Z_AXIS PD2 PH5
IN NC
42 IN SMC_ANALOG_ID PD3
46 IN SMC_MCP_CORE_ISENSE PD4
SMC_MCP_DDR_ISENSE
A 46
42
IN
IN ALS_LEFT
PD5
PD6 SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 A
42 ALS_RIGHT PD7 PAGE TITLE
IN
SMC
DRAWING NUMBER SIZE

REVISION
R
A.0.0
49 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SMC Reset "Button" / Brownout Detect 41 SMC_FAN_1_CTL NC_SMC_FAN_1_CTL SMC FSB to 3.3V Level Shifting
MAKE_BASE=TRUE NO_TEST=TRUE
41 SMC_FAN_1_TACH NC_SMC_FAN_1_TACH
50 42 41 8 =PP3V3_S5_SMC 42 8 =PP3V3_S0_SMC
41 SMC_FAN_2_CTL NC_SMC_FAN_2_CTL
1
41 SMC_FAN_2_TACH NC_SMC_FAN_2_TACH
R5060
1 1
C5000 CRITICAL R5000 470
41 SMC_FAN_3_CTL NC_SMC_FAN_3_CTL 8 =PP1V05_S0_SMC_LS 5%
0.1uF 1K MAKE_BASE=TRUE NO_TEST=TRUE 1/16W
20%
10V
CERM 2
U5000 5%
1/16W 41 SMC_FAN_3_TACH NC_SMC_FAN_3_TACH
MF-LF
402 TO SMC
402 NCP303LSN MF-LF MAKE_BASE=TRUE NO_TEST=TRUE
1
R5061
2
SOT23-5-HF 2
402
SMC_PROCHOT_3_3_L
3.3K OUT 41
41 SMC_GFX_OVERTEMP_L TP_SMC_GFX_OVERTEMP_L
D
5%
SMC_MANUAL_RST_L 5 CD OUT 1 SMC_RESET_L
D NO STUFF NO STUFF NC 4 NC IN 2
OUT 7 41 43
41 SMC_GFX_THROTTLE_L
MAKE_BASE=TRUE
SMC_IG_THROTTLE_L 21
2
1/16W
MF-LF
402 3
1
R5001
1
R5002
GND MAKE_BASE=TRUE
Q5060
1 CPU_PROCHOT_BUF 5
C5001 3 BC847BV-X-F
0 0 57 56 42 41 SMC_BC_ACOK =CHGR_ACOK
SOT563-HF
5% 5%
0.01UF MAKE_BASE=TRUE
10%
1/10W 1/10W
16V 4
MF-LF MF-LF 2 41 ALS_GAIN NC_ALS_GAIN TO CPU 6
SILK_PART=SMC_RST 603 603
CERM
MAKE_BASE=TRUE
R5062
2 2 402
3.3K
2
Q5060
SILK_PART=SMC_RST 69 60 14 10 BI CPU_PROCHOT_L 1 2 CPU_PROCHOT_L_R BC847BV-X-F
5%
SOT563-HF
1/16W
1
PLACE R5015,R5001 ON BOTTOM SIDE MF-LF
PLACE R5016,R5002 ON TOP SIDE 402
6 D Q5059
41 SMC_PB3 NC_SMC_PB3
MAKE_BASE=TRUE SSM6N15FEAPE
SOT563
41 SMC_P24 TP_SMC_P24
MAKE_BASE=TRUE
41 SMC_P26 SMC_BMON_MUX_SEL 46
SMC Crystal Circuit Debug Power "Button" 41 SMC_P41
MAKE_BASE=TRUE
TP_SMC_P41 1
S G 2
MAKE_BASE=TRUE
SMC_RSTGATE_L TP_SMC_RSTGATE_L SMC_PROCHOT IN 41
41
MAKE_BASE=TRUE
C5010 SMC_EXCARD_PWR_EN TP_SMC_EXCARD_PWR_EN
R5010 15pF
41
MAKE_BASE=TRUE
0 1 2 41 ALS_RIGHT NC_ALS_RIGHT 69 14 10 OUT PM_THRMTRIP_L
41 SMC_XTAL 1 2 SMC_XTAL_R SMC_ONOFF_L OUT 41 42 49
5% NO STUFF NO STUFF 41 ESTARLDO_EN NC_ESTARLDO_EN
5%
1/10W CRITICAL 50V SILK_PART=PWR_BTN 1SILK_PART=PWR_BTN MAKE_BASE=TRUE NO_TEST=TRUE 3 D
MF-LF 1
1
R5015 R5016 SMC_ANALOG_ID NC_SMC_ANALOG_ID Q5059
603 Y5010 CERM
402
41
MAKE_BASE=TRUE NO_TEST=TRUE SSM6N15FEAPE
20.00MHZ 0 0
5% 5% PLACE R5015,R5001 ON BOTTOM SIDE 41 SMC_SYS_KBDLED NC_SMC_SYS_KBDLED SOT563
5X3.2-SM
C5011 1/10W 1/10W PLACE R5016,R5002 ON TOP SIDE MAKE_BASE=TRUE NO_TEST=TRUE
2 MF-LF MF-LF =SMC_SMS_INT SMS_INT_L
41 50
15pF 2
603
2 603
MAKE_BASE=TRUE
SMC_EXTAL 1 2 SMC_MCP_VSENSE SMC_GPU_VSENSE
41 45 41
4
S G 5
5% 46 SMC_CPU_FSB_ISENSE ALS_LEFT 41 SMC_THRMTRIP IN 41

50V
CERM
C 402
C
50 42 41 8 =PP3V3_S5_SMC
41 SMC_PA0 R5091 100K 1 2

5% 1/16W MF-LF 402
41 SMC_PA1 R5092 100K 1 2
5% 1/16W MF-LF 402
SMC AVREF Supply CRITICAL
VR5020 49 42 41 SMC_ONOFF_L R5070 10K 1 2
REF3333 5% 1/16W MF-LF 402

56 49 41 SMC_LID R5071 100K 1 2
SOT23-3
R5095 5% 1/16W MF-LF 402
8 =PPVIN_S5_SMCVREF 1 IN OUT 2 PP3V3_S5_AVREF_SMC 41 0 41 SMC_FWE R5072 10K 1 2
MIN_LINE_WIDTH=0.4 mm 41 SMC_EXCARD_OC_L 1 2 EXCARD_OC_L 20 5% 1/16W MF-LF 402
OUT IN SMC_TX_L R5073 10K 1 2
MIN_NECK_WIDTH=0.2 mm 43 41 39 7
GND VOLTAGE=3.3V 5% 5% 1/16W MF-LF 402
1/16W 43 41 39 7 SMC_RX_L R5074 100K 1 2
3 MF-LF 5% 1/16W MF-LF 402
1
C5026 402
ONEWIRE_PU
0.01UF
10%
56 41 SYS_ONEWIRE R5075 2.0K 1 2
16V
2 5% 1/16W MF-LF 402
CERM
56 41 SMC_BS_ALRT_L R5076 100K 1 2
402
5% 1/16W MF-LF 402
1
C5020 C5025 1
43 41 7 SMC_TMS R5077 10K 1 2
5% 1/16W MF-LF 402
0.47UF 10uF 43 41 7 SMC_TDO R5078 10K 1 2
10% 20%
5% 1/16W MF-LF 402
2
6.3V 6.3V
2 43 41 7 SMC_TDI R5079 10K 1 2
CERM-X5R X5R
5% 1/16W MF-LF 402
402 603
43 41 7 SMC_TCK R5080 10K 1 2
5% 1/16W MF-LF 402
41 SMC_BIL_BUTTON_L R5081 10K 1 2
GND_SMC_AVSS 41 45 46 5% 1/16W MF-LF 402
MIN_LINE_WIDTH=0.4 mm 57 56 42 41 SMC_BC_ACOK R5087 470K 1 2
MIN_NECK_WIDTH=0.2 mm 5% 1/16W MF-LF 402

VOLTAGE=0V
B R5055 B
1
10K 2
41 SMC_NB_MISC_ISENSE
5%
1/16W
MF-LF
402
System (Sleep) LED Circuit R5054

SMC_GPU_ISENSE 1
10K 2
41
5%
8 =PP5V_S3_SYSLED 1/16W
41 36 33 21 SMC_ADAPTER_EN R5085 10K MF-LF
1 2
402 5% 1/16W MF-LF 402
41 SMC_CASE_OPEN R5086 10K 1 2
5% 1/16W MF-LF 402

1 1
R5031 R5030 41 SMC_EXCARD_CP R5088 10K 1 2
2.37K 100 5% 1/16W MF-LF 402
1% 5%
1/16W 1/16W
MF-LF MF-LF 41 PM_SLP_S5_L R5090 22K 1 2
402 2 2 402 5% 1/16W MF-LF 402

64 41 21 PM_SLP_S4_L NEED TO TUNE VALUE FOR POWER SAVING
SYS_LED_ILIM
2 42 8 =PP3V3_S0_SMC
SOD
SYS_LED_L_VDIV 2SA2154MFV-YAE
1
Q5030 SMC_PA5 R5089 10K 1 2
41
5% 1/16W MF-LF 402
R5032 1
3
9.09K
1% SYS_LED_ANODE OUT 38
1/16W
MF-LF
402
2
SYS_LED_L
A Q5032
SSM3K15FV
D 3 PAGE TITLE
SOD-VESM-HF
SMC Support
DRAWING NUMBER SIZE
41 SMC_SYS_LED
IN
1 G S 2
REVISION
R
A.0.0
ADD NC ALIASES FOR FAN1 SIGNALS I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

50 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LPC+SPI Connector
CRITICAL
LPCPLUS
J5100
55909-0374
M-ST-SM
D 43 8 =PP3V3_S5_LPCPLUS 31 32 D
8 =PP5V_S0_LPCPLUS
1 2 LPC_CLK33M_LPCPLUS IN 7 26 72
72 41 19 7 BI LPC_AD<0> 3 4 LPC_AD<2> BI 7 19 41 72
72 41 19 7 BI LPC_AD<1> 5 6 LPC_AD<3> BI 7 19 41 72
7 8
Alternate SPI ROM Support 43 7

IN
OUT
SPI_ALT_MOSI
SPI_ALT_MISO
9
11
10
12
SPIROM_USE_MLB
SPI_ALT_CLK
OUT
IN
7 43
7 43
72 41 19 7 IN LPC_FRAME_L 13 14 SPI_ALT_CS_L IN 7 43
41 19 7 OUT PM_CLKRUN_L 15 16 LPC_SERIRQ BI 7 19 41
42 41 7 OUT SMC_TMS 17 18 LPC_PWRDWN_L IN 7 19 41
26 7 IN DEBUG_RESET_L 19 20 SMC_TDI OUT 7 41 42
42 41 7 OUT SMC_TDO 21 22 SMC_TCK OUT 7 41 42
41 7 IN SMC_TRST_L 23 24 SMC_RESET_L OUT 7 41 42
41 7 OUT SMC_MD1 25 26 SMC_NMI OUT 7 41
42 41 39 7 IN SMC_TX_L 27 28 SMC_RX_L OUT 7 39 41 42

43 8 =PP3V3_S5_LPCPLUS 29 30 LPCPLUS_GPIO OUT 7 18
51 43 8 =PP3V3_S5_ROM
33 34
R51441 1 C5144
10K 0.1UF
5% 20%
1/16W 10V
2 CERM
MF-LF 402
402 2
516S0573
9
VCC
1 Y+ LPCPLUS
72 43 21 IN SPI_CLK_R M+ 5 SPI_ALT_CLK OUT 7 43
2 Y- M- 4
C R5164 1
72 43 21 IN SPI_MOSI_R
U5110
PI3USB102ZLE
SPI_ALT_MOSI OUT 7 43
43 8 =PP3V3_S5_LPCPLUS C
10K TQFN D+ 7 SPI_CLK_MUX 43 51 72
OUT
5%
1/16W D- 6 SPI_MOSI_MUX OUT 43 51 72
R51401
MF-LF 100K
402 2 5%
1/16W
43 7 SPIROM_USE_MLB 10 SEL OE* 8 MF-LF
402 2
GND
43 7 SPIROM_USE_MLB =SPI_CS1_R_L_USE_MLB BI 21
3
MAKE_BASE=TRUE
43 8 =PP3V3_S5_LPCPLUS
1 C5145
0.1UF
20%
10V
2 CERM
402 SPI_ALT_MISO 7 43
IN
9
VCC LPCPLUS
43 21 SPI_MISO 1 Y+ LPCPLUS M+ 5
R5166
OUT 0
SPI_CS0_R_L 2 Y- M- 4 SPI_ALT_CS_L_MUX 1 2 SPI_ALT_CS_L
72 21 IN U5120 5% 1/16W
OUT 7 43
PI3USB102ZLE MF-LF 402

TQFN D+ 7 SPI_MISO_MUX 43 51 72
IN
LPCPLUS
D- 6 SPI_MLB_CS_L_MUX R5165
0
B 10 SEL OE* 8 5%
1
402 1/16W MF-LF
2 SPI_MLB_CS_L OUT 51
B
GND
3
R51611
20K
5%
1/16W
MF-LF
402 2
LPCPLUS_NO
R5160 =PP3V3_S5_ROM 8 43 51
1 2
0
5% 1/16W
MF-LF 402
SPI Bus Series Resistance Option

LPCPLUS_NO
R5156
33
72 51 43 OUT SPI_CLK_MUX 1 2 SPI_CLK_R IN 21 43 72
5% LPCPLUS_NO
1/16W
MF-LF
402 R5157
33
72 51 43 OUT SPI_MOSI_MUX 1 2 SPI_MOSI_R IN 21 43 72
LPCPLUS_NO 5%
1/16W
MF-LF
R5158 402
0
72 51 43 IN SPI_MISO_MUX 1 2 SPI_MISO OUT 21 43
A 5%
1/16W
MF-LF
402
PAGE TITLE
LPC+SPI Debug Connector

DRAWING NUMBER SIZE

REVISION
R
A.0.0
51 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP79 SMBUS "0" CONNECTIONS SMC "0" SMBus Connections SMC "A" SMBus Connections
NOTE: SMC RMT bus remains powered and may be active in S3 state
8 =PP3V3_S0_SMBUS_SMC_0_S0
44 8 =PP3V3_S0_SMBUS_MCP_0 8 =PP3V3_S3_SMBUS_SMC_A_S3
R5270 1 1
R5271
MCP79 R5200 1 1
R5201 SO-DIMM "A" SMC R52501 1
R5251 MCP Temp SMC 1K 1K MINI-PCIE
4.7K 4.7K 4.7K 4.7K 5% 5%
U1400 5% 5% J3100 U4900 5% 5% EMC1403-5: U5535 U4900 1/16W 1/16W J3400
1/16W 1/16W 1/16W 1/16W MF-LF MF-LF
(MASTER) MF-LF MF-LF (Write: 0xA0 Read: 0xA1) (MASTER) MF-LF MF-LF (Write: 0x98 Read: 0x99) (MASTER) 402 2 2 402 (Write: 0x52 Read: 0x53)
402 2 2 402 402 2 2 402
D 72 21 13 7 SMBUS_MCP_0_CLK
MAKE_BASE=TRUE
=I2C_SODIMMA_SCL 28 41 SMB_0_S0_CLK 75 SMBUS_SMC_0_S0_SCL
MAKE_BASE=TRUE
=I2C_MCPTHMSNS_SCL 47 41 SMB_A_S3_CLK 75 SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
I2C_MINI_PCIE_SCL 7 31
D
72 21 13 7 SMBUS_MCP_0_DATA =I2C_SODIMMA_SDA 28 41 SMB_0_S0_DATA 75 SMBUS_SMC_0_S0_SDA =I2C_MCPTHMSNS_SDA 47 41 SMB_A_S3_DATA 75 SMBUS_SMC_A_S3_SDA I2C_MINI_PCIE_SDA 7 31
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
SO-DIMM "B"
J3200
(Write: 0xA2 Read: 0xA3)
C5250 1 1 C5251
22PF 22PF C5270 1 1 C5271
5% 5%
50V
2 50V
2 CERM 22PF 22PF
=I2C_SODIMMB_SCL 29
CERM 5% 5%
402 402 50V 50V
CERM 2 2 CERM
=I2C_SODIMMB_SDA 402 402
29
C5250,C5251 close to Destination end

C5270,C5271 close to destination end
SMC "Battery A" SMBus Connections SMC "B" SMBus Connections

=PP3V42_G3H_SMBUS_SMC_BSA
8 =PP3V3_S0_SMBUS_SMC_B_S0
8
1
R5280 1
1K R5281 1 1
SMC 5% 1K Battery SMC R5260 R5261 CPU Temp
1/16W 5% 4.7K 4.7K
U4900 MF-LF 1/16W J6950 U4900 5% 5% EMC1403-5: U5515
402 2 MF-LF 1/16W 1/16W
(MASTER) 2 402
(See Table) (MASTER) MF-LF MF-LF (Write: 0x98 Read: 0x99)
MCP79 SMBUS "1" CONNECTIONS 402
2 2
402
C 41 SMB_BSA_CLK
SMB_BSA_DATA
75 SMBUS_SMC_BSA_SCL
MAKE_BASE=TRUE
75 SMBUS_SMC_BSA_SDA
=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
56 41 SMB_B_S0_CLK
SMB_B_S0_DATA
75 SMBUS_SMC_B_S0_SCL
MAKE_BASE=TRUE
75 SMBUS_SMC_B_S0_SDA
=I2C_CPUTHMSNS_SCL
=I2C_CPUTHMSNS_SDA
47
C
44 8 =PP3V3_S0_SMBUS_MCP_0 41
MAKE_BASE=TRUE
56 41
MAKE_BASE=TRUE
47
HDCP ROM
1 1
R5230 R5231 U2690 OR U2695
MCP79 10K 10K (Write: 0xA0-0xAE,
Battery Charger
U1400 5% 5% ISL6258A - U7000
1/16W 1/16W Read: 0xA1-0xAF)
(MASTER?) MF-LF MF-LF (Write: 0x12 Read: 0x13)
402 2
2 402
(All 8 addresses used)
SMBUS_MCP_1_CLK =I2C_HDCPROM_SCL
=SMBUS_CHGR_SCL 57 C5260 1 1 C5261
72 21
MAKE_BASE=TRUE
25
=SMBUS_CHGR_SDA 57 22PF 22PF
5% 5%
SMBUS_MCP_1_DATA =I2C_HDCPROM_SDA 50V 50V
2 2 CERM
72 21
MAKE_BASE=TRUE
25
C5280 1 1 C5281 CERM
402 402
22PF 22PF
Battery 5%
50V 2
5%
2 50V
CERM CERM
402 402
Battery Manager - (Write: 0x16 Read: 0x17)
C5260,C5261 close to destination end
Battery Temp - (Write: 0x90 Read: 0x91) C5280,C5281 close to destination end
SMC "Management" SMBus Connections

The bus formerly known as "Battery B"
8 =PP3V3_S3_SMBUS_SMC_MGMT
1 1
SMC R5290 R5291 Vref DACs
4.7K 4.7K
U4900 5% 5% U2900
1/16W 1/16W
(MASTER) MF-LF MF-LF (Write: 0x98 Read: 0x99)
B 402 2
2 402 B
41 SMB_MGMT_CLK 75 SMBUS_SMC_MGMT_SCL =I2C_VREFDACS_SCL 27
MAKE_BASE=TRUE
41 SMB_MGMT_DATA 75 SMBUS_SMC_MGMT_SDA =I2C_VREFDACS_SDA 27
MAKE_BASE=TRUE
Margin Control
U2901
(Write: 0x30 Read: 0x31)
=I2C_PCA9557D_SCL 27
=I2C_PCA9557D_SDA 27
SMS
U5930
(Write: 0x70 Read: 0x71)
=I2C_SMS_SCL
=I2C_SMS_SDA
PAGE TITLE
SMBUS CONNECTIONS
DRAWING NUMBER SIZE

REVISION
R
A.0.0
52 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU Voltage Sense / Filter

XW5309 R5309
SM
4.53K
8 =PPVCORE_S0_CPU_VSENSE 1 2 CPUVSENSE_IN 1 2 SMC_CPU_VSENSE OUT 41
PLACEMENT_NOTE=Place near U1000 center 1%

1/16W
MF-LF
402
1
C5309
0.22UF
20%
6.3V
2 X5R
402
D GND_SMC_AVSS 41 42 45 46 D
Place RC close to SMC
MCP Voltage Sense / Filter

XW5359 R5359
SM
4.53K
8 =PPVCORE_S0_MCP_VSENSE 1 2 MCPVSENSE_IN 1 2 SMC_MCP_VSENSE OUT 42
PLACEMENT_NOTE=Place near U1400 center 1%

1/16W
MF-LF
402
1
C5359
0.22UF
20%
6.3V
2
X5R
402
GND_SMC_AVSS 41 42 45 46
C C
PBUS VOLTAGE SENSE ENABLE & FILTER
Q5315
NTUD3127CXXG
SOT-963
N-CHANNEL
6 PBUSVSENS_EN_L
D
1
R5316
100K
64 =PBUSVSENS_EN 2 G 1%
IN
S 1/16W
MF-LF
Enables PBUS VSense 1
402
2
divider when high.
3 PPBUS_G3HRS5_VSENSE
D VOLTAGE=18.5V 1
R5385
27.4K
5 G 1%
S 1/16W
8 =PPBUS_G3HRS5 MF-LF
4
402
2
RTHEVENIN = 4573 OHMS
P-CHANNEL SMC_PBUS_VSENSE 41
B R53151
1
OUT
B
100K R5386
1%
5.49K
1
C5385
1/16W
MF-LF 1%
0.22UF
20%
402 1/16W
2 MF-LF 2
6.3V
X5R
402 402
PBUSVSENS_EN_L_DIV 2
PAGE TITLE
VOLTAGE SENSING
DRAWING NUMBER SIZE

REVISION
R
A.0.0
53 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP VCore Current Sense
8 =PP5VR3V3_S0_MCPCOREISNS
R5490 1 C5415
0.001 0.1uF
1% 20%
3
1W
MF
2 CERM
10V
V+
MCP VCore Current Sense Filter CPU VCORE LOAD SIDE CURRENT SENSOR / FILTER DC-IN (AMON) CURRENT SENSE
1206 402
IN =PPVCORE_S0_MCP_REG_R 1 2 =PPVCORE_S0_MCP
R5471 R5481
8
3 4
OUT 8 22 24 61
U5400 R5416 6.19K2 4.53K2
INA213
D 61 ISNS_PVCORES0MCP_N 5 IN- SC70 OUT 6 MCPCORE_IOUT 2
4.53K1 SMC_MCP_CORE_ISENSE
MAKE_BASE=TRUE
OUT 41
60 IN IMVP6_IMON 1
1%
SMC_CPU_ISENSE OUT 41 57 IN CHGR_AMON 1
1%
SMC_DCIN_ISENSEOUT 41
D
1% 1/16W 1/16W
1/16W MF-LF MF-LF
ISNS_PVCORES0MCP_P 4 IN+ REF 1 C5472 1
MF-LF
402
1
0.22UF
402
R5480 1 C5470
402
1 C5487
20%
17.4K 0.22UF 0.22UF
GND 6.3V 1% 20% 20%
2 X5R 1/16W 6.3V 6.3V
MF-LF 2 X5R 2 X5R
2
402
402 2 402 402

GND_SMC_AVSS 41 42 45 46 GND_SMC_AVSS 41 42 45 46
MCP MEM VDD Current Sense
8 =PP3V3_S0_MCPDDRISNS
CPU 1.05V CURRENT SENSE
1 C5416
R5491
0.002 0.1uF
1% 20% =PP3V3_S0_CPUVTTISNS
3
1/4W 10V
MCP MEM VDD Current Sense Filter 8
C
C =PP1V8_S0_FET_R 1
MF
1206
2 =PP1V8_S0
2 CERM
402 V+
R5492 1 C5417
8 IN OUT 8
U5401 0.01 0.1uF
3 4
INA210
R5417 0.5% 20%
3
4.53K1 1W 2 10V
CERM
ISNS_P1V5S0MCP_N 5 IN- SC70 OUT 6 MCPDDR_IOUT 2 SMC_MCP_DDR_ISENSE OUT 41 MF
0612 402 V+
MAKE_BASE=TRUE
1% =PPBUS_G3H_CPU_ISNS_R 2 1 =PPBUS_G3H_CPU_ISNS
ISNS_P1V5S0MCP_P 4 IN+ REF 1
1/16W
MF-LF 1 C5435
8 IN
4 3
OUT 8
U5402 R5418
402
0.22UF 5 IN-
INA213 6CPUVTT_IOUT
4.53K1
ISNS_CPUVTT_N SC70 OUT 2 SMC_CPU_FSB_ISENSE OUT 42
20%
GND 2
6.3V
X5R
1%
1/16W
2
402 ISNS_CPUVTT_P 4 IN+ REF 1 MF-LF 1 C5436

402
GND_SMC_AVSS 41 42 45 46 0.22UF
20%
GND 2
6.3V
X5R
2
402
CHARGER BMON CURRENT SENSE

8 =PP3V42_G3H_BMON_ISNS
B 1
ENG_BMON ENG_BMON 1
ENG_BMON
C5459
B
C5418 U5413 0.1UF
0.1uF NC7SB3157P6XG 20%
10V
3
20% 2 CERM
SC70
10V
2 CERM BMON_INAOUT 1 B1 SEL 6
SMC_BMON_MUX_SEL 42
V+ IN 402
402
1
U5403 2 GND
LOAD SIDE INA213 VCC 5
57 CHGR_CSO_R_P 5 IN- SC70 OUT 6
IN
0 R5401
ENG_BMON CHGR_BMON 3 4 BMON_AMUX_OUT 1
4.53K2 SMC_BATT_ISENSE
57 IN CHGR_CSO_R_N 4 IN+ REF 1 57 IN OUT 41
B0 A
1% ENG_BMON
PROD_BMON VER 1 1/16W
1 1 C5490
REGULATOR SIDE GND R5431 R5423 MF-LF
402
0.22UF
0 2 100K
2
1 20%
5% 6.3V
1/16W 2 X5R
5% MF-LF
1/16W 402
MF-LF 2 402
ENG_BMON
402 GND_SMC_AVSS 41 42 45 46
STUFF EITHER R5431 OR U5413 DEPENDING ON BMON CURRENT SENSING METHOD
PAGE TITLE
Current Sensing
DRAWING NUMBER SIZE

REVISION
R
A.0.0
54 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU T-Diode Thermal Sensor

INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE
R5515
47
8 =PP3V3_S0_CPUTHMSNS 1 2 PP3V3_S0_CPUTHMSNS_R
5% MIN_NECK_WIDTH=0.25 mm
D
1/16W
MF-LF
402
VOLTAGE=3.3V 1
1
C5515 R55161 1
R5517 D
VDD 0.1uF 10K 10K
20% 5% 5%
10V 1/16W 1/16W
10 BI CPU_THERMD_P U5515 2 CERM MF-LF MF-LF
402 402
SIGNAL_MODOL=EMPTY
EMC1403-1-AIZL 402 2 2
1 2 TSSOP
C5521 DP1 THERM* 7 CPUTHMSNS_THERM_L
DETECT CPU DIE TEMPERATURE 0.0022uF
10% 3 CPUTHMSNS_ALERT_L
50V DN1 ALERT* 8
CERM 2
402 4 9 =I2C_CPUTHMSNS_SDA
DP2/DN3 SMDATA BI 44
10 BI CPU_THERMD_N
5 CRITICAL 10
DN2/DP3 SMCLK =I2C_CPUTHMSNS_SCL BI 44
GND
6
7 CPUTHMSNS_D2_P
SIGNAL_MODOL=EMPTY
1
PLACEMENT NOTE: PLACE U5515 NEAR CPU
C5520
0.0022uF
10%
50V
CERM 2
DETECT HEAT-PIPE TEMPERATURE 402
7 CPUTHMSNS_D2_N
MCP T-Diode Thermal Sensor

J5520 INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE
78171-0004
C M-RT-SM
5 8 =PP3V3_S0_MCPTHMSNS R5535
47
C
NC 1 2 PP3V3_S0_MCPTHMSNS_R
5% MIN_NECK_WIDTH=0.25 mm
1 1/16W VOLTAGE=3.3V 1
2
MF-LF
402 1
C5535 R5536 1 1
R5537
3
VDD 0.1uF 10K 10K
5% 5%
20% 1/16W 1/16W
4 MCP_THMDIODE_P 10V
21 BI U5535 2 CERM MF-LF MF-LF
402
EMC1403-1-AIZL 402 2 2 402
SIGNAL_MODOL=EMPTY
1 2 TSSOP
6 C5522 DP1 THERM* 7 MCPTHMSNS_THERM_L
NC
DETECT MCP DIE TEMPERATURE 0.0022uF
10% 3 MCPTHMSNS_ALERT_L
50V DN1 ALERT* 8
518S0521 CERM 2
402 4 9 =I2C_MCPTHMSNS_SDA
DP2/DN3 SMDATA BI 44
21 BI MCP_THMDIODE_N
5 CRITICAL 10
DN2/DP3 SMCLK =I2C_MCPTHMSNS_SCL BI 44
GND
6
7 MCPTHMSNS_D2_P
SIGNAL_MODOL=EMPTY
1
C5540 PLACEMENT NOTE: PLACE U5535 NEAR MCP
0.0022uF
10%
50V
CERM 2
DETECT FIN-STACK TEMPERATURE 402
7 MCPTHMSNS_D2_N
B B
PAGE TITLE
Thermal Sensors
DRAWING NUMBER SIZE

REVISION
R
A.0.0
55 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
8 =PP5V_S0_FAN_RT
8 =PP3V3_S0_FAN_RT
CRITICAL
R5660 1 J5601
78171-0004
C 47K
5%
M-RT-SM
5
C
1/16W
MF-LF
NC
R5665 402 2
1
5V DC
41
SMC_FAN_0_TACH 1 47K 2 7 FAN_RT_TACH 2
TACH
5% 3
1/16W FAN_RT_PWM MOTOR CONTROL
MF-LF 7 4
402 GND
6
NC
R5661 1
100K 518S0521
5%
1/16W
1
MF-LF
402 2
G
S
D
41 SMC_FAN_0_CTL
3
2
Q5660
SSM3K15FV
SOD-VESM-HF
B B
PAGE TITLE
Fan
DRAWING NUMBER SIZE

REVISION
R
A.0.0
56 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
- SYNC WITH T18
- COPY THIS PAGE FROM T18 CSA.58
PLACEMENT NOTE
D PLACE L5800,L5801,L5803 NEAR J5800
D
PLACE C5800,C5810,C5803 NEAR J5800
PLACE D5800 NEAR J5800
GEYSER
8 IN =PP5V_S3_TPAD L5802
600-OHM-300MA VOLTAGE=5V
0402 MIN_LINE_WIDTH=0.6MM
1 2 7 PP5V_S3_TPAD_F
PLACEMENT_NOTE=NEAR J5800 1 C5860

L5804 0.1UF
20%
600-OHM-300MA
2
10V
0402 CERM
402
C 1 2 7 TPAD_GND_F C
VOLTAGE=0V
R5810
1K
42 41 OUT SMC_ONOFF_L 1 2 7 CONN_TPAD_ONOFF_FLTR_L
5%
1/16W
1 C5810 MF-LF
402
0.1UF
20%
10V
2 CERM
402
PLACEMENT_NOTE=NEAR J5800 CRITICAL

J5800
53307-1032
F-ST-SM PLACEMENT_NOTE=NEAR J5800
CRITICAL
1 2 L5803
(CONN_TPAD_USB_P) 3 4 600-OHM-300MA
=USB2_TPAD_N L5801 72 7 CONN_TPAD_USB_N (CONN_TPAD_USB_N) 5 6
NC 0402
BI 1 2
7 8
NC 7 SMC_LID_LC 1 2 SMC_LID
9
IN 41 42 56
9 10
BI
=USB2_TPAD_P 4 3 72 7 CONN_TPAD_USB_P NC NC
SYM_VER-2
DLP0NS 2 5 3 4 PLACEMENT_NOTE=NEAR J5800
9
90-OHM
C5803
NC
IO
NC
IO
6 VBUS 516S0588 1
0.01uF
10%
1 GND 16V
2 CERM
B 402 B
D5800
RCLAMP0502N
SLP1210N6
CRITICAL
PLACE D5800 CLOSE J5800
PAGE TITLE
GEYSER
DRAWING NUMBER SIZE

REVISION
R
A.0.0
58 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
42 41 8 =PP3V3_S5_SMC
R59321
10K SMSINT_L SHOULD BE PULL UP IF NOT USED.
5%
1/16W
MF-LF
402 2
42 SMS_INT_L
ANALOG SMS
8 =PP3V3_S3_SMS
1
C5920 1 C5926
R59201
14
0.1uF 10UF
10K 20%
10V 20%
5%
1/16W
VDD 2 CERM 2 6.3V
X5R
402
MF-LF
402 2
U5920 603
AP344ALH
C 1 FS
LGA
VOUTX 12 SMS_X_AXIS OUT 41
C
41 IN SMS_ONOFF_L SMS_PWRDN 5 PD
MAKE_BASE=TRUE VOUTY 10 SMS_Y_AXIS OUT 41
SMS_SELFTEST 2 ST
VOUTZ 8 SMS_Z_AXIS OUT 41
15 RES
4 RES
NC
1
CRITICAL
3 NC NC 11
R5921 NC NC
10K 6 NC NC 13
5% NC NC
9 NC 1 1 1
1/16W
NC NC 16 NC C5904 C5905 C5906
MF-LF GND
402 0.01UF 0.01UF 0.01UF
2 20% 20% 20%
7
16V 16V 16V
2 CERM 2 CERM 2 CERM
402 402 402
Desired orientation when Desired orientation when

placed on board top-side: placed on board bottom-side:
Package Top Top-through View
+Y +Y
Front of system
B +Z (up)
+X +X
+Z (down)
B
1 1
A A
PAGE TITLE
SMS
DRAWING NUMBER SIZE

REVISION
R
A.0.0
59 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
43 8 =PP3V3_S5_ROM
NO STUFF
R61901 R61001 1
R6101 1 C6100
10K 3.3K 3.3K 0.1UF
5% 5% 5% 20%
1/16W 1/16W 1/16W 2 10V
MF-LF MF-LF MF-LF CERM CRITICAL
8
402 2 402 2 402
2 402 VCC
OMIT
U6100
C PLACEMENT_NOTE=PLACE CLOSE TO U6100 R6150 32MBIT R6152 PLACEMENT_NOTE=PLACE CLOSE TO U6100
C
0 SOP 0
72 43 SPI_CLK_MUX 2 1 SPI_CLK 6 SCLK SI/SIO0 5 SPI_MOSI 2 1 SPI_MOSI_MUX 43 72
IN IN
5% MX25L3205DM2I-12G 5%
1/16W 1/16W
MF-LF MF-LF
43 SPI_MLB_CS_L 402 1 CE* 402
IN
3 WP*/ACC SO/SIO1 2
SPI_WP_L
SPI_HOLD_L 7 HOLD* R6105 PLACEMENT_NOTE=PLACE CLOSE TO U6100
72 SPI_MISO_R 2
33 1 SPI_MISO_MUX OUT 43 72
GND
NO STUFF 5%
4
1/16W
R61911 MF-LF
402
10K
5%
1/16W
MF-LF
402 2
B B
MCP79 SPI Frequency Select

Frequency SPI_MOSI SPI_CLK
31 MHz 0 0
42 MHz 0 1
25 MHz 1 0
1 MHz 1 1
25MHZ IS SECLECTED WITH R5164 AND R5144

ANY FO THE 4 FREQUENCIES CAN BE SELECTED
WITH R6190, R6191, R5164 AND R5144
PAGE TITLE
SPI ROM
DRAWING NUMBER SIZE

REVISION
R
A.0.0
61 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO CODEC
APPLE P/N 353S1538
L6202 MIN_LINE_WIDTH=0.40MM
FERR-220-OHM
D 1 2
VOLTAGE=4.5V
PP4V5_AUDIO_ANALOG 52
D
0402
L6201
VOLTAGE=3.3V
FERR-220-OHM MIN_NECK_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
55 54 52 8 =PP3V3_S0_AUDIO 1 2 52 CODEC_DVDD AVDD_ADC_DAC
0402 CRITICAL CRITICAL CRITICAL
C6200 1 1 C6201 1 C6203 C6204 1 1 C6206 C6205 1 1 C6207
1UF 0.001UF 0.001UF 150UF 0.001UF 150UF 0.001UF
10% 10% 10% 20% 10% 20% 20%
6.3V 50V 50V 6.3V 2 2 50V 6.3V 2 50V
CERM 2 2 CERM 2 CERM
POLY-TANT CERM POLY-TANT
2 CERM
402 402 402 CASE-B2-SM 402 CASE-B2-SM 402
=GND_AUDIO_CODEC
25
38
9 52 53 54 55
1
9
DVDD
DVDD_IO
AVDD1
AVDD2
72 21 IN HDA_BIT_CLK R6206
72 21 IN HDA_SYNC 39
6 BCLK SPDIFO 48 AUD_SPDIF_O 1 2 AUD_SPDIF_OUT 54
CODEC_DVDD 72 21 IN HDA_SDOUT
52 NO STUFF 10 SYNC SPDIFI/EAPD/MIDI-I/DMIC-R 47 5%
1
R6270 R6204 5 SDATA_OUT CRITICAL
1/16W
MF-LF AUD_SPDIF_I 54
39 402
5%
100K 72 21 OUT HDA_SDIN0 1 2 CODEC_SDATA_IN 8 SDATA_IN U6200 SENSE_A 13 AUD_SENSE_A 55
1/16W 5%
1/16W
ALC885Q-VB3-GR SENSE_B 34 AUD_SENSE_B 55
MF-LF QFN
MF-LF
2 402 402 REV B3
53 AUD_GPIO_0 2 GPIO0/DMIC-CLK PORT-A-L 39 AUD_BI_PORT_A_L 55
AUD_GPIO_1 3 GPIO1/DMIC-L PORT-A-R 41 AUD_BI_PORT_A_R 55
1
R6271 PORT-F-L 16 NO_TEST NC_AUD_BI_PORT_F_L
55 AUD_BI_PORT_C_L 23 PORT-C-L
10K PORT-F-R 17 NO_TEST NC_AUD_BI_PORT_F_R
5% 55 AUD_BI_PORT_C_R 24 PORT-C-R
1/16W PORT-F-VREFO 30 NO_TEST NC_AUD_VREF_PORT_F
MF-LF AUD_VREF_PORT_A
AUD_BI_PORT_D_L 35 33
C 2 402 53
53 AUD_BI_PORT_D_R 36
PORT-D-L
PORT-D-R
PORT-A-VREFO/DCVOL
PORT-E-L 14 NO_TEST NC_AUD_BI_PORT_E_L
55
C
PORT-E-R 15 NO_TEST NC_AUD_BI_PORT_E_R
NC_BAL_IN_L NO_TEST18 CD-L PORT-E-VREFO 31 NO_TEST NC_AUD_VREF_PORT_E
NC_BAL_IN_COM NO_TEST19 CD-GND PORT-B-VREFO 28 AUD_VREF_PORT_B 55
NC_BAL_IN_R NO_TEST20 CD-R PORT-B-L 21 AUD_BI_PORT_B_L 55
PORT-B-R 22 AUD_BI_PORT_B_R 55
PORT-C-VREFO 29 NO_TEST NC_AUD_VREF_PORT_C

BEEP 12 BEEP PORT-B-VREFO2 32 NO_TEST NC_AUD_VREF_PORT_D
PORT-G-L 43 NO_TEST NC_AUD_BI_PORT_G_L
72 21 IN HDA_RST_L 11 RESET* PORT-G-R 44 AUD_BI_PORT_G_R 53
PORT-H-L 45 NO_TEST NC_AUD_BI_PORT_H_L

1 CRITICAL PORT-H-R 46 NO_TEST NC_AUD_BI_PORT_H_R
R6203 C6208
THRM_PAD
1
100K 0.1UF VREF 27 AUD_CODEC_VREF 1
5% R6209
AVSS1
AVSS2
10% JDREF 40 AUD_CODEC_JDREF
DVSS
1/16W 16V
MF-LF 2 X5R 100K
2 402 402 NC 37 NC_VRP 1 5%
NO_TEST R6205 1/16W
MF-LF
20.0K
49
4
7
26
42
1% 1 C6212 2 402
1/16W 0.001UF
MF-LF 10%
NO STUFF 2 402 CRITICAL 2 50V
1 CERM
1
R6201 C6210 402
3.3UF
0 10%
5% 16V 2
1/16W TANT
MF-LF SMA-HF1
2 402
B 55 54 53 52 9 =GND_AUDIO_CODEC
B
VOLTAGE=0V
AUDIO 4.5V REGULATOR

APPLE P/N 353S1576
MIN_NECK_WIDTH=0.20 MM L6200
FERR-220-OHM
U6201
VOLTAGE=5V LREG_TPS79501DRB
SON
55 8 =PP5V_S0_AUDIO 1 2 AUD_4V5_REG_IN 1 IN1 OUT1 3 PP4V5_AUDIO_ANALOG 52
0402 2 IN2 OUT2 4

8 EN NR/FB 5 4V5_REG_FB
R6202 1
R6210 1 C6224
1K GND THRM_PAD NC 80.6K 15PF
55 54 52 8 =PP3V3_S0_AUDIO 1 2 AUD_REG_SHDN_L 1% 5%
50V
1/16W 2 CERM
6
7
5% MF-LF
1/16W 402
MF-LF 2 402
402
CRITICAL
C6221 1 1 C6223 1 PLACE R6210, R6211, AND C6224 CLOSE TO U6201
1 C6220 10UF 0.001UF VOUT=1.2246V*[1+(R6210/R6211)]=4.58V R6211
0.1UF
20%
6.3V 2
10% 29.4K
10% X5R 2 50V
CERM 1%
1/16W
2 16V
603 402
X5R MF-LF
A 402 2 402
SYNC_MASTER=K36A_MLB SYNC_DATE=08/29/2008 A
PAGE TITLE
=GND_AUDIO_CODEC
55 54 53 52 9
AUDIO: CODEC
NO STUFF DRAWING NUMBER SIZE
R6200 051-8089 D
1
0 2
Apple Inc. REVISION
5%
1/16W
R
A.0.0
MF-LF
402
62 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SATELLITE & SUB TWEETER AMPLIFIER APN:353S1595
SATELLITE 169 HZ < FC < 282 HZ

SUB 80 HZ < FC < 132 HZ
D GAIN 12DB D
MIN_LINE_WIDTH=0.30 mm MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM R6660 MIN_NECK_WIDTH=0.20 MM
SPKRAMP_R_P_OUT 2
0 1 SPKRCONN_R_P_OUT
53 OUT 7 54
VOLTAGE=5V 5%
1/16W
MIN_LINE_WIDTH=0.60 MM MF-LF
402
53 8 =PP5V_S0_AUDIO_AMP
MIN_NECK_WIDTH=0.20 MM R6661 MIN_NECK_WIDTH=0.20 MM
0
53 SPKRAMP_R_N_OUT 2 1 SPKRCONN_R_N_OUT OUT 7 54
5%
PP5V_S0_AUDIO_F 53 1/16W
VOLTAGE=5V MF-LF
402
R6600 MIN_LINE_WIDTH=0.30 MM
1
0 2
5%
RIGHT SATELLITE
1/16W CRITICAL
MF-LF C6607 1 C6602 1 1
402
1uF
1UF
C6601
10%
6.3V
1 10
10%
47UF
CERM 2 VDD PVDD 6.3V
20%
CRITICAL 402 CERM 2 2 6.3V
POLY
L6610 C6610 U6610 402 CASE-B3-SM1
FERR-1000-OHM 0.047UF AUD_SPKRAMP_INR MAX9705
TDFN1
AUD_BI_PORT_D_R 1 2 AUD_SPKRAMP_INR_L 1 2 SPKRAMP_R_P_OUT
52 IN 2 IN+ OUT+ 8 53
0402
10% MAX9705_R_N 3 IN- OUT- 9 SPKRAMP_R_N_OUT 53
16V CRITICAL SYNC 6
X7R 5 SHDN* MIN_LINE_WIDTH=0.30 mm MIN_LINE_WIDTH=0.30 mm
402
C 53 AUD_SPKRAMP_SHUTDOWN_L CRITICAL GND PGND PAD
THRML MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_P_OUT
R6670
2
0 1
SPKRCONN_L_P_OUT
C
C6611 1
4 7 11
53
5%
OUT 7 54
0.047UF 1/16W
10% MF-LF
16V 402
X7R 2
402
55 54 53 52 9 =GND_AUDIO_CODEC
SPKRAMP_THERMPLANE 53 MIN_LINE_WIDTH=0.30 mm MIN_LINE_WIDTH=0.30 mm
53 9 =GND_AUDIO_AMP MIN_NECK_WIDTH=0.20 MM R6671 MIN_NECK_WIDTH=0.20 MM
SPKRAMP_L_N_OUT 2
0 1 SPKRCONN_L_N_OUT
53 OUT 7 54
5%
53 PP5V_S0_AUDIO_F 1/16W
CRITICAL MF-LF
402
C6604 1 1
C6603
1UF 47UF
C6608 1 1 10 10%
6.3V 20%
2 6.3V LEFT SATELLITE
CRITICAL 1uF VDD PVDD CERM 2 POLY
10% 402 CASE-B3-SM1
L6620 C6620 6.3V
CERM 2
U6620
FERR-1000-OHM 0.047UF 402 MAX9705
TDFN1
AUD_BI_PORT_D_L 1 2 AUD_SPKRAMP_INL_L 1 2 AUD_SPKRAMP_INL 2 IN+ 8 SPKRAMP_L_P_OUT
52 IN OUT+ 53
0402
10%
MAX9705_L_N 3 IN- OUT- 9 SPKRAMP_L_N_OUT 53
16V 6
X7R CRITICAL SYNC
402 5 SHDN*
53 AUD_SPKRAMP_SHUTDOWN_L THRML
CRITICAL GND PGND PAD
C6621 1 4 7 11
0.047UF
10% MIN_LINE_WIDTH=0.30 mm MIN_LINE_WIDTH=0.30 mm
16V
X7R 2
402 MIN_NECK_WIDTH=0.20 MM R6680 MIN_NECK_WIDTH=0.20 MM
=GND_AUDIO_CODEC SPKRAMP_THERMPLANE SPKRAMP_SUB_P_OUT 2
0 1 SPKRCONN_SUB_P_OUT
55 54 53 52 9 53 53 7 54
B 53 9 =GND_AUDIO_AMP
5%
1/16W
OUT
B
MF-LF
402
53 PP5V_S0_AUDIO_F CRITICAL MIN_NECK_WIDTH=0.20 MM R6681 MIN_NECK_WIDTH=0.20 MM
0
C6606 1 1
C6605 53 SPKRAMP_SUB_N_OUT 2 1 SPKRCONN_SUB_N_OUT OUT 7 54
1UF 120UF 5%
C6609 1 1 10 10%
6.3V
20%
2 6.3V
1/16W
MF-LF
CRITICAL 1uF VDD PVDD CERM 2 POLY-TANT 402
10% 402 CASE-B2-SM
L6630 C6630 6.3V
CERM 2
U6630
FERR-1000-OHM 0.1UF 402 MAX9705
52 IN
AUD_BI_PORT_G_R 1 2 AUD_SPKRAMP_INSUB_L 1 2 AUD_SPKRAMP_INSUB 2 IN+
TDFN1
OUT+ 8 SPKRAMP_SUB_P_OUT 53 SUB-TWEETER
0402
10%
MAX9705_SUB_N 3 IN- OUT- 9 SPKRAMP_SUB_N_OUT 53
L6611 16V
X5R CRITICAL SYNC
5 SHDN*
6
FERR-1000-OHM 402
52 AUD_GPIO_0 1 2 THRML
IN GND PGND PAD
0402
4 7 11
R66101 AUD_SPKRAMP_SHUTDOWN_L 53 CRITICAL
10K
5%
C6631 1
1/16W 0.1UF
MF-LF 10%
16V
402 2 X5R 2
402
55 54 53 52 9 =GND_AUDIO_CODEC SPKRAMP_THERMPLANE 53
53 9 =GND_AUDIO_AMP
A SYNC_MASTER=K36A_MLB SYNC_DATE=08/29/2008 A
PAGE TITLE
XW6600
SM
AUDI0: SPEAKER AMP
DRAWING NUMBER SIZE
53 9 =GND_AUDIO_AMP 1 2 SPKRAMP_THERMPLANE 53

REVISION
R
A.0.0
66 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MIC CONNECTOR
AUDIO JACK 1: LO/HP CONNECTOR, SPDIF TX APN:518S0392 CRITICAL
J6701
48227-0301
L6790 M-RT-SM1
4
FERR-220-OHM
D 55 52 8 =PP3V3_S0_AUDIO 1
0402
2
AUD_SPDIF_OUT
IN 52
54 7 MIC_LO_CONN 1
D
L6700 L6701 54 7 MIC_HI_CONN 2
FERR-120-OHM-1.5A FERR-120-OHM-1.5A 55 54 7 MIC_SHLD_CONN 3
AUD_CONNJ1_SLEEVE 1 2 AUD_CONNJ1_SLEEVE_F 1 2
54 PP3V3_S0_AUDIO_SPDIF 0402-LF 0402-LF 5
L6702 CRITICAL
OMIT
CRITICAL AUD_CONNJ1_TIPDET
FERR-1000-OHM
1 2
AUD_CONNJ1_TIPDET_F SPEAKER CONNECTOR J6702
78171-0002
J6700 0402
APN:518S0519
M-RT-SM
3
AUDIO-OUT-K36-MG3 L6703 L6704
F-RT-TH-HF
2
DETECT FOR PLUG TYPE FERR-1000-OHM FERR-1000-OHM 53 7 SPKRCONN_L_P_OUT 1
AUD_CONNJ1_RING_F IN
SWITCH 3 1 2 1 2 AUD_PORTA_R 55 53 7 SPKRCONN_L_N_OUT 2
BI IN
LEFT 4 0402 0402
4
RIGHT 5 AUD_CONNJ1_RING L6705 L6706
1 FERR-1000-OHM FERR-1000-OHM CRITICAL
GROUND
1 2 1 2
J6703
VCC
7 AUD_CONNJ1_TIP AUD_CONNJ1_TIP_F AUD_PORTA_L BI 55 78171-0004
6 0402 0402 M-RT-SM
GND 5
VIN 8
9
L6707
SHLD_PIN
10
FERR-1000-OHM R6700 53 7 IN SPKRCONN_SUB_P_OUT 1
SHLD_PIN AUD_CONNJ1_SLEEVEDET 1 2 AUD_CONNJ1_SLEEVEDET_F 1
10K 2 AUD_J1_SLEEVEDET_R SPKRCONN_SUB_N_OUT 2
OUT 55 53 7 IN
0402 5% SPKRCONN_R_P_OUT 3
APN:514-0604 NO STUFF
2
CRITICAL 1/16W
MF-LF
53 7
53 7
IN
SPKRCONN_R_N_OUT 4
HF APN:514-0521 DZ6700 DZ6704 402 IN

1 C6700 5.6V-15A CRITICAL 2
6.8V-100PF
402 R6701 APN:518S0521 6
1UF 4.7
C 10%
6.3V
2 CERM
0405 1 3
DZ6702
6.8V-100PF 1 2
1
5%
2 AUD_J1_TIPDET_R OUT 55 C
402 CRITICAL CRITICAL
402 2 1/16W
54 GND_AUDIO_SPDIF_DGND 1 3 DZ6703 DZ6705 MF-LF
402 XW6705
R6791 2 4
NO STUFF 1
6.8V-100PF 6.8V-100PF SM
0 DZ6701 402 402
1 2
5.6V-15A 1 1 C6705 9 =GND_CHASSIS_AUDIO_JACK 1 2 CHASSIS_AUDIO_JACK_ISOL 54
5% 0405 1 100PF
1/16W 2 4 5%
MF-LF 50V
2 CERM
402 402
54 CHASSIS_AUDIO_JACK_ISOL XW6700
SM
AUD_J1_COM 1 2
XW6701
SM
AUD_J2_COM 1 2 =GND_AUDIO_CODEC 9 52 53 55
AUD_J2_OPT_OUT
R6749
10 AUD_SPDIF_I
MIC EMI FILTER
1 2 OUT 52
5%
54 PP3V3_S0_AUDIO_SPDIF 1/16W
MF-LF
L6750 L6751 L6770
402 FERR-120-OHM-1.5A FERR-120-OHM-1.5A FERR-1000-OHM
55
AUD_CONNJ2_SLEEVE 1 2 AUD_CONNJ2_SLEEVE_F 1 2 MIC_LO 1 2 MIC_LO_CONN
OUT 7 54
OMIT 0402-LF 0402-LF 0402
CRITICAL L6752
J6750 FERR-1000-OHM
B AUDIO-IN-MG3-K36
F-RT-TH-HF
1 2 AUD_CONNJ2_TIPDET_F B
0402
DETECT FOR PLUG TYPE 2 L6772
LEFT 4 AUD_CONNJ2_TIP L6753 L6754 FERR-1000-OHM
MIC_HI_CONN
FERR-1000-OHM FERR-1000-OHM MIC_HI 1 2
SWITCH
3 AUD_CONNJ2_TIPDET 1 2
AUD_CONNJ2_RING_F 1 2
55 OUT 7 54
AUD_PORTC_R BI 55 0402
RIGHT 5 AUD_CONNJ2_RING 0402 0402
1 CRITICAL
GROUND
L6755 L6756 2
VCC
8
FERR-1000-OHM FERR-1000-OHM DZ6770
GND
7 6.8V-100PF
1 2 AUD_CONNJ2_TIP_F 1 2 AUD_PORTC_L 55 402
6 BI
VOUT
0402 0402 CRITICAL
SHLD_PIN 9 1 2
SHLD_PIN
10 L6757 DZ6771 MIC_SHLD_CONN 7 54 55
6.8V-100PF
FERR-1000-OHM R6750 402 1
R6740
10K
APN:514-0603 AUD_CONNJ2_SLEEVEDET 1 2 AUD_CONNJ2_SLEEVEDET_F 1 2
1 5%
0
0402 5%
HF APN:514-0519 1/16W
MF-LF
1/16W
MF-LF
1 3 402 2 402
NO STUFF
1 C6750 1 C6751 2 CRITICAL 2
R6751
1UF 10uF DZ6751 DZ6753 CRITICAL
4.7
10%
6.3V
2 CERM
20%
6.3V
2 X5R
5.6V-15A
0405 6.8V-100PF DZ6755 1 2 AUD_J2_TIPDET_R OUT 55
54 CHASSIS_AUDIO_JACK_ISOL
402 603 2 4 402 6.8V-100PF 5%
CRITICAL 2 2 402 1/16W
54 GND_AUDIO_SPDIF_DGND NO STUFF 1 3 1 CRITICAL 1 MF-LF
DZ6750
DZ6752 DZ6754
402
6.8V-100PF
5.6V-15A
0405
402 6.8V-100PF
402
1 C6756
1 1 100PF
2 4 5%
50V
2 CERM
A 54 CHASSIS_AUDIO_JACK_ISOL
402
SYNC_MASTER=K36A_MLB SYNC_DATE=08/29/2008 A
PAGE TITLE
AUDIO: JACK
DRAWING NUMBER SIZE
AUDIO JACK 2: LINE IN CONNECTOR, SPDIF RX Apple Inc. 051-8089 D
REVISION
R
A.0.0
67 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CODEC OUTPUT SIGNAL PATHS

FUNCTION VOLUME CONVERTER PIN COMPLEX MUTE CONTROL DET ASSIGNMENT
HP OUT 0X0F (15) 0X05 (5) 0X15 (21,PORTA) VREF_A(100%) 0X15 (21,PORTA)
SAT SPKR 0X26 (38) 0X25 (37) 0X14 (20,PORTD) GPIO 0 N/A
D SUB SPKR
SPDIF OUT
0X0E (14)
N/A
0X04 (4)
0X06 (6)
0X16 (22,PORTG)
0X1E (30,SPDIF OUT)
GPIO 0
N/A
N/A
0X1B (27,PORTE)
D
CODEC INPUT SIGNAL PATHS

FUNCTION MIXER VOLUME MUTE CONTROL CONVERTER PIN COMPLEX VREF DET ASSIGNMENT
LINE IN 0X23 (35) 0X08 (8) 0X08 (8) 0X08 (8) 0X1A (26,PORTC) N/A 0X1A (26,PORTC)
MIC IN 0X24 (36) 0X07 (7) 0X07 (7) 0X07 (7) 0X18 (24,PORTB) VREF_B (80%) N/A HP/LO DE-POP SWITCH
SPDIF IN N/A N/A N/A 0X0A (10) 0X1F (31,SPDIF IN) N/A N/A APN:353S1459 PORT A HP/LO
52 8 =PP5V_S0_AUDIO
CRITICAL
C6830
100UF
1 2 AUD_PORTA_L 54
OUT
1
1 C6836 MAX9890BETA+ 20%
6.3V
1UF VCC 1
POLY-TANT R6834
52 IN AUD_BI_PORT_A_R 10%
2 6.3V U6801 CASE-B2-SM
27.4K
PORT A DETECT PORT E DETECT(SPDIF DELEGATE) CERM
402 TDFN CRITICAL 1%
OUT AUD_SENSE_B
7 4 MAX9890_OUTL C6831 1/16W
MF-LF
52 INRCRITICALOUTL 100UF 402
2
3 6 1 2
55 52 OUT AUD_SENSE_A 52 IN AUD_BI_PORT_A_L INL OUTR MAX9890_OUTR AUD_PORTA_R OUT 54
2 20%
55 PP3V3_S0_AUDIO_F SHDN* AUD_VREF_PORT_A IN 52 6.3V
AUD_OUTJACK_INSERT_L 1 1
R6806 R6805 POLY-TANT
CASE-B2-SM
8 MAX9890_CEXT
C 1
R6801
1%
39.2K
1/16W
1%
39.2K
1/16W
CEXT
THM 1
R6839
R6835
27.4K
1
C
MF-LF MF-LF GND PAD
5%
270K Q6800 D 3
2 402 2 402
1 C6835 10K
5%
1%
1/16W
1/16W SSM6N15FEAPE AUD_PORTA_DET_L NC AUD_PORTE_DET_L NC 5 9 0.1UF 1/16W MF-LF
MF-LF SOT563 10% MF-LF 402
16V 2
2 402 2 X5R 2 402
Q6801 D 6
Q6801 D 3 402
R6802 5 G S SSM6N15FEAPE SSM6N15FEAPE 55 54 53 52 9 =GND_AUDIO_CODEC

4 SOT563 SOT563
47K
54 IN AUD_J1_TIPDET_R 1 2 AUD_J1_DET_RC
5%
1/16W 1
2 G S 5 G S
MF-LF
402
C6801 1 4
0.1UF
2 10% 16V
X5R 402
=GND_AUDIO_CODEC
PLACE L6800/C6800 CLOSE TO Q6800
55 54 53 52 9
L6800
R6803 FERR-1000-OHM
PP3V3_S0_AUDIO_F 1
100K 2 AUD_J1_SLEEVEDET_INV =PP3V3_S0_AUDIO 1 2 PP3V3_S0_AUDIO_F
55 54 52 8 55
5% 0402
1 1/16W
R6861 MF-LF
1
270K 402 C6800
5%
1/16W
Q6800 D 6
55 54 AUD_J1_SLEEVEDET_R
0.1UF
MF-LF SSM6N15FEAPE 10%
16V
SOT563
2 402 2 X5R
AUD_J1_SLEEVEDET_R =GND_AUDIO_CODEC 402
55 54 IN 55 54 53 52 9
2 G S 1
MIC INPUT CIRCUITRY PORT C LI

CRITICAL
1 C6802 R6850 R6855 C6832
B 0.01UF
10% 1
6.81K
2 VREF_PORT_B_R 1
2.2K
2 AUD_VREF_PORT_B 52
2
3.3UF
1 AUD_BI_PORT_C_L
B
2 16V
CERM 54 IN AUD_PORTC_L OUT 52
1/16W 1% 1/16W 5%
402 MF-LF 402 MF-LF 402
1 10%
55 54 53 52 9 =GND_AUDIO_CODEC CRITICAL R6836 16V
1 TANT
C6853 27.4K SMA-HF1
1%
4.7UF 1/16W
20% MF-LF
6.3V
2 X5R-CERM 402 2
402 =GND_AUDIO_CODEC 9 52 53 54 55
1
=GND_AUDIO_CODEC 9 52 53 54 55
R6837
27.4K
Line-in (PORT C) DETECT 1% CRITICAL
C6850 1/16W
MF-LF C6833
0.1uF 402 2
55 52 AUD_SENSE_A
MIC_HI 1 2 AUD_BI_PORT_B_L
3.3UF
54 IN 52
MAKE_BASE=TRUE 54 AUD_PORTC_R 2 1 AUD_BI_PORT_C_R 52
IN OUT
R68131 CRITICAL
10% 16V
X5R 402
10%
55 PP3V3_S0_AUDIO_F 10K 1
R6852 CRITICAL AUD_BI_PORT_B_R 52 16V
5% C6851 1 CRITICAL TANT
1/16W 680PF 100K 1 SMA-HF1
MF-LF 10%
5% C6852 NO STUFF
1 402 2 1/16W
100PF
R6811
50V
CERM 2 MF-LF
5%
PLACE C6852 NEAR U6200
5%
270K AUD_INJACK_INSERT_L NC 402 2 402 XW6800
SM
50V
CERM 2
402
1/16W
MIC_LO =GND_AUDIO_CODEC
MF-LF
2 402
Q6802 54 IN 1 2 9 52 53 54 55
SSM3K15FV D 3 NO STUFF
SOD-VESM-HF R6853
R6812 MIC_SHLD_CONN 0
54 7 1 2
47K IN
54 IN AUD_J2_TIPDET_R 1 2 AUD_J2_DET_RC 5%
1/16W
5% MF-LF
1
A 1/16W
MF-LF
402
C6811
0.1UF
1 G S 2
402
NO STUFF SYNC_MASTER=K36A_MLB SYNC_DATE=08/29/2008 A

2
10% 16V R6854 PAGE TITLE
X5R 402
55 54 53 52 9 =GND_AUDIO_CODEC
1
0
2 =GND_CHASSIS_AUDIO_MIC 9 AUDIO: JACK TRANSLATORS
5% DRAWING NUMBER SIZE
1/16W
MF-LF
402 Apple Inc. 051-8089 D
REVISION
NO STUFF
R
A.0.0
R6856 NOTICE OF PROPRIETARY PROPERTY: BRANCH
0
1 2 THE INFORMATION CONTAINED HEREIN IS THE
5% THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1/16W
MF-LF
402
68 OF 109
IV ALL RIGHTS RESERVED <CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
- COPY THIS PAGE FROM T18 CSA.69 CRITICAL
- DO WE NEED TO CHANGE BATTERY CONNECTOR? J6900 CRITICAL
78048-0573 F6905
M-RT-SM Q6910 restricts system load to 10K-70K window until
6AMP-24V
1 2 adapter detects system and enables 16.5V output. =PP18V5_DCIN_CONN 8 56
1 7 PP18V5_DCIN_FUSE
MIN_LINE_WIDTH=1mm
2 MIN_NECK_WIDTH=0.20mm
3
VOLTAGE=18.5V 1206 CRITICAL
4
1 C6905 Q6910
0 0.01UF NTUD3127CXXG
5 7 ADAPTER_SENSE 1 2
2
20%
50V
CERM
1-Wire OverVoltage Protection SOT-963
5%
603 Vgs(max) = 8V
1/16W
PP18V5_DCIN_ONEWIRE
S
MF-LF
4
402 MIN_LINE_WIDTH=0.25mm
518S0656 R6928 MIN_NECK_WIDTH=0.20mm
D
P-CHN
VOLTAGE=18.5V
D R6917 1 R6911 1
G
1
C6915
0.1UF 270K 180K
5% 5%
<Ra> 10%
5
If ADAPTER_SENSE > Vth 1/16W 1/16W
MagSafe DC Power Jack ADAPTER_SENSE_R
R6913 1
25V
X5R
402
2
then turn off FET
MF-LF
402
2
MF-LF
402
2
100K
5% ONEWIRE_EN ONEWIRE_PWR_EN_L_DIV
1
1/16W
MF-LF
R6915 Vgs = 7.30V @ 20V DCIN
402 2 CRITICAL 270K
U6915
5%
1/16W
R69181 Vgs = 4.74V @ 13V DCIN R6912 1
5
MF-LF
D 3
270K 470K
ONEWIRE_DCIN_DIV 1
LM397 402 2 CRITICAL 5% 5%
<Vth> V+ SOT23-5-HF Q6915 1/16W
MF-LF
1/16W
MF-LF
<Rb> 4 ONEWIRE_OVERVOLT SSM3K15FV 402
2
402
2
1 SOD-VESM-HF
R6914 ONEWIRE_ESD 3
V- ONEWIRE_PWR_EN_L
100K 1
R6916 1 G S 2
5% 2 1 C6917
1/16W 270K 0.001UF CRITICAL
MF-LF 5% 6 N-CHN
402 2 1/16W 10%
50V
Q6910
MF-LF 2 CERM
402 2 D NTUD3127CXXG
402
SOT-963
R6910
G 1K
2 SMC_BC_ACOK_RC 1 2 SMC_BC_ACOK IN 41 42 57
Vth = Vdcin * (Rb / (Ra + Rb)) VOLTAGE DIVIDER FROM DCIN ENSURES Q6910 S
5%
Vth = Vdcin / 2 Vgs is met when SYS_ONEWIRE is high or low. 1/16W
C6910 1 MF-LF
Q6920 used as bilateral switch to ensure 1 0.001UF
402
SYS_ONEWIRE doesn’t drive unpowered U6990 10%

1 50V
R6920 CRITICAL CRITICAL CERM 2
402
24.3K
1%
1/16W
Q6920 Q6920
MF-LF SSM6N15FEAPE SSM6N15FEAPE
2
2 402
G
SOT563 SOT563
C C
D
SYS_ONEWIRE_BILAT SYS_ONEWIRE BI 41 42
6
4
1
R6905 D6905
47 HN2D01JEAPE
56 8 =PP18V5_DCIN_CONN 1
5%
1/8W
2 PPDCIN_S5_P3V42G3H
1
SOT665
5
3.425V "G3Hot" Supply
VOLTAGE=18.5V
MF-LF Supply needs to guarantee 3.31V delivered to SMC VRef generator
805
3 4
57 56 BATT_POS_F PPVIN_G3H_P3V42G3H P3V42G3H_BOOST

MIN_LINE_WIDTH=0.6 MM 2 MIN_LINE_WIDTH=0.4 mm
NC NC MIN_NECK_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V
VOLTAGE=12.6V
C6990 1 3 6 C6994 1
10uF VIN BOOST 0.22uF

10% 20%
CRITICAL
25V
X5R 2
U6990 6.3V
X5R 2 L6995
1206-1 LT3470ETS8 402 33UH =PP3V42_G3H_REG
TSOT23-8 8
1 5 P3V42G3H_SW 1 2
SHDN* SW
CDPH4D19FHF-SM
Vout = 3.425V
BIAS 7 MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE 200mA max output
NC 2 NC CRITICAL (Switcher limit)
FB 8 <Ra>
LID HALL EFFECT SENSOR
GND 1
C6995 R6995 1
4 22pF 348K
1%
MLB TOP VIEW 5% 1/16W
50V
2 CERM MF-LF
402 402 2 1
C6999
PIN 1 22UF
P3V42G3H_FB 20%
6.3V
<Rb> 2
B R6996 1
CERM
805 B
200K
1%
1/16W
MF-LF
BATTERY/LID CONNECTOR 402 2
L6901 Vout = 1.25V * (1 + Ra / Rb)

FERR-50-OHM
SM-LF
7 PPVBAT_G3H_CONN_F 1 2 BATT_POS_F 56 57
L6902
L6909 120-OHM-0.3A-EMI
2 1 0402-LF
600-OHM-300MA
0402 4 3
7 SMBUS_BATT_SCL_F 1 2 =SMBUS_BATT_SCL 44
6 5
8 =PP3V42_G3H_LIDSWITCH 1 2 7 PP3V42_G3H_LIDSWITCH_F
NC 8 7 NC
10
VOID
9 SMBUS_BATT_SDA_F
L6903
7
120-OHM-0.3A-EMI
12 11 0402-LF
L6907 14 13
1 2 =SMBUS_BATT_SDA
600-OHM-300MA 16 15 44
0402
18 17 7 SMC_BS_ALRT_L_F
1 2 GND_SMC_LID_F 20 19
L6904
7
120-OHM-0.3A-EMI
0402-LF
CRITICAL
CRITICAL D6950 1 2 SMC_BS_ALRT_L
A L6908 J6950 RCLAMP2402B
41 42
A
1
600-OHM-300MA SC-75 SYNC_MASTER=RAYMOND SYNC_DATE=08/17/2008

0402 8199-3520-M281 1 C6942 1 C6943 1 C6944 1 C6945 PAGE TITLE
F-ST-SM
49 42 41 SMC_LID 1 2 7 SMC_LID_F
0.001UF
10%
0.001UF
10%
47pF
5%
47pF
5% DC-In & Battery Connectors
2 50V
CERM 2 50V
CERM
50V
2 CERM 50V
2 CERM DRAWING NUMBER SIZE
3
APN:516S0620
402 402 402 402
REVISION
1 C6920 1 C6921 HFAPN:516S0735 56 9 =GND_BATT_CHGND
R
A.0.0
0.01uF 0.01uF NOTICE OF PROPRIETARY PROPERTY: BRANCH
10% 10%
2 16V
CERM 2 16V
CERM THE INFORMATION CONTAINED HEREIN IS THE
402 402 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
=GND_BATT_CHGND 9 56
69 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PBUS SUPPLY / BATTERY CHARGER Q7001

HAT1127H
LFPAK-SM
Q7000 CRITICAL
HAT1127H
LFPAK-SM
CRITICAL
3
=PP18V5_G3H_CHGR PPVDCIN_G3H_PRE
3
8 PPVDCIN_G3H_PRE2
S
5
2
S
D
2
1
1
D 2 D
G
D7010
G
1SS418 C7063 1 R7098 1
4
=PP3V42_G3H_CHGR R7099
4
SOD-723-HF
1 0.1UF 100K
5%
57 8
CHGR_LOWCURRENT_GATE_MOS 100K
10% 1 2
25V
X5R 2
1/16W
MF-LF 1 C7060 5%
402 402 2 1 0.1UF
R7060 10%
25V
R7062 1/16W
MF-LF
R7001
62K
57.6K
1% 2 X5R
402
62K
5%
1 402
1 MIN_LINE_WIDTH=0.2 MM 1/16W 1/16W

R7010 CHGR_SGATE 1 2 MIN_NECK_WIDTH=0.2 MM MF-LF
402 2 5
MF-LF
402
CHGR_DCIN 30.1K
1% 5% 57 46 CHGR_AMON 1 2
57 1/16W 1/16W VCC
MF-LF MF-LF 4
402 402 CHGR_LOWCURRENT_GATE
2
R7061 1 3 GND
CRITICAL
(CHGR_ACIN)
1.82K
1%
CHGR_LOWCURRENT_REF 2 U7060
1/16W
MF-LF
TL331
402 SOT23-5
2
57 1 2 CHGR_VDD 1 2 CHGR_VDDP
C7010 1
R7040 XW7020
0.1UF 4.7 1 C7040 R70235% 10 SM
10% 1 C7041 5% 1UF 1/16W
25V 2
X5R R7011 57 8 =PP3V42_G3H_CHGR 1UF
10%
1/16W
MF-LF 10%
1
402
2 CHGR_CSIP_XW7020 1 2
402 9.31K 10V 402 2 10V 1CRITICAL
MF-LF
1%
1/16W
C7047 1
1UF
X5R
402-1
X5R
402-1 C7024
0.047UF
1
R7021
R7020
MF-LF
10% 10% 0.02
402 10 0.5%
19
20
2 10V 2 10V 2 5% 1W
X5R
402-1
CERM
402 1/16W
MF-LF
XW7021
SM
MF PP18V5_S5_CHGR_SW_R
VDD VDDP 402 2 0612 CRITICAL CRITICAL
CHGR_AGATE
1 2 CHGR_CSIN_XW7021 1 2
1 1 1 C7022 1 C7023 1 C7027
12 VHST AGATE 1 C7020 C7021 0.001UF
C 57 CHGR_SCL
CHGR_SDA
11 SCL CSIP 28
10 SDA CRITICALCSIN 27
CHGR_CSIP
CHGR_CSIN 1 C7061 1 C7062
22UF
20%
25V
22UF
20%
25V
1UF
10%
25V
1UF
10%
25V
20%
50V
CERM
C
57
0.1UF 0.1UF 2 POLY-TANT 2 POLY-TANT 2 X5R 2 X5R 2 402
U7000 10% 10% CASE-D2-SM CASE-D2-SM 603-1 603-1
NC 4 VREF
QFN BGATE
57 16 CHGR_BGATE
CHGR_DCIN 57 2
25V
X5R
402 2
25V
X5R
402
5 MAX CURRENT = 7A
DCIN 2
CHGR_ACIN 3 ACIN GND_CHGR_SGND 57 CRITICAL PWM FREQ. = 400 KHZ
ISL6258A
BOOT 25 CHGR_BOOT Q7020
CHGR_ICOMP 5 UGATE 24 CHGR_UGATE 4
CRITICAL
ICOMP
RJK0305DPB TO SYSTEM
CHGR_VCOMP 7 VCOMP PHASE 23 CHGR_PHASE MIN_NECK_WIDTH=0.2 MM LFPAK-HF 1 2 =PPBUS_G3H 8
1 C7044 C7042 1
CHGR_VNEG 8 VNEG
LGATE 21 CHGR_LGATE C7025 1
0.01UF 0.033UF
10% CHGR_CSOP 18 CSOP 0.1UF R7008 F7000
10% TRKL* 13 NC 10% 7AMP
16V
2 CERM
16V
X5R
CHGR_CSON 17 CSON 25V
X5R CRITICAL 0.01 1206
2 AMON 9 CHGR_AMON 2 1 2 3 0.5%
402 402
R7045 1 46 57
402 L7000 MIN_LINE_WIDTH=0.6 MM 1W
THRM_PAD
56.2K
C7043 BMON 15 CHGR_BMON 46 MIN_NECK_WIDTH=0.25 MM
MF
0612
1% 0.1UF ACOK 14 CHGR_ACOK 57
1 2 PPVBAT_G3H_CHGR_REG 1 2 PPVBAT_G3H_CHGR_OUT 57
6 AGND
22 PGND
1/16W 1 2 MIN_LINE_WIDTH=0.6 MM
MF-LF MIN_NECK_WIDTH=0.2 MM 4.7UH-9.5A 3 4
402 2
5 IHLP4040DZ-SM CRITICAL 1 C7011 1 C7028
CHGR_VCOMP_R 10% NO STUFF 1
C7008 1UF 0.001UF
1 20%
29
26
16V R7090 10%
50V
X5R 33UF 2
25V
CERM
C7045 1 402 2.2
EMI request 2
20%
16V
X5R
603-1 2 402
57 GND_CHGR_SGND 0.001UF 5%
1/16W POLY-TANT
10% 4 MF-LF CASED2E-SM
50V
CERM 2 MIN_LINE_WIDTH=0.5 MM 2 402
402 MIN_NECK_WIDTH=0.2 MM CHGR_PHASE_SNUBBER PWM FREQ. = 400KHZ
1 2 CRITICAL NO STUFF
MAX CURRENT = 7 A
(??? LIMITED)
XW7000 1 C7026 Q7021 1 C7090
R70461 SM
0.001UF
RJK0305DPB
LFPAK-HF 1 2 3
100PF EMI request
5%
3.01K 10% 50V
2 CERM
1%
1/16W 2 50V
X7R 402
MF-LF 402
402 2
57 GND_CHGR_SGND R7031
B CHGR_VNEG_R
(CHGR_CSOP) 2
10 1 46 CHGR_CSO_R_P
B
C7046 1
5%
470PF
10%
50V
R7047 1/16W
MF-LF
CERM 2 (CHGR_CSON) 2
10 1
402
402 46 CHGR_CSO_R_N
5%
1/16W
(CHGR_CSO_R_N) MF-LF
402
AMON PULLDOWN LOGIC
44 =SMBUS_CHGR_SCL CHGR_SCL 57
57 46 CHGR_AMON BATTERY CHARGING
44 =SMBUS_CHGR_SDA CHGR_SDA 57 CRITICAL CRITICAL
57 8 =PP3V42_G3H_CHGR
Q7050 Q7052
ACOK pullup/down on SMC page Q7070 NO STUFF FDS6681Z FDS6681Z TO BATTERY
56 42 41 SMC_BC_ACOK CHGR_ACOK 57
R70741 SSM6N15FEAPE
SOT563
D 6
R70751 SO-8 SO-8
MAKE_BASE=TRUE
BATT_POS_F
1 2 3
5 6 7 8
5 6 7 8
1 2 3
1M 1M 57 PPVBAT_G3H_CHGR_OUT BATT_POS_INRUSH 56
5% 5%
1/16W 1/16W 1 C7050 1 C7051
MF-LF MF-LF
402 2 402 0.01uF 0.1UF
2 10% 10%
2 G S 1
2 16V
CERM 2 16V
X5R
402 402
1
R7052
4
4
CHGR_VDD_L
1 C7052
0.1UF 1M
10% 5%
2 16V
1/16W
X5R MF-LF
2
Q7070 D 3
CHGR_BGATE
402 402
SSM6N15FEAPE
SOT563
57 BATT_POS_GATE
A A
1
CHGR_VDD SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008
57
R7053 PAGE TITLE
330K
R70731
5 G S 4 5%
1/16W
MF-LF
PBUS Supply/Battery Charger
2
402 DRAWING NUMBER SIZE
1K
5% 051-8089 D
1/16W Apple Inc. REVISION
MF-LF
402 2 R
A.0.0
CHGR_VDD_R THE INFORMATION CONTAINED HEREIN IS THE
70 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
5V_RT/3.3V POWER SUPPLY D
VOUT = (2 * RA / RB) + 2 VOUT = (2 * RC / RD) + 2
<RA> <RB> <RD> <RC>

R7267
15.0K
R7268
10K
R7269
10K
R7270
6.49K
ROUTING NOTE: ROUTING NOTE:
Place XW7203 by Pin1 OF L7260.
XW7203 1%
1/16W
MF-LF
1%
1/16W
MF-LF
1%
1/16W
MF-LF
1%
1/16W
MF-LF
XW7204 Place XW7204 by Pin 2 of L7220.
SM 402 402 402 402 SM
2 1 5VRT_S0_VFB_XW7203 1 2 1 2 1 2 1 2 3V3S5_VFB_R7270 2 1
58
GND_5VRT3V3S5_SGND
ROUTING NOTE:
XW7205
SM Place XW7205 by C7252.
2 1
C 58 8
=PPVIN_S0_5VRTS0 C
ROUTING NOTE:
Place XW7202 by C7292.
XW7202 1 C7272
SM 1UF
10%
2 1 25V
2 X5R
603-1
=PPVIN_S0_5VRTS0 8 58
5V3V3S5_REG3
=PPVIN_S5_3V3S5
5VRTS3_3V3S5_VREF 8
1
EMI request
C7232 1 CRITICAL 1 C7281 1 C7270
10UF
EMI request
0.001UF C7280 1UF 20%

1 C7230 C7241 1 1 CRITICAL
20% 33UF 10% 6.3V
2 X5R 0.001UF C7240
50V 20% 25V 1 C7271 20% 1UF
16
2 CERM 2 2 X5R 603 50V 33UF
16V 10%
3
402 POLY-TANT
CASED2E-SM
603-1 C7260 0.22UF
10% VIN VREF C7220 2 CERM
402 2 25V
X5R 2 20%
16V
5 0.1UF
10% 2 10V
CERM
14 SKIPSEL VREG3 8 0.1UF
10%
603-1 POLY-TANT
16V 402 CASED2E-SM
16V
X5R 4 TONSEL VREG5 17 5V3V3S5_REG5 X5R
CRITICAL 402 MIN_LINE_WIDTH=0.6 MM 402 9 4 3 2
Q7260
D
2 1 5VRT_S0_VBST 22 VBST1 CRITICAL VBST2 9 3V3S5_VBST 2 1 CRITICAL
SI7110DN MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM 5VRT_S0_DRVH 21 DRVH1
U7200 MIN_LINE_WIDTH=0.6 MM
Q7220
PWRPK-1212-8-HF G 4 DRVH2 10 3V3S5_DRVH 1
FDMS9600S
MIN_LINE_WIDTH=0.6 MM QFN
20 LL1 LL2 11 MIN_LINE_WIDTH=0.6 MM MLP CRITICAL
S MIN_NECK_WIDTH=0.2 MM 5VRT_S0_LL 3V3S5_LL
PWM FREQ. = 375 KHZ
TPS51125
PWM FREQ. = 300 KHZ L7260 MIN_NECK_WIDTH=0.2 MM L7220
3 2 1 5VRT_S0_DRVL 19 DRVL1 DRVL2 12 3V3S5DRVL 4.7UH-5.5A
MAX CURRENT = 4A 1 2
5VRT_S0_VO1 24 VO1 VO2 7 5VRT_S0_VO2
Q1
10 EMI request 1 2 MAX CURRENT = 4A
CRITICAL SW NO STUFF
B 3.3UH
IHLP
1
NO STUFF
R7294 5
5VRT_S0_VFB 2 VFB1 VFB2 5 3V3S5_VFB
8 1
R7295
2.2
IHLP2525CZ
B
2.2
8
=PP5VRT_S0_REG 5%
CRITICAL 1 ENTRIP1
5% =PP3V3_S5_REG 8
VOLTAGE=5V 1/16W 5VRT_S0_ENTRIP ENTRIP2 6 3V3S5_ENTRIP 1/16W
MF-LF VOLTAGE=3.3V
EMI request
2
MF-LF
402
D
Q7261 2 402
EMI request
SI7110DN VCLK 18 NC Q2
3V3S5_LL_SNUBBER
MIN_NECK_WIDTH=0.20 MM CRITICAL CRITICAL 5VRT_S0_LL_SNUBBER 4 1 CRITICAL CRITICAL
C7231 C7252
1 C7233 1 C7290
10UF
1
C7291 1
C7292 EMI request
G
PWRPK-1212-8-HF 1 R7271 PGOOD 23 1 R7272 EMI request 0.001UF 1
C7251 1 C7250
10UF
1
0.001UF 20% 150UF

20%
150UF
20%
NO STUFF S
75K EN0 13
1 C7273 75K 7 6 5 1
NO STUFF
C7295
20%
50V 150UF 150UF
20% 20% 20%
20%
50V
2 CERM
6.3V
2 X5R 2 6.3V 2 6.3V
1 C7294
3 2 1
1%
1/16W
NC 10UF
20%
1%
1/16W 100PF
2 CERM
402 2 6.3V 2 6.3V
6.3V
2 X5R
POLY-TANT POLY-TANT 100PF GND THRM_PAD POLY-TANT POLY-TANT
402 603 CASE-B2-SM CASE-B2-SM 5%
MF-LF
2 6.3V MF-LF 5% CASE-B2-SM CASE-B2-SM 603
X5R
15
25
50V 402 402 50V
2 CERM 2 603 2 2 CERM
402 402
58 GND_5VRT3V3S5_SGND 1 2
XW7201
SM
D 6 Q7221
SSM6N15FEAPE P5V3V3_PGOOD
64
SOT563
ROUTING NOTE:
=P5VRTS0_EN_L 2 G S
64 IN
1 Q7221 Place XW7201 between Pin 15 and Pin 25 of U7200.
D 3
SSM6N15FEAPE
SOT563
A 64
=P3V3S5_EN_L 5 G S 4
IN PAGE TITLE
5V/3.3V SUPPLY
DRAWING NUMBER SIZE

REVISION
SEPERATED MASTER PGOOD FOR BOTH 5V AND 3V3. R
A.0.0
72 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1.8V/0.9V(DDR2) POWER SUPPLY D

D VOUT = 0.75V * (1 + RA / RB)
<RB> NO STUFF
1 2
1 2 1V8S3_VDDQSET
R7322
20K <RA> C7303
0.1%
1/16W R7321 5%100PF
MF 28K 402 1% 50V
1/16W CERM
27 8 =PPVTT_S3_DDR_BUF MF-LF 402
402
1 2
1 2
C7340 1 C7301
0.033UF 10UF
10% 20%
16V 6.3V
2 X5R
X5R
402 603
1 2 1V8S3_V5FILT 1 2 =PP5V_S3_1V8S3_0V9S0
C7300 R7307 1 C7302
1UF 4.7 10UF
20%
10% 5% 6.3V
10V 1/16W 2 X5R
X5R MF-LF 603
402-1 402 ROUTING NOTE:
1V5S3_VTTSNS
XW7301
SM
Place XW7301 by L7320.
=PP0V9_S0_REG 1V8S3_VDDQSNS 1 2
C 8
1V8S3_VBST 1 2
C
1V8S3_VBST_RC
=PPVIN_S5_1V8S3_0V9S0
23
24
14
22
15
8
R7300
9
2
0 CRITICAL CRITICAL CRITICAL
5 1 C7332 C7333
1
R7310 VDDQSET VTTREF VLDOIN VTT V5FILT VBST V5IN VDDQSNS VTTSNS
5%
1/16W Q7320
1 C7330
33UF
1 C7331
33UF 1UF
1
0.001UF
1%
10.7K MF-LF
402 20% 20% 10% 20%
1/16W
MF-LF 1
C7309
0.1uF
D SI7110DN
PWRPK-1212-8-HF
2 16V
POLY-TANT 2 16V
POLY-TANT 2 25V
X5R
603-1
2
50V
CERM
402 MAX CURRENT = 12A
2 402 10%
CASED2E-SM CASED2E-SM
16V 4 G CRITICAL
65 26 =DDRVTT_EN 10 S3 PGOOD 13 2
X5R
402 L7320 PWM FREQ. = 400 KHZ
11 S5 CRITICAL
S
1.0UH-13A-5.6M-OHM PUT ONE BULK CAP NEXT TO THE LOAD
MIN_LINE_WIDTH=1 mm SM-IHLP-1
21 1V8S3_DRVH VOLTAGE=1.8V
64 =DDRREG_EN U7300 DRVH
20 1V8S3_LL
MIN_LINE_WIDTH=1 mm
1 2 3
1 2
=PP1V8_S3_REG
XW7303
SYM (1 OF 2) LL 8
MIN_NECK_WIDTH=0.25 mm EMI request
6 TPS51116 NO STUFF
1
CRITICAL
2
COMP 5 R7390 1
QFN MIN_LINE_WIDTH=1 mm C7343 C7344
SM
1V8S3_CS 16 CS
DRVL 19 1V8S3_DRVL MIN_NECK_WIDTH=0.25 mm 2.2 CRITICAL 330UF
1
5%
20% 0.001UF
ROUTING NOTE: ROUTING NOTE:
MODE 4 Q7321
SI7108DN
D 1/16W
MF-LF
1
C7342 1 C7341
10UF
2 2.5V
POLY-TANT
20%
50V
1
2 CERM
Place XW7303 by C7308. 2 402
1V8S3_LL_SNUBBER
330UF 20% CASE-C2-SM1
402
CONNECT CS_GND TO NC0 7 NC PWRPK-1212-8-HF 20%
Q7321 PIN1,2.3 4 G 2 2.5V 2 6.3V
X5R
USING KEVIN CONNECTION. NC1 12 NC POLY-TANT
603
CRITICAL S
EMI request
NO STUFF
CASE-D2E-SM
THRM_PAD CS_GND GND PGND VTTGND 1 C7390

1 C7307 1 C7308 1 2 3
100PF
22UF 22UF
25
17
18
1
5%
20% 20% 50V
2 CERM
6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 402
603 603
B DDRREG_PGOOD
B
GND_1V8S3_SGND 1 2
ROUTING NOTE: XW7300
SM
ROUTING NOTE: R7399
100K
PUT 6 VIAS UNDER THE THERMAL PAD Place XW7300 between 5%
Pin 3 and Pin 25 1/16W
MF-LF
of U7300. 402
GND_1V8S3_CSGND 1 2 1 2 =PP3V3_S3_PDCISENS 8
XW7302
SM ROUTING NOTE:
Place XW7302 by Q7321.
STATE PM_SLP_S4_L PM_SLP_S3_L PP1V8_S3 PP0V9_S0

S0 HIGH HIGH 1.8V 0.9V
S3 HIGH LOW 1.8V 0.0V
S5/G3HOT LOW LOW 0.0V 0.0V
PAGE TITLE
1.8V/0.9V DDR2 SUPPLY

DRAWING NUMBER SIZE

REVISION
R
A.0.0
73 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 =PP5V_S0_CPU_IMVP 60 8 =PPVIN_S5_CPU_IMVP
5
CRITICAL CRITICAL C7419
1 2 PP5V_S0_IMVP6_VDD 1 C7409 1 C7417 1 C7418 1
0.001UF
MIN_LINE_WIDTH=0.25 MM 33UF 33UF 1UF
1 C7426 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V DPRSLPVR DPRSTP* PSI* OPERATION MODE
CRITICAL 20% 20% 10%
20%
50V PWM FREQ. = 300 KHZ
R7412 1UF
10% 1 C7435 Q7400 2 16V
POLY-TANT 2 16V
POLY-TANT
25V
X5R 2 CERM
402
10 6.3V 10UF CASED2E-SM CASED2E-SM 2 603-1
5%
1/16W 2 CERM 20% 0 1 1 2-PHASE CCM
4 RJK0305DPB MAX CURRENT = 44A
D
MF-LF
402
402
2
6.3V
X5R
603
LFPAK-HF
LOAD LINE SLOPE = -2.1 MV/A

D
60 8 =PPVIN_S5_CPU_IMVP 1 2 PPVIN_S5_IMVP6_VIN 0 1 0 1-PHASE CCM
R7420 1 0 1 1-PHASE DCM 1 2 3
10 (IMVP6_PHASE1) =PPVCORE_S0_CPU_REG 8
5%
1/16W 1 C7496 1 0 0 1-PHASE DCM
1 2
MF-LF 0.01UF CRITICAL
10%
69 21 IN
PM_DPRSLPVR 402 16V 5
L7400
CERM
2 402 MIN_LINE_WIDTH=0.25 MM CRITICAL EMI request
0.36UH-30A-0.80MOHM
MIN_NECK_WIDTH=0.2 MM 1 2 IMVP6_BOOT1_RC MPC1055-SM
=PP3V3_S0_IMVP1 2 PP3V3_S0_IMVP6_3V3 Q7401 1
NO STUFF MPC1055LR36
DCR=0.8MOHM 1 C7420
8
4 R7490 0.001UF
C7430 R7424 RJK0328DPB 2.2 1 2
20%
50V
1 0 LFPAK-HF
R7421 0.1uF
10%
1 R7447 5%
5%
1/16W
NO STUFF 2 CERM
402
10 16V 2.0K 1/16W MF-LF
R7451
5% 5% MF-LF 2 402
1/16W X5R
402 1/16W 402 10K
1%
MF-LF 2 MF-LF IMVP6_PHASE1_SNUBBER 1/16W
402 1 2IMVP6_BOOT2_RC MF-LF
60 GND_IMVP6_SGND 2 402 20 22 31 1 2 3 402
EMI request
NO STUFF
R7427
NO STUFF VIN VDD PVCC R7425 C7427 1 C7415
0.1UF
NO STUFF
1 2 1 2 1 2
4.02K R7426
470K 69 11 CPU_VID<6> 43 VID6 BOOT1
36 60 IMVP6_BOOT1 0
5%
1 0.1UF
10%
10%
1 C7490
100PF
1%
1/16W 402 CRITICAL CPU_VID<5> 42 VID5 CRITICAL
BOOT2 26 60 IMVP6_BOOT2
1/16W
MF-LF 16V
16V
2 X5R
NO STUFF 5% R7400 C7403 R7404
MF-LF
402
69 11
CPU_VID<4> 41 VID4 U7400 402 2 X5R 402 1 C7400 50V

2 CERM 10K
1%
0.22uF 1
5%
1 2 1 2 69 11 QFN 402 0.0022UF 402
1/16W 10% 1/16W
CPU_VID<3> 40 VID3 35 IMVP6_UGATE1 10% 6.3V
ISL9504BCRZ
69 11 UGATE1 60 MF-LF MF-LF
1 CERM-X5R
R7445 69 11 CPU_VID<2> 39 VID2
34 2
50V
CERM
402 402 402
NO STUFF 499 38 VID1 PHASE1 60 IMVP6_PHASE1 402
C7410 ERT-J0EV474J 1% 69 11 CPU_VID<1>
1/16W 37 VID0
0.01uF MF-LF 69 11 CPU_VID<0> LGATE1 32 60 IMVP6_LGATE1
10% IMVP6_NTC_R 2 402 (GND)
16V
46 DPRSTP* PGND1 33
CERM 69 14 10CPU_DPRSTP_L
402
69
IN
IMVP_DPRSLPVR 45 DPRSLPVR ISEN1 24 60 IMVP6_ISEN1 (IMVP6_ISEN1)
1 2
C NO STUFF
10 IN CPU_PSI_L
IMVP6_IMON
2 PSI*
3 IMON 27 IMVP6_UGATE2
C
R7406 46 OUT UGATE2 60
=PPVIN_S5_CPU_IMVP
0 8 60
5% PHASE2 28 60 IMVP6_PHASE2
1/16W
MF-LF
48 3V3 CRITICAL CRITICAL C7411 C7422
69 42 14 10
CPU_PROCHOT_L
1
402
2
(NC) 47 CLK_EN*
44 VR_ON
LGATE2 30 60 IMVP6_LGATE2 5 1 C7401
33UF
1 C7408
33UF
1
1UF
10%
1
0.001UF
20% 1
FROM SMC 41 IMVP_VR_ON (GND) 50V R7401
PGND2 29
IN 20% 20% 25V
1 PGOOD 16V 16V X5R CERM 3.65K
1 2 26 OUT VR_PWRGOOD_DELAY 2 POLY-TANT 2 POLY-TANT2 603-1 2 402
5 VR_TT* 1%
IMVP6_VR_TT 23
CASED2E-SM CASED2E-SM 1/16W
R7408 6 NTC ISEN2 60 IMVP6_ISEN2 4 MF-LF
C7405 IMVP6_NTC Q7402 2 402
147K
0.015uF 1% RJK0305DPB
1/16W 7 VSUM 19 60 IMVP6_VSUM
10% MF-LF 60 IMVP6_SOFT SOFT LFPAK-HF
16V 402 OCSET 8 60 IMVP6_OCSET
X7R
402 1 2 60 IMVP6_RBIAS 4 RBIAS VO
18 60 IMVP6_VO NO STUFF
CRITICAL
1 1 2 3
DROOP 16 60 IMVP6_DROOP C7416 (IMVP6_PHASE2) 1 2
60 IMVP6_VDIFF 13 VDIFF 0.001UF
2 CRITICAL
DFB 17 60 IMVP6_DFB 1 2 10%
1 C7406 1 2 IMVP6_FB2 12 FB2 50V 5
CRITICAL L7401 1 C7423
0.001UF 60
1 CERM 0.36UH-30A-0.80MOHM 0.001UF
10% IMVP6_FB 11 FB 14 R7418 R7417 1 C7429 402 20%
50V
CERM
NO STUFF 60
IMVP6_COMP 10 COMP
VSEN
15 1K 4.42K 180pF 1
Q7403 EMI request
NO STUFF
1
MPC1055-SM
MPC1055LR36 50V
CERM
1
R7409
2 402 R7413 60
9 VW
RTN 1%
1/16W
1%
1/16W 5% R7416 RJK0328DPB R7491 DCR=0.8MOHM 2 402
1K IMVP6_VW MF-LF 2 50V 13.7K 4 LFPAK-HF 2.2
IMVP6_VSEN
60 MF-LF
1K 1%
2 402
402 1%
IMVP6_RTN
CERM 5%
1% IMVP6_VDIFF_RC 1/16W 1 2
402 1/16W 1/16W 1 2 1 2 1 2
1/16W MF-LF 25 NC MF-LF MF-LF
MF-LF 402
1 2 402 2 402
2 402 R7411 C7431 (IMVP6_VO) IMVP6_PHASE2_SNUBBER R7405 C7404 R7407
255 GND TPAD 0.068UF 10K
1%
0.22uF 1
5%
1% 10% EMI request 10%
1/16W 21 49 10V 1 1 2 3 NO STUFF
1/16W
6.3V 1/16W
MF-LF
2 402
CERM
402
R7430 1 C7491
MF-LF
402 CERM-X5R
402
MF-LF
402
1 2
60 60
3.92K
(IMVP6_FB) 1% 100PF
60 GND_IMVP6_SGND 1/16W 5%
B VOLTAGE=0 V
(IMVP6_VW) NO STUFF C7434 1 C7428 1
R7415
MF-LF
2 402
NO STUFF
C7402
2 50V
CERM
402
NO STUFF
1 2 B
1 C7414 C7432 1
0.12UF 0.22UF 11K
IMVP6_VO_R 1
0.0022UF
1
R7443 R7452
470PF 0.01UF 10% 10% 1% 10% 3.65K 10K 1%
10% 10.0V 6.3V 1/16W 1 1% 1/16W
50V 10% 2 CERM-X5R 2 CERM-X5R MF-LF 2 50V 1/16W MF-LF
2 CERM 16V 402 402 CRITICAL CERM 402
402 CERM 2 402 MF-LF
C7413 402 R7431 402 2 402
1
220PF 1 C7407 1
R7410 1 2 10KOHM-5%
IMVP6_COMP_RC 5%
25V
0.001UF 6.81K (IMVP6_ISEN2)
10% 1% 0603-LF
CERM 50V
2 402 CERM 1/16W 2
1
R7414
2 402 MF-LF
2 402
C7433 ERT-J1VR103J (IMVP6_VSUM)
0.018UF
97.6K 10%
1% 16V (IMVP6_VO)
1/16W X7R
MF-LF 402
2 402 (IMVP6_COMP)
1 2 R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
NOTE 1: C7432,C7433 = 27.4 OHM FOR VALIDATING CPU ONLY.
1 1
OMIT
2 C7421 R7423 R7422
0.22uF 0 0
XW7400
SM
10%
6.3V
5%
1/16W
5%
1/16W
CERM-X5R MF-LF MF-LF
1 402 2 402 2 402
CPU_VCCSENSE_P 11 60 69 MIN_LINE_WIDTH MIN_NECK_WIDTH
CPU_VCCSENSE_N 11 60 69 60
IMVP6_OCSET 0.25 MM 0.20 MM
60
IMVP6_VSUM 0.25 MM 0.20 MM
GND_IMVP6_SGND 0.50 MM 0.20 MM
IMVP6 CPU VCORE REGULATOR

60
60
IMVP6_VO 0.25 MM 0.20 MM
60
IMVP6_DROOP 0.25 MM 0.20 MM
60
IMVP6_DFB 0.25 MM 0.20 MM
A 60
IMVP6_SOFT
IMVP6_RBIAS
0.25 MM
0.25 MM
0.20 MM
0.20 MM
60 PAGE TITLE
MIN_LINE_WIDTH MIN_NECK_WIDTH MIN_LINE_WIDTH MIN_NECK_WIDTH 60
IMVP6_VDIFF 0.25 MM 0.20 MM
IMVP6 CPU VCore Regulator
60
IMVP6_PHASE1 1.5 MM 0.25 MM 60
IMVP6_PHASE2 0.25 MM 0.25 MM 60
IMVP6_FB2 0.25 MM 0.20 MM
DRAWING NUMBER SIZE
60
IMVP6_BOOT1 0.25 MM 0.25 MM 60
IMVP6_BOOT2 0.25 MM 0.25 MM 60
IMVP6_FB 0.25 MM 0.20 MM
051-8089 D
60
IMVP6_UGATE1 1.5 MM 0.25 MM 60
IMVP6_UGATE2 0.25 MM 0.25 MM 60
IMVP6_COMP 0.25 MM 0.20 MM Apple Inc. REVISION
60
IMVP6_LGATE1 1.5 MM 0.25 MM 60
IMVP6_LGATE2 0.25 MM 0.25 MM 60
IMVP6_VW 0.25 MM 0.25 MM R
A.0.0
60
IMVP6_ISEN1 0.25 MM 0.25 MM 60
IMVP6_ISEN2 0.25 MM 0.25 MM 69 60 11
CPU_VCCSENSE_P NOTICE OF PROPRIETARY PROPERTY: BRANCH
69 60 11
CPU_VCCSENSE_N THE INFORMATION CONTAINED HEREIN IS THE
60
IMVP6_RTN 0.25 MM 0.25 MM PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
IMVP6_VSEN 0.25 MM 0.25 MM
LATEST ISSUE: 2007/01/23 60 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
74 OF 109
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
- SYNC WITH T18
- COPY THIS PAGE FROM T18 CSA.75
D MCP VCORE/5V_S3 LEFT REGULATOR D

=PPVIN_S3_5VLTS3
8
VOLTAGE=12.6V
CRITICAL
1 C7512
0.001UF 5
20%
50V
2
CERM
402
D
Q7510
SI7110DN 4
PP5V_S3_MCPREG_LDO
PWRPK-1212-8-HF G 61
S 8 =PPVIN_S0_MCPREG_VIN
CRITICAL 8 =PPVIN_S0_MCPCORES0
1 1 3 2 1
C7510 C7511 (P5VLTS3_UGATE) CRITICAL
33UF 1UF MIN_LINE_WIDTH=0.6MM
C7500 1 C7501 1 1 1 C7561 1 C7562
20% 10%
GATE_NODE=TRUE
C7560 0.001UF
16V 2 2
25V 10UF 1UF 33UF 1UF 20%
POLY-TANT X5R 10% 10% 20% 10% 50V
CASED2E-SM 603-1 25V
2
6.3V
2 16V 2 2
25V
2 CERM
CRITICAL X5R
805
CERM
402
(Internal 10-ohm path
POLY-TANT
CASED2E-SM
X5R
603-1
402
PWRPK-1212-8-HF from PVCC to VCC)
5
Q7511 61 PP5V_S0_MCPREG_VCC
5
SI7110DN MIN_NECK_WIDTH=0.2 MM
D VOLTAGE=5V CRITICAL
MCPREG_VREF3
(P5VLTS3_LGATE)
MIN_LINE_WIDTH=0.6MM 1 1 4
Q7560
4 MIN_NECK_WIDTH=0.2MM
1 C7503 C7502 (MCPCORES0_UGATE) RJK0305DPB
G GATE_NODE=TRUE C7504 1UF 4.7UF MIN_LINE_WIDTH=0.5 MM
19
MIN_NECK_WIDTH=0.2 MM LFPAK-HF Vout = See below
5
1UF 10% 20%
C S (P5VLTS3_BOOT) 10%
6.3V
6.3V
CERM 2 2
6.3V
X5R-CERM
GATE_NODE=TRUE
MAX CURRENT : 11A C
V5DRV
V5FILT
VREF3
MIN_LINE_WIDTH=0.6MM CERM 2 402 402
3 2 1 MIN_NECK_WIDTH=0.2MM 402 Max load 100mA FREQ = 300 KHZ
TDP: 5.2A
1 C7514 LDO 7 61 PP5V_S3_MCPREG_LDO C7564 1
CRITICAL
(Q7510
7A MAX
LIMIT)
OUTPUT CRITICAL 0.1UF
10%
6 VIN LDOREFIN 8 (SGND)
VOLTAGE=5V 0.22UF
5%
10V
1 2 3
L7500
1.0UH-13A-5.6M-OHM
VOUT = 5V L7520 P5VLTS3_BOOT 17 VBST1 CRITICAL VBST2 24 MCPCORES0_BOOT 2
3.3UH 2
50V
SWITCH_NODE=TRUE
CERM-X7R SM-IHLP-1
FREQ = 400 KHZ X7R
MIN_NECK_WIDTH=0.2MM P5VLTS3_UGATE 15 DRVH1 DRVH2 26 MCPCORES0_UGATE 603
603-1 MIN_LINE_WIDTH=0.6MM
=PP5VLT_S3_REG
8
1 2 (P5VLTS3_PHASE) P5VLTS3_PHASE 16 LL1 U7500 LL2 25 MCPCORES0_PHASE (MCPCORES0_PHASE) 1 2 =PPMCPCORE_S0_REG
8
QFN MIN_LINE_WIDTH=0.5 MM
IHLP P5VLTS3_LGATE 18 DRVL1 DRVL2 23 MCPCORES0_LGATE MIN_NECK_WIDTH=0.2 MM
SN0802043
SWITCH_NODE=TRUE NO STUFF
CRITICAL (=PP5VLT_S3_REG) 10 VOUT1 VOUT2 30 ISNS_PVCORES0MCP_N 46 5 1
1 C7518 1 REGULATE TO AFTER SENSE RES R7596
1 (=P5VLTS3_EN) 14 EN1 EN2 27 2.2
0.001UF C7517 C7516 NO STUFF 5%
20% 150UF 10UF 1 9 VSW 1/16W
EMI request
50V
2
CERM
2
20%
6.3V
20%
10V
2 R7595 P5VLTS3_FB 11 VFB1 REFIN2 32 MCPCORES0_REFIN MF-LF
402 POLY-TANT 2 X5R 2.2 (MCPCORES0_LGATE) 4 2 402
CASE-B2-SM 805
XW7501 5% EMI request P5VLTS3_ILIM 12 TRIP1 TRIP2 31 MCPCORES0_ILIM MIN_LINE_WIDTH=0.5 MM CRITICAL
SM 1/16W MIN_NECK_WIDTH=0.2 MM C7570
CRITICAL PLACEMENT_NOTE=Place next to C7516 MF-LF 29 SKIPSEL GATE_NODE=TRUE MCPCORES0_PHASE_SNUBBER 1
C7567 1 C7566 1 1
C7565 1
C7569
C7515 1 1 2 402 0.001UF 10UF 0.0027UF
150UF (=P5VLTS3_EN) 4 EN_LDO VREF2 1 PP2V_S0_MCPREG_REF CRITICAL 10UF 20% 20%
330UF
NO STUFF 50V 20% 10%
20% VOLTAGE=2V 20% 4V
P5VLTS3_VSNS P5VLTS3_PHASE_SNUBBER PP5V_S0_MCPREG_VCC 20 V5DRV1 PGOOD1 13 Q7565 1 4V 2 CERM 2 2 2.5V 2
50V
6.3V
POLY-TANT
61
Max load 50uA RJK0328DPB
C7596 2 X5R 402
X5R
603 POLY-TANT CERM
402
CASE-B2-SM 2 NO STUFF NO STUFF 2 TONSEL PGOOD2 28 1 2 3 100PF EMI request 603 CASE-C2-SM
NO STUFF 1 LFPAK-HF
1 C7520 1 R7570 50V
5%
R7521 1 C7595 THRM_PAD GND PGND 48.7K 2 CERM
61.9K 100PF 0.1% 402
5% 100PF EMI request
33
21
22
1% 50V 5% 1/16W
1/16W CERM 2 MF
MF-LF 402 2 50V
CERM 402
2
2 402 402
<Ra> <Ra>
R75201
180K
1
R7522 5% XW7500 1 R7530
1
R7571
1 1
R7580
1
R7581
1
R7582
1/16W SM C7530
0 MF-LF 0.1UF 180K 54.9K 475K 237K 110K
5% 402 1 2 5% 0.1% 0.1% 0.1% 0.1%
1/16W 2 20%
1/16W 1/16W 1/16W 1/16W 1/16W
B MF-LF
2 402
2
10V
CERM
402
MF-LF
402 2
MF
402 2
MF
2 402
MF
2 402
MF
2 402
B
<Rb> GND_MCPREG_SGND
<Rb> <Rc> <Rd> <Re> PLACE C7565 AND C7568 ONE CLOSE TO U7500 AND ANOTHER CLOSE TO MCP.
MIN_LINE_WIDTH=0.5 MM MCP_VID0_L MCP_VID1_L MCP_VID2_L
Vout = 0.7V * (1 + Ra / Rb) VOLTAGE=0V Q7582
D 3 D 6 SSM3K15FV D 3
64 IN =P5VLTS3_EN Q7580 Q7580
Vout = 2.0V * Req / (Ra + Req) SOD-VESM-HF =PPVCORE_S0_MCP 8 22 24 46
64 MCPCORES0_PGOOD SSM6N15FEAPE SSM6N15FEAPE
OUT SOT563 SOT563
64 OUT P5V_LT_S3_PGOOD Req = Rb || Rc || Rd || Re
64 IN =MCPCORES0_EN
CRITICAL
5 G S 4
2 G S 1
1 G S 2 1
C7568
330UF
R7590 20%
7.5K 2 2.5V
21 IN MCP_VID<0> 1 2 MCP_VID0_RC POLY-TANT
CASE-C2-SM
21 IN MCP_VID<1> 5% MCP_VID1_RC
1/16W
21 IN MCP_VID<2> MF-LF R7591 MCP_VID2_RC
402 7.5K
1 2
5%
1/16W
C7590 1
C7591 1
C7592 1
C7568 NEEDS TO BE PLACE CLOSE TO LOAD SIDE
R7592 MF-LF 0.1UF 0.1UF 0.1UF CONNECTING IT TO AFTER SENSE RESISTOR INSTEAD OF BEFORE
7.5K 402 20% 20% 20%
1 2 10V 10V 10V
CERM 2 CERM 2 CERM 2
Rev A01 Production 5%

1/16W
402 402 402
MF-LF
402
VID<2:0> Voltage Voltage MCP Target
000 +1.224V +1.060V +1.05V

001 +1.159V +0.994V +1.00V
A 010 +1.101V +0.937V +0.95V M97 DIFFERENCES FROM LAST SYNC ON 12/05/07 TO T18 MLB:
Added C7568 bulk cap on output.
011 +1.049V +0.885V +0.90V PAGE TITLE
100 +0.995V +0.830V +0.85V

Tied TON to REF.
Changed Q7510 to 376S0674.
MCP VCORE REGULATOR
DRAWING NUMBER SIZE
C7500 changed to 138S0638.
101 +0.952V +0.789V +0.80V
L7560 changed from T18 MLB inductor to 152S0782. Apple Inc. 051-8089 D
REVISION
110 +0.913V +0.752V +0.75V Changed Q7565 to 376S0637.
Changed R7514 to 280K, R7564 to 180K.
R
A.0.0
111 +0.876V +0.719V +0.70V NOTICE OF PROPRIETARY PROPERTY: BRANCH
75 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
CPUVTT POWER SUPPLY D
8 =PPVIN_S0_CPUVTTS0
CRITICAL
C7630 1 1 C7695 1 C7696
33UF 1UF 0.001UF
20% 10% 20%
16V 2 2
25V 50V
POLY-TANT X5R
2
CERM
CASED2E-SM 603-1 402
5
CRITICAL
C D C
Q7620
4 G
SI7110DN
PWRPK-1212-8-HF
S
8 =PP5V_S0_CPUVTTS0 1 2 3
L7620 =PPCPUVTT_S0_REG 8 65
1.0UH-13A-5.6M-OHM
R7601 1 2 CRITICAL Vout = 1.052V
301 8A max output
PLACEMENT_NOTE=Place XW7665 next to L7620

1 2 PP5V_S0_CPUVTTS0_V5FILT
SM-IHLP-1 F = 400 KHZ
1%
R7603 1 5 EMI request
187K NO STUFF
10
1/16W VOLTAGE=5V 1
4
1 1
MF-LF
402
C7601 C7604 1% R7690
1UF 4.7UF 1/16W
MF-LF D
CRITICAL 2.2
10% V5FILT V5DRV 10% 1
C7665
10V
2 2
6.3V 402
2 Q7621 5%
1/16W
2
X5R
402-1 CRITICAL X5R-CERM
603 SI7108DN MF-LF
XW7665
10UF
20% 1 C7661
4 G 2 402 6.3V 0.001UF
U7600 PWRPK-1212-8-HF
CPUVTTS0_LL_SNUBBER
SM 2 X5R 20%
TPS51117RGY_QFN14 1
603 50V
SYM (2 OF 2) S CERM
=CPUVTTS0_EN
QFN
CPUVTTS0_TON
C7603 1
EMI request 2 402
64 IN 1 EN_PSV TON 2
0.1UF NO STUFF CRITICAL
10%
1 2 3 1
64 CPUVTTS0_PGOOD 6 PGOOD VBST 14 CPUVTTS0_VBST 50V
2
1 C7690 C7660
OUT X7R 100PF 330UF
MIN_LINE_WIDTH=0.6MM 603-1
MIN_NECK_WIDTH=0.2MM 5% 20%
(=PPCPUVTT_S0_REG) 3 VOUT DRVH 13 CPUVTTS0_DRVH 50V
2 CERM 2.5V 2
GATE_NODE=TRUE MIN_LINE_WIDTH=0.6MM POLY-TANT
MIN_NECK_WIDTH=0.2MM 402 CASE-C2-SM
CPUVTTS0_VFB 5 VFB LL 12 CPUVTTS0_LL
SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6MM
CPUVTTS0_TRIP 11 TRIP DRVL 9 CPUVTTS0_DRVL CPUVTTS0_VSNS
GATE_NODE=TRUE MIN_LINE_WIDTH=0.6MM
GND THRM_PAD PGND MIN_NECK_WIDTH=0.2MM
1
NO STUFF
15
R7670 C7670
7
1
8.45K
B 1
R7604
6.65K
1%
1/16W
MF-LF
100PF
5%
50V
CERM 2
B
1%
XW7600 2 402 402
1/16W
MF-LF SM <Ra> 2 XW7601
2 402 1 2 (GND)
SM
1
R7671 1
ROUTING NOTE: 20.0K
1%
1/16W
Place XW7600 between Pin 7 and Pin 15 of U7600. MF-LF ROUTING NOTE:
402
2
GND_CPUVTTS0_SGND
<Rb> Place XW7601 by C7660.
VOLTAGE=0V
Vout = 0.75V * (1 + Ra / Rb)
(CPUVTTS0_VFB)
CPUVTT_VOUT (=PPCPUVTT_S0_REG)
PAGE TITLE
CPU VTT(1.05V) SUPPLY

DRAWING NUMBER SIZE

REVISION
R
A.0.0
76 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FireWire 1.0V (Core) Supply CRITICAL

L7710
4.7UH-0.8A
D CRITICAL
P1V0FW_SW
1
PCAA031B-SM
2
<Ra>
=PP1V0_FW_REG
Vout = 1.001V
8
D
SWITCH_NODE=TRUE
U7780
C7712 1
1
R7712 300mA max output
LTC3410ESC6
22pF 52.3K
SC70 5%
1% (Switcher limit)
50V 1/16W
CERM 2 MF-LF
8 =PP3V3_FW_P1V0FW 4
VIN SW 3
402 2 402 f = 2.25 MHz
1 P1V0FW_VFB
RUN VFB 6 1 C7715
GND <Rb> 4.7UF
1 20%
C7710 1
5 2 R7713 6.3V
2
4.7UF 200K X5R-CERM
20% 402
6.3V 1%
X5R-CERM 2 1/16W
402 MF-LF
2 402
Vout = 0.8V * (1 + Ra / Rb)
C C
MCP 1.05V_S5 AUXC SUPPLY

1.5V S0 SWITCH
=PP3V3_S5_P1V05S5
8
CRITICAL 65 8 =PP3V3_S0_FET
1
R7722 1 C7720
1
5% 22UF
20%
1
R7742 1 C7740
1/16W
MF-LF 2 6.3V 1
5% 22UF
402 CERM 1/16W 20%
2 805 MF-LF 6.3V
1V05S5_AVIN CRITICAL 2 402
2 CERM
805
L7720 CRITICAL
10
1V5S0_AVIN
9
2.2UH-3.25A L7740
10
9
AVINPVIN IHLP1616BZ-SM 2.2UH-3.25A
=P1V05_S5_EN
=PP1V05_S5_REG IHLP1616BZ-SM
64 6 EN CRITICAL SW 1 1V05S5_SW 1 2 8
AVINPVIN
<Ra> =P1V5S0_EN CRITICAL SW 1V5S0_SW 1 2 =PP1V5_S0_FET

5
U7750 4 1V05S5_FB 1 C7782
1 Vout = 1.05V
64 6 EN 1
<Ra>
OVT
TPS62510
FB
22PF
R7780 U7740 1
C7742 R7740 VOUT = 1.5V
B 7 MODE 8
5%
50V
301K
1% CRITICAL MAX Current = 1.5A 5 OVT
TPS62510
FB 4 1V5S0_FB 1
22PF 301K MAX CURRENT = 1.5A
B
C7781 BQA PG 2 CERM
402 2
1/16W
MF-LF
1 C7783 FREQ = 1MHZ
7 8
5%
50V 1%
1 AGND PGND THRM_PAD
402
<Rb>
22UF
20%
C7741 MODE BQA PG 2 CERM
402 2
1/16W
MF-LF
402
1 C7743 FREQ = 1MHZ
6.3V 22UF
0.1UF
10%
1
R7781
2 CERM 1 AGND PGND THRM_PAD <Rb> 20%
6.3V
3
11
805
2 16V
X5R 392K 0.1UF
10%
1
R7741 2 CERM
805
11
402 P1V05_S5_PGOOD 64 1% 16V
OUT
1/16W 2 X5R P1V5_S0_PGOOD
200K
1%
MF-LF
402
402 OUT 64
1/16W
2 MF-LF
1V05S5_SGND 1 2
2 402
MODE_GND 1 2
VOUT = 0.6V * (1 + Ra / Rb) XW7700
SM
VOUT = 0.6V * (1 + Ra / Rb) XW7740
SM
PAGE TITLE
MISC POWER SUPPLIES

DRAWING NUMBER SIZE

REVISION
R
A.0.0
77 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V 1.05V S5 ENABLE

R7802 Power Control Signals
100K
64 8 =PP3V42_G3H_PWRCTL 2 1 PM_G2_P3V3S5_EN_L =P3V3S5_EN_L 58
OUT
MAKE_BASE=TRUE
5%
1/16W 5VLT_S0, 3.3V_S0, 1.8V_S0 ENABLE
MF-LF NO STUFF
402 1 C7802 MCPDDR, CPUVTT,MCPCORES0 ENABLE
0.068UF
Q7800 10% 1.5V S0 AND 1.05V S0 ENABLE
D SSM3K15FV
SOD-VESM-HF
D 3 2
10V
CERM
402
D
SMC_PM_G2_EN
R7813
41 IN 68K
64 8 =PP3V42_G3H_PWRCTL 2 1 PM_SLP_S3_L_INVERT =P5VRTS0_EN_L 58
OUT
MAKE_BASE=TRUE
1 5%
Q7813
R7800 1/16W
D 3
100K 1 G S 2 MF-LF SSM3K15FV
402 SOD-VESM-HF
5% NO STUFF
1/16W
R7801 1 C7813
MF-LF
402 5.1K 0.068UF
2 2 1 PM_G2_P1V05S5_EN =P1V05_S5_EN 63
MAKE_BASE=TRUE
OUT 10%
10V
5% 2 CERM
1/16W 1 G S 2 402
MF-LF 1 (PM_SLP_S3_L)
402 C7801
0.47UF 41 36 33 21 PM_SLP_S3_L
10% IN
6.3V
2 CERM-X5R NO STUFF
402
1
64 8 =PP3V3_S5_PWRCTL
C7858
R7879 0.1UF PM_SLP_S3_L_BUF =P3V3S0_EN OUT 65
100K
5%
2 1 MAKE_BASE=TRUE
1/16W
MF-LF =PBUSVSENS_EN OUT 45
20%
402
2 10V
CERM
402
NO STUFF 5 TC7SZ08AFEAPE
2 SOT665
A
4 (PM_SLP_S3_L_BUF) 1
U7859 Y R7880 R78811 R78821 R78831
(PM_SLP_S3_L) 1 22K 33K 0 5.1K
B
5% 5% 5% 5%
3 1/16W 1/16W 1/16W 1/16W
402 402 402 402 2
S3 ENABLE 2 2 2
P1V8S0_EN =P1V5S0_EN 63
OUT
(PM_S4_STATE_L) MAKE_BASE=TRUE
C 42 41 21 IN PM_SLP_S4_L
MAKE_BASE=TRUE
C7810
=P3V3S3_EN
OUT 65
MCPDDR_EN
MAKE_BASE=TRUE
=MCPDDR_EN
OUT 65 C
R7811 0.47UF
1
5.1K CPUVTTS0_EN =CPUVTTS0_EN OUT 62
R7810 1 2 MAKE_BASE=TRUE
100K 1 2 R7859 MCPCORES0_EN =MCPCORES0_EN
5%
1/16W
5%
1/16W 10%
2
100 1 MAKE_BASE=TRUE
OUT 61
MF-LF MF-LF 6.3V

402 CERM-X5R
402
2
5%
402
1/16W
MF-LF
DDRREG_EN 402 NO STUFF
=DDRREG_EN OUT 59
MAKE_BASE=TRUE 1 C7880 1 C7881 1 C7882 1 C7883
NO STUFF 0.47UF 0.47UF 0.47UF 0.47UF
C7812 =USB_PWR_EN OUT 39 10% 10% 10% 10%
R7812 0.47UF 2
6.3V
CERM-X5R
2
6.3V
CERM-X5R
2
6.3V
CERM-X5R
2
6.3V
CERM-X5R
0 402 402 402 402
1 2
1 2
5%
1/16W 10%
MF-LF 6.3V
402 CERM-X5R
402
P5VLTS3_EN =P5VLTS3_EN 61
MAKE_BASE=TRUE OUT
64 8 =PP3V42_G3H_PWRCTL
OTHER S0 RAILS PGOOD C7840 1

0.1uF 1
B 64 8
=PP3V3_S5_PWRCTL
20%
10V
CERM 2
R7840
100K
5%
B
402
8 =PP3V3_S0_PWRCTL 1/16W
6
MF-LF
402
2
VDD
5.0V (RIGHT AND LEFT), 3.3V AND 1.5V S0 RAILS MONITOR CIRCUIT
5 SENSE 1
R7820
1 U7840RESET* RSMRST_PWRGD 41
10K
TPS3808G33DBVRG4
LAYOUT_NOTE: ADD XW IF NEEDS TO SAVE SPACE FOR PIN2,10,1,9 CT SOT23-6
5% 4 CT MR* 3 P1V05_S5_PGOOD 63
1/16W
MF-LF TPS3808 MR* HAS INTERNAL PULLUP
402
GND
2
2
8 =PP3V3_S0_VMON
1 NEED TO CHANGE SIMBOL

63 P1V5_S0_PGOOD
C7841
IN 0.001UF
C7870 1
20%
0.1uF 58 IN P5V3V3_PGOOD 50V
2
20% CERM
10V 402
CERM 2
402 61 IN MCPCORES0_PGOOD
3
VCC 62 CPUVTTS0_PGOOD
IN
U7870
LTC2909
61 IN P5V_LT_S3_PGOOD
1 SEL DFN TMR 2 TIE TMR TO GND
TRST = 200MS
ALL_SYS_PWRGD 7 26 41
OUT
MAKE_BASE=TRUE
8
=PP1V8_S0_VMON 8 ADJ1
RST* 4 S0PGOOD_PWROK (S0PGOOD_PWROK)
7 ADJ2
6 REF
NC
8
=PP1V05_S0_VMON GND THRM_PAD
A A
5
Unused PGOOD signal SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008

PAGE TITLE
LTC2901 THRESHOLD IS 95% (4.75V, 3.136V)
1.5V 1.05V COMPARED TO 0.5V
TP_ENETLV_PGOOD
MAKE_BASE=TRUE
ENETLV_PGOOD POWER SEQUENCING
DRAWING NUMBER SIZE

REVISION
R
A.0.0
78 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V S3 FET
CRITICAL
Q7910
1.8V S0 FET
(1.8V S0 FET FOR DDR2 MEM)
FDC638P_G
SM
6 =PP3V3_S3_FET 8 21
3.3V S3 FET 8 =PP1V8_S3_P1V8S0FET
4
5 1.8V S0 FET
D
8 =PP3V3_S5_P3V3S3FET
2
1
MOSFET FDC638P
MOSFET FDM6296G D
R7912 1
CHANNEL P-TYPE C7902 1
10K
C7911 1
RDS(ON) 48 mOhm @4.5V

0.1UF
20%
5
CHANNEL N-TYPE
5%
0.033UF 10V
1/16W
10% 3 CERM
2
D RDS(ON) 15 MOHM @4.5V VGS
MF-LF
16V
2 LOADING 0.182 A (EDP) 402 CRITICAL
X5R
402
2
R7910
402 C7910 R7901 Q7901 LOADING 5A (EDP)
0.01UF 10K FDM6296G
47K 1 2 8 =PP5V_S3_MCPDDRFET 1 2 MCPDDR_SS 4 G
P3V3S3_EN_L 1 2 P3V3S3_SS MICROFET3X3
5%
1%
S CKT FROM T18
10% 1/16W
1/16W
MF-LF
Q7903 MF-LF 16V
1
Q7971 D 6
402 CERM
402
R7903 402 1 2 3
SSM3K15FV D 3 100K SSM6N15FEAPE
SOD-VESM-HF 5% SOT563 =PP1V8_S0_FET 8
1/16W
MF-LF
402
2
R7971 2 G S 1
1
C7903
47K 0.068UF
1 G S 2 MCPDDR_EN_L 1 2 10%
10V
64 =P3V3S3_EN 2 CERM
IN 5%
1/16W 402
MF-LF
Q7971 D 3
402
MCPDDR_EN_L_RC
SSM6N15FEAPE
SOT563
5 G S 4
3.3V S0 FET 64 IN =MCPDDR_EN
CRITICAL
Q7930
C FDC606P_G
SOT-6
C
3.3V S0 FET
6
=PP3V3_S0_FET 8 63
5
MOSFET FDC606P
S
D
4
2
8 =PP3V3_S5_P3V3S0FET
1
CHANNEL P-TYPE
R7932 1
G
100K RDS(ON) 26 MOHM @4.5V

5% C7931 1
0.033UF
3
1/16W
MF-LF
10%
LOADING 1.431 A (EDP)
402
2
R7930
16V
2
C7930
X5R
0.01UF
47K 402
1 2
P3V3S0_EN_L 1 2 P3V3S0_SS
5%
1/16W 10%
16V
Q7905 MF-LF
402 CERM
402
SSM3K15FV D 3
SOD-VESM-HF
MCP79 DDRVTT FET

1 G S 2
64 =P3V3S0_EN
IN
MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT
NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.
IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE
MUST GUARANTEE MEM_CKE SIGNALS ARE LOW
BEFORE RAIL IS TURNED OFF, AND REMAINS LOW
UNTIL AFTER RAIL TURNS BACK ON OR DIMMS
WILL EXIT SELF-REFRESH PREMATURELY.
B MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP

ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS
B
LOW THROUGH VTT TERMINATION RESISTORS.
R7975
10
8 =PPVTT_S0_VTTCLAMP 2 1 VTTCLAMP_L 90mA max load @ 0.9V
5% 81mW max power
=PP1V05_S0_FET 8 1/10W
MF-LF
R79551 =PP5V_S3_VTTCLAMP
603
CKT FROM T18
0 8
5% Q7975 D 6
1/8W
MF-LF 1 SSM6N15FEAPE
805 2 R7976 SOT563
100K
62 8 =PPCPUVTT_S0_REG 5%
1/16W
MF-LF
402 2 2 G S 1
VTTCLAMP_EN
D NO STUFF
Q7975 3
C7976 1
SSM6N15FEAPE
SOT563 0.001UF
20%
50V
CERM 2
402
A 5 G S 4 SYNC_MASTER=K36B_MLB SYNC_DATE=08/17/2008 A
59 26 =DDRVTT_EN PAGE TITLE
IN
POWER FETS
DRAWING NUMBER SIZE

REVISION
R
A.0.0
79 OF 109
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
8
=PP5V_S0_LCD
PP5V_INV
R9000
1
100K
VOLTAGE=5V
L9003
FERR-120-OHM-1.5A
1% =PPBUS_S5_INV 1 2 7 PPBUS_ALL_INV_CONN
1/16W 3 8
MF-LF Q9005 0402-LF VOLTAGE=12.6V
2 402 MIN_LINE_WIDTH=0.30 MM
R9001
100K
D NTK3142PXXH
D INV_PWREN_F_L 1 2 INV_PWREN_L 1 G
SOT723-3-HF
L9002
INVERTER CONNECTOR D
Q9006 1%
1/16W 0
SSM3K15FV D 3 MF-LF
402
S 1 2 CRITICAL
SOD-VESM-HF 5%
1/16W J9000
2 MF-LF
402
78171-0004
M-RT-SM
L9000 5
1 G 120-OHM-0.3A-EMI
S 2 C9014
LVDS_IG_BKL_ON 0.0022UF 1 2 7 PP5V_INV_F 1
66 18 IN 1 2 0402-LF VOLTAGE=5V 7 INV_GND 2
3
10% MIN_NECK_WIDTH=0.20 MM
50V
CERM
7 INV_BKLIGHT_PWM_L
4
402 L9001
120-OHM-0.3A-EMI 6
1 2
66 8 =PP3V3_S0_LCD 0402-LF 518S0521
1 C9001 1 1 1 C9000
CRITICAL
100PF
C9002 C9003 100PF
5%
100PF
5%
0 5%
5 TC7SZ08AFEAPE 5%
BKLT_PLT_RST_L 2 SOT665 2 50V
CERM 2 50V
CERM
1/16W 2 50V
CERM
26 A 402 MF-LF 402
402
4 BKLIGHT_CTL 2 402
1
U9053Y
66 18 LVDS_IG_BKL_PWM B
3
C90591 THIS GND CONECTS TO CHASSIS GND
0.1UF
10% INVT_CHGND 9
16V 2
X5R
402
C CRITICAL C
Q9003
FDC606P_G
SOT-6 6
5 PP3V3_LCDVDD_SW
=PP3V3_S5_LCD
D
8
4 2
1
VOLTAGE=3.3V
1
R9002 LCD + CAMERA CONNECTOR
G
100K
5%
1/16W
MF-LF 3
1 C9011 1 C9012
0.1UF 10UF
2 402 R9023 10%
2 16V
20%
2 6.3V
LCDVDD_PWREN_L 1
10K 2 LCDVDD_PWREN_L_R
X5R
402
X5R
603
5% CRITICAL
Q9004 1/16W
MF-LF J9001
SSM3K15FV D 3 402 S-050162B
SOD-VESM-HF F-RT-SM
25
C9013
0.0033UF =GND_CHASSIS_LVDS 23
1 2 66 9
1 G S 2 L9004
10% FERR-120-OHM-1.5A 1
50V
66 18 IN LVDS_IG_PANEL_PWR CERM
402
1 2 7 PP3V3_LCDVDD_SW_F 2
0402-LF VOLTAGE=3.3VMIN_LINE_WIDTH=0.30MIN_NECK_WIDTH=0.20
MM MM 3
L9008 7 PP3V3_S0_LCD_F (LVDS DDC POWER) 4
120-OHM-0.3A-EMI VOLTAGE=3.3V MIN_LINE_WIDTH=0.25 MIN_NECK_WIDTH=0.20
MM MM 5
IT IS CO-LAY FUNCTION
66 8 =PP3V3_S0_LCD 1 2 6
B 66 18 7 LVDS_IG_DDC_CLK
0402-LF
CRITICAL
71 18 7
71 18 7
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<0>
7
8 B
66 18 7 LVDS_IG_DDC_DATA L9006
90-OHM-200MA
71 18 7 LVDS_IG_A_DATA_N<1> 9
AMC2012-SM LVDS_IG_A_DATA_P<1> 10
66 8 =PP3V3_S0_LCD SYM_VER-1
71 18 7
LVDS_IG_A_DATA_N<2> 11
71 18 7
71 18 LVDS_IG_A_CLK_N 1 4
12
71 18 7 LVDS_IG_A_DATA_P<2>
1
R9015 1R9016 CRITICAL
LVDS_IG_A_CLK_P
7 LVDS_IG_A_CLK_F_N 13
14
2.7K 2.7K L9007 71 18
2 3 7 LVDS_IG_A_CLK_F_P
5% 5% 90-OHM-200MA 15
1/16W
MF-LF
1/16W
MF-LF 72 20 USB_CAMERA_P LCD I/F
2 3 16
2 402 2 402
72 7 USB2_CAMERA_CONN_P 17
72 20 USB_CAMERA_N 72 7 USB2_CAMERA_CONN_N 18 CAMERA I/F
66 18 7 LVDS_IG_DDC_CLK 1 4
19
L9005
FERR-120-OHM-1.5A
SYM_VER-1
AMC2012-SM 20
21
66 18 7 LVDS_IG_DDC_DATA 8 =PP5V_S3_CAMERA 1 2 7 PP5V_S3_CAMERA_F NC
NC 22
0402-LF VOLTAGE=5V
LVDS_IG_BKL_PWM MIN_LINE_WIDTH=0.30 MM 24
66 18
LVDS_IG_BKL_ON
1 C9016 1 C9015 1 C9010
66 18 0.001UF 0.001UF 0.001UF 66 9 =GND_CHASSIS_LVDS 26
LVDS_IG_PANEL_PWR 10% 10% 10%
66 18 50V
2 CERM 2 50V
CERM
50V
2 CERM
402 402 402 Plexi: 516S0212
*Enclosure: 518S0364
R90191 R90181 R90121

1K 1K 1K
5% 5% 5%
1/16W 1/16W 1/16W
A MF-LF
402 2
MF-LF
402 2
MF-LF
402 2
PAGE TITLE
INVERTER,LVDS
DRAWING NUMBER SIZE

REVISION
LVDS: Power +VDD_IFPx at 1.8V R
A.0.0
Dual-channel TMDS: Power +VDD_IFPx at 3.3V NOTICE OF PROPRIETARY PROPERTY: BRANCH
90 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
18 =MCP_HDMI_DDC_CLK DP_IG_DDC_CLK 68
MAKE_BASE=TRUE
D9301, D9302, D9303, D9304 PLACE CLOSE TO J9401
=MCP_HDMI_DDC_DATA 18 DP_IG_DDC_DATA 68
MAKE_BASE=TRUE
CRITICAL CRITICAL CRITICAL CRITICAL
D9301 D9301 D9303 D9303
RCLAMP0524P RCLAMP0524P RCLAMP0524P RCLAMP0524P
SLP2510P8 SLP2510P8 SLP2510P8 SLP2510P8
D D
5 IO IO 4 2 IO IO 1 5 IO IO 4 2 IO IO 1
6 NC NC 7 9 NC NC 10 6 NC NC 7 9 NC NC 10
GND
GND
GND
GND
C9301 3 3 3 3
0.1UF
10V
CERM
20%
402 C9302
0.1UF
2
18 MCP_HDMI_TXC_P 10V 20% TMDS_TX_CLK_P 68
CERM 402
2
18 MCP_HDMI_TXC_N TMDS_TX_CLK_N 68
C9303
0.1UF
10V
CERM
20%
402 C9304
0.1UF
2
18 MCP_HDMI_TXD_P<0> 10V 20% TMDS_TX_P<0> 68
CERM 402
2
18 MCP_HDMI_TXD_N<0> TMDS_TX_N<0> 68
C9305
0.1UF
10V
CERM
20%
402 C9306
0.1UF
10V 20%
1
18 MCP_HDMI_TXD_P<1> TMDS_TX_P<1> 68
CERM 402
1
2
C C9307
0.1UF
C
10V
CERM
20%
402
C9308
0.1UF
1
18 MCP_HDMI_TXD_P<2> 10V 20% TMDS_TX_P<2> 68

CERM 402
1
R9301 R9302 R9304 R9306

2
2
499 499 499 499
1% 1% 1% 1%
1/16W 1/16W 1/16W 1/16W
402 402 402 402
1
1
R9303 R9305 R9307 R9308
2
2
499 499 499 499
1% 1% 1% 1%
1/16W 1/16W 1/16W 1/16W
402 402 402 402
1
1
B B
Interface Mode Setting

L9320
R9321 600-OHM-300MA
MCP_HDMI_HPD
1.00K2
1 HDMI_HPD_R 1 2 TMDS_HTPLG DP_IG_CA_DET
18 68 18
0.1% 0402
1/16W
MF
402 1
R9370
1M
1 C9320 R9322 1 C9321 5%
2
100PF 180PF 1/16W

5% 100K 5% MF-LF
402
2 50V
CERM
1% 2 50V
CERM
2
1/16W
402 MF-LF 402
402
1
PAGE TITLE
TMDS ALIASES
DRAWING NUMBER SIZE

R9322, C9320 PLEASE PLACE CLOSE TO MCP79 R9321, L9320, C9321 PLEASE PLACE CLOSE TO J9401 REVISION
R
A.0.0
93 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Video Connectors EXTERNAL VIDEO (VGA) INTERFACE

D D
Isolation required for DVI power switch
TMDS(MINI DVI) INTERFACE
NEED CHANGE SYMBOL
CRITICAL
F9404 D9401 L9444
600-OHM-300MA
0.5AMP-13.2V 1SS418 PLACE THE RESISTOR CLOSE TO MCP79 AND THE CAP NEAR J9401
8 =PP5V_S0_TMDS 1 2 PP5V_S0_TMDS_FUSE 2 1 1 2 PP5V_S0_DVIPORT 68
VOLTAGE=5V VOLTAGE=5V 0402 VOLTAGE=5V
MIN_LINE_WIDTH=0.30 MM MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.20 MM SM-HF MIN_NECK_WIDTH=0.25 MM SOD-723-HF MIN_NECK_WIDTH=0.25 MM
1 C9404 =PP3V3_S0_TMDS 8 68
0.1UF
1 C9408
0.047UF
1 C9409
0.047UF
20%
2 10V
CERM
1 C9460
10%
16V
10%
16V C9409 PLACE CLOSE TO Z0912 402 0.1UF
20%
2 X7R 2 X7R 10V
402 402 2 CERM
=GND_CHASSIS_TMDS_UPPER 9 68 CRITICAL 402
U9404
8 SN74LVC2G125DCU
R9460
0 VCC
US
R9470
71 18 CRT_IG_HSYNC 1 2 CRT_HSYNC_LS_R
5 3 CRT_HSYNC_LS 1 39 2 VGA_HSYNC 68
C9408 PLACE CLOSE TO F9404
5%
A
125 Y
5%
1/16W GND 1/16W NO STUFF
PP5V_S0_DVIPORT_D MF-LF MF-LF
402 4
7 402 1 C9442
DVI power DIODE on page 95 (D9500) 47PF
5%
2 50V
CERM
402
1 1 PLACE THE RESISTOR CLOSE TO MCP79 AND THE CAP NEAR THE CONNECTOR
R9462 R9463
C 2.7K 5%
2.7K
5%
CRITICAL
U9404
8 SN74LVC2G125DCU
C
1/16W
MF-LF
1/16W
MF-LF R9461
0 VCC
US
R9471
39
4022 2402 CRT_IG_VSYNC 1 2 CRT_VSYNC_LS_R
2 A 6 CRT_VSYNC_LS 1 2 VGA_VSYNC 68
71 18
5%
125 Y
5%
1/16W GND 1/16W NO STUFF
MF-LF MF-LF
67 TMDS_HTPLG 402 4
1
402 1 C9443
47PF
5%
=PP3V3_S0_TMDS 2 50V
68 8
1 C9410
0.001UF
CERM
402
10%
R94211 R94221 Q9401 2 50V
CERM
402
2.7K
5%
2.7K
5% SSM6N15FEAPE
1/16W
MF-LF
1/16W
MF-LF 5 GPU_CRT_DDC_CLK
4022 4022
G
SOT563
2
Q9401 1 C9411
220PF
CRITICAL
DP_IG_DDC_CLK SSM6N15FEAPE L9405
S
5%
G
67 BI 25V
3 SOT563 2 CERM 90-OHM-100MA
4 1210-4SM1
TMDS_TX_P<2>
402 OMIT 67
2 3
DP_IG_DDC_DATA GPU_CRT_DDC_DATA
S
67 BI
1 6 CRITICAL
NOTE: CRT_DDC_* ARE NOT 5V COMPLIANT
1 C9412 J9401 1 4
TMDS_TX_N<2> 67
220PF MINI-DVI-M42-MG3 SYM_VER-1

5% F-RT-TH-HF CRITICAL
2 25V TMDS_TX_CONN_P<2>
CERM
402
PP5V_S0_DVIPORT 17
25 1
9
L9407
90-OHM-100MA
68 1210-4SM1
26 2 TMDS_TX_CONN_N<2> TMDS_TX_P<1> 67
2 3
18 10
TMDS_TX_CONN_P<1>
B NC
NC
27
19
3
11 1 4
TMDS_TX_N<1> 67
B
6
28 4 TMDS_TX_CONN_N<1> SYM_VER-1
CRITICAL 20 12
VGA_B
D9400 29 5 TMDS_TX_CONN_P<0> CRITICAL
SC70-6-1 VGA_HSYNC
RCLAMP0504F
68
13 L9406
90-OHM-100MA
30 6 TMDS_TX_CONN_N<0> 1210-4SM1 TMDS_TX_P<0>
1
67
VGA_G 22 14 2 3
68 VGA_VSYNC 31 7 TMDS_TX_CONN_CLK_P
15 TMDS_TX_N<0> 67
for VG signal trace, we need follow NV’s recommendation. So we need change the segment impedance base on NV design guide. 1 4
for A segment: 37.5 ohm from MCP to 150 ohm PD res: Top/bottom layer width is 0.18 mm 32 8 TMDS_TX_CONN_CLK_N SYM_VER-1
for B segment: 50 ohm B/W 2 150 PF res. inner layer width is 0.09 mm top/bottom layer width is 0.115 mm VGA_R 24 16 CRITICAL
for C segment: 75 ohm from FL to connector, top/bottom layer width is 0.076 mm. L9404
300-OHM-100MA
33
34
35
36
1210-4SM TMDS_TX_CLK_P 67
2 3
TMDS_TX_CLK_N 67
1 4
68 9 =GND_CHASSIS_TMDS_UPPER =GND_CHASSIS_TMDS_DOWN 9 SYM_VER-1
FL9400
210MHZ
1 MEA2010P-SM 8
71 18 CRT_IG_R_C_PR 2 7
71 18 CRT_IG_G_Y_Y 3 6
CRT_IG_B_COMP_PB 4 5
A 71 18
R9493 R9494 R9495 R9490 R9491 R9492 PAGE TITLE
2
2
2
2
150
1%
1/16W
150
1%
1/16W
150
1%
1/16W
150
1%
1/16W
150
1%
1/16W
150
1%
1/16W
CRITICAL MINI-DVI CONNECTOR
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF DRAWING NUMBER SIZE
402 402 402 402 402
402

1
1
1
1
REVISION
R
A.0.0
R9493, R9494, R9495 PLACE CLOSE TO U1400 THE INFORMATION CONTAINED HEREIN IS THE
R9490, R9491, R9492 PLACE CLOSE TO FL9400 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
94 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FSB (Front-Side Bus) Constraints CPU / FSB Net Properties
TABLE_PHYSICAL_RULE_HEAD
ALLOW ROUTE NET_TYPE

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
FSB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD
FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_D_L<15..0> 10 14
FSB_DSTB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR FSB_DATA_GROUP0 FSB_50S FSB_DATA FSB_DINV_L<0> 10 14
FSB_DSTB0 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<0> 10 14

TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
FSB_DSTB0 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_N<0> 10 14

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
FSB 4X Signal Groups

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM
FSB_DATA * =2x_DIELECTRIC ? FSB_DATA TOP,BOTTOM =4x_DIELECTRIC ?
FSB_DATA_GROUP1 FSB_50S FSB_DATA FSB_DINV_L<1> 10 14
FSB_DSTB * =3x_DIELECTRIC ? FSB_DSTB TOP,BOTTOM =5x_DIELECTRIC ? FSB_DSTB1 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<1> 10 14
D FSB_ADDR * =STANDARD ?
TABLE_SPACING_RULE_ITEM
FSB_ADDR TOP,BOTTOM =3x_DIELECTRIC ?


D

FSB_ADSTB * =2x_DIELECTRIC ? FSB_ADSTB TOP,BOTTOM =4x_DIELECTRIC ?
FSB_1X * =STANDARD ? FSB_1X TOP,BOTTOM =3x_DIELECTRIC ? FSB_DSTB2 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<2> 10 14

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 4X signals / groups shown in signal table on right.
Signals within each 4x group should be matched within 5 ps of strobe.
FSB_DSTB3 FSB_DSTB_50S FSB_DSTB FSB_DSTB_L_P<3> 10 14
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs. FSB_ADDR_GROUP0 FSB_50S FSB_ADDR FSB_A_L<16..3> 10 14
Signals
FSB_REQ_L<4..0>
FSB 2X
FSB_ADDR_GROUP0 FSB_50S FSB_ADDR 10 14
FSB 2X signals / groups shown in signal table on right.
FSB_ADSTB0 FSB_50S FSB_ADSTB FSB_ADSTB_L<0> 10 14
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#. FSB_ADDR_GROUP1 FSB_50S FSB_ADDR FSB_A_L<35..17> 10 14
FSB_ADSTB1 FSB_50S FSB_ADSTB FSB_ADSTB_L<1> 10 14

FSB 1X signals shown in signal table on right.
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils. FSB_1X FSB_50S FSB_1X FSB_ADS_L 10 14
FSB_BREQ0_L FSB_50S FSB_1X FSB_BREQ0_L 10 14

Design Guide recommends each strobe/signal group is routed on the same layer.
FSB_BREQ1_L FSB_50S FSB_1X FSB_BREQ1_L 14
Intel Design Guide recommends FSB signals be routed only on internal layers.
FSB 1X Signals
FSB_1X FSB_50S FSB_1X FSB_BNR_L 10 14
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened. FSB_1X FSB_50S FSB_1X FSB_BPRI_L 10 14
FSB_1X FSB_50S FSB_1X FSB_DBSY_L 10 14

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
FSB_1X FSB_50S FSB_1X FSB_DEFER_L 10 14
SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
FSB_1X FSB_50S FSB_1X FSB_DRDY_L 10 14
FSB_1X FSB_50S FSB_1X FSB_HIT_L

CPU Signal Constraints FSB_1X FSB_50S FSB_1X FSB_HITM_L
10 14
10 14
ALLOW ROUTE
C PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
FSB_1X
FSB_CPURST_L
FSB_50S
FSB_50S
FSB_1X
FSB_1X
FSB_LOCK_L
FSB_CPURST_L
10 14
10 13 14
C
CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD
FSB_1X FSB_50S FSB_1X FSB_RS_L<2..0> 10 14
CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE 7 MIL 7 MIL FSB_1X FSB_50S FSB_1X FSB_TRDY_L 10 14
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance. CPU_ASYNC CPU_50S CPU_AGTL CPU_A20M_L 10 14
CPU_BSEL CPU_50S CPU_AGTL CPU_BSEL<2..0> 9 10
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT CPU_FERR_L CPU_50S CPU_8MIL CPU_FERR_L 10 14
CPU_ASYNC CPU_50S CPU_AGTL CPU_IGNNE_L 10 14

CPU_AGTL * =STANDARD ? CPU_AGTL TOP,BOTTOM =2x_DIELECTRIC ?
CPU_INIT_L CPU_50S CPU_AGTL CPU_INIT_L 10 14
CPU_8MIL * 8 MIL ? CPU_ASYNC_R CPU_50S CPU_AGTL CPU_INTR 10 14

CPU_ASYNC_R CPU_50S CPU_AGTL CPU_NMI 10 14

CPU_COMP * 25 MIL ?
CPU_PROCHOT_L CPU_50S CPU_AGTL CPU_PROCHOT_L 10 14 42 60
CPU_GTLREF * 25 MIL ? SR DG recommends at least 25 mils, >50 mils preferred CPU_PWRGD CPU_50S CPU_AGTL CPU_PWRGD 10 13 14
CPU_ASYNC CPU_50S CPU_AGTL CPU_SMI_L 10 14
CPU_ITP * =2:1_SPACING ?
CPU_ASYNC CPU_50S CPU_AGTL CPU_STPCLK_L 10 14
CPU_VCCSENSE * 25 MIL ? PM_THRMTRIP_L CPU_50S CPU_8MIL PM_THRMTRIP_L 10 14 42
FSB_CPUSLP_L CPU_50S CPU_AGTL FSB_CPUSLP_L 10 14

Most CPU signals with impedance requirements are 55-ohm single-ended.
CPU_FROM_SB CPU_50S CPU_AGTL CPU_DPSLP_L 10 14
Some signals require 27.4-ohm single-ended impedance.
CPU_DPRSTP_L CPU_50S CPU_AGTL CPU_DPRSTP_L 10 14 60
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 CPU_ASYNC CPU_50S CPU_AGTL FSB_DPWR_L 10 14
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4 MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_BCLK_VML_COMP_VDD 14
MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_BCLK_VML_COMP_GND 14
MCP FSB COMP Signal Constraints MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP_VCC 14
ALLOW ROUTE
MCP_CPU_COMP MCP_50S MCP_FSB_COMP MCP_CPU_COMP_GND 14

FSB_CLK_CPU CLK_FSB_100D CLK_FSB FSB_CLK_CPU_P 10 14

MCP_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD
FSB_CLK_CPU CLK_FSB_100D CLK_FSB FSB_CLK_CPU_N 10 14
B TABLE_SPACING_RULE_HEAD
FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_ITP_P 7 13 14 B
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT FSB_CLK_ITP CLK_FSB_100D CLK_FSB FSB_CLK_ITP_N 7 13 14
FSB_CLK_MCP CLK_FSB_100D CLK_FSB FSB_CLK_MCP_P 14
MCP_FSB_COMP * 8 MIL ?
FSB_CLK_MCP CLK_FSB_100D CLK_FSB FSB_CLK_MCP_N 14
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

CPU_IERR_L CPU_50S CPU_IERR_L 10
FSB Clock Constraints PM_DPRSLPVR CPU_50S CPU_AGTL PM_DPRSLPVR 21 60
ALLOW ROUTE
(See above) CPU_50S CPU_AGTL IMVP_DPRSLPVR 60

CPU_GTLREF CPU_50S CPU_GTLREF CPU_GTLREF 10 27

CLK_FSB_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
CPU_COMP CPU_50S CPU_COMP CPU_COMP<3> 10
CPU_COMP CPU_27P4S CPU_COMP CPU_COMP<2> 10

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT CPU_COMP CPU_50S CPU_COMP CPU_COMP<1> 10
CPU_COMP CPU_27P4S CPU_COMP CPU_COMP<0> 10
CLK_FSB * =3x_DIELECTRIC ? CLK_FSB TOP,BOTTOM =4x_DIELECTRIC ?
XDP_TDI CPU_50S CPU_ITP XDP_TDI 6 7 10 13
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5
XDP_TDO1 CPU_50S CPU_ITP XDP_TDO 6 10
XDP_TMS CPU_50S CPU_ITP XDP_TMS 6 7 10 13
XDP_TCK CPU_50S CPU_ITP XDP_TCK 6 7 10 13
XDP_TRST_L CPU_50S CPU_ITP XDP_TRST_L 6 7 10 13
XDP_BPM_L CPU_50S CPU_ITP XDP_BPM_L<4..0> 7 10 13
XDP_BPM_L5 CPU_50S CPU_ITP XDP_BPM_L<5> 7 10 13
(FSB_CPURST_L) CPU_50S CPU_ITP XDP_CPURST_L 7 13
CPU_50S CPU_8MIL CPU_VID<6..0> 11 60
CPU_50S CPU_8MIL IMVP6_VID<6..0>

CPU_VCCSENSE CPU_27P4S CPU_VCCSENSE CPU_VCCSENSE_P 11 60
A CPU_VCCSENSE
(CPU_VCCSENSE)
CPU_27P4S
CPU_27P4S
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE_N
IMVP6_VSEN_P
11 60
PAGE TITLE
(CPU_VCCSENSE) CPU_27P4S CPU_VCCSENSE IMVP6_VSEN_N
CPU/FSB Constraints
DRAWING NUMBER SIZE

REVISION
R
A.0.0
100 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Memory Bus Constraints Memory Net Properties

MEM_40S * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD
MEM_A_CLK MEM_70D_VDD MEM_CLK MEM_A_CLK_P<5..0> 15 28
MEM_40S_VDD * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD MEM_A_CLK MEM_70D_VDD MEM_CLK MEM_A_CLK_N<5..0> 15 28
MEM_70D * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CKE<3..0> 15 28 30
MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_CS_L<3..0> 15 28 30

MEM_70D_VDD * =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF =70_OHM_DIFF
MEM_A_CNTL MEM_40S_VDD MEM_CTRL MEM_A_ODT<3..0> 15 28 30
TABLE_SPACING_RULE_HEAD
MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_A<14..0> 15 28 30

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_BA<2..0> 15 28 30
D MEM_CLK2MEM * =4:1_SPACING ?
MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_RAS_L 15 28 30 D

MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_CAS_L 15 28 30

MEM_CTRL2CTRL * =2:1_SPACING ?
MEM_A_CMD MEM_40S_VDD MEM_CMD MEM_A_WE_L 15 28 30
MEM_CTRL2MEM * =2.5:1_SPACING ?
MEM_A_DQ_BYTE0 MEM_40S MEM_DATA MEM_A_DQ<7..0> 15 28
MEM_CMD2CMD * =1.5:1_SPACING ? MEM_A_DQ_BYTE1 MEM_40S MEM_DATA MEM_A_DQ<15..8> 15 28

MEM_CMD2MEM * =3:1_SPACING ?
MEM_DATA2DATA * =1.5:1_SPACING ? MEM_A_DQ_BYTE4 MEM_40S MEM_DATA MEM_A_DQ<39..32> 15 28


MEM_DATA2MEM * =3:1_SPACING ?
MEM_DQS2MEM * =3:1_SPACING ? MEM_A_DQ_BYTE7 MEM_40S MEM_DATA MEM_A_DQ<63..56> 15 28

MEM_2OTHER * 25 MIL ? MEM_A_DQ_BYTE0 MEM_40S MEM_DATA MEM_A_DM<0> 15 28
MEM_A_DQ_BYTE1 MEM_40S MEM_DATA MEM_A_DM<1> 15 28
MEM_A_DQ_BYTE2 MEM_40S MEM_DATA MEM_A_DM<2>

Memory Bus Spacing Group Assignments MEM_A_DQ_BYTE3 MEM_40S MEM_DATA MEM_A_DM<3>
15 28
15 28
TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_A_DQ_BYTE4 MEM_40S MEM_DATA MEM_A_DM<4> 15 28
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CLK MEM_CLK * MEM_CLK2MEM MEM_CMD MEM_CLK * MEM_CMD2MEM
MEM_CLK MEM_CTRL * MEM_CLK2MEM MEM_CMD MEM_CTRL * MEM_CMD2MEM MEM_A_DQ_BYTE7 MEM_40S MEM_DATA MEM_A_DM<7> 15 28
MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS_P<0> 15 28
MEM_A_DQS0 MEM_70D MEM_DQS MEM_A_DQS_N<0> 15 28

MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_CMD MEM_DATA * MEM_CMD2MEM
MEM_A_DQS1 MEM_70D MEM_DQS MEM_A_DQS_P<1> 15 28
MEM_CLK MEM_DQS * MEM_CLK2MEM MEM_CMD MEM_DQS * MEM_CMD2MEM MEM_A_DQS1 MEM_70D MEM_DQS MEM_A_DQS_N<1> 15 28

C NET_SPACING_TYPE1
MEM_CTRL
NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
MEM_A_DQS3 MEM_70D MEM_DQS MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
15 28 C
MEM_CLK * MEM_CTRL2MEM MEM_DATA MEM_CLK * MEM_DATA2MEM MEM_A_DQS3 MEM_70D MEM_DQS 15 28

MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL MEM_DATA MEM_CTRL * MEM_DATA2MEM
MEM_CTRL MEM_CMD * MEM_CTRL2MEM MEM_DATA MEM_CMD * MEM_DATA2MEM MEM_A_DQS5 MEM_70D MEM_DQS MEM_A_DQS_P<5> 15 28
MEM_CTRL MEM_DATA * MEM_CTRL2MEM MEM_DATA MEM_DATA * MEM_DATA2DATA
MEM_CTRL MEM_DQS * MEM_CTRL2MEM MEM_DATA MEM_DQS * MEM_DATA2MEM MEM_A_DQS6 MEM_70D MEM_DQS MEM_A_DQS_N<6> 15 28

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
MEM_B_CLK MEM_70D_VDD MEM_CLK MEM_B_CLK_P<5..0> 15 29

MEM_DQS MEM_CLK * MEM_DQS2MEM MEM_CLK * * MEM_2OTHER
MEM_B_CLK MEM_70D_VDD MEM_CLK MEM_B_CLK_N<5..0> 15 29
MEM_DQS MEM_CTRL * MEM_DQS2MEM MEM_CTRL * * MEM_2OTHER

MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_CKE<3..0> 15 29 30
MEM_DQS MEM_CMD * MEM_DQS2MEM MEM_CMD * * MEM_2OTHER MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_CS_L<3..0> 15 29 30

MEM_B_CNTL MEM_40S_VDD MEM_CTRL MEM_B_ODT<3..0> 15 29 30

MEM_DQS MEM_DATA * MEM_DQS2MEM MEM_DATA * * MEM_2OTHER
MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_A<14..0> 15 29 30

MEM_DQS MEM_DQS * MEM_DQS2MEM MEM_DQS * * MEM_2OTHER
MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_BA<2..0> 15 29 30
Need to support MEM_*-style wildcards! MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_RAS_L 15 29 30
DDR2: MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_CAS_L 15 29 30
DQ signals should be matched within 20 ps of associated DQS pair. MEM_B_CMD MEM_40S_VDD MEM_CMD MEM_B_WE_L 15 29 30
DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.

MEM_B_DQ_BYTE0 MEM_40S MEM_DATA MEM_B_DQ<7..0> 15 29
All DQS pairs should be matched within 100 ps of clocks.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
B DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_40S
MEM_40S
MEM_DATA
MEM_DATA
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
15 29
15 29
B
DDR3: MEM_B_DQ_BYTE6 MEM_40S MEM_DATA MEM_B_DQ<55..48> 15 29
DQ signals should be matched within 5 ps of associated DQS pair. MEM_B_DQ_BYTE7 MEM_40S MEM_DATA MEM_B_DQ<63..56> 15 29
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
MEM_B_DQ_BYTE0 MEM_40S MEM_DATA MEM_B_DM<0> 15 29
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
A/BA/cmd signals should be matched within 5 ps of CLK pairs.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 MEM_B_DQ_BYTE6 MEM_40S MEM_DATA MEM_B_DM<6> 15 29
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2 MEM_B_DQ_BYTE7 MEM_40S MEM_DATA MEM_B_DM<7> 15 29
MEM_B_DQS0 MEM_70D MEM_DQS MEM_B_DQS_P<0>

MCP MEM COMP Signal Constraints MEM_B_DQS0 MEM_70D MEM_DQS MEM_B_DQS_N<0>
15 29
15 29
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_B_DQS1 MEM_70D MEM_DQS MEM_B_DQS_P<1> 15 29
ON LAYER?
MEM_B_DQS1 MEM_70D MEM_DQS MEM_B_DQS_N<1> 15 29

MCP_MEM_COMP * Y 7 MIL 7 MIL =STANDARD =STANDARD =STANDARD
MEM_B_DQS2 MEM_70D MEM_DQS MEM_B_DQS_P<2> 15 29
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MEM_B_DQS3 MEM_70D MEM_DQS MEM_B_DQS_P<3> 15 29


MCP_MEM_COMP * 8 MIL ?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4 MEM_B_DQS4 MEM_70D MEM_DQS MEM_B_DQS_N<4> 15 29
A MEM_B_DQS6
MEM_B_DQS7
MEM_70D
MEM_70D
MEM_DQS
MEM_DQS
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
15 29
15 29
PAGE TITLE
Memory Constraints
MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_VDD 16 DRAWING NUMBER SIZE
MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP_GND 16
REVISION
R
A.0.0
101 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI-Express

PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
PCIE_90D PCIE PEG_R2D_P<15..0>
CLK_PCIE_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF PCIE_90D PCIE PEG_R2D_N<15..0>
PEG_R2D PCIE_90D PCIE PEG_R2D_C_P<15..0>
PEG_R2D PCIE_90D PCIE PEG_R2D_C_N<15..0>
PEG_D2R PCIE_90D PCIE PEG_D2R_P<15..0>
PCIE * =3X_DIELECTRIC ? PCIE TOP,BOTTOM =4X_DIELECTRIC ? PCIE_90D PCIE PEG_D2R_N<15..0>

PCIE_90D PCIE PEG_D2R_C_P<15..0>

CLK_PCIE * 20 MIL ?
PCIE_90D PCIE PEG_D2R_C_N<15..0>
D MCP_PEX_COMP * 8 MIL ?
PCIE_90D PCIE PCIE_MINI_R2D_P 7 31

D
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4 PCIE_90D PCIE PCIE_MINI_R2D_N 7 31
PCIE_MINI_R2D PCIE_90D PCIE PCIE_MINI_R2D_C_P 17 31
Analog Video Signal Constraints PCIE_90D PCIE PCIE_MINI_R2D_C_N 17 31

PCIE_MINI_D2R PCIE_90D PCIE PCIE_MINI_D2R_P 7 17 31

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? PCIE_90D PCIE PCIE_MINI_D2R_N 7 17 31
CRT_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD

PCIE_90D PCIE PCIE_FW_R2D_P 35
TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
PCIE_90D PCIE PCIE_FW_R2D_N 35
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET PCIE_FW_R2D PCIE_90D PCIE PCIE_FW_R2D_C_P 17 35
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
PCIE_90D PCIE PCIE_FW_R2D_C_N 17 35

CRT * =4:1_SPACING ? CRT CRT * CRT_2CRT
PCIE_FW_D2R PCIE_90D PCIE PCIE_FW_D2R_P 17 35
CRT_2CRT * =STANDARD ? PCIE_90D PCIE PCIE_FW_D2R_N 17 35

PCIE_90D PCIE PCIE_FW_D2R_C_P 35

CRT_2CLK * 50 MIL ?
PCIE_90D PCIE PCIE_FW_D2R_C_N 35
CRT_2SWITCHER * 250 MIL ?

PCIE_90D PCIE PCIE_EXCARD_R2D_P
CRT_SYNC * 16 MIL ? PCIE_90D PCIE PCIE_EXCARD_R2D_N

PCIE_EXCARD_R2D PCIE_90D PCIE PCIE_EXCARD_R2D_C_P 9 17

MCP_DAC_COMP * =2:1_SPACING ?
PCIE_90D PCIE PCIE_EXCARD_R2D_C_N 9 17
CRT signal single-ended impedence varies by location: PCIE_EXCARD_D2R PCIE_90D PCIE PCIE_EXCARD_D2R_P 9 17
- 37.5-ohm from MCP to first termination resistor. PCIE_90D PCIE PCIE_EXCARD_D2R_N 9 17
- 50-ohm from first to second termination resistor.

MCP_PE0_REFCLK CLK_PCIE_100D CLK_PCIE PEG_CLK100M_P 9 17
- 75-ohm from output of three-pole filter to connector (if possible).
CLK_PCIE_100D CLK_PCIE PEG_CLK100M_N 9 17
R/G/B signals should be matched as close as possible and < 10 inches.
MCP_PE1_REFCLK CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_P 7 17 31
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_N 7 17 31
C Digital Video Signal Constraints

MCP_PE2_REFCLK CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE
CLK_PCIE
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
17 35
17 35
C
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MCP_PE3_REFCLK CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_EXCARD_P 9 17
ON LAYER?
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_EXCARD_N 9 17
DP_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
MCP_PEX_CLK_COMP MCP_PEX_COMP MCP_PEX_CLK_COMP 17
LVDS_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

CRT_RED CRT_MCP_P CRT CRT_IG_R_C_PR 18 68
MCP_DV_COMP * Y 20 MIL 20 MIL =STANDARD =STANDARD =STANDARD CRT_GREEN CRT_MCP_P CRT CRT_IG_G_Y_Y 18 68
CRT_BLUE CRT_MCP_P CRT CRT_IG_B_COMP_PB 18 68

CRT_SYNC CRT_50S CRT_SYNC CRT_IG_HSYNC 18 68

CRT_SYNC CRT_50S CRT_SYNC CRT_IG_VSYNC 18 68
DISPLAYPORT * =3x_DIELECTRIC ? DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? MCP_DAC_RSET MCP_DAC_COMP MCP_TV_DAC_RSET 9 18

MCP_DAC_VREF MCP_DAC_COMP MCP_TV_DAC_VREF 9 18

LVDS * =3x_DIELECTRIC ? LVDS TOP,BOTTOM =4x_DIELECTRIC ?
TMDS_IG_TXC DP_100D DISPLAYPORT TMDS_IG_TXC_P
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
TMDS_IG_TXC DP_100D DISPLAYPORT TMDS_IG_TXC_N
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
TMDS_IG_TXD DP_100D DISPLAYPORT TMDS_IG_TXD_P<2..0>
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
TMDS_IG_TXD DP_100D DISPLAYPORT TMDS_IG_TXD_N<2..0>
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4. DP_ML DP_100D DISPLAYPORT DP_IG_ML_P<3..0>
DP_ML DP_100D DISPLAYPORT DP_IG_ML_N<3..0>
SATA Interface Constraints DP_AUX_CH DP_100D DISPLAYPORT TP_DP_IG_AUX_CH_P
DP_AUX_CH DP_100D DISPLAYPORT TP_DP_IG_AUX_CH_N

ON LAYER?
MCP_HDMI_RSET MCP_DV_COMP MCP_HDMI_RSET 18 25

SATA_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
MCP_HDMI_VPROBE MCP_DV_COMP MCP_HDMI_VPROBE 18 25
SATA_100D_HDD * =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD =100_OHM_DIFF_HDD

LVDS_IG_A_CLK LVDS_100D LVDS LVDS_IG_A_CLK_P 18 66
LVDS_IG_A_CLK LVDS_100D LVDS LVDS_IG_A_CLK_N 18 66

B SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

LVDS_IG_A_DATA
LVDS_IG_A_DATA
LVDS_100D
LVDS_100D
LVDS
LVDS
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
7 18 66
7 18 66
B
SATA * =4x_DIELECTRIC ? SATA TOP,BOTTOM =3x_DIELECTRIC ?
LVDS_IG_A_DATA3 LVDS_100D LVDS LVDS_IG_A_DATA_P<3> 9 18
SATA_TERMP * 8 MIL ? LVDS_IG_A_DATA3 LVDS_100D LVDS LVDS_IG_A_DATA_N<3> 9 18
LVDS_IG_B_CLK LVDS_100D LVDS LVDS_IG_B_CLK_P 9 18

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
LVDS_IG_B_CLK LVDS_100D LVDS LVDS_IG_B_CLK_N 9 18
LVDS_IG_B_DATA LVDS_100D LVDS LVDS_IG_B_DATA_P<2..0> 9 18
LVDS_IG_B_DATA LVDS_100D LVDS LVDS_IG_B_DATA_N<2..0> 9 18
LVDS_IG_B_DATA3 LVDS_100D LVDS LVDS_IG_B_DATA_P<3> 9 18
LVDS_IG_B_DATA3 LVDS_100D LVDS LVDS_IG_B_DATA_N<3> 9 18
MCP_IFPAB_RSET MCP_DV_COMP MCP_IFPAB_RSET 18 25
MCP_IFPAB_VPROBE MCP_IFPAB_VPROBE 18 25
SATA_HDD_R2D SATA_100D_HDD SATA SATA_HDD_R2D_C_P 20 38
SATA_100D_HDD SATA SATA_HDD_R2D_C_N 20 38
SATA_100D_HDD SATA SATA_HDD_R2D_P 7 38
SATA_100D_HDD SATA SATA_HDD_R2D_N 7 38
SATA_100D_HDD SATA SATA_HDD_R2D_UF_P 38
SATA_100D_HDD SATA SATA_HDD_R2D_UF_N 38
SATA_HDD_D2R SATA_100D_HDD SATA SATA_HDD_D2R_P 20 38
SATA_100D_HDD SATA SATA_HDD_D2R_N 20 38
SATA_100D_HDD SATA SATA_HDD_D2R_C_P 7 38
SATA_100D_HDD SATA SATA_HDD_D2R_C_N 7 38
SATA_ODD_R2D SATA_100D SATA SATA_ODD_R2D_C_P 20 38
A SATA_100D
SATA_100D
SATA
SATA
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
20 38
38
PAGE TITLE
SATA_100D
SATA_100D
SATA
SATA
SATA_ODD_R2D_N
SATA_ODD_R2D_UF_P
38
7 38
MCP Constraints 1
DRAWING NUMBER SIZE
SATA_100D SATA SATA_ODD_R2D_UF_N 7 38
SATA_ODD_D2R SATA_100D SATA SATA_ODD_D2R_P 20 38 Apple Inc. 051-8089 D

REVISION
SATA_100D SATA SATA_ODD_D2R_N
SATA_100D SATA SATA_ODD_D2R_C_P
20 38
7 38
R
A.0.0
SATA_ODD_D2R_C_N
SATA_100D SATA 7 38
SATA_100D SATA SATA_ODD_D2R_UF_P 38 PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.
SATA_100D SATA SATA_ODD_D2R_UF_N 38
102 OF 109
MCP_SATA_TERMP SATA_TERMP MCP_SATA_TERMP 20 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCI Bus Constraints

PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
MCP_DEBUG PCI_55S PCI MCP_DEBUG<7..0> 7 13 19
CLK_PCI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCI_AD PCI_55S PCI PCI_AD<23..8>
PCI_AD24 PCI_55S PCI PCI_AD<24>
PCI_AD PCI_55S PCI PCI_AD<31..25>

PCI_AD PCI_55S PCI PCI_PAR
PCI * =STANDARD ? PCI_C_BE_L PCI_55S PCI PCI_C_BE_L<3..0>

PCI_CNTL PCI_55S PCI PCI_IRDY_L

CLK_PCI * 8 MIL ?
PCI_CNTL PCI_55S PCI PCI_DEVSEL_L
D SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

PCI_CNTL PCI_55S PCI PCI_PERR_L D
PCI_CNTL PCI_55S PCI PCI_SERR_L
PCI_CNTL PCI_55S PCI PCI_STOP_L
LPC Bus Constraints PCI_CNTL PCI_55S PCI PCI_TRDY_L
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCI_CNTL PCI_55S PCI PCI_FRAME_L
ON LAYER?
PCI_REQ0_L PCI_55S PCI PCI_REQ0_L 19

LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
PCI_GNT0_L PCI_55S PCI PCI_GNT0_L
CLK_LPC_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCI_REQ1_L PCI_55S PCI PCI_REQ1_L 19
PCI_GNT1_L PCI_55S PCI PCI_GNT1_L

PCI_INTW_L PCI_55S PCI PCI_INTW_L

PCI_INTX_L PCI_55S PCI PCI_INTX_L
LPC * 6 MIL ? PCI_INTY_L PCI_55S PCI PCI_INTY_L

PCI_INTZ_L PCI_55S PCI PCI_INTZ_L
CLK_LPC * 8 MIL ?
MCP_PCI_CLK2 CLK_PCI_55S CLK_PCI PCI_CLK33M_MCP_R 19
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1. CLK_PCI_55S CLK_PCI PCI_CLK33M_MCP 19
LPC_AD LPC_55S LPC LPC_AD<3..0>

USB 2.0 Interface Constraints LPC_FRAME_L0 LPC_55S LPC LPC_FRAME_L
7 19 41 43
7 19 41 43
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP LPC_RESET_L LPC_55S LPC LPC_RESET_L 19 26
ON LAYER?
MCP_USB_RBIAS * =STANDARD 8 MIL 8 MIL =STANDARD =STANDARD =STANDARD MCP_LPC_CLK CLK_LPC_55S CLK_LPC LPC_CLK33M_SMC_R 19 26
MCP_LPC_CLK CLK_LPC_55S CLK_LPC LPC_CLK33M_SMC 26 41

USB_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
MCP_LPC_CLK CLK_LPC_55S CLK_LPC LPC_CLK33M_LPCPLUS 7 26 43
USB_EXTA USB_90D USB USB_EXTA_P 20 39

USB_EXTA USB_90D USB USB_EXTA_N 20 39
USB * =2x_DIELECTRIC ? USB TOP,BOTTOM =4x_DIELECTRIC ? USB_EXTA USB_90D USB USB2_EXTA_MUXED_P 39
C SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1. I188

USB_EXTA
USB_EXTA
USB_90D
USB_90D
USB
USB
USB2_EXTA_MUXED_N
USB2_EXTA_F_P
39
39
C
I185
USB_EXTA USB_90D USB USB2_EXTA_F_N 39
SMBus Interface Constraints USB_MINI USB_90D USB USB_MINI_P 9 20
ALLOW ROUTE
USB_MINI USB_90D USB USB_MINI_N 9 20
I190 USB_MINI USB_90D USB USB2_AIRPORT_P 7 31
SMB_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD I189

USB_MINI USB_90D USB USB2_AIRPORT_N 7 31
USB_EXTD USB_90D USB USB_EXTD_P 9 20

USB_90D USB USB_EXTD_N 9 20

USB_CAMERA USB_90D USB USB_CAMERA_P 20 66
SMB * =2x_DIELECTRIC ? USB_CAMERA USB_90D USB USB_CAMERA_N 20 66

USB_CAMERA USB_90D USB USB2_CAMERA_CONN_P 7 66
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1. I183 USB_CAMERA USB_90D USB USB2_CAMERA_CONN_N 7 66
USB_IR USB_90D USB USB_IR_P 20 40
HD Audio Interface Constraints USB_IR USB_90D USB USB_IR_N 20 40
ALLOW ROUTE
USB_TPAD USB_90D USB USB_TPAD_P 9 20

USB_TPAD USB_90D USB USB_TPAD_N 9 20
HDA_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_TPAD USB_90D USB CONN_TPAD_USB_P
I187 7 49
I186
USB_TPAD USB_90D USB CONN_TPAD_USB_N 7 49
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT USB_BT USB_90D USB USB_BT_P 9 20

USB_BT USB_90D USB USB_BT_N 9 20
HDA * =2x_DIELECTRIC ?
I194 USB_BT USB_90D USB USB2_BT_F_P_CONN 7 40
MCP_HDA_COMP * 8 MIL ? USB_BT USB_90D USB USB2_BT_F_N_CONN
I193 7 40
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1. USB_EXTB USB_90D USB USB_EXTB_P 20 39
USB_EXTB USB_90D USB USB_EXTB_N 20 39
B SIO Signal Constraints I192

USB_EXTB USB_90D USB USB2_EXTB_F_P 39 B
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP I191
USB_EXTB USB_90D USB USB2_EXTB_F_N 39
ON LAYER?
CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD USB_EXCARD USB_90D USB USB_EXCARD_P 9 20
USB_90D USB USB_EXCARD_N 9 20

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT USB_EXTC USB_90D USB USB_EXTC_P 9 20

I184 USB_90D USB USB_EXTC_N 9 20

CLK_SLOW * 8 MIL ?
MCP_USB_RBIAS MCP_USB_RBIAS MCP_USB_RBIAS_GND 20
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.

SMBUS_MCP_0_CLK SMB_55S SMB SMBUS_MCP_0_CLK 7 13 21 44
SPI Interface Constraints SMBUS_MCP_0_DATA SMB_55S SMB SMBUS_MCP_0_DATA 7 13 21 44
ALLOW ROUTE
SMBUS_MCP_1_CLK SMB_55S SMB SMBUS_MCP_1_CLK 21 44

SMBUS_MCP_1_DATA SMB_55S SMB SMBUS_MCP_1_DATA 21 44
SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD HDA_BIT_CLK HDA_55S HDA HDA_BIT_CLK 21 52
HDA_55S HDA HDA_BIT_CLK_R 21

HDA_SYNC HDA_55S HDA HDA_SYNC 21 52

HDA_55S HDA HDA_SYNC_R 21
SPI * 8 MIL ? HDA_RST_L HDA_55S HDA HDA_RST_R_L 21
HDA_55S HDA HDA_RST_L 21 52
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14. HDA_SDIN0 HDA_55S HDA HDA_SDIN0 21 52
HDA_55S HDA HDA_SDIN_CODEC

HDA_SDOUT HDA_55S HDA HDA_SDOUT 21 52
HDA_55S HDA HDA_SDOUT_R 21
MCP_HDA_PULLDN_COMP MCP_HDA_COMP MCP_HDA_PULLDN_COMP 21
A MCP_SUS_CLK CLK_SLOW_55S
CLK_SLOW_55S
CLK_SLOW
CLK_SLOW
PM_CLK32K_SUSCLK_R
PM_CLK32K_SUSCLK
21 26
26 41
PAGE TITLE
SPI_CLK SPI_55S SPI SPI_CLK_R
SPI_CLK_MUX
21 43 MCP Constraints 2
SPI_55S SPI 43 51 DRAWING NUMBER SIZE
SPI_MOSI SPI_55S SPI SPI_MOSI_R 21 43
SPI_55S SPI SPI_MOSI_MUX 43 51 REVISION
SPI_MISO SPI_55S SPI SPI_MISO_MUX 43 51
R
A.0.0
SPI_55S SPI SPI_MISO_R 51 NOTICE OF PROPRIETARY PROPERTY: BRANCH
SPI_CS0 SPI_55S SPI SPI_CS0_R_L 21 43 THE INFORMATION CONTAINED HEREIN IS THE
SPI_55S SPI SPI_CS0_L THE POSESSOR AGREES TO THE FOLLOWING: PAGE
103 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MCP RGMII (Ethernet) Constraints

MCP_MII_COMP * =STANDARD 7.5 MIL 7.5 MIL =STANDARD =STANDARD =STANDARD
MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP_VDD 18
ENET_MII_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD MCP_MII_COMP MCP_MII_COMP MCP_MII_COMP_GND 18
MCP_CLK25M_BUF0 ENET_MII_55S MCP_BUF0_CLK MCP_CLK25M_BUF0_R 18 33

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT ENET_MII_55S MCP_BUF0_CLK MCP_CLK25M_BUF0

MCP_BUF0_CLK * =3:1_SPACING ? ENET_INTR_L ENET_MII_55S ENET_MII ENET_INTR_L

ENET_MDIO ENET_MII_55S ENET_MII ENET_MDIO 18 32

ENET_MII * 12 MIL ?
ENET_MDC ENET_MII_55S ENET_MII ENET_MDC 18 32
D SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

ENET_PWRDWN_L ENET_MII_55S ENET_MII ENET_PWRDWN_L D
ENET_RXCLK ENET_MII_55S ENET_MII ENET_CLK125M_RXCLK 18 32
88E1116R (Ethernet PHY) Constraints ENET_MII_55S ENET_MII ENET_CLK125M_RXCLK_R 32

ENET_RXD_STRAP ENET_MII_55S ENET_MII ENET_RXD<3..1> 18 32

ON LAYER? ENET_RXD ENET_MII_55S ENET_MII ENET_RX_CTRL 18 32
ENET_MDI_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

ENET_TXCLK ENET_MII_55S ENET_MII ENET_CLK125M_TXCLK 18 32
ENET_MII_55S ENET_MII ENET_CLK125M_TXCLK_R 32
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT ENET_TXD0 ENET_MII_55S ENET_MII ENET_TXD<0> 18 32

ENET_TXD ENET_MII_55S ENET_MII ENET_TXD<3..1> 18 32

ENET_MDI * 25 MIL ?
ENET_TXD ENET_MII_55S ENET_MII ENET_TX_CTRL 18 32
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4 ENET_MII_55S ENET_MII ENET_RESET_L 18 32
ENET_MDI ENET_MDI_100D ENET_MDI ENET_MDI_P<3..0> 32 34
ENET_MDI_100D ENET_MDI ENET_MDI_N<3..0> 32 34
C C
B B
PAGE TITLE
Ethernet Constraints
DRAWING NUMBER SIZE

REVISION
R
A.0.0
104 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FireWire Interface Constraints FireWire Net Properties

FW_110D * =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF
FW_P0_TPA FW_110D FW_TP FW_P0_TPA_P 35 37
FW_P0_TPA FW_110D FW_TP FW_P0_TPA_N 35 37

SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT FW_P0_TPB FW_110D FW_TP FW_P0_TPB_P 35 37

FW_P0_TPB FW_110D FW_TP FW_P0_TPB_N 35 37

FW_TP * =3:1_SPACING ?
FW_P1_TPA FW_110D FW_TP FW_P1_TPA_P 35 37
FW_P1_TPA FW_110D FW_TP FW_P1_TPA_N 35 37
FW_P1_TPB FW_110D FW_TP FW_P1_TPB_P 35 37
FW_P1_TPB FW_110D FW_TP FW_P1_TPB_N 35 37
D FW_P1_TPA FW_110D FW_TP FW_PORT_A_P 37 D

FW_P1_TPA FW_110D FW_TP FW_PORT_A_N 37
FW_P1_TPB FW_110D FW_TP FW_PORT_B_P 37
FW_P1_TPB FW_110D FW_TP FW_PORT_B_N 37
Port 2 Not Used
C C
B B
PAGE TITLE
FireWire Constraints
DRAWING NUMBER SIZE

REVISION
R
A.0.0
105 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SMC SMBus Net Properties

1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM
SMBUS_SMC_A_S3_SCL SMB_55S SMB SMBUS_SMC_A_S3_SCL 44
SMBUS_SMC_A_S3_SDA SMB_55S SMB SMBUS_SMC_A_S3_SDA 44
SMBUS_SMC_B_S0_SCL SMB_55S SMB SMBUS_SMC_B_S0_SCL 44
SMBUS_SMC_B_S0_SDA SMB_55S SMB SMBUS_SMC_B_S0_SDA 44
SMBUS_SMC_0_S0_SCL SMB_55S SMB SMBUS_SMC_0_S0_SCL 44
SMBUS_SMC_0_S0_SDA SMB_55S SMB SMBUS_SMC_0_S0_SDA 44
SMBUS_SMC_BSA_SCL SMB_55S SMB SMBUS_SMC_BSA_SCL 44
SMBUS_SMC_BSA_SDA SMB_55S SMB SMBUS_SMC_BSA_SDA 44
D SMBUS_SMC_MGMT_SCL SMB_55S SMB SMBUS_SMC_MGMT_SCL 44 D

SMBUS_SMC_MGMT_SDA SMB_55S SMB SMBUS_SMC_MGMT_SDA 44
SMBus Charger Net Properties

NET_TYPE
CHGR_CSI 1TO1_DIFFPAIR CHGR_CSI_P

1TO1_DIFFPAIR CHGR_CSI_N
CHGR_CSO 1TO1_DIFFPAIR CHGR_CSO_P

1TO1_DIFFPAIR CHGR_CSO_N
C C
B B
PAGE TITLE
SMC Constraints
DRAWING NUMBER SIZE

REVISION
R
A.0.0
106 OF 109
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
K36B BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS
TABLE_BOARD_INFO
BOARD LAYERS BOARD AREAS BOARD UNITS ALLEGRO TABLE_SPACING_RULE_HEAD TABLE_SPACING_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_HEAD
(MIL or MM) VERSION SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA_P1MM MM 15.5.1

DEFAULT * 0.1 MM ? * * BGA_P1MM BGA_P1MM MEM_40S BGA_P1MM STANDARD
TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM
ALLOW ROUTE
STANDARD * =DEFAULT ? MEM_CLK * BGA_P1MM BGA_P2MM MEM_40S_VDD BGA_P1MM STANDARD

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
BGA_P1MM * =DEFAULT ? CLK_FSB * BGA_P1MM BGA_P2MM

DEFAULT * Y =50_OHM_SE =50_OHM_SE 30 MM 0 MM 0 MM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
BGA_P2MM * =DEFAULT ? CLK_LPC * BGA_P1MM BGA_P2MM
STANDARD * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
BGA_P3MM * =DEFAULT ? CLK_PCI * BGA_P1MM BGA_P2MM

TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_ASSIGNMENT_ITEM
D PHYSICAL_RULE_SET LAYER ALLOW ROUTE

ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP

CLK_PCIE * BGA_P1MM BGA_P2MM
D
55_OHM_SE TOP,BOTTOM Y 0.090 MM 0.090 MM TABLE_SPACING_RULE_ITEM
CLK_SLOW * BGA_P1MM BGA_P2MM
1.5:1_SPACING * 0.15 MM ? TABLE_SPACING_ASSIGNMENT_ITEM
55_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM

FSB_DSTB FSB_DSTB BGA_P1MM BGA_P3MM
2:1_SPACING * 0.2 MM ?
TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 2.5:1_SPACING * 0.25 MM ?
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM
50_OHM_SE TOP,BOTTOM Y 0.115 MM 0.115 MM 3:1_SPACING * 0.3 MM ?

50_OHM_SE * Y 0.090 MM 0.090 MM =STANDARD =STANDARD =STANDARD 4:1_SPACING * 0.4 MM ?
TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_HEAD
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
ON LAYER?
40_OHM_SE TOP,BOTTOM Y 0.165 MM 0.165 MM 2X_DIELECTRIC TOP,BOTTOM 0.140 MM ?

40_OHM_SE * Y 0.145 MM 0.145 MM =STANDARD =STANDARD =STANDARD 3X_DIELECTRIC TOP,BOTTOM 0.210 MM ?

4X_DIELECTRIC TOP,BOTTOM 0.280 MM ?
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM
ON LAYER? 5X_DIELECTRIC TOP,BOTTOM 0.350 MM ?

27P4_OHM_SE TOP,BOTTOM Y 0.310 MM 0.310 MM TABLE_SPACING_RULE_ITEM
2X_DIELECTRIC * 0.152 MM ?
27P4_OHM_SE * Y 0.275 MM 0.275 MM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM
ALLOW ROUTE
70_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

C 70_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.175 MM 0.175 MM 0.200 MM 0.200 MM

C
70_OHM_DIFF TOP,BOTTOM Y 0.185 MM 0.185 MM 0.200 MM 0.200 MM
ON LAYER?

90_OHM_DIFF ISL3,ISL4,ISL9,ISL10 Y 0.109 MM 0.109 MM 0.220 MM 0.220 MM

ON LAYER?


ON LAYER?
100_OHM_DIFF_HDD * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

100_OHM_DIFF_HDD ISL3,ISL4,ISL9,ISL10 Y 0.095 MM 0.095 MM 0.400 MM 0.400 MM

100_OHM_DIFF_HDD TOP,BOTTOM Y 0.095 MM 0.095 MM 0.400 MM 0.400 MM
ON LAYER?
B 110_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD

B
ON LAYER?
1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM
PAGE TITLE
K36B RULE DEFINITIONS

DRAWING NUMBER SIZE

REVISION
R
A.0.0
109 OF 109
8 7 6 5 4 3 2 1

K36C MLB schematic overview

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

K36C MLB schematic overview

Uploaded by

Copyright:

Available Formats

8 7 6 5 4 3 2 1

Page Contents Page

Schematic / PCB #’s SCHEM,MLB,K36C

Apple Inc. 051-8089 D

SATA SPI FAN CONN AND CONTROL

Conn 3GHZ. SATA MCP79 SMC Prt

CONN LVDS OUT CTRL

J4810 J5800 J4501 J9001 J4600,4601

DP OUT TRACKPAD/ EXTERNAL

CONN DVI OUT

J4300 U6801 U6801 U6610,6620,6630

Apple Inc. 051-8089 D

MINI PCI-E J6800,6801,6802,6803

K36C POWER SYSTEM ARCHITECTURE D6905

SLP_S3# 15 U4900 04-1 Q7800 ENTRIP1 VIN

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

341S2420 1 IC,SMC,HS8/2117,9X9MM,TLP,HF,BLANK U4900 CRITICAL SMC_PROG

341S2418 1 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM_PROG

341S2093 1 IC, CYPRESS, CY7C63833 U4800 CRITICAL

338S0654 1 IC,FW643E,1394B PHY/OHCI LINK/PCI-E,127 U4100 CRITICAL

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

826-4393 1 LBL,P/N LABEL,PCB,28MMX6MM [EEE:9WN] CRITICAL TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

TABLE_5_HEAD 128S0093 128S0218 ALL ALTERNATE PER CYNDI

152S0847 152S0586 ALL ALTERNATE PER CYNDI

152S0874 152S0516 ALL ALTERNATE PER CYNDI

C 338S0702 1 IC,GMCP,MCP79,35X35MM,BGA1437,B03 U1400 CRITICAL 152S0778

ALTERNATE PER CYNDI

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

514-0665 1 CONN,RCPT,MINI-DVI,32P,R/A J9401 CRITICAL

514-0666 1 CONN,RCPT,3.5MM AUDIO IN,R/A J6750 CRITICAL

514-0667 1 CONN,RCPT,3.5MM AUDIO OUT,R/A J6700 CRITICAL

514-0668 1 CONN,RCPT,RJ45,NO FILTER,8P J3900 CRITICAL

514-0669 1 CONN,RCPT,USB,4P,MIDPLANE J4600 CRITICAL

514-0669 1 CONN,RCPT,USB,4P,MIDPLANE J4601 CRITICAL

10 SIGNAL(High Speed) CONFIGURATION OPTIONS

11 GROUND Apple Inc. 051-8089

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

R06021 69 13 10 7 6 XDP_TMS 4 A3 B3 8 JTAG_MCP_TMS MAKE_BASE=TRUE 7 13 21

JTAG Scan Chain

Apple Inc. 051-8089 D

Functional Test Points

I228 TRUE PP5VRT_S0

TRUE SMBUS_BATT_SCL_F 56 I277 TRUE PP5V_S3_IR_CONN 38 TRUE TP_XDP_OBSFN_B1 13 I221 TRUE 19 41 43

TRUE TRUE SMC_TRST_L

TRUE TRUE SMC_MD1

TRUE GND Need 6 TP I273 TRUE PCIE_CLK100M_MINI_N 17 31 71

PCIE_MINI_R2D_N TRUE SPIROM_USE_MLB

TRUE PCIE_MINI_R2D_P XDP_TCK TRUE SPI_ALT_CLK

TRUE PP3V3_WLAN Need 4 TP 31 PPCPUVTT_S0 TRUE SPI_ALT_CS_L

#J9000 INVERTER Connector I266 TRUE PP1V5_S0_R Need 3 TP 7 8

MINI_RESET TRUE LPC_PWRDWN_L

PP3V3_S3_AIRPORT_CONN TRUE SMC_TDI

TRUE I2C_MINI_PCIE_SCL TRUE SMC_TCK

TRUE I2C_MINI_PCIE_SDA TRUE MCP_DEBUG<1> TRUE SMC_RESET_L

TRUE USB2_AIRPORT_N TRUE SMC_NMI

C I300 TRUE PP3V3_LCDVDD_SW_F 66 I260 TRUE GND Need 6 TP

I172 TRUE JTAG_MCP_TDI

I302 TRUE LVDS_IG_DDC_DATA 18 66 I258 TRUE ALL_SYS_PWRGD 26 41 64 I169 TRUE MCP_DEBUG<5> 13 19 72

I305 TRUE LVDS_IG_A_DATA_N<0> 18 66 71 I256 TRUE PPVCORE_S0_CPU 8 I168 TRUE MCP_DEBUG<6> 13 19 72

I304 TRUE LVDS_IG_A_DATA_P<0> 18 66 71 I257 TRUE PPCPUVTT_S0 7 8 I167 TRUE MCP_DEBUG<7> 13 19 72

I306 TRUE LVDS_IG_A_DATA_N<1> 18 66 71 I255 TRUE PPVCORE_S0_MCP_R 8 I165 TRUE FSB_CLK_ITP_P 13 14 69