Sualaptop365.edu - VN - X200 - MLB - C1 051-0886 Ra00

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
MLB-C1
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
SCH AND BOARD PART NUMBERS

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
TABLE_5_HEAD
X200 LAST_MODIFIED=Tue Oct 29 15:52:27 2013
A 0002535199 PRODUCTION RELEASED
DATE
2014-01-13
PDF CSA CONTENTS

TABLE_5_ITEM
051-0886 1 SCH,MLB-C1,X200 SCH1 SYNC MASTER DATE

D
TABLE_5_ITEM
TABLE_TABLEOFCONTENTS_HEAD
D 820-4124 1 PCBF,MLB-C1,X200 PCB1

21 27 SENSOR: ACCEL, COMPASS, GYRO
TABLE_TABLEOFCONTENTS_ITEM
N/A N/A
22 28 SENSOR: PROX
J85 MLB_C
12/05/12
23 29 CAMERA: REAR CONN & FILTERS

N/A N/A
24 30 CELL:AP INTERFACE & DEBUG CONNECTORS

RADIO_MLB_87
10/29/2013
25 32 CELL: BASEBAND PMU (1 0F 2)

RADIO_MLB_87
10/29/2013
26 33 CELL: BASEBAND PMU (2 OF 2)

RADIO_MLB_87
10/29/2013
27 34 CELL: BASEBAND (1 OF 2)
RADIO_MLB_87
10/29/2013
PDF CSA CONTENTS SYNC MASTER DATE

28 35 CELL: BASEBAND (2 OF 2)
RADIO_MLB_87
10/29/2013
TABLE_TABLEOFCONTENTS_HEAD
29 36 CELL: RF TRANSCEIVER (1 0F 2) RADIO_MLB_87

10/29/2013
1
1 TABLE OF CONTENTS N/A N/A
30 37 CELL: RF TRANSCEIVER (2 OF 2) RADIO_MLB_87

10/29/2013
2
2 BLOCK DIAGRAM: SYSTEM J85_MLB_B
04/02/2013 31 38 CELL: RX MATCHING RADIO_MLB_87
10/29/2013
3 4 BOM TABLES J72_MLB_C

11/26/2012 32 39 CELL: RF TRANSCEIVER (3 OF 4)
RADIO_MLB_87
10/29/2013
4 6 SOC: MAIN N/A 04/18/2011

33 40 CELL: PENTABAND PA
RADIO_MLB_87
10/29/2013
C
34 41 CELL: BAND 2/3 PAD RADIO_MLB_87

10/29/2013 C
5
7 SOC: I/OS N/A 05/05/2011
35 42 CELL: BAND 7/20 PAD RADIO_MLB_87

10/29/2013
6
8 SOC: NAND N/A 04/18/2011 36 43 CELL: BAND 5/8 PAD RADIO_MLB_87
10/29/2013
7 9 SOC: DP,MIPI MLB 05/04/2012 37 44 CELL: 2G PA

RADIO_MLB_87
10/29/2013
38 45 CELL: PA DCDC CONVERTER RADIO_MLB_87

10/29/2013
8 10 SOC: SRAM, IO PWRS N/A 04/18/2011 TABLE_TABLEOFCONTENTS_ITEM
39 46 CELL: ASM AND HB LTE FRONT-END RADIO_MLB_87

10/29/2013
9
11 SOC: VDD, SRAM, CPU, GPU PWRS N/A 04/18/2011
40 47 CELL: RX DIVERSITY RADIO_MLB_87

10/29/2013
10 12 SOC: MISC & ALIASES N/A 04/11/2011 41 48 CELL: GPS RADIO_MLB_87

10/29/2013
11 13 IO: TRISTAR N/A N/A 42 49 CELL: ANTENNA FEEDS

RADIO_MLB_87
10/29/2013
12 14 NAND STORAGE MLB 05/04/2012

43 57 IO: FILTERS & HOTBAR CONN
N/A 04/18/2011
44 58 WIFI/BT: MODULE WIFI_DEV05/20/2013

13
17 TOUCH: SUPPORT CKT & CONN N/A 06/21/2010
45 75 POWER: BATTERY CONNECTOR N/A N/A

14
18 AUDIO: HP FLEX CONN N/A 03/31/2011 46 81 PMU: ANYA PAGE 1 J72_MLB_C
11/26/2012
B 15 19 AUDIO: L81 CODEC KAVITHA 01/18/2012 47 82 PMU: ANYA PAGE 2

J85 MLB_C
12/03/2012
B
16 20 AUDIO: CS35L19A AMPS KAVITHA 01/18/2012

48 83 PMU: ANYA PAGE 3
J72_MLB_C
11/26/2012
49 84 PMU: ANYA PAGE 4 J72_MLB_C

11/26/2012
17
21 BUTTON: CONN N/A N/A
50 85 POWER: PP1V8_SW J85 MLB_C

11/26/2012
18
22 VIDEO: EDP SUPPORT & CONN J85 MLB_C
12/05/2012 51 90 SEP: EEPROM & SOC DEBUG J72_MLB_C
11/26/2012
19 24 SENSOR: OSCAR J72_MLB_C

11/26/2012 52 93 TEST: TP/HOLES/FIDUCIALS
J85 MLB_C
12/03/12
20 26 CAMERA: FF-ALS CONN & FILTERS J85 MLB_C

12/03/2012
53 94 TEST: EE TP/PP
J72_MLB_C
11/26/2012
54 121 POWER: ALIASES

J72_MLB_C
11/26/2012
A A
DRAWING TITLE
SCH,MLB-C1,X200
DRAWING NUMBER SIZE
Apple Inc. 051-0886 D

REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
DRAWING I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 121
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 1 OF 54
8 7 6 5 4 3 2 1
http://sualaptop365.edu.vn
8 7 6 5 4 3 2 1
ISP1_I2C FRONT CAMERA

GRAPE MIPI1C
SPI1
ISP0_I2C REAR CAMERA
CUMULUS CUMULUS MIPI0C
D D
HSIC2 MIMO
UART1 WIFI/BT ANT
WIFI/BT
UART2
I2S3 BT_I2S WIFI/BT ANT
CSA 58
ALCATRAZ NOT ON
DISPLAY/ CELLULAR/ WIFI-ONLY CONFIG
TOUCH PANEL HSIC1 HSIC1
GPS
EDP PRIMARY CELLULAR ANT
DIVERSITY CELLULAR ANT
I2S4 JTAG
UART3 USART GPS ANT
C USB
C
SIM CARD
CSA 31-46
BACKLIGHT
UART5
BUTTON FLEX PMU BATTERY

ANYA TRISTAR
CSA 75 USB2.0
HOME BUTTON DWI UART0
I2C0 UART6
CSA 81-84
I2C0
OSCAR
B UART4 CSA 13 B
HALL EFF I2C1
1-3 CSA 24 I2C2
I2S1
CSA 17 RIGHT
SPI BUS I2C3 AMP SPEAKER
CSA 20
SPI2 SPI
COMPASS I2S0 MBUS
ACCELEROMETER GYRO ASP AMP
FMI0 FMI1 I2S2 XSP LEFT
CSA 20
CSA 27 CSA 27 CSA 27 SPEAKER
L81
AUDIO
A CODEC SYNC_MASTER=J85_MLB_B SYNC_DATE=04/02/2013 A
PAGE TITLE
NAND FLASH HP BLOCK DIAGRAM: SYSTEM

DRAWING NUMBER SIZE
PROX SENSOR CSA 19 051-0886 D
Apple Inc. REVISION
ALS R
A.0.0
CSA 28 THE INFORMATION CONTAINED HEREIN IS THE
CSA 14 MIC1 MIC2 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

2 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC
TABLE_5_HEAD
Page Notes PART#
339S0207
QTY
1
DESCRIPTION
H6P + 1GB ELPIDA

REFERENCE DESIGNATOR(S)
U0652
CRITICAL
CRITICAL
BOM OPTION
TABLE_5_ITEM
Power aliases required by this page:

(NONE) TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

Signal aliases required by this page: PART NUMBER
TABLE_ALT_ITEM
(NONE) 339S0208 339S0207 U0652 HYNIX DDR
BOM options provided by this page:
D D
BOM OPTIONS
COMMON
ALTERNATE
16GB_PROD
32GB_PROD
64GB_PROD
128GB_PROD
PMU
TABLE_5_HEAD
DEVELOPMENT_JTAG_TAP PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

JTAG_DAP
MLB (WDOG TO PMU) TABLE_5_ITEM
343S0656 1 IC,PMU,ANYA,D2089A1,OTPXX,FCCSP342 U8100 CRITICAL
WIFI BOM OPTIONS FLASH CONFIGURATIONS

ANDGATE_TI
FERRITE_TY
FERRITE_TDK TABLE_5_HEAD

TABLE_5_ITEM
335S0921 1 TOS,19NM,PPN1.5,C,DDP,16GB U1400 16GB

TABLE_5_ITEM
335S0922 1 TOS,19NM,PPN1.5,C,QDP,32GB U1400 32GB

TABLE_5_ITEM
335S0923 1 TOS,19NM,PPN1.5,C,ODP,64GB U1400 64GB

TABLE_5_ITEM
335S0929 1 TOS,19NM,PPN1.5,C,12DP,64GB U1400 96GB

TABLE_5_ITEM
335S0924 1 TOS,19NM,PPN1.5,C,16DP,128GB U1400 128GB
TABLE_ALT_HEAD
TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS PART NUMBER
TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM
BASIC COMMON,ALTERNATE 335S0930 335S0921 16GB U1400 HYNIX 20NM PPN1.5 16GB
C 335S0931 335S0922 32GB U1400

TABLE_ALT_ITEM
HYNIX 20NM PPN1.5 32GB

TABLE_ALT_ITEM
C
335S0932 335S0923 64GB U1400 HYNIX 20NM PPN1.5 64GB
U2200
TABLE_5_HEAD

TABLE_5_ITEM
353S4272 1 IC,SLG5AP1423V,PWR SW,GREENFET3,4A,TDFN8 U2200
NOTE: FOLLOWING J72, U2200 USES 353S3672 FOOTPRINT (353S4272 HAS SMALLER PADS DUE TO NEW DFM RULES)
WIFI 4.3UF CAP

TABLE_ALT_HEAD TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER PART NUMBER
TABLE_ALT_ITEM TABLE_ALT_ITEM
339S0223 339S0213 U5800 138S0702 138S0657 C1009,C1015,... RDAR #13988471
MECHANICAL PARTS
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
B 806-6207 1 FENCE,TALL,MLB,X221 PD_FENCE_MLB CRITICAL

TABLE_5_ITEM
TABLE_5_ITEM
B
806-7613 1 FENCE,RADIO,MLB,C BRD,X221 PD_CAN_RADIO CRITICAL
GYRO
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM
338S1192 1 GYRO, ST MICRO U2720 CRITICAL GYRO_STMICRO 338S1158 OLD GYRO - ST MICRO
TABLE_5_ITEM
338S1218 1 GYRO, INVENSENSE U2720 CRITICAL GYRO_INVENSENSE OLDER INVENSENSE P/N 338S1135
BARCODE LABEL/EEEE CODES OLD INVENSENSE P/N 338S1200 (3/22/13)
TABLE_5_ITEM
TABLE_5_HEAD
132S0391 1 CAP 0.01UF 25V 0201 C2726 CRITICAL GYRO_STMICRO

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_5_ITEM
TABLE_5_ITEM
132S0288 1 CAP 0.1UF 16V 0201 C2726 CRITICAL GYRO_INVENSENSE

825-7639 1 EEEE FOR 639-5393 (X200C1 GOOD) FNJD CRITICAL EEEE_X200C_GOOD
TABLE_5_ITEM
825-7639 1 EEEE FOR 639-5394 (X200C1 BETTER) FNJ5 CRITICAL EEEE_X200C_BETTER

TABLE_5_ITEM
825-7639 1 EEEE FOR 639-5385 (X200C1 BEST) FNJ9 CRITICAL EEEE_X200C_BEST

TABLE_5_ITEM
825-7639 1 EEEE FOR 639-5386 (X200C1 BEST+) FNJH CRITICAL EEEE_X200C_BEST+

TABLE_5_ITEM
825-7639 1 EEEE FOR 639-5387 (X200C1 ULTIMATE) FNJ6 CRITICAL EEEE_X200C_ULTIMATE

TABLE_5_ITEM
825-7639 1 EEEE FOR 639-5388 (X200C1 GOOD IVS) FNJ8 CRITICAL EEEE_X200C_GOOD_IVS
TABLE_5_ITEM
825-7639 1 EEEE FOR 639-5389 (X200C1 BETTER IVS) FNJF CRITICAL EEEE_X200C_BETTER_IVS
TABLE_5_ITEM
ACCEL
A 825-7639 1 EEEE FOR 639-5390 (X200C1 BEST IVS) FNJC CRITICAL EEEE_X200C_BEST_IVS
TABLE_5_ITEM TABLE_5_HEAD SYNC_MASTER=J72_MLB_C SYNC_DATE=11/26/2012 A
825-7639 1 EEEE FOR 639-5391 (X200C1 BEST+ IVS) FNJ7 CRITICAL EEEE_X200C_BEST+_IVS PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION PAGE TITLE
825-7639 1 EEEE FOR 639-5392 (X200C1 ULTIMATE IVS) FNJG CRITICAL EEEE_X200C_ULTIMATE_IVS
TABLE_5_ITEM
338S1163 1 IC,ACCEL,3-AXIS,DIG,BMA282,LGA14 U2700 CRITICAL

TABLE_5_ITEM
BOM TABLES
DRAWING NUMBER SIZE

TABLE_ALT_HEAD

PART NUMBER REVISION
R
A.0.0
338S1233 ST MICRO - DISQUAL’ED THE INFORMATION CONTAINED HEREIN IS THE
338S1114 OLD ACCEL - ST MICRO PROPRIETARY PROPERTY OF APPLE INC.
338S1191 OLD ACCEL - ST MICRO THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
4 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
H6P: JTAG, USB, PLL, HSIC, XTAL

D D
NOTE: CANDIDATE FOR COST-SAVINGS

(REPLACE WITH XW LATER?)
=PP1V8_PLL_SOC R06222
1 52 PP1V8_PLL_SOC_F =PP1V0_USB_SOC
54 54
0.00 01005
1 C0651 1 C0648 1 C0608

1 C0627
0.01UF
0.1UF 0.01UF 0.01UF 10%
20% 10% 10% 6.3V
6.3V 6.3V 6.3V 2 X5R
2 X5R-CERM 2 X5R 2 X5R 01005
01005 01005 01005
=PP3V3_USB_SOC 54
USB_VDD330 F23 (25MA)

54 =PP1V2_HSIC_SOC
1 C0630
0.1UF
20%
C0690 1 C0691 1
HSIC_VDD122 AM31
VDD_ANA_PLL_CCC AE20
6.3V
2 X5R-CERM
HSIC_VDD120 G22
HSIC_VDD121 G23
VDD_ANA_PLL U16
(5.4MA) USB_DVDD F24

0.22UF 0.22UF 01005
20% 20%
6.3V 6.3V
X5R 2 X5R 2
(3X 13MA)
0201 0201
(6X 1MA)
C0607
(25MA)
(1MA)
12PF
C TBD: XTAL PASSIVES WILL CHANGE ON H6P WITH FIRST HW BUILD 1 2
C
1 5%
R0655 Y0602 16V
3
XTAL_SOC_24M_I CERM
4
OMIT 1.00M 1.60X1.20MM-SM 01005
54 18 10 7 5 4 =PP1V8_SOC XTAL_SOC_24M_O 1% 24.000MHZ-30PPM-9.5PF-60OHM
2
1 1 1
U0652 1/32W
MF C0613
R0647 R0646 R0645 R0640
1
NC_HSIC0_DATA A26 HSIC0_DATA HSIC_VDD120 H6P 01005 2 12PF
100K 100K 100K NC_HSIC0_STB B26 HSIC0_STB POP-1GB-DDR 1
1.33K2 SOC_24M_O 1 2
1% 1% 1%
1/32W 1/32W 1/32W FCMSP XI0 F25 1% MF
MF MF MF SYM 1 OF 13 VDDIO18_GRP4 1/32W 01005 5%
2 01005 2 01005 2 01005 53 27 24 BI HSIC2_BB_DATA HSIC1_BB_DATA A27 HSIC1_DATA
HSIC_VDD121 XO0 E25 16V
JTAG_SOC_TDI MAKE_BASE=TRUE
B27 HSIC1_STB CERM
52 4
53 27 24 BI HSIC2_BB_STB HSIC1_BB_STB 01005
MAKE_BASE=TRUE
52 11 4 JTAG_SOC_TMS
53 44 HSIC1_WLAN_DATA HSIC2_WLAN_DATA AM33 HSIC2_DATA
52 11 4 JTAG_SOC_TCK BI
MAKE_BASE=TRUE
HSIC_VDD122 ANALOGMUXOUT E26 NC_ANALOGMUXOUT
53 44 BI HSIC1_WLAN_STB HSIC2_WLAN_STB AM34 HSIC2_STB
MAKE_BASE=TRUE
USB_DP B29 USB_SOC_P BI 11 52
52 10 IN JTAG_SOC_SEL D28 JTAG_SEL USB_DM A29 USB_SOC_N BI 11 52
NC_JTAG_SOC_TRTCK D27 JTAG_TRTCK USBHS ON/OFF TOLERANCE 5V/1.98V

52 10 IN JTAG_SOC_TRST_L E28 JTAG_TRST* USB_ANALOGTEST D26 NC_USB_ANALOGTEST
52 TP_JTAG_SOC_TDO E27 JTAG_TDO R0651
54 18 10 7 5 4 =PP1V8_SOC
F27
68.1K
52 4 IN JTAG_SOC_TDI JTAG_TDI USB_VBUS D23 USB_VBUS_DETECT_R USB_VBUS_DETECT IN 46
52 11 4 IN JTAG_SOC_TMS F28 JTAG_TMS 1%

1 VDDIO18_GRP3
R0617 52 11 4 IN JTAG_SOC_TCK C28 JTAG_TCK USB_ID E24 NC_USB_ID
1/32W
MF
100K 01005
1%
1/32W
MF F29 RESET*
2 01005 1.8V TOLERANT USB_REXT E23 USB_REXT
52 48 24 11 10 8 IN RESET_SOC_L E29 CFSB
1
1 C0618 10 IN SOC_HOLD_RESET D29 HOLD_RESET WDOG AD4 WDOG_SOC OUT 10 R0642
1000PF TP0600 200
B 10%
6.3V
2 X5R-CERM
H16 FUSE1_FSRC
VDDIO18_GRP1
TST_CLKOUT AC3 SOC_TEST_CLKOUT TP
TP-P55
1%
1/32W
MF
NOTE: NEW USB_REXT
VALUE FOR H6 = 200 OHM
OLD (H5) VALUE: 44.2 OHM
B
01005 FAST_SCAN_CLK AD3 SOC_FAST_SCAN_CLK IN 10 2 01005
TESTMODE AB3 SOC_TESTMODE IN 10 52
H21 HSIC_VSS121
AM32 HSIC_VSS122
H20 HSIC_VSS120
H23 USB_VSSA0
A SYNC_MASTER=N/A SYNC_DATE=04/18/2011 A
PAGE TITLE
SOC: MAIN
DRAWING NUMBER SIZE

REVISION
R
A.0.0
6 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC I/OS
R0720 OMIT
33.2
1%
1/32W
MF OMIT 48 13 5 IN GPIO_BTN_HOME_L AC5 GPIO0 U0652
01005 48 17 5 GPIO_BTN_ONOFF_L AB1 GPIO1 H6P
IN
53 15 OUT I2S0_CODEC_ASP_MCK 1 2 I2S0_CODEC_ASP_MCK_R C30 I2S0_MCK U0652 I2C0_SCL AV6 I2C0_SCL_1V8 OUT 5 11 48 52
TRISTAR 17 GPIO_BTN_VOL_UP_L AB2 GPIO2 POP-1GB-DDR
AL32 IN
15 OUT I2S0_CODEC_ASP_BCLK I2S0_BCLK H6P I2C0_SDA AR7 I2C0_SDA_1V8 BI 5 11 48 52 PMU AD1 FCMSP
GPIO_BTN_VOL_DOWN_L
VDDIO18_GRP1
AL31 POP-1GB-DDR 17 IN GPIO3
15 I2S0_CODEC_ASP_LRCK I2S0_LRCK SYM 2 OF 13
D
VDDIO18_GRP2
OUT GPIO_BTN_SRL_L AD5 GPIO4
D R0721
33.2
1%
15
15
IN
OUT
I2S0_CODEC_ASP_DIN
I2S0_CODEC_ASP_DOUT
AJ31
AK31
I2S0_DIN
I2S0_DOUT
FCMSP
SYM 3 OF 13
I2C1_SCL AP8
I2C1_SDA AU7
I2C1_SOC2OSCAR_SWDCLK_1V8
I2C1_SOC2OSCAR_SWDIO_1V8
OUT
BI
5 19
5 19
48 17 5 IN
OUT GPIO_SOC2BEACON_EN AE4 GPIO5 TMR32_PWM0 AC31 OSCAR_TIME_SYNC_HOST_INT IN 19
1/32W 14 GPIO_SOC2AJ_HS4_SHUNT_EN AF1 GPIO6 TMR32_PWM1 AD34 GPIO_SPKAMP_KEEPALIVE 5 16 52

MF OUT CRITICAL OUT
01005
AL33 I2S1_MCK CRITICAL 14 OUT GPIO_SOC2AJ_HS3_SHUNT_EN AE2 GPIO7 TMR32_PWM2 AC32 CLK_32K_SOC2CUMULUS OUT 13 52
53 16 OUT I2S1_SPKAMP_MCK 1 2 I2S1_SPKAMP_MCK_R I2C2_SCL AT11 I2C2_SCL_1V8 OUT 5 16 52
AE5
AL34 I2S1_BCLK SPK AMPS 10 IN GPIO_BOARD_REV0 GPIO8
53 16 OUT I2S1_SPKAMP_BCLK I2C2_SDA AR11 I2C2_SDA_1V8 BI 5 16 52
AF3
AK33 I2S1_LRCK 10 IN GPIO_BOARD_REV1 GPIO9 UART0_RXD AR19 UART0_SOC_RXD IN 11 52
53 16 OUT I2S1_SPKAMP_LRCK
AJ32 I2S1_DIN VDDIO18_GRP2 I2C3_SCL W30 I2C3_SCL_1V8 OUT 5 20 22
ALS 10 IN GPIO_BOARD_REV2 AF4 GPIO10 UART0_TXD AR18 UART0_SOC_TXD OUT 11 52
53 16 IN I2S1_SPKAMP_DIN
AK34 I2S1_DOUT I2C3_SDA W32 I2C3_SDA_1V8 BI 5 20 22 PROX 52 15 IN GPIO_CODEC_IRQ_L AF2 GPIO11
53 16 OUT I2S1_SPKAMP_DOUT
52 28 GPIO_SOC2BB_WAKE_MODEM AG1 GPIO12 UART1_CTSN AL2 UART1_BT2SOC_RTS_L 44
VDDIO18_GRP2
OUT IN
DWI_CLK AP19 DWI_AP_CLK IN 48 52
AG3 AL4
52 13 IN GPIO_GRAPE_IRQ_L GPIO13 UART1_RTSN UART1_SOC2BT_RTS_L OUT 44
NC_GPIO_GYRO_IRQ1 E30 I2S2_MCK DWI_DI AT18 TP_SOC_TST_CPUSWITCH_OUT
28 BB_IPC_GPIO AG4 GPIO14 UART1_RXD AK4 UART1_BT2SOC_TX 44 53
AJ33 IN IN
15 I2S2_CODEC_XSP_BCLK I2S2_BCLK DWI_DO AT19 DWI_AP_DO 48 53
VDDIO18_GRP1
OUT OUT GPIO_ALS_IRQ_L AH3 AK3 UART1_SOC2BT_TX
AJ34 20 IN GPIO15 UART1_TXD OUT 44 53
53 15 I2S2_CODEC_XSP_LRCK I2S2_LRCK
VDDIO18_GRP1
OUT AR1 NC_SEP_7816UART0_RST GPIO_BOARD_ID3 AH2
AH31 SEP_7816UART0_RST 10 IN GPIO16
15 IN I2S2_CODEC_XSP_DIN I2S2_DIN AP3 SEP_I2C0_SCL AH4 AL5
VDDIO18_GRP1
SEP_7816UART0_SCL OUT 5 51 28 24 IN GPIO_BB2SOC_RESET_DET_L GPIO17 UART2_CTSN NC_UART2_CTS
53 15 I2S2_CODEC_XSP_DOUT AH34 I2S2_DOUT
OUT AP2 SEP_I2C0_SDA GPIO_BOOT_CONFIG0 AG5 AM3 NC_UART2_RTS
SEP_7816UART0_SDA BI 5 51 10 IN GPIO18 UART2_RTSN
SEP_7816UART1_RST AR4 NC_SEP_7816UART1_RST 48 IN GPIO_PMU2SOC_IRQ_L AJ5 GPIO19 UART2_RXD AM2 UART2_WLAN2SOC_TX IN 44 53
16 GPIO_SPKAMP_RIGHT_IRQ_L AG31 I2S3_MCK
IN AR2 NC_SEP_7816UART1_SCL GPIO_SOC2PMU_KEEPACT AJ4 AM1 UART2_SOC2WLAN_TX
AG32 I2S3_BCLK SEP_7816UART1_SCL 48 5 OUT GPIO20 UART2_TXD OUT 44 53
10 OUT I2S3_SOC2BT_BCLK AP4 AK2
SEP_7816UART1_SDA NC_SEP_7816UART1_SDA 52 13 OUT GPIO_GRAPE_RST_L GPIO21
10 OUT I2S3_SOC2BT_LRCK AH33 I2S3_LRCK
AF31 I2S3_DIN AB33 28 IN GPIO_BB2SOC_GPS_SYNC AP13 GPIO22 UART3_CTSN AN3 UART3_BB2SOC_RTS_L IN 24 28
10 I2S3_BT2SOC_DATA SIO_7816UART0_RST HSIC1_WLAN2SOC_REMOTE_WAKE 44 53
VDDIO18_GRP2
IN GPIO_SOC2BB_RADIO_ON_L AP12 AN4 UART3_SOC2BB_RTS_L
AG34 I2S3_DOUT AA31 52 26 24 IN GPIO23 UART3_RTSN OUT 24 28
10 OUT I2S3_SOC2BT_DATA SIO_7816UART0_SCL HSIC1_WLAN2SOC_DEVICE_RDY 44 53
AR13 AP1
NC_GPIO_BB_HSIC_DEV_RDY GPIO24 UART3_RXD UART3_BB2SOC_TX IN 11 24 28 52
SIO_7816UART0_SDA AB31 HSIC1_SOC2WLAN_HOST_RDY 5 44 53
10 IN GPIO_BOOT_CONFIG1 AN14 GPIO25 UART3_TXD AN1 UART3_SOC2BB_TX OUT 11 24 28 52
52 27 24 OUT BB_JTAG_TCK AE31 I2S4_MCK SIO_7816UART1_RST AA33 HSIC2_BB2SOC_REMOTE_WAKE 28
52 5 IN GPIO_FORCE_DFU AT12 GPIO26
52 27 24 OUT BB_JTAG_TMS AF33 I2S4_BCLK SIO_7816UART1_SCL AA32 HSIC2_BB2SOC_DEVICE_RDY 24 28
TP_GPIO_DFU_STATUS AT13 GPIO27 UART4_CTSN AV3 PMU_GPIO_OSCAR2PMU_HOST_WAKE IN 19 48
52 27 24 OUT BB_JTAG_TDI AE32 I2S4_LRCK SIO_7816UART1_SDA AA34 HSIC2_SOC2BB_HOST_RDY 24 28
10 IN GPIO_BOOT_CONFIG2 AV13 GPIO28 UART4_RTSN AU3 GPIO_OSCAR_RESET_L OUT 19
52 27 24 IN BB_JTAG_TDO AD31 I2S4_DIN
AE33 I2S4_DOUT SOCHOT0 AP18 SOCHOT0_L 5 49 52 10 IN GPIO_BOOT_CONFIG3 AP14 GPIO29 UART4_RXD AT3 UART4_OSCAR2SOC_RXD IN 19 53
52 27 24 OUT BB_JTAG_TRST_L
VDDIO18_GRP1 SOCHOT1 AP17 SOCHOT1_L OUT 5 48 19 OUT GPIO_SOC2OSCAR_DBGEN AU13 GPIO30 UART4_TXD AT2 UART4_SOC2OSCAR_TXD OUT 19 53
C DISP_VSYNC AN17 DISPLAY_SYNC OUT 13

52 26 24
22
OUT GPIO_SOC2BB_RST_L AP15
GPIO_PROX_IRQ_L AR14
GPIO31
GPIO32 UART5_RTXD AM5 UART5_BATT_RTXD 45 48
C
IN BI
28 IN GPIO_BB2SOC_GSM_TXBURST AT14 GPIO33
10 GPIO_BOARD_ID2 AN6 SPI0_MISO
IN GPIO_SPKAMP_RST_L AT15
AP5 16 5 OUT GPIO34
10 IN GPIO_BOARD_ID1 SPI0_MOSI AP16
53 44 GPIO_BT_WAKE GPIO35
VDDIO18_GRP2
GPIO_BOARD_ID0 AT5 OUT
10 IN SPI0_SCLK
AV5 48 11 IN GPIO_TS2SOC2PMU_INT AR16 GPIO36
NC_SPI0_SSIN SPI0_SSIN
16 GPIO_SPKAMP_LEFT_IRQ_L AT16 GPIO37 UART6_RXD W31 UART6_TS_ACC_RXD 11 52
IN IN
18 GPIO_SOC2LCD_PWREN AT17 GPIO38 UART6_TXD Y31 UART6_TS_ACC_TXD 11 52
SPI1_GRAPE_MISO AU5 OUT OUT
52 13 IN SPI1_MISO
52 13 SPI1_GRAPE_MOSI AV4 SPI1_MOSI
OUT
VDDIO18_GRP1
13 SPI1_GRAPE_SCLK AU4 SPI1_SCLK
OUT
52 13 SPI1_GRAPE_CS_L AR5 SPI1_SSIN
OUT
53 15 IN SPI2_CODEC_MISO AU6 SPI2_MISO

53 15 OUT SPI2_CODEC_MOSI AR6 SPI2_MOSI
53 15 OUT SPI2_CODEC_SCLK AP7 SPI2_SCLK
15 OUT SPI2_CODEC_CS_L AN8 SPI2_SSIN
NC_SPI1_NAVAJO_MISO AV10 SPI3_MISO

NC_SPI1_NAVAJO_MOSI AN12 SPI3_MOSI
NC_SPI1_NAVAJO_SCLK AT10 SPI3_SCLK
NC_GPIO_NAVAJO2SOC_INT AP11 SPI3_SSIN
54 51 5 =PP1V8_S2R_MISC
B R0771
220K 2
B
1 GPIO_BTN_HOME_L 5 13 48 54 18 10 7 5 4 =PP1V8_SOC
5% NOSTUFF NOSTUFF
1/32W 1 1 1 1 1 1 1 1 1 1
MF R0700 R0701 R0702 R0703 R0704 R0705 R0750 R0751 R0752 R0753 GPIO_SPKAMP_RST_L 5 16
01005 2.2K 2.2K 1.8K 1.8K 2.2K 2.2K 2.2K 2.2K 2.2K 2.2K GPIO_SOC2PMU_KEEPACT 5 48
5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
54 =PP1V8_ALWAYS 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W HSIC1_SOC2WLAN_HOST_RDY 5 44 53
R0770 MF MF MF MF MF MF MF MF MF MF
220K 2 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 GPIO_FORCE_DFU 5 52
1 GPIO_BTN_ONOFF_L 5 17 48 GPIO_SPKAMP_KEEPALIVE 5 16 52
52 48 11 5 I2C0_SDA_1V8
5%
1/32W 52 48 11 5 I2C0_SCL_1V8
MF
01005
52 16 5 I2C2_SDA_1V8
1 1 1 1 1
54 51 5 =PP1V8_S2R_MISC 52 16 5 I2C2_SCL_1V8 R0739 R0735 R0736 R0737 R0738
R0765 100K 100K 100K 100K 100K
1
220K 2 GPIO_BTN_SRL_L 22 20 5 I2C3_SDA_1V8 1% 1% 1% 1% 1%
5 17 48 1/32W 1/32W 1/32W 1/32W 1/32W
22 20 5 I2C3_SCL_1V8 MF MF MF MF MF
5%
1/32W
(SCREEN ROTATION LOCK) 2 01005 2 01005 2 01005 2 01005 2 01005
MF SEP_I2C0_SDA
01005 51 5
51 5 SEP_I2C0_SCL
19 5 I2C1_SOC2OSCAR_SWDIO_1V8
19 5 I2C1_SOC2OSCAR_SWDCLK_1V8
54 18 10 7 5 4 =PP1V8_SOC
R0754
100K 2
1 SOCHOT0_L 5 49 52
5%
1/32W
A =PP1V8_S2R_MISC
MF
01005
SYNC_MASTER=N/A SYNC_DATE=05/05/2011 A
54 51 5
R0755 PAGE TITLE
1
100K 2
SOCHOT1_L 5 48
SOC: I/OS
5% DRAWING NUMBER SIZE
1/32W
MF
01005
REVISION
R
A.0.0
7 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT OMIT
AN32 C10 A1 AF21

AN33 U0652 C11 A2 U0652 AF23
H6P H6P
AN34 POP-1GB-DDR C12 A3 POP-1GB-DDR AF29
AP6 FCMSP C13 A4 FCMSP AF32
AP20 SYM 12 OF 13 C15 A5 SYM 11 OF 13 AG2
AP21 C16 A7 AG8
AP24 CRITICAL C17 A9 CRITICAL AG10
D AP25
AP26
C18
C19
A11
A13
AG12
AG14
D
AP27 C22 A14 AG16
AP28 C23 A16 AG18
AP29 C24 A18 AG20
AP30 C26 A25 AG22
AP31 C27 A28 AG24
AP32 C29 A30 AG26
AR3 C31 A33 AG28
AR8 D1 A34 AG30
AR12 D2 AA1 AH5 =PP1V8_NAND_SOC
54 6
AR15 D3 AA2 AH7
AR17 D4 AA3 AH9 R0831 R0832
AR20 D5 AA4 AH11 1 1
AR21 D6 AA8 AH13 100K 100K
AR22 D7 AA10 AH15 1% 1%
1/32W 1/32W
AR23 D8 AA12 AH17 MF MF
2 01005 OMIT 2 01005
AR24 D9 AA14 AH19
AR25 D10 AA16 AH21 FMI0_CE0_L G32 PPN0_CEN0 PPN1_CEN0 R32 FMI1_CE0_L
52 12 OUT U0652 OUT 12 52
AR28 D11 AA18 AH23 NC_PPN0_CEN1 H31 PPN0_CEN1 H6P PPN1_CEN1 P32 NC_PPN1_CEN1
AR29 D12 AA22 AH25 POP-1GB-DDR
AR32 D13 AA24 AH27 FCMSP
AT1 D15 AA26 AH29 SYM 4 OF 13
AT4 D16 AA28 AH32 CRITICAL
AT6 D17 AA30 AJ1
AT20 D18 AB5 AJ3
AT21 D19 AB7 AJ8
C AT22 D20 AB9 AJ10 12 BI FMI0_AD<0> B32 PPN0_IO0 PPN1_IO0 M34 FMI1_AD<0> BI 12
C
AT23 D21 AB11 AJ12 12 FMI0_AD<1> C32 PPN0_IO1 PPN1_IO1 M33 FMI1_AD<1> 12
VSS BI BI
AT24 D22 AB13 AJ14 12 FMI0_AD<2> C33 PPN0_IO2 PPN1_IO2 L32 FMI1_AD<2> 12
VSS BI BI
AT25 D32 AB15 AJ16 53 12 FMI0_AD<3> C34 PPN0_IO3 PPN1_IO3 M32 FMI1_AD<3> 12
BI BI
AT26 E1 AB17 AJ18 12 FMI0_AD<4> F32 PPN0_IO4 PPN1_IO4 K32 FMI1_AD<4> 12
BI BI
AT27 E3 AB19 AJ22 12 BI FMI0_AD<5> F33 PPN0_IO5 VDDIO18_GRP3 PPN1_IO5 J32 FMI1_AD<5> BI 12
AT28 E4 AB21 AJ24 12 FMI0_AD<6> F34 PPN0_IO6 PPN1_IO6 H33 FMI1_AD<6> 12
BI BI
AT29 E5 AB23 AJ26 12 BI FMI0_AD<7> G34 PPN0_IO7 PPN1_IO7 H34 FMI1_AD<7> BI 12
AT30 VSS E6 AB25 AJ28
VSS
AT31 E7 AB27 AJ30
AT32 E8 AB29 AK5 12 FMI0_ALE A31 PPN0_ALE PPN1_ALE N34 FMI1_ALE 12
OUT OUT
AU1 E9 AB32 AK7 12 OUT FMI0_CLE B31 PPN0_CLE PPN1_CLE P31 FMI1_CLE OUT 12
AU2 E10 AC4 AK9 12 OUT FMI0_WE_L A32 PPN0_WEN PPN1_WEN N32 FMI1_WE_L OUT 12
AU11 E11 AC8 AK11 12 OUT FMI0_RE_L D33 PPN0_REN PPN1_REN L31 FMI1_RE_L OUT 12
AU16 E12 AC10 AK13 53 12 FMI0_DQS D34 PPN0_DQS PPN1_DQS L34 FMI1_DQS 12
BI BI
AU18 E13 AC12 AK15 FMI0_ZQ E33 PPN0_ZQ PPN1_ZQ K33 FMI1_ZQ
AU21 E14 AC14 AK17 R0870 R0871
AU33 E15 AC16 AK19 1
240 2 1
240 2
AU34 E18 AC18 AK21
1% 1%
AV1 E19 AC20 AK23 1/32W 1/32W
MF D31 PPN0_VREF MF
AV2 E20 AC22 AK27 01005 PPN1_VREF N31 01005
AV9 E21 AC24 AK29
AV11 E22 AC26 AK32
AV14 E31 AC28 AL3
AV16 E32 AC30 AL6
AV18 E34 AC34 AL8
B AV20
AV33
F2
F3
AD2
AD7
AL10
AL12
=PP1V8_NAND_SOC 6 54
B
AV34 F4 AD9 AL14
1
B1 F5 AD11 AL16 R0860 1
50K C0860
B2 F6 AD13 AL18 1% 0.01UF
B4 F7 AD15 AL20 1/32W 10%
MF 6.3V
2 X5R
B5 F8 AD17 AL22 2 01005 01005
B6 F9 AD19 AL24 PPVREF_FMI_SOC
B7 F10 AD21 AL26
B8 F12 AD23 AL28
1
B9 F13 AD25 AL30 R0861 1 C0861
B10 F14 AD29 AM4
50K 0.01UF
1% 10%
1/32W
B11 F15 AD32 AM7 MF 2 6.3V
X5R
B12 F26 AE3 AM18 2 01005 01005
B13 F30 AE8 AM30
B15 F31 AE10 AN2
B16 G1 AE12 AN5
B17 G3 AE14 AN7
B18 G4 AE16 AB6
B19 G5 AE18 AM9
B25 G6 AE22 AM11
B28 G7 AE24 AM13
B30 G8 AE26 AN16
B33 G9 AE28 AM15
B34 G10 AF5 AN19
C1 G11 AF7 AN20
A C2 G12 AF9 AN21 SYNC_MASTER=N/A SYNC_DATE=04/18/2011 A
C3 G13 AF11 AN22 PAGE TITLE
C5
C6
G14
G15
AF13
AF15
AN23
AN24
SOC: NAND
DRAWING NUMBER SIZE
C7 G26 AF17 AN31
C9 G28 AF19 REVISION
R
A.0.0
8 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP1V8_MIPI_SOC 54
1 C0962
0.1UF
20%
6.3V
2 X5R-CERM
01005
D D
NC_MIPI0D_VREG
54
=PP1V0_MIPI_SOC NC_MIPI1D_VREG
1 C0930
AN25
AN26
AN27
AN28
AN29
(2MA) MIPI0D_VDD18 AR26

(2MA) MIPI1D_VDD18 AR31
MIPI0D_VREG_0P4V AR27
MIPI1D_VREG_0P4V AR30
1UF
20%
2 4V
X6S
0204 MIPI_VDD10 =PP1V8_SOC 4 5 10 18 54
(55MA)
1 1 1 1
R0931 R0930 R0933 R0932
2.2K 2.2K 2.2K 2.2K
5% 5% 5% 5%
VDDIO18_GRP1
NC_SENSOR0_ISTRB AN10 SENSOR0_ISTRB 1/32W 1/32W 1/32W 1/32W
AR9 MF MF MF MF
NC_SENSOR0_XSHUTDOWN SENSOR0_XSHUTDOWN 2 01005 2 01005 2 01005 2 01005
OMIT
NC_SENSOR1_ISTRB AR10 SENSOR1_ISTRB
NC_SENSOR1_XSHUTDOWN AP10 SENSOR1_XSHUTDOWN
U0652
H6P
POP-1GB-DDR
53 23 MIPI0C_CAM_REAR_DATA_P<0> AU27 MIPI0C_DPDATA0 FCMSP ISP0_SCL AT7 ISP0_CAM_REAR_SCL 23 52
IN BI
AV27 MIPI0C_DNDATA0 SYM 5 OF 13
53 23 IN MIPI0C_CAM_REAR_DATA_N<0> ISP0_SDA AV7 ISP0_CAM_REAR_SDA OUT 23 52
CRITICAL
53 23 IN MIPI0C_CAM_REAR_DATA_P<1> AU26 MIPI0C_DPDATA1
MIPI0C_CAM_REAR_DATA_N<1> AV26 MIPI0C_DNDATA1
VDDIO18_GRP1
53 23 IN
ISP1_SCL AU8
DISPLAYPORT NC_MIPI0C_CAM_REAR_DATA_P2
NC_MIPI0C_CAM_REAR_DATA_N2
AU24 MIPI0C_DPDATA2
AV24 MIPI0C_DNDATA2
ISP1_SDA AP9
100
01005
ISP1_CAM_FRONT_SCL
ISP1_CAM_FRONT_SDA OUT
BI 20 52
20 52
SENSOR0_CLK AV8 ISP0_CAM_REAR_CLK_R 1 2 R0941 ISP0_CAM_REAR_CLK OUT 23 52
NC_MIPI0C_CAM_REAR_DATA_P3 AU23 MIPI0C_DPDATA3 SENSOR0_RST AT8 ISP0_CAM_REAR_SHUTDOWN_L 23 52

OUT
C R0901
0.00 2
NC_MIPI0C_CAM_REAR_DATA_N3 AV23 MIPI0C_DNDATA3
SENSOR1_CLK AU9 ISP1_CAM_FRONT_CLK_R 1
49.9
01005
2 R0940 ISP1_CAM_FRONT_CLK OUT 20 52
C
=PP1V8_EDP_SOC 1 PP1V8_EDP_AVDD_AUX AU25 MIPI0C_DPCLK
54
53 23 OUT MIPI0C_CAM_REAR_CLK_P SENSOR1_RST AT9 ISP1_CAM_FRONT_SHUTDOWN_L OUT 20 52
0% MIPI0C_CAM_REAR_CLK_N AV25 MIPI0C_DNCLK
53 23
1 C0951 1/32W
MF
1 C0952 1 C0953 1 C0954 1 C0955 1 C0956 OUT
56PF 01005 8.2PF 56PF 0.22UF 1.0UF 1.0UF
5% +/-0.5PF 5% 20% 20% 20% NC_MIPI0D_DPDATA0 AU32 MIPI0D_DPDATA0
16V 16V 16V 6.3V 6.3V 6.3V
2 NP0-C0G 2 NP0-C0G-CERM 2 NP0-C0G 2 X5R 2 X5R 2 X5R AV32 MIPI0D_DNDATA0
01005 01005 01005 0201 0201-1 0201-1
NC_MIPI0D_DNDATA0
MIPI_VDD10
NC_MIPI0D_DPDATA1 AU31 MIPI0D_DPDATA1
NC_MIPI0D_DNDATA1 AV31 MIPI0D_DNDATA1
NC_MIPI0D_DPDATA2 AU29 MIPI0D_DPDATA2

=PP1V0_EDP_PAD_DVDD_SOC NC_MIPI0D_DNDATA2 AV29 MIPI0D_DNDATA2
54
MIPI1C_DPDATA0 AT33 MIPI1C_CAM_FRONT_DATA_P<0> IN 20 53
1 C0957 1 C0958 NC_MIPI0D_DPDATA3 AU28 MIPI0D_DPDATA3 MIPI1C_DNDATA0 AT34 MIPI1C_CAM_FRONT_DATA_N<0> IN 20 53
1.0UF 8.2PF NC_MIPI0D_DNDATA3 AV28 MIPI0D_DNDATA3
20% +/-0.5PF
6.3V 16V
2 X5R 2 NP0-C0G-CERM MIPI1C_DPDATA1 AP33 NC_MIPI1C_CAM_FRONT_DATA_P1
0201-1 01005 NC_MIPI0D_DPCLK AU30 MIPI0D_DPCLK MIPI1C_DNDATA1 AP34 NC_MIPI1C_CAM_FRONT_DATA_N1
NC_MIPI0D_DNCLK AV30 MIPI0D_DNCLK
MIPI1C_DPCLK AR33 MIPI1C_CAM_FRONT_CLK_P OUT 20 53
DP_PAD_DVDD F16
DP_PAD_AVDDX F17
DP_PAD_AVDDP0 G18
(50MA) DP_PAD_AVDD1 F20

(1MA) DP_PAD_AVDD_AUX F18

MIPI1C_DNCLK AR34 MIPI1C_CAM_FRONT_CLK_N OUT 20 53
MIPI_VSS
(10MA)
(14MA)
(14MA)
AL25
AM25
AM26
AM27
AM28
AM29
B OMIT
B
U0652
H6P
POP-1GB-DDR
FCMSP
TP_EDP_PAD_DC_TP E16 DP_PAD_DC_TP

SYM 6 OF 13
SOC_EDP_R_BIAS E17 DP_PAD_R_BIAS CRITICAL

NOSTUFF VDDIO18_GRP3 EDP_HPD D30 EDP_HPD IN 18
1
1 C0950 R0900
4.99K
0.01UF 1%
10% 1/32W
6.3V MF
2 X5R
01005 2 01005 DP_PAD_AUXP A20 EDP_AUX_P BI 18
DP_PAD_AUXN B20 EDP_AUX_N BI 18
DP_PAD_TX0P A21 EDP_DATA_P<0> OUT 18 53
DP_PAD_TX0N B21 EDP_DATA_N<0> OUT 18 53

DP_PAD_AVSS_AUX

DP_PAD_AVSSP0
DP_PAD_TX2N B23 EDP_DATA_N<2>

DP_PAD_AVSS2
DP_PAD_AVSS3
DP_PAD_AVSSX
DP_PAD_AVSS1
DP_PAD_AVSS0
OUT 18 53
A
DP_PAD_DVSS

SYNC_MASTER=MLB
PAGE TITLE
SYNC_DATE=05/04/2012 A
SOC: DP,MIPI
DRAWING NUMBER SIZE

G20
G21
G16
H17
H18
G19
H19
G17
REVISION
R
A.0.0
9 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT
54
=PP1V2_VDDIOD_SOC AM20 R33
AM21 U0652 T1 52 48 24 11 10 4 RESET_SOC_L AP22 DDR0_CKEIN G30
AM22 H6P T2 NOTE: CKEIN CONFIRMED 1.8V TOLERANT U32 DDR1_CKEIN G31
VDDIOD_DDR0CA POP-1GB-DDR ON 5/6/12, BY MANU G
AM23 T3 G33
CAPS FOR VDDIOD ARE SHARED WITH VDDQ FCMSP
AM24 T5 54
=PP1V2_S2R_DDR_SOC AP23 DDR0_VDD_CKE (<1MA) H1
CRITICAL U31 H2
T7 DDR1_VDD_CKE (<1MA)
C1000 1
R29 T9 DDR0_CA_ZQ AU15 DDR0_RREF_CA H3
0.1UF
D T29
U29 VDDIOD_DDR1CA
T11
T13
20%
6.3V
X5R-CERM 2
DDR1_CA_ZQ
DDR0_DQ_ZQ
AC33
F11
DDR1_RREF_CA
DDR0_RREF_DQ
OMIT
U0652
H4
H5
D
01005
V29 T15 =PP1V2_S2R_DDR DDR1_DQ_ZQ T4 DDR1_RREF_DQ H25
54 8 H6P
T17 1 8 PPVREF_DDR0_CA AU17 DDR0_VREF_CA POP-1GB-DDR H27
AA6 T19 1 R1001 1R1000 1
R1030 1
R1031 PPVREF_DDR1_CA Y33 DDR1_VREF_CA FCMSP H29
R1005 240 240 240 240 8
H6 T21 2.21K 1% 1% 1% 1% 8 PPVREF_DDR0_DQ D14 DDR0_VREF_DQ H32

1% 1/32W 1/32W 1/32W 1/32W U4 CRITICAL J2
H7 T23 1/32W MF MF MF MF 8 PPVREF_DDR1_DQ DDR1_VREF_DQ
MF 2 01005 2 01005 2 01005 2 01005
H8 T25 J3
2 01005
H9 T27 AB34 J4
SYM 9 OF 13 AF34 J5
H10 T30
H11 T31
PPVREF_DDR0_CA 8 (DDR IMPEDANCE CONTROL) AV12 J6
(CURRENT CONSUMPTION
H12 T32 NOSTUFF VOLTAGE=0.6V AV15 SHARED WITH VDDIOD) J8
1 1 SYM 7 OF 13
H13 T33 R1006 C1002 MIN_NECK_WIDTH=0.15 MM
MIN_LINE_WIDTH=0.3MM AV19 VDDCA J10
2.21K 0.01UF NET_SPACING_TYPE=PWR AV21 J12
H14 T34 1% 10% MAX_NECK_LENGTH=3 MM
1/32W 6.3V
2 X5R
H15 U3 MF R34 J14
VDDIOD_DDRDQ 01005
M6 U5 2 01005 W34 J16
(1000MA)
N6 U8 =PP1V2_S2R_DDR J18
54 8
P6 U10 AC2 J20
R6 U12 1 C1009 1 1 AD33 J22
C1006 C1007
T6 U14 4.3UF 1UF 1UF C20 J24
20% 20% 20%
4V G2 J26
U6 U18 2 X5R-CERM 2 4V
X6S 2 4V
X6S
=PP1V2_VDDQ_DDR 0610 0204 0204 J33 J28
V6 U20 54 8
W6 U22 L3 J30
Y6 U24 P33 VSS J31
1
U26 R1053 U2 K1
1.00K 1 (500MA)
U28 1% C1004 U33 K2
1/32W 0.47UF Y34 K3
U30 MF 20% VDD2
C U34 2 01005 4V
2 X7S
0204
AG33
AJ2
K4
K5
C
V2
VSS AU10 K7
V3 PPVREF_DDR0_DQ 8
V4 AU14 K9
1 NOSTUFF VOLTAGE=0.6V AU20 K11
V5 R1054 1 C1054 MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
V7 1.00K 0.01UF NET_SPACING_TYPE=PWR AU22 K13
1% 10% MAX_NECK_LENGTH=3 MM AV17 K15
V9 1/32W 6.3V
MF 2 X5R
V11 01005 C4 K17
2 01005
V13 C8 K19
V15 C14 K21
V17 D24 K23
V19 K25
V21 54
=PP1V8_S2R_DDR AE34 K27
CAPS FOR VDDIO18_X ARE SHARED WITH VDDIODX V23 AK1 K29
V25
1 C1015 B3 K31
4.3UF
=PP1V8_VDDIO18_SOC AD6 V27 =PP1V2_S2R_DDR 20% B14 K34
54 9 54 8
2 4V
X5R-CERM
AH6 V30 D25 L2
1 C1070 1 C1071 AM8 V32 1
0610
E2
4.7UF R1051 (45MA)
20% 1UF AM10 V34 2.21K J34
2 6.3V 20% VDD1
X5R 4V
2 X6S AM12 VDDIO18_GRP1 W1 1% P34
402 1/32W
0204 (65MA) MF U1
AM14 W2
(GPIO,UART,SPI,I2C) 2 01005 V33
AM16 (SENSOR,SOCHOT,PMU) W3
AM19 W4 AU12
PPVREF_DDR1_CA AU19
1 C1072 1 C1073 W5 8
AV22
1UF 0.47UF W8 NOSTUFF VOLTAGE=0.6V
20% 20% 1 1 MIN_NECK_WIDTH=0.2MM
4V 4V
2 X7S W10 R1052 C1052 MIN_LINE_WIDTH=0.3MM
2 X6S 2.21K 0.01UF =PP1V2_VDDQ_DDR
B 0204 0204 W12
W14
1%
1/32W
MF
10%
6.3V
2 X5R
NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM 54 8
1
A6
A8
B
01005 C1027
W16 2 01005 4.3UF C21
W18 20% C25
2 4V
X5R-CERM
W20 F1
0610
W22 J1
W24 L1 (CURRENT CONSUMPTION
W26 54 8
=PP1V2_VDDQ_DDR N1 SHARED WITH VDDIOD)
W28 1 C1028 1 C1029 R1

AD30 W33 1 1UF 1UF V1
R1055 20% 20% VDDQ
AH30 Y2 1.00K 2 4V
X6S 2 4V
X6S
A10
VDDIO18_GRP2 1% 0204 0204 A12
(20MA) Y3 1/32W
Y4 MF A15
G25 2 01005
Y5 A17
G27 1 C1031 1 C1026 A19
Y7
H30 PPVREF_DDR1_DQ8 0.47UF 0.47UF AC1
Y9 20% 20%
K30 VDDIO18_GRP3 2 4V 2 4V AE1
FL1000 M30 (31MA)
Y11
1 NOSTUFF VOLTAGE=0.6V X7S
0204
X7S
0204
1KOHM-25%-0.2A Y13 R1056 1 C1056 MIN_NECK_WIDTH=0.2MM
AH1
P30 1.00K 0.01UF NET_SPACING_TYPE=PWR AL1
1 2 Y15 1% 10% MAX_NECK_LENGTH=3 MM
G29 1/32W 6.3V Y1
0201 Y17 MF 2 X5R
01005
52 PP1V8_XTAL G24 VDDIO18_GRP4 Y19 2 01005
(2MA) Y21
1 C1042 Y23
1.0UF
20% Y27
10V
2 X5R-CERM
Y29
0201-1
Y32
A AM17
Y30
PAGE TITLE
AC6
AE6
SOC: SRAM, IO PWRS
DRAWING NUMBER SIZE
AG6
AJ6 Apple Inc. 051-0886 D
REVISION
AE30 R
A.0.0
10 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
54
=PPVDD_GPU
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
54
=PPVDD_SOC 1 C1170 1 C1171 1 C1172 1 C1173 1 C1174 1 C1175 1 C1176 1 C1177 1 C1178 1 C1179 1 C1180
15UF 15UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF 1UF 1UF 1UF
CRITICAL CRITICAL CRITICAL CRITICAL 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
1 C1100 1 C1101 1 C1102 1 C1103 OMIT 2 X5R 2 X5R 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X6S 2 X6S 2 X6S
4.3UF 4.3UF 4.3UF 4.3UF 0402 0402 0610 0610 0610 0610 0610 0610 0204 0204 0204
20% 20% 20% 20% L4
4V
2 X5R-CERM 4V
2 X5R-CERM 4V
2 X5R-CERM 4V
2 X5R-CERM U0652 L5
0610 0610 0610 0610 H6P CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
POP-1GB-DDR L6 1 C1181 1 C1182 1 C1183 1 C1184 1 C1185 1 C1186 1 C1187
FCMSP L8 1UF 1UF 1UF 0.47UF 0.47UF 0.47UF 0.47UF
20% 20% 20% 20% 20% 20% 20%
SYM 8 OF 13 L10 4V 4V 4V 4V 4V 4V 4V
2 X6S 2 X6S 2 X6S 2 X7S 2 X7S 2 X7S 2 X7S
L12
D 1
CRITICAL
C1104 1
CRITICAL
C1105 1
CRITICAL
C1106 1
CRITICAL
C1107 1
CRITICAL
C1108 1
CRITICAL
C1109
CRITICAL L14
0204 0204 0204 0204 0204 0204 0204
D
L16
1UF 1UF 1UF 1UF 1UF 1UF
20% 20% 20% 20% 20% 20% L18
2 4V
X6S 2 4V
X6S 2 4V
X6S 2 4V
X6S 2 4V
X6S 2 4V
X6S
CRITICAL CRITICAL
L20 1 C1188 1 C1189 1 C1190 1 C1191 1 C1192 1 C1193 1 C1194
0204 0204 0204 0204 0204 0204
L22 0.47UF 0.47UF 0.22UF 0.22UF 0.22UF 0.22UF 8.2PF
20% 20% 20% 20% 20% 20% +/-0.5PF
L24 4V 4V 6.3V 6.3V 6.3V 6.3V 16V
2 X7S 2 X7S 2 X5R 2 X5R 2 X5R 2 X5R 2 NP0-C0G-CERM
L26 0204 0204 01005 01005 01005 01005 01005
L28
CRITICAL CRITICAL L30
1 C1110 1 C1111 1 C1112 1 C1113 1 C1114 OMIT
0.22UF 0.22UF 8.2PF L33 AA21 AB10
0.47UF 0.47UF 20% 20% +/-0.5PF U0652
20% 20% AA23 AB12
2 4V 2 4V 2 6.3V
X5R 2 6.3V
X5R 2 16V
NP0-C0G-CERM
M1 H6P
X7S X7S AA25 AB16
0204 0204 0201 0201 01005 M2 POP-1GB-DDR
M3 AA27 FCMSP AB18
M4 AA29 SYM 13 OF 13 AC11
M5 =PPVDD_CPU AB22 AC13
54
AB24 CRITICAL AC15
M7
M9 AB26 AC17
M11 AB28 AC19
OMIT M13 AC21 AC7
CRITICAL CRITICAL CRITICAL CRITICAL
AA7 R23 M15 1 C1115 1 C1116 1 C1117 1 C1118 1 C1119 1 C1120 AC23 AC9
AA17 U0652 R27 15UF 15UF 4.3UF 4.3UF 4.3UF 4.3UF AC25 AD10
H6P M17 20% 20% 20% 20% 20% 20%
AA19 T14 4V 4V 4V 4V 4V 4V AC27 AD12
POP-1GB-DDR M19 2 X5R 2 X5R 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM
L29 FCMSP T16 0402 0402 0610 0610 0610 0610 AC29 AD14
M21
M28 T18 M23 AD22 AD16
SYM 10 OF 13
N27 T20 M25 AD27 AD18
CRITICAL
P26 T22 M27 AE29 AD8
R25 T24 AF22 AE11
C U15 T26
M29
M31 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL AF25 AE13 C
V22 T28 N2
1 C1121 1 C1122 1 C1123 1 C1124 1 C1125 1 C1126 AF27 AE15
AB30 U7 4.3UF 4.3UF 1UF 1UF 1UF 1UF AG21 AE17
N3 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V
AH20 U17 N4 2 X5R-CERM 2 X5R-CERM 2 X6S 2 X6S 2 X6S 2 X6S AG23 AE19
0610 0610 0204 0204 0204 0204
H26 U19 =PPVDD_SRAM_SOC AD24 N5 AG25 AE7
54
J25 U21 AD26 N8 AG27 AE9
K20 U23 1 C1148 AD28 N10 AG29 AF10
K22 U25 4.3UF AH22 AF12
20% AE23 N12
K24 U27 4V
2 X5R-CERM CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL AH24 AF14
AE25 N14 1 C1127 1 C1128 1 C1129 1 C1130 1 C1131 1 C1132 7,500MA FOR G3 GPU
0610 @125C
K26 V14 AE27 N16 1UF 1UF 1UF 1UF 1UF 1UF AH26 AF16
VDD_SRAM_CPU 20% 20% 20% 20% 20% 20% @1.1V
K28 V16 1,500MA FOR CYCLONE + M$ SRAM AH28 AF18
AF24 N18 2 4V
X6S 2 4V
X6S 2 4V
X6S 2 4V
X6S 2 4V
X6S 2 4V
X6S VDD_CPU VDD_GPU
L7 V18 @125C 0204 0204 0204 0204 0204 0204 AJ21 AF8
AF26 @1.0V N20 10,800MA FOR CPU0+1
L9 V20 1 C1150 1 C1151 AF28 N22 AJ23 @125C
@1.1V/1.2GHZ
AG11
L11 V24 1UF 1UF AK25 N24 AJ25 AG13
20% 20%
L13 V26 4V 4V AJ27 AG15
2 X6S 2 X6S Y25 N26
L15 V28 0204 0204 VSS AJ29 AG17
N28 CRITICAL CRITICAL CRITICAL CRITICAL
L17 W7 AA9 N30
1 C1133 1 C1134 1 C1135 1 C1136 1 C1137 1 C1138 AK22 AG19
L19 W17 0.22UF 8.2PF 0.47UF 0.47UF 0.47UF 0.47UF AK24 AG7
AA11 N33 20% +/-0.5PF 20% 20% 20% 20%
L21 W19 2 6.3V 2 16V
NP0-C0G-CERM 2 4V 2 4V 2 4V 2 4V AK26 AG9
L23 Y16
1 C1152 1 C1153 AA13 P1 X5R
0201 01005 X7S
0204
X7S
0204
X7S
0204
X7S
0204 AK28 AH10
0.47UF 0.47UF AA15 (1500MA) P2
20% 20%
L25 Y18 4V 4V AB8 P3 AL21 AH12
2 X7S 2 X7S
L27 Y20 0204 0204 T8 P4 AL27 AH14
M8 (VDD BALLS = VDD_SOC PWR DOMAIN) AN11 T10 P5 W21 AH16
M10 AB14 CRITICAL CRITICAL CRITICAL CRITICAL W23 AH18
VDD VDD T12 P7 1 C1139 1 C1140 1 C1141 1 C1142 1 C1143 1 C1144 1 C1145
M12 2,500MA FOR VDD_SOC AB20 W25 AH8
@125C U9 P9 0.47UF 0.47UF 0.47UF 0.47UF 0.22UF 0.22UF 0.22UF
20% 20% 20% 20% 20% 20% 20%
M14 @1.0V AN13 U11 P11 4V 4V 4V 4V 6.3V 6.3V 6.3V W27 AJ11
B M16
M18
(THERMAL VIRUS) AD20
AN15
U13 VDD_SRAM_SOC P13
2 X7S
0204
2 X7S
0204
2 X7S
0204
2 X7S
0204
2 X5R
01005
2 X5R
01005
2 X5R
0201 W29
Y22
AJ13
AJ15
B
V8 P15
M20 AE21 V10 P17 Y24 AJ17
M22 AF6 V12 P19 Y26 AJ19
M24 AF20 W9 P21 Y28 AJ7
M26 AF30 W11 P23 AL29 AJ9
N7 AN18 W13 P25 AK10
N9 AK6 W15 P27 AK12
N11 AK20 Y8 P29 AK14
N13 AK30 Y10 R2 AK16
N15 AL23 Y12 R3 AK18
N17 AN9 Y14 R4 AK8
N19 H24 R5 AL11
N21 H28 R8 AL13
53 PPVDD_CPU_SOC_SENSE AN30 VDD_SENSE_CPU
N23 J7 R10 AL15
N25 J9 R12 AL17
N29 J11 AJ20 R14 AL19
VDD_ANA_TMPSADC0(2.5MA)
P8 J13 AA20 R16 AL7
=PP1V8_VDDIO18_SOC VDD_ANA_TMPSADC1(2.5MA)
P10 J15 54 8
AB4 R18 AL9
VDD_ANA_TMPSADC2(2.5MA)
P12 J17 H22 R20 AM6
1 C1160 VDD_ANA_TMPSADC3(2.5MA)
P14 J19 R22
0.1UF
P16 J21 20% R24
6.3V
2 X5R-CERM
P18 J23 R26
01005
P20 J27 VDD_GPU_SENSE AA5 PPVDD_GPU_SOC_SENSE
R28
P22 J29 R30
P24 K6
A P28 K8
R31
R7 K10 PAGE TITLE
R9 K12 SOC: VDD, SRAM, CPU, GPU PWRS
R11 K14 DRAWING NUMBER SIZE
R13 K16
R15 K18 REVISION
R
R17 A.0.0
R19 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R21 THE INFORMATION CONTAINED HEREIN IS THE
V31 VDD_SENSE PROPRIETARY PROPERTY OF APPLE INC.
53 PPVDD_SOC_SOC_SENSE THE POSESSOR AGREES TO THE FOLLOWING: PAGE
11 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOOT CONFIG ID
54 18 10 7 5 4 =PP1V8_SOC
NOSTUFF NOSTUFF NOSTUFF JTAG NOSTUFF
1 1 1 1
R1200 R1201 R1202 R1203 R1250
2.2K 2.2K 2.2K 2.2K JTAG_SOC_TRST_L 1
0.00 2 RESET_SOC_L
5% 5% 5% 5% 52 4 4 8 11 24 48 52
1/32W 1/32W 1/32W 1/32W
MF MF MF MF 0%
1/32W
2 01005 2 01005 2 01005 2 01005 1
BOOT_CONFIG[3] (GPIO29) 5 GPIO_BOOT_CONFIG3 R1211 MF
01005
100
5%
BOOT_CONFIG[2] (GPIO28) 5 GPIO_BOOT_CONFIG2 1/32W
MF
2 01005
D BOOT_CONFIG[1] (GPIO25) 5 GPIO_BOOT_CONFIG1
D
BOOT_CONFIG[0] (GPIO18) 5 GPIO_BOOT_CONFIG0
BOOT_CONFIG[3-0] S/W READ FLOW

JTAG_SOC_SEL OUT 4 52
1. SET GPIO AS INPUT 1

0000 SPI0
2. DISABLE PU AND ENABLE PD
R1210
0001 SPI0 TEST MODE 100
0010 NAND <-- SELECTED 3. READ 5%
1/32W
0011 NAND TEST MODE MF
2 01005
R1260
1
100 2 SOC_TESTMODE 4 52
5%
1/32W
MF
01005
BOARD ID SOC_FAST_SCAN_CLK
C 54 18 10 7 5 4 =PP1V8_SOC
ID_J86_J87 ID_J85_J87 ID_DEV
4
5 I2S3_SOC2BT_BCLK I2S4_SOC2BT_BCLK 44
C
1 1 1 1 SOC_HOLD_RESET 4
MAKE_BASE=TRUE
R1213 R1204 R1205 R1206 5 I2S3_SOC2BT_LRCK I2S4_SOC2BT_LRCK 44

MAKE_BASE=TRUE
2.2K 2.2K 2.2K 2.2K 5 I2S3_BT2SOC_DATA I2S4_BT2SOC_DATA 44
5% 5% 5% 5% MAKE_BASE=TRUE
1/32W 1/32W 1/32W 1/32W
MF MF MF MF 5 I2S3_SOC2BT_DATA I2S4_SOC2BT_DATA 44
2 01005 2 01005 2 01005 2 01005 MAKE_BASE=TRUE
BOARD_ID[3] 5 GPIO_BOARD_ID3
4 WDOG_SOC WDOG_SOC2PMU_RESET_IN 48
MAKE_BASE=TRUE
ID[3-0] SYSTEM
1010 J85 AP S/W READ FLOW
MLB 1011 J85 DEV
1. SET GPIO AS INPUT
1100 J86 AP 2. DISABLE PU AND ENABLE PD
MLB_B 1101 J86 DEV
3. READ
MLB_C 1110 J87 AP
1111 J87 DEV
BOARD REVISION
5 GPIO_BOARD_REV2
SIM CARD
5 GPIO_BOARD_REV1
5 GPIO_BOARD_REV0
NOSTUFF NOSTUFF 52 27 25 24
PP_LDO6_RUIM_1V8
B 1
R1207
2.2K
1
R1208
2.2K
1
R1209
2.2K CELL
B
5% 5% 5% 1 C3001
1/32W 1/32W 1/32W 1.0UF
MF MF MF 10% CELL
2 01005 2 01005 2 01005 NC_J3000_5
2 16V
X5R
1
R3000
0402 15.00K
1%
5
1/32W
VCC VPP MF
CELL 2 01005
J3000
SIM-CARD-X113-X223
F-ST-SM
BRD_REV[2-0] S/W READ FLOW SIMCRD_RST_CONN 2 RESET SIMCRD_IO_CONN
52 28 24 IN I/O 6 BI 24 28 52
1. SET GPIO AS INPUT
DETGND
101 EVT 52 28 24
SIMCRD_CLK_CONN 3 CLK DETECT 7 SIM_TRAY_DETECT 24 28 52
IN OUT
2. ENABLE PU AND DISABLE PD
GND
GND
GND
GND
GND
3. READ CELL
1 C3002
9
10
11
12
4
8
100PF
5%
6.3V
2 CERM
01005
PAGE TITLE
SOC: MISC & ALIASES

DRAWING NUMBER SIZE

REVISION
R
A.0.0
TABLE_DASHBOARD_INFO NOTICE OF PROPRIETARY PROPERTY: BRANCH
CKPLUS RULE EXCEPTIONS REQUIRED THE INFORMATION CONTAINED HEREIN IS THE
SCHEMATIC DEFINED CONSTRAINTS (YES/NO) NO THE POSESSOR AGREES TO THE FOLLOWING: PAGE
12 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
343S0658 = TRISTAR 2, A1
998-5855 = TRISTAR 2, TC
343S0639 = TRISTAR 2, A0
343S0614 = TRISTAR 1
D D
TRISTAR
54
=PP3V0_S2R_TRISTAR
1 C1320 1 C1300 1 C1360
8.2PF 0.1UF 1.0UF
+/-0.5PF 20% 20%
2 16V 6.3V
NP0-C0G-CERM 2 X5R-CERM
10V
2 X5R-CERM
01005 01005 0201-1
54
=PP1V8_S2R_TRISTAR =PP3V3_ACC 54
1 C1321 1 C1301 1 C1302 1 C1322
8.2PF 0.1UF 0.1UF 8.2PF
VDD_1V8 F3
VDD_3V0 F4
ACC_PWR D5
+/-0.5PF 20% CRITICAL 10% +/-0.5PF
2 16V
NP0-C0G-CERM 2 6.3V
X5R-CERM 2 6.3V
CERM-X5R 2 16V
NP0-C0G-CERM
01005 01005 0201 01005
PPVBUS_PROT 46 52
CRITICAL
U1300 1 C1361
CBTL1610A1UK 1UF
10%
C3 WLCSP 2 25V
52 15 MIKEY_TS_P DIG_DP P_IN F6 X5R
C4 402
52 15 MIKEY_TS_N DIG_DN ACC1 C5 PPOUT_E75_ACC_ID1 43
A1 ACC2 E5 PPOUT_E75_ACC_ID2 43
USB_BB_P
C TO USB BB MUX
53 52 24
53 52 24 USB_BB_N B1
USB1_DP
USB1_DN DP1 A2 E75_DPAIR1_P 43
C
C2 DN1 B2 E75_DPAIR1_N 43
48 PMU_USB_BRICKID BRICK_ID
A3 DP2 A4 E75_DPAIR2_P 43
AP USB 52 4 USB_SOC_P USB0_DP
B3 DN2 B4 E75_DPAIR2_N 43
52 4 USB_SOC_N USB0_DN
E2 CON_DET_L E3 TS_CON_DET_L 43
52 5 UART6_TS_ACC_TXD UART0_TX
ACCESSORY UART
52 5 UART6_TS_ACC_RXD E1 UART0_RX POW_GATE_EN* D6 OVP_SW_EN_L 46
OUT
52 5 UART0_SOC_TXD F2 UART1_TX SWITCH_EN E4 RESET_SOC_L 4 8 10 24 48 52

IN
AP DEBUG UART F1
52 5 UART0_SOC_RXD UART1_RX HOST_RESET B6 TS2PMU_RESET_IN OUT 48
UART3_BB2SOC_TX D2 D3 I2C0_SDA_1V8
BB DEBUG UART 52 28 24 5 UART2_TX SDA 5 48 52
(T’S OFF TO H4A UART4) UART3_SOC2BB_TX D1 UART2_RX D4 I2C0_SCL_1V8
52 28 24 5 SCL 5 48 52
INT C6 GPIO_TS2SOC2PMU_INT
52 4 JTAG_SOC_TCK A5 JTAG_CLK OUT 5 48
BYPASS E6 TRISTAR_BYPASS
JTAG_SOC_TMS B5 JTAG_DIO
52 4
VOLTAGE=3V
DVSS
DVSS
DVSS
MIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=0.5MM
CRITICAL
F5
C1
A6
1 C1303
1.0UF
20% TRISTAR BYPASS FOR 3V LDO
2 10V
X5R-CERM
0201-1
B R1370
0.00 2
B
15 OUT L81_MBUS_REF 1
0%
1/32W
MF
01005
A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
IO: TRISTAR
DRAWING NUMBER SIZE

REVISION
R
A.0.0
13 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
54 =PP3V3_NAND
1 1 1 1 1 1 1 1 1 1 C1404
C1490 C1491 C1400 C1401 C1402 C1480 C1405 C1406 C1407 =PP1V8_NAND 12 48 54
27PF 27PF 10UF 10UF 10UF 10UF 1UF 1UF 1UF 0.47UF
5% 5% 20% 20% 20% 20% 20% 20% 20% 20%
16V 16V 6.3V 6.3V 6.3V 6.3V 4V 6.3V 6.3V 4V 1 1
2 NP0-C0G 2 NP0-C0G 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 X6S 2 X5R 2 X5R 2 X7S C1410 C1411 1 C1412 1 C1413 1 C1493 1 C1494
01005 01005 0402-2 0402-2 0402-2 0402-2 0204 0201 0201 0204 15UF 15UF 15UF 2.2UF 27PF 27PF
20% 20% 20% 20% 5% 5%
2 4V
X5R 2 4V
X5R 2 4V
X5R 2 4V
X5R-CERM 2 16V
NP0-C0G 2 16V
NP0-C0G
0402 0402 0402 0201 01005 01005
PPVDDI_NAND
LAYOUT NOTE FOR U1400 VDDI:
ENSURE TRACE INDUCTANCE < 2NH 1 1
C1492 C1450
C 5%
27PF 2.2UF
20%
C
2 16V
NP0-C0G 2 4V
X5R-CERM
01005 0201
OB8
OC8
OD8
OE0
OF8
OA8
B6
F2
M6
N1
N7
G0
VDDI
VCC VCCQ
CRITICAL
6 FMI0_AD<0> G3 IO0-0 OMIT
BI A5 FMI0_CE0_L
CE0*
6 BI FMI0_AD<1> H2 IO1-0 U1400 CLE0 A3 FMI0_CLE
IN 6 52
6 BI FMI0_AD<2> J3 IO2-0 LGA-12X17 IN 6
ALE0 C1 FMI0_ALE IN 6
FMI0_AD<3> K2
XXNM-XGBX8-MLC-PPN1.5-ODP
53 6 BI IO3-0 E3
WE0* FMI0_WE_L IN 6
6 FMI0_AD<4> L5 IO4-0
BI
6 FMI0_AD<5> K6 IO5-0
BI
J5 RE0 B4 NC_U1400_RE0
6 BI FMI0_AD<6> IO6-0
H6 RE0* C7 FMI0_RE_L IN 6
G1 DQS0 H4 FMI0_DQS IN 6 53
J1 DQS0* F4 NC_U1400_DQS0
6 BI FMI1_AD<2> L1 IO2-1
N3 R/B0* E5 TP_U1400_RB0 53
6 BI FMI1_AD<4> N5 IO4-1
CE1* C5 FMI1_CE0_L 6 52
FMI1_AD<5> L7 IN
6 BI IO5-1 C3
CLE1 FMI1_CLE IN 6
6 FMI1_AD<6> J7 IO6-1
BI D2 FMI1_ALE
G7 ALE1 IN 6
WE1* E1 FMI1_WE_L IN 6 =PP1V8_NAND 12 48 54
RE1 D4 NC_U1400_RE1
RE1* D6 FMI1_RE_L
B IN 6
1
R1460 1 C1460
B
DQS1 M4 FMI1_DQS IN 6 50K 0.01UF
1% 10%
DQS1* K4 NC_U1400_DQS1 1/32W
MF 2 6.3V
X5R
R/B1* E7 TP_U1400_RB1 53
2 01005 01005
PPVREF_FMI_NAND
VREF G5
53 TP_TCKC_U1400 OA0 TCKC ZQ A1 FMI_ZQ_U1400

53 TP_TMSC_U1400 OB0 TMSC
VSS VSSQ
1 1 1
R1454 R1461 C1461
B2
F6
L3
A7
M2
OC0
OD0
OE8
OF0
G8
243 50K 0.01UF
1% 1% 10%
1/32W 1/32W 6.3V
2 X5R
MF MF
01005
2 01005 2 01005
A SYNC_MASTER=MLB SYNC_DATE=05/04/2012 A
PAGE TITLE
NAND STORAGE
DRAWING NUMBER SIZE

REVISION
R
A.0.0
14 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TOUCH SUBSYSTEM
L1700
240OHM-350MA RCPT - MLB 998-4526 -> 516S1054
=PP5V25_GRAPE PP5V25_GRAPE_FILT
D 54
1
0201
2 13 52
(PLUG - FLEX 998-4527)
D
CRITICAL
1 C1700 1 C1701 1 C1702 J1700
27PF 1UF 1000PF 503304-2010
5% 10% 10%
16V
2 NP0-C0G
10V
2 X5R
16V
2 X7R-CERM F-ST-SM-1
22
01005 402 0201 R1752 21
0.00
0%
1/32W
MF PP3V0_S2R_HALL_FILT 2 1 GPIO_BTN_HOME_FILT_L
01005 52 13 13 52
5 DISPLAY_SYNC 1 2 52 DISPLAY_SYNC_R 4 3
5 SPI1_GRAPE_SCLK 1 2 52 SPI1_GRAPE_SCLK_R 6 5 NC_PMU_GPIO_HALL_IRQ_4

52 5 SPI1_GRAPE_MISO 8 7 PMU_GPIO_MB_HALL3_IRQ 48
R1753 5 SPI1_GRAPE_MOSI
10 9 PMU_GPIO_MB_HALL2_IRQ
0.00
0%
52 48
1/32W NOSTUFF 52 5 SPI1_GRAPE_CS_L 12 11 PMU_GPIO_MB_HALL1_IRQ 48

=PP1V8_S2R_GRAPE
54
CRITICAL
MF
01005
1 C1761 52 5 CLK_32K_SOC2CUMULUS 14 13
=PPVCC_MAIN_GRAPE 1 27PF 5 GPIO_GRAPE_IRQ_L

16 15
54
C1752 5% 52
1UF 2 16V
NP0-C0G 52 5 GPIO_GRAPE_RST_L 18 17 PP5V25_GRAPE_FILT 13 52
20% 01005
CRITICAL CRITICAL 2 6.3V 52 13 PP1V8_GRAPE_FILT 20 19
1
1 C1750 X5R
0201
0.1UF VDD
10% 23
16V
2 X5R-CERM U1700 24
0201 SLG5AP302
VCC_MAIN_GRAPE_RAMP TDFN
7 CAP D 3
=PP1V8_GRAPE 2 ON 5
52 PP1V8_GRAPE_SW
54 S
CRITICAL
1 CRITICAL GND 1 C1753
R1751 1 C1751
8
10UF
100K 4700PF 20%
1% 10% 2 10V
C 1/32W
MF
10V
2 X7R
201
X5R-CERM
0402-2 C
2 01005
L1760 R1790
GPIO_BTN_HOME_L 1 2 GPIO_BTN_HOME_R_L 1.00K2
1 GPIO_BTN_HOME_FILT_L
LAYOUT NOTE: 48 5 13 52
PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION 01005 1%

150OHM-25%-200MA-0.7DCR 1/32W
MF
1 C1760 01005
27PF
5%
2 16V
NP0-C0G
01005
0.38 DCR
L1701
240OHM-350MA
1 2 PP1V8_GRAPE_FILT 13 52
0201
1 C1703 1 C1704 1 C1705
27PF 1UF 1000PF
5% 20% 10%
16V
2 NP0-C0G
6.3V
2 X5R
16V
2 X7R-CERM
01005 0201 0201
B L1702
B
240-OHM-0.2A-0.8-OHM
=PP3V0_S2R_HALL 1 2 PP3V0_S2R_HALL_FILT
54 13 52
0201-2
1 C1706 1 C1707 1 C1708
27PF 1UF 1000PF
5% 20% 10%
16V
2 NP0-C0G
6.3V
2 X5R
16V
2 X7R-CERM
01005 0201 0201
PAGE TITLE
TOUCH: SUPPORT CKT & CONN

DRAWING NUMBER SIZE

REVISION
R
A.0.0
17 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
R1850
DMIC1_FF_SCLK 1
0.00 2 DMIC1_FF_SCLK_FILT
15
0%
1/32W
MF NOSTUFF
01005
1 C1850 P/N 510S0760 - MLB
27PF (P/N 510S0761 - FLEX)
5%
16V
2 NP0-C0G
01005 CRITICAL
J1800
AA07A-S016VA1
F-ST-SM-COMBO
18
17
15 DMIC1_FF_SD 2 1 CONN_HP_HS4_FILT 15 AUDIO_JACK_FLEX RET2

L1800 4 3 CONN_HP_HS4_REF_FILT 15 AUDIO_JACK_FLEX MIC1 PER DAVE BREECE
54
=PP1V8_DMIC 1 2 PP1V8_DMIC_FILT 6 5 CONN_HP_HS3_REF_FILT 15 AUDIO_JACK_FLEX MIC2
0201-2 5 GPIO_SOC2AJ_HS4_SHUNT_EN 8 7 CONN_HP_HS3_FILT 15 AUDIO_JACK_FLEX RET1
240-OHM-0.2A-0.8-OHM
5 GPIO_SOC2AJ_HS3_SHUNT_EN 10 9 CONN_HP_RIGHT_FILT 15
52 28 LAT_SW2_CTL 12 11 CONN_HP_LEFT_FILT 15
PP_LDO14_2V65 VOLTAGE=2.65V MIN_NECK_WIDTH=0.06 MM 14 13 CONN_HP_HEADSET_DET_FILT 15
1 C1800 40 39 33 32 25
16 15
27PF 52 28 24 LAT_SW1_CTL
5%
16V
2 NP0-C0G
01005 19
1 C1820 1 C1830 1 C1821 1 C1822 1 C1801 1 C1802 20
C 5%
56PF
2 16V
5%
56PF
2 16V
5%
56PF
2 16V
5%
56PF
2 16V
0.1UF
10%
2 6.3V
27PF
5%
2 16V
C
NP0-C0G NP0-C0G NP0-C0G NP0-C0G CERM-X5R NP0-C0G
01005 01005 01005 01005 0201 01005
B B
PAGE TITLE
AUDIO: HP FLEX CONN

DRAWING NUMBER SIZE

REVISION
R
A.0.0
14 OF 54
18 OF 121
IV ALL RIGHTS RESERVED
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
54 16 =PPVCC_MAIN_AUDIO
CRITICAL
C1904 1 1 C1909
54 15 =PP1V8_AUDIO NOTE:
0.1UF 4.7UF
1 1 10% 20%
C1902 C1915 10V 10V U1900 DECAPS CHANGED ON 5/24/12 PER RADAR #11485846 MIKEY BUS FILTER
0.1UF 0.1UF X5R-CERM 2 2 X5R-CERM
0201 0402
20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
01005 01005
VOLTAGE=4.2V SIGNAL_MODEL=EMPTY
MIN_NECK_WIDTH=0.15MM R1951
1 C1930
PPVCC_VPROG_CP 1.00 2 100PF
VOLTAGE=1.7V 1 5%
MIN_LINE_WIDTH=0.3MM PLACE R1930 & R1931 CLOSE TO U3600 25V
MIN_NECK_WIDTH=0.15MM 2 NP0-CERM
R1950
D 1
1.002 PP1V7_VCP
1 C1914
0.1UF
1%
1/20W
0201
MF-LF 1
R1930
12
0201
D
1 2
MF-LF 1% 0201 10%
10V R1953
1/20W CRITICAL CRITICAL 2 X5R-CERM 0 5% NOSTUFF
54 16 =PP1V7_VA_VCP 1 C1950 1 C1951 0201 5% 1/20W 1 C1931
4.7UF 1.0UF 1/20W 15 L81_MBUS_P MF MIKEY_TS_P BI 11 52
20% 20% MF
L81_MBUS_N 201 100PF MIKEY_TS_N
CRITICAL CRITICAL 6.3V 6.3V 2 201 15 5% BI 11 52
1 C1901 1 C1903 2 X5R
402
2 X5R
0201-1 VOLTAGE=4.2V R1931 25V
2 NP0-CERM
4.7UF 0.1UF GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.3MM 12 0201
20% 10% 52 15 MIN_NECK_WIDTH=0.15MM R1952 1 2
6.3V 10V 255K 2
2 X5R 2 X5R-CERM PPVCC_VPROG_MB_F PPVCC_VPROG_MB 5%
1
402 0201 1/20W SIGNAL_MODEL=EMPTY
GND_AUDIO_CODEC MF
52 15
1 C1913
1%
1/20W
VOLTAGE=4.2V
201 1 C1932
C1905 0.1UF 201
MF
MIN_NECK_WIDTH=0.15MM 100PF
10% 5%
4.7UF 10V 25V
2 NP0-CERM
2 1 L81_FLYP 2 X5R-CERM
0201 0201
0.3MM
VPROG_CP G10
G1
VCP0 G8
VCP1 G9
A9
VL A8
VP0 E8
VP1 E9
VPROG_MB H1
6.3V 20% 0.15MM
402 X5R
L81_FLYC
VA
VD
0.3MM CRITICAL
0.15MM
C1906 C1907
4.7UF 4.7UF
2 1 L81_FLYN CRITICAL 1 2 GND_AUDIO_CODEC 15 52
0.3MM
6.3V 20% 0.15MM H10 FLYP +VCP_FILT H9
U1900 L81_PVCP 0.15MM 0.30MM 20% 6.3V
402 X5R J10 L1920
FLYC CS42L81-CWZR-A1 GNDCP J9 X5R 402
R1920 240-OHM-0.2A-0.8-OHM
K10 FLYN WLCSP K9 L81_NVCP 3.3K 2
-VCP_FILT CRITICAL 1 2
SYM 1 OF 2 0.15MM 0.30MM C1908 15 CODEC_HP_DET 1 52 CODEC_HP_DET_R CONN_HP_HEADSET_DET_FILT IN 14
0201-2
NC_MIC1_BIAS NO_TEST=TRUE H2 MIC1_BIAS AOUT1+ F10 NC_LEFT_CH_OUT_P 4.7UF 5% NOSTUFF
R1901 1 2
1/32W
1
2.21K2 L81_MIC2_BIAS_IN 15 AIN1P
NO_TEST=TRUE E3 AIN1+ AOUT1_M F9
NO_TEST=TRUE
NC_LEFT_CH_OUT_N MF
01005
C1920
1
E4 NO_TEST=TRUE 20% 6.3V 4700PF
15 AIN1N
NO_TEST=TRUE
MF 201 AIN1- X5R 402 10%
1% 10V
1/20W 15 MIC1_BIAS_FILT
NO_TEST=TRUE H3 MIC1_BIAS_FILT 2 X7R
L81_MIC2_BIAS 201
C AOUT2+
D10 NC_RIGHT_CH_OUT_P
PLACE L1900 TO 1905 CLOSE
TO THE HP CONNECTOR
C
C1911 1 NO_TEST=TRUE
AOUT2- D9 NC_RIGHT_CH_OUT_N
1.0UF J3 NO_TEST=TRUE
20% MIC2_BIAS_IN L1900
6.3V FERR-33-OHM-0.8A-0.09-OHM
X5R 2 G4 MIC2_BIAS
0201-1 C1912
4.7UF K3 MIC2_BIAS_FILT_IN DP J4 L81_MBUS_P 15
1 2 CONN_HP_LEFT_FILT 14
OUT
1 2 F3 MIC2_BIAS_FILT DN K4 L81_MBUS_N 15
0201 MIN_LINE_WIDTH=0.20MM
L81_MIC2_BIAS_FILT_IN L81_MIC2_BIAS_FILT L81_AIN2_POS C1 AIN2+ HPOUTA J8 52 CODEC_HP_LEFT MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM
20%
6.3V L81_AIN2_NEG D1 AIN2M HPOUTB K8 52 CODEC_HP_RIGHT MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM
X5R L1901
402 HS3 J1 52 15 CODEC_HP_HS3 FERR-33-OHM-0.8A-0.09-OHM
C1916 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM TO HEADPHONE JACK
XW1902 HS4 K1 52 15 CODEC_HP_HS4 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM 1 2 CONN_HP_RIGHT_FILT
SHORT-8L-0.25MM-SM 0.1UF H4 OUT 14
1 2 NC_MIC3_BIAS NO_TEST=TRUE
MIC3_BIAS HS3_REF K7 MIN_LINE_WIDTH=0.20MM
52 15 CODEC_HP_HS4 2 1 HP_MIC_POS 0201
NOSTUFF 15 AIN3P NO_TEST=TRUE C3 AIN3+ HS4_REF J7
6.3V 10% C2 H8
0201 CERM-X5R 15 AIN3N NO_TEST=TRUE
AIN3- HPDETECT CODEC_HP_DET 15 L1902
15 MIC3_BIAS_FILT NO_TEST=TRUE G3 MIC3_BIAS_FILT FERR-33-OHM-0.8A-0.09-OHM
XW1903 C1917 1 2 CONN_HP_HS3_FILT IN 14
SHORT-8L-0.25MM-SM 0.1UF
1 2 LINEOUTA K6 NO_TEST=TRUE NC_CODEC_LINE_OUT_L 0201 MIN_LINE_WIDTH=0.50MM
52 15 CODEC_HP_HS3 2 1 HP_MIC_NEG
F4
NOSTUFF NC_MIC4_BIAS NO_TEST=TRUE
MIC4_BIAS LINEOUTB J6 NO_TEST=TRUE NC_CODEC_LINE_OUT_R
6.3V 10% AIN4P NO_TEST=TRUE D2 AIN4+ LINEOUT_REF H6
0201 CERM-X5R
15 L1903
15 AIN4N NO_TEST=TRUE E2 AIN4- FERR-33-OHM-0.8A-0.09-OHM
MIC4_BIAS_FILT NO_TEST=TRUE F2 MIC4_BIAS_FILT FILT+ E1 L81_FILT 1 2
15 CONN_HP_HS4_FILT IN 14
FILT- F1 CRITICAL 0201 MIN_LINE_WIDTH=0.50MM
1 C1910 CODEC_HP_HS3_REF 52
10UF MIN_LINE_WIDTH=0.15MM
C10 MIN_NECK_WIDTH=0.1MM L1904
GNDHS
GNDHS
NC_SPEAKER_VQ
GNDP
GNDD
GNDA
SPEAKER_VQ 20%
2 6.3V
CERM-X5R 120-OHM-210MA
0402 1 2 CONN_HP_HS3_REF_FILT IN 14
B
E10
A10
K2
J2
G2
B CODEC_HP_HS4_REF
52
MIN_NECK_WIDTH=0.1MM L1905
NOSTUFF VOLTAGE=0V 120-OHM-210MA
0.15MM
XW1900 0.20MM 1 2 CONN_HP_HS4_REF_FILT
SHORT-8L-0.25MM-SM IN 14
1 2 GND_AUDIO_CODEC15 52
MIC1_BIAS_FILT 15
CODEC_MIC_BIAS_FILT MIC3_BIAS_FILT 15 DIGITAL MIC TABLE_ALT_HEAD
GND0 C6 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
MAKE_BASE=TRUE 14 DMIC1_FF_SD R1912 1 2 22 L81_DMIC1_FF_SD B1 DMIC1_SD PART NUMBER
MIC4_BIAS_FILT IN D3
1 C1990 15 1/32W 5% MF 01005
B2 GND1
14 IN DMIC1_FF_SCLK R1913 1 2 22 L81_DMIC1_FF_SCLK DMIC1_SCLK D5
TABLE_ALT_ITEM
100PF 1/32W 5% MF 01005 GND2 155S0773 155S0453 L1904,L1905 RADAR:11100717

5% U1900 D6
16V GND3
2 NP0-C0G B7 DMIC2_SD CS42L81-CWZR-A1 TABLE_ALT_ITEM
01005 GND4 D7 338S1213 338S1116 U1900 RADAR:13373870 SSMC FAB

NC_DMIC2_SCLK NO_TEST=TRUE B6 DMIC2_SCLK WLCSP
GND5 D8
SYM 2 OF 2
GND6 E5
53 5 I2S0_CODEC_ASP_MCK C8 MCLK
AIN1P IN E6
15 GND7
5 I2S0_CODEC_ASP_BCLK A3 ASP_SCLK GND8 E7
CODEC_AIN AIN1N IN
15
5 I2S0_CODEC_ASP_LRCK B3 ASP_LRCK GND9 F5
MAKE_BASE=TRUE IN
1 AIN3P I2S0_CODEC_ASP_DOUT A2 ASP_SDIN GND10 F6
C1991 15 5 IN
100PF 5 I2S0_CODEC_ASP_DIN R1910 1 2 22 I2S0_CODEC_ASP_SDOUT A1 ASP_SDOUT GND11 F7
AIN3N IN
5% 15 1/32W 5% MF 01005
F8
16V GND12
2 NP0-C0G
01005 AIN4P 15 5 I2S2_CODEC_XSP_BCLK B4 XSP_SCLK GND13 G5
IN
A AIN4N 15
53 5 IN I2S2_CODEC_XSP_LRCK B5
A5
XSP_LRCK_FSYNC GND14 G6
G7
SYNC_MASTER=KAVITHA SYNC_DATE=01/18/2012 A
53 5 IN I2S2_CODEC_XSP_DOUT XSP_SDIN_DAC2_MUTE GND15 PAGE TITLE
5 IN I2S2_CODEC_XSP_DIN R1911
L81_MBUS_REF
1/32W 5%
1 2
MF
22
01005
I2S2_CODEC_XSP_SDOUT A4
K5
XSP_SDOUT
MBUS_REF
GND16
GND17
H5
H7
AUDIO: L81 CODEC
54 15 =PP1V8_AUDIO 11 IN DRAWING NUMBER SIZE
SPI2_CODEC_CS_L C5 J5
5 OUT
A6
CS* GND18
NOSTUFF 53 5 OUT SPI2_CODEC_SCLK CCLK REVISION
1 B8
R1940 53 5 IN SPI2_CODEC_MOSI CDIN R
A.0.0
1.00K SPI2_CODEC_MISO A7 CDOUT
5% 53 5 OUT
TSTI0 C4 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1/32W
MF
B9 TSTI1 C7 THE INFORMATION CONTAINED HEREIN IS THE 15 OF 54
2 01005 52 5 OUT GPIO_CODEC_IRQ_L INT* PROPRIETARY PROPERTY OF APPLE INC.
B10 TSTI2 D4 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
52 48 OUT PMU_GPIO_CODEC_HS_INT_L WAKE* I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 19 OF 121
48 PMU_GPIO_CODEC_RST_L C9 RESET* II NOT TO REPRODUCE OR COPY IT
IN SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RIGHT SPEAKER AMP I2C ADDRESS: 1000001X

54 16 15 =PPVCC_MAIN_AUDIO =PP1V7_VA_VCP 15 16 54
CRITICAL CRITICAL CRITICAL
L19_R_VBOOST
1 C2041 1 C2042 1 C2043 1 C2044 CRITICAL CRITICAL CRITICAL
1 C2092 1 C2045 1 C2091 1 C2094
4.7UF 4.7UF 4.7UF 0.1UF 1 C2046
20% 20% 20% 10% 0.1UF 10UF 10UF 10UF
10V
2 X5R-CERM 2 10V
X5R-CERM
10V
2 X5R-CERM 10V
2 X5R-CERM 10%
10V
20%
10V
20%
10V
20%
10V
0.1UF
2 X5R-CERM 2 X5R 2 X5R-CERM 2 X5R-CERM 10% CRITICAL
0402 0402 0402 0201 6.3V
A1
B1
F5
2 CERM-X5R
C1
D1
A4
A5
0201 603 0402-1 0402-1 C2047
0201
4.7UF
VA
D CRITICAL
VBST VP
1
20%
6.3V
2
X5R-CERM1
402
D
L2040
2.2UH-20%-3.3A-0.115OHM U2040 CRITICAL
CS35L19B-CWZR/C0 C2048
A2
1 2 L19_R_SWITCH WLCSP FILT+ F2 L19_R_FILT 4.7UF
TFA302610A-SM B2 SW VER1 LDO_FILT C5 L19_R_LDO_FILT 1 2
20% X5R-CERM1
I2C2_SDA_1V8 D5 6.3V 402 SPKR_R_VSENSE_N
52 16 5 SDA 16
VSENSE- E3
D6
52 16 5 I2C2_SCL_1V8 SCL VSENSE+ E2
A7 INT* 16 SPKR_R_VSENSE_P
5 GPIO_SPKAMP_RIGHT_IRQ_L ISENSE- F1 SPKR_R_SES_N
SIGNAL_MODEL=EMPTY
A6 RESET* ISENSE+ E1 SPKR_R_SES_P
GPIO_SPKAMP_RST_L
SIGNAL_MODEL=EMPTY
16 5
D7 ALIVE OUT+ D2 SPKR_R_P

GPIO_SPKAMP_KEEPALIVE
XW2041
52 16 5
OUT- C2
XW2040
SM
54 52 47 PP1V7_VA_VCP C7 ADO
IREF+ B7 L19_R_IREF
SM
53 16 5 I2S1_SPKAMP_MCK E7 MCLK
53 16 5 I2S1_SPKAMP_BCLK E6 SCLK
CRITICAL
53 16 5 I2S1_SPKAMP_LRCK F6 LRCK/FSYNC R2040 MIN_LINE_WIDTH=0.5 MM
0.1002 MIN_NECK_WIDTH=0.2 MM SPKR_R_CONN_P
53 16 5 I2S1_SPKAMP_DOUT F7 SDIN 1
MIN_LINE_WIDTH=0.5 MM 1%
E5 SDOUT 1 MIN_NECK_WIDTH=0.2 MM 1/4W
53 16 5 I2S1_SPKAMP_DIN R2041 MF
GNDP GNDA 44.2K
1%
1/20W
MF
0402
SPEAKER CONNECTOR
A3
B3
B4
B5
B6
C3
C4
D3
D4
C6
E4
F3
F4
2 201
C C
SPKR_R_CONN_P
XW2074
SM
16 SPKR_R_VSENSE_P 1 2 SIGNAL_MODEL=EMPTY
SPKR_R_CONN_N SPKR_R_CONN_N
MIN_LINE_WIDTH=0.5 MM XW2075
MIN_NECK_WIDTH=0.2 MM
SM 16 43 5216 43
52
16 SPKR_R_VSENSE_N 1 2 SIGNAL_MODEL=EMPTY 16 43 5216 43
52
SPKR_L_CONN_P 16 43 5216 43
52
XW2076 16 43 5216 43
SM 52
16 SPKR_L_VSENSE_P 1 2 SIGNAL_MODEL=EMPTY
SPKR_L_CONN_N
LEFT SPEAKER AMP I2C ADDRESS: 1000000X

16 SPKR_L_VSENSE_N
XW2077
1
SM
2 SIGNAL_MODEL=EMPTY
PLACE XWS CLOSE TO CONNECTOR

54 16 15 =PPVCC_MAIN_AUDIO =PP1V7_VA_VCP 15 16 54
L19_L_VBOOST NET_SPACING_TYPE=PWR
CRITICAL CRITICAL CRITICAL
1 C2051 1 C2052 1 C2053 1 C2054 CRITICAL CRITICAL CRITICAL
1 C2093 1 C2055 1 C2090 1 C2095
4.7UF 4.7UF 4.7UF 0.1UF 1 C2056
20% 20% 20% 10% 0.1UF 10UF 10UF 10UF
2 10V 2 10V 10% 0.1UF
X5R-CERM 2 10V X5R-CERM 2 10V 10V 20%
2 X5R-CERM 2 10V
20%
10V
20%
10V 10% CRITICAL
UPDATED: DEC 13
0402 X5R-CERM 0402 X5R-CERM 6.3V
0402 0201 X5R 2 X5R-CERM 2 X5R-CERM
A1
B1
F5
C1
D1
A4
A5
0201 2 CERM-X5R C2057

603 0402-1 0402-1 0201
4.7UF
VA 1 2
VBST VP
20% X5R-CERM1
6.3V 402 1. ALL THE EMI/DESSENSE FILTER COMPONENTS HAVE BEEN
L2050
2.2UH-20%-3.3A-0.115OHM U2050 CRITICAL REMOVED BASED ON PERFORMANCE ON J65
B 1 2 L19_L_SWITCH A2
CS35L19B-CWZR/C0
WLCSP FILT+ F2 L19_L_FILT
C2058
4.7UF
B
TFA302610A-SM B2 SW VER1 LDO_FILT C5 L19_L_LDO_FILT 1 2 2. THE CURRENT VERSION OF L19 IS B0 AND WILL CHANGE TO C0
20% X5R-CERM1
52 16 5 I2C2_SDA_1V8 D5 SDA 6.3V 402
SPKR_L_VSENSE_N
BY MARCH 2013. C0 FIXES PROCESS ISSUES.
VSENSE- E3
16
52 16 5 I2C2_SCL_1V8 D6 SCL VSENSE+ E2
5 GPIO_SPKAMP_LEFT_IRQ_L A7 INT* ISENSE- F1 SPKR_L_SES_N 16 SPKR_L_VSENSE_P
SIGNAL_MODEL=EMPTY
A6 RESET* ISENSE+ E1 SPKR_L_SES_P
SIGNAL_MODEL=EMPTY
16 5 GPIO_SPKAMP_RST_L
D7 ALIVE OUT+ D2 SPKR_L_P
52 16 5 GPIO_SPKAMP_KEEPALIVE
OUT- C2
XW2050
XW2051
C7 ADO
IREF+ B7 L19_L_IREF
SM
SM
53 16 5 I2S1_SPKAMP_MCK E7 MCLK
53 16 5 I2S1_SPKAMP_BCLK E6 SCLK
CRITICAL
53 16 5 I2S1_SPKAMP_LRCK F6 LRCK/FSYNC R2050
F7 SDIN 1
0.1002 MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM SPKR_L_CONN_P
53 16 5 I2S1_SPKAMP_DOUT
MIN_LINE_WIDTH=0.5 MM 1%
1
53 16 5 I2S1_SPKAMP_DIN E5 SDOUT R2051MIN_NECK_WIDTH=0.2 MM 1/4W MF
44.2K 0402
GNDP GNDA 1%
1/20W
MF
2 201
A3
B3
B4
B5
B6
C3
C4
D3
D4
C6
E4
F3
F4
A SYNC_MASTER=KAVITHA SYNC_DATE=01/18/2012 A
SPKR_L_CONN_N PAGE TITLE
MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM AUDIO: CS35L19A AMPS
DRAWING NUMBER SIZE

REVISION
R
A.0.0
20 OF 121
IV ALL RIGHTS RESERVED 16
4 OF 54
4
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
BUTTON CONNECTOR
(MOVED HERE TO SUPPORT COST FORMAT) 516S0828
(REF DES PRESERVED FOR LAYOUT) CRITICAL
J2960
503548-1010
F-ST-SM
L2960 11 12
240-OHM-0.2A-0.8-OHM R2900
1 2 GPIO_BTN_VOL_DOWN_R_L 1.00K2 1 2
5 GPIO_BTN_VOL_DOWN_L 1 52 GPIO_BTN_VOL_DOWN_L_FILT
0201-2 3 4
1% 52 GPIO_BTN_VOL_UP_L_FILT
L2961 1/32W
240-OHM-0.2A-0.8-OHM MF
01005
R2901 52 GPIO_BTN_SRL_L_FILT 5 6
GPIO_BTN_VOL_UP_R_L 1.00K2 7 8
C 5 GPIO_BTN_VOL_UP_L 1
0201-2
2 1
1%
9 10 C
L2962 1/32W
240-OHM-0.2A-0.8-OHM MF
01005
R2902
1 2 GPIO_BTN_SRL_R_L 1.00K2 13 14
48 5 GPIO_BTN_SRL_L 1
0201-2
1%
L2963 1/32W
240-OHM-0.2A-0.8-OHM MF
01005
R2903
GPIO_BTN_ONOFF_L 1 2 GPIO_BTN_ONOFF_R_L 1.00K2
1 52 GPIO_BTN_ONOFF_L_FILT
48 5
0201-2
1%
1/32W
MF 2 DZ2962 2
01005 DZ2960 201-1
201-1
12.8V-100PF 12.8V-100PF
1 1 DZ2961 2
C2960 C2961 1 C2962 1 C2963 DZ2963 2
82PF 82PF 201-1 201-1
5% 5% 82PF 82PF 1 12.8V-100PF 1 12.8V-100PF
5% 5%
2 25V
CERM 2 25V
CERM 25V
2 CERM
25V
2 CERM
0201 0201 0201 0201 1 1
B B
PAGE TITLE
BUTTON: CONN
DRAWING NUMBER SIZE

REVISION
R
A.0.0
21 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
EDP CONNECTOR SUPPORT PART NUMBER
155S0667
ALTERNATE FOR
PART NUMBER
155S0583
BOM OPTION REF DES COMMENTS:
RDAR://PROBLEM/8616060,
TABLE_ALT_HEAD
TABLE_ALT_ITEM
L2242,L2810,L2811,L2812,L2813,L2814,L2710,L2711,L2712,L6030,L6031
RADAR://PROBLEM/9015335
54 =PPVCC_MAIN_LCD
1 C2240 1
0.1UF
C2239
10% 0.1UF
10%
2 16V
X5R-CERM 2 16V
1
0201 OMIT X5R-CERM
0201
VDD
U2200 CRITICAL
D LCD_RAMP 7 CAP
SLG5AP304V
TDFN
D 3 L2201 D
FERR-120-OHM-1.5A
CRITICAL PPVCC_MAIN_LCD_SW PPVCC_MAIN_LCD_SW_CONN
18 5 GPIO_SOC2LCD_PWREN 2 ON S 5 1 2 18 52
IN
1 0402A
R2205 GND
100K CRITICAL 1 C2232
1 1 1 1
8
5% C2241 C2203 C2202 C2230 15PF
1/32W 3900PF 0.1UF 10UF 82PF 5%
MF
2 01005
10% 10% 20% 5% 2 16V
2 50V
X7R 2 16V
X5R-CERM 2 6.3V
CERM-X5R 2 25V
CERM
NP0-C0G-CERM
01005
0402 0201 0402 0201
REVIEW: 4700PF 0201 132S0187

RDAR://PROBLEM/12579948 P/N 516S1056
CRITICAL
LAYOUT NOTE:
J2201
AA07A-S032-VA1
PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION LCM_PWR_EN_RES F-ST-SM-1
R2291 34 33
18 5 OUT GPIO_SOC2LCD_PWREN 1 2
0.00
0% LCM_OFF_L 2 1
1/32W
MF EDP_HPD_EMI 4 3 EDP_DATA_EMI_CONN_N<3>
01005 18 IN 18 53
52 18 PPVCC_MAIN_LCD_SW_CONN 6 5 EDP_DATA_EMI_CONN_P<3> 18 53
IN IN
8 7
BACK-UP DELAYED PWREN CKT 10 9 EDP_DATA_EMI_CONN_N<2> IN 18 53
54 10 7 5 4 =PP1V8_SOC 12 11 EDP_DATA_EMI_CONN_P<2> IN 18 53
CRITICAL LCM_PWR_EN_OR_GATE 14 13
L2200 1 C2270 16 15 EDP_DATA_EMI_CONN_N<1>
C 220-OHM-1A 0.1UF
20%
LCM_PWR_EN_OR_GATE
18 17 EDP_DATA_EMI_CONN_P<1>
IN
IN
18 53
18 53
C
54 =PPLED_REG_A 1 2 PPLED_BACK_REG_A 18 52 2 6.3V
X5R-CERM 47 LED_IO_6_A 20 19
01005 CRITICAL IN
0402 LCM_PWR_EN_OR_GATE 22 21
6
74LVC1G32 47 IN LED_IO_5_A EDP_DATA_EMI_CONN_N<0> IN 18 53
1 C2233 1 C2221 2
8.2PF 56PF
SOT891
GATE2LCD_PWREN 1
R2290
2
47 IN LED_IO_4_A 24 23 EDP_DATA_EMI_CONN_P<0> IN 18 53
4 LED_IO_3_A 26 25
+/-0.5PF 2%
GPIO_SOC2LCD_PWREN U2201 47 IN
2 50V
C0G-CERM 2 50V
NP0-C0G-CERM 18 5 IN 1
0.00 47 LED_IO_2_A 28 27 EDP_AUX_EMI_CONN_N 18
NC
0% IN IN
201 0201 30 29
5 3 1/32W 47 IN LED_IO_1_A EDP_AUX_EMI_CONN_P IN 18
MF
01005 52 18 IN PPLED_BACK_REG_A 32 31
NC_U2201_5
36 35
REVIEW: CAN/SHOULD WE USE 132S0316, 0.1UF 20%, 01005

RDAR://PROBLEM/12579963
CRITICAL REVIEW: WILL THE DISPLAY INCLUDE A VOLTAGE DIVIDER
7 IN EDP_AUX_P C2250 1 20.1UF EDP_AUX_EMI_P L2242 EDP_AUX_EMI_CONN_P OUT 18
TO REDUCE THE 2.5V FROM THE TCON TO 1.8V TO THE AP?
01005 6.3V 20% X5R-CERM 2 3 RDAR://PROBLEM/12579981
0.1UF
7 IN EDP_AUX_N C2251 1 2 EDP_AUX_EMI_N 1 4 EDP_AUX_EMI_CONN_N OUT 18 L2240
01005 6.3V 20% X5R-CERM
1 1
TAM0605-4SM
SYM_VER-2
3.25-OHM-0.1A-2.4GHZ
240-OHM-25%-0.20A-1.0DCR R2250
R2241 R2243 1 2 7.5K 2
18 EDP_HPD_EMI EDP_HPD_2P5 1 EDP_HPD OUT 7
100K 100K
B 5%
1/32W
MF
5%
1/32W
MF
01005 5%
1/32W
MF
1
R2242
B
2 01005 2 01005
1 C2260 01005 20.0K
27PF 5%
5% 1/32W
2 16V
NP0-C0G
MF
01005 2 01005
CRITICAL
53 7 IN EDP_DATA_P<0> C2242 1 2 0.1UF 53 EDP_DATA_EMI_P<0>
L2212 EDP_DATA_EMI_CONN_P<0> OUT 18 53
01005 6.3V 20% X5R-CERM 2 3 NOTE:
PER GREG DE MERCEY, EDP_HPD PIN IS 2.5V TOLERANT
53 7 IN EDP_DATA_N<0> C2243 1 2 0.1UF 53 EDP_DATA_EMI_N<0> 1 4 EDP_DATA_EMI_CONN_N<0> OUT 18 53 HOWEVER TO BE CONSERVATIVE, DIVIDER CKT IS NOT REMOVED
01005 6.3V 20% X5R-CERM SYM_VER-2
TAM0605-4SM
3.25-OHM-0.1A-2.4GHZ
CRITICAL
53 7 IN EDP_DATA_N<1> C2244 1 2 0.1UF 53 EDP_DATA_EMI_N<1>
L2222 EDP_DATA_EMI_CONN_N<1> OUT 18 53
01005 6.3V 20% X5R-CERM 2 3
53 7 IN EDP_DATA_P<1> C2245 1 2 0.1UF 53 EDP_DATA_EMI_P<1> 1 4 EDP_DATA_EMI_CONN_P<1> OUT 18 53

01005 6.3V 20% X5R-CERM SYM_VER-2
TAM0605-4SM
3.25-OHM-0.1A-2.4GHZ
CRITICAL
53 7 IN EDP_DATA_N<2> C2246 1 2 0.1UF 53 EDP_DATA_EMI_N<2>
L2232 EDP_DATA_EMI_CONN_N<2> OUT 18 53
01005 6.3V 20% X5R-CERM 2 3
53 7 IN EDP_DATA_P<2> C2247 1 2 0.1UF 53 EDP_DATA_EMI_P<2> 1 4 EDP_DATA_EMI_CONN_P<2> OUT 18 53

01005 6.3V 20% X5R-CERM TAM0605-4SM
SYM_VER-2
3.25-OHM-0.1A-2.4GHZ
A SYNC_MASTER=J85 MLB_C SYNC_DATE=12/05/2012 A
PAGE TITLE
CRITICAL
53 7 IN EDP_DATA_N<3> C2248 1 2 0.1UF 53 EDP_DATA_EMI_N<3> L2202 EDP_DATA_EMI_CONN_N<3> OUT 18 53
VIDEO: EDP SUPPORT & CONN
01005 6.3V 20% X5R-CERM 2 3 DRAWING NUMBER SIZE

53 7 IN EDP_DATA_P<3> C22491 2 0.1UF 53 EDP_DATA_EMI_P<3> 1 4 EDP_DATA_EMI_CONN_P<3> OUT 18 53 REVISION
R
01005 6.3V 20% X5R-CERM TAM0605-4SM
SYM_VER-2
3.25-OHM-0.1A-2.4GHZ A.0.0
22 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D OSCAR VDDIO = 1.8V HIBERNATE (NEED TO WAKE HOST)

OSCAR D
OSCAR CORE = 1.2V HIBERNATE (NEED TO RUN IN S2R) APN 337S4416
54 =PP1V2_S2R_OSCAR =PP1V8_S2R_OSCAR 19 54
C2400 1 C2401 1
1.0UF 1.0UF
VDDC C1
VDDC C6
VDDIO C2
20% 20%
6.3V 2 6.3V 2
X5R X5R
0201-1 0201-1
REVIEW:NEED PU ON CS? CRITICAL

R2405
15.0 2
RDAR://PROBLEM/12579997 U2400 1 SPI_OSCAR_SCLK OUT 21
SPI_OSCAR2ACCEL_CS_L E3 LPC18A1UK-CPA1 A1 NC_ISP0_CAM_REAR_SCL 5%

21 OUT P0_0 P0_11 1/32W
E5 WLCSP B2 MF
21 OUT SPI_OSCAR2GYRO_CS_L P0_1 P0_12 SPI_OSCAR_SCLK_R 01005
21 ACCEL2OSCAR_INT1 E6 P0_2 P0_13 A4 SPI_OSCAR_MISO
IN IN 21
GYRO2OSCAR_INT2 C5 P0_3 P0_14 B3 SPI_OSCAR_MOSI_R
21 IN
D5 B4
R2406
21 IN GYRO2OSCAR_INT1 P0_4 P0_15 UART4_OSCAR2SOC_RXD OUT 5 53 15.0 2
E2 A5 1 SPI_OSCAR_MOSI IN 21
54 19 =PP1V8_S2R_OSCAR 21 IN ACCEL2OSCAR_INT2 P0_5 P0_16 UART4_SOC2OSCAR_TXD IN 5 53
D3 B5 5%
21 IN COMPASS2OSCAR_INT P0_6 P0_17 OSCAR2RADIO_CONTEXT_A OUT 28 44 52 1/32W
MF
1 R2400 21 SPI_OSCAR2COMPASS_CS_L D4 P0_7 P0_18 C3 OSCAR2RADIO_CONTEXT_B 01005
OUT OUT 28 44 52
100K 5 OSCAR_TIME_SYNC_HOST_INT E1 P0_8 P0_19 C4 I2C1_SOC2OSCAR_SWDIO_1V8 BI 5

OUT
5% A3 B6 NOTE: I2C1 IS ASSUMED TO USE PUSH-PULL INSTEAD OF OPEN-DRAIN
1/32W 48 5 OUT PMU_GPIO_OSCAR2PMU_HOST_WAKE P0_9 P0_20 I2C1_SOC2OSCAR_SWDCLK_1V8 IN 5
MF A2 D1
2 01005
NC_ISP0_CAM_REAR_SDA P0_10 P0_21 PMU_GPIO_CLK_32K_OSCAR IN 48 52
P0_22 A6 TP_OSCAR_P0_22
5 IN GPIO_OSCAR_RESET_L E4 RESET* R2450
0.00 2
DBGEN D2 GPIO_SOC2OSCAR_DBGEN_R 1 GPIO_SOC2OSCAR_DBGEN
C IN 5
C
VSS
VSS
0%
1/32W
MF
01005
B1
D6
REVIEW: N51 HAS OSCAR I2C CONNECTED TO RF CAM I2C
COMPARE SENSOR CONNECTIONS WITH N51, IDENTIFY AND UNDERSTAND DIFFERENCES
B B
A SYNC_MASTER=J72_MLB_C SYNC_DATE=11/26/2012 A
PAGE TITLE
SENSOR: OSCAR
DRAWING NUMBER SIZE

REVISION
R
A.0.0
24 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VGA FRONT CAMERA CONNECTOR
D L2600
D
240OHM-350MA
=PP2V9_CAM_FRONT 1 2 PP2V9_AVDD_CAM_FRONT_FILT
54 20
0201 VOLTAGE=2.9V
1 C2600 1 C2601 1 C2602 MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
56PF 1UF 1000PF NET_SPACING_TYPE=PWR
XW2600 5%
16V
20%
6.3V
10%
6.3V MAX_NECK_LENGTH=3 MM
SM 2 NP0-C0G
01005
2 X5R
0201
2 X5R-CERM
01005
L2610
1 2 GND_AVDD_CAM_FRONT 20 53 20 MIPI1C_CAM_FRONT_CLK_FILT_P 2 3 MIPI1C_CAM_FRONT_CLK_P OUT 7 53
VOLTAGE=0V
NET_SPACING_TYPE=GND 53 20 MIPI1C_CAM_FRONT_CLK_FILT_N 1 4 MIPI1C_CAM_FRONT_CLK_N 7 53
OUT
SYM_VER-2
TCM0605-1
90-OHM-50MA
L2611
53 20 MIPI1C_CAM_FRONT_DATA_FILT_P<0> 2 3 MIPI1C_CAM_FRONT_DATA_P<0> 7 53
OUT
L2601
240OHM-350MA
=PP1V8_CAM_FRONT MIPI1C_CAM_FRONT_DATA_FILT_N<0> 1 4 MIPI1C_CAM_FRONT_DATA_N<0>
54
1 2 PP1V8_CAM_FRONT_FILT 20
53 20
SYM_VER-2
OUT 7 53
TCM0605-1
0201
90-OHM-50MA
1 C2603 1 C2604 1 C2605
56PF 1UF 1000PF L2660
5% 20% 10%
16V
2 NP0-C0G
6.3V
2 X5R
6.3V
2 X5R-CERM
150OHM-25%-200MA-0.7DCR
01005 0201 01005 20 ISP1_CAM_FRONT_CLK_F_R 1 2 ISP1_CAM_FRONT_CLK_F 20
01005
C C
L2602 516S0869 PLUG FLEX

240-OHM-0.2A-0.8-OHM
516S0876 RCPT MLB
=PP3V0_ALS
54
1 2 PP3V0_ALS_FILT 20
0201-2 CRITICAL
1 C2606 1 C2607 1 C2608 J2601
503548-1820
56PF 1UF 1000PF F-ST-SM
5% 20% 10%
16V
2 NP0-C0G
6.3V
2 X5R
6.3V
2 X5R-CERM 20 19
01005 0201 01005
20 I2C3_SCL_1V8_F 2 1 I2C3_SDA_1V8_F 20
20 GPIO_ALS_IRQ_L_F 4 3 ISP1_CAM_FRONT_CLK_F_R 20
20 PP3V0_ALS_FILT 6 5
8 7 ISP1_CAM_FRONT_SHUTDOWN_L_F 20
53 20 MIPI1C_CAM_FRONT_DATA_FILT_P<0> 10 9 ISP1_CAM_FRONT_SDA_F 20
53 20 MIPI1C_CAM_FRONT_DATA_FILT_N<0> 12 11 ISP1_CAM_FRONT_SCL_F 20
14 13 PP2V9_AVDD_CAM_FRONT_FILT 20
53 20 MIPI1C_CAM_FRONT_CLK_FILT_P 16 15 GND_AVDD_CAM_FRONT 20
B U2600
400MHZ-0.1A-27PF 53 20 MIPI1C_CAM_FRONT_CLK_FILT_N 18 17 PP1V8_CAM_FRONT_FILT 20 B
1208
52 7 BI ISP1_CAM_FRONT_SDA IN1 OUT1 ISP1_CAM_FRONT_SDA_F 20 22 21
52 7 IN ISP1_CAM_FRONT_SCL IN2 OUT2 ISP1_CAM_FRONT_SCL_F 20
22 5 BI I2C3_SDA_1V8 IN3 OUT3 I2C3_SDA_1V8_F 20
52 7 IN ISP1_CAM_FRONT_CLK IN4 OUT4 ISP1_CAM_FRONT_CLK_F 20
GND
U2601
400MHZ-0.1A-27PF
1208
NC_U2601_1 IN1 OUT1 NC_U2601_5
22 5 IN I2C3_SCL_1V8 IN2 OUT2 I2C3_SCL_1V8_F 20
5 OUT GPIO_ALS_IRQ_L IN3 OUT3 GPIO_ALS_IRQ_L_F 20
52 7 IN ISP1_CAM_FRONT_SHUTDOWN_L IN4 OUT4 ISP1_CAM_FRONT_SHUTDOWN_L_F 20
GND
1
R2601 ISP1_CAM_FRONT_SHUTDOWN_L
100K
A 1%
1/32W
MF
LOW = SHUT DOWN CAMERA SYNC_MASTER=J85 MLB_C SYNC_DATE=12/03/2012 A
2 01005 HIGH = TURN ON CAMERA PAGE TITLE
CAMERA: FF-ALS CONN & FILTERS

DRAWING NUMBER SIZE

REVISION
R
A.0.0
26 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GYRO
L2702
120-OHM-25%-250MA-0.5DCR
54 =PP3V0_S2R_GYRO 1 2 PP3V0_GYRO =PP1V8_S2R_GYRO 54
01005
ACCELEROMETER 1
20%
C2721
6.3V
0.1UF
2 X5R-CERM
1 C2723
10UF
20%
6.3V
2 CERM-X5R
C2725
0.1UF
20%
6.3V
1
X5R-CERM 2
01005 0402-2 01005
D L2700
120-OHM-25%-250MA-0.5DCR D
54 =PP3V0_S2R_ACCEL 1 2 PP3V0_ACCEL =PP1V8_S2R_ACCEL 54
01005
C2700 1 C2701 1 C2750 1
10UF 0.1UF 0.1UF
7
20% 20% OMIT 20%
6.3V 6.3V 6.3V
CERM-X5R 2 X5R-CERM 2 VDD VDD_IO X5R-CERM 2
0402-2 01005 01005
CKPLUS_WAIVE=PWRTERM2GND
CRITICAL
U2700 GYRO_RES_VDD
AP2DHAB26TR
LGA
15
VDD 16
OMIT
1
19 SPI_OSCAR2ACCEL_CS_L 4 CS SCL/SPC 1 SPI_OSCAR_SCLK
IN IN 19 21
14 RES SDA/SDI/SDO 2 SPI_OSCAR_MOSI IN 19 21

R2757 RES/VDD VDD_IO
0.00 2 CRITICAL
13 RES SDO/SA0 3 SPI_OSCAR_MISO_ACCEL 1 SPI_OSCAR_MISO 19 21 U2720
0% AP3GDL20HAB18TR
12 RES 1/32W
MF LGA
01005
19 ACCEL2OSCAR_INT1 6 INT1 RES 10 19 SPI_OSCAR2GYRO_CS_L 5 CS SCL/SPC 2 SPI_OSCAR_SCLK IN 19 21
OUT IN
19 OUT ACCEL2OSCAR_INT2 5 INT2 RES 11 19 OUT GYRO2OSCAR_INT2 6 DRDY/
INT2 SDA/SDI/SDO 3 SPI_OSCAR_MOSI IN 19 21
R2727
8 0.00 2
GYRO_DEN DEN SDO/SA0 4 SPI_OSCAR_MISO_GYRO 1 SPI_OSCAR_MISO 19 21
GND 0%
7 INT1 1/32W
RES0 9
9
19 OUT GYRO2OSCAR_INT1 MF
01005
RES1 10
RES2 11
13 GND
12 GND
CAP 14 GYRO_PUMP
OMIT
1
1 C2726
R2750 11V CHARGE PUMP 0.1UF
0.00 10%
2 16V
C 0%
1/32W
MF
X5R-CERM
0201 C
2 01005
B COMPASS APN 338S1014

B
L2701 L2741
120-OHM-25%-250MA-0.5DCR 120-OHM-25%-250MA-0.5DCR
54 =PP3V0_S2R_COMP 1 2 PP3V0_COMP 21 PP1V8_COMP 1 2 =PP1V8_S2R_COMP 54
01005 01005
1 C2711
B1
C4
C2710 1
1.0UF 0.1UF
20% VDD VID 20%
6.3V 2 CRITICAL 2
6.3V
X5R X5R-CERM
0201-1 U2710 01005
21 GND_COMP AK8963C GND_COMP 21

CSP
D1 CAD0 SCL/SK A3 SPI_OSCAR_SCLK IN 19 21
D2 CAD1 SDA/SI A4 SPI_OSCAR_MOSI IN 19 21
NC_COMPASS_TST1 NO_TEST=TRUE C2 TST1 CSB* A2 SPI_OSCAR2COMPASS_CS_L 19

IN
R2747
B3 RSV 15.0 2
NC_COMPASS_RSV NO_TEST=TRUE SO B4 SPI_OSCAR_MISO_COMP1 1 SPI_OSCAR_MISO OUT 19 21
5%
1/32W
NC_COMPASS_TRG NO_TEST=TRUE C3 TRG DRDY A1 COMPASS2OSCAR_INT OUT 19 MF
01005
21 PP1V8_COMP D4 RST*
VSS
A TO VID WHEN NOT USED XW2700 A
C1
SHORT-10L-0.25MM-SM SYNC_MASTER=N/A SYNC_DATE=N/A

21 GND_COMP 1 2 PAGE TITLE
TIE CSB* TO VID FOR I2C MODE
XW2701
SHORT-10L-0.25MM-SM
SENSOR: ACCEL, COMPASS, GYRO
DRAWING NUMBER SIZE

REVISION
R
A.0.0
27 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PROX SENSOR
D D
54 22 =PP1V8_PROX VDRIVE FOR: I2C AND GPIO
PROX PROX
C2804 1 C2805 1
0.1UF 68PF
20% 5%
6.3V 6.3V
X5R-CERM 2 NP0-C0G 2
PROX 01005 01005
L2800
240-OHM-0.2A-0.8-OHM
54
=PP3V0_PROX 2 1 PP3V0_SENSOR_PROX_FILT 1.8 MA MAX
0201-2 PROX PROX PROX
C2800 1 C2801 1 C2806 1
2.2UF 0.1UF 68PF
10% 20% 5%
6.3V 6.3V 6.3V
X5R 2 X5R-CERM 2 NP0-C0G 2
402 01005 01005 I2C ADDRESS: 0101100+R/W
READ: 0X59, WRITE: 0X58
516S0872
C 54 22 =PP1V8_PROX C
D2
C2
PROX
PROX 1 PROX CRITICAL
R2800 J2800
2.0K VCC VDRIVE
PROX 503548-0620
1% PROX
1/32W U2800 CRITICAL CRITICAL F-ST-SM
MF
01005 2 AD7149 L2802 L2801 7 8
390NH-2%-170MA-4.0OHM 68NH-2%-320MA-1.0OHM
WLCSP
PROX_BIAS E3 BIAS 353S2964 CIN0 D3 2 1 CIN9 2 1 CIN9 SENSOR ELECTRODE PROX_CIN9_CONN 1 2 NC_J2800_2
NC
CRITICAL CIN1 A3 PROX_CIN1 0603 0402 CIN7 DUMMY PROX_CIN7_CONN 3 4 NC_J2800_4
20 5 I2C3_SDA_1V8 E1 SDA
BI
CIN2 B3 TP_PROX_CIN2 PROX_ACSHIELD_CONN 5 6 NC_J2800_6
I2C3_SCL_1V8 C1 SCLK CIN3 A4
20 5 IN NC PROX PROX
C3
VDRIVE RAIL
CIN4 9 10
D1 ADD0 NC CRITICAL CRITICAL
CIN5 A5 L2804 L2803
NC 390NH-2%-170MA-4.0OHM 68NH-2%-320MA-1.0OHM
B1 ADD1 CIN6 B4
NC
CIN7 B5 PROX_CIN7 2 1 CIN7 2 1
5 GPIO_PROX_IRQ_L A1 INT*
OUT
CIN8 C4 0603 0402
NC
PROX_GPIO A2 GPIO CIN9 C5 PROX_CIN9
INT* IS OPEN DRAIN PU RAIL MATCH VDRIVE D4
B2 CIN10 NC
NC TP D5
CIN11 NC
ACSHIELD
PROX 1 CIN12 E5
INT IS 1.8V LEVEL. PROX PROX NC PCB: ACSHIELD NEEDS TO BE
C2802 1 C2807 1 R2801
100K PROX A PLANE UNDER PROX_CIN NETS
0.01UF 27PF
GND
1% C2803 1
PROX GPIO WILL NOT BE USED.

10%
10V
1%
25V 1/32W 0.5PF 0.5 PF
JUST IN CASE
AND ALSO TIE TO CONNECTOR.
X5R-CERM 2 NP0-C0G 2 MF +/-0.05PF
THEREFORE,PROX GPIO IS NOT 0201 201 01005 2 25V NEED EXTERNAL
E4
E2
CONNECTED TO MLB INTERCONNECT. CERM 2 REF CAP TO MEASURE
201
B CHOSE CIN NUMBERS FOR LAYOUT EASE B

PROX PROX
CRITICAL CRITICAL
L2808 L2807
390NH-2%-170MA-4.0OHM 68NH-2%-320MA-1.0OHM
ACSHIELD_SB 2 1 ACSH_SB 2 1
0603 0402
PCB: ENSURE ACSHIELD PLANE UNDER

U3200, NO GND PLANE NEAR PROX_CIN NETS..

PAGE TITLE
SENSOR: PROX
DRAWING NUMBER SIZE

REVISION
R
A.0.0
28 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REAR CAMERA CONNECTOR
D L2902 APN: 516S0973 L2950 D

240OHM-350MA 150OHM-25%-200MA-0.7DCR
=PP1V8_CAM_REAR PLUG: 516S0974
54
1 2 PP1V8_CAM_REAR_FILT ISP0_CAM_REAR_CLK_F 1 2 ISP0_CAM_REAR_CLK 7 52
IN
0201 01005
1 C2972 1 C2906 1 C2907 1 C2908 CRITICAL
56PF 56PF 1UF 1000PF
5% 5% 10% 10% J2950
16V
2 NP0-C0G
16V
2 NP0-C0G 2 X5R
10V 6.3V
2 X5R-CERM
01005 01005 402 01005
AA07-S022VA1 L2911
F-ST-SM
24 2 3 MIPI0C_CAM_REAR_DATA_P<0> 7 53
OUT
23
1 4 MIPI0C_CAM_REAR_DATA_N<0> 7 53
ISP0_CAM_REAR_SCL 1 2 OUT
52 7 IN SYM_VER-2
TCM0605-1
L2903 52 7 BI ISP0_CAM_REAR_SDA 3 4
90-OHM-50MA
240OHM-350MA
52 7 ISP0_CAM_REAR_SHUTDOWN_L 5 6 53 MIPI0C_CAM_REAR_DATA_FILT_P<0>
=PP1V3_CAM_REAR PP1V3_CAM_REAR_FILT IN
1 2 7 8 MIPI0C_CAM_REAR_DATA_FILT_N<0>
54
0201 9 10
53
2
L2910 3 MIPI0C_CAM_REAR_CLK_P OUT 7 53
1 C2973 1 C2909 1 C2910 1 C2911 11 12 53 MIPI0C_CAM_REAR_CLK_FILT_P
56PF 56PF 1UF 1000PF CAM_REAR_VSYNC 13 14 53 MIPI0C_CAM_REAR_CLK_FILT_N
5% 5% 10% 10% 1 4
2 16V 2 16V 2 10V 2 6.3V 15 16 MIPI0C_CAM_REAR_CLK_N OUT 7 53
NP0-C0G NP0-C0G X5R X5R-CERM SYM_VER-2
01005 01005 402 01005 GND_CAM_AVDD 17 18 53 MIPI0C_CAM_REAR_DATA_FILT_P<1> TCM0605-1
19 20 MIPI0C_CAM_REAR_DATA_FILT_N<1> 90-OHM-50MA
GND_AF_AVDD 53
21 22
L2912
2 3 MIPI0C_CAM_REAR_DATA_P<1> 7 53
OUT
1 25
R2950
L2900 100K 1 C2980 26
240OHM-350MA 1% 1000PF 1 4 MIPI0C_CAM_REAR_DATA_N<1> OUT 7 53
1/32W 10%
=PP2V9_CAM_REAR 1 2 PP2V9_AVDD_CAM_REAR_FILT MF 6.3V
2 X5R-CERM
SYM_VER-2
TCM0605-1
C 54
0201 VOLTAGE=2.9V
MIN_LINE_WIDTH=0.6 mm
2 01005 01005 90-OHM-50MA C
1 C2970 1 C2900 1 C2901 1 C2902 MIN_NECK_WIDTH=0.2 mm
56PF 56PF 1UF 1000PF MAX_NECK_LENGTH=3 MM
5% 5% 10% 10%
16V
2 NP0-C0G XW2950
SM
16V
2 NP0-C0G 2 X5R
10V 6.3V
2 X5R-CERM
01005 01005 402 01005
1 2
VOLTAGE=0V
NET_SPACING_TYPE=GND
MAX_NECK_LENGTH=5 MM
L2901
240OHM-350MA
=PP2V6_CAM_REAR_AF 1 2
PP2V6_CAM_REAR_AF_FILT
54
0201
VOLTAGE=2.6V
1 C2971 1 C2903 1 C2904 1 C2905 MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
56PF 56PF 1UF 1000PF NET_SPACING_TYPE=PWR
5% 5% 10% 10% MAX_NECK_LENGTH=3 MM
16V
2 NP0-C0G XW2951
SM
16V
2 NP0-C0G
10V
2 X5R
6.3V
2 X5R-CERM
01005 01005 402 01005
1 2
VOLTAGE=0V
NET_SPACING_TYPE=GND
B B
PAGE TITLE
CAMERA: REAR CONN & FILTERS

DRAWING NUMBER SIZE

REVISION
R
A.0.0
29 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AP INTERFACE & DEBUG CONNECTORS DEBUG CONNECTOR

=PPBATT_VCC_BB 25 33 34 35 36 37 38 54
IN
NOSTUFF
J3003
AXE654124
D 56
M-ST-SM
55 D
2 1
4 3
6 5
52 26 PS_HOLD_PMIC 8 7 GPIO_SOC2BB_RST_L OUT 5 26 52
OUT
XW3002 52 26 5 OUT GPIO_SOC2BB_RADIO_ON_L 10 9 PP_SMPS3_MSME_1V8IN 24 25 27 28 30 52
SHORT-10L-0.25MM-SM PMU_GPIO_PMU2BBPMU_RST_L 12 11 RESET_SOC_L 11 48 52
52 48 26 OUT OUT 4 8
53 52 11 USB_BB_N 1 2 10 CKPLUS_WAIVE=SINGLE_NODENET
BI PMIC_RESOUT_L 14 13
27 26 IN
NOSTUFF 16 15 UART3_BB2SOC_TX
PROBE POINTS 18 17 GPIO_DEBUG_LED
IN
IN
5 11 28 52
28
27 USB_BB_DEBUG_N 20 19
BI
PP3000 USB_BB_DEBUG_P 22 21 UART3_SOC2BB_TX
P4MM 27 BI OUT 5 11 28 52
SM
PP
1 BB_ERROR_FLAG 28 52 27 OUT DEBUG_RST_L 24 23 UART3_BB2SOC_RTS_L IN 5 28
52 27 5 BB_JTAG_TMS 26 25 UART3_SOC2BB_RTS_L 5 28
PP3001 OUT OUT
XW3003 BB_JTAG_TRST_L 28 27
P4MM SHORT-10L-0.25MM-SM 52 27 5 OUT
SM
1 SLEEP_CLK_32K 26 27 53 52 11 USB_BB_P 1 2 52 27 5 BB_JTAG_TCK 30 29
PP BI OUT
52 27 5 BB_JTAG_TDO 32 31
PP3002 NOSTUFF IN
P4MM 52 27 5 BB_JTAG_TDI 34 33 PMU_GPIO_BB_VBUS_DET 27 48 52
SM
OUT OUT
1 PMIC_SSBI 26 27 52 27 BB_JTAG_RTCLK 36 35
PP OUT
38 37
PP3003
P4MM 52 28 24 14 OUT LAT_SW1_CTLGPIO48/BOOT_CONFIG_6 40 39
SM
PP
1 19P2M_MDM 26 27
42 41
40 39 28 OUT ANT_SEL_2 GPIO54/BOOT_CONFIG_0 44 43
PP3008 PMU_GPIO_BB2PMU_HOST_WAKE 46 45
P4MM 52 48 28 IN HSIC2_BB2SOC_DEVICE_RDY IN 5 28
SM
1 WTR_SSBI_TX_GPS 28 29 40 39 33 28 24 ANT_SEL_1 GPIO53/BOOT_CONFIG_1 48 47
PP OUT
GPIO_51 GPIO51/BOOT_CONFIG_3 50 49 GPIO_BB2SOC_RESET_DET_L
C PP3009
P4MM
SM
28 OUT
52 51 HSIC2_SOC2BB_HOST_RDY
IN
IN
5 28
5 28
C
1 WTR_SSBI_PRX_DRX 28 29
54 53
PP
PP3010 58 57
P4MM
SM
1 WTR_RX_ON 28 29
PP
PP3011
P4MM
SM
1 WTR_RF_ON 28 29
PP
PP3012
P4MM
SM
1 UART_WLAN2BB_LTE_COEX 28 44
PP PP_SMPS3_MSME_1V8 24 25 27 28 30 52 GPIO/BOOT_CONFIG CONFIGURATION
PP3013
P4MM BOOT_CONFIG 6 5 4 3 2 1 0
SM
1 UART_BB2WLAN_LTE_COEX NOSTUFFNOSTUFF BOOT OPTIONS SW REGISTER
PP 28 44 1 1
R3002 R3003 VALUE 47 48 49 50 51 52 53 54 55
10K 10K BOOT_DEFAULT_OPTION
5% 5% 0X00 X 0 0 0 0 0 0 0 X
1/32W 1/32W
MF MF
2 01005 2 01005 BOOT_NAND_OPTION 0X01 X 1 0 0 0 0 0 1 X
BOOT_HSIC_OPTION 0X02 X 1 0 0 0 0 1 0 X
LAT_SW1_CTL GPIO48/BOOT_CONFIG_6
52 28 24 14
GPIO53/BOOT_CONFIG_1 BOOT_USB_OPTION 0X03 X 1 0 0 0 0 1 1 X
40 39 33 28 24 ANT_SEL_1
ENABLE SAHARA PROTOCOL 0X08 X 1 0 0 1 0 X X X
J3002
MM4829-2702
F-ST-SM
B NOSTUFF
1 HSIC2_BB_DATA 4 27 53
B
2
3
4
PP_LDO6_RUIM_1V8 10 25 27 52
SIM CARD ESD PROTECTION
CELL
1 CELL CELL
C3000 J3001
12V-33PF
01005-1 U3000 U3002 MM4829-2702
F-ST-SM
2 ESD0P2RF-02LS ESD0P2RF-02LS
NOSTUFF HSIC2_BB_STB
52 28 10 SIMCRD_IO_CONN 1 2 2 1 SIM_TRAY_DETECT 10 28 52
1 4 27 53
TSSLP-2-1 TSSLP-2-1
2
3
4
CELL CELL
U3001 U3003
ESD0P2RF-02LS ESD0P2RF-02LS
52 28 10 SIMCRD_RST_CONN 1 2 2 1 SIMCRD_CLK_CONN 10 28 52
TSSLP-2-1 TSSLP-2-1
A A
PAGE TITLE
CELL:AP INTERFACE & DEBUG CONNECTORS

DRAWING NUMBER SIZE

REVISION
R
A.0.0
30 OF 121
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 24 OF 54
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PMU (1 OF 2)
PP_LVS1 OUT 27
PP_VREG
INTERNAL USE ONLY
D 1 C3230
1.0UF
D
20%
6.3V
2 X5R
L3200 0201-1
2.2UH-20%-1.2A-0.15OHM
1 2 PP_SMPS1_MSMC_1V05 OUT 27 52
0806
CRITICAL 1 C3229
22UF
20%
6.3V
2 X5R-CERM-1
603
L3201 S1_GND 25 26
2.2UH-20%-1.2A-0.15OHM
1 2 PP_SMPS2_RF1_1V3 OUT 27 30
0806
CRITICAL 1 C3228
22UF
20%
6.3V
2 X5R-CERM-1
603
L3202 S2_GND 25 26
REF_BYP U3300 2.2UH-20%-1.2A-0.15OHM
PM8018-0 1 2 PP_SMPS3_MSME_1V8 24 25 27 28 30 52
OUT
1 C3209 BGA 0806
0.1UF VREG CRITICAL
20% (SYM 5 OF 5) 1 C3227
XW3200 6.3V
2 X5R-CERM CRITICAL
1 C3226 0.1UF
SHORT-10L-0.1MM-SM 28 REF_BYP VOUT_LVS1 53 22UF
01005 20%
1 2 34 REF_GND 20% 4V
2 6.3V
X5R-CERM-1
2 X5R
01005
REF_GND VREG_RFCLK 13 603
S3_GND NOSTUFF
C 54 38 37 36 35 34 33 24 IN =PPBATT_VCC_BB 104 VDD_S1 92 PP_VSW_S1 L3203
2.2UH-20%-1.2A-0.15OHM
25 26
C
VSW_S1 97
1 2 PP_SMPS4_RF2_2V05 OUT 25 30 52
1 C3200 1 C3201 1 C3202 1 C3203 VREG_S1 79
0806
10UF 10UF 10UF 56PF 95 VDD_S2 90 PP_VSW_S2 CRITICAL
20% 20% 20% 5%
2 6.3V 2 6.3V 2 6.3V 2 16V VSW_S2 102 1 C3225
CERM-X5R CERM-X5R CERM-X5R NP0-C0G
0402-2 0402-2 0402-2 01005
VREG_S2 83 22UF
20%
6 42 6.3V
2 X5R-CERM-1
18 VSW_S3 48 PP_VSW_S3 603
VDD_S3 S4_GND
24 VSW_S5_2 100 L3204 25 26
VREG_S3 12 2.2UH-20%-2.34A-0.113OHM
98 VDD_S4 81 PP_VSW_S4 1 2 PP_SMPS5_DSP_1V05 25 52
OUT
VSW_S4 87 2520-SM
105 CRITICAL
VREG_S4 1 C3224
89 82 PP_VSW_S5 22UF
VDD_S5 VSW_S5 20%
101 88 6.3V
2 X5R-CERM-1
VREG_S5 76 603
1 C3204 1 C3205 1 C3206 1 C3207 1 C3208 S5_GND
4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 25 26
20% 20% 20% 20% 20%
10V 10V 10V 10V 10V INTERNAL USE ONLY
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM PP_LDO1
8 VDD_XO VREG_XO 20 52
0402 0402 0402 0402 0402
44 VDD_L2_L3 VREG_L2 31 PP_LDO2_XO_HS_1V8 OUT 27
25 S1_GND 25 S2_GND 25 S3_GND 25 S4_GND 25 S5_GND 32 PP_LDO3_AMUX_1V8
26 26 26 26 26 VREG_L3 OUT 26 27
78 VDD_L4 VREG_L4 84 PP_LDO4_VDDA_3V3 OUT 27
VREG_L5 11 PP_LDO5_GPS_LNA_2V5 OUT 41

5 VDD_L5_L6_L13_L14 VREG_L6 17 PP_LDO6_RUIM_1V8 OUT 10 24 27 52
VREG_L13 23 PP_LDO13_VDDPX_2V95 OUT 27
VREG_L14 29 PP_LDO14_2V65 14 32 33 39 40
B 52 30 25 IN
PP_SMPS4_RF2_2V05
PP_SMPS3_MSME_1V8
75
58
VDD_L7 VREG_L7 63
54
PP_LDO7_DAC_1V8
PP_LDO8_VDDPX_1V2
OUT
OUT 27 B
52 30 28 27 25 24 IN VDD_L8 VREG_L8 OUT 27
70 VDD_L9 VREG_L9 77 PP_LDO9_PLL_1V05 OUT 27
52 25
PP_SMPS5_DSP_1V05 59 VDD_L10_L11 VREG_L10 65 PP_LDO10_ADSP_1V05 27
IN OUT
VREG_L11 55 PP_LDO11_MDSP_FW_1V05 OUT 27
64 VDD_L12 VREG_L12 43 PP_LDO12_MDSP_SW_1V05 OUT 27
1 C3211 1 C3213 1 C3215 1 C3216 1 C3218 1 C3220 1 C3222 1 C3231

1.0UF 1.0UF 1.0UF 1.0UF 10UF 10UF 10UF 1.0UF
20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
X5R
0201-1 0201-1 0201-1 0201-1 0402-2 0402-2 0402-2 0201-1
1 C3210 1 C3212 1 C3214 1 C3217 1 C3219 1 C3221 1 C3223

1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20%
2 6.3V
X5R 6.3V
2 X5R
6.3V
2 X5R
6.3V
2 X5R
6.3V
2 X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
0201-1 0201-1 0201-1 0201-1 0201-1 0402-2 0402-2
A A
PAGE TITLE
CELL: BASEBAND PMU (1 0F 2)
DRAWING NUMBER SIZE

REVISION
R
A.0.0
32 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PMU (2 OF 2) PA_ID MAV VER

0.1V 8.7
27 26 25
PP_LDO3_AMUX_1V8 0.3V 8.6
IN
1
1
R3306
0.5V 8.5
R3304
BOARD_ID REVISION 100K 1%
100K
1.1V 7.7
1% 1/32W
D 0.7V PROTO1 1/32W

MF
2 01005
MF
2 01005
1.3V 7.6
D
0.9V PROTO2 PROTO2
BOARD_ID PA_ID
1.5V 1.5V 7.5
1
1.1V EVT1 1
R3305 R3307
499K
100K 1%
1%
1.3V EVT2 1/32W
MF
1/32W
MF U3300
2 01005
2 01005 PM8018-0
1.5V DVT BGA
MPP MISC
(SYM 4 OF 5)
1.7V PVT 85 MPP_01
CRITICAL
GPIO_01 33
NC
67 MPP_02 GPIO_02 38
NC
VDDPX_BIAS 66 MPP_03 GPIO_03 50
27 OUT NC
72 MPP_04 GPIO_04 60
NC NC
BB GPIO_29 PRODUCT_ID NC
73 MPP_05 GPIO_05 71
NC
VREF_DAC_BIAS 80 MPP_06 GPIO_06 49
28 IN NC
1 (1.8V) JXX
0 (NC, PD) NXX
R3300
GPIO_SOC2BB_RST_L 1
1.00K2 AP SECTION NEEDS ITS OWN THERMISTOR PLACED NEAR THE PA’S.
52 24 5 IN
5%
1/32W
MF
U3300
01005 PM8018-0
BGA
CONTROL
R3301 (SYM 1 OF 5)
20.0K2 PS_HOLD_PMIC 47 PS_HOLD LED_DRV_N 86 NC
52 24
PS_HOLD
C 28 IN
1
5%
1/32W
C
MF
01005
52 24 5 GPIO_SOC2BB_RADIO_ON_L 69 KPD_PWR* PON_RESET* 4 PMIC_RESOUT_L 24 27
IN OUT
52 48 24 IN PMU_GPIO_PMU2BBPMU_RST_L16 PM_RESIN_N
PM_USR_INT_N 21 PM_USR_IRQ_L OUT 28
62
OPT_1 PM_MDM_INT_N 14 PM_MDM_IRQ_L
NC OUT 28
74 OPT_2
NC
PON_TRIG 41
27 24 PMIC_SSBI 68 SSBI BAT_ID 35
BI
GND NEEDS TO BE CLEARED UNDER THIS CRYSTAL

TO MINIMIZE THERMAL DRIFT
Y3300
19.200MHZ
2.0X1.6-SM
1 3 19P2M_XTAL_IN
4 2 U3300
CRITICAL PM8018-0
BGA
CLOCKS
(SYM 2 OF 5)
1 XTAL_19M_IN
19P2M_XTAL_OUT 2 XTAL_19M_OUT XO_OUT_A0 19 19P2M_WTR 29
OUT
XO_OUT_D0 25 19P2M_MDM 24 27
B XW3300
27 26 25 IN
PP_LDO3_AMUX_1V8 OUT
B
SM
U3300 1
R3303 3 XTAL_32K_IN
1 2 XO_OUT_A1 37 NC
PM8018-0 100K
BGA 1% NC 15 XTAL_32K_OUT
INPUT PWR XW3301 1/32W XO_OUT_D0_EN 9 19P2M_CLK_EN 27
(SYM 3 OF 5) MF IN
SHORT-10L-0.25MM-SM
91 1 2 2 01005 45 GND1
GND_S1 25 S1_GND
103
27 GND0 SLEEP_CLK 26 SLEEP_CLK_32K 24 27
OUT
GND_S2 96 25 S2_GND XW3302 XO_THERM_Y1 10 XO_THERM
SM
30
S3_GND 1 2 22 XOADC_GND
GND_S3 36
25 1 C3300
93 1000PF RSVD 7
10%
GND_S4
25 S4_GND XW3303 6.3V
99 SHORT-10L-0.25MM-SM
2 X5R-CERM
01005
GND_S5 94 25 S5_GND 1 2
39 XW3304
SM XO_GND
51
1 2
57 VCOIN 61
NC
56 2
GND
46 XW3305
SHORT-10L-0.1MM-SM
52
40 1
A A
PAGE TITLE
CELL: BASEBAND PMU (2 OF 2)

DRAWING NUMBER SIZE

REVISION
R
A.0.0
33 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BASEBAND (1 OF 2)
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST. U3400
52 27 25 IN PP_SMPS1_MSMC_1V05 MDM9615M
27 25 IN PP_LDO8_VDDPX_1V2 27 25 IN PP_LDO4_VDDA_3V3 BGA
1 C3400 1 C3401 1 C3402 1 C3403 1 C3404 (6 OF 6)
1.0UF
20% 20%
1.0UF 1.0UF
20%
1.0UF
20%
1.0UF
20%
1 C3431 1 C3432 1 C3433 1 C3434 A21 GND M14
6.3V 6.3V 6.3V 6.3V 6.3V 1.0UF 0.22UF 1.0UF 0.22UF CRITICAL
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 20% 20% 20% 20% AA1 M15
0201-1 0201-1 0201-1 0201-1 0201-1 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R
AA21 M16
0201-1 01005 0201-1 0201
B2 M17
D B7
B11
M19
N6
D
PP_LDO9_PLL_1V05 PP_LDO10_ADSP_1V05 PP_LDO11_MDSP_FW_1V05
27 25 IN 27 25 IN 27 25 IN B14 N7
1 C3414 B15 N10
1 C3405 1 C3406 1 C3407 1 C3408 1 C3413 1.0UF
1 C3418 1 C3419 1 C3420
1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 20% 1.0UF 1.0UF 1.0UF C19 N11
20% 20% 20% 20% 20% 6.3V 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 2 X5R 6.3V 6.3V 6.3V F6 N14
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 0201-1 2 X5R 2 X5R 2 X5R
0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 F7 P6
F10 P10
F15 P11
F16 GND R6
PP_SMPS3_MSME_1V8 PP_SMPS3_MSME_1V8 PP_LDO12_MDSP_SW_1V05 F19 R10
52 30 28 27 25 24 IN 27 25 24 IN 27 25 IN
52 30 28 G2 R11
1 C3409 1 C3410 1 C3411 1 C3412 1 C3415 1 C3416 1 C3417 G6 R15
1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF G10 R16
20% 20% 20% 20% 20% 20% 20%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R G11 R17
0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 0201-1
G15 R19
G16 T10
G17 T12
G20 T13 U3400
H6 T14 MDM9615M
BGA
U3400 H10 GND U2 (2 OF 6) R3403
MDM9615M H11 V19 EBI1_EBI2
EBI1_CAL C21 EBI1_CAL 1
240 2
BGA H15
(5 OF 6) 1%
H16 F11 1/32W
PWR D21 EBI2_NAND_CS* EBI2_AD_0 J20 MF
52 27 25 IN
PP_SMPS1_MSMC_1V05 F8 AA20 PP_SMPS3_MSME_1V8 IN 24 25 27 28 30 52 J6 J16 NC NC 01005
E19 EBI2_OE* EBI2_AD_1 J19
F9 B19 J7 K16 NC NC
PP_SMPS1_MSMC_1V05 D20 EBI2_WE* EBI2_AD_2 G19
F12 VDD_DDR F20 J10 L16 NC NC
C 52 27 25 IN
F13 M20 J11 T6 NC
D19 EBI2_BUSY* EBI2_AD_3
EBI2_AD_4
H20
J21
NC C
1 C3421 F14 J14 T7 NC
EBI2_AD_5 H19
1.0UF G9 C5 PP_LDO10_ADSP_1V05 IN 25 27 J15 T11 NC
20% C20 EBI2_CLE* EBI2_AD_6 H21
6.3V
2 X5R G12 C6 K6 U9 NC NC
GND_ANA E20 EBI2_ALE* EBI2_AD_7 E21
0201-1 H9 E6 K7 U12 NC NC
VDD_ADSP
H12 E7 K10 W7
J8 F5 K11 W14
J9 K14 Y7
J12 T15 PP_LDO11_MDSP_FW_1V05 IN 25 27
K15 Y11
J13 T16 K20 Y15
K8 T17 L2 Y18
K9 U14 L6 U13
K12 VDD_MDSP_FW U15 L7 W13
K13 U16 L10
L8 U17 L11
VDD_CORE
L9 U19 L14
L12 T19 L15
L13 M6
M8 N15 PP_LDO12_MDSP_SW_1V05 25 27 M7
IN
M9 N16 M10
M12 N17 PP_LVS1 IN 25 M11
M13 N19
1
N8 VDD_MDSP_SW P15 R3400
N9 P16 470K
5%
N12 P17 1/32W
MF
N13 P19 2 01005 U3400
B P9
P12
MDM9615M
BGA
B
VDD_QFUSE_PRG B13
R9 (1 OF 6)
R12 PP_LDO2_XO_HS_1V8 DIGITAL
VDD_USB_1P8 E12 IN 25 26 24 IN PMIC_RESOUT_L Y20 RESIN* RESOUT* U20 NC
T8 VDD_USB_3P3 E10 PP_LDO4_VDDA_3V3 IN 25 27 52 24 IN DEBUG_RST_L Y4 SRST*
T9 1 C3422 26 24 SLEEP_CLK_32K AA19 SLEEP_CLK
IN
VDD_HVPAD_BIAS E16 VDDPX_BIAS 26
1.0UF
IN 20%
27 25 IN
PP_LDO9_PLL_1V05 C17 6.3V
2 X5R 52 24 5 IN BB_JTAG_TCK Y3 TCK TDO AA3 BB_JTAG_TDO OUT 5 24 52
C18 K17 PP_LDO9_PLL_1V05
1 C3423 0201-1 BB_JTAG_TDI AA2 TDI RTCK Y2 BB_JTAG_RTCLK
IN 25 27
0.1UF 52 24 5 IN OUT 24 52
E17 VDD_PLL1 L17 20% 52 24 5 IN BB_JTAG_TMS W4 TMS R3402
PP_LDO3_AMUX_1V8 2 4V
X5R 50_HSIC_CAL 240
F17 VDD_PLL2 W12 IN 25 26 52 24 5 IN BB_JTAG_TRST_L AA4 TRST* HSIC_CAL A8 1 2
01005
G7 NOSTUFF HSIC_DATA C7 HSIC2_BB_DATA 4 24 53 1%
BI 1/32W
G8 VDD_A2 U6 PP_LDO7_DAC_1V8 25 52 TP_BB_TEST_MODE_0 W20 MODE_0 HSIC_STB B8 HSIC2_BB_STB 4 24 53 MF
IN BI 01005
G13 VDD_A2 U7 TP_BB_TEST_MODE_1 Y19 MODE_1
PP_SMPS2_RF1_1V3 25 30
52
G14 AA11 IN
GND
H7 GND AA18 1 C3424 1 C3425 26 24 IN
19P2M_MDM V20 CXO
H8 1.0UF 1.0UF 19P2M_CLK_EN U21 CXO_EN
20% 20% 26 OUT
6.3V 6.3V
H13 VDD_A1 W9 2 X5R 2 X5R 26 24 PMIC_SSBI Y21 SSBI_PMIC
VDD_MEM 0201-1 0201-1 BI
H14 VDD_A1 AA7 E8
NC
P7 GND AA15 24 USB_BB_DEBUG_P C11 USB_HS_DP C8
BI NC
P8 USB_BB_DEBUG_N E11 USB_HS_DM DNC B9
PP_SMPS3_MSME_1V8
24 BI NC
P13 A15 RREFEXT A12 USB_HS_REXT A9
IN 24 25 27 28 30 52
NC
P14 G1 C12 USB_HS_ID
NC
R7 G21 1 C3426 B12 USB_HS_SYSCLK
R8 VDD_P3 L1 1.0UF 52
24 IN PMU_GPIO_BB_VBUS_DET C10 USB_HS_VBUS
20% 48
R13 U1 6.3V E9
A R14 W19
2 X5R
0201-1 C9
NC
NC A
DNC B10 PAGE TITLE
NC
52 30 28 27 25 24 IN
PP_SMPS3_MSME_1V8 A14
A19
VDD_P4 A2
A3
PP_LDO6_RUIM_1V8 IN 10 24 25 52
1
R3401
200
A10
NC CELL: BASEBAND (1 OF 2)
VDD_P5 PP_SMPS3_MSME_1V8 IN 24 25 27 28 30 52
1% DRAWING NUMBER SIZE
F21
VDD_P1 VDD_P6 A7 PP_LDO8_VDDPX_1V2 IN 25 27
1/32W
MF SDC1_CMD K19 NC Apple Inc. 051-0886 D
M1 VDD_P7 A11 PP_SMPS3_MSME_1V8 2 01005 SDC1_CLK L21 REVISION
IN 24 25 27 28 30 52
NC R
M21 A.0.0
SDC1_DATA0 L19 NOTICE OF PROPRIETARY PROPERTY: BRANCH
NC
PP_LDO13_VDDPX_2V95 K21 VDD_P2 SDC1_DATA1 L20 THE INFORMATION CONTAINED HEREIN IS THE
25 IN NC PROPRIETARY PROPERTY OF APPLE INC.
SDC1_DATA2 N20 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
NC
SDC1_DATA3 N21
NC
34 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BASEBAND (2 OF 2)
D D
U3400
MDM9615M
BGA
(4 OF 6)
ANALOG VREF_DAC_BIAS
DAC0_VREF W5 OUT 26
CRITICAL
1 C3500
29 IN PRX_BB_I_P U8 BBRX_IP_CH0 0.1UF
20%
52 30 28 27 25 24 PP_SMPS3_MSME_1V8 WLAN_TX_BLANK NEEDS TO CONNECT TO AP
PRX_BB_I_N W8 BBRX_IM_CH0
29 IN 2 4V
X5R
PRX_BB_Q_P Y8 BBRX_QP_CH0 TX_DAC1_QP Y13 1 CRITICAL
29 IN NC 01005 R3502
29 IN PRX_BB_Q_N AA8 BBRX_QM_CH0 TX_DAC1_QM AA13 NC 10K U3400
5%
1/32W
MF
MDM9615M
DRX_BB_I_P Y10 BBRX_IP_CH1 TX_DAC0_IP Y6 TX_BB_I_P BI BGA
29 IN 29
2 01005 (3 OF 6)
29 DRX_BB_I_N AA10 BBRX_IM_CH1 TX_DAC0_IM AA6 TX_BB_I_N OUT 29
IN
Y9 Y5 TX_BB_Q_P B6 GPIO P3
29 IN DRX_BB_Q_P BBRX_QP_CH1 TX_DAC0_QP OUT 29 52 24 10 IN SIM_TRAY_DETECT GPIO_0 GRFC_14 GPIO_44 PA_R1 OUT 33 34 35 36 37
29 DRX_BB_Q_N AA9 BBRX_QM_CH1 TX_DAC0_QM AA5 TX_BB_Q_N 29 52 24 10 SIMCRD_RST_CONN A6 GPIO_1 GRFC_15 GPIO_45 R1 B40_FILT_SELECT 39
IN OUT OUT OUT
TX_DAC0_IREF W6 WTR_BB_TX_DAC_IREF 29 52 24 10 SIMCRD_CLK_CONN A5 GPIO_2 GRFC_18 GPIO_46 N5
OUT OUT NC LAT_SW3_CTL
W17 BBRX_IP_CH2 SIMCRD_IO_CONN B5 GPIO_3 GRFC_19 GPIO_47 N3
C NC
NC
W18 BBRX_IM_CH2 TX_DAC1_IP Y14 NC
52 24 10 BI
NC
C4 GPIO_4 GRFC_20 GPIO_48 P2
NC
LAT_SW1_CTL BOOT_CONFIG_6
OUT 14 24 52
BOOT_CONFIG_5
C
W15 BBRX_QP_CH2 TX_DAC1_IM AA14 NC B3 GPIO_5 GRFC_21 GPIO_49 M2 GPIO_BB2SOC_GSM_TXBURST
NC NC OUT 5
W16 BBRX_QM_CH2 B4 GPIO_6 GRFC_22 GPIO_50 N1 BOOT_CONFIG_4
NC NC NC
A4 GPIO_7 GRFC_23 GPIO_51 N2 GPIO_51 BOOT_CONFIG_3
NC ANT_SEL_0
IN 24
H17 SPI_CLK A16 GPIO_8 GRFC_24 GPIO_52 M3 BOOT_CONFIG_2
NC 28 OUT 33 39 40
J17 SPI_CS_L A13 GPIO_9 GRFC_25 GPIO_53 L3 ANT_SEL_1 BOOT_CONFIG_1
NC 28 OUT 24 33 39 40
29 GPS_BB_I_P W10 GNSS_BB_IP 28 SPI_DATA_MISO E14 GPIO_10 GRFC_26 GPIO_54 M5 ANT_SEL_2 BOOT_CONFIG_0 24 39 40
IN OUT
GPS_BB_I_N U10 GNSS_BB_IM V21 SPI_DATA_MOSI E13 GPIO_11 GRFC_27 GPIO_55 L5 ANT_SEL_3
29 IN NC 28 BI 39 40
GPS_BB_Q_P W11 GNSS_BB_QP W21 UART3_BB2SOC_RTS_L C14 GPIO_12 GRFC_28 GPIO_56 K1 ANT_SEL_4
29 IN NC 24 5 OUT OUT 39
29 GPS_BB_Q_N U11 GNSS_BB_QM Y12 24 5 UART3_SOC2BB_RTS_L C13 GPIO_13 GRFC_29 GPIO_57 K5 3P4T_SEL_0 33
IN
DNC NC IN OUT
Y16 UART3_SOC2BB_TX E15 GPIO_14 GRFC_30 GPIO_58 K3 3P4T_SEL_1
NC 52 24 11 5 OUT OUT 33
Y17 UART3_BB2SOC_TX A18 GPIO_15 GRFC_31 GPIO_59 K2 LAT_SW2_CTL
NC 52 24 11 5 IN OUT 14 52
AA12
NC
R3531 NC C15 GPIO_16 GRFC_32 GPIO_60 J2 DCDC_EN OUT 38
AA16 OSCAR2RADIO_CONTEXT_A1
0.00 2 OSCAR_CONTEXT_A_MDM B16 J5 DCDC_MODE
GPIO_17 GRFC_33 GPIO_61
NCNC
52 44 19 IN OUT 38
AA17 0% GPIO_SOC2BB_WAKE_MODEM B18 GPIO_18 GRFC_34 GPIO_62 J1
1/32W
52 5 IN NC
MF GPIO_DEBUG_LED C16 GPIO_19 GRFC_35 GPIO_63 J3
01005
24 OUT NC
A17 GPIO_20 GRFC_36 GPIO_64 H3 BB_PDM
NC OUT 38
B21 GPIO_21 GRFC_37 GPIO_65 H5 UART_WLAN2BB_LTE_COEX
NC IN 24 44
B20 GPIO_22 GRFC_38 GPIO_66 G5 UART_BB2WLAN_LTE_COEX
NC OUT 24 44
A20 GPIO_23 GRFC_39 GPIO_67 H1
NC NC
B17 GPIO_24 GPIO_68 H2 HSIC2_BB2SOC_REMOTE_WAKE 5
NC OUT
P21 GPIO_25 GPIO_69 F3 BB_IPC_GPIO
NC OUT 5
R21 GPIO_26 GPIO_70 F1 WTR_SSBI_PRX_DRX
NC BI 24 29
P20 GPIO_27 GPIO_71 G3 WTR_SSBI_TX_GPS
NC BI 24 29
GPIO_29 PRODUCT_ID NC
R20 GPIO_28 GPIO_72 V3
NC
52 30 28 27 25 24 PP_SMPS3_MSME_1V8 T20 GPIO_29 GPIO_73 W3 BB_ERROR_FLAG 24
IN OUT
B 1 (1.8V) JXX RESERVED FOR FUTURE PRODUCT ID USE NC
T21 GPIO_30 GPIO_74 W2 WTR_GP_DATA0 GPH
OUT 29 B
37 GSM_PA_LB_EN U5 GPIO_31 GRFC_0 GPIO_75 W1 WTR_GP_DATA1 GPH 29
OUT OUT
0 (NC, PD) NXX 37 OUT GSM_PA_HB_EN V2 GPIO_32 GRFC_1 GPIO_76 Y1
NC
L3520 35 OUT PA_ON_B7_B20 V1 GPIO_33 GRFC_2 GPIO_77 F2 WLAN_TX_BLANK IN
R3530
44 52
70-OHM-300MA 0.00
U3 GPIO_34 GRFC_3 GPIO_78 E2 OSCAR_CONTEXT_B_MDM 1 2 OSCAR2RADIO_CONTEXT_B
PP_SMPS3_MSME_1V8_FILT NC IN 19 44 52
52 30 28 27 25 24
PP_SMPS3_MSME_1V8
1 2 33 PA_MB_CTL1 T3 GPIO_35 GRFC_4 GPIO_79 E3 HSIC2_BB2SOC_DEVICE_RDY 5 24 0%
IN OUT OUT 1/32W
01005-1 34 PA_ON_B2_B3 T1 GPIO_36 GRFC_5 GPIO_80 D1 HSIC2_SOC2BB_HOST_RDY 5 24 MF
OUT IN 01005
1 C3520 36 OUT PA_ON_B5_B8 T5 GPIO_37 GRFC_6 GPIO_81 E1 PM_MDM_IRQ_L OUT 26
0.1UF 33 32 OUT PA_MB_CTL0 R5 GPIO_38 GRFC_7 GPIO_82 D2 GPIO_BB2SOC_RESET_DET_L OUT 5 24
20%
4V R3 D3 PS_HOLD
2 X5R NC GPIO_39 GRFC_8 GPIO_83 OUT 26
01005 PA_BS T2 C1
36 35 34 33 OUT GPIO_40 GRFC_9 GPIO_84 NC
29 24 OUT WTR_RX_ON R2 GPIO_41 GRFC_10 GPIO_85 B1 GPIO_BB2SOC_GPS_SYNC OUT 5
29 24 OUT WTR_RF_ON P5 GPIO_42 GRFC_11 GPIO_86 C2 PMU_GPIO_BB2PMU_HOST_WAKE OUT 24 48 52

P1 C3 PM_USR_IRQ_L
B2
NC GPIO_43 GRFC_13 GPIO_87 OUT 26
VCC
U3520
SERIAL-SPI-2MX8-1.8V
WLCSP
MX25U1635EBAI-10G B3 SPI_CS_L
D3 CS* 28
WP*/SIO2 CRITICAL
SO/SIO1 C3 SPI_DATA_MISO 28
28 SPI_DATA_MOSI E2 SI/SIO0
A4
28 SPI_CLK D2 SCLK NC
F1
C2
NC NC
NC/SIO3 F4
GND NC
A A
E3
PAGE TITLE
CELL: BASEBAND (2 OF 2)
DRAWING NUMBER SIZE

REVISION
R
A.0.0
35 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RF TRANSCEIVER (1 OF 2)
PRX TRANSCEIVER RF AND IQ PORTS

TRANSCEIVER PHASE CONTROL, TX RF & IQ PORTS
D U3600
WTR1605 U3600 D
SM WTR1605
SYM 3 OF 5 SM
100_XCVR_B20_PRX_P 78 PRX PRX_BB_I_P SYM 2 OF 5
31 IN PRX_LB1_INP PRX_BB_IP 84 OUT 28
TX
100_XCVR_B20_PRX_N 69 CRITICAL TX_BB_I_P 130 140 50_XCVR_B20_TX
31 IN PRX_LB1_INM PRX_BB_IM 92 PRX_BB_I_N OUT 28 28 IN TX_BB_IP TX_LB1 OUT 32
TX_BB_I_N 138 CRITICAL 132 50_XCVR_2G_LB_TX
100_XCVR_B8_PRX_N 61 28 IN TX_BB_IM TX_LB2 OUT 37
31 IN PRX_LB2_INP PRX_BB_QP 91 PRX_BB_Q_P OUT 28 141 50_XCVR_B8_TX
100_XCVR_B8_PRX_P 54 TX_BB_Q_P 131 TX_LB3 OUT 32
31 IN PRX_LB2_INM PRX_BB_QM 82 PRX_BB_Q_N OUT 28 28 IN TX_BB_QP 133 50_XCVR_B5_B18_TX
TX_BB_Q_N 139 TX_LB4 OUT 32
100_XCVR_B5_B18_PRX_P 48 86 28 IN TX_BB_QM
31 IN PRX_LB3_INP DNC NC 126 50_XCVR_B2_TX
100_XCVR_B5_B18_PRX_N 43 WTR_BB_TX_DAC_IREF 109 TX_MB1 OUT 32
31 IN PRX_LB3_INM 28 IN DAC_REF 119 50_XCVR_B1_B3_TX
TX_MB2 OUT 32
31
100_XCVR_B2_PRX_P 36
PRX_MB1_INP 28
WTR_GP_DATA0 GPH 105 GP_DATA0 TX_MB3 112 50_XCVR_B34_B39_TX 32
IN IN OUT
31
100_XCVR_B2_PRX_N 30 PRX_MB1_INM 28
WTR_GP_DATA1 GPH 121 GP_DATA1 TX_MB4 95 50_XCVR_2G_HB_TX 37
IN IN OUT
88 GP_DATA2
31
100_XCVR_B3_PRX_P 23
PRX_MB2_INP NC TX_HB 103 50_XCVR_B7_B38_B40_TX 32
IN 114 DNC OUT
100_XCVR_B3_PRX_N 17
PRX_MB2_INM NC
31 IN 96 DNC DNC 93 C3602
NC NC 56PF R3602
31
100_XCVR_B1_B34_B39_DCS_PRX_N 8
PRX_MB3_INP 61.9 2 50_PDET_PAD_IN
IN 90 DNC PDET_IN 101 50_PDET_IN 1 2 50_PDET_PAD_OUT 1
31 IN
100_XCVR_B1_B34_B39_DCS_PRX_P 16 PRX_MB3_INM R3600 NC IN 35
4.75K WTR_RBIAS 60 5%
1%
1 2 RBIAS 1/32W
31
100_XCVR_B7_B38_B40_PRX_P 7 PRX_HB_INP 16V MF
IN 1% NP0-C0G 01005
100_XCVR_B7_B38_B40_PRX_N 15
PRX_HB_INM 1/32W 79 VTUNE_PRX 01005
31 IN MF NC 1 1
01005 R3601 R3603
28 24
WTR_RX_ON 45 RX_ON 105 105
IN
WTR_RF_ON 100 1% 1%
28 24 IN RF_ON 1/32W 1/32W
WTR_SSBI_TX_GPS 89 MF MF
28 24 BI SSBI_TX_GNSS 2 01005 2 01005
28 24
WTR_SSBI_PRX_DRX 80 SSBI_PRX_DRX
BI
DRX TRANSCEIVER RF AND IQ PORTS
134 GND
C U3600 C3600
100PF R3604
120 XO_IN 9.0 DB ATTENUATOR C
WTR1605 19P2M_WTR 0.00
26 IN
1 2 19P2M_WTR_FILT_IN 1 2 19P2M_WTR_IN
SM
SYM 1 OF 5 0%
5% 1/32W
DRX_GPS 16V MF
40
100_XCVR_B5_B18_DRX_P 5
DRX_LB1_INP DRX_BB_IP 63 DRX_BB_I_P 28
NP0-C0G 01005 1 C3601
IN OUT 01005
100_XCVR_B5_B18_DRX_N 14 CRITICAL 10PF
40 IN DRX_LB1_INM DRX_BB_IM 72 DRX_BB_I_N OUT 28
5%
16V
100_XCVR_B8_B20_DRX_P 4 2 CERM
40 IN DRX_LB2_INP DRX_BB_QP 50 DRX_BB_Q_P OUT 28
01005
40
100_XCVR_B8_B20_DRX_N 13
DRX_LB2_INM DRX_BB_QM 57 DRX_BB_Q_N 28
NOSTUFF
IN OUT
40
100_XCVR_B1_B2_B3_B34_B39_DRX_P 3
DRX_MB_INP
IN
40
100_XCVR_B1_B2_B3_B34_B39_DRX_N 12
DRX_MB_INM
IN
40
100_XCVR_B7_B38_B40_DRX_P 2
DRX_HB_INP
IN
40 IN
100_XCVR_B7_B38_B40_DRX_N 11
DRX_HB_INM
40
100_XCVR_GPS_RX_P 10
GNSS_INP GNSS_BB_IP 56 GPS_BB_I_P 28
IN OUT
40
100_XCVR_GPS_RX_N 18 GNSS_INM GNSS_BB_IM 62 GPS_BB_I_N 28
IN OUT
GNSS_BB_QP 70 GPS_BB_Q_P OUT 28
GNSS_BB_QM 71 GPS_BB_Q_N OUT 28
GND 1
TRANSCEIVER GROUND CONNECTIONS
U3600
B WTR1605 B
SM
SYM 5 OF 5
GND
46
GND
77 CRITICAL GND 125
GND
47 GND 124
GND
68 123
GND GND
29 GND GND 110
22 102
GND GND
27 99
GND GND
21 GND GND 129
20 94
GND GND
33 115
GND GND
6
GND 137
75 GND
GND 122
38 GND
GND 107
GND
41 106
GND GND
58 GND GND 135
74 128
GND GND
59 104
GND GND
52 113
GND GND
39
GND
73 GND 19
GND
34 GND 32
GND
GND 49
A 64
81
GND
GND
A
PAGE TITLE
35 GND CELL: RF TRANSCEIVER (1 0F 2)
142 DRAWING NUMBER SIZE
GND GND 9
REVISION
R
A.0.0
36 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RF TRANSCEIVER (2 OF 2)
R3700
RF1_1V3 RF1_1V3 RF2_2V05
22-OHM-25%-1800MA STAR ROUTING STAR ROUTING STAR ROUTING STAR ROUTING R3702 STAR ROUTING
PP_SMPS2_RF1_1V3_FILT PP_RF1_1V3_PRX_PLL PP_RF1_1V3_GPS_LNA 0 PP_RF2_2V05_DRX_BB
25 PP_SMPS2_RF1_1V3
1 2 30
ALIAS 30 30 PP_SMPS2_RF1_1V3_FILT ALIAS 52 25
30 PP_SMPS4_RF2_2V05 1 2 PP_SMPS4_RF2_2V05_FILT ALIAS
30
27
0201 5%
1
C3701 1
C3702 1
C3713 1/20W
PP_RF1_1V3_GPS_DIG MF 1
C3715 PP_RF2_2V05_TX_DA
D 2
10UF
20%
10V 2
0.1UF
20%
6.3V
X5R-CERM 2
0.1UF
20%
6.3V
X5R-CERM
ALIAS
30 201
10UF
20%
ALIAS 30
D
X5R-CERM 10V
2 1
0402-1 01005
PLACE NEAR U3.66
01005
PLACE NEAR U3.24 AND U3.31
X5R-CERM
0402-1
C3716
100PF
STAR ROUTING
5%
16V
2 NP0-C0G
ALIAS
PP_RF1_1V3_SHDR_PLL 30 ALIAS
PP_RF1_1V3_GPS_VCO 30 01005
PLACE NEAR U3.111
NOSTUFF
1
C3703
1
C3714 PP_RF1_1V3_GPS_PLL STAR ROUTING
0.1UF ALIAS
30
PP_RF2_2V05_PRX_BB 30
0.1UF 20% ALIAS
20% 6.3V
6.3V 2 X5R-CERM
2 X5R-CERM 01005
01005 PLACE NEAR U3.37 AND U3.55
PLACE NEAR U3.65 ALIAS
PP_RF2_2V05_TX_BB 30
PP_RF1_1V3_PRX_VCO 30 STAR ROUTING

ALIAS
1
C3704 RF1_1V8 ALIAS
PP_RF2_2V05_PRX_VCO
30
0.1UF 1
C3717
20%
6.3V
52 28 27 25 24 PP_SMPS3_MSME_1V8 PP_RF1_1V8_DIG 0.1UF
ALIAS 30
2 X5R-CERM 20%
01005 6.3V
2
PLACE NEAR U3.76 1
C3700 X5R-CERM
01005
1.0UF PLACE NEAR U3.67
20%
10V
ALIAS
PP_RF1_1V3_SHDR_VCO 30
2 X5R-CERM PP_RF2_2V05_SHDR_VCO
0201-1 ALIAS 30
PLACE NEAR U3.87
1
C3705
0.1UF
20%
1
C3718
6.3V 0.1UF
2 X5R-CERM 20%
6.3V
01005 2 X5R-CERM
PLACE NEAR U3.40 01005
PLACE NEAR U3.51
C ALIAS
PP_RF1_1V3_TX_DA 30
PP_RF2_2V05_TX_VCO
C
ALIAS 30
1
C3706 1 C3721
0.1UF 56PF
20%
6.3V 5% 1
C3719
2 X5R-CERM 2 16V
NP0-C0G 0.1UF
01005 01005 20%
PLACE NEAR U3.118 6.3V
2
NOSTUFF X5R-CERM
01005
STAR ROUTING PLACE NEAR U3.136
ALIAS
PP_RF1_1V3_TX_SYNTH 30
ALIAS
PP_RF2_2V05_TX_PLL 30
1
C3707
0.1UF
20%
2
6.3V
ALIAS
PP_RF2_2V05_XO_FILT 30
X5R-CERM
01005
PLACE NEAR U3.98 1
C3720
0.1UF
PP_RF1_1V3_TX_LO 20%
ALIAS 30 6.3V
2 X5R-CERM
01005
PLACE NEAR U3.127
1
C3708
0.1UF
20%
6.3V
2 X5R-CERM
01005
PLACE NEAR U3.116
PP_RF1_1V3_TX_UPCONVERTER TRANSCEIVER POWER CONNECTIONS

ALIAS 30
1
C3709 U3600
100PF WTR1605
B 2
5%
16V
NP0-C0G
SM
SRM 4 OF 5
B
01005
PLACE NEAR U3.117
PWR
30 PP_RF1_1V3_PRX_FELO1 53 VDD_RF1_P_FELO CRITICAL VDD_RF2_T_DA 111 PP_RF2_2V05_TX_DA 30
STAR ROUTING PP_RF1_1V3_PRX_FELO2 42 118 PP_RF1_1V3_TX_DA
STAR ROUTING 30 VDD_RF1_P_FELO VDD_RF1_T_DA 30
PP_RF1_1V3_PRX_FELO1 30
PP_RF1_1V3_DRX_LBLO
ALIAS 30
28 VDD_RF1_D_LBLO VDD_RF1_T_UPC 117 PP_RF1_1V3_TX_UPCONVERTER 30
30 PP_RF1_1V3_DRX_FE PP_RF1_1V3_TX_LO
26 116
1
C3710 VDD_RF1_D_FE VDD_RF1_T_LO 30
0.1UF 30
PP_RF1_1V3_DRX_MBLO 25
VDD_RF1_D_MBLO VDD_RF2_T_BB 108 PP_RF2_2V05_TX_BB 30
20% PP_RF1_1V3_DRX_FE 30
PP_RF1_1V3_JAM_DET 85
6.3V ALIAS 30 VDD_RF1_JDET
2 X5R-CERM VDD_RF2_T_VCO 136 PP_RF2_2V05_TX_VCO 30
30 PP_RF2_2V05_PRX_BB
83
01005 VDD_RF2_P_BB 127 PP_RF2_2V05_XO_FILT
PLACE NEAR U3.53 AND U3.26
PP_RF2_2V05_DRX_BB 44 VDD_RF2_XO 30
30 VDD_RF2_D_BB 98
VDD_RF1_T_SYN PP_RF1_1V3_TX_SYNTH 30
PP_RF2_2V05_PRX_VCO 67
VDD_RF2_P_VCO VDD_RF2_T_PLL 97 PP_RF2_2V05_TX_PLL
PP_RF1_1V3_PRX_FELO2 30 30
ALIAS 30
30
PP_RF1_1V3_PRX_VCO 76
VDD_RF1_P_VCO
VDD_RF1_G_LNA 24 PP_RF1_1V3_GPS_LNA
PP_RF1_1V3_PRX_PLL 66
VDD_RF1_P_PLL
30
1
C3711 30
VDD_RF1_G_VCO 37 PP_RF1_1V3_GPS_VCO 30
30 PP_RF2_2V05_SHDR_VCO
0.1UF 51 VDD_RF2_S_VCO
20% VDD_RF1_G_PLL 55 PP_RF1_1V3_GPS_PLL 30
6.3V 30
PP_RF1_1V3_SHDR_VCO 40 VDD_RF1_S_VCO
2 X5R-CERM VDD_RF1_G_BB 31 PP_RF1_1V3_GPS_DIG 30
01005 30
PP_RF1_1V3_SHDR_PLL 65
VDD_RF1_S_PLL
PLACE NEAR U3.42
VDD_DIO 87 PP_RF1_1V8_DIG 30
STAR ROUTING
PP_RF1_1V3_DRX_LBLO 30
ALIAS
1
C3712 PP_RF1_1V3_DRX_MBLO 30
0.1UF ALIAS
20%
6.3V
2 X5R-CERM
01005
A PLACE NEAR U3.25 AND U3.28

A
PAGE TITLE
PP_RF1_1V3_JAM_DET 30
ALIAS
CELL: RF TRANSCEIVER (2 OF 2)
DRAWING NUMBER SIZE

REVISION
R
A.0.0
37 OF 121
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RX MATCHING
L3805 L3810
D 0.7NH-0.8A
1 2
10NH-3%-140MA
1 2
D
33 IN 100_RX_MODULE_OUT_P 100_XCVR_B1_B34_B39_DCS_PRX_P OUT 29 36 IN 100_B8_DUPLX_RX_N 100_XCVR_B8_PRX_N OUT 29
0201 01005
1 CRITICAL 1
L3804 L3811
5.6NH-3%-0.35A 18NH-3%-140MA
0201 01005
CRITICAL
L3812
2 L3806 2 10NH-3%-140MA
0.7NH-0.8A
36 100_B8_DUPLX_RX_P 1 2 100_XCVR_B8_PRX_P 29
100_RX_MODULE_OUT_N 1 2 100_XCVR_B1_B34_B39_DCS_PRX_NOUT IN OUT
33 IN 29
01005
0201
CRITICAL
L3808
8.2NH+/-3%-0.25A-0.7OHM
C3800
0.6PF 36 100_B5_DUPLX_RX_N 1 2 100_XCVR_B5_B18_PRX_N 29
IN OUT
34 IN
50_B2_DUPLX_RX 1 2 100_XCVR_B2_PRX_NOUT 29
0201
1
+/-0.05PF
1 16V 1
CERM
01005 L3807
NO_XNET_CONNECTION=TRUE 22NH-5%-0.1A
L3800 L3801 01005
13NH-5%-0.28A 6.8NH-5%-0.5A
0201DS 0201DS
CRITICAL CRITICAL L3809
2 8.2NH+/-3%-0.25A-0.7OHM
2 C3801 2
27PF 100_B5_DUPLX_RX_P 1 2 100_XCVR_B5_B18_PRX_P
C 50_B2_RX_BALUN 1 2 100_XCVR_B2_PRX_POUT 29 L3840
36 IN
0201
OUT 29
C
2.0NH+/-0.1NH-0.6A
5%
1 C3802 16V 1 2 50_B7_B38_B40_PRX_BALUN_IN
NP0-C0G
0.9PF 01005 0201
+/-0.05PF NO_XNET_CONNECTION=TRUE CRITICAL L3813
2 16V 1 L3825 C3806
CERM
27PF 0.6NH+/-0.1NH-0.85A
01005 33 IN 0.4PF
50_3P4T_PRX_OUT +/-0.1PF 1
100_B7_B38_B40_PRX_BALUN_OUT_N 2 100_B7_B38_B40_PRX_MATCH_N1 2 100_XCVR_B7_B38_B40_PRX_N OUT 29
25V
2 C0G-CERM 0201
201 5%
CRITICAL 16V 1
NP0-C0G
C3803 U3803 01005
1.2PF 2.3-2.69GHZ
50_B3_DUPLX_RX 1 2 100_XCVR_B3_PRX_NOUT LLP L3814
34 IN 29
3.6NH+/-0.1NH-400MA
+/-0.05PF UNBAL_PORT 2 0201
1 16V 1
NP0-C0G-CERM
01005 BAL_PORT1 3
C3807 2 L3815
NO_XNET_CONNECTION=TRUE BAL_PORT2 4 0.6NH+/-0.1NH-0.85A
L3802 L3803 27PF
8.7NH-5%-0.29A 5.6NH-5%-0.33A CRITICAL 1 2
100_B7_B38_B40_PRX_BALUN_OUT_P 100_B7_B38_B40_PRX_MATCH_P1 2 100_XCVR_B7_B38_B40_PRX_P OUT 29
0201DS 0201DS
CRITICAL CRITICAL 0201
GND 5%
16V
C3804 NP0-C0G
1
2 2 01005
27PF
50_B3_RX_BALUN 1 2 100_XCVR_B3_PRX_POUT 29
5%
1 C3805 16V
NP0-C0G
1.2PF 01005
+/-0.05PF NO_XNET_CONNECTION=TRUE 50_B38_FILTER U3801
2 16V
NP0-C0G-CERM 33 BI FIL_DIPLEXER_B38_B40
01005 ACFM-2043-AP1
1
LGA
B C3808 1 B38
B
9.1NH-3%-220MA 3 50_B38_B40_SPDT
L3822 0201
B40 CRITICAL ANT 6 BI 39
18NH-3%-140MA CRITICAL
35
100_B20_DUPLX_RX_N 1 2 100_XCVR_B20_PRX_NOUT 29
GND
IN 1
2
01005
2
4
5
7
8
9
1 L3817
50_B40_FILTER 1
0 2 50_B40_FILTER_MATCH
C3810
33 BI 5.6NH-3%-0.35A
L3823 5% 0201
22NH-5%-0.1A 1 1/20W CRITICAL
MF
01005 201
NOSTUFF 2
L3824 C3809
2 18NH-3%-140MA 6.8NH-3%-0.3A
0201
35 100_B20_DUPLX_RX_P 1 2 100_XCVR_B20_PRX_POUT 29
IN CRITICAL
01005 U3802
2
TX-BAND40-LTE
SAFEA2G35MB0F57
L3819 LGA
2.7NH+/-0.1NH-200MA CRITICAL L3821
50_FULL_B40_FILTER 1 2 4 UNB_PORT2
50_FULL_B40_SPDT_MATCH 0
33 BI UNB_PORT1 1 1 2 50_FULL_B40_SPDT BI 39
01005 50_FULL_B40_FILTER_MATCH GND 5%
CRITICAL 1/20W
MF
1 C3811 201
1
5
3
2
56PF
5%
2 16V
NP0-C0G
01005 L3820
NOSTUFF 3.3NH+/-0.1NH-0.45A
0201
CRITICAL
A 2 A
PAGE TITLE
CELL: RX MATCHING
DRAWING NUMBER SIZE

REVISION
R
A.0.0
38 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TX INTERSTAGE FILTERS
C3901
2.0NH+/-0.1NH-0.2A-1.35OHM
29 50_XCVR_B2_TX 1 2 50_B2_TX_SAW_IN
IN
01005
CRITICAL 1 C3902
D 5%
56PF D
2 16V
NP0-C0G
01005 C3913
NOSTUFF
50_XCVR_B34_B39_TX 1
0.00 2 50_B34_B39_TX_FILT_IN
29 IN
0%
1/32W
MF
01005 1
C3903
0.00 2 FL3902
29 IN 50_XCVR_B5_B18_TX 1 50_B5_B18_TX_SAW_IN FL3901 SAW-BAND-TX-B1-B3-B34-B39
L3905 AF48
0%
1/32W
SATGR832MBM0F57 2.7NH+/-0.1NH-200MA LGA
MF LGA 01005 1 IN B34/B39 OUT B34 9 50_B34_TX_SAW_OUTOUT 33
1 INPUT BAND2 CRITICALOUTPUT BAND2 11 50_B2_TX_SAW_OUT OUT CRITICAL CRITICAL
01005
1 34 OUT B39 8 50_B39_TX_SAW_OUTOUT 33
2 4 IN B1/B3
R3901
3 INPUT BAND5+18 OUT B1 7 1.5NH+/-0.1NH-220MA
L3901 OUTPUT BAND5+18 9 50_B5_TX_SAW_OUT OUT 36
10NH-5%-140MA OUT B3 6 1 2
GND 50_B1_TX_SAW_MATCH 50_B1_TX_SAW_OUT OUT 33
01005
5 INPUT BAND8 OUTPUT BAND8 7 50_B8_TX_SAW_OUT OUT 36 01005
2
3
5
10
CRITICAL 1
2
GND THRM C3914
PAD 50_XCVR_B1_B3_TX 0.00 2 50_B1_B3_TX_SAW_IN L3907
1
29 IN 10NH-3%-140MA
2
4
6
8
10
12
13
0% 01005
C3904 1/32W NOSTUFF
50_XCVR_B8_TX 1
0.00 2 50_B8_TX_SAW_IN
MF
01005 1
29 IN
2
0%
1/32W
1
L3909
MF
01005
L3906 1.5NH+/-0.1NH-220MA
2.0NH+/-0.1NH-0.2A-1.35OHM
01005 50_B3_TX_SAW_MATCH 1 2 50_B3_TX_SAW_OUT OUT 34
L3902 01005
10NH-5%-140MA
01005 2 1
C 2
CRITICAL
L3908
C
5.1NH-3%-0.16A
01005
NOSTUFF
2
C3905
50_XCVR_B20_TX 1
0.00 2 50_B20_TX_SAW_IN
29 IN OUT 35
0%
1/32W
MF 1
01005
L3903
10NH-5%-140MA
01005
40 39 33 25 14 IN PP_LDO14_2V65
1 C3909
0.01UF
10%
6.3V
2 X5R
01005
4
VDD
C3906 U3901
C3910
B 29 IN 50_XCVR_B7_B38_B40_TX
3.3PF
1 2
50_XCVR_B7_B38_B40_TX_MATCH
BGS12SL6
5 RFIN TSLP6-2 RF1 3 50_B7_TX_SPDT_OUT 1
0.00 2
50_B7_TX_FILT_IN
OUT 35
B
CRITICAL 0%
+/-0.1PF 1 1/32W
16V 33 28 PA_MB_CTL0 6 CTRL RF2 1 MF
NP0-C0G IN 1
01005 C3911 01005
C3907 GND 56PF
5%
1.5NH+/-0.1NH-220MA 1 C3908 16V
2
2 NP0-C0G
01005
56PF 01005
5% NOSTUFF
16V
2 NP0-C0G
2 01005
C3912
100PF
50_B38_B40_TX_SPDT_OUT1 2 50_B38_B40_TX_SPDT_MATCH
OUT 33
5%
16V
NP0-C0G 1
01005
L3904
1.2NH+/-0.1NH-220MA
01005
NOSTUFF
2
A A
PAGE TITLE
CELL: RF TRANSCEIVER (3 OF 4)
DRAWING NUMBER SIZE

REVISION
R
A.0.0
39 OF 121
SHEET
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R4064
0.00 2
BAND 1/34/39/38/40 TX 40 39 33 32 25 14 IN PP_LDO14_2V65 1

0%
1/32W
MF
01005
PP_LDO14_3P4T
1 C4072
56PF
VDD A1
5%
16V
2 NP0-C0G
01005
=PPBATT_VCC_BB U4000
54 38 37 36 35 34 25 24 IN 33 28 3P4T_SEL_0 B1 VC1 SKY13477 RF1 C5
IN
38 37 36 35 34 IN
PP_PA 3P4T_SEL_1 C1 BGA C4
33 28 IN VC2 RF2
1 1 ANT_SEL_1 C2 VC4 CRITICAL RF3 C3 50_3P4T_PRX_OUT
C4001 1 C4043 C4002 1 C4054
40 39 28 24 IN OUT 31
D 0.1UF
20% 5%
100PF 1.0UF
20% 5%
100PF 40 39 28 IN ANT_SEL_0 A2 VC3 RF4
RF5
B5
A4 50_B40_FILTER
D
2 6.3V
X5R-CERM 2 16V 2 6.3V
X5R 2 16V
BI 31
NP0-C0G NP0-C0G 1 1 1 1 A5 50_FULL_B40_FILTER
01005 01005 0201-1 01005 C4075 C4076 C4008 C4012 RF6 BI 31
56PF 56PF 56PF 56PF
DGND
GND1
GND2
RF7 A3 50_B38_FILTER 31
5% 5% 5% 5% BI
16V 16V 16V 16V
2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G
36 35 34 28 IN PA_BS 01005 01005 01005 01005
PA_MB_CTL1 L4012
B2
B4
B3
28 IN
PA_MB_CTL0 50_B7_RX_SP3T_IN
1
0.00 2 50_B7_DUPLX_RX
32 28 IN IN 35
37 36 35 34 28 PA_R1 C4058 0%
IN 0 1/32W
1 C4023
50_B38_PA_OUT 1 2 50_B38_PA_MATCH MF
5%
56PF 01005
1 1 1 1 5%
C4041 C4042 C4052 C4053 1/20W 16V
2 NP0-C0G
56PF 56PF 56PF 56PF MF
201 01005
5% 5% 5% 5% 1 NOSTUFF
2 16V 2 16V 2 16V 2 16V C4060
NP0-C0G NP0-C0G NP0-C0G NP0-C0G 56PF
01005 01005 01005 01005
5%
2 25V
NP0-C0G
201
L4029 NOSTUFF
50_B1_TX_SAW_OUT
1
0.00 2 50_B1_PA_IN
32 IN C4048
0%
1/32W 50_B40_PA_OUT 1
0 2 50_B40_PA_MATCH
1 C4038 MF
01005 5%
1.2PF 1 1/20W
+/-0.1PF MF
16V 201
2 NP0-C0G
01005 C4061
NOSTUFF
11
10
26
12NH+/-3%-0.25A-0.7OHM
3
7
8
0201
VMODE
VBS_0
VBS_1
VBS_2
VCC
VBATT
L4030
50_B34_TX_SAW_OUT 1
0.00 2 50_B34_PA_IN
32 IN 2 FL4012
0% 1880-2025MHZ L4083
C 1 C4039
1/32W
MF
01005
2
21
RFIN_B1
RFOUT_B1
U4025
ACPM-7900-AP1 CPL_IN 12 50_MBPA_CPL_IN IN 36
C4049
0
DEA162025LT-5046B1SJ
50_B34_B39_PA_FILT_IN1 IN/OUTLGAOUT/IN 3
2.9NH+/-0.1NH-0.5A-0.2OHM
1 2
50_B34_B39_TX_ASM
C
1.2PF 50_B34_B39_PA_OUT1 2 50_B34_B39_PA_FILT_OUT OUT 39
+/-0.1PF 5 LLP CPL_OUT 24 50_B2_B3_CPL_INOUT 34 CRITICAL 0201
RFIN_B34 5% GND
2 16V
NP0-C0G 4 CRITICAL 1/20W 1 C4063 CRITICAL
MF
2
4
01005 RFIN_B39 1
NOSTUFF 19 201 0.6PF
RFOUT_B34/B39 +/-0.05PF
25V
2 CERM
6 RFIN_B38/B40 C4071 0201
L4044 8.2NH+/-3%-0.25A-0.7OHM
0.00 2 50_B39_PA_IN 17 RFOUT_B38 CRITICAL
32
50_B39_TX_SAW_OUT 1 0201
IN 15 RFOUT_B40 CRITICAL
1 0% THRM
1/32W GND PAD 2
MF 3P4T_SEL_0 IN 28 33
01005
3P4T_SEL_1
1
9
13
14
16
18
20
22
23
25
27
28
29
30
31
32
IN 28 33
C4040
18NH-3%-140MA
01005 R4065
0.00 2 PP_LDO14_RX_MOD 1 C4033 1 C4034
40 39 33 32 25 14 IN PP_LDO14_2V65
1
56PF 56PF
2 0% 5% 5%
1 16V 16V
1/32W
1 C4074 2 NP0-C0G 2 NP0-C0G
MF
01005
C4073 0.1UF 01005 01005
56PF 20%
L4020 L4045 5% 2 6.3V
16V X5R-CERM
50_B38_B40_TX_SPDT_MATCH
100PF 4.0PF 2 NP0-C0G 01005
1 2 50_B38_B40_TX_MATCH 1 2 50_B38_B40_PA_IN 01005
32 IN L4070
5% +/-0.1PF 50_RX_MOD_DCS_IN1
0.00 2 50_DCS_RX_ASM
6
IN 39
16V 1 16V
NP0-C0G NP0-C0G C4047 VDD 0%
01005 01005 3.0PF 1/32W
MF
C4037 50_B1_PA_OUT 1 2 50_B1_PA_OUT_MATCH 01005 1 C4055
U4027 0.5PF
7.5NH-3%-0.140A LMSWFKJM CRITICAL
01005 +/-0.05PF
25V 15 BAND1_TX VC1 8 +/-0.05PF
16V
C0G-CERM LGA VC2 7
2 NP0-C0G
1 0201 1 01005
17 BAND1ANT CRITICAL NOSTUFF
B 2
C4064 C4046
DCSRXIN 1
L4071 B
100_RX_MODULE_OUT_P 11 BAND1_34_39_DCSRXOUT0 BAND34_39_RXIN 18 4.0PF
10NH-3%-250MA 15NH+/-3%-0.25A-0.7OHM 31 OUT
0201 0201 31 100_RX_MODULE_OUT_N 12 BAND1_34_39_DCSRXOUT1 50_RX_MOD_B34_B39_IN 1 2 50_B34_B39_RX_ASM 39
OUT IN
+/-0.1PF
2 2 1 25V
COG-CERM
THRM GND 0201
PAD CRITICAL
C4056
20
19
16
14
13
10
9
5
4
3
2
5.6NH-3%-0.35A
0201
CRITICAL
2
BAND PA POWER MODE PA_BS PA_CTL1 PA_CTL0 PA_R1 L4072

100PF
======================================================= 50_B1_RX_MOD_ANT 1
5%
2 50_B1_ANT BI 39
OFF X X 0 0 0 25V
NP0-CERM
0201
CRITICAL
1
B1 HPM X 1 0 0 L4097
7.5NH-0.30A
0201
B1 LPM X 1 0 1 CRITICAL
B34 HPM 1 0 1 0 2
B34 LPM 1 0 1 1
A B39 HPM 0 0 1 0 PAGE TITLE
A
B39 LPM 0 0 1 1 CELL: PENTABAND PA
B38 HPM 1 1 1 0 Apple Inc.
DRAWING NUMBER
051-0886
SIZE
D
B38 LPM 1 1 1 1 R
REVISION
A.0.0
B40 HPM 0 1 1 0 NOTICE OF PROPRIETARY PROPERTY:
BRANCH
B40 LPM 0 1 1 1 THE POSESSOR AGREES TO THE FOLLOWING:

PAGE
40 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BAND 2/3 PAD

D D
PA_ON_B2_B3
38 37 36 35 33 IN
PP_PA IN 28
54 38 37 36 35 33 25 24
=PPBATT_VCC_BB
IN PA_BS 28 33 35 36
IN
1 C4100 1 C4101 1 C4148 1 C4149
0.22UF 0.22UF 0.1UF 1.0UF PA_R1
IN 28 33 35 36 37
20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R-CERM 2 X5R
01005 01005 01005 0201-1 1 C4102 1 C4103
C4146
0.00 2 100PF 100PF
32 50_B3_TX_SAW_OUT 1 50_B2_B3_CPL_IN 33
5% 5%
IN IN
2 6.3V
CERM 2 6.3V
CERM
0% 01005 01005
BS 29
1/32W
VBATT 25
VEN_B2_B3 30
VMODE 24
MF
VCC 2
1 01005 1 50_B7_B20_CPL_IN 35
OUT
L4122 L4182
9.1NH-3%-140MA 2.2NH+/-0.1NH-200MA
01005 01005 L4136
NOSTUFF NOSTUFF 3.0NH+/-0.1NH-0.45A
50_B3_TX_PAD_IN 26 RFIN_B3 CPL_IN 4
2 2 U4123 1 2 50_B3_ANT 39
50_B2_TX_PAD_IN 28 RFIN_B2 CPL_OUT 20
BI
TQM6M6224 0201
CRITICAL
13 RX_B3 LGA
CRITICAL 1 C4154 1 C4150
14 GND 50_B3_DPLX_ANT
ANT_B3 16 0.5PF 0.5PF
+/-0.05PF +/-0.05PF
11 RX_B2 25V 25V
L4123 ANT_B2 8 50_B2_DPLX_ANT 2 COG-CERM 2 CERM
C 2.7NH+/-0.1NH-200MA
1 2
10 GND
GND
THRM_PAD
0201
CRITICAL
201
NOSTUFF
C
32 IN 50_B2_TX_SAW_OUT
1
3
5
6
7
9
12
15
17
18
19
21
22
23
27
31
01005
1 C4104 1 C4147
0.5PF 0.5PF
+/-0.05PF +/-0.05PF
16V 16V
2 C0G-CERM 2 C0G-CERM
01005 01005 L4138
NOSTUFF 3.0NH+/-0.1NH-0.45A R4139
1 2
50_B2_DPLX_ANT_MATCH
1
0.00 2 50_B2_ANT BI 39
0201 1%
CRITICAL 1/20W
MF
1 C4155 1 C4151 0201
50_B2_DUPLX_RX
OUT 31
0.6PF 0.5PF
+/-0.05PF +/-0.05PF
50_B3_DUPLX_RX 31 2 25V 2 25V
OUT CERM CERM
0201 201
CRITICAL NOSTUFF
B B
BAND PA POWER MODE PA_BS PA_ON_B2_B3 PA_R1

=====================================================
A
OFF X X 0 X A
B3 HPM 0 1 0 PAGE TITLE
CELL: BAND 2/3 PAD
B3 LPM 0 1 1 Apple Inc.
DRAWING NUMBER
051-0886
SIZE
D
B2 HPM 1 1 0 R
NOTICE OF PROPRIETARY PROPERTY:

REVISION
A.0.0
B2 LPM 1 1 1 THE INFORMATION CONTAINED HEREIN IS THE
THE POSESSOR AGREES TO THE FOLLOWING:
BRANCH
PAGE
41 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BAND 20/7 PAD

D D
PA_ON_B7_B20 IN 28
PA_BS 28 33 34 36
IN
1 C4239 1 C4233 1 C4234

100PF 100PF 100PF
5% 5% 5%
6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM
01005 01005 01005
38 37 36 34 33 IN
PP_PA
54 38 37 36 34 33 25 24 IN
=PPBATT_VCC_BB
1 1 1 C4229 1 C4230
C4235 C4232
0.22UF 0.22UF 0.1UF 1.0UF
20% 20% 20% 20% CELL
6.3V
2 X5R
6.3V
2 X5R 2 6.3V
X5R-CERM 2 6.3V
X5R PA_R1
01005 0201-1 IN 28 33 34 36 37 C4207
01005 01005 1.0PF
C4231 50_B7_B20_CPL_IN IN 34
22PF 1 2
1 2
50_B7_TX_FILT_MATCH
32 IN 50_B7_TX_FILT_IN +/-0.1PF
L4253 16V
VBATT 25
VEN_B7_B20 30
BS 29
2.7NH+/-0.1NH-200MA
VMODE 24
C 5% NP0-C0G
C
VCC 2
16V 50_PDET_PAD_IN OUT 29 01005
1 CERM 50_B20_TX_SAW_OUT 1 2
01005 CRITICAL
FL4211 01005 CELL
C4216
SAWFD847MGA0F57 1
CRITICAL
LGA C4227 L4200
2.2NH+/-0.1NH-200MA 4 INPUT_BAND7 OUTPUT_BAND7 6 1.2PF 6.2NH-0.30A
01005 CRITICAL +/-0.1PF
NOSTUFF 16V U4215
2 NP0-C0G 50_B20_TX_PAD_IN 26 RFIN_B20 CPL_IN 4 1 2 50_B20_ANT 39
1 INPUT_BAND20 BI
OUTPUT_BAND20 9 01005 50_B7_TX_PAD_IN 28 RFIN_B7 AFEM-790720
2 NOSTUFF LGA CPL_OUT 20 50_B20_DPLX_ANT 0201
CRITICAL
CRITICAL CELL
GND L4254 12 RX_P_B20 1
1
3.3NH+/-0.1NH-180MA 13 RX_N_B20 C4208
C4218 3.9PF
2
3
5
7
8
10
50_B7_TX_FILT_OUT 1 2 ANT_B20 16 +/-0.1PF

56PF 11 RX_B7 L4257 25V
1 2 ANT_B7 8 10NH-3%-250MA 2 C0G-CERM
32 IN 50_B20_TX_SAW_IN 50_B20_TX_SAW_MATCH 01005
10 GND 0201
CRITICAL CRITICAL 0201
GND THRM_PAD NOSTUFF CRITICAL
5% 1 C4228
16V
0.8PF
1
3
5
6
7
9
14
15
17
18
19
21
22
23
27
31
32
33
34
35
36
37
38
39
40
41
42
1 C4219 NP0-C0G 2
01005 +/-0.1PF
56PF 16V
2 NP0-C0G
5%
2 16V
NP0-C0G
01005
01005 NOSTUFF
C4236
NOSTUFF 2.2NH+/-0.1NH-0.6A
50_B7_DPLX_ANT 1 2 50_B7_ANT 39
BI
50_B7_DUPLX_RX OUT 33 0201
1 L4228
1 L4229 0.5PF
0.5PF +/-0.05PF
100_B20_DUPLX_RX_N OUT 31
+/-0.05PF 25V
2 CERM
25V
2 COG-CERM 201
100_B20_DUPLX_RX_P OUT 0201
31 NOSTUFF
CRITICAL
B B

A
=====================================================
OFF X X 0 X PAGE TITLE
A
B20 HPM 0 1 0 CELL: BAND 7/20 PAD
DRAWING NUMBER SIZE
051-0886 D
B20 LPM 0 1 1 R
Apple Inc. REVISION
A.0.0
B7 HPM 1 1 0 NOTICE OF PROPRIETARY PROPERTY:
BRANCH
B7 LPM 1 1 1 PROPRIETARY PROPERTY OF APPLE INC.

PAGE
SHEET
42 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BAND 5/8 PAD

D D
38 37 35 34 33 IN
PP_PA PA_ON_B5_B8 IN 28
54 38 37 35 34 33 25 24
=PPBATT_VCC_BB
IN PA_BS 28 33 34 35
IN
1 1 1 C4318 1 C4319
C4322 C4323 PA_R1 1 1
0.22UF 0.22UF 0.1UF 1.0UF IN 28 33 34 35 37
C4324 C4325
20% 20% 20% 20% 100PF 100PF 1
6.3V 6.3V 6.3V 6.3V R4300
2 X5R 2 X5R 2 X5R-CERM 2 X5R 5% 5%
01005 0201-1 6.3V
2 CERM 6.3V
2 CERM 49.9
01005 01005
01005 01005 1%
1/32W
MF
2 01005
L4314
VBATT 29
VEN_B5_B8 24
BS 25
VMODE 30
2.2NH+/-0.1NH-200MA 50_PA_ISO
VCC 2
32 IN 50_B5_TX_SAW_OUT 1 2
01005 50_MBPA_CPL_IN OUT 33
1 C4316 CRITICAL 1 C4327 C4320

1.2PF 1.2PF 2.7NH+/-0.1NH-0.50A
+/-0.1PF +/-0.1PF
2 16V 2 16V 50_B5_TX_PAD_IN 26 RFIN_B5 CPL_IN 4 50_B5_DPLX_ANT 1 2 50_B5_ANT
NP0-C0G NP0-C0G BI 39
01005 01005 50_B8_TX_PAD_IN 28 RFIN_B8 U4358 CPL_OUT 20 0201
NOSTUFF NOSTUFF
L4315
SKY77493
LGA
CRITICAL
13 RX_P_B5
2.2NH+/-0.1NH-200MA 14 CRITICAL
RX_N_B5
32 IN 50_B8_TX_SAW_OUT 1 2 ANT_B5 16
1 L4316
01005 11 RX_P_B8 ANT_B8 8
10 0.5PF
1 C4317 CRITICAL RX_N_B8 GND THRM_PAD +/-0.05PF
2.2PF 1 C4326 2 25V
COG-CERM
+/-0.1PF 0201
1.2PF
1
3
5
6
7
9
12
15
17
18
19
21
31
32
33
34
35
36
37
38
39
40
41
42
22
23
27
C 16V
2 NP0-C0G
01005-1
+/-0.1PF
16V
2 NP0-C0G
CRITICAL C
CRITICAL 01005
NOSTUFF
C4321
18PF
50_B8_DPLX_ANT 1 2 50_B8_ANT 39
BI
100_B8_DUPLX_RX_N 31
2%
OUT 1 25V
C0H-CERM
100_B8_DUPLX_RX_P 31
0201
OUT
100_B5_DUPLX_RX_N L4317
OUT 31
22NH-100MA
0201
100_B5_DUPLX_RX_P OUT 31 NOSTUFF
2
B B

A
=====================================================
OFF X X 0 X PAGE TITLE
A
B5 HPM 0 1 0 CELL: BAND 5/8 PAD
DRAWING NUMBER SIZE
051-0886 D
B5 LPM 0 1 1 R
Apple Inc. REVISION
A.0.0
B8 HPM 1 1 0 NOTICE OF PROPRIETARY PROPERTY:
BRANCH
B8 LPM 1 1 1 PROPRIETARY PROPERTY OF APPLE INC.

PAGE
43 OF 121
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
2G PA
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
2G PA GAIN MODES
BAND MODE GAIN MODE PA_R1 PCL RANGE
=======================================================
LOW BAND GSM ULTRA LOW HIGH 16 TO 19
LOW BAND GSM LOW HIGH 14 TO 15
LOW BAND GSM MEDIUM LOW 7 TO 13
LOW BAND GSM HIGH LOW 5 TO 6
HIGH BAND GSM ULTRA LOW HIGH 10 TO 15
HIGH BAND GSM LOW HIGH 7 TO 9
HIGH BAND GSM HIGH LOW 0 TO 6
LOW BAND EDGE LOW HIGH 15 TO 19
LOW BAND EDGE MEDIUM LOW 10 TO 14
D LOW BAND
HIGH BAND
EDGE
EDGE
HIGH
LOW
LOW
HIGH
8 TO 9
9 TO 15
D
HIGH BAND EDGE HIGH LOW 2 TO 8
38 36 35 34 33
PP_PA
IN
1 C4485 1 C4488
4.7UF 0.1UF
20% 20%
6.3V 4V
2 X5R-CERM1 2 X5R
402 01005
L4440
C 54 38 36 35 34 33 25 24 =PPBATT_VCC_BB
240OHM-350MA
1 2 PP_BATT_VCC_2G_PA
C
IN
0201
C4467 C4472
2.7PF 12PF
29
50_XCVR_2G_HB_TX 1 2 50_TX_G_HB_MCH 1 2 50_TX_G_HB_PAIN
IN 1 C4489 1 C4487
+/-0.1PF 5% 56PF 1.0UF
16V 1 16V 5% 20%
NP0-C0G CERM 16V 10V
01005-1 01005 2 NP0-C0G 2 X5R-CERM
01005 0201-1
L4436
2.7NH+/-0.1NH-200MA
01005
V2G 14
VBATT 7
2
U4410 L4437
SKY77355 3.2NH+/-0.1NH-0.45A-025OHM
C4484 1 LGA 1 2
L4435 HB_GSM_RF_IN HB_GSM_RF_OUT 11 50_TX_G_HB_PAOUT 50_TX_G_HB_ASM OUT 39
33PF CRITICAL
50_XCVR_2G_LB_TX 0.00 2 50_TX_G_LB_MCH 1 2 50_TX_G_LB_PAIN 3
0201
29 IN
1 LB_GSM_RF_IN LB_GSM_RF_OUT 8 CRITICAL 1
0%
1/32W 5% 36 35 34 33 28 IN
PA_R1 6 VMODE0
MF 16V
01005 NP0-C0G
4
L4438
CRITICAL 01005 28 IN
GSM_PA_LB_EN PA_ON2 3.6NH+/-0.1NH-400MA
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD
GSM_PA_HB_EN 5 0201
1 C4471 28 IN PA_ON3
6.0PF NOSTUFF
+/-0.1PF
GND
GND
GND
GND
GND
16V
2 NP0-C0G
1 C4483 1 C4486 2
B 01005
NOSTUFF 5%
100PF
16V
5%
100PF
16V B
2
9
10
12
13
15
16
17
18
19
20
21
22
23
2 NP0-C0G 2 NP0-C0G
01005 01005
R4437
50_TX_G_LB_PAOUT 1
0.00 2 50_TX_G_LB_ASM OUT 39
1%
1/20W 1
MF
0201
L4439
3.6NH+/-0.1NH-400MA
0201
NOSTUFF
2
A A
PAGE TITLE
CELL: 2G PA
DRAWING NUMBER SIZE

REVISION
R
A.0.0
44 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PA DC/DC CONVERTER
D D
54 37 36 35 34 33 25 24 IN
=PPBATT_VCC_BB
C 1 C4502 1 C4503 1 C4504 C

56PF 0.01UF 10UF
5% 10% 20%
2 16V
NP0-C0G 2 6.3V
X5R 2 6.3V
CERM
01005 01005 0402
A3
B3
D1
PVIN VDD
U4500 L4500
PLACE NEAR U1.H3 PLACE NEAR U11.D2 LM3258 1.5UH-2.0A-0.137OHM
DCDC_EN C2 EN BGA
DCDC_OUT PP_PA
28 IN SW A2 1 2
OUT 33 34 35 36 37
R4500 R4534 CRITICAL
C3 BP SW B2 PIFE20161T-SM
1.00K BB_PDM_FILT 1.00K CRITICAL CRITICAL
28 IN BB_PDM 1 2 1 2
1 CRITICAL
DCDC_MODE D3 MODE FB D4 C4507
1%
1/32W
1%
1/32W
28 IN 10UF
1 C4508
MF
1 C4500 MF DCDC_ADJ ACB A4 20%
6.3V
3300PF
01005 1000PF 01005 D2 VCON 2 CERM-X5R 10%
ACB B4 2 6.3V
C1 SGND
C4 BGND
10% 0402 X5R
6.3V
2 X5R-CERM
1 C4545 01005
01005 1000PF PGND
10%
6.3V
A1
B1
2 X5R-CERM
01005
B B
A A
PAGE TITLE
CELL: PA DCDC CONVERTER

DRAWING NUMBER SIZE

REVISION
R
A.0.0
45 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PRIMARY ASM
D D
40 39 33 32 25 14 IN
PP_LDO14_2V65
1 C4669
100PF
1 = PARTIAL B40 5%
6.3V
2 CERM
01005
0 = FULL B40
5
VDD
C4640 SW4601
1.8NH+/-0.1NH-600MA CXA4403GC
1 2
50_TXRX_B38_B40_SPDT 6 RF1 XFLGA RF2 4 50_FULL_B40_SPDT BI 31
0201
CRITICAL
1 VC RF3 2 50_B38_B40_SPDT 31
B40_FILT_SELECT BI
28 IN
C 1 L4642 1 C4668
GND
C
3
0.3PF
+/-0.1PF 100PF
25V 5%
2 C0G-CERM
201 2 6.3V
CERM
01005
40 39 33 32 25 14 IN
PP_LDO14_2V65
1 C4622 1 C4641
100PF 0.1UF
5% 20%
6.3V 4V
2 CERM 2 X5R
01005 01005
R4605
0
VDD 26
1 2 50_PRI_ANT_COAX BI 42
5%
1/20W
MF 1
201
U4617
LGA L4613
4 2 56NH-100MA-3.9OHM
RF1495
34 BI 50_B3_ANT TRX1 ANT1 50_ASM_ANT
0201
34 50_B2_ANT 5 TRX2 ANT2 20 50_ANT2_TERM
BI
33 50_B34_B39_RX_ASM 6 TRX3
BI
HBTX 10 50_TX_G_HB_ASM 2
35 50_B20_ANT 7 TRX4
IN 37
BI 12 50_TX_G_LB_ASM
8 LBTX IN 37
35 BI 50_B7_ANT TRX5 CRITICAL
36 50_B5_ANT 14 TRX6 RF1 3 50_TXRX_B38_B40_ASM
BI
36 50_B8_ANT 15 TRX7 RF2 19 50_RF2_TERM
BI
33 50_DCS_RX_ASM 16 TRX8
BI
VC1 21 ANT_SEL_0
17 28 33 40
B 33
33
BI
BI
50_B1_ANT
50_B34_B39_TX_ASM 18
TRX9
TRX10
VC2 22
23
ANT_SEL_1
IN
IN 24 28 33 40 B
VC3 ANT_SEL_2 IN 24 28 40
VC4 24 ANT_SEL_3 28 40
IN
25
THRM
VC5 ANT_SEL_4 28
GND
GND
GND
GND
IN
PAD
1
9
11
13
27
1 1
R4607 R4608 1 C4639
1 C4663 1 C4664 1 C4665 1 C4666
49.9 49.9 100PF 100PF 100PF 100PF 100PF
1% 1% 5% 5% 5% 5% 5%
1/20W 1/20W 6.3V 6.3V 6.3V 6.3V 6.3V
MF MF 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
2 201 2 201 01005 01005 01005 01005 01005
A A
PAGE TITLE
CELL: ASM AND HB LTE FRONT-END

DRAWING NUMBER SIZE

REVISION
R
A.0.0
46 OF 121
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
RX DIVERSITY
D D
CRITICAL PP_LDO14_2V65
39 33 32 25 14 IN
C4794
R4701 27PF
50_DRX_ANT
0 50_DRX_ASM_MCH 1 2 1 1 C4739
41 IN 1 2 C4798
5% 0.01UF 56PF
5% 10% 5%
1/20W
MF 6.3V 2 6.3V 2 16V
NP0-C0G
201 1 NP0-C0G X5R 01005
0201 01005
NOSTUFF
L4743
3.0NH+/-0.1NH-0.45A
0201
7
2 VDD
U4714
HFQSWBUUA-239
LGA
50_DIVERSITY_SWITCH_MATCH 1 ANTENNA CRITICAL BAND 5+18 OUT 25 100_XCVR_B5_B18_DRX_P 29
OUT
BAND 5+18 OUT 26 100_XCVR_B5_B18_DRX_N 29
39 33 28
ANT_SEL_0 6 VC1 OUT
IN
39 33 28 24
ANT_SEL_1 5 VC2 BAND 8,20 OUT 23 100_XCVR_B8_B20_DRX_P 29
IN OUT
39 28 24
ANT_SEL_2 4 VC3 BAND 8,20 OUT 24 100_XCVR_B8_B20_DRX_N 29
IN OUT
ANT_SEL_3 3
C 39 28 IN
1 1 1 1 100_XCVR_GPS_RX_MATCH_N 17
VC4
GPS OUT
BAND 7,38,40 OUT 19
BAND 7,38,40 OUT 20
100_XCVR_B7_B38_B40_DRX_P
100_XCVR_B7_B38_B40_DRX_N
OUT 29 C
C4710 C4736 C4737 C4738 OUT 29
56PF 56PF 56PF 56PF 100_XCVR_GPS_RX_MATCH_P 18 GPS OUT

5% 5% 5% 5% BAND 1,2,3,34,39 OUT 21 100_XCVR_B1_B2_B3_B34_B39_DRX_P 29
50_GPS_DRX_MOD_IN 14 OUT
16V 16V 16V 16V GPS IN 100_XCVR_B1_B2_B3_B34_B39_DRX_N
2 NP0-C0G 2 NP0-C0G 2 NP0-C0G 2 NP0-C0G BAND 1,2,3,34,39 OUT 22 OUT 29
01005 01005 01005 01005 12 BAND 38 IN
11 AUX1 33 50_DRX_MOD_TERM
BAND 40 IN
AUX2 9
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C4755 THRM
PAD
5.6NH-3%-140MA 1
R4739
2
8
10
13
15
16
27
28
29
30
31
32
34
35
36
37
38
29
100_XCVR_GPS_RX_N 1 2 49.9
OUT
01005 1%
1/20W
1 MF
2 201
L4742
4.7NH-3%-160MA
01005
C4756
5.6NH-3%-140MA 2
29
100_XCVR_GPS_RX_P 1 2
OUT
01005
C4797
56PF
41 50_GPS_LNA_OUT 1 2
IN
5%
1 16V
NP0-C0G
NOSTUFF L4746
B L4740
01005
1
0 2
50_B38_DRX_MOD_IN B
10NH-3%-140MA 5%
01005 1/20W
1 MF
201
2
C4799
6.8NH-3%-0.3A
0201
CRITICAL
2
U4722
885035
R4711 BAW-DUAL-RX-B38-B40
5.6PF LGA
50_B38_B40_DRX_AUX2_OUT 1 2 50_B38_B40_DRX_FILT_IN 8 B38_ANT B38_RX 1 50_B38_DRX_FILT_OUT L4747
7 B40_ANT 0 50_B40_DRX_MOD_IN
+/-0.1PF
25V B40_RX 4 50_B40_DRX_FILT_OUT 1 2
1 NP0-C0G 5%
0201 1/20W
MF
GND 201
C4708 1
2
3
5
6
9
10
2.3NH+/-0.1NH-0.50A-0.2OHM
0201
1 L4701
5.6NH-3%-0.35A
2 0201
L4765 CRITICAL
3.0NH+/-0.1NH-0.45A
0201 2
NOSTUFF
A 2
A
PAGE TITLE
CELL: RX DIVERSITY
DRAWING NUMBER SIZE

REVISION
R
A.0.0
47 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPS
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
D D
CELL
FL4802
150OHM-25%-200MA-0.7DCR
PP_GPS_LNA_2V5 1 2 PP_LDO5_GPS_LNA_2V5 25
IN
01005
CELL CRITICAL
1 C4809
0.1UF
20%
2 6.3V
X5R-CERM
787MHZ TRAP 2400MHZ TRAP 01005
CRITICAL
CELL
CELL
L4806
CELL L4804 4.7NH-3%-0.35A
2
8.2NH+/-3%-0.25A-0.7OHM CRITICAL VCC
FL4801 1 2
1 2 CELL CELL
SASLE1G58AB0F57
0201
0201 C4807 U4801
LGA
CRITICAL
CRITICAL 2.0NH+/-0.1NH-0.6A BGA824N6
CELL 50_GPS_LNA_IN TSNP6
L4801 GPS/GNSS 1 50_GPS_FILT1 CELL 50_GPS_FILT2 CELL 50_GPS_FILT4 1 2 5 AI CRITICAL A0 3 50_GPS_LNA_OUT OUT 40
0 50_GPS_DIV_TRI_ANT 6 3 C4803 C4805 0201

41 50_GPS_DIV_SW_CONN 1 2 ANT HB/LB PON 6
5.0PF 0.9PF
C 5%
1/20W
MF
GND 1 2 1 2 GND GND C
4
201
1 +/-0.1PF +/-0.05PF
2
4
5
7
8
9
CRITICAL 25V 16V
1 C0G CERM
L4802
0201
CRITICAL
1 01005
CRITICAL
1 L4807
1.3PF
27NH-3%-0.140A-2.3OHM L4803 +/-0.1PF
0201
10NH-3%-250MA L4805 25V
2 C0G-CERM
NOSTUFF 0201 15NH+/-3%-0.25A-0.7OHM 201
0201 NOSTUFF
2 NOSTUFF CELL
CRITICAL
2
2
50_GPS_FILT3
1 C4804
1.8PF
+/-0.1PF
2 16V
NP0-C0G
01005-1
900MHZ TRAP
CELL
CRITICAL
50_DRX_ANT OUT 40
B B
CELL
GPS_DRX_ANT J4802
MM8930-2600B
CELL F-RT-SM
J4800
MM5829-2700 CELL
F-ST-SM R4801
0
1 50_GPS_ANT_COAX 1 2 50_GPS_ANT_TEST 2 1 50_GPS_DIV_SW_CONN 41
R C
5%
1/20W
2
3
4
MF GND
201
1 C4801 CRITICAL 1 C4802
0.2PF 0.2PF
6
5
4
3
+/-0.1PF +/-0.1PF
25V 25V
2 COG-CERM 2 COG-CERM
201 201
NOSTUFF NOSTUFF
TOP MOUNT TOP MOUNT
A SYNC_MASTER=RADIO_MLB_87 SYNC_DATE=10/29/2013 A
PAGE TITLE
CELL: GPS
DRAWING NUMBER SIZE

REVISION
R
A.0.0
48 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ANTENNA FEEDS
D D
C C
PRI_ANT COAX CELL

J4910
MM5829-2700
F-ST-SM
1 50_PRI_ANT_COAX BI 39
2
3
4
B B
A SYNC_MASTER=RADIO_MLB_87 SYNC_DATE=10/29/2013 A
PAGE TITLE
CELL: ANTENNA FEEDS

DRAWING NUMBER SIZE

REVISION
R
A.0.0
49 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOSTUFF
J5700
MLB-X200
HB-SM L5700
52 43 16 SPKR_R_CONN_N 1 FERR-70-OHM-4A
D 52 43 16 SPKR_R_CONN_P 3
2
4
SPKR_R_CONN_N 16
SPKR_R_CONN_P 16
43 52
43 52
43
PPVBUS_E75_USB_CONN 1
0603
2 =PPVBUS_USB_EMI
54 D
5
6 PPOUT_E75_ACC_ID2_CONN 43 52
43 CONN_DET_L 7 2 1 C5700 1 C5701 1
R5700 1 C5702 1 C5703
9
8 DZ5700 27PF 0.01UF 100K 27PF 6.8PF
10 E75_DPAIR2_CONN_P 43 52
27V-100PF 1% 10% 1% 1% +/-0.25PF
52 43 E75_DPAIR2_CONN_N 11 0402 2 25V
NP0-C0G 2 25V
X7R 1/20W 2 25V
NP0-C0G 2 25V
CERM
12 201 402 MF 201 201
13 2 201
14 PPVBUS_E75_USB_CONN 43 1
43 PPVBUS_E75_USB_CONN 15
16
17
18
19
20
21
22 PPOUT_E75_ACC_ID1_CONN 43 52
23
24
52 43 E75_DPAIR1_CONN_N 25
26 E75_DPAIR1_CONN_P 43 52
27
28
52 43 16 SPKR_L_CONN_N 29
30 SPKR_L_CONN_N 16 43 52
52 43 16 SPKR_L_CONN_P 31
32 SPKR_L_CONN_P 16 43 52
NOTE: SPKR_L_CONN_N AND SPKR_L_CONN_P WERE SWAPPED ON 5/22/12 PER RADAR #11526818
L5703
C E75_DPAIR1_CONN_P
90-OHM-50MA
TCM0605-1
SYM_VER-1
E75_DPAIR1_P
C
52 43
1 4 11
E75_DPAIR1_CONN_N 2 3
E75_DPAIR1_N
52 43 11
2
CRITICAL 2
CRITICAL
D5700 D5702
TSSLP-2-1 TSSLP-2-1
=PPVCC_MAIN_DOCK 1 1
54
NOSTUFF
NOSTUFF
1
R5790
R5705 1
0.00 2 PMU_E75_ACC_DET_L
OUT 48
100K
1% 0%
1/32W 1/32W
MF MF
01005 1
2 01005 R5791
R5706 0.00
CONN_DET_L 1
10K 2
0%
43 1/32W
MF
C CRITICAL 1%
2 01005
1/32W K CRITICAL
DZ5702 1 C5704 MF
01005 DZ5710
14.2V-6PF 6.8PF
+/-0.25PF
25V
SM-201 L5704
0201-1 2 CERM DSF01S30SC 90-OHM-50MA
A 201 A TCM0605-1
SYM_VER-1
E75_DPAIR2_CONN_P 1 4
E75_DPAIR2_P
TS_CON_DET_L 52 43 11
OUT 11
B 52 43
E75_DPAIR2_CONN_N 2 3
E75_DPAIR2_N
11
B
2
CRITICAL 2
CRITICAL
D5701 D5703
L5701 TSSLP-2-1 TSSLP-2-1
FERR-22-OHM-1A-0.055OHM
1 1
52 43
PPOUT_E75_ACC_ID1_CONN 1 2 PPOUT_E75_ACC_ID1 11
C CRITICAL 0201
DZ5703 1 C5705 0.055 OHM DCR
14.2V-6PF 8.2PF
+/-0.5PF
16V
0201-1 2 NP0-C0G-CERM
A 01005
L5702
FERR-22-OHM-1A-0.055OHM
PPOUT_E75_ACC_ID2_CONN 1 2 PPOUT_E75_ACC_ID2
52 43 11
C CRITICAL 0201
DZ5704 1 C5707 0.055 OHM DCR
8.2PF
A 14.2V-6PF
0201-1
+/-0.5PF
2 16V
NP0-C0G-CERM
A 01005 PAGE TITLE
IO: FILTERS & HOTBAR CONN

DRAWING NUMBER SIZE

REVISION
R
A.0.0
57 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
WIFI/BT: MODULE MODULE ISOLATION

XW5890
SHORT-10L-0.25MM-SM
52 48 IN PMU_GPIO_WLAN_REG_ON 1 2 PMU_GPIO_WLAN_REG_ON_R 44
XW5891
SHORT-10L-0.25MM-SM
52 48 PMU_GPIO_BT_REG_ON 1 2 PMU_GPIO_BT_REG_ON_R 44
D
IN
D
XW5892
SHORT-10L-0.25MM-SM
52 48 IN PMU_GPIO_CLK_32K_WLAN 1 2 PMU_GPIO_CLK_32K_WLAN_R 44
XW5893 54 =PPVCC_MAIN_WLAN
SHORT-10L-0.25MM-SM
=PP3V3_S2R_WIFI_PA 54
28 24 OUT UART_WLAN2BB_LTE_COEX 1 2 UART_WLAN2BB_LTE_COEX_R 44
1 C5880 1 C5881 1 C5882
10UF 10UF 10UF 1 C5800 1 C5801
20% 20% 20%
XW5894 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
4.7UF 4.7UF
SHORT-10L-0.25MM-SM 20% 20%
0402-2 0402-2 0402-2 6.3V 6.3V
28 24 UART_BB2WLAN_LTE_COEX 1 2 UART_BB2WLAN_LTE_COEX_R 44
2 X5R-CERM1 2 X5R-CERM1
IN
402 402
XW5895
VBAT 16
VBAT 17
RF_VCC_FEM 70
RF_VCC_FEM 71
SHORT-10L-0.25MM-SM =PP1V8_S2R_VDDIO_WLAN_BT 44 54
53 5 OUT UART2_WLAN2SOC_TX 1 2 UART2_WLAN2SOC_TX_R 44
BT_GPIO5/LTE_COEX_UART_TX 51 UART_WLAN2BB_LTE_COEX_R 44
PMU_GPIO_CLK_32K_WLAN_R 33
XW5896 1 NOSTUFF 44 CLK_32K
BT_GPIO4/LTE_COEX_UART_RX 50 UART_BB2WLAN_LTE_COEX_R
SHORT-10L-0.25MM-SM R5805 44
10K BT_GPIO1/HOSTWAKE 55 PMU_GPIO_BT_HOST_WAKE

53 5 IN UART2_SOC2WLAN_TX 1 2 UART2_SOC2WLAN_TX_R 44
5% 44 PMU_GPIO_WLAN_REG_ON_R OUT 48 52
1/32W BT_GPIO0/BTWAKE 56 GPIO_BT_WAKE 5 53

IN
MF
2 01005 44 PMU_GPIO_BT_REG_ON_R
XW5897
SHORT-10L-0.25MM-SM CRITICAL
HSIC1_SOC2WLAN_HOST_RDY 1 2 HSIC1_SOC2WLAN_HOST_RDY_R 52 JTAG_WLAN_SEL
53 5 IN 44
1
4 WL_REG_ON U5800
R5800 53 4 HSIC1_WLAN_DATA WIFI-BT-DOPPELBOCK
10K BI 3 BT_REG_ON BT_UART_RXD 37 UART1_SOC2BT_TX 5 53
HSIC1_WLAN_STB LGA IN
5% 53 4 BI 38 UART1_BT2SOC_TX
1/32W 23 BT_UART_TXD OUT 5 53
MF JTAG_SEL 36 UART1_BT2SOC_RTS_L
2 01005 BT_UART_RTS* OUT 5
C BT_UART_CTS* 39 UART1_SOC2BT_RTS_L
IN 5 C
13 HSIC_DATA BT_PCM_CLK 41 I2S4_SOC2BT_BCLK
14 42 I2S4_SOC2BT_LRCK
IN 10
R5804
HSIC_STROBE BT_PCM_SYNC IN 10
1
0.00 2 WLAN_TX_BLANK 28 52
BT_PCM_OUT 43 I2S4_BT2SOC_DATA OUT 10
IN
CRITICAL 7
SDIO_CLK 0%
NC BT_PCM_IN 44 I2S4_SOC2BT_DATA
IN 10 1/32W
CRITICAL
CRITICAL U5811 NC
6 SDIO_CMD
8 SDIO_DATA0 22 PMU_GPIO_WLAN_HOST_WAKE
MF
01005
R5830
1%
BAW-2436MHZ CRITICAL NC GPIO0/WL_HOST_WAKE OUT 48 53
U5810 1/20W 885061

C5811 NC
9 SDIO_DATA1 GPIO1/HOST_READY 20 HSIC1_SOC2WLAN_HOST_RDY_R 44 R5801
2.4-5.0GHZ MF LGA 10 SDIO_DATA2 27 TP_JTAG_WLAN_TCK 0.00 2 OSCAR2RADIO_CONTEXT_A
SM
0201 2.0NH+/-0.1NH-0.6A NC GPIO2/WL_TCK 52 1 IN 19 28 52
0.00 2 11 SDIO_DATA3 GPIO3/WL_TMS 28 JTAG_WLAN_TMS_TX_BLANK 0%
LOW(2.4GHZ) 3 RF_G_0_DIPLEXER 1 RF_G_0_BAW_ANT 4 OUT IN 1 RF_G_0_BAW_MOD 1 2 RF_G_0_MATCH_MOD NC 1/32W
0201 CRITICAL GPIO4/WL_TDI 26 JTAG_WLAN_TDI_OSCAR_A MF
GND 77 RF_SW_CTRL11 01005
HIGH(5.0GHZ) 1 1 C5810 NC GPIO5/WL_TDO 24 JTAG_WLAN_TDO_OSCAR_B
0.5PF 47 25 TP_JTAG_WLAN_TRST_L 52 R5802
5
3
2
ANT(COMMON) 5 NC I2SWS GPIO12/WL_TRST*

+/-0.05PF
46 I2SDO 19 0.00 2 OSCAR2RADIO_CONTEXT_B
1 1 2 25V
CERM NC GPIO9/AGG_CHANNEL NC 1 IN 19 28 52
GND 201 48 I2SDI 1
NC GPIO10/HSIC_DEVICE_READY HSIC1_WLAN2SOC_DEVICE_RDY OUT 5 53 0%
CRITICAL CRITICAL 49 I2SCLK 2 1/32W
6
4
2
NC GPIO11/HSIC_RESUME HSIC1_WLAN2SOC_REMOTE_WAKE 5 53 MF
L5811 L5810 GPIO15/WLAN_UART_TX 52 UART2_WLAN2SOC_TX_R
OUT 01005
10NH-3%-250MA 8.2NH+/-3%-0.25A-0.7OHM 67 RF_A_0
44
0201 0201 GPIO14/WLAN_UART_RX 53 UART2_SOC2WLAN_TX_R 44
79 RF_A_1
GPIO6 30 =PP1V8_S2R_VDDIO_WLAN_BT 44 54
NC
2 2 62 RF_G_0 GPIO7 29 WLAN_GPIO7
74 31 1
RF_G_1 GPIO8 NC R5803
10K
CRITICAL VIO 35 =PP1V8_S2R_VDDIO_WLAN_BT 44 54
5%
1/32W
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
GND_SIGNAL
CRITICAL
J5810 MF
MM4829-2702 CRITICAL C5814 DUMMY 57 NC 2 01005
F-ST-SM R5810 1.0NH+/-0.1NH-0.75A
1 RF_0_ANT 1
0.00 2 RF_0_ANT_MATCH_T RF_A_0_DIPLEXER 1 2 RF_A_0_MATCH
B 1
NOSTUFF
C5817
1%
1/20W 1
NOSTUFF
C5816 1
NOSTUFF
C5815
0201
1
CRITICAL
C5813
B
2
3
4
MF
0.2PF 0.2PF 0.2PF 0.2PF
5
12
15
18
21
32
34
40
45
54
58
59
60
61
63
64
65
66
68
69
72
73
75
76
78
80
81
82
83
84
85
86
87
88
0201
+/-0.1PF +/-0.1PF +/-0.1PF +/-0.05PF
25V 25V
2 COG-CERM 2 COG-CERM 2 25V
COG-CERM 2 25V
COG-CERM
201 201 201 0201
CRITICAL
CRITICAL U5820
J5820 CRITICAL DPX205850DT-9038A1SJ
MM4829-2702 SM CRITICAL
F-ST-SM R5820
0.00 2 5 COM C5821
1 RF_1_ANT 1 RF_1_ANT_MATCH_T HI 1 1.1NH+/-0.1NH
NOSTUFF 1% NOSTUFF
1 C5827 1/20W 1 C5826 LO 3 RF_G_1_DIPLEXER 1 2 RF_G_1_MATCH_MOD
2
3
4
MF
0.2PF 0201 0.2PF NOSTUFF 0201 CRITICAL
+/-0.1PF +/-0.1PF GND
25V
2 COG-CERM
25V
2 COG-CERM
1 C5822 1 C5820
0.2PF 0.5PF
6
4
2
201 201
+/-0.1PF +/-0.05PF
2 25V
COG-CERM 2 25V
CERM
201 201
A SYNC_MASTER=WIFI_DEV SYNC_DATE=05/20/2013 A
PAGE TITLE
CRITICAL
C5824 WIFI/BT: MODULE
1.0NH+/-0.1NH-0.75A DRAWING NUMBER SIZE
RF_A_1_DIPLEXER 1 2 RF_A_1_MATCH Apple Inc. 051-0886 D

CRITICAL REVISION
NOSTUFF 0201 R
1 C5825 1 C5823 A.0.0
0.2PF 0.2PF NOTICE OF PROPRIETARY PROPERTY: BRANCH
+/-0.1PF +/-0.05PF
2 25V
COG-CERM 2 25V
COG-CERM
201 0201 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
58 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
XW7520
SM
46 BATT_SNS 1 2
NET_SPACING_TYPE=ANLG
54 45 =PPBATT_POS_CONN
TP7500
1 P/N 516S0906
A CRITICAL
TP-P55
NOSTUFF J7500
FL7500 CPB2304-0101F
240-OHM-0.2A-0.8-OHM 13 F-ST-SM
UART5_BATT_RTXD 1 2 9 10
C 48 5 BI
0201-2
45 BATT_SWI_CONN
C
2 1 =PPBATT_POS_CONN 45 54
4 3 BATT_SWI_CONN 45
52 48 45 BATT_NTC C7522 1 C7523 1 C7524 1 C7525 1 C7526 1 6 5 BATT_NTC 45 48 52
BI
33PF 33PF 1000PF 27PF 4.7PF 8 7
5% 5% 10% 5% +/-0.1PF
16V 16V 16V 16V 16V
NP0-C0G 2 NP0-C0G 2 X7R-CERM 2 NP0-C0G 2 NP0-C0G 2
01005 01005 0201 01005 01005 11 12
14
TP7501
1
A
TP-P55
NOSTUFF

TABLE_ALT_HEAD
TP7503
1
PART NUMBER A
TP-P55
TABLE_ALT_ITEM
NOSTUFF
155S0644 155S0823 RADAR:8391945
FL7500,L1702,L1800,L1920,L2602,L2700,L2701,L2702,L2800,L2960,L2961,L2962,L2963,L38014_RF
B B
PAGE TITLE
POWER: BATTERY CONNECTOR

DRAWING NUMBER SIZE

REVISION
R
A.0.0
75 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PLACEMENT_NOTE=PLACE NEAR L8225.1 PLACEMENT_NOTE=PLACE NEAR L8225.1 PPVCC_MAIN 46 47 48 49 52 54
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
C8190 1 C8140 1 C8141 1 1 C8150 1 C8151 1 C8152 1 C8153 1 C8154 1 C8155 1 C8156 1 C8157 1 C8158 1 C8159 1 C8144 1 C8142 1 C8143 CRITICAL
100UF 100UF 100UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 1.0UF 82PF 18PF L8100
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 5% 5% 1.0UH-3.51A-0.036OHM
6.3V 2 6.3V 2 6.3V 2
TANT-POLY TANT-POLY TANT-POLY 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
X5R 2 25V
CERM 2 25V
C0G-CERM
B1G-1 B1G-1 B1G-1 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0201-1 0201 0201 BUCK0_LX0 1 2 PPVDD_CPU 52 54
MIN_LINE_WIDTH=0.60MM CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
MIN_NECK_WIDTH=0.20MM PILE25201D
ESR MAX=70MOHM ESR MAX=70MOHM NET_SPACING_TYPE=PWR CRITICAL 1 C8100 1 C8101 1 C8102 1 C8103 1 C8104
MAX_NECK_LENGTH=0.5 MM
DIDT=TRUE SWITCH_NODE=TRUE L8101 15UF 15UF 15UF 15UF 15UF
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL 1.0UH-3.51A-0.036OHM 20% 20% 20% 20% 20%
VCC_MAIN BYPASS 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4V
X5R 2 4V
X5R 2 4V
X5R 2 4V
X5R 2 4V
X5R
C8160 C8161 C8162 C8163 C8164 C8165 C8166 C8167 C8168 C8169 C8170 C8171 C8172 BUCK0_LX1 1 2 0402 0402 0402 0402 0402
PLACE TWO 10UF CAP 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF MIN_LINE_WIDTH=0.60MM
PILE25201D
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% MIN_NECK_WIDTH=0.20MM
AT EACH VDD INPUT 6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R NET_SPACING_TYPE=PWR CRITICAL
D 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 DIDT=TRUE SWITCH_NODE=TRUE L8102
1.0UH-3.51A-0.036OHM CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL D
BUCK0_LX2 1 2
1 C8105 1 C8106 1 C8107 1 C8108 1 C8109
MIN_LINE_WIDTH=0.60MM 15UF 15UF 15UF 15UF 15UF
MIN_NECK_WIDTH=0.20MM PILE25201D 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V
NET_SPACING_TYPE=PWR CRITICAL 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
CRITICAL OMIT_TABLE MAX_NECK_LENGTH=0.5 MM
DIDT=TRUE SWITCH_NODE=TRUE L8103 0402 0402 0402 0402 0402
L8112 U8100
1.0UH-3.51A-0.036OHM
2.2UH-20%-5.5A-0.054OHM 1 2
D2089A0 BUCK0_LX3
54 52 49 48 47 46 PPVCC_MAIN 1 2 SW_CHGA MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM PILE25201D
NOSTUFF PIME061D-SM
MIN_LINE_WIDTH=0.6 MM FCBGA NET_SPACING_TYPE=PWR
CRITICAL CRITICAL
CRITICAL K MIN_NECK_WIDTH=0.20 MM
SYM 1 OF 4
R8170 1 2 3 DCR=54MOHM MAX
D8100 NET_SPACING_TYPE=PWR
G19 E1
DIDT=TRUE SWITCH_NODE=TRUE XW8101
1 C8110 1 C8111
OVP_SW_EN_L 1
4.7K 2 SOD-123W
DIDT=TRUE
SWITCH_NODE=TRUE
CHG_LX0
BUCK0_FB 1 2
15UF 15UF
46 11 S H19 BUCK0_LX0 E2 20% 20%
CRITICAL PMEG4030ER CHG_LX1 MIN_LINE_WIDTH=0.25MM SM 4V
2 X5R 4V
2 X5R
5% 4 G J19 G1 MIN_NECK_WIDTH=0.20MM
1/20W A CHG_LX2 CRITICAL 0402 0402
MF Q8104 PLACE_NEAR=U8100.R17:2MM
K19 G2
201 FDMC6683 CHG_LX3 BUCK0_LX1 L8104
R8172 J1 1.0UH-3.51A-0.036OHM
MLP3.3X3.3
BATT_SNS 1
0 2 BATT_SNS_R R17
45 VBAT BUCK0_LX2 J2
PLACE_NEAR=U8100.R17:10MM P17 BUCK1_LX0 1 2 PPVDD_GPU 52 54
D 5% IBAT_S MIN_LINE_WIDTH=0.60MM
1/20W NOSTUFF 1 PLACE_NEAR=U8100.R17:10MM L1 PILE25201D CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
RDSON=0.0136@VGS=-2.5V 5 MF 1 C8149 R8173 MIN_NECK_WIDTH=0.20MM
ID=12.0A LAYOUT NOTE - 201

0.022UF 499 M19 IBAT0 BUCK0_LX3 L2 NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=0.5 MM CRITICAL 1 C8112 1 C8113 1 C8114 1 C8115 1 C8116
1% N19 DIDT=TRUE SWITCH_NODE=TRUE
L8105 15UF 15UF 15UF 15UF 15UF
R8172- PLACE NEAR PMU 10%
25V 1/20W IBAT1 BUCK0_FB H6 20% 20% 20% 20% 20%
C8149- PLACE NEAR PMU 2 X7R MF P19 1.0UH-3.51A-0.036OHM 2 4V 2 4V 2 4V 2 4V 2 4V
R8173- PLACE NEAR PMU 0402 2 201 IBAT2 N1 X5R X5R X5R X5R X5R
R19 BUCK1_LX1 1 2 0402 0402 0402 0402 0402
IBAT3 BUCK1_LX0 N2 MIN_LINE_WIDTH=0.60MM
54 52 46 PPBATT_VCC MIN_NECK_WIDTH=0.20MM PILE25201D
ACT_DIO N17 ACT_DIO R1 NET_SPACING_TYPE=PWR CRITICAL
BUCK1_LX1 R2 DIDT=TRUE SWITCH_NODE=TRUE
L8106
XW8114 PMU_VCENTER F18
SHORT-0201 U1 1.0UH-3.51A-0.036OHM CRITICAL CRITICAL CRITICAL CRITICAL
MIN_LINE_WIDTH=0.60MM F19 1 1 1 1
MOSFET FDMC6676BZ 4 USB_VBUS_DETECT 2 1 MIN_NECK_WIDTH=0.20MM
NET_SPACING_TYPE=PWR G18
BUCK1_LX2 U2 BUCK1_LX2 1 2 C8117 C8118 C8119 C8120
MIN_LINE_WIDTH=0.60MM 15UF 15UF 15UF 15UF
MIN_LINE_WIDTH=0.20MM MAX_NECK_LENGTH=3 MM
H18 BUCK1_FB M6 MIN_NECK_WIDTH=0.20MM PILE25201D 20% 20% 20% 20%
USB/BAT
CHANNEL P-TYPE MIN_NECK_WIDTH=0.15MM PLACE_NEAR=U8100.F18:2MM PLACE_NEAR=U8100.L18:2MM VOLTAGE=6.0V 4V 4V 4V 4V
BUCK
NET_SPACING_TYPE=PWR CRITICAL CRITICAL NET_SPACING_TYPE=PWR 2 X5R 2 X5R 2 X5R 2 X5R
VCENTER MAX_NECK_LENGTH=0.5 MM
C RDS(ON) 27 MOHM @-4.5V
VOLTAGE=6.0V
1 C8148
4.7UF
1 C8147
4.7UF LAYOUT NOTE: PLACE
J18
K18 BUCK2_LX0
U7
V7
DIDT=TRUE
BUCK1_FB
SWITCH_NODE=TRUE
1
XW8102
2
0402 0402 0402 0402
C
10% 10% L18
IMAX 6.9 A 35V
2 X5R-CERM
35V
2 X5R-CERM RIGHT AT THE PIN BUCK2_FB P7 MIN_LINE_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20MM SM
0603 0603 L19 CRITICAL
VGS MAX +/- 25V A5
L8107 ADDITIONAL DISTRIBUTED
52 11 PPVBUS_PROT F16 BUCK3_LX0 B5 1.0UH-3.51A-0.036OHM 27UF (NO DERATING)
NOSTUFF CRITICAL MIN_LINE_WIDTH=0.20MM PLACE_NEAR=U8100.F16:10MM F17 BUCK3_FB E6 PPVDD_SOC
K
MIN_NECK_WIDTH=0.15MM CRITICAL BUCK2_LX0 1 2

DZ8120 52 54
3
2
1
G16
R81161 CRITICAL
BZT52C10LP
MAX_NECK_LENGTH=3 MM C8145 1 A7
MIN_NECK_WIDTH=0.20MM PILE25201D CRITICAL CRITICAL CRITICAL
470K Q8123 VOLTAGE=6.0V 2.2UF G17 NET_SPACING_TYPE=PWR 1 C8121 1 C8122 1 C8123
1% S LLP
10% BUCK4_LX0 B7 MAX_NECK_LENGTH=0.5 MM
1/20W FDMC6676BZ 25V H16 DIDT=TRUE SWITCH_NODE=TRUE XW8103 15UF 15UF 15UF
NOTE: 10V ZENER BUCK4_FB E7
A
MF MLP3.3X3.3 G 4 X5R-CERM 2 H17 VBUS BUCK2_FB 1 2

20% 20% 20%
201 2 603
2 4V
X5R 2 4V
X5R 2 4V
X5R
J17 U5 MIN_NECK_WIDTH=0.20MM SM 0402 0402 0402
VBUS_PROT_G CRITICAL
MIN_LINE_WIDTH=0.20MM K16 BUCK5_LX0 V5
MIN_NECK_WIDTH=0.1MM LAYOUT NOTE: PLACE L8108 ADDITIONAL DISTRIBUTED
D 1 NET_SPACING_TYPE=ANLG RIGHT AT THE PIN K17 BUCK5_FB P6 1.0UH-3.51A-0.036OHM
R8130 L16
64UF (NO DERATING)
5
220K C1 BUCK3_LX0 1 2 PP1V8_S2R 46 47 52 54

1% L17
54 52 PPVBUS_USB_DCIN 1/20W R8146 BUCK6_LX0 C2
MIN_NECK_WIDTH=0.20MM PILE25201D CRITICAL CRITICAL CRITICAL
MF
201 2
OVP_SW_EN_L 1
4.7K 2 OVP_SW_EN_L_R C16 VBUS_OVP_OFF F6
1 C8124 1 C8125 1 C8126
46 11 52 BUCK6_FB 15UF 15UF 15UF
USB REVERSE VOLTAGE PROTECTION NOSTUFF A1
DIDT=TRUE SWITCH_NODE=TRUE XW8104 20% 20% 20%
5% BUCK6_BYP0 BUCK3_FB 1 2
1 D17 HV_CHG_DIS 4V 4V 4V
1/20W
MF
C8146 TP_HV_CHG_EN
BUCK6_BYP1 A2 MIN_LINE_WIDTH=0.25MM SM
2 X5R 2 X5R 2 X5R
201 0.01UF MIN_NECK_WIDTH=0.20MM 0402 0402 0402
LAYOUT NOTE: 10% 54 46 =PPVCC_MAIN_CPU F1 BUCK6_BYP2 A3 CRITICAL
25V
R8146, C8146 CAN BE 2 X5R-CERM F2 VDD_BUCK0_01 L8109 ADDITIONAL DISTRIBUTED
ANYWHERE BET.TRISTAR 0201 B13 1.0UH-3.51A-0.036OHM
K1 27UF (NO DERATING)
AND PMU B14
K2 VDD_BUCK0_23 VBUCK3 BUCK4_LX0 1 2 PP1V2_S2R 46 47 52 54
C14 MIN_LINE_WIDTH=0.60MM PILE25201D CRITICAL CRITICAL CRITICAL
54 46
=PPVCC_MAIN_GPU P1 A12 NET_SPACING_TYPE=PWR 1 C8127 1 C8128 1 C8129
P2 VDD_BUCK1_01 B12 DIDT=TRUE SWITCH_NODE=TRUE XW8105 15UF 15UF 15UF
20% 20% 20%
V1 BUCK3_SW1 C12 BUCK4_FB 1 2 4V
2 X5R
4V
2 X5R
4V
2 X5R
B V2
V3
VDD_BUCK1_2
C13
BUCK3_SW2 A13
CRITICAL
SM 0402 0402 0402
B
L8110 ADDITIONAL DISTRIBUTED
U8 BUCK3_SW3 A14 1.0UH-3.33A-66MOHM 64UF (NO DERATING)
54 46 =PPVCC_MAIN_SOC
V8 VDD_BUCK2 B10 BUCK5_LX0 1 2 PPVDD_SRAM 52 54
MIN_LINE_WIDTH=0.60MM CRITICAL CRITICAL CRITICAL
B11 MIN_NECK_WIDTH=0.20MM PILE20161D-SM
54 52 49 48 47 46 PPVCC_MAIN A4 VBUCK4 NET_SPACING_TYPE=PWR 1 C8130 1 C8131 1 C8132
C11 MAX_NECK_LENGTH=0.5 MM
15UF 15UF 15UF
SWITCHED POWER
B4 VDD_BUCK3
VCC-MAIN
A9
DIDT=TRUE SWITCH_NODE=TRUE
XW8106 20% 20% 20%
54 46 =PPVCC_MAIN_CPU BUCK5_FB 1 2 4V
2 X5R
4V
2 X5R
4V
2 X5R
A8 B9 MIN_LINE_WIDTH=0.25MM SM
MIN_NECK_WIDTH=0.20MM 0402 0402 0402
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL B8 VDD_BUCK4 BUCK4_SW1 C9 CRITICAL
1 C8175 1 C8176 1 C8177 1 C8178 1 C8179 1 C8180 1 C8181 C10 L8111 ADDITIONAL DISTRIBUTED
10UF 10UF 10UF 10UF 10UF 10UF 10UF U4 2.2UH-2.35A-0.073OHM
20% 20% 20% 20% 20% 20% 20%
V4 VDD_BUCK5 BUCK4_SW2 A10 32UF (NO DERATING)
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R BUCK6_LX0 1 2 PP3V3_S2R 52 54
0402 0402 0402 0402 0402 0402 0402 B1 VPUMP A11 MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM PILE25201D CRITICAL CRITICAL CRITICAL CRITICAL
NET_SPACING_TYPE=PWR 1 C81A0 1 C81A1 1 C81A2 1 C81A3
B2 MAX_NECK_LENGTH=0.5 MM
VDD_BUCK6 DIDT=TRUE SWITCH_NODE=TRUE XW8107 10UF 10UF 10UF 10UF
B3 20% 20% 20% 20%
BUCK6_FB 1 2 6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
54 46 =PPVCC_MAIN_GPU T16 VCC_MAIN_S MIN_NECK_WIDTH=0.20MM SM 0402 0402 0402 0402
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL M18

1 C8182 1 C8183 1 C8184 1 C8185 1 C8186 N18 PP1V8_S2R 46 47 52 54
10UF 10UF 10UF 10UF 10UF PP1V8_SW1 50 52 54
20% 20% 20% 20% 20% P18 VCC_MAIN CRITICAL CRITICAL CRITICAL CRITICAL
6.3V 6.3V 6.3V 6.3V 6.3V PP1V8_SW2
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 52 54
0402 0402 0402 0402 0402
R18
PP1V8_S2R_SW3
1 C81A4 1 C81A5 1 C81A6 1 C81A7
54
10UF 10UF 10UF 10UF
20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V
NOTE: FOR NO BATTERY SITUATION 2 CERM-X5R
0402
2 CERM-X5R
0402
2 CERM-X5R
0402
2 CERM-X5R
0402
=PPVCC_MAIN_SOC 54 52 46 PPBATT_VCC
54 46 PP1V2_S2R 46 47 52 54
A 1
CRITICAL
C8187 1
CRITICAL
C8188
CRITICAL CRITICAL PMU_VPUMP
PP1V2_SW1
PP1V2_S2R_SW2
52 54
SYNC_MASTER=J72_MLB_C SYNC_DATE=11/26/2012 A
1 C8193 1 C8194 MIN_LINE_WIDTH=0.30MM
52 54
PAGE TITLE
10UF 10UF
20%
6.3V
2 CERM-X5R
20%
6.3V
2 CERM-X5R
20%
10UF
6.3V
2 CERM-X5R
10UF
20%
6.3V
2 CERM-X5R
MAX_NECK_LENGTH=3 MM 1 C8196 1 C8135 1 C8136 1 C8137 1 C81A8 1 C8138 1 C8139 1 C81A9
PMU: ANYA PAGE 1
0402 0402 VOLTAGE=4.6V DRAWING NUMBER SIZE
0402 0402 0.22UF 1.0UF 1UF 1.0UF 1.0UF 1.0UF 1UF 1.0UF
PPBATT_POS_RC 20%
6.3V
20%
6.3V
10%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
10%
6.3V
20%
6.3V Apple Inc. 051-0886 D
MIN_LINE_WIDTH=0.30MM 2 X5R 2 X5R 2 CERM 2 X5R 2 X5R 2 X5R 2 CERM 2 X5R REVISION
MIN_NECK_WIDTH=0.20MM 0201 0201-1 402 0201-1 0201-1 0201-1 402 0201-1 R
R8100 1 NET_SPACING_TYPE=PWR
A.0.0
0.5 VOLTAGE=4.7V NOTICE OF PROPRIETARY PROPERTY: BRANCH
1% THE INFORMATION CONTAINED HEREIN IS THE
1/16W PROPRIETARY PROPERTY OF APPLE INC.
MF C8137 0201 OKAY IF GRAPE HAS EXT FET THE POSESSOR AGREES TO THE FOLLOWING: PAGE
402 2
81 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
LDO INPUTS U8100

D2089A0
54 52 46 PP1V8_S2R
1 CAP PER PIN
FCBGA
SYM 2 OF 4
LDO OUTPUTS
1 C8200 1 C8203 T18 U19 (50MA; 2.5-3.3V)
1UF 1UF PPVCC_MAIN PP3V0_SPARE1
D 10%
6.3V
2 CERM
10%
6.3V
2 CERM
54 52 49 48 47 46
B16
VDD_LDO1_3_4
VDD_LDO2
VLDO1
VLDO2 A16 (100MA; 1.65-1.805V; BUCK3) PP1V7_VA_VCP
47 52 54
16 47 52 54
D
402 402 54 52 49 48 47 46 PPVCC_MAIN U9 VDD_LDO5 VLDO3 U18 (50MA; 2.5-3.3V) PP3V0_S2R_SENSOR 47 52 54
U10 T19 (50MA; 2.5-3.3V) PP3V0_ALS
LDO INPUT
VDD_LDO6 VLDO4 47 52 54
54 52 46 PP1V2_S2R U14 VDD_LDO7 VLDO5 V9 (1000MA; 2.5-3.6V) PP3V0_UVLO 47 52 54
LDO
U15 VDD_LDO8 VLDO6 V10 (150MA; 2.5-3.6V) PP3V3_ACC 47 52 54
1 C8201 B15 VDD_LDO9 VLDO7 V14 (300MA; 1.7-3.0V) PP3V0_S2R_TRISTAR
1UF B17 V15
47 52 54
10% VDD_LDO10 VLDO8 (300MA; 1.7-3.0V) NC_LDO8 54
6.3V
2 CERM U16 A15 (300MA; 1.2-3.0V)
402 54 52 49 48 47 46 PPVCC_MAIN VDD_LDO11 VLDO9 PP1V3_CAM 47 52 54
T17 VDD_LDO13 VLDO10 A17 (150MA; 0.6-1.3V) PP1V0_SOC 47 52 54 CRITICAL
CRITICAL CRITICAL V16 (300MA; 1.7-3.0V)
L8225 C18 VLDO11 PP2V6_CAM_AF 54
47 L8229 MIN_LINE_WIDTH=0.4 MM
D8228 WLED_LX_A WLED_LXA0
VLDO13 U17 (300MA; 1.7-3.0V) PP2V9_CAM
52
2.2UH-1.05A-0.195OHM MIN_NECK_WIDTH=0.2 MM
4.7UH-3.2A PMEG4010BEA
DIDT=TRUE
SWITCH_NODE=TRUE
C19 WLED_LXA1
47 52 54 NET_SPACING_TYPE=PWR
ON_BUF T10 (5MA; 1.8V; ON_BUFF) PP1V8_ALWAYS 1 2 DIDT=TRUE
54 =PPVCC_MAIN_LED 1 2 (PPLED_OUT_A) D16 VOUT_WLED_A

47 52 54
MAKE_BASE=TRUE CRITICAL
A K VOLTAGE=6.0V VLS201612E-SM
PIME051E-SM R8227 52 LED_IO1_A_R E14 WLED1_A VDD_LCM_SW C17 =PPVCC_MAIN_VDD_LCM 54 MIN_LINE_WIDTH=0.4MM D8230
CRITICAL SOD-323 MIN_NECK_WIDTH=0.2MM
C8226 1 1.00 52 LED_IO2_A_R F14 WLED2_A VDD_BOOST_LCM A18 PP6V0_LCM_HI (NOTE: 2MHZ) PMEG2005AEL
18 IN LED_IO_1_A 1 2 NET_SPACING_TYPE=PWR
MAKE_BASE=TRUE
10UF
LCD BACKLIGHT
52 LED_IO3_A_R G14 WLED3_A BOOST_LCM_LX B19 LCM_LX MAX_NECK_LENGTH=3 MM
VOLTAGE=6.0V
20% 1% A K MIN_LINE_WIDTH=0.4MM
LCM/GRAPE
6.3V
R8231 1/32W
LED_IO4_A_R H14 WLED4_A LCM_FB C15 MIN_NECK_WIDTH=0.2MM
CERM-X5R 2 MF
52
0402 1.00 01005 J14 U11 SOD882
52 LED_IO5_A_R WLED5_A VDD_LCM 52 PP6V0_LCM_VBOOST MAX_NECK_LENGTH=3 MM
18 IN LED_IO_2_A 1 2
52 LED_IO6_A_R J16 WLED6_A VLCM1 V11 (100MA; 5.0-6.0V) PP5V25_GRAPE 54
1% CRITICAL CRITICAL
54 52 PPLED_OUT_A 1/32W
R8232 VLCM2 V12 (100MA; 5.0-6.0V) NO_TEST=TRUE NC_VLCM2 1 C8211 1 C8290
MF
NC_WLED_LXB0 E18 WLED_LXB0
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
LED_IO_3_A
01005
1
1.00
2 E19 LCM2_EN E8 NC_LCM2_EN 4.7UF 4.7UF
18 IN NC_WLED_LXB1 WLED_LXB1 20% 20%
1 C8250 1 C8251 1 C8252 1 C8253 1 C8254 1 C8259 1% E16 VLCM3 U12 (5MA; 5.0-6.0V) NO_TEST=TRUE NC_VLCM3
1 C8212 1 C8210 10V
2 X5R-CERM
10V
2 X5R-CERM
4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 56PF 1/32W
NC_VOUT_WLED_B VOUT_WLED_B 10UF 2.2UF 0402 0402
10%
35V
10%
35V
10%
35V
10%
35V
10%
35V
2%
50V
R8235 MF
NC_WLED1_B K14 WLED1_B
20%
25V
20%
10V
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 NP0-C0G-CERM 1.00 01005 2 X5R-CERM 2 X5R-CERM
0603 0603 0603 0603 0603 0201 18 IN LED_IO_4_A 1 2
NC_WLED2_B L14 WLED2_B 0603 402
M14 XTAL1 V18 PMU_XTAL
XTAL
1%
NC_WLED3_B WLED3_B
R8239 XTAL2 V17
1/32W
MF M16 PMU_EXTAL
01005 1.00 NC_WLED4_B WLED4_B
LED_IO_5_A
C 18 IN
1
1%
2
NC_WLED5_B
NC_WLED6_B
N14
P14
WLED5_B
WLED6_B
C
R8240 1/32W
MF
1.00 01005
18 IN LED_IO_6_A 1 2
1% CRITICAL
1/32W
MF Y8200
01005 32.768K-20PPM-12.5PF
2 1
CRITICAL CRITICAL
C8215 1 2012-1 1 C8216
18PF 18PF
5% 5%
25V 2 25V
C0G-CERM 2 C0G-CERM
0201 0201
TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
197S0399 197S0392 Y8200 RDAR://PROBLEM/9936684
1 C8280 1 C8281 1 C8282 1 C8283 1 C8284 1 C8285 LDO BYPASS

56PF 56PF 56PF 56PF 56PF 56PF
5%
25V
5%
25V
5%
25V
5%
25V
5%
25V
5%
25V 54 52 47 PP3V0_SPARE1
2 NP0-C0G-CERM 2 NP0-C0G-CERM 2 NP0-C0G-CERM 2 NP0-C0G-CERM 2 NP0-C0G-CERM 2 NP0-C0G-CERM
0201 0201 0201 0201 0201 0201 54 52 47 16 PP1V7_VA_VCP
54 52 47 PP3V0_S2R_TRISTAR
54 52 47 PP3V0_ALS
54 52 47 PP3V0_UVLO
54 52 47 PP3V3_ACC
54 52 47 PP3V0_S2R_SENSOR
B CRITICAL
C8237 1
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL B
2.2UF
C8235 1 C8234 1 C8233 1 C8232 1 C8231 1 C8230 1
10% 4.7UF 10UF 2.2UF 10UF 10UF 2.2UF

6.3V 2 20% 20% 10% 20% 20% 10%
X5R 6.3V 2 6.3V 6.3V 2 6.3V 6.3V 6.3V 2
402 X5R CERM-X5R 2 X5R CERM-X5R 2 CERM-X5R 2 X5R
402 0402 402 0402 0402 402
54 52 47 PP1V3_CAM
54 52 47 PP1V0_SOC
54 52 47 PP2V6_CAM_AF
54 52 47 PP2V9_CAM
54 52 47 PP1V8_ALWAYS
CRITICAL CRITICAL CRITICAL CRITICAL

C8242 1 C8241 1
C8240 1 C8239 1 C8238 1
0.22UF 10UF 10UF 4.7UF 4.7UF
20% 20% 20% 20% 20%
6.3V 2 6.3V 6.3V 6.3V 6.3V
X5R CERM-X5R 2 CERM-X5R 2 X5R-CERM1 2 X5R-CERM1 2
0201 0402 0402 402 402

PAGE TITLE
PMU: ANYA PAGE 2

DRAWING NUMBER SIZE

REVISION
R
A.0.0
82 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_ALT_HEAD

REVIEW: VERIFY NC ON TDEV2 IS OK PART NUMBER
TABLE_ALT_ITEM
138S0739 138S0706 C8308
1
R8303
I2C ADDRESS: 0111100X (0X78) 1 C8305 200K
0.1UF 1%
10% 1/20W
6.3V MF
OMIT_TABLE 2 CERM-X5R 2 201
0201
U8100
D D2089A0
FCBGA
D
SYM 3 OF 4 PLACE_NEAR=U8100.T11:3MM
PLACE_NEAR=U8100.M17:4MM
1 C8300 1 C8301 1 C8302 GPIO_BTN_HOME_L D5 BUTTON1 IREF T12 PMU_IREF
1 C8306 1 C8307 1 C8308
0.01UF 0.01UF 0.01UF
13 5 IN NET_SPACING_TYPE=ANLG 0.1UF 1UF 1.0UF
ANALOG
GPIO_BTN_ONOFF_L D6 V13 PMU_VREF 10% 10% 20%
32K REFRENCES
BUTTON2 VREF
INPUT
10% 10% 10% 17 5 IN
2 6.3V 2 6.3V 2 6.3V D7 M17
2 6.3V
CERM-X5R 2 10V
X5R
10V
2 X5R-CERM
X5R X5R X5R 17 5 IN GPIO_BTN_SRL_L BUTTON3 VDD_REF PMU_VDD_REF
NET_SPACING_TYPE=ANLG 0201 402-1 0201-1
01005 01005 01005 D8 T11
NC_ANYA_BUTTON4 BUTTON4 VDD_REF_A
43 IN PMU_E75_ACC_DET_L T7 ACC_DET VDD_RTC U13 PMU_VDD_RTC
ADC_REF T13 PMU_ADC_REF NET_SPACING_TYPE=ANLG
R8399 R12
DIGITAL
PMU_ACC_ID ACC_ID MIN_LINE_WIDTH=0.1MM
0.00 2
CLK
INPUT
11 PMU_USB_BRICKID 1 52 PMU_USB_BRICKID_R P16 BRICK_ID OUT_32K T14 NC_PMU_OUT_32K_CLK_GPS 1 C8310
IN
1% ADC_IN7 N16 ADC_IN7 T6
1000PF
1/20W GPIO1 PMU_GPIO_CLK_32K_OSCAR 19 52
10%
MF R11 ADC_IN31 OUT 6.3V
2 X5R-CERM
0201 GPIO2 T5 PMU_GPIO_CLK_32K_WLAN 44 52
OUT 01005
T8 T4
WDOG
5 IN GPIO_SOC2PMU_KEEPACT KEEPACT GPIO3 PMU_GPIO_BT_REG_ON OUT 44 52
1
IN PMU_SHDWN (INTERNAL PULL-DOWN) T9 SHDN GPIO4 R3 PMU_GPIO_WLAN_REG_ON OUT 44 52
R8330
CRITICAL
PLACE_NEAR=U8100.R9:10MM
P3 1.00K2
1 C8327 (INTERNAL PULL-DOWN) R5 GPIO5 PMU_GPIO_PMU2BBPMU_RST_R_L 1 PMU_GPIO_PMU2BBPMU_RST_L OUT 24 26 52
R8327 PA_NTC_P 10 IN WDOG_SOC2PMU_RESET_IN RESET_IN1 N3 UART5_BATT_RTXD
100PF TS2PMU_RESET_IN R6 GPIO6 IN 5 45 5%
1/32W
10KOHM-1%-0.31MA 5% 11 IN RESET_IN2 M3
RESET
16V PA_NTC_N R7 GPIO7 PMU_GPIO_BT_HOST_WAKE IN 44 52 MF
0201 2 NP0-C0G 5 IN
SOCHOT1_L RESET_IN3 L3 01005
PLACE_NEAR=U4000.1:10MM 01005 R8 GPIO8 PMU_GPIO_WLAN_HOST_WAKE IN 44 53
PLACE_SIDE=TOP 2 52 24 11 10 8 4 OUT RESET_SOC_L RESET* K3
GPIO
(TEMP1 - NEAR BB) (PULLUP INSIDE SOC)T15 GPIO9 PMU_GPIO_BB2PMU_HOST_WAKE IN 24 28 52
5 GPIO_PMU2SOC_IRQ_L
OUT IRQ* J3
GPIO10 PMU_GPIO_CODEC_HS_INT_L IN 15 52
52 11 5 I2C0_SCL_1V8 E12 SCL GPIO11 H3 PMU_GPIO_MB_HALL1_IRQ 13

IN IN
I2C & DWI

52 11 5 I2C0_SDA_1V8 E13 SDA GPIO12 G3 GPIO_TS2SOC2PMU_INT 5 11
BI IN
1 F3
PLACE XW AND CAP (INTERNAL PULL-DOWN) E11 GPIO13 PMU_GPIO_MB_HALL2_IRQ IN 13
CRITICAL
52 5 IN DWI_AP_CLK DWI_CK E3
1 C8321 CLOSE TO PMU (INTERNAL PULL-DOWN) E10 GPIO14 PMU_GPIO_MB_HALL3_IRQ IN 13
NOTE: NEW ON J85
R8321 100PF
52 BOARD_TEMP3_P
53 5 IN DWI_AP_DO DWI_DI
GPIO15 D3 PMU_GPIO_CODEC_RST_L 15
5% NC_DWI_AP_DI NO_TEST=TRUE
E9 DWI_DO OUT
10KOHM-1%-0.31MA XW8327 C3
16V
2 NP0-C0G
BOARD_TEMP3_N GPIO16 PMU_GPIO_OSCAR2PMU_HOST_WAKE IN 5 19
C 0201
PLACE_NEAR=U5800.30:10MM
PLACE_SIDE=TOP 2
01005
1
SM
2
NET_SPACING_TYPE=BOARD_TEMP R9
R10
TDEV1
TDEV2
GPIO17 C4 PMU_GPIO_BB_VBUS_DET OUT 24 27 52 C
NC AMUX_A0 E4 NC_PPVDD_CPU_SOC_SENSE
(TEMP3 - TOP SIDE NEAR WIFI) NET_SPACING_TYPE=BOARD_TEMP R13 TDEV3
PLACE_NEAR=U8100.R13:10MM AMUX_A1 F4 NC_PPVDD_GPU_SOC_SENSE
NET_SPACING_TYPE=BOARD_TEMP R14 TDEV4
TEMPERATURE
XW8321 AMUX_A2 G6 NC_PPVDD_SOC_SOC_SENSE
1 2 NET_SPACING_TYPE=BOARD_TEMP L4 TDEV5
ANALOG MUX
1 AMUX_A3 J6 NC_ADC_SMPS1_MSMC_1V05
PLACE_NEAR=U8100.R14:10MM SM NET_SPACING_TYPE=BOARD_TEMP M4 TDEV6
CRITICAL AMUX_AY G4 NC_AMUX_AY
1 C8322 52 BOARD_TEMP4_P NET_SPACING_TYPE=BOARD_TEMP N4 TDEV7
R8322 100PF PLACE_NEAR=U8100.R14:10MM
P4 AMUX_B0 K4 NC_PPVDD_CPU_RAIL_SENSE
10KOHM-1%-0.31MA
5% XW8322 NET_SPACING_TYPE=BOARD_TEMP
TDEV8 J4
16V BOARD_TEMP4_N 1 2 R16 AMUX_B1 NC_PPVDD_GPU_RAIL_SENSE
2 NP0-C0G 52 45 BATT_NTC NET_SPACING_TYPE=ANLG
TBAT
0201 IN K6 NC_PPVDD_SOC_RAIL_SENSE
01005 SM R15 AMUX_B2
PLACE_NEAR=UJ000.8:10MM
2
PMU_TCALNET_SPACING_TYPE=ANLG TCAL
PLACE_SIDE=TOP AMUX_B3 L6 NC_ADC_SMPS3_MSME_1V8
(TEMP4 - TOP SIDE NEAR SIM) PLACE_NEAR=U8100.L4:10MM
2 CRITICAL AMUX_BY H4 NC_AMUX_BY
XW8323 C8340 1 R8340
1 2 100PF 3.92K
5% 0.1%
SM 16V 0201
1 PLACE_NEAR=U8100.L4:10MM NP0-C0G 2 1/20W
MF
01005 1
CRITICAL 1 C8323 52 BOARD_TEMP5_P PLACE_NEAR=U8100.M4:10MM
R8323 100PF XW8324
5% RESISTOR FOR TEMP CALIBRATION
10KOHM-1%-0.31MA 16V
2 NP0-C0G
BOARD_TEMP5_N 1 2
0201 01005 SM
PLACE_NEAR=U1600.A1:10MM
PLACE_SIDE=TOP 2
PLACE_NEAR=U8100.N4:10MM
(TEMP5 - TOP SIDE NEAR NAND) XW8325
1 2
SM
1
PLACE_NEAR=U8100.M4:10MM PLACE_NEAR=U8100.P4:10MM
CRITICAL XW8326
R8324 1 C8324 52 BOARD_TEMP6_P 1 2
100PF BOARD_TEMP6_N SM
10KOHM-1%-0.31MA 5%
B 0201
PLACE_NEAR=J2800.1:10MM
16V
2 NP0-C0G
01005
B
PLACE_SIDE=TOP 2
(TEMP6 TOP SIDE NEAR REAR CAM)
1
PLACE_NEAR=U8100.N4:10MM
CRITICAL 52 BOARD_TEMP7_P
R8325 1 C8325
10KOHM-1%-0.31MA 100PF BOARD_TEMP7_N
5%
0201 16V
2 NP0-C0G
PLACE_NEAR=U0600.W19:10MM
PLACE_SIDE=BOTTOM 2 01005
(TEMP7 - BOTTOM SIDE NEAR SOC)
BUCK6 POWER IS ON IN HIBERNATE DUE TO WIFI PAS

1 SWITCH NEEDED TO GATE POWER TO NAND AND SOC
PLACE_NEAR=U8100.P4:10MM
CRITICAL REVIEW: CHECK FOR POWER SEQUENCING VOILATIONS BETWEEN PP1V8 AND PP3V3
R8326 1 C8326 52 BOARD_TEMP8_P
100PF =PP3V3_S2R_SWITCH
10KOHM-1%-0.31MA 5% BOARD_TEMP8_N 54
16V
0201 2 NP0-C0G
PLACE_NEAR=U8100.K9:10MM
PLACE_SIDE=BOTTOM 2
01005 54 52 49 47 46
PPVCC_MAIN 1 C8355
1.0UF
(TEMP8 - BOTTOM SIDE NEAR PMU) 20%
CRITICAL 2 6.3V
1
1 C8350 X5R
0201-1
0.1UF VDD
10%
16V
2 X5R-CERM U8350
0201 SLG5AP1443V
VCC_MAIN_PP3V3SW_RAMP 7
TDFN 3
CAP D
A 54 12 =PP1V8_NAND 2 ON S 5 PP3V3_SW 52 54
PAGE TITLE
1
R8352 1
CRITICAL
C8352
GND
1
CRITICAL
C8356
PMU: ANYA PAGE 3
8
100K 10UF DRAWING NUMBER SIZE
5% 4700PF
TABLE_ALT_HEAD
1/32W
MF
10%
10V
20%
10V
2 X5R-CERM Apple Inc. 051-0886 D
PART NUMBER 01005 2 X7R REVISION
2 201 0402-2 R
107S0150 107S0208
R8321,R8322,R8323,R8324,R8325,R8326
TABLE_ALT_ITEM
A.0.0
TABLE_ALT_ITEM NOTICE OF PROPRIETARY PROPERTY: BRANCH
118S0764 118S0717 R8340 THE INFORMATION CONTAINED HEREIN IS THE
83 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
OMIT_TABLE
U8100
D2089A0
FCBGA
SYM 4 OF 4
M1 H10
M2 VSS_BUCK01 H11
H12
T1
H13
T2 VSS_BUCK1_12
J7
H1 J8
H2 VSS_BUCK0_12 J9
J10
U6
J11
V6 VSS_BUCK25
J12
A6 J13
B6 VSS_BUCK34 K7
K8
D1
K9
D2 VSS_BUCK06
K10
D18 VSS_WLED K11
D19 K12
K13
B18 VSS_LCM
L7
A19 L8
C D15 L9 C
V19 L10
D4 L11
C5 L12
C6 L13
C7 M7
C8 M8 ADD A VIA PER PIN FOR ALL VSS_* AND VSSA_* PINS
D9 VSS M9
D10 M10
D11 M11
D12 M12
D13 M13
D14 N6
E17 N7
F7 N8
F8 N9
XW8410
THROTTLER F9
F10
F11
N10
N11
N12
SHORT-10L-0.1MM-SM
PPVCC_MAIN 1 2 VCC_MAIN_UVLO_SENSE VSS
54 52 48 47 46 F12 N13
F13 P8
G7 P9
G8 P10
R84511 G9 P11
4.7K
1% G10 P12
NOSTUFF 1/32W
1 MF G11 P13
B R8450
150K
1%
01005 2 =PP3V0_SPARE1 54
G12
G13
R4
T3
B
1/32W MAIN_UVLO_SENSE_R 1 C8400
MF H7 U3
01005 2 0.1UF
20% H8
R84101 6.3V
2 X5R-CERM R8445 H9
75K 01005 0.00 2
1% SOCHOT0_R_L 1 SOCHOT0_L 5 52
1/32W OUT
NOSTUFF MF 0%
01005 2 3 1/32W
R8420 U8400 MF
=PP3V0_UVLO 150K 2 A3 MAX9039BEBT+ 01005
54 1
UCSP D
VCC
1% UVLO_COMP_NEG B2 APN 353S4103

1/32W Q8440
MF A2 THROTTLER_OUT 2 G DMN2990UFA
REF
01005
NOSTUFF B1 S DFN0806-VML0806-COMBO-N78
1 C8460 R8411 1
VEE
B3 1
100PF 50K R8435
5%
6.3V 1% A1 100K 1
2 CERM 1/32W 5%
01005 MF 1/32W
01005 2 UVLO_COMP_REF 49 MF
2 01005
R8425 R8430
1.00K2 255K 2
49 UVLO_COMP_REF 1 UVLO_COMP_POS 1
1% 1%
1/32W 1/32W
MF MF
01005 01005
PAGE TITLE
PMU: ANYA PAGE 4

DRAWING NUMBER SIZE

REVISION
R
A.0.0
84 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
SWITCH TO GATE POWER TO SOC AND NAND. NEEDED FOR J72 ROUTING.
CRITICAL
U8550
TPS22924X
CSP
54 =PP1V8_S2R_EXT_SWITCH A2 A1 PP1V8_EXT_SW 52 54
B2 VIN VOUT B1
1 C8550
10UF PP1V8_SW1 C2 ON
20% 54 52 46
10V
2 X5R-CERM GND
0402-2
C1
1 C8555
0.01UF
10%
6.3V
2 X5R
01005
C C
B B

PAGE TITLE
POWER: PP1V8_SW
DRAWING NUMBER SIZE

REVISION
R
A.0.0
85 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
DEBUG
=PP1V8_S2R_MISC TP9002
1
54 5
A
TP-P55
C C
SEP EEPROM
UNPROGRAMMED P/N: 335S0894
=PP1V8_EEPROM 54
1 C9000
0.22UF
A1
20%
CRITICAL 2 6.3V
X5R
VCC 0201
B U9000 B
CAT24C08C4A
WLCSP
5 SEP_I2C0_SCL B1 SCL SDA B2 SEP_I2C0_SDA 5
VSS
A2
PAGE TITLE
SEP: EEPROM & SOC DEBUG

DRAWING NUMBER SIZE

REVISION
R
A.0.0
90 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RF TEST POINTS
TP93001 TP93801 TP93G11
A GPIO_CODEC_IRQ_L 5 15 A OVP_SW_EN_L_R 46
A PP_SMPS1_MSMC_1V05 25 27
TP93041
TP-P5 TP-P5
TP9301
TP-P5 STANDOFFS: P/N 860-1657
A PMU_GPIO_CODEC_HS_INT_L 15 48
A PP_SMPS3_MSME_1V8 24 25 27 28 30
TP-P5
TP93821 TP93G51
TP-P5 STD9300
A PMU_GPIO_BT_HOST_WAKE 44 48
A PP_SMPS5_DSP_1V05 25 STDOFF-3.3X1.8R1.28H-SM
TP-P5 TP-P5
TP93031 TP93831 TP93E11
A BATT_NTC 45 48 A PMU_GPIO_BT_REG_ON 44 48 A PP_LDO1 25 1
TP-P5 TP-P5 TP-P5
TP93841 TP93G41 TP93H91
A PMU_GPIO_CLK_32K_OSCAR 19 48
A PP_SMPS4_RF2_2V05 25 30 A TP_BB_TEST_MODE_0 27
TP-P5 TP-P5 TP-P5
TP93051 TP93851 TP93I01
A PPLED_OUT_A 47 54
A PMU_GPIO_CLK_32K_WLAN 44 48
A TP_BB_TEST_MODE_1 27
TP93961
TP-P5 TP-P5
TP9302
TP-P5 STD9301
A PP3V0_UVLO 47 54 A SIMCRD_RST_CONN 10 24 28 STDOFF-3.3X1.8R1.28H-SM
TP-P5 TP-P5
TP93971 TP93871 TP93B9
D A
TP93981
TP-P5
PP3V0_SPARE1
SOCHOT0_L
47 54 A
TP93881
PMU_USB_BRICKID_R
TP-P5
PP1V0_SOC
48 A
TP93E7
SIMCRD_CLK_CONN
TP-P5
SIMCRD_IO_CONN
10 24 28 1
D
A TP-P5
5 49
A TP-P5
47 54
A TP-P5
10 24 28
TP93891 TP93G91 TP93E8
A PP1V2_S2R 46 47 54 A SOC_TESTMODE 4 10 A SIM_TRAY_DETECT 10 24 28
TP-P5 TP-P5 TP-P5
TP93901 TP93F31
A PP1V2_S2R_SW2 46 54 A PP_LDO6_RUIM_1V8 10 24 25 27
TP-P5 TP-P5
TP93911 TP93H11 TP93J2
A PP1V2_SW1 46 54
A SPI1_GRAPE_CS_L 5 13
A GPIO_SOC2BB_RADIO_ON_L 5 24 26
TP-P5 TP-P5 TP-P5
TP93121 TP93H21 TP93J3
A BOARD_TEMP3_P 48
A SPI1_GRAPE_MISO 5 13
A GPIO_SOC2BB_RST_L 5 24 26
TP-P5 TP-P5 TP-P5
TP93131 TP93931 TP93H31 TP93J4
A BOARD_TEMP4_P 48 A PP1V7_VA_VCP 16 47 54
A SPI1_GRAPE_MOSI 5 13 A PMU_GPIO_PMU2BBPMU_RST_L 24 26 48 STANDOFF: P/N 860-1683
TP-P5 TP-P5 TP-P5 TP-P5
TP93141 TP93H41 TP93811
A BOARD_TEMP5_P 48
A SPI1_GRAPE_SCLK_R 13
A PMU_GPIO_BB2PMU_HOST_WAKE 24 28 48 STD9302
TP-P5 TP-P5 TP-P5
TP93151 TP93951 TP93H51 TP93J5 STDOFF-3.3X2.2R1.35H-SM-1
A BOARD_TEMP6_P 48 A PP1V8_ALWAYS 47 54 A SPKR_L_CONN_N 16 43 A PS_HOLD_PMIC 24 26
TP93161 TP93H61 TP93271 1
A BOARD_TEMP7_P 48 A SPKR_L_CONN_P 16 43 A DEBUG_RST_L 24 27
TP-P5 TP-P5 TP-P5
TP93171 TP93H71 TP93061
A BOARD_TEMP8_P 48 A SPKR_R_CONN_N 16 43 A BB_JTAG_RTCLK 24 27
TP-P5 TP-P5 TP-P5
TP93181 TP93H81 TP93071
A CLK_32K_SOC2CUMULUS 5 13
A SPKR_R_CONN_P 16 43
A BB_JTAG_TCK 5 24 27
TP-P5 TP-P5 TP-P5
TP93081
A BB_JTAG_TDI 5 24 27
TP-P5
TP93201 TP93A01 TP93091
A CODEC_HP_DET_R 15
A PP1V8_EXT_SW 50 54
A BB_JTAG_TDO 5 24 27
PLATED THROUGH HOLES
TP-P5 TP-P5 TP-P5
TP93211 TP93A11 TP93I11 TP93101
A CODEC_HP_HS3 15
A PP1V8_GRAPE_FILT 13
A TP_JTAG_SOC_TDO 4
A BB_JTAG_TMS 5 24 27
DRILL SIZE: 1.1MM X 0.4MM
TP93221 TP93A21 TP93I21 TP93111
A CODEC_HP_HS3_REF 15 A PP1V8_GRAPE_SW 13 A TP_JTAG_WLAN_TCK 44 A BB_JTAG_TRST_L 5 24 27 PLATING SIZE: 1.4MM X 0.7MM
TP93231 TP93A31 TP93I31 TP93J6
A CODEC_HP_HS4 15 A PP1V8_PLL_SOC_F 4 A TP_JTAG_WLAN_TRST_L 44 A USB_BB_N 11 24 53
TP93241 TP93A41 TP93I41 TP93J7
A TP-P5
CODEC_HP_HS4_REF 15
A TP-P5
PP1V8_S2R 46 47 54
A TP-P5
UART0_SOC_RXD 5 11
A TP-P5
USB_BB_P 11 24 53 SL9300
TH-NSP
TP93251 TP93I51 TP93G61
A CODEC_HP_LEFT 15
A UART0_SOC_TXD 5 11
A RESET_SOC_L 4 8 10 11 24 48 1
TP-P5 TP-P5 TP-P5
TP93261 TP93A61 TP93I61 TP93J8
A CODEC_HP_RIGHT 15 A PP1V8_S2R_SW3_COMP 54 A UART3_BB2SOC_TX 5 11 24 28 A PMU_GPIO_BB_VBUS_DET 24 27 48 SL-1.1X0.4-1.4X0.7
TP93A71 TP93I71
A PP1V8_SW1 46 50 54 A UART3_SOC2BB_TX 5 11 24 28
TP-P5 TP-P5
TP93281 TP93A81 TP93I81
A DISPLAY_SYNC_R A PP1V8_SW2 A UART6_TS_ACC_RXD
C TP93291
A
TP-P5
TP-P5
DWI_AP_CLK
13
5 48
TP93A91
A
TP-P5
TP-P5
PP1V8_XTAL
46 54
8
TP93I91
A
TP-P5
TP-P5
UART6_TS_ACC_TXD
5 11
5 11
C
TP93301 TP93B01 TP93J01
A TP-P5
E75_DPAIR1_CONN_N 43 A TP-P5
PP2V6_CAM_AF 47 54 A TP-P5
USB_SOC_N 4 11 SL9303
TH-NSP
TP93311 TP93J11
A E75_DPAIR1_CONN_P 43 A USB_SOC_P 4 11 1
TP-P5 TP-P5
TP93321
A E75_DPAIR2_CONN_N 43 SL-1.1X0.4-1.4X0.7
TP-P5
TP93331
A TP-P5
E75_DPAIR2_CONN_P 43 SL9304
TH-NSP
TP93341 TP93J91
A FMI0_CE0_L 6 12
A PP3V0_ALS 47 54 1
TP-P5 TP-P5
TP93351 TP93JA1
A FMI1_CE0_L 6 12 A PP2V9_CAM 47 54
SL-1.1X0.4-1.4X0.7
TP-P5 TP-P5
TP93361 TP93JB1
A TP-P5
GND A TP-P5
PP1V3_CAM 47 54 SL9305
TH-NSP
TP93371 TP93JC1
A GND_AUDIO_CODEC 15 A PMU_GPIO_WLAN_REG_ON 44 48 1
TP-P5 TP-P5
TP93381 TP93B81
A GPIO_BTN_HOME_FILT_L 13 A PP3V0_S2R_HALL_FILT 13 SL-1.1X0.4-1.4X0.7
TP-P5 TP-P5
TP93391
A GPIO_BTN_ONOFF_L_FILT 17
TP-P5
TP93401 TP93C01
A GPIO_BTN_SRL_L_FILT 17 A PP3V0_S2R_SENSOR 47 54
TP-P5 TP-P5
TP93411 TP93C11
A GPIO_BTN_VOL_DOWN_L_FILT 17
A PP3V0_S2R_TRISTAR 47 54
TP-P5 TP-P5
TP93421
A GPIO_BTN_VOL_UP_L_FILT 17
TP-P5
TP93431
A GPIO_FORCE_DFU 5
TP93C31
A PP3V3_ACC 47 54
MH9300
TP-P5 TP-P5 3P25R2P5
TP93441 TP93C41
A GPIO_GRAPE_IRQ_L 5 13 A PP3V3_S2R 46 54 1
TP-P5 TP-P5
TP93451 TP93C51
A GPIO_GRAPE_RST_L 5 13 A PP3V3_SW 48 54
TP-P5 TP-P5
TP93461 TP93C61
A GPIO_SOC2BB_WAKE_MODEM 5 28 A PP5V25_GRAPE_FILT 13
TP-P5 TP-P5
TP93471
A GPIO_SPKAMP_KEEPALIVE 5 16
TP-P5
TP93481 TP93C81
A I2C0_SCL_1V8 5 11 48 A PP6V0_LCM_VBOOST 47
TP-P5 TP-P5
TP93491 TP93C91
A I2C0_SDA_1V8 5 11 48 A PPBATT_VCC 46 54
B TP93501
A
TP-P5
TP-P5
I2C2_SCL_1V8 5 16
TP93D01
A
TP-P5
TP-P5
PPLED_BACK_REG_A 18
B
TP93511 TP93D11
A I2C2_SDA_1V8 5 16 A PPOUT_E75_ACC_ID1_CONN 43
TP-P5 TP-P5
TP93521 TP93D21
A ISP0_CAM_REAR_CLK 7 23 A PPOUT_E75_ACC_ID2_CONN 43
TP-P5 TP-P5
TP93531 TP93D31 860-1688
A ISP0_CAM_REAR_SCL 7 23
A PPVBUS_PROT 11 46
TP-P5 TP-P5
TP93541
A ISP0_CAM_REAR_SDA 7 23
TP93D41
A PPVBUS_USB_DCIN 46 54
MH9302
TP93551
TP-P5
TP93D51
TP-P5 WASHER-BTN-MLB-X221
A ISP0_CAM_REAR_SHUTDOWN_L 7 23 A PPVCC_MAIN 46 47 48 49 54 TH
TP-P5 TP-P5
TP93561 TP93D61 1
A ISP1_CAM_FRONT_CLK 7 20
A PPVCC_MAIN_LCD_SW_CONN 18
TP-P5 TP-P5
TP93571 TP93D71
A ISP1_CAM_FRONT_SCL 7 20
A PPVDD_CPU 46 54
TP-P5 TP-P5
TP93581 TP93D81
A ISP1_CAM_FRONT_SDA 7 20
A PPVDD_GPU 46 54
TP-P5 TP-P5
TP93591 TP93D91
A ISP1_CAM_FRONT_SHUTDOWN_L 7 20 A PPVDD_SOC 46 54
TP93601
TP-P5
TP93E01
TP-P5 NEAR BUTTON FLEX CONN
A JTAG_SOC_SEL 4 10
A PPVDD_SRAM 46 54
TP-P5 TP-P5
TP93611
A JTAG_SOC_TCK 4 11
TP-P5
TP93621
A JTAG_SOC_TDI 4
TP-P5
TP93631
A JTAG_SOC_TMS 4 11
TP-P5
TP93641
A JTAG_SOC_TRST_L 4 10
TP-P5
TP93651
A JTAG_WLAN_SEL 44
TP-P5
TP93661
A OSCAR2RADIO_CONTEXT_A 19 28 44
TP-P5
TP93671
A OSCAR2RADIO_CONTEXT_B 19 28 44
TP-P5
TP93681
A WLAN_TX_BLANK 28 44
TP-P5
TP93691
A LAT_SW1_CTL 14 24 28
TP-P5
TP93701
A A
TP93711
TP-P5
LAT_SW2_CTL 14 28
SYNC_MASTER=J85 MLB_C SYNC_DATE=12/03/12 A
A TP-P5 PAGE TITLE
TP93721
A
TP93731
TP-P5
LED_IO1_A_R 47
TEST: TP/HOLES/FIDUCIALS
A LED_IO2_A_R 47 DRAWING NUMBER SIZE
TP-P5
TP93741
A LED_IO3_A_R 47
TP-P5
TP93751 REVISION
A LED_IO4_A_R 47 R
TP93761
TP-P5 A.0.0
A LED_IO5_A_R 47
TP-P5
TP93771
A LED_IO6_A_R 47 THE INFORMATION CONTAINED HEREIN IS THE
TP-P5 PROPRIETARY PROPERTY OF APPLE INC.
TP93781 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
A MIKEY_TS_N 11 15
TP93791
TP-P5
MIKEY_TS_P
93 OF 121
A TP-P5
11 15
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FOR FRANK (SEG)
EE CHARACTERIZATION TP
PP9450 PP
1 PPVDD_SOC_SOC_SENSE PLACE_NEAR=U0652.V31:1MM 9
P4MM SM
NAND PP9451 PP
1 PPVDD_CPU_SOC_SENSE PLACE_NEAR=U0652.AN30:1MM 9
P4MM SM
PLACE_SIDE=BOTTOM
PP9401
P4MM SM
PP
1 FMI0_DQS PLACE_NEAR=U0652.D34:2MM 6 12 53
PLACE_SIDE=BOTTOM
PP9402
P4MM SM
PP
1 FMI0_AD<3> PLACE_NEAR=U0652.C34:2MM 6 12
PP9403 1 FMI0_DQS PLACE_NEAR=U0652.D34:2MM
D P4MM SM
PP 6 12 53
D
PP9410SM
PP
1 TP_TCKC_U1400 12
P4MM
PP9411
P4MM SM
PP
1 TP_TMSC_U1400 12
PP9412
P4MM SM
PP
1 TP_U1400_RB0 12
PP9413
P4MM SM
PP
1 TP_U1400_RB1 12
DWI WIFI
PP9480
P4MM SM
PP HSIC1_WLAN2SOC_DEVICE_RDY 5 44
PLACE_SIDE=BOTTOM
PP9405
P4MM SM
PP
1 DWI_AP_DO PLACE_NEAR=U8100:2MM 5 48 PP9481
P4MM SM
PP HSIC1_WLAN2SOC_REMOTE_WAKE 5 44
PP9482
P4MM SM
PP PMU_GPIO_WLAN_HOST_WAKE 44 48
AUDIO PP9483SM
PP HSIC1_SOC2WLAN_HOST_RDY 5 44
P4MM
PP9406
P4MM SM
PP
1 I2S0_CODEC_ASP_MCK PLACE_NEAR=U1900:2MM 5 15
GPIO_BT_WAKE FUNC_TEST=TRUE 5 44
I76
FOR HSIC CHARACTERIZATION

PP9416
P4MM SM
PP
1 I2S2_CODEC_XSP_LRCK PLACE_NEAR=U1900:2MM 5 15 PP9460
P4MM SM
PP
1 HSIC1_WLAN_DATA PLACE_NEAR=U0652.AM33:3MM 4 44 53
PP9417
P4MM SM
PP
1 I2S2_CODEC_XSP_DOUT PLACE_NEAR=U1900:2MM 5 15
PP9462SM
PP
1 HSIC1_WLAN_DATA PLACE_NEAR=U5800.13:3MM 4 44 53
P4MM
C PP9463
P4MM SM
PP
1 HSIC1_WLAN_STB PLACE_NEAR=U5800.14:3MM
4 44 C
PP9419
P4MM SM
PP
1 I2S1_SPKAMP_MCK PLACE_NEAR=U2040:2MM 5 16
PP9420
P4MM SM
PP
1 I2S1_SPKAMP_BCLK PLACE_NEAR=U2040:2MM 5 16 PP9468
P4MM SM
PP
1 UART1_BT2SOC_TX PLACE_NEAR=U0652:3MM 5 44
PP9421SM
PP
1 I2S1_SPKAMP_LRCK PLACE_NEAR=U2040:2MM 5 16 PP9469SM
PP
1 UART1_SOC2BT_TX PLACE_NEAR=U5800:3MM 5 44
P4MM P4MM
PP9422SM
PP
1 I2S1_SPKAMP_DOUT PLACE_NEAR=U2040:2MM 5 16
P4MM PLACE_SIDE=BOTTOM
PP9423
P4MM SM
PP
1 I2S1_SPKAMP_DIN PLACE_NEAR=U0652:2MM
5 16 PP9471
P4MM SM
PP
1 UART2_WLAN2SOC_TX PLACE_NEAR=U0652:3MM
5 44
PP9472
P4MM SM
PP
1 UART2_SOC2WLAN_TX PLACE_NEAR=U5800:3MM 5 44
PP9424
P4MM SM
PP
1 SPI2_CODEC_SCLK PLACE_NEAR=U1900:2MM 5 15
PP9425SM
PP
1 SPI2_CODEC_MOSI PLACE_NEAR=U1900:2MM 5 15
P4MM PLACE_SIDE=BOTTOM
PP9426SM
PP
1 SPI2_CODEC_MISO PLACE_NEAR=U0652:2MM 5 15
P4MM
GRAPE
BASEBAND
USB_BB_P FUNC_TEST=TRUE 11 24 52
I192
OSCAR PLACE_SIDE=BOTTOM
I193
USB_BB_N FUNC_TEST=TRUE 11 24 52
PP9428
P4MM SM
PP
1 UART4_SOC2OSCAR_TXD PLACE_NEAR=U2400:2MM 5 19 FOR HSIC CHARACTERIZATION
PLACE_SIDE=BOTTOM
PP9429
P4MM SM
PP
1 UART4_OSCAR2SOC_RXD PLACE_NEAR=U0652:2MM 5 19
PP9465
P4MM SM
PP
1 HSIC2_BB_STB PLACE_NEAR=U0652.B27:3MM 4 24 27
UART5 PP9466SM
PP
1 HSIC2_BB_DATA PLACE_NEAR=U3400.C7:3MM 4 24 27
P4MM
B B
PROX
HIGH SPEED, NO TEST

MIPI0C_CAM_REAR_CLK_P NO_TEST=TRUE 7 23 53
I141
MIPI0C_CAM_REAR_CLK_N NO_TEST=TRUE 7 23 53
I140
MIPI0C_CAM_REAR_DATA_P<0..3> NO_TEST=TRUE 7 23 53
I139
MIPI0C_CAM_REAR_DATA_N<0..3> NO_TEST=TRUE 7 23 53
I138
MIPI0C_CAM_REAR_CLK_FILT_P NO_TEST=TRUE 23
I142
MIPI0C_CAM_REAR_CLK_FILT_N NO_TEST=TRUE 23
I144
MIPI0C_CAM_REAR_DATA_FILT_P<0..3> NO_TEST=TRUE 23
I145
MIPI0C_CAM_REAR_DATA_FILT_N<0..3> NO_TEST=TRUE 23
I143
MIPI1C_CAM_FRONT_CLK_P NO_TEST=TRUE 7 20 53
I146
MIPI1C_CAM_FRONT_CLK_N NO_TEST=TRUE 7 20 53
I149
CAMERA I150
MIPI1C_CAM_FRONT_DATA_P<0> NO_TEST=TRUE
NO_TEST=TRUE
7 20 53
I148
MIPI1C_CAM_FRONT_DATA_N<0> 7 20 53
PP9440 1 MIPI1C_CAM_FRONT_CLK_P PLACE_NEAR=U0652.AR33:3MM 7 20 53 MIPI1C_CAM_FRONT_CLK_FILT_P NO_TEST=TRUE 20
P4MM SM PP I147
MIPI1C_CAM_FRONT_CLK_FILT_N NO_TEST=TRUE 20
A PP9441
P4MM SM PP
1 MIPI1C_CAM_FRONT_CLK_N PLACE_NEAR=U0652.AR34:3MM
7 20 53
I152
I151
I153
MIPI1C_CAM_FRONT_DATA_FILT_P<0>
MIPI1C_CAM_FRONT_DATA_FILT_N<0>
NO_TEST=TRUE
NO_TEST=TRUE
20
20
PP9442
P4MM SM PP
1 MIPI1C_CAM_FRONT_DATA_P<0> PLACE_NEAR=U0652.AT33:3MM 7 20 53
PAGE TITLE
PP9443 1 MIPI1C_CAM_FRONT_DATA_N<0> PLACE_NEAR=U0652.AT34:3MM

7 20 53 I187
EDP_DATA_P<0..3> NO_TEST=TRUE 7 18
TEST: EE TP/PP
P4MM SM PP I185
EDP_DATA_N<0..3> NO_TEST=TRUE 7 18 DRAWING NUMBER SIZE
EDP_DATA_EMI_P<0..3> NO_TEST=TRUE
PP9444
P4MM SM PP
1 MIPI0C_CAM_REAR_CLK_P PLACE_NEAR=U0652.AU25:3MM 7 23 53 I186
EDP_DATA_EMI_N<0..3> NO_TEST=TRUE
18
18 Apple Inc. 051-0886 D
I188
EDP_DATA_EMI_CONN_P<0..3> NO_TEST=TRUE REVISION
PP9445 1 MIPI0C_CAM_REAR_CLK_N PLACE_NEAR=U0652.AV25:3MM 7 23 53 I190
18
R
P4MM SM PP I189
EDP_DATA_EMI_CONN_N<0..3> NO_TEST=TRUE 18 A.0.0
PP9446
P4MM SM PP
1 MIPI0C_CAM_REAR_DATA_P<0> PLACE_NEAR=U0652.AU27:3MM 7 23 53 NOTICE OF PROPRIETARY PROPERTY: BRANCH
PP9447
P4MM SM PP
1 MIPI0C_CAM_REAR_DATA_N<0> PLACE_NEAR=U0652.AV27:3MM 7 23 53 PROPRIETARY PROPERTY OF APPLE INC.
94 OF 121
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
POWER CONNECTIONS
BUCK0
52 46 PPVDD_CPU =PPVDD_CPU 9
CHARGER MAIN
MAKE_BASE=TRUE
52 49 48 47 46 PPVCC_MAIN =PPVCC_MAIN_AUDIO 15 16
MAKE_BASE=TRUE
D BUCK1 =PPVCC_MAIN_LED 47
D
PPVDD_GPU =PPVDD_GPU
BUCK5 LDO7 LDO7 SHOULD BE ON IN HIBERNATE
=PPVCC_MAIN_DOCK 43
52 46
MAKE_BASE=TRUE
9 =PPVCC_MAIN_DEV
52 46 PPVDD_SRAM =PPVDD_SRAM_CPU 52 47 PP3V0_S2R_TRISTAR =PP3V0_S2R_TRISTAR 11 =PPVCC_MAIN_CPU 46
MAKE_BASE=TRUE MAKE_BASE=TRUE
=PPVDD_SRAM_SOC 9 =PPVCC_MAIN_GPU 46
BUCK2 =PPVCC_MAIN_SOC 46
52 46 PPVDD_SOC =PPVDD_SOC 9 =PPVCC_MAIN_GRAPE 13

MAKE_BASE=TRUE
=PPVCC_MAIN_LCD 18
BUCK3 BUCK6 =PPVCC_MAIN_NAVAJO

=PPVCC_MAIN_VDD_LCM 47
PP1V8_S2R =PP1V8_S2R_MISC
52 47 46
MAKE_BASE=TRUE
5 51
=PP1V8_S2R_VDDIO_WLAN_BT 44
52 46 PP3V3_S2R
MAKE_BASE=TRUE
=PP3V3_S2R_SWITCH 48 LDO8 =PPVCC_MAIN_WLAN 44
=PP1V8_S2R_TRISTAR 11
=PP3V3_S2R_WIFI_PA 44 =PPVCC_MAIN_GPS
=PP1V8_S2R_DDR 8 47 NC_LDO8 NO_TEST=TRUE =NC_LDO8
MAKE_BASE=TRUE
=PP1V8_S2R_GRAPE 13
=PP1V8_S2R_EXT_SWITCH 50
=PP1V8_S2R_REAR_CAMERA BATTERY
=PP1V8_S2R_MESA 52 48 PP3V3_SW =PP3V3_EDP_PU
MAKE_BASE=TRUE
=PP1V8_S2R_VDD_CORE_GPS =PP3V3_NAND 12
=PP1V8_S2R_VDD_IO_GPS
=PP3V3_USB_SOC 4 52 46 PPBATT_VCC =PPBATT_POS_CONN 45
MAKE_BASE=TRUE
LDO9 BACKUP RAIL. CAN BE BOOSTED TO MEET

=PPBATT_VCC_BB
=PPBATT_AUDIO
24 25 33 34 35 36 37 38
1.1V MIN ON CAMERA IF NEEDED.

BUCK3_SW PP1V3_CAM =PP1V3_CAM_FRONT
C PP1V8_SW1 =PP1V8_AUDIO
52 47
MAKE_BASE=TRUE
=PP1V3_CAM_REAR C
52 50 46
MAKE_BASE=TRUE
=PP1V8_DMIC
15
14 LDO1 23
USB POWER INPUT

=PP1V8_CAM_FRONT 20
=PP1V8_CAM_REAR 23
52 47 PP3V0_SPARE1 =PP3V0_SPARE1 49
MAKE_BASE=TRUE
=PP1V8_PROX 22
52 46 PPVBUS_USB_DCIN =PPVBUS_USB_EMI 43
MAKE_BASE=TRUE
52 50 PP1V8_EXT_SW =PP1V8_VDDIO18_SOC 8 9
LDO10
MAKE_BASE=TRUE
=PP1V8_SOC 4 5 7 10 18 52 47 PP1V0_SOC =PP1V0_USB_SOC 4
MAKE_BASE=TRUE
=PP1V8_MIPI_SOC 7 =PP1V0_MIPI_SOC
=PP1V8_EDP_SOC
=PP1V8_NAND_SOC
7
6
LDO2 =PP1V0_EDP_PAD_DVDD_SOC
7
=PP1V8_NAND 12 48
52 47 16 PP1V7_VA_VCP =PP1V7_VA_VCP 15 16
=PP1V8_PLL_SOC 4
MAKE_BASE=TRUE
ON_BUF
=PP1V8_SPKRAMP
=PP1V8_EEPROM 51 LDO11 52 47 PP1V8_ALWAYS
MAKE_BASE=TRUE
=PP1V8_ALWAYS 5
=PP1V8_BEACON
PP2V6_CAM_AF =PP2V6_CAM_REAR_AF
LDO3 LDO3 SHOULD BE ON IN HIBERNATE
COMPASS, ACCEL, GYRO, PROX ARE ON OSCAR
HALL EFFECT NEEDS TO BE ON IN HIBERNATE
52 47
MAKE_BASE=TRUE
23
52 46 PP1V8_SW2 =PP1V8_GRAPE 13 52 47 PP3V0_S2R_SENSOR =PP3V0_S2R_HALL 13

MAKE_BASE=TRUE MAKE_BASE=TRUE
=PP3V0_S2R_GYRO 21
46 PP1V8_S2R_SW3
MAKE_BASE=TRUE
=PP1V8_S2R_GYRO 21 =PP3V0_S2R_ACCEL 21 BACKLIGHT BOOST
=PP1V8_S2R_ACCEL 21 =PP3V0_S2R_COMP 21
B =PP1V8_S2R_OSCAR 19
LDO13 52 47 PPLED_OUT_A
MAKE_BASE=TRUE
=PPLED_REG_A 18 B
PP1V8_S2R_SW3_COMP 52 54
PP2V9_CAM =PP2V9_CAM_FRONT
LDO4 52 47
MAKE_BASE=TRUE
=PP2V9_CAM_REAR
20
23
54 52 PP1V8_S2R_SW3_COMP =PP1V8_S2R_COMP 21
MAKE_BASE=TRUE
PP1V8_S2R_SW3 SHOULD BE ON IN HIBERNATE 52 47 PP3V0_ALS =PP3V0_ALS 20

CURRENTLY POWERS OSCAR AND 1.8V RAIL ON SENSOR MAKE_BASE=TRUE
=PP3V0_PROX 22
=PP3V0_HP_ALS
BUCK4 =PP3V0_IO_ALS
SHOULD IO ALS POWER HERE?
52 47 46 PP1V2_S2R =PP1V2_S2R_DDR 8
MAKE_BASE=TRUE
=PP1V2_S2R_DDR_SOC
=PP1V2_S2R_CAM_REAR
8 LDO5
52 47 PP3V0_UVLO =PP3V0_UVLO 49
MAKE_BASE=TRUE
BUCK4_SW LDO6 VLCM1

52 46 PP1V2_SW1 =PP1V2_VDDQ_DDR 8
MAKE_BASE=TRUE
=PP1V2_VDDIOD_SOC PP3V3_ACC =PP3V3_ACC 47 PP5V25_GRAPE =PP5V25_GRAPE 13
A =PP1V2_HSIC_SOC
8
4
52 47
MAKE_BASE=TRUE
11
MAKE_BASE=TRUE
PAGE TITLE
52 46 PP1V2_S2R_SW2 =PP1V2_S2R_OSCAR 19
POWER: ALIASES
MAKE_BASE=TRUE
DRAWING NUMBER SIZE
PP1V2_S2R_SW2 SHOULD BE ON IN HIBERNATE
PROVIDE 1.2V TO OSCAR REVISION
R
A.0.0
121 OF 121
8 7 6 5 4 3 2 1

Sualaptop365.edu - VN - X200 - MLB - C1 051-0886 Ra00

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Sualaptop365.edu - VN - X200 - MLB - C1 051-0886 Ra00

Uploaded by

Copyright:

Available Formats

8 7 6 5 4 3 2 1

SCH AND BOARD PART NUMBERS

PDF CSA CONTENTS

051-0886 1 SCH,MLB-C1,X200 SCH1 SYNC MASTER DATE

D 820-4124 1 PCBF,MLB-C1,X200 PCB1

23 29 CAMERA: REAR CONN & FILTERS

24 30 CELL:AP INTERFACE & DEBUG CONNECTORS

25 32 CELL: BASEBAND PMU (1 0F 2)

26 33 CELL: BASEBAND PMU (2 OF 2)

PDF CSA CONTENTS SYNC MASTER DATE

29 36 CELL: RF TRANSCEIVER (1 0F 2) RADIO_MLB_87

30 37 CELL: RF TRANSCEIVER (2 OF 2) RADIO_MLB_87

3 4 BOM TABLES J72_MLB_C

4 6 SOC: MAIN N/A 04/18/2011

34 41 CELL: BAND 2/3 PAD RADIO_MLB_87

35 42 CELL: BAND 7/20 PAD RADIO_MLB_87

7 9 SOC: DP,MIPI MLB 05/04/2012 37 44 CELL: 2G PA

38 45 CELL: PA DCDC CONVERTER RADIO_MLB_87

39 46 CELL: ASM AND HB LTE FRONT-END RADIO_MLB_87

40 47 CELL: RX DIVERSITY RADIO_MLB_87

10 12 SOC: MISC & ALIASES N/A 04/11/2011 41 48 CELL: GPS RADIO_MLB_87

11 13 IO: TRISTAR N/A N/A 42 49 CELL: ANTENNA FEEDS

12 14 NAND STORAGE MLB 05/04/2012

44 58 WIFI/BT: MODULE WIFI_DEV05/20/2013

45 75 POWER: BATTERY CONNECTOR N/A N/A

B 15 19 AUDIO: L81 CODEC KAVITHA 01/18/2012 47 82 PMU: ANYA PAGE 2

16 20 AUDIO: CS35L19A AMPS KAVITHA 01/18/2012

49 84 PMU: ANYA PAGE 4 J72_MLB_C

50 85 POWER: PP1V8_SW J85 MLB_C

19 24 SENSOR: OSCAR J72_MLB_C

20 26 CAMERA: FF-ALS CONN & FILTERS J85 MLB_C

54 121 POWER: ALIASES

Apple Inc. 051-0886 D

ISP1_I2C FRONT CAMERA

BUTTON FLEX PMU BATTERY

NAND FLASH HP BLOCK DIAGRAM: SYSTEM

CSA 14 MIC1 MIC2 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

Page Notes PART#

H6P + 1GB ELPIDA

Power aliases required by this page:

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

(NONE) 339S0208 339S0207 U0652 HYNIX DDR

BOM options provided by this page:

DEVELOPMENT_JTAG_TAP PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

343S0656 1 IC,PMU,ANYA,D2089A1,OTPXX,FCCSP342 U8100 CRITICAL

WIFI BOM OPTIONS FLASH CONFIGURATIONS

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

335S0921 1 TOS,19NM,PPN1.5,C,DDP,16GB U1400 16GB

335S0922 1 TOS,19NM,PPN1.5,C,QDP,32GB U1400 32GB

335S0923 1 TOS,19NM,PPN1.5,C,ODP,64GB U1400 64GB

335S0929 1 TOS,19NM,PPN1.5,C,12DP,64GB U1400 96GB

335S0924 1 TOS,19NM,PPN1.5,C,16DP,128GB U1400 128GB

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

C 335S0931 335S0922 32GB U1400

HYNIX 20NM PPN1.5 32GB

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION

353S4272 1 IC,SLG5AP1423V,PWR SW,GREENFET3,4A,TDFN8 U2200

WIFI 4.3UF CAP

339S0223 339S0213 U5800 138S0702 138S0657 C1009,C1015,... RDAR #13988471

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

B 806-6207 1 FENCE,TALL,MLB,X221 PD_FENCE_MLB CRITICAL

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

132S0391 1 CAP 0.01UF 25V 0201 C2726 CRITICAL GYRO_STMICRO