820-00244-A CBB MLB 051-00532 Resolved

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
X260 MLB - CBB

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
<REV> <ECN> <ECO_DESCRIPTION> <ECODATE>
D D
LAST_MODIFICATION=Thu Sep 10 15:22:41 2015
<CSA> DATE PAGE <CSA> CONTENTS SYNC DATE
PAGE CONTENTS SYNC
1 MASTER 76 05/13/2015
1 page1 MASTER 46 page78 DEVMLB
2 10/24/2012 78 05/11/2015
2 page2 J43_MLB 47 page79 DEVMLB
3 10/24/2012 79 05/11/2015
4 10/24/2012 80 05/11/2015
5 05/11/2015 81 04/30/2015
5 page5 DEVMLB 50 page82 DEVMLB
6 05/11/2015 82 05/06/2015
7 04/14/2015 83 05/11/2015
8 05/11/2015 84 03/16/2015
9 05/11/2015 85 05/11/2015
10 04/14/2015 86 05/13/2015
11 04/14/2015 87 05/11/2015
12 05/06/2015 88 05/11/2015
13 05/11/2015 90 05/11/2015
14 05/11/2015 91 05/13/2015
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05/13/2015 C
16 05/11/2015 96 03/16/2015
17 05/11/2015 100 10/24/2012
17 page17 DEVMLB 62 page102 J43_MLB
19 05/11/2015 102 04/30/2015
20 05/04/2015 103 07/08/2014
19 page20 DEVMLB 64 page104 J92_DEVMLB
22 04/14/2015 104 07/08/2014
20 page22 DEVMLB 65 page105 J92_DEVMLB
23 04/14/2015 105 10/24/2012
21 page23 DEVMLB 66 page120 J41_MLB
25 04/14/2015 120 05/18/2015
22 page25 DEVMLB 67 page130 J92_LAYOUT_STUDY_MLB
30 04/09/2015 130 MASTER
23 page30 DEVMLB MASTER
31 05/11/2015 <CSA_PAGE69> <SYNC_DATE69>
24 page31 DEVMLB <SYNC_MASTER69>
25 page37 J72_MLB <SYNC_MASTER70>
26 page38 J92_DEVMLB <SYNC_MASTER71>
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<SYNC_MASTER77>
<SYNC_DATE77>
B
36 page61 J92_DEVMLB <SYNC_MASTER81>
41 page70 <SYNC_MASTER41> <SYNC_MASTER86>
A ALIASES RESOLVED PRODUCT SAFETY REQUIREMENTS:

PCB, UL RECOGNIZED, MIN. 130-C TEMP. RATING AND V-0 FLAME RATING PER UL 796 & UL 94.
DRAWING TITLE
Table of Contents [1]
<PART_DESCRIPTION>
DRAWING NUMBER
<SCH_NUM>
SIZE
D
A
PCB TO BE SILK-SCREENED WITH UL/CUL RECOGNITION MARK, MANUFACTURER'S UL FILE Apple Inc.
REVISION
Schematic / PCB #'s NUMBER, UL PCB MATERIAL DESIGNATION, 130-C TEMP. RATING AND V-0 FLAME RATING. R
<E4LABEL>
NOTICE OF PROPRIETARY PROPERTY: BRANCH
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
<BRANCH>
051-00532 1 SCHEM,MLB,X260 SCH CRITICAL THE POSESSOR AGREES TO THE FOLLOWING: PAGE
820-00244 1 PCBF,MLB,X260 PCB CRITICAL

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 130
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 1 OF 67
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Alternate Parts
BOM Groups TABLE_ALT_HEAD TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS PART NUMBER PART NUMBER

TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_ALT_ITEM
MLB_COMMON ALTERNATE,COMMON,MLB_MISC,MLB_DEBUG:ENG,MLB_PROGPARTS,BUILD:CBB 376S00074 376S0855 ALL Toshiba alt for Diodes dual 128S00007 128S00015 ALL NEC alt to Sanyo
MLB_MISC CAM_FREQ:24M,CAM_XTAL:NO,SSDRAM:4GBIT,S3X:B0,UPC:A1,PCH24M:SUS,EQ:4CH,PMIC:A0D,BSSB_GPIO 376S1129 376S0855 ALL NXP alt for Diodes dual 128S00009 128S00015 ALL Kemet alt to Sanyo
MLB_DEBUG:ENG DEBUGLED 376S1089 376S1128 ALL NXP alt for Diodes single 128S00029 128S00015 ALL Rohm alt to Sanyo
TABLE_ALT_ITEM TABLE_ALT_ITEM
138S0703 138S0648 ALL Murata alt to Taiyo Yuden 128S00011 128S00010 ALL Kemet alt to Sanyo
372S0186 372S0185 ALL NXP alt to Diodes 128S00026 128S00010 ALL NEC alt to Sanyo
D 376S1053 376S0604 ALL Diodes alt to Fairchild

TABLE_ALT_ITEM
128S00031 128S00010 ALL Rohm alt to Sanyo

TABLE_ALT_ITEM
D
CPU DRAM CFG Chart 107S0249 107S0251 ALL TFT alt to Cyntec
TABLE_ALT_ITEM
138S00073 138S00047 ALL Murata alt to Taiyo
TABLE_ALT_ITEM
128S00044 128S00041 ALL Rubycon alt to Sanyo 138S0772 138S00013 ALL Taiyo alt to Murata
VENDOR CFG 1 CFG 0 TABLE_ALT_ITEM TABLE_ALT_ITEM
740S00004 740S0134 ALL Kemet alt to Sanyo 132S00012 132S0401 ALL Multi alt to Taiyo
CPU DRAM SPD Straps HYNIX 0 0

740S00005 740S0190 ALL Polytronics alt to Wayon
TABLE_ALT_ITEM
152S00028 152S1751 ALL Murata alt to Taiyo Yuden

TABLE_ALT_ITEM
TABLE_BOMGROUP_HEAD
SAMSUNG 1 0 TABLE_ALT_ITEM TABLE_ALT_ITEM
BOM GROUP BOM OPTIONS 128S0296 128S0487 ALL Sanyo alt to NEC 353S00712 353S2216 ALL OnSemi alt to TI
TABLE_BOMGROUP_ITEM
MICRON 0 1 TABLE_ALT_ITEM TABLE_ALT_ITEM
DRAM:SAM_8GB RAMCFG0_L,DRAM_TYPE:SAMSUNG_8GB 128S00012 128S0487 ALL ROHM alt to NEC 353S00714 353S2208 ALL ONSemi alt to TI
TABLE_BOMGROUP_ITEM
ELPIDA 1 1 TABLE_ALT_ITEM TABLE_ALT_ITEM
DRAM:HYN_8GB RAMCFG0_L,RAMCFG1_L,DRAM_TYPE:HYNIX_8GB 128S0397 128S0325 ALL Kemet alt to Sanyo 337S00174 337S00175 S3X:B0 ALL S3X B0 alt to A0
DRAM:ELP_8GB DRAM_TYPE:ELPIDA_8GB 107S00070 107S0085 ALL TDK alt to Murata 138S00077 138S00035 ALL Taiyo alt to Murata
SIZE CFG 3 CFG 2 TABLE_ALT_ITEM TABLE_ALT_ITEM
376S00007 376S1179 ALL AOS alt to Vishay 152S00343 152S1682 ALL Murata alt to Cyntec
2GB 0 0 TABLE_ALT_ITEM TABLE_ALT_ITEM
376S1080 376S0820 ALL Diodes alt to OnSemi 155S00155 155S0441 ALL TDK alt to Murata
4GB QDP 0 1 TABLE_ALT_ITEM TABLE_ALT_ITEM
152S00311 152S2037 ALL Cyntec new alt to Cyntec 155S0741 155S0361 ALL Murata alt to TDK
4GB DDP 1 0 TABLE_ALT_ITEM TABLE_ALT_ITEM
152S00098 152S00224 ALL Vishay alt to Cyntec 155S00165 155S0382 ALL Taiyo alt to TDK
8GB 1 1 TABLE_ALT_ITEM TABLE_ALT_ITEM
128S00021 128S00020 ALL ROHM alt to NEC 155S00166 155S0391 ALL TDK alt to Murata
Programmable Parts 138S0786 138S0705 ALL Samsung alt to Murata 155S0706 155S0302 ALL Taiyo alt to Murata

SSD Configs TABLE_BOMGROUP_HEAD
197S00053 197S00050 ALL Kyocera alt to TXC
TABLE_ALT_ITEM
TABLE_ALT_ITEM
BOM GROUP BOM OPTIONS 197S00055 197S00050 ALL Murata alt to TXC
335S00084 1 IC,SPI SERIAL FLASH,8MBIT,3.0V,CSP,8P U3090 CRITICAL UPCROM:BLANK TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM
SSD:128GB NAND:64GB,CAPACITY1 311S00004 311S0370 ALL OnSemi alt to NXP
C 341S00466 1 IC,NVM (VXXX) CBB, X260 U3090 CRITICAL UPCROM:PROG

SSD:256GB NAND:128GB,CAPACITY0,CAPACITY1
TABLE_BOMGROUP_ITEM
333S00030 333S00016 ALL Hynix alt to Micron

TABLE_ALT_ITEM
C
338S1231 1 IC,SMC12-B1,40MHZ/50DMIPS MCU,7X7,168BGA U5000 CRITICAL SMC:BLANK TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM
SSD:512GB NAND:256GB,CAPACITY2 338S00175 338S1264 ALL Broadcom alt packaging

341S00431 1 IC,SMC-B1,EXTERNAL (V2.33A2) PROTO 1,X260 U5000 CRITICAL SMC:PROG TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM
SSD:256GB_SAND NAND:128GB_SAND,CAPACITY0,CAPACITY1,SANDISK_1Y 107S00020 107S0276 ALL TFT alt to Cyntec

335S1009 1 64 MBIT SPI QUAD I/O FLASH,CSP,3.3V,QUAD IO U6100 CRITICAL BOOTROM_WIN:BLANK TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM
SSD:512GB_SAND NAND:256GB_SAND,CAPACITY2,SANDISK_1Y 107S00021 107S0284 ALL TFT alt to Cyntec

335S1010 1 64 MBIT SPI QUAD I/O FLASH,CSP,3.3V,QUAD IO U6100 CRITICAL BOOTROM_MAC:BLANK TABLE_ALT_ITEM
353S00773 353S4296 ALL Semtech alt to TI

335S1029 1 64 MBIT SPI QUAD I/O FLASH,CSP,3.3V,QUAD IO U6100 CRITICAL BOOTROM_MIC:BLANK TABLE_ALT_ITEM
311S00057 311S0612 ALL Diodes alt to NXP

341S00465 1 IC,EFI ROM (VXXX) CBB,X260 U6100 CRITICAL BOOTROM:PROG TABLE_ALT_ITEM
155S00011 155S00008 ALL Murata alt to TDK
SSD Parts 138S0739 138S0706 ALL Samsung alt to Murata

TABLE_ALT_ITEM
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION TABLE_ALT_ITEM
138S0945 138S0706 ALL Kyocera alt to Murata
337S00175 1 IC,S3-X,B0 U8600 CRITICAL S3X:B0 TABLE_ALT_ITEM
138S00090 138S0943 ALL Taiyo alt to Murata
333S00017 1 IC,LPDDR3-1600,128MX8,1.8V,25NM,276 POP U8600_POP_DRAM CRITICAL SSDRAM:4GBIT TABLE_ALT_ITEM
Module Parts 335S1030 2 NAND,TOG DDR2,2CH,64GB,1YNM,3.3V,LGA60 U9100,U9120 CRITICAL NAND:64GB

107S00086 107S00056 ALL TFT alt to Cyntec
TABLE_ALT_ITEM
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 335S00050 2 NAND,TOG DDR2,2CH,128GB,1YNM,3.3V,LGA60 U9100,U9120 CRITICAL NAND:128GB TABLE_ALT_ITEM
152S00347 152S00220 ALL Chilisin alt to Cyntec
337S00207 1 IC,CPU,SKY,SR2EN,PRQ,D1,2/2,1.1,5W,.85,B1515 U0500 CRITICAL CPU:1.1GHZ 335S00051 2 NAND,TOG DDR2,2CH,256GB,1YNM,3.3V,LGA60 U9100,U9120 CRITICAL NAND:256GB TABLE_ALT_ITEM
337S00208 1 IC,CPU,SKY,SR2EM,PRQ,D1,2/2,1.2,5W,.85,B1515 U0500 CRITICAL CPU:1.2GHZ 335S00121 2 NAND,TOG DDR2,2CH,128GB,1YNM,3.3V,LGA60 U9100,U9120 CRITICAL NAND:128GB_SAND TABLE_ALT_ITEM
138S00049 138S0831 ALL Kyocera alt to Murata
337S00209 1 IC,CPU,SKY,SR2EH,PRQ,D1,2/2,1.3,5W,.85,B1515 U0500 CRITICAL CPU:1.3GHZ 335S00122 2 NAND,TOG DDR2,2CH,256GB,1YNM,3.3V,LGA60 U9100,U9120 CRITICAL NAND:256GB_SAND TABLE_ALT_ITEM
152S00362 152S1129 ALL Cyntec alt to Murata
946-3892 1 J11/J13 MLB DYMAX ADHESIVE 29993-SC 0.4G GLUE CRITICAL TABLE_ALT_ITEM
128S00039 128S00038 ALL NEC alt to Kemet
825-00162 1 LABEL,BARCODE,2D,1D,CONFIG,MLB,X260 LABEL

B B
Module Parts
353S00660 1 IC,CD3215,USB PWR SWITCH,A1,6X6MM,BGA96 U3100 CRITICAL UPC:A1
338S00168 1 IC,PMU,P650839A0D,7X7MM,BGA168 U7800 CRITICAL PMIC:A0D
Board IDs TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS

TABLE_BOMGROUP_ITEM
BUILD:PROTO1 BOARDID0_L
TABLE_BOMGROUP_ITEM
BUILD:CBB BOARDID1_L
Board ID should start all-high (first build), and each new build increment stuffing
in a binary fashion (ID0 is the LSb). IDx is high if not set low in the BOM table.
DRAM Parts
333S00052 2 IC,SDRAM,LPDDR-1866,32GBIT,253B FBGA U2300,U2500 CRITICAL DRAM_TYPE:SAMSUNG_8GB
333S00053 2 IC,SDRAM,LPDDR-1866,32GBIT,253B FBGA U2300,U2500 CRITICAL DRAM_TYPE:HYNIX_8GB
A 333S00054 2 IC,SDRAM,LPDDR-1866,32GBIT,253B FBGA U2300,U2500 CRITICAL DRAM_TYPE:ELPIDA_8GB

SYNC_MASTER=X260_ERIC SYNC_DATE=06/09/2015 A
PAGE TITLE
BOM Configuration [2]

DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
2 OF 130
SHEET
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8 7 6 5 4 3 2 1
Top level BOM Variants TABLE_BOMGROUP_HEAD
BOM NUMBER BOM NAME BOM OPTIONS

TABLE_BOMGROUP_ITEM
639-6664 PCBA,MLB,1.3GHZ,EL 8GB,TOSH 256G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,SSD:256GB,WIFI:FCC

TABLE_BOMGROUP_ITEM
639-6665 PCBA,MLB,1.3GHZ,EL 8GB,TOSH 512G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,SSD:512GB,WIFI:FCC

TABLE_BOMGROUP_ITEM
639-6666 PCBA,MLB,1.3GHZ,HY 8GB,TOSH 256G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:HYN_8GB,SSD:256GB,WIFI:FCC

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM
639-6668 PCBA,MLB,1.3GHZ,SA 8GB,TOSH 256G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:SAM_8GB,SSD:256GB,WIFI:FCC
D
TABLE_BOMGROUP_ITEM
639-6669 PCBA,MLB,1.3GHZ,SA 8GB,TOSH 512G,WIFI FCC,X260

D
ALTERNATE,CMN,CPU:1.3GHZ,DRAM:SAM_8GB,SSD:512GB,WIFI:FCC
TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM
639-6671 PCBA,MLB,1.2GHZ,EL 8GB,TOSH 256G,WIFI ETSI,X260 ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,SSD:256GB,WIFI:ETSI

TABLE_BOMGROUP_ITEM
639-6672 PCBA,MLB,1.2GHZ,SA 8GB,TOSH 512G,WIFI APAC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:SAM_8GB,SSD:512GB,WIFI:APAC

TABLE_BOMGROUP_ITEM
639-6673 PCBA,MLB,1.2GHZ,EL 8GB,SAND 256G,WIFI ETSI,X260 ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,SSD:256GB_SAND,WIFI:ETSI

TABLE_BOMGROUP_ITEM
639-6674 PCBA,MLB,1.3GHZ,EL 8GB,SAND 256G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,SSD:256GB_SAND,WIFI:FCC

TABLE_BOMGROUP_ITEM
639-6675 PCBA,MLB,1.3GHZ,SA 8GB,SAND 512G,WIFI APAC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:SAM_8GB,SSD:512GB_SAND,WIFI:APAC

TABLE_BOMGROUP_ITEM
639-6676 PCBA,MLB,1.2GHZ,EL 8GB,SAND 256G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,SSD:256GB_SAND,WIFI:FCC

TABLE_BOMGROUP_ITEM
639-6677 PCBA,MLB,1.3GHZ,SA 8GB,SAND 512G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:SAM_8GB,SSD:512GB_SAND,WIFI:FCC

TABLE_BOMGROUP_ITEM
639-6678 PCBA,MLB,1.3GHZ,HY 8GB,SAND 512G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:HYN_8GB,SSD:512GB_SAND,WIFI:FCC

TABLE_BOMGROUP_ITEM
639-6679 PCBA,MLB,1.2GHZ,HY 8GB,SAND 512G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.2GHZ,DRAM:HYN_8GB,SSD:512GB_SAND,WIFI:FCC

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM
639-6684 PCBA,MLB,1.1GHZ,SA 8GB,SAND 512G,WIFI ETSI,X260 ALTERNATE,CMN,CPU:1.1GHZ,DRAM:SAM_8GB,SSD:512GB_SAND,WIFI:ETSI

TABLE_BOMGROUP_ITEM
639-6685 PCBA,MLB,1.2GHZ,SA 8GB,SAND 256G,WIFI IND,X260 ALTERNATE,CMN,CPU:1.2GHZ,DRAM:SAM_8GB,SSD:256GB_SAND,WIFI:IND

TABLE_BOMGROUP_ITEM
C C
TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM
B B
Partial & development BOMs TABLE_BOMGROUP_HEAD
BOM NUMBER BOM NAME BOM OPTIONS

TABLE_BOMGROUP_ITEM
685-00073 CMN PTS,PCBA,MLB,X260 MLB_COMMON

TABLE_BOMGROUP_ITEM
939-01879 PCBA,MLB,NO CPU,SA 8GB,TOSH 512G,WIFI FCC,X260 ALTERNATE,CMN,DRAM:SAM_8GB,SSD:512GB,WIFI:FCC

TABLE_BOMGROUP_ITEM
939-01880 PCBA,MLB,NO CPU,SA 8GB,SAND 512G,WIFI FCC,X260 ALTERNATE,CMN,DRAM:SAM_8GB,SSD:512GB_SAND,WIFI:FCC
Common BOM
A 685-00073 1 CMN PTS,PCBA,MLB,X260 CMNPTS CRITICAL CMN

SYNC_MASTER=J43_MLB SYNC_DATE=10/24/2012 A
Programmable Parts PAGE TITLE
X260 BOM Variants

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION DRAWING NUMBER SIZE
341S00345 1 BT ROM (VXX) PROTO0,X260 U3770 CRITICAL BT:PROG Apple Inc.

<SCH_NUM> D
REVISION
341S00346 1 WIFI ROM (PXXXX) PROTO0,WW1,X260 U3780 CRITICAL WIFI:FCC

R
<E4LABEL>
BOM Groups 341S00347 1 WIFI ROM (PXXXX) PROTO0,WW2,X260 U3780 CRITICAL WIFI:ETSI
NOTICE OF PROPRIETARY PROPERTY:
BRANCH
<BRANCH>
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS 341S00348 1 WIFI ROM (PXXXX) PROTO0,WW3,X260 U3780 CRITICAL WIFI:APAC THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MLB_PROGPARTS BOOTROM:PROG,BT:PROG,SMC:PROG,UPCROM:PROG
TABLE_BOMGROUP_ITEM
341S00349 1 WIFI ROM (PXXXX) PROTO0,IND,X260 U3780 CRITICAL WIFI:IND

3 OF 130
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WIFI EMI CAN

1
SH0400 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
SM
806-7064 1 CAN,EMI,WIFI,X261 SH0400 CRITICAL
SHLD-J92-EMI-CAN-WIFI
OMIT_TABLE
D D
DRAM EMI CAN
1
SH0402 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
SM
806-04848 1 CAN,EMI,DRAM,X260 SH0402 CRITICAL
SHLD-CAN-EMI-DRAM-X261
OMIT_TABLE
SSD EMI CANs

1 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
SH0403
SM 806-00889 1 FENCE,EMI,SSD,TOP,X261 SH0403 CRITICAL
870-00878 1 TAPE,CONDUCTIVE,SSD,REEL,X261 SSD_TAPE_TOP CRITICAL
SHLD-FENCE-SSD-TOP-X261
OMIT_TABLE
C SH0404 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
C
SM
806-05622 1 FENCE,EMI,SSD,BTM,X260 SH0404 CRITICAL
SHLD-CAN-EMI-SSD-BTM-X261 870-01557 1 TAPE,CONDUCTIVE,SSD,REEL,X260 SSD_TAPE_BTM CRITICAL
OMIT_TABLE
CPU Heat Spreader Bosses USB-C BTB Connector Boss

Z0403 Z0406
3.7OD1.85ID-1.5H-SM 2.73OD1.15ID-0.814H-SM
1 1
Z0404 860-00324
3.7OD1.85ID-1.5H-SM
1
Z0405
3.7OD1.85ID-1.5H-SM
1
860-00329
B B
870-00998 1 MYLAR,SHIM,MLB,X261 MYLAR_SHIM CRITICAL
A SYNC_MASTER=J43_MLB SYNC_DATE=10/24/2012 A
PAGE TITLE
PD PARTS
www.vinafix.vn
DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
4 OF 130
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CRITICAL
OMIT_TABLE
U0500
SKL-Y-ULX
BGA
DDI Port Assignments: SKL-Y eDP Port Assignment:
DP_XA_ML_C_N<0> A46 DDI1_TXN0 SYM 1 OF 20 EDP_TXN0 H45 DP_INT_ML_C_N<0>
D
60 23 OUT OUT 53
D 60 23
60 23
OUT
DP_XA_ML_C_P<0>
DP_XA_ML_C_N<1>
C46
C48
DDI1_TXP0
DDI1_TXN1
DISPLAY EDP_TXP0
EDP_TXN1
F45
J44
DP_INT_ML_C_P<0>
DP_INT_ML_C_N<1>
OUT 53
53
OUT OUT
60 23 DP_XA_ML_C_P<1> A48 DDI1_TXP1 EDP_TXP1 G44 DP_INT_ML_C_P<1> 53
OUT OUT
USBC Sink 0 DP_XA_ML_C_N<2> B45 J46 DP_INT_ML_C_N<2>
60 23 OUT DDI1_TXN2 EDP_TXN2 OUT 53 Internal panel
60 23 DP_XA_ML_C_P<2> D45 DDI1_TXP2 DDI EDP EDP_TXP2 G46 DP_INT_ML_C_P<2> 53
OUT OUT
60 23 DP_XA_ML_C_N<3> B47 DDI1_TXN3 EDP_TXN3 H43 DP_INT_ML_C_N<3> 53
OUT OUT
60 23 DP_XA_ML_C_P<3> D47 DDI1_TXP3 EDP_TXP3 F43 DP_INT_ML_C_P<3> 53
OUT OUT
64 NC_DP_DDI2_ML_CN<0> A42 DDI2_TXN0 EDP_AUXN J42 DP_INT_AUXCH_C_N 53

OUT BI
64 NC_DP_DDI2_ML_CP<0> C42 DDI2_TXP0 EDP_AUXP G42 DP_INT_AUXCH_C_P 53
OUT BI
NC_DP_DDI2_ML_CN<1> A44 DDI2_TXN1
EDP_DISP_UTIL A40
64 OUT
C44 TP_EDP_DISP_UTIL
64 OUT
NC_DP_DDI2_ML_CP<1> DDI2_TXP1
USBC Sink 1 NC_DP_DDI2_ML_CN<2> B41 H41 DP_XA_AUXCH_C_N
64 OUT DDI2_TXN2 DDI1_AUXN BI 23 60
64 NC_DP_DDI2_ML_CP<2> D41 DDI2_TXP2 DDI1_AUXP F41 DP_XA_AUXCH_C_P 23 60

OUT BI
64 NC_DP_DDI2_ML_CN<3> B43 DDI2_TXN3 DDI2_AUXN J40 NC_DP_DDI2_AUXCH_CN 64
OUT BI
64 NC_DP_DDI2_ML_CP<3> D43 DDI2_TXP3 DDI2_AUXP G40 NC_DP_DDI2_AUXCH_CP 64
OUT BI
65 30 26 19 15 14 IN
PLT_RST_L
DISPLAY SIDEBANDS
PCH_UPC_XA_SWD_CLK L6 GPP_E18/DDPB_CTRLCLK GPP_E13/DDPB_HPD0 C11 DP_DDI1_HPD
R0514
23 5 5 19
1 OUT IN
61 47 11 8 PPVCCIO_S0 19 PCH_DDPB_CTRLDATA H6 GPP_E19/DDPB_CTRLDATA GPP_E14/DDPC_HPD1 L10 DP_DDI2_HPD 5 64
OUT IN
100K (IPD-PLTRST#) M7 TP_PCH_GPP_E15
PLACE_NEAR=U0500.A50:15.24mm 5% H4 GPP_E15/DDPD_HPD2
1/32W PCH_UPC_XA_SWD_DATA GPP_E20/DDPC_CTRLCLK F6
R0520
23 5
1 MF
BI
F4 GPP_E16/DDPE_HPD3 JTAG_ISP_TDO 5 64
01005 2 63 NC_PCH_DDPC_CTRLDATA GPP_E21/DDPC_CTRLDATA A7
IN
24.9 OUT
(IPD-PLTRST#) GPP_E17/EDP_HPD DP_INT_HPD IN 5 53
1% M5
1/20W SSD_RESET_L GPP_E22
EDP_BKLEN D4
59
MF
OUT
L4 EDP_BKLT_EN 5 52
201 2 TBT_POC_RESET GPP_E23
OUT
EDP_BKLCTL B6
64 5 OUT
(IPD-PLTRST#) EDP_BKLT_PWM OUT 53 65
MCP_EDP_RCOMP A50 EDP_RCOMP EDP_VDDEN D3 EDP_PANEL_PWR OUT 5 53
C C
'Ridge systems: GPP_E18: JTAG_TBT_X_TMS
GPP_E20: JTAG_TBT_T_TMS
B B
PP3V3_S0
A 6 14 15 16 17 19 23 26 27 31 33
34 35 39 46 50 51 53 61 67
SYNC_MASTER=DEVMLB SYNC_DATE=05/11/2015 A
R0510 10K 1 2 PCH_UPC_XA_SWD_CLK 5 23
PAGE TITLE
R0512 10K 1 2
5% 1/32W MF 01005
PCH_UPC_XA_SWD_DATA 5 23 CPU GFX
R0515 100K 1 2
5% 1/32W MF 01005
TBT_POC_RESET 5 64 DRAWING NUMBER SIZE
R0580 100K 1 2
5% 1/32W MF 01005
DP_DDI1_HPD 5 19
Apple Inc.
<SCH_NUM> D
R0581 100K 1 2
5% 1/32W MF 01005
DP_DDI2_HPD 5 64 REVISION
R0583 10K 1 2
5% 1/32W MF 01005
JTAG_ISP_TDO 5 64
R
<E4LABEL>
R0584 100K 1 2
5% 1/32W MF 01005
DP_INT_HPD 5 53 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R0590 100K 1 2
5% 1/32W MF 01005
EDP_BKLT_EN 5 52 THE INFORMATION CONTAINED HEREIN IS THE <BRANCH>
R0591 100K 1 2
5%
5%
1/32W
1/32W
MF
MF
01005
01005
EDP_PANEL_PWR 5 53
5 OF 130
SHEET
BOM_COST_GROUP=CPU & CHIPSET IV ALL RIGHTS RESERVED 5 OF 67
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
61 50 42 31 15 12 8 PP1V_S3
CRITICAL
OMIT_TABLE
D
63 61 50 12 8 PP1V_S0SW R0613 1
49.9
U0500 D
1% SKL-Y-ULX
R0610 1 R0612 1 1/20W
MF
BGA
SKL-Y
1.00K 1.00K 201 2
5% 5% SYM 4 OF 20
1/32W 1/32W H49 D53
MF MF CPU_CATERR_L CATERR* (IPU) (IPD) PROC_TCK XDP_CPUPCH_TCK
R0611
65 30 OUT IN 6 63
01005 2 01005 2 F49 C54
CPU_PECI XDP_CPUPCH_TDI
JTAG
PECI (IPU) PROC_TDI
CPU MISC
31 BI IN 6 63
CPU_PROCHOT_L 2
499 1 CPU_PROCHOT_R_L J48 G48 XDP_CPUPCH_TDO
42 31 30 BI PROCHOT* PROC_TDO OUT 6 63
1% 31 30 PM_THRMTRIP_L H47 THERMTRIP* (IPU) PROC_TMS C59 XDP_CPUPCH_TMS 6 63

OUT IN
1/20W
MF B62 SKTOCC* (IPD) PROC_TRST* F47 XDP_CPUPCH_TRST_L
201 NC IN 6 63
63 TP_XDP_BPM_L<0> H51 BPM0* (IPU) (IPD) PCH_JTAG_TCK B53 TP_XDP_PCH_TCK 63

BI IN
63 TP_XDP_BPM_L<1> J50 BPM1* (IPU) (IPU) PCH_JTAG_TDI C50 XDP_CPUPCH_TDI 6 63
BI IN
63 TP_XDP_BPM_L<2> F51 BPM2* (IPU) PCH_JTAG_TDO B51 XDP_CPUPCH_TDO 6 63
BI OUT
63 TP_XDP_BPM_L<3> G50 BPM3* (IPU) (IPU) PCH_JTAG_TMS A52 XDP_CPUPCH_TMS 6 63
BI IN
PCH_TRST* C52 XDP_CPUPCH_TRST_L
TP_XDP_PCH_OBSFN_C1 E11 GPP_E3/CPU_GP0
IN 6 63
63 OUT
JTAGX B49 XDP_CPUPCH_TCK
63 TP_XDP_PCH_OBSDATA_A3 M9 GPP_E7/CPU_GP1
BI 6 63
BI
64 6 BT_PWRRST_L BD8 GPP_B3/CPU_GP2
OUT
64 6 BT_TIMESTAMP BC11 GPP_B4/CPU_GP3
OUT
CPU_OPI_RCOMP BN17 PROC_POPIRCOMP

PCH_OPI_COMP BP16 PCH_OPIRCOMP
R0620 1 R0621 1
49.9 49.9
1% 1%
1/20W 1/20W
MF MF
201 2 201 2
C PLACE_NEAR=U0500.BN17:2.54mm
C
PLACE_NEAR=U0500.BP16:2.54mm
CRITICAL
OMIT_TABLE
NC_CPU_CFG0 G52 BL64 TP_MCP_RSVD_BL64
63 BI
F53
CFG0 U0500 RSVD_TP
BG47
63 BI
NC_CPU_CFG1 CFG1 SKL-Y-ULX RSVD_TP TP_MCP_RSVD_BG47
NC_CPU_CFG2 J52 CFG2 BGA
63 BI
RSVD_TP BA17 TP_MCP_RSVD_BA17
TP_CPU_CFG3 H53 CFG3 SKL-Y
63 BI
RSVD_TP AY18 TP_MCP_RSVD_AY18
64 CPU_CFG<4> H55 CFG4 SYM 12 OF 20
BI
63 NC_CPU_CFG5 D55 CFG5 RESERVED SIGNALS RSVD BF18 TP_MCP_RSVD_BF18
BI
C56 BE19
R0634 1 63 BI
NC_CPU_CFG6
F55
CFG6 RSVD TP_MCP_RSVD_BE19
1.00K 63 NC_CPU_CFG7 CFG7 BA23
5%
BI
D61 TP5 TP_MCP_RSVD_BA23
1/32W 63 NC_CPU_CFG8 CFG8 AY22
MF
BI
G58 TP6 TP_MCP_RSVD_AY22
01005 2 63 BI
NC_CPU_CFG9 CFG9
NC_CPU_CFG10 D57 CFG10 RSVD R12
63 BI NC
NC_CPU_CFG11 F61 CFG11 RSVD P13
63 BI NC
NC_CPU_CFG12 J60 CFG12 RSVD M15
63 BI NC
B 63 BI
NC_CPU_CFG13
NC_CPU_CFG14
J58
H61
CFG13
CFG14
RSVD L16
NC B
63 BI
RSVD L18
NC_CPU_CFG15 H59 CFG15 NC
63 BI
RSVD M17
NC
NC_CPU_CFG16 J54 CFG16
63 BI
RSVD AH7
63 NC_CPU_CFG17 G54 CFG17 NC
BI
RSVD K12
NC_CPU_CFG18 G56 CFG18 NC
63 BI
RSVD H12
63 NC_CPU_CFG19 J56 CFG19 NC
BI
RSVD BN3
CPU_CFG_RCOMP A54 CFG_RCOMP NC
RSVD BP3
NC
TP_ITP_PMODE A60 ITP_PMODE (IPU)
63 OUT
RSVD L22
NC
B4 RSVD RSVD M23
R0680 1 NC
NC
B3 RSVD BN1
NC
49.9 TP4 TP_MCP_RSVD_BN1
1% F3
1/20W NC RSVD AY20
MF F1 RSVD NC
201 2 NC RSVD BA21
RSVD NC
L36 RSVD
NC RSVD BB14
L38 RSVD NC
NC
RSVD M25 TP_MCP_RSVD_M25
BA19 RSVD
NC RSVD L24 TP_MCP_RSVD_L24
BB18 RSVD
NC
RSVD L28 TP_MCP_RSVD_L28
BC19 RSVD
NC RSVD M27 TP_MCP_RSVD_M27
BD18 RSVD
NC
TP1 BJ15 TP_MCP_RSVD_BJ15
TP_MCP_RSVD_D49 D49 RSVD
TP2 BJ17 TP_MCP_RSVD_BJ17
M21 RSVD
NC
A NC
L20
M19
RSVD
NC RSVD PAGE TITLE
NC
L26 RSVD CPU Misc/JTAG/CFG/RSVD
DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
PP3V3_S0 5 14 15 16 17 19 23 26 27 31 33
34 35 39 46 50 51 53 61 67
R
<E4LABEL>
R0618 100K 1 2 BT_PWRRST_L 6 64 THE INFORMATION CONTAINED HEREIN IS THE <BRANCH>
R0619 100K 1 2
5%
5%
1/32W
1/32W
MF
MF
01005
01005
BT_TIMESTAMP 6 64
6 OF 130
SHEET
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
CRITICAL CRITICAL
OMIT_TABLE OMIT_TABLE
62 21 MEM_A_DQ<0> AG61 DDR0_DQ0 DDR0_CKN0 BC62 MEM_A_CLK_N<0> 21 65 62 22 MEM_B_DQ<0> BC41 DDR0_DQ32/DDR1_DQ0 DDR1_CKN0 BK36 MEM_B_CLK_N<0> 22
BI OUT BI OUT
62 21 BI MEM_A_DQ<1> AH60 DDR0_DQ1 U0500 DDR0_CKP0 BC60 MEM_A_CLK_P<0> OUT 21 65 62 22 BI MEM_B_DQ<1> BC39 DDR0_DQ33/DDR1_DQ1 U0500 DDR1_CKP0 BM36 MEM_B_CLK_P<0> OUT 22
MEM_A_DQ<2> AK62 DDR0_DQ2 SKL-Y-ULX DDR0_CKN1 BA60 MEM_A_CLK_N<1> MEM_B_DQ<2> BG41 DDR0_DQ34/DDR1_DQ2 DDR1_CKN1 BD32 MEM_B_CLK_N<1>
62 21 BI OUT 21 62 22 BI SKL-Y-ULX OUT 22
D
62 21 BI MEM_A_DQ<3>
MEM_A_DQ<4>
AK60
AH62
DDR0_DQ3
DDR0_DQ4
BGA
SKL-Y
DDR0_CKP1 BA62 MEM_A_CLK_P<1> OUT 21 62 22 BI MEM_B_DQ<3>
MEM_B_DQ<4>
BE39
BF42
DDR0_DQ35/DDR1_DQ3
DDR0_DQ36/DDR1_DQ4
BGA
SKL-Y
DDR1_CKP1 BF32 MEM_B_CLK_P<1> OUT 22
D
62 21 BI
SYM 2 OF 20 DDR0_CKE0 BB57 MEM_A_CKE<0> 62 22 BI
SYM 3 OF 20 DDR1_CKE0 BN33 MEM_B_CKE<0>
MEM_A_DQ<5> AG63 DDR0_DQ5
OUT 21
MEM_B_DQ<5> BD42 DDR0_DQ37/DDR1_DQ5
OUT 22
62 21 BI
DDR CH - A DDR0_CKE1 BC58 MEM_A_CKE<1> 62 22 BI
DDR CH - B DDR1_CKE1 BK32 MEM_B_CKE<1>
MEM_A_DQ<6> AL61 DDR0_DQ6
OUT 21
MEM_B_DQ<6> BG39 DDR0_DQ38/DDR1_DQ6
OUT 22 65
62 21 BI
DDR0_CKE2 BE57 MEM_A_CKE<2> 62 22 BI
DDR1_CKE2 BG33 MEM_B_CKE<2>
MEM_A_DQ<7> AL63 DDR0_DQ7
OUT 21
MEM_B_DQ<7> BE41 DDR0_DQ39/DDR1_DQ7
OUT 22
62 21 BI
DDR0_CKE3 AW61 MEM_A_CKE<3> 62 22 BI
DDR1_CKE3 BH30 MEM_B_CKE<3>
62 21 MEM_A_DQ<8> AM60 DDR0_DQ8
OUT 21
62 22 MEM_B_DQ<8> BC43 DDR0_DQ40/DDR1_DQ8
OUT 22
BI BI
62 21 MEM_A_DQ<9> AM62 DDR0_DQ9 DDR0_CS0* AW63 MEM_A_CS_L<0> 21 65 62 22 MEM_B_DQ<9> BD46 DDR0_DQ41/DDR1_DQ9 DDR1_CS0* BM30 MEM_B_CS_L<0> 22
BI OUT BI OUT
62 21 MEM_A_DQ<10> AT60 DDR0_DQ10 DDR0_CS1* BJ57 MEM_A_CS_L<1> 21 62 22 MEM_B_DQ<10> BG43 DDR0_DQ42/DDR1_DQ10 DDR1_CS1* BJ33 MEM_B_CS_L<1> 22 65
BI OUT BI OUT
62 21 MEM_A_DQ<11> AR61 DDR0_DQ11 DDR0_ODT0 BN61 MEM_A_ODT<0> 21 62 22 MEM_B_DQ<11> BG45 DDR0_DQ43/DDR1_DQ11 DDR1_ODT0 BC35 MEM_B_ODT<0> 22
BI OUT BI OUT
MEM_A_DQ<12> AN61 DDR0_DQ12 MEM_B_DQ<12> BC45 DDR0_DQ44/DDR1_DQ12
62 21 BI
DDR0_CAA0 AW59 MEM_A_CAA<0> 65 62 22 BI
DDR1_CAA0 BK30 MEM_B_CAA<0>
MEM_A_DQ<13> AN63 DDR0_DQ13
OUT 21 65
MEM_B_DQ<13> BE43 DDR0_DQ45/DDR1_DQ13
OUT 22
62 21 BI
DDR0_CAA1 AW55 MEM_A_CAA<1> 62 22 BI
DDR1_CAA1 BN31 MEM_B_CAA<1>
MEM_A_DQ<14> AR63 DDR0_DQ14
OUT 21
MEM_B_DQ<14> BE45 DDR0_DQ46/DDR1_DQ14 OUT 22
62 21 BI
DDR0_CAA2 BF62 MEM_A_CAA<2> 62 22 BI
DDR1_CAA2 BM32 MEM_B_CAA<2>
MEM_A_DQ<15> AT62 DDR0_DQ15
OUT 21
MEM_B_DQ<15> BF46 DDR0_DQ47/DDR1_DQ15
OUT 22 65
62 21 BI
DDR0_CAA3 AV56 MEM_A_CAA<3> 62 22 BI
DDR1_CAA3 BL37 MEM_B_CAA<3>
MEM_A_DQ<16> AT56 DDR1_DQ0/DDR0_DQ16
OUT 21
MEM_B_DQ<16> BM28 DDR1_DQ32/DDR1_DQ16 OUT 22 65
62 21 BI
DDR0_CAA4 AW57 MEM_A_CAA<4> 62 22 BI
DDR1_CAA4 BG31 MEM_B_CAA<4>
MEM_A_DQ<17> AR55 DDR1_DQ1/DDR0_DQ17
OUT 21
MEM_B_DQ<17> BN27 DDR1_DQ33/DDR1_DQ17
OUT 22
62 21 BI
DDR0_CAA5 AV58 MEM_A_CAA<5> 62 22 BI
MEM_A_DQ<18> AN57 DDR1_DQ2/DDR0_DQ18
OUT 21
MEM_B_DQ<18> BK28 DDR1_DQ34/DDR1_DQ18
OUT 22
62 21 BI
DDR0_CAA6 BA56 MEM_A_CAA<6> 62 22 BI
DDR1_CAA6 BJ37 MEM_B_CAA<6>
MEM_A_DQ<19> AN55 DDR1_DQ3/DDR0_DQ19
OUT 21
MEM_B_DQ<19> BL25 DDR1_DQ35/DDR1_DQ19
OUT 22
62 21 BI
DDR0_CAA7 BD59 MEM_A_CAA<7> 62 22 BI
DDR1_CAA7 BJ35 MEM_B_CAA<7>
MEM_A_DQ<20> AR57 DDR1_DQ4/DDR0_DQ20
OUT 21
MEM_B_DQ<20> BN25 DDR1_DQ36/DDR1_DQ20
OUT 22
62 21 BI
DDR0_CAA8 BD61 MEM_A_CAA<8> 62 22 BI
DDR1_CAA8 BM34 MEM_B_CAA<8>
MEM_A_DQ<21> AT58 DDR1_DQ5/DDR0_DQ21
OUT 21
MEM_B_DQ<21> BL27 DDR1_DQ37/DDR1_DQ21
OUT 22
62 21 BI
DDR0_CAA9 BG61 MEM_A_CAA<9> 62 22 BI
62 21 MEM_A_DQ<22> AM58 DDR1_DQ6/DDR0_DQ22
OUT 21
62 22 MEM_B_DQ<22> BJ25 DDR1_DQ38/DDR1_DQ22
OUT 22
BI BI
62 21 MEM_A_DQ<23> AM56 DDR1_DQ7/DDR0_DQ23 DDR0_CAB0 BK59 MEM_A_CAB<0> 21 62 22 MEM_B_DQ<23> BJ27 DDR1_DQ39/DDR1_DQ23 DDR1_CAB0 BG37 MEM_B_CAB<0> 22
BI OUT BI OUT
62 21 MEM_A_DQ<24> AL55 DDR1_DQ8/DDR0_DQ24 DDR0_CAB1 BL62 MEM_A_CAB<1> 21 62 22 MEM_B_DQ<24> BM24 DDR1_DQ40/DDR1_DQ24 DDR1_CAB1 BE37 MEM_B_CAB<1> 22 65
BI OUT BI OUT
62 21 MEM_A_DQ<25> AL57 DDR1_DQ9/DDR0_DQ25 DDR0_CAB2 BJ61 MEM_A_CAB<2> 21 62 22 MEM_B_DQ<25> BK24 DDR1_DQ41/DDR1_DQ25 DDR1_CAB2 BC37 MEM_B_CAB<2> 22
BI OUT BI OUT
62 21 MEM_A_DQ<26> AH58 DDR1_DQ10/DDR0_DQ26 DDR0_CAB3 AV60 MEM_A_CAB<3> 21 62 22 MEM_B_DQ<26> BN21 DDR1_DQ42/DDR1_DQ26 DDR1_CAB3 BF34 MEM_B_CAB<3> 22
BI OUT BI OUT
62 21 MEM_A_DQ<27> AH56 DDR1_DQ11/DDR0_DQ27 DDR0_CAB4 BN62 MEM_A_CAB<4> 21 62 22 MEM_B_DQ<27> BJ23 DDR1_DQ43/DDR1_DQ27 DDR1_CAB4 BC33 MEM_B_CAB<4> 22
BI OUT BI OUT
62 21 MEM_A_DQ<28> AK58 DDR1_DQ12/DDR0_DQ28 DDR0_CAB5 BB61 MEM_A_CAB<5> 21 62 22 MEM_B_DQ<28> BL23 DDR1_DQ44/DDR1_DQ28 DDR1_CAB5 BF30 MEM_B_CAB<5> 22
BI OUT BI OUT
62 21 MEM_A_DQ<29> AK56 DDR1_DQ13/DDR0_DQ29 DDR0_CAB6 BL61 MEM_A_CAB<6> 21 62 22 MEM_B_DQ<29> BN23 DDR1_DQ45/DDR1_DQ29 DDR1_CAB6 BD36 MEM_B_CAB<6> 22
BI OUT BI OUT
C 62 21 BI MEM_A_DQ<30> AG55
AG57
DDR1_DQ14/DDR0_DQ30 DDR0_CAB7 BM59
BN58
MEM_A_CAB<7> OUT 21 62 22 BI MEM_B_DQ<30> BJ21
BL21
DDR1_DQ46/DDR1_DQ30 DDR1_CAB7 BG35
BC31
MEM_B_CAB<7> OUT 22 C
62 21 BI MEM_A_DQ<31> DDR1_DQ15/DDR0_DQ31 DDR0_CAB8 MEM_A_CAB<8> OUT 21 62 22 BI MEM_B_DQ<31> DDR1_DQ47/DDR1_DQ31 DDR1_CAB8 MEM_B_CAB<8> OUT 22
62 21 MEM_A_DQ<32> BE55 DDR0_DQ16/DDR0_DQ32 DDR0_CAB9 AV62 MEM_A_CAB<9> 21 62 22 MEM_B_DQ<32> BN45 DDR0_DQ48/DDR1_DQ32 DDR1_CAB9 BF36 MEM_B_CAB<9> 22
BI OUT BI OUT
MEM_A_DQ<33> BC55 DDR0_DQ17/DDR0_DQ33 MEM_B_DQ<33> BM46 DDR0_DQ49/DDR1_DQ33
DDR0_MA3 BB63 DDR1_MA3 BJ31
62 21 BI 62 22 BI
MEM_A_DQ<34> BG53 DDR0_DQ18/DDR0_DQ34 NC MEM_B_DQ<34> BL43 DDR0_DQ50/DDR1_DQ34 NC
DDR0_MA4 BL57 DDR1_MA4 BK34
62 21 BI 62 22 BI
62 21 MEM_A_DQ<35> BE53 DDR0_DQ19/DDR0_DQ35 NC 62 22 MEM_B_DQ<35> BK46 DDR0_DQ51/DDR1_DQ35 NC
BI BI
62 21 MEM_A_DQ<36> BC53 DDR0_DQ20/DDR0_DQ36 DDR0_DQSN0 AJ61 MEM_A_DQS_N<0> 21 62 62 22 MEM_B_DQ<36> BN43 DDR0_DQ52/DDR1_DQ36 DDR0_DQSN4/DDR1_DQSN0 BD40 MEM_B_DQS_N<0> 22 62
BI BI BI BI
62 21 MEM_A_DQ<37> BG55 DDR0_DQ21/DDR0_DQ37 DDR0_DQSP0 AJ63 MEM_A_DQS_P<0> 21 62 62 22 MEM_B_DQ<37> BL45 DDR0_DQ53/DDR1_DQ37 DDR0_DQSP4/DDR1_DQSP0 BF40 MEM_B_DQS_P<0> 22 62
BI BI BI BI
62 21 MEM_A_DQ<38> BD52 DDR0_DQ22/DDR0_DQ38 DDR0_DQSN1 AP62 MEM_A_DQS_N<1> 21 62 65 62 22 MEM_B_DQ<38> BJ45 DDR0_DQ54/DDR1_DQ38 DDR0_DQSN5/DDR1_DQSN1 BD44 MEM_B_DQS_N<1> 22 62
BI BI BI BI
62 21 MEM_A_DQ<39> BF52 DDR0_DQ23/DDR0_DQ39 DDR0_DQSP1 AP60 MEM_A_DQS_P<1> 21 62 65 62 22 MEM_B_DQ<39> BJ43 DDR0_DQ55/DDR1_DQ39 DDR0_DQSP5/DDR1_DQSP1 BF44 MEM_B_DQS_P<1> 22 62
BI BI BI BI
62 21 MEM_A_DQ<40> BC51 DDR0_DQ24/DDR0_DQ40 DDR1_DQSN0/DDR0_DQSN2 AP56 MEM_A_DQS_N<2> 21 62 62 22 MEM_B_DQ<40> BM42 DDR0_DQ56/DDR1_DQ40 DDR1_DQSN4/DDR1_DQSN2 BK26 MEM_B_DQS_N<2> 22 62
BI BI BI BI
62 21 MEM_A_DQ<41> BE51 DDR0_DQ25/DDR0_DQ41 DDR1_DQSP0/DDR0_DQSP2 AP58 MEM_A_DQS_P<2> 21 62 62 22 MEM_B_DQ<41> BN41 DDR0_DQ57/DDR1_DQ41 DDR1_DQSP4/DDR1_DQSP2 BM26 MEM_B_DQS_P<2> 22 62
BI BI BI BI
62 21 MEM_A_DQ<42> BC49 DDR0_DQ26/DDR0_DQ42 DDR1_DQSN1/DDR0_DQSN3 AJ57 MEM_A_DQS_N<3> 21 62 62 22 MEM_B_DQ<42> BJ41 DDR0_DQ58/DDR1_DQ42 DDR1_DQSN5/DDR1_DQSN3 BM22 MEM_B_DQS_N<3> 22 62
BI BI BI BI
62 21 MEM_A_DQ<43> BE49 DDR0_DQ27/DDR0_DQ43 DDR1_DQSP1/DDR0_DQSP3 AJ55 MEM_A_DQS_P<3> 21 62 62 22 MEM_B_DQ<43> BN39 DDR0_DQ59/DDR1_DQ43 DDR1_DQSP5/DDR1_DQSP3 BK22 MEM_B_DQS_P<3> 22 62
BI BI BI BI
62 21 MEM_A_DQ<44> BG51 DDR0_DQ28/DDR0_DQ44 DDR0_DQSN2/DDR0_DQSN4 BD54 MEM_A_DQS_N<4> 21 62 62 22 MEM_B_DQ<44> BK42 DDR0_DQ60/DDR1_DQ44 DDR0_DQSN6/DDR1_DQSN4 BK44 MEM_B_DQS_N<4> 22 62
BI BI BI BI
62 21 MEM_A_DQ<45> BG49 DDR0_DQ29/DDR0_DQ45 DDR0_DQSP2/DDR0_DQSP4 BF54 MEM_A_DQS_P<4> 21 62 62 22 MEM_B_DQ<45> BL41 DDR0_DQ61/DDR1_DQ45 DDR0_DQSP6/DDR1_DQSP4 BM44 MEM_B_DQS_P<4> 22 62
BI BI BI BI
62 21 MEM_A_DQ<46> BF48 DDR0_DQ30/DDR0_DQ46 DDR0_DQSN3/DDR0_DQSN5 BF50 MEM_A_DQS_N<5> 21 62 62 22 MEM_B_DQ<46> BL39 DDR0_DQ62/DDR1_DQ46 DDR0_DQSN7/DDR1_DQSN5 BM40 MEM_B_DQS_N<5> 22 62
BI BI BI BI
62 21 MEM_A_DQ<47> BD48 DDR0_DQ31/DDR0_DQ47 DDR0_DQSP3/DDR0_DQSP5 BD50 MEM_A_DQS_P<5> 21 62 62 22 MEM_B_DQ<47> BJ39 DDR0_DQ63/DDR1_DQ47 DDR0_DQSP7/DDR1_DQSP5 BK40 MEM_B_DQS_P<5> 22 62
BI BI BI BI
62 21 MEM_A_DQ<48> BJ55 DDR1_DQ16/DDR0_DQ48 DDR1_DQSN2/DDR0_DQSN6 BM54 MEM_A_DQS_N<6> 21 62 62 22 MEM_B_DQ<48> BF28 DDR1_DQ48 DDR1_DQSN6 BD26 MEM_B_DQS_N<6> 22 62
BI BI BI BI
62 21 MEM_A_DQ<49> BL55 DDR1_DQ17/DDR0_DQ49 DDR1_DQSP2/DDR0_DQSP6 BK54 MEM_A_DQS_P<6> 21 62 62 22 MEM_B_DQ<49> BD28 DDR1_DQ49 DDR1_DQSP6 BF26 MEM_B_DQS_P<6> 22 62
BI BI BI BI
62 21 MEM_A_DQ<50> BJ53 DDR1_DQ18/DDR0_DQ50 DDR1_DQSN3/DDR0_DQSN7 BK50 MEM_A_DQS_N<7> 21 62 62 22 MEM_B_DQ<50> BG25 DDR1_DQ50 DDR1_DQSN7 BF22 MEM_B_DQS_N<7> 22 62
BI BI BI BI
62 21 MEM_A_DQ<51> BL53 DDR1_DQ19/DDR0_DQ51 DDR1_DQSP3/DDR0_DQSP7 BM50 MEM_A_DQS_P<7> 21 62 62 22 MEM_B_DQ<51> BC27 DDR1_DQ51 DDR1_DQSP7 BD22 MEM_B_DQS_P<7> 22 62
BI BI BI BI
MEM_A_DQ<52> BN55 DDR1_DQ20/DDR0_DQ52 MEM_B_DQ<52> BG27 DDR1_DQ52
DDR0_ALERT* BG57 DDR1_ALERT* BD34
62 21 BI 62 22 BI
MEM_A_DQ<53> BN53 DDR1_DQ21/DDR0_DQ53 MEM_B_DQ<53> BE27 DDR1_DQ53
DDR0_PAR BM56 DDR1_PAR BD30
62 21 BI 62 22 BI
MEM_A_DQ<54> BM52 DDR1_DQ22/DDR0_DQ54 NC MEM_B_DQ<54> BE25 DDR1_DQ54 NC
DRAM_RESET* BP20
62 21 BI 62 22 BI
62 21 MEM_A_DQ<55> BK52 DDR1_DQ23/DDR0_DQ55 DDR_VREF_CA AR53 CPU_DIMM_VREFCA 20 62 22 MEM_B_DQ<55> BC25 DDR1_DQ55 NC
BI OUT BI
B 62 21
62 21
BI
BI
MEM_A_DQ<56>
MEM_A_DQ<57>
BL51
BJ51
DDR1_DQ24/DDR0_DQ56
DDR1_DQ25/DDR0_DQ57
DDR0_VREF_DQ AN53
DDR1_VREF_DQ AW53
CPU_DIMMA_VREFDQ
CPU_DIMMB_VREFDQ
OUT
OUT
20
20
62 22
62 22
BI
BI
MEM_B_DQ<56>
MEM_B_DQ<57>
BF24
BD24
DDR1_DQ56
DDR1_DQ57
DDR_RCOMP0 BF64
DDR_RCOMP1 BJ64
CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
B
MEM_A_DQ<58> BL49 DDR1_DQ26/DDR0_DQ58 MEM_B_DQ<58> BG21 DDR1_DQ58 DDR_RCOMP2 BC64 CPU_SM_RCOMP<2>
DDR_VTT_CNTL BN47
62 21 BI 62 22 BI
BJ49 TP_CPU_MEMVTT_PWR_EN 63 BC23
62 21 BI
MEM_A_DQ<59> DDR1_DQ27/DDR0_DQ59
OUT
62 22 BI MEM_B_DQ<59> DDR1_DQ59
BN49 BE23
62 21 BI
MEM_A_DQ<60>
BN51
DDR1_DQ28/DDR0_DQ60 62 22 BI MEM_B_DQ<60>
BG23
DDR1_DQ60 R0752 1 R0751 1 R0750 1
62 21 BI
MEM_A_DQ<61> DDR1_DQ29/DDR0_DQ61 62 22 BI MEM_B_DQ<61> DDR1_DQ61 162 80.6 200
BK48 BC21 1% 1% 1%
62 21 BI
MEM_A_DQ<62> DDR1_DQ30/DDR0_DQ62 62 22 BI MEM_B_DQ<62> DDR1_DQ62 1/20W 1/20W 1/20W
BM48 BE21 MF MF MF
62 21 BI
MEM_A_DQ<63> DDR1_DQ31/DDR0_DQ63 62 22 BI MEM_B_DQ<63> DDR1_DQ63 201 2 201 2 201 2
PLACE_NEAR=U0500.BC64:12.7mm
PLACE_NEAR=U0500.BJ64:12.7mm
PLACE_NEAR=U0500.BF64:12.7mm
A SYNC_MASTER=DEVMLB SYNC_DATE=04/14/2015 A
PAGE TITLE
CPU LPDDR3 Interface

DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
7 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SKL-ULX current estimates from Skylake Processor EDS vol 1, doc #544924, v0.94 NOTE: Aliases not used on CPU supply outputs
VCCIO breakdown per 4/20/15 email from Srini to avoid any extraneous connections.
CRITICAL
OMIT_TABLE
U0500
SKL-Y-ULX
BGA
SKL-Y
61 43 11 PPVCCSA_S0 SYM 16 OF 20 PPVCCG0_S0_CPU 11
AA29 AA35 MIN_LINE_WIDTH=0.2000
3.78A Max VCCSA VCCG0 MIN_NECK_WIDTH=0.2000
AF30 R38 VOLTAGE=1.5V
VCCSA VCCG0
D
AN29 VCCSA VCCG0 Y35
D
CPU POWER 4 OF 4
L30 VCCSA VCCG0 AA38
T30 VCCSA VCCG0 T35
AC29 VCCSA VCCG0 Y38
AH29 VCCSA VCCG0 AC35
AN30 VCCSA VCCG0 T38
M31 VCCSA VCCG0 AC38
V29 VCCSA VCCG0 V35
AC30 VCCSA VCCG0 R35
CRITICAL AK29 V38 CRITICAL
VCCSA VCCG0
OMIT_TABLE AR29 OMIT_TABLE
VCCSA AF35
N30 VCCG1 PPVCCG1_S0_CPU 11
U0500 PLACE_NEAR=U0500.N30:50.8mm Y29
VCCSA
VCCG1 AK38 MIN_LINE_WIDTH=0.2000
MIN_NECK_WIDTH=0.2000 U0500
SKL-Y-ULX VCCSA AR35 VOLTAGE=1.5V SKL-Y-ULX
BGA R0860 1 AE29 VCCSA
VCCG1
AF38 BGA
SKL-Y 100 AK30 VCCG1 61 50 47 22 21 20 12 PP1V2_S3 PPVCCIO_S0 5 8 11 47 61
34 12 8 PPVCORE_S0_GT SYM 14 OF 20
PPVCORE_S0_GT 8 12 34 44 61 5% VCCSA AL35 AH64
SKL-Y
AC23
61 44
AA53 AC53 1/32W R29 VCCG1 2A Max VDDQ SYM 15 OF 20 VCCIO 1.185A Max
24A Max VCCGT VCCGT MF VCCSA AR38 BA27 AF24
AB62 AC63 01005 2 Y30 VCCG1 VDDQ VCCIO
VCCGT VCCGT VCCSA AH35 BA37 AN26
VCCG1 VDDQ VCCIO
CPU POWER 3 OF 4
AC47 VCCGT VCCGT AD62 VCCSA & VCCSA_DDR must AF29 VCCSA
VCCG1 AL38 BA49 VDDQ VCCIO AC24
AC55 VCCGT VCCGT AE59 be isolated from VR AL29 VCCSA
CPU POWER 2 OF 4
VCCG1 AH38 BP32 VDDQ VCCIO AF26

AD54 VCCGT VCCGT AF46 output to BGA pads T29 VCCSA
VCCG1 AN35 BP50 VDDQ VCCIO AR26
AD64 VCCGT VCCGT AG53
PPVCCSA_DDR_S0 AT29 VCCSA_DDR VCCG1 AK35 AK64 VDDQ VCCIO AE23
AE61 VCCGT VCCGT AK47 61 43 11
320mA Max AT30 VCCSA_DDR VCCG1 AN38 BA29 VDDQ VCCIO AH26
AF47 VCCGT VCCGT AN44
BA41 VDDQ VCCIO AT26
AJ53 VCCGT VCCGT AN51 CPU_VCCSASENSE_P M29 VCCSA_SENSE
42 OUT BA51 VDDQ VCCIO AE24
AK49 VCCGT VCCGT AT49 CPU_VCCSASENSE_N N28 VSSSA_SENSE VCCIO & VCCIO_DDR must
42 OUT BP34 VDDQ VCCIO AK26
AN46 VCCGT VCCGT N48 be isolated from local
PLACE_NEAR=U0500.R30:50.8mm BP56 VDDQ VCCIO AE26
AT43 VCCGT VCCGT T44 plane to BGA pads
AT64 AL26
C AT50 VCCGT VCCGT T51 R0861 1 BA31
VDDQ VCCIO
C
N50 U59 100 VDDQ AV26 PPVCCIO_S0
VCCGT VCCGT 5% BA43 VCCIO_DDR 5 8 11 47 61
T46 V58 1/32W VDDQ AV36
VCCGT VCCGT MF
TP_MCP_DC_BN64 BN64 VCCIO_DDR 1.75A Max
T54 W55 01005 2 VDDQ AV46
VCCGT VCCGT BP40 VCCIO_DDR
U61 Y43 VDDQ AW31
VCCGT VCCGT BP58 VCCIO_DDR
V60 Y50 VDDQ AW41
VCCGT VCCGT AV64 VCCIO_DDR
W57 Y60 VDDQ AW51
VCCGT VCCGT BA33 VCCIO_DDR
Y44 AB56 VDDQ AV28
VCCGT VCCGT BA45 VCCIO_DDR
Y51 AC43 VDDQ AV38
VCCGT VCCGT CRITICAL BP24 VCCIO_DDR
Y62 AC50 24A Max VDDQ AV48
VCCGT VCCGT
PPVCORE_S0_CPU OMIT_TABLE PPVCORE_S0_CPU BP42 VCCIO_DDR
AB54 AC59 61 43 34 11 8 8 11 34 43 61 VDDQ AW33
VCCGT VCCGT A64 M58 BP64 VCCIO_DDR
TP_MCP_DC_A64 VCC VCC TP_MCP_DC_BP64 VDDQ
AB64 VCCGT VCCGT AD58
AE32 VCC
U0500 VCC N34 BA25 VDDQ
VCCIO_DDR AW43
AC49 VCCGT VCCGT AE55 SKL-Y-ULX VCCIO_DDR AV30
AE40 VCC VCC N54 BA35 VDDQ
AC57 AF43 BGA AV40
AD56
VCCGT
VCCGT
VCCGT
VCCGT AF50
AH41 VCC SKL-Y VCC N63 VDDQC must implement XW0850
SM
BA47 VDDQ
VCCIO_DDR
VCCIO_DDR AV50
AN32 VCC SYM 13 OF 20 VCC P64 1nH trace filter BP26 VDDQ
AE53 VCCGT VCCGT AK44 1 2 VCCIO_DDR AW35
AT33 VCC CPU POWER 1 OF 4 VCC R61 BP48 VDDQ
AE63 VCCGT VCCGT AK51 BYPASS=U0500.BA39::0.59mm VCCIO_DDR AW45
AT41 VCC VCC V41 PP1V2_S0_CPU_VDDQC BA39 VDDQC
AF49 VCCGT VCCGT AN49 MIN_LINE_WIDTH=0.2000 VCCIO_DDR AV32
J64 VCC VCC AC41 MIN_NECK_WIDTH=0.2000
AK43 VCCGT VCCGT AT46 V26 VCCST VCCIO_DDR AV42
AK50 VCCGT VCCGT N44
L48 VCC VCC AE38 C0850 1 VOLTAGE=1.2V
PP1V_S3 Y26 VCCST VCCIO_DDR AW27
AN47 R53
M33 VCC VCC AH32 0.1UF 15 12 8 6
61 50 42 31
AW37
VCCGT VCCGT 10% VCCIO_DDR
M43 VCC VCC AL41 10V PP1V_S0SW R26 VCCSTG
AT44 VCCGT VCCGT T49 X5R-CERM 2 61 50 12 8 6
63 VCCIO_DDR AW47
M53 VCC VCC AT32 0201 T26 VCCSTG PLACE_NEAR=U0500.AT26:50.8mm
AT51 VCCGT VCCGT U55 VCCIO_DDR AV34
M64 AT40
R51 VCCGT VCCGT V54
N40
VCC VCC
H63 61 50 12 PP1V2_S0SW AE27 VCCPLL_OC VCCIO_DDR AV44
1
R0840
T47 V64 VCC VCC AF27 AW29 100
VCCGT VCCGT N59 L46 VCCPLL_OC VCCIO_DDR 5%
U53 W61 VCC VCC AW39 1/32W
VCCGT VCCGT P60 L63 R27 VCCIO_DDR MF
VCC VCC PP1V_S3 VCCPLL 2 01005
B
U63 Y47 AW49
B
61 50 42 31 15 12 8 6
VCCGT VCCGT R57 M41 T27 VCCIO_DDR
V62 Y56 VCC VCC VCCPLL
VCCGT VCCGT T41 M51 AT24
W59 AN50 VCC VCC VCCIO_SENSE CPU_VCCIOSENSE_P OUT 47
VCCGT VCCGT AA32 M62 AR24
Y46 AT47 VCC VCC VSSIO_SENSE CPU_VCCIOSENSE_N OUT 47
VCCGT VCCGT AE33 N38
Y54 N46 VCC VCC
VCCGT VCCGT AE41 N57 PLACE_NEAR=U0500.AN24:50.8mm
Y64 T43 VCC VCC
AB58
VCCGT VCCGT
T50
AK32 VCC VCC P58
1
R0841
VCCGT VCCGT AN41 R41 100
AC44 U57 VCC VCC 5%
VCCGT VCCGT AT35 T32 1/32W
AC51 V56 VCC VCC MF
VCCGT VCCGT B64 Y41 2 01005
AC61 W53 PLACE_NEAR=U0500.N52:50.8mm TP_MCP_DC_B64 VCC VCC
VCCGT VCCGT L40 AC32
AD60 VCCGT VCCGT W63
1
R0830 L50
VCC VCC
AE36
AE57 Y49 100 VCC VCC
VCCGT VCCGT 5% M35 AF41
AF44 Y58 1/32W VCC VCC
VCCGT VCCGT MF M45 AL32
AF51 AN43 2 01005 VCC VCC
VCCGT VCCGT M56 AR41
AK46 VCC VCC
VCCGT
AB60 VCCGT_SENSE N52 CPU_VCCGTSENSE_P OUT 42
N32 VCC VCC AT38
VCCGT
AC46 VSSGT_SENSE P52 CPU_VCCGTSENSE_N OUT 42
N42 VCC VCC F64
VCCGT N61 L44
VCC VCC
PLACE_NEAR=U0500.P52:50.8mm P62 L54 PP1V_S3 6 8 12 15 31 42 50 61
VCC VCC
1
R0831 R59 VCC VCC M39 PLACE_NEAR=U0500.L34:50.8mm
5%
100 V32 VCC VCC M49 R0820 1
1/32W
MF AA41 VCC VCC M60 100
5% R0800 1 1
R0802
2 01005 AE35 N36 1/32W 56 100
VCC VCC MF 1% 1%
AF32 N55 01005 2 1/20W 1/20W
VCC VCC MF MF
AK41 VCC L34
R0810 201 2 2 201
AR32 VCC_SENSE CPU_VCCSENSE_P 42 220
VCC L32
OUT 1 2 CPU_VIDALERT_L 42
AT36 VSS_SENSE CPU_VCCSENSE_N OUT 42
IN
A VCC 1%
D64 VCC VIDALERT* B58 CPU_VIDALERT_R_L
1/20W
MF
201
R0811
0 SYNC_MASTER=DEVMLB SYNC_DATE=05/11/2015 A
L42 VCC VIDSCK A56 CPU_VIDSCLK_R 1 2 CPU_VIDSCLK 42
PAGE TITLE
OUT
L52
M37
VCC VIDSOUT A58 CPU_VIDSOUT_R
R0812
5%
1/20W
CPU Power
VCC AA26 MF DRAWING NUMBER SIZE
M47 VCCSTG PP1V_S0SW 0 0201
VCC
VCCSTG AC26
6 8 12 50
61 63 1 2 CPU_VIDSOUT BI 42
Apple Inc.
<SCH_NUM> D
R63 VCC PLACE_NEAR=U0500.L32:50.8mm 5% REVISION
P56 1/20W R0800.2: PLACE_NEAR=U0500.B58:12.7mm
VCC R0821 1 MF
0201 R0802.2: PLACE_NEAR=U0500.A58:12.7mm
R
<E4LABEL>
R32 VCC 100 NOTICE OF PROPRIETARY PROPERTY: BRANCH
Y32 5% R0811.1: PLACE_NEAR=U0500.A56:12.7mm
VCC 1/32W
MF
<BRANCH>
01005 2 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
8 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SPT-LP current estimates from Sunrise Point-LP PCH EDS vol 1, doc #545659, v1.2. NOTE: Aliases not used on CPU supply outputs
to avoid any extraneous connections.
VCCAMPHYPLL_1P0 and VCCPRIM_1P0 / VCCPRIM_3P3 breakdowns from Srini email 4/13/15
CRITICAL
OMIT_TABLE
U0500
SKL-Y-ULX
BGA
D 61 50 48 19 16 13 9 PP1V_SUS AH18 VCCPRIM_1P0 SKL-Y
SYM 17 OF 20
VCCPGPPA AT1 PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 D
370mA Max AH19 VCCPRIM_1P0 VCCPGPPA AU2 20/9mA @ 3.3/1.8V Max
AK18 PCH POWER AV1
VCCPRIM_1P0 VCCPGPPB PP3V3_SUS 9 13 14 16 17 36 46 49 50 61
AL18 VCCPRIM_1P0 VCCPGPPB AW2 4/2mA @ 3.3/1.8V Max
VCCPGPPC AH1 PP3V3_SUS
PPVCORE_SUS_PCH AE18 VCCPRIM_CORE
9 13 14 16 17 36 46 49 50 61
61 48
VCCPGPPC AJ2 6/3mA @ 3.3/1.8V Max
1.1A Max AE19 VCCPRIM_CORE
VCCPGPPD AF1 PP3V3_SUS
AF18 VCCPRIM_CORE
9 13 14 16 17 36 46 49 50 61
VCCPGPPD AG2 8/3mA @ 3.3/1.8V Max

AF19 VCCPRIM_CORE
VCCPGPPE AA2 PP3V3_SUS
AR16 VCCPRIM_CORE
9 13 14 16 17 36 46 49 50 61
VCCPGPPE AB1 6/2mA @ 3.3/1.8V Max

AT16 VCCPRIM_CORE
BYPASS=U0500.AL2::5.32mm VCCPGPPF AN2 PP1V8_SUS 9 13 17 24 33 48 50 61
PP1V_S5_PCH_DCPDSW AL2 DCPDSW_1P0 VCCPGPPF AP1 33/161mA @ 3.3/1.8V Max

MIN_LINE_WIDTH=0.2000 AM1 AN15
MIN_NECK_WIDTH=0.2000 DCPDSW_1P0 VCCPGPPG PP3V3_SUS 9 13 14 16 17 36 46 49 50 61
C0920 1 VOLTAGE=1.0V
PP1V_SUS V1 VCCMPHYAON_1P0
VCCPGPPG AP13 41/56mA @ 3.3/1.8V Max
1.0UF 16 13 9
61 50 48 19
W2 AC2
20%
6.3V 2 22mA Max VCCMPHYAON_1P0 VCCPRIM_3P3 PP3V3_SUS 9 13 14 16 17 36 46 49 50 61
X5R VCCPRIM_3P3 AD1 1mA Max
0201-1 61 50 13 9 PP1V_SUSSW_HSIO T1 VCCMPHYGT_1P0
Project specific (X260 TBD) T15 VCCMPHYGT_1P0 VCCPRIM_1P0 AA15 PP1V_SUS 9 13 16 19 48 50 61
See EDS Table 10-5 T16 VCCMPHYGT_1P0 VCCPRIM_1P0 AA16 6mA Max
U2 VCCMPHYGT_1P0
VCCATS AE15 PP1V8_SUS 9 13 17 24 33 48 50 61
13 PP1V_SUSSW_PCH_VCCAMPHYPLL V15 VCCAMPHYPLL_1P0 VCCATS AE16 6mA Max

V16 Must not exceed
88mA Max VCCAMPHYPLL_1P0 AK19 PP3V3_SUS
VCCRTCPRIM_3P3 9 13 14 16 17 36 46 49 50 61 3.2V max
13 PP1V_SUS_PCH_VCCAPLL AA18 VCCAPLL_1P0 VCCRTCPRIM_3P3 AL19 <1mA Max
AA19 PPVRTC_G3H 15 16 46 61
26mA Max VCCAPLL_1P0 AR19
VCCRTC
61 50 48 19 16 13 9 PP1V_SUS AH13 VCCPRIM_1P0 VCCRTC AT19 <1mA Max
C 168mA Max AH15 VCCPRIM_1P0
DCPRTC AT18 PPVOUT_S0_PCH_DCPRTC C0900
0.1UF
1 1 C0901
1.0UF
C
AL15 AV18 MIN_LINE_WIDTH=0.2000
60 59 50 49 48 46 45 18 15 13 PP3V3_S5 VCCDSW_3P3 DCPRTC MIN_NECK_WIDTH=0.2000 10%
10V
20%
67 61
AM13 VOLTAGE=1.0V X5R-CERM 2 2 6.3V
X5R
71mA Max VCCDSW_3P3 V18 PP1V_SUS 0201 0201-1
VCCCLK1 9 13 16 19 48 50 61
PP3V3R1V8R1V5_S0_PCH_VCCHDA AT23 VCCHDA VCCCLK1 Y18 35mA Max

13
68/36/33mA @ 3.3/1.8/1.5V Max AV22 VCCHDA 61

1 C0910 BYPASS=U0500.AR19::2.10mm
BYPASS=U0500.AT19::2.10mm
VCCCLK2 V19 PP1V_SUS 19 48 50
9 13 16
0.1UF
10%
61 50 49 46 36 17 16 14 13 9 PP3V3_SUS AT15 VCCSPI VCCCLK2 Y19 29mA Max 2 10V
X5R-CERM
11/7mA @ 3.3/1.8V Max AV15 VCCSPI 0201
VCCCLK3 V23 PP1V_SUS_PCH_VCCCLK3 13 BYPASS=U0500.AT18::1.08mm
61 50 13 9 PP1V_SUSSW_HSIO AA21 VCCSRAM_1P0 VCCCLK3 Y23 24mA Max
0.565A Max AA23 VCCSRAM_1P0
VCCCLK4 V21 PP1V_SUS_PCH_VCCCLK4
AK23 VCCSRAM_1P0
13
VCCCLK4 Y21 33mA Max

AL23 VCCSRAM_1P0
AN23 VCCSRAM_1P0 VCCCLK5 R21 PP1V_SUS_PCH_VCCCLK5 13
AR23 VCCSRAM_1P0 VCCCLK5 R23 4mA Max
61 50 49 46 36 17 16 14 13 9 PP3V3_SUS AH21 VCCPRIM_3P3 VCCCLK6 R19 PP1V_SUS 9 13 16 19 48 50 61
74mA Max AK21 VCCPRIM_3P3 VCCCLK6 T19 10mA Max

61 50 48 19 16 13 9 PP1V_SUS AR21 VCCPRIM_1P0 GPP_B0/CORE_VID0 BA13 TP_PCH_CORE_VID<0>
55mA Max AT21 VCCPRIM_1P0 GPP_B1/CORE_VID1 BB12 TP_PCH_CORE_VID<1>
61 50 13 9 PP1V_SUSSW_HSIO R15 VCCAPLLEBB_1P0
33mA Max R16 VCCAPLLEBB_1P0
B B
PAGE TITLE
PCH Power
DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
9 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL CRITICAL CRITICAL

OMIT_TABLE OMIT_TABLE OMIT_TABLE
U0500 U0500 U0500
SKL-Y-ULX SKL-Y-ULX SKL-Y-ULX
BGA BGA
SKL-Y BGA
D A14 VSS
SYM 18 OF 20
VSS K23 BH20 VSS
SKL-Y
SYM 19 OF 20
VSS AR50 AF33 VSS
SKL-Y
SYM 20 OF 20
VSS R46 D
AA36 VSS VSS K33 BH32 VSS VSS AT27 AF58 VSS VSS R6
AA47 K43 BH42 AU59 AH16 T23
GND 1 OF 3
GND 3 OF 3
VSS VSS VSS VSS VSS VSS
AA57 VSS VSS K53 BH52 VSS VSS AV24 AH33 VSS VSS T56
GND 2 OF 3
AC15 VSS VSS L61 BJ47 VSS VSS AY26 AH46 VSS VSS V13
AC27 VSS VSS N20 BL1 VSS VSS AW21 AH54 VSS VSS V36
AE10 VSS VSS R10 BL47 VSS VSS AY36 AK15 VSS VSS V47
AE43 VSS VSS R24 BM18 VSS VSS AY46 AK33 VSS VSS Y11
AE50 VSS VSS R40 BN6 VSS VSS BA1 AK7 VSS VSS Y27
AF16 VSS VSS R49 BP38 VSS VSS BB22 AL27 VSS VSS Y5
AF40 VSS VSS T13 BP60 VSS VSS BA58 AL43 VSS VSS BB26
AF62 VSS VSS T33 E16 VSS VSS BB32 AL50 VSS VSS BB36
AH24 VSS VSS T60 E26 VSS VSS BB42 AM64 VSS VSS BB46
AH40 VSS VSS V27 E36 VSS VSS BB52 AN24 VSS VSS BB59
AH49 VSS VSS V43 R43 VSS VSS BE12 AN59 VSS VSS BD38
AK1 VSS VSS V50 E46 VSS VSS BC47 AR15 VSS VSS BE31
AK24 VSS VSS Y15 E56 VSS VSS BE47 AR33 VSS VSS BF38
AK40 VSS VSS Y33 J3 VSS VSS BG12 AR44 VSS VSS BG17
AL16 VSS VSS Y9 K15 VSS VSS BG4 AR51 VSS VSS BG63
AL33 VSS VSS AA24 K25 VSS VSS BH34 AT54 VSS VSS BH26
AL46 VSS VSS AA40 K35 VSS VSS BH22 AU61 VSS VSS BH38
AL53 VSS VSS AA49 K45 VSS VSS BH44 AV52 VSS VSS BH48
AN18 VSS VSS AA59 K55 VSS VSS BH54 AW23 VSS VSS BH59
AN33 VSS VSS AC16 M3 VSS VSS BJ62 AY28 VSS VSS BK38
AP64 VSS VSS AC33 N22 VSS VSS BL29 AY38 VSS VSS BL33
AR2 VSS VSS AE2 R30 VSS VSS BM20 AY48 VSS VSS BM14
C AR4
AR47
VSS VSS AE44
AE51
R50
T18
VSS VSS BL8
BP22
BA11
BA64
VSS VSS BN29
BP30
C
VSS VSS VSS VSS VSS VSS
AR6 VSS VSS AF21 T36 VSS VSS BP44 BB24 VSS VSS BP52
AU55 VSS VSS AF54 T62 VSS VSS E18 BB34 VSS VSS C40
AV16 VSS VSS AF64 V30 VSS VSS E28 BB44 VSS VSS D8
AW17 VSS VSS AH27 V44 VSS VSS D6 BB54 VSS VSS E22
AY16 VSS VSS AH43 V51 VSS VSS E38 BD20 VSS VSS E32
AY32 VSS VSS AH50 Y16 VSS VSS E48 BE29 VSS VSS E42
AY42 VSS VSS AK11 Y36 VSS VSS E59 BF20 VSS VSS E52
AY52 VSS VSS AK27 Y7 VSS VSS K17 BG15 VSS VSS G14
BA5 VSS VSS AK5 AA27 VSS VSS J5 BG6 VSS VSS J7
BA9 VSS VSS AL21 AA43 VSS VSS K27 BH24 VSS VSS K21
BB28 VSS VSS AL36 AA50 VSS VSS K37 BH36 VSS VSS K31
BB38 VSS VSS AL47 AA61 VSS VSS K47 BH46 VSS VSS K41
BB48 VSS VSS AL59 AC18 VSS VSS N14 BH56 VSS VSS K51
BC17 VSS VSS AN19 AC36 VSS VSS L14 BK20 VSS VSS L59
BD56 VSS VSS AN36 AE21 VSS VSS N24 BL31 VSS VSS N18
BE33 VSS VSS AR10 AE46 VSS VSS R33 BM11 VSS VSS P54
BF56 VSS VSS AR27 AE8 VSS VSS R44 BM38 VSS VSS R2
BG2 VSS VSS AR40 AF23 VSS VSS T21 BP28 VSS VSS R4
BG8 VSS VSS AR49 AF56 VSS VSS R55 BP46 VSS VSS R47
BH28 VSS VSS AR8 AG59 VSS VSS T40 C14 VSS VSS R8
BH40 VSS VSS AU57 AH30 VSS VSS T64 D62 VSS VSS T24
BH50 VSS VSS AV20 AH44 VSS VSS V33 E20 VSS VSS T58
BJ29 VSS VSS AW19 AH51 VSS VSS Y1 E30 VSS VSS Y3
BK56 VSS VSS AY24 AK13 VSS VSS V46 E40 VSS VSS AA33
B
BL35
BM16
VSS
VSS
VSS
VSS
AY34
AY44
AK3
AK54
VSS
VSS
VSS
VSS
Y24
Y40
E50
F62
VSS
VSS
VSS
VSS
AA46
AA55 B
BP36 VSS VSS BA53 AL24 VSS VSS AA30 J62 VSS VSS AB13
BP54 VSS VSS BB20 AL40 VSS VSS AA51 K19 VSS VSS AC21
D10 VSS VSS BB30 AL49 VSS VSS AA44 K29 VSS VSS AD13
E14 VSS VSS BB40 AM54 VSS VSS AA63 K39 VSS VSS AE4
E24 VSS VSS BB50 AN21 VSS VSS AC19 K49 VSS VSS AE49
E34 VSS VSS BC29 AN40 VSS VSS AC40 L57 VSS VSS AF15
E44 VSS VSS BD63 AR12 VSS VSS AE47 N16 VSS VSS AF36
E54 VSS VSS BE35 AR30 VSS VSS AE30 N26 VSS VSS AF60
J14 VSS VSS BF59 AR43 VSS VSS AF13 R18 VSS VSS AH23
J9 VSS VSS BG29 AP54 VSS VSS AU53 R36 VSS VSS BP1 TP_MCP_DC_BP1
AH47 VSS VSS AL30 AR18 VSS VSS AU63 AY40 VSS VSS A5 TP_MCP_DC_A5
AJ59 VSS VSS AL44 AR36 VSS VSS AV54 V49 VSS VSS D1 TP_MCP_DC_D1
AK16 VSS VSS AL51 AR46 VSS VSS AW25 Y13 VSS
AK36 AN16 AR59 AY30 AH36 VSS BP62 TP_MCP_DC_BP62
VSS VSS VSS VSS VSS
AK9 VSS VSS AN27 BA3 VSS VSS AY50 V40 VSS
V24 VSS VSS BA7
PAGE TITLE
CPU & PCH Grounds

DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
10 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
All Intel recommendations from Intel doc #543016 Skylake U and Y Platform Design Guide Rev 1.3 unless stated otherwise
Intel's placeholders are no longer required per 4/20/15 email from Srini
CPU VCORE Decoupling

Intel recommendation (Table 52-2): 20x 0.1uF 0201 STUFF, 8x 10uF 0402, 6x 47uF 6.3V 0805 STUFF (2x NO STUFF)
61 43 34 8 PPVCORE_S0_CPU Apple implementation : 20x 0.1uF 0201 STUFF (6x NO STUFF), 16x 20uF 0402, 3x 270uF 2V B2
NO STUFF NO STUFF
1 C1100 1 C1101 1 C1102 1 C1103 1 C1104 1 C1105 1 C1106 1 C1107 1 C1108 1 C1109 1 C110A 1 C110B 1 C110C 1 C110D 1 C110E 1 C110F 1 C1110 1 C1111 1 C1112 1 C1113 1 C1114 1 C1115
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
6.3V
2 CERM-X5R 6.3V
2 CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
6.3V
2 CERM-X5R 2 6.3V
CERM-X5R
D
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201
D
NO STUFF NO STUFF NO STUFF NO STUFF CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL NO STUFF CRITICAL CRITICAL NO STUFF NO STUFF CRITICAL CRITICAL
1 C1116 1 C1117 1 C1118 1 C1119 1 C1132 1 C1133 1 C1120 1 C1121 1 C1122 1 C1123 1 C1124 1 C1125 1 C1126 1 C1127 1 C1128 1 C1129 1 C112A 1 C112B
0.1UF 0.1UF 0.1UF 0.1UF 12PF 12PF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF
10% 10% 10% 10% 5% 5% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
6.3V
2 CERM-X5R 2 6.3V
CERM-X5R 2 25V
NP0-C0G 2 25V
NP0-C0G 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
0201 0201 0201 0201 0201 0201 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
CRITICAL CRITICAL CRITICAL NO STUFF OMIT_TABLE OMIT_TABLE

1 C112C 1 C112D 1 C112E 1 C112F 1
C1130 1
C1131
20UF 20UF 20UF 20UF 220UF 220UF PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
20% 20% 20% 20% 20% 20%
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 3 2 2.0V 3 2 2.0V
0402 0402 0402 0402
POLY-TANT
D15T-D1L-COMBO
POLY-TANT
D15T-D1L-COMBO
128S00041 2 CAP,AL,POLY,220UF,20%,2V C1130,C1131 CRITICAL
CPU VCORE G0 Decoupling

Intel recommendation (Table 52-2): 12x 0.1uF 0201
8 PPVCCG0_S0_CPU Apple implementation : 12x 0.1uF 0201
1 C1140 1 C1141 1 C1142 1 C1143 1 C1144 1 C1145 1 C1146 1 C1147 1 C1148 1 C1149 1 C114A 1 C114B
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
C
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
C 2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
CPU VCORE G1 Decoupling

8 PPVCCG1_S0_CPU Apple implementation : 12x 0.1uF 0201
1 C1150 1 C1151 1 C1152 1 C1153 1 C1154 1 C1155 1 C1156 1 C1157 1 C1158 1 C1159 1 C115A 1 C115B
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
6.3V
2 CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201
CPU VCCIO Decoupling

Intel recommendation (Table 52-2): 13X 0.1UF 0201 STUFF (10x NO STUFF), 1x 1uF 0402, 1x 22uF 0805
61 47 8 5 PPVCCIO_S0 Apple implementation : 13x 0.1uF 0201 STUFF (10x NO STUFF), 1x 1uF 0201, 1x 20uF 0402
CRITICAL
1 C1160 1 C1161 1 C1162 1 C1163 1 C1164 1 C1165 1 C1166 1 C1167 1 C1168 1 C1169 1 C116A 1 C116B 1 C116C 1 C1177 1 C1178
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 1.0UF 20UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 20% 20%
B 2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
2 6.3V
CERM-X5R
0201
6.3V
2 X5R
0201-1
2 2.5V
X6S-CERM
0402 B
CPU VCCSA Decoupling

Intel recommendation (Table 52-2): 1x 1uF 0201, 4x 22uF 0603
61 43 8 PPVCCSA_S0 Apple implementation : 1x 1uF 0201, 5x 0.1uF NO STUFF, 5x 20uF 0402, 1x 270uF 2V B2
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF CRITICAL CRITICAL NO STUFF CRITICAL CRITICAL
1 C1180 1 C1181 1 C1182 1 C1183 1 C1184 1 C118A 1 C118B 1 C118C 1 C118D 1 C118E 1 C118F 1
C1190
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 1.0UF 10UF 10UF 10UF 10UF 10UF 120UF
10% 10% 10% 10% 10% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
6.3V
2 X5R 2 4V
X6S 2 4V
X6S 2 4V
X6S 2 4V
X6S 2 4V
X6S 2 2.5V
TANT-POLY
0201 0201 0201 0201 0201 0201-1 0402 0402 0402 0402 0402 CASE-B2-SM
A CPU VCCSA DDR Decoupling SYNC_MASTER=DEVMLB SYNC_DATE=04/14/2015 A

Intel recommendation (Table 52-2): 1x 0.1uF 0201 STUFF, 1x 22uF 0603 PAGE TITLE
61 43 8 PPVCCSA_DDR_S0 Apple implementation : 1x 0.1uF 0201 STUFF, 1x 20uF 0402 CPU Decoupling 1
DRAWING NUMBER SIZE
CRITICAL
Apple Inc.
<SCH_NUM> D
1 C1195 1 C1197 REVISION
0.1UF 10UF R
<E4LABEL>
10% 20%
2 6.3V
CERM-X5R 2 4V
X6S NOTICE OF PROPRIETARY PROPERTY: BRANCH
0201 0402 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
11 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
All Intel recommendations from Intel doc #543016 Skylake U and Y Platform Design Guide Rev 1.3 unless stated otherwise
Intel's placeholders are no longer required per 4/20/15 email from Srini
CPU GT Decoupling
Intel recommendation (Table 52-2): 12x 0.1uF 0201 STUFF, 2x 1uF 0402, 2x 10uF 0402 NO STUFF, 9x 47uF 6.3V 0805
61 44 34 8 PPVCORE_S0_GT Apple implementation : 12x 0.1uF 0201 STUFF (20x NO STUFF), 2x 1uF 0201, 16x 20uF 0402, 2x 270uF 2V B2
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF
1 C1200 1 C1201 1 C1202 1 C1203 1 C1204 1 C1205 1 C1206 1 C1207 1 C1208 1 C1209 1 C1210 1 C1211 1 C1212 1 C1213 1 C1214 1 C1215 1 C1216 1 C1217 1 C1218 1 C1219 1 C1220 1 C1221
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
D
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 0201
D
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF
1 C1222 1 C1223 1 C1224 1 C1225 1 C1226 1 C1227 1 C1228 1 C1229 1 C1230 1 C1231
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201
NO STUFF CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL NO STUFF
1 C1252 1 C1253 1 C1254 1 C1255 1 C1256 1 C1257 1 C1258 1 C1259 1 C125A 1 C125B 1 C125C 1 C125D 1 C125E 1 C125F
1.0UF 1.0UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
X5R 2 6.3V
X5R 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM
0201-1 0201-1 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
NO STUFF CRITICAL CRITICAL NO STUFF CRITICAL CRITICAL

1 C1260 1 C1261 1 C1262 1 C1263 1
C1264 1
C1265
20UF 20UF 20UF 20UF 270UF 270UF
20% 20% 20% 20% 20% 20%
2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2.5V
X6S-CERM 2 2V 2 2V
TANT TANT
0402 0402 0402 0402 CASE-B2-SM CASE-B2-SM
C CPU VDDQ DECOUPLING C

50 47 22 21 20 8
61
PP1V2_S3 Apple implementation : 18x 0.1uF 0201
1 C1270 1 C1271 1 C1272 1 C1273 1 C1274 1 C1275 1 C1276 1 C1277 1 C1278 1 C1279
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201
1 C1280 1 C1281 1 C1282 1 C1283 1 C1284 1 C1285 1 C1286 1 C1287

0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
10% 10% 10% 10% 10% 10% 10% 10%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
0201 0201 0201 0201 0201 0201 0201 0201
CPU VCCST BYPASS

(CPU 1.0V SUSTAIN PWR)
42 31 15 12 8
61
6
50
PP1V_S3
C1290 1
0.1UF
10%
B
6.3V 2
X6S
0201 B
BYPASS=U0500.V26::2.38mm
CPU VCCSTG BYPASS

(CPU 1.0V SUSTAIN GATED PWR)
63 61 50 8 6 PP1V_S0SW
C1292 1
0.1UF
10%
6.3V 2
X6S
0201
BYPASS=U0500.R26::4.20mm
CPU VCCPLL_OC BYPASS

(CPU 1.2V PLL PWR)
61 50 8 PP1V2_S0SW
C1294 1
0.1UF
10%
6.3V 2
X6S
0201
BYPASS=U0500.AE27::2.07mm
CPU VCCPLL BYPASS

A (CPU 1.0V DIGITAL PLL PWR) SYNC_MASTER=DEVMLB SYNC_DATE=05/06/2015 A
42 31 15 12 8 6 PP1V_S3 PAGE TITLE
61 50
CPU Decoupling 2
C1296 1 DRAWING NUMBER SIZE
0.1UF <SCH_NUM> D
10%
6.3V 2 Apple Inc.
X6S REVISION
0201
R
<E4LABEL>

<BRANCH>
NOTE: Bypass calcs based on 0.1mm trace width
with worst case stackup and 500pH added
12 OF 130
SHEET
for power/ground via pair. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH VCCDSW_3P3 BYPASS PCH VCCATS BYPASS PCH VCCPRIM_1P0 BYPASS
(PCH 3.3V DSW PWR) (PCH 1.8V THERMAL PWR) (PCH 1.0V USB PWR)
59 50 49 48 46 45 18 15
67 61
9
60
PP3V3_S5 61 50 48 33 24 17 9 PP1V8_SUS 61 50 48 19 16 13 9 PP1V_SUS
C1300 1 C1330 1 C1336 1

0.1UF 1.0UF 0.1UF
10% 20% 10%
6.3V 2 6.3V 2 6.3V 2
X6S X5R X6S
0201 0201-1 0201
BYPASS=U0500.AL15::1.96mm BYPASS=U0500.AE15::1.76mm BYPASS=U0500.AH13::1.39mm
PCH VCCSPI BYPASS

(PCH 3.3V/1.8V SPI PWR)
D 50 49 46 36 17 16 14 13 9
61
PP3V3_SUS D
PCH VCCMPHYAON_1P0 BYPASS PCH VCCAPLLEBB BYPASS PCH VCCMPHYGT_1P0 BYPASS
C1302 1
(PCH 1.0V MPHY ALWAYS ON PWR) (PCH 1.0V APLL EBB PWR) (PCH 1.0V MPHY GATED PWR)
0.1UF
10%
6.3V 2 61 50 48 19 16 13 9 PP1V_SUS 61 50 13 9 PP1V_SUSSW_HSIO 61 50 13 9 PP1V_SUSSW_HSIO
X6S
0201
BYPASS=U0500.AT15::2.38mm C1340 1 C1344 1
0.1UF
10%
0.1UF
10% C1346 1 1 C1347 1 C1348
6.3V 2
X6S
6.3V 2
X6S
0.1UF 1.0UF 20UF
10% 20% 20%
0201 0201 6.3V 2 6.3V
2 X5R 2 6.3V
BYPASS=U0500.V1::1.68mm BYPASS=U0500.R15::1.54mm X6S CERM-X5R
0201 0201-1 0402
BYPASS=U0500.T15::3.07mm
PCH VCCAMPHYPLL_1P0 FILTER/BYPASS

(PCH 1.0V USB3/PCIE/SATA/MIPI PLL PWR)
61 50 13 9 PP1V_SUSSW_HSIO R1370 PP1V_SUSSW_PCH_VCCAMPHYPLL
MIN_LINE_WIDTH=0.2000
9
PCH VCCRTCPRIM BYPASS 1

0 2
MIN_NECK_WIDTH=0.1000
VOLTAGE=1.0V
(PCH 3.3V SUSPEND RTC PWR)
PP3V3_SUS
5% NOSTUFF NOSTUFF NOSTUFF
50 49 46 36 17 16 14 13 9
61
1/16W
MF-LF
402
C1370 1 C1371 1 1 C1372
20UF 20UF 0.1UF
20% 20% 10%
6.3V 2 6.3V 2 2 6.3V
C1306 1 1 C1307 CERM-X5R
0402
CERM-X5R
0402
X6S
0201
1.0UF 0.1UF
20% 10% BYPASS=U0500.V15::12.82mm
6.3V 2 2 6.3V BYPASS=U0500.V15::12.82mm
X5R X6S BYPASS=U0500.V15::3.91mm
0201-1 0201
BYPASS=U0500.AK19::1.68mm
C BYPASS=U0500.AK19::1.68mm
PCH VCCCLK3 FILTER/BYPASS C
(PCH 1.0V CLOCK 3 PWR)
61 50 48 19 16 13 9 PP1V_SUS R1380 PP1V_SUS_PCH_VCCCLK3
9
1
0 2
VOLTAGE=1.0V
5% NOSTUFF NOSTUFF
1/16W
MF-LF
402
C1380 1 C1381 1
20UF 20UF
20% 20%
6.3V 2 6.3V 2
CERM-X5R CERM-X5R
0402 0402
PCH VCCPGPPE BYPASS
(PCH 3.3V/1.8V GPIO GROUP E PWR)
61 50 49 46 36 17 16 14 13 9 PP3V3_SUS PCH VCCCLK4 FILTER/BYPASS
C1318 1
PP1V_SUS R1385 PP1V_SUS_PCH_VCCCLK4
9
0.1UF 19 16 13 9
61 50 48 0 MIN_NECK_WIDTH=0.1000
10% 1 2 VOLTAGE=1.0V
6.3V 2
X6S 5% NOSTUFF NOSTUFF
0201
BYPASS=U0500.AA2::0.84mm
1/16W
MF-LF
402
C1385 1 C1386 1
20UF 20UF
20% 20%
6.3V 6.3V
CERM-X5R 2 CERM-X5R 2
0402 0402
B PCH VCCCLK5 FILTER/BYPASS B

61 50 48 19 16 13 9 PP1V_SUS R1390 PP1V_SUS_PCH_VCCCLK5
9
1
0 2
VOLTAGE=1.0V
5% NOSTUFF NOSTUFF
1/16W
MF-LF
402
C1390 1 C1391 1 1 C1392
20UF 20UF 0.1UF
20% 20% 10%
6.3V
CERM-X5R 2
6.3V
CERM-X5R 2 2 6.3V
X6S
0402 0402 0201
PCH VCCHDA FILTER/BYPASS

L1309 (PCH 3.3V/1.8V/1.5V HDA PWR)
220-OHM-0.7A-0.28-OHM PP3V3R1V8R1V5_S0_PCH_VCCHDA 9
61 49 46 39 18 PP1V5_S0 MIN_LINE_WIDTH=0.0950
1 2 MIN_NECK_WIDTH=0.0700
VOLTAGE=1.5V
0402-1
C1309 1
0.1UF
10%
6.3V 2
X6S
0201
BYPASS=U0500.AT23::1.23mm
A PCH VCCAPLL FILTER/BYPASS

L1395 (PCH 1.0V APLL PWR) PAGE TITLE
PP1V_SUS_PCH_VCCAPLL
61 50 48 19 16 13 9 PP1V_SUS 220-OHM-0.7A-0.28-OHM
1 2
9
PCH Decoupling
VOLTAGE=1.0V DRAWING NUMBER SIZE
0402-1
Apple Inc.
<SCH_NUM> D
C1395 1 REVISION
0.1UF R
<E4LABEL>
10%
6.3V 2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
X6S
BYPASS=U0500.AA18::1.23mm
0201 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
13 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
OMIT_TABLE
U0500
SKL-Y-ULX
D BGA
SKL-Y
PLT_RST_L IN 5 15 19 26 30 65 D
TBT TBT
39 OUT
HDA_SYNC R1400 33 1 2
5% 1/32W MF 01005 HDA_SYNC_R BJ19 HDA_SYNC/I2S0_SFRM
SYM 7 OF 20
GPP_G0/SD_CMD AH9 TBT_X_CIO_PWR_EN 14 64
1
R1424 1
R1425 1
R1426 1
R1428
OUT
HDA_BIT_CLK R1401 33 1 2
PLACE_NEAR=U0500.BJ19:1.27mm
HDA_BIT_CLK_R BK18 (IPD-PLTRST#)
AH11 TBT_X_USB_PWR_EN 100K 100K 100K 100K
39 OUT HDA_BLK/I2S0_SCLK GPP_G1/SD_DATA0 OUT 14 64 5% 5% 5% 5%
5% 1/32W MF 01005 BK16 AG12 1/32W 1/32W 1/32W 1/32W
HDA_SDOUT_R TBT_T_CIO_PWR_EN
39 OUT
HDA_SDOUT R1402 33 1 2
PLACE_NEAR=U0500.BK18:1.27mm
5% 1/32W MF 01005 65 39
18
HDA_SDIN0 BL15
HDA_SDO/I2S0_TXD
(IPD-PLTRST#)
HDA_SDI0/I2S0_RXD
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2 AF9 TBT_T_USB_PWR_EN
OUT 14 64
14 64
MF
2 01005
MF
2 01005
MF
2 01005
MF
2 01005
IN OUT
PLACE_NEAR=U0500.BK16:1.27mm BL17 (IPD) AF11
64 NC_HDA_SDIN1 HDA_SDI1/I2S1_RXD GPP_G4/SD_DATA3 TBT_X_PCI_RESET_L OUT 64
39 OUT
HDA_RST_L R1403 33 1 2
5% 1/32W MF 01005
HDA_RST_R_L BL19 HDA_RST*/I2S1_SCLK GPP_G5/SD_CD* AG8 TBT_T_PCI_RESET_L OUT 64
PLACE_NEAR=U0500.BL19:1.27mm 63 TP_XDP_PCH_OBSDATA_D0 V5 GPP_D23/I2S_MCLK GPP_G6/SD_CLK AG10 AP_RESET_L 25 65

OUT OUT
TP_PCH_I2S1_SFRM BL12 I2S1_SFRM (IPD) GPP_G7/SD_WP AE12 AP_DEV_WAKE 14 25 65
OUT
BK14 AUDIO
TP_PCH_I2S1_TXD I2S1_TXD BL4
GPP_A17/SD_PWR_EN*/ISH_GP7 CAMERA_RESET_L OUT 27 65
64 NC_PCH_BT_I2S_SYNC AT13 GPP_F1/I2S2_SFRM GPP_A16/SD_1P8_SEL BN4 CAMERA_PWR_EN 14 27 65

OUT OUT
NC_PCH_BT_I2S_CLK AT11 GPP_F0/I2S2_SCLK
64 OUT
SD_RCOMP BF1 PCH_SD_RCOMP
64 NC_PCH_BT_I2S_R2D AP11 GPP_F2/I2S2_TXD
OUT
NC_PCH_BT_I2S_D2R AT5 AJ8 SSD_PWR_EN_L SD
GPP_F3/I2S2_RXD GPP_F23
R1430
64 14 59
IN OUT 1
63 TP_XDP_PCH_OBSDATA_C2 V3 GPP_D19/DMIC_CLK0 200

OUT
V11 SDIO/SDXC 1%
63 OUT
TP_XDP_PCH_OBSDATA_C3 GPP_D20/DMIC_DATA0 1/20W
MF
63 TP_XDP_PCH_OBSDATA_C0 U12 GPP_D17/DMIC_CLK1 2 201
OUT
63 TP_XDP_PCH_OBSDATA_C1 U8 GPP_D18/DMIC_DATA1
OUT
Requires connection to SMC via 1K series R 31 PCH_STRP_TOPBLK_SWP_L AV3 GPP_B14/SPKR

IN
(IPD-PLTRST#)
CRITICAL
C OMIT_TABLE
C
U0500
SKL-Y-ULX
BGA
SKL-Y
36 OUT
SPI_CLK AU10 SPI0_CLK SYM 5 OF 20 GPP_C0/SMBCLK AC12 SMBUS_PCH_CLK OUT 33
AU12 GPP_C1/SMBDATA W6
(IPU-RSMRST#)
36 BI
SPI_MISO SPI0_MISO SMBUS_PCH_DATA BI 33
AT3 GPP_C2/SMBALERT* W8
(IPU)
SPI_MOSI SPI0_MOSI PCH_STRP_TLSCONF TLS strap sampled at RSMRST# rising (0 = disable)
SMBUS, SMLINK
36 BI 14
SPI_IO<2> AV11 (IPU-RSMRST#) (IPD-RSMRST#)
SPI - FLASH
SPI0_IO2
GPP_C3/SML0CLK W4
36 BI
AV13 (IPU) SML_PCH_0_CLK 33
SPI_IO<3> SPI0_IO3
OUT
GPP_C4/SML0DATA AC10
36 BI
AU4 (IPU) SML_PCH_0_DATA 33
SPI_CS0_L SPI0_CS0*
BI
GPP_C5/SML0ALERT* AA6
36 OUT
AU6 (IPU-RSMRST#) PCH_STRP_ESPI 14 LPC strap sampled at RSMRST# rising (0 = LPC, 1 = eSPI)
TP_SPI_CS1_L SPI0_CS1* (IPD-RSMRST#)
AU8 GPP_C6/SML1CLK AA4
(IPU-RSMRST#)
TP_SPI_CS2_L SPI0_CS2* SMBUS_SMC_1_S0_SCL OUT 30 33 35 53
GPP_C7/SML1DATA W10
(IPU-RSMRST#)
SMBUS_SMC_1_S0_SDA BI 30 33 35 53
TP_PCH_GPP_D1 P9 GPP_D1 GPP_B23/SML1ALERT*/PCHHOT* BB6 PCH_STRP_BSSB_SEL_GPIO 14 BSSB strap sampled at RSMRST# rising (0 = USB-SS, 1=GPP_D11/D12)
63 TP_SPKR_ID1 N8 GPP_D2
(IPD-PLTRST#)
IN
TP_PCH_GPP_D3 P3 GPP_D3 GPP_A1/LAD0/ESPI_IO0 BK11 LPC_AD_R<0> R1470 33.2 1 2 LPC_AD<0> BI 30
MLB_RAMCFG4 W12 GPP_D21 GPP_A2/LAD1/ESPI_IO1 BJ8 LPC_AD_R<1> R1471 33.2 1 2

1% 1/32W MF 01005
LPC_AD<1>
LPC
17 IN BI 30
63 IN
TP_SPKR_ID0 V7 GPP_D22
(IPU)
GPP_A3/LAD2/ESPI_IO2 BG10 LPC_AD_R<2> R1472 33.2 1 2
1% 1/32W MF 01005
LPC_AD<2> BI 30
TP_PCH_GPP_D0 N6 GPP_D0 GPP_A4/LAD3/ESPI_IO3 BP5 LPC_AD_R<3> R1473 33.2 1 2

1% 1/32W MF 01005
LPC_AD<3> BI 30
(IPU-eSPI)
GPP_A5/LFRAME*/ESPI_CS* BP7 LPC_FRAME_R_L R1474 33.2 1 2
1%
1%
1/32W
1/32W
MF
MF
01005
01005
LPC_FRAME_L OUT 30
NC_CLINK_CLK F12 CL_CLK GPP_A14/SUS_STAT*/ESPI_RESET* BJ6 LPC_PWRDWN_L
C LINK
64 (IPU/IPD) OUT 30
NC_CLINK_DATA D12
64
NC_CLINK_RESET_L B12
CL_DATA
CL_RST*
(IPU/IPD)
GPP_A9/CLKOUT_LPC0/ESPI_CLK BJ10 LPC_CLK24M_SMC_R R1476 22 1 2
1% 1/20W MF 201
LPC_CLK24M_SMC OUT 30
GPP_A10/CLKOUT_LPC1 BF5
64
TP_PCH_CLKOUT_LPC1
TP_PCH_GPP_A0 BL10 GPP_A0/RCIN* (IPU-eSPI) GPP_A8/CLKRUN* BH11 LPC_CLKRUN_L 14 30
BI
65 30 14 LPC_SERIRQ BN8 GPP_A6/SERIRQ (IPU-eSPI)
BI
B B
PP3V3_SUS 9 13 14 16 17 36 46 49 50 61
PP3V3_SUS 9 13 14 16 17 36 46 49 50 61
PP3V3_SUS 9 13 14 16 17 36 46 49 50 61
PP3V3_S0 5 6 15 16 17 19 23 26 27 31 33
34 35 39 46 50 51 53 61 67
TBT (x4)
R1420 100K 1 2 TBT_X_CIO_PWR_EN 14 64
R1421 100K 1 2
5% 1/32W MF 01005
TBT_X_USB_PWR_EN 14 64
R1422 100K 1 2
5% 1/32W MF 01005
TBT_T_CIO_PWR_EN 14 64
R1423 100K 1 2
5% 1/32W MF 01005
TBT_T_USB_PWR_EN 14 64
R1427 100K 1 2
5% 1/32W MF 01005
AP_DEV_WAKE 14 25 65
R1429 100K 1 2
5% 1/32W MF 01005
CAMERA_PWR_EN
A R1431 100K 1 2
5% 1/32W MF 01005
SSD_PWR_EN_L
14 27 65
14 59 SYNC_MASTER=DEVMLB SYNC_DATE=05/11/2015 A
R1450 10K 1 2
5% 1/32W MF 01005
LPC_SERIRQ 14 30 65
PAGE TITLE
TLS
5% 1/32W MF 01005
PCH Audio/LPC/SPI/SMBus
R1463 1.00K 1 2
5% 1/32W MF 01005
PCH_STRP_TLSCONF 14
DRAWING NUMBER
<SCH_NUM>
SIZE
D
Apple Inc.
ESPI REVISION
R1466 1.00K 1 2
5% 1/32W MF 01005
PCH_STRP_ESPI 14
R
<E4LABEL>
BSSB_GPIO
R1469 1.00K 1 2 PCH_STRP_BSSB_SEL_GPIO 14
<BRANCH>
R1478 10K 1 2
5%
5%
1/32W
1/32W
MF
MF
01005
01005
LPC_CLKRUN_L 14 30
THE POSESSOR AGREES TO THE FOLLOWING:
PAGE
14 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
67
27 26 23 19 17 16 15 14 6 5
61 53 51 50 46 39 35 34 33 31
PP3V3_S0 OMIT_TABLE
1
R1510 U0500
2.2K SKL-Y-ULX
D 61 50 42 31 12 8 6 PP1V_S3
5%
1/20W
MF
BGA
SKL-Y
D
2 201 SYM 11 OF 20
SYSTEM POWER MANAGEMENT
BB8 BC9
R1520 1 65 30 26 19 14 5 OUT
PLT_RST_L
H2
GPP_B13/PLTRST* GPP_B12/SLP_S0*
AY14
PM_SLP_S0_L OUT 15 30 46 67
1.00K 30 IN
PM_SYSRST_L SYS_RESET* GPD4/SLP_S3* PM_SLP_S3_L OUT 15 30 46 49 50 51 65
5% BJ12 BF16
1/32W 63 46 30 IN
PM_RSMRST_L RSMRST* GPD5/SLP_S4* PM_SLP_S4_L OUT 15 30 46 47 50 51 63
MF BH14
01005 2 R1521 TP_CPU_PWRGD A62 PROCPWRGD
GPD10/SLP_S5* PM_SLP_S5_L OUT 15 30 45 50 51
CPU_VCCST_PWRGD 1
60.4 2 CPU_VCCST_PWRGD_R B61 BN10 PM_SLP_SUS_L
46 IN VCCST_PWRGD SLP_SUS* OUT 15 46 48 50 51
PLACE_NEAR=U0500.B61:7.62mm BP11
1% J1 SLP_LAN* TP_PCH_SLP_LAN_L
1/20W 51 46 30 PMIC_SYS_PWROK SYS_PWROK BH16
MF IN
BP14 GPD9/SLP_WLAN* TP_PCH_SLP_WLAN_L
201 46 PM_PCH_PWROK PCH_PWROK BE17 PPVRTC_G3H 9 16 46 61
IN
BN15 GPD6/SLP_A* TP_PM_SLP_A_L
65 30 IN
PM_DSW_PWRGD DSW_PWROK
BF14
SMC_PCH_SUSWARN_L BL6 GPP_A13/SUSWARN*/
(IPU) GPD3/PWRBTN*
BD14
PM_PWRBTN_L IN 15 30
1
R1580
R1530 1
63 30 OUT
BF9 SUSPWRDNACK GPD1/ACPRESENT SSD_SR_EN_L 15 59 65 1M
63 30 SMC_PCH_SUSACK_L GPP_A15/SUSACK* (IPU) BD16
OUT
5%
100K IN
(IPD-DeepSx) GPD0/BATLOW* PM_BATLOW_L IN 15 30 1/20W
5% BP9 MF
1/32W 18 15 PCIE_WAKE_L WAKE* (IPD-DeepSx) BF7 2 201
MF
IN
BE15 (IPU) GPP_A11/PME* NC_PCI_PME_L 64
01005 2 65 30 15 SMC_WAKE_SCI_L GPD2/LAN_WAKE* (IPD-DeepSx) BG19
IN
BC15 INTRUDER* PCH_INTRUDER_L
TP_PCH_LANPHYPC GPD11/LANPHYPC
TP_PCH_GPD7 BB16 GPD7/RSVD GPP_B11/EXT_PWR_GATE* BC7 PCH_HSIO_PWR_EN 50
OUT
GPP_B2/VRALERT* BD6 BT_LOW_PWR_L 15 25
OUT
C C
B B
PP3V3_S5 9 13 18 45 46 48 49 50 59 60 61
67
PP3V3_S4 18 24 25 26 29 31 46 50 59 61
PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31
33 34 35 39 46 50 51 53 61 67
R1540 10K 1 2 PCIE_WAKE_L 15 18
A R1541 100K 1 2
5%
5%
1/32W
1/32W
MF
MF
01005
01005
SMC_WAKE_SCI_L 15 30 65
SYNC_MASTER=X260_ERIC SYNC_DATE=06/04/2015 A
R1550 100K 1 2 PM_SLP_S0_L 15 30 46 67
PAGE TITLE
R1551 100K 1 2
5% 1/32W MF 01005
PM_SLP_S3_L 15 30 46 49 50 51 65 PCH Power Management
R1552 100K 1 2
5% 1/32W MF 01005
PM_SLP_S4_L 15 30 46 47 50 51 63 DRAWING NUMBER SIZE
R1553 100K 1 2
5% 1/32W MF 01005
PM_SLP_S5_L 15 30 45 50 51
Apple Inc.
<SCH_NUM> D
R1554 100K 1 2
5%
5%
1/32W
1/32W
MF
MF
01005
01005
PM_SLP_SUS_L 15 46 48 50 51 REVISION
R1570 1.00K 1 2 PM_PWRBTN_L 15 30

R
<E4LABEL>
R1571 100K 1 2
5% 1/32W MF 01005
SSD_SR_EN_L 15 59 65
<BRANCH>
R1572 10K 1 2
5% 1/32W MF 01005
PM_BATLOW_L 15 30
R1576 10K 1 2
5%
5%
1/32W
1/32W
MF
MF
01005
01005
BT_LOW_PWR_L 15 25
PAGE
15 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
OMIT_TABLE
U0500
SKL-Y-ULX
PCIe Port Assignments: BGA
SKL-Y USB3 Port Assignments:
65 63 PCIE_SSD_D2R_N<0> C20 PCIE1_RXN/USB3_5_RXN SYM 8 OF 20 USB3_1_RXN C16 USB3_EXTA_D2R_N 60 65
IN IN
65 63 PCIE_SSD_D2R_P<0> A20 PCIE1_RXP/USB3_5_RXP USB3_1_RXP A16 USB3_EXTA_D2R_P 60 65
IN IN
SSD lane 0 54 PCIE_SSD_R2D_C_N<0> G20 PCIE1_TXN/USB3_5_TXN USB3_1_TXN G16 USB3_EXTA_R2D_C_N 60 Ext A (SS, DCI)
OUT OUT
54 PCIE_SSD_R2D_C_P<0> J20 PCIE1_TXP/USB3_5_TXP USB3_1_TXP J16 USB3_EXTA_R2D_C_P 60
OUT OUT
D 63 IN
PCIE_SSD_D2R_N<1> B19 PCIE2_RXN/USB3_6_RXN USB3_2_RXN/SSIC_RXN B15 NC_USB3_EXTB_D2RN IN 65 D
63 PCIE_SSD_D2R_P<1> D19 PCIE2_RXP/USB3_6_RXP USB3_2_RXP/SSIC_RXP D15 NC_USB3_EXTB_D2RP 65
IN IN
PCIE_SSD_R2D_C_N<1> F19 F15 NC_USB3_EXTB_R2D_CN Ext B (SS)
SSD lane 1 54 OUT PCIE2_TXN/USB3_6_TXN USB3_2_TXN/SSIC_TXN OUT 65
PCIE_SSD_R2D_C_P<1> H19 PCIE2_TXP/USB3_6_TXP USB3_2_TXP/SSIC_TXP H15 NC_USB3_EXTB_R2D_CP
SSIC / USB3
54 OUT OUT 65
63 NC_PCIE_SSD_D2RN<2> C22 PCIE3_RXN USB3_3_RXN C18 NC_USB3_EXTC_D2RN 65

IN IN
63 NC_PCIE_SSD_D2RP<2> A22 PCIE3_RXP USB3_3_RXP A18 NC_USB3_EXTC_D2RP 65
IN IN
NC_PCIE_SSD_R2D_CN<2> G22 G18 NC_USB3_EXTC_R2D_CN Ext C (SS)
SSD lane 2 63 OUT PCIE3_TXN USB3_3_TXN OUT 65
63 NC_PCIE_SSD_R2D_CP<2> J22 PCIE3_TXP USB3_3_TXP J18 NC_USB3_EXTC_R2D_CP 65

OUT OUT
63 NC_PCIE_SSD_D2RN<3> B21 PCIE4_RXN USB3_4_RXN B17 NC_USB3_EXTD_D2RN 65

IN IN
63 NC_PCIE_SSD_D2RP<3> D21 PCIE4_RXP USB3_4_RXP D17 NC_USB3_EXTD_D2RP 65
IN IN
PCIE/USB3/SATA
NC_PCIE_SSD_R2D_CN<3> F21 F17 NC_USB3_EXTD_R2D_CN Ext D (SS)
SSD lane 3 63 OUT PCIE4_TXN USB3_4_TXN OUT 65
63 NC_PCIE_SSD_R2D_CP<3> H21 PCIE4_TXP USB3_4_TXP H17 NC_USB3_EXTD_R2D_CP 65 USB Port Assignments:

OUT OUT
65 PCIE_TEST_D2R_N C24 PCIE5_RXN USB2N_1 AJ6 USB_EXTA_N 23 65

BI
A24 Ext A (LS/FS/HS)
65 PCIE_TEST_D2R_P PCIE5_RXP USB2P_1 AJ4 USB_EXTA_P BI 23 65
Reserved: Thunderbolt A lane 0 PCIE_TEST_R2D_N G24 PCIE5_TXN

USB2N_5 AH5
65
J24 NC_USB_EXTDN 65
PCIE_TEST_R2D_P PCIE5_TXP
BI
Ext D (LS/FS/HS)
USB2P_5 AH3
65
NC_USB_EXTDP BI 65
TP_PCIE_TBT_A_D2RN<1> B23 PCIE6_RXN

D23 USB2N_7 AF5 TP_USB_7N
TP_PCIE_TBT_A_D2RP<1> PCIE6_RXP Unused
F23 USB2P_7 AF3 TP_USB_7P
Reserved: Thunderbolt A lane 1 TP_PCIE_TBT_A_R2D_CN<1> PCIE6_TXN
USB2
TP_PCIE_TBT_A_R2D_CP<1> H23 PCIE6_TXP USB2N_3 AL6 NC_USB_EXTCN 65
BI
Ext C (LS/FS/HS)
C26 USB2P_3 AL4 NC_USB_EXTCP 65
TP_PCIE_TBT_B_D2RN<0> PCIE7_RXN/SATA0_RXN
BI
TP_PCIE_TBT_B_D2RP<0> A26 PCIE7_RXP/SATA0_RXP USB2N_9 AG6 USB_TEST_N 65

G26 Unused
Reserved: Thunderbolt B lane 0 TP_PCIE_TBT_B_R2D_CN<0> PCIE7_TXN/SATA0_TXN USB2P_9 AG4 USB_TEST_P 65
TP_PCIE_TBT_B_R2D_CP<0> J26 PCIE7_TXP/SATA0_TXP AM3 NC_USB_EXTBN

C TP_PCIE_TBT_B_D2RN<1> B25 PCIE8_RXN/SATA1A_RXN
USB2N_2
USB2P_2 AM5 NC_USB_EXTBP
BI
BI
65
65
Ext B (LS/FS/HS) C
D25 (IPD)
TP_PCIE_TBT_B_D2RP<1> PCIE8_RXP/SATA1A_RXP N2
Reserved: Thunderbolt B lane 1 F25 USB2_COMP PCH_USB2_COMP
TP_PCIE_TBT_B_R2D_CN<1> PCIE8_TXN/SATA1A_TXN AF7
H25 (IPU) USB2_ID
TP_PCIE_TBT_B_R2D_CP<1> PCIE8_TXP/SATA1A_TXP AE6 Grounded per SKL MOW 2015WW10
USB2_VBUSSENSE USB2_VBUSSENSE
PCIE_AP_D2R_N C28 PCIE9_RXN PLACE_NEAR=U0500.N2:2.54mm
25 IN
GPP_E9/USB2_OC0* N12 XDP_USB_EXTA_OC_L
A28
R1620 1
R1622
16 23 24 63 65
25 PCIE_AP_D2R_P PCIE9_RXP M11
IN 1
IN
G28 GPP_E10/USB2_OC1* USB_EXTB_OC_L 16 63 64
Airport 25 PCIE_AP_R2D_C_N PCIE9_TXN F8
IN
1.00K 113
OUT
J28 GPP_E11/USB2_OC2* XDP_USB_EXTC_OC_L 16 64 5% 1%
25 PCIE_AP_R2D_C_P PCIE9_TXP B8
IN
1/32W 1/20W
OUT
GPP_E12/USB2_OC3* XDP_USB_EXTD_OC_L IN 16 64 MF MF
B27 (IPD-RSMRST#) 2 01005 2 201
65 28 PCIE_CAMERA_D2R_N PCIE10_RXN F10
IN
D27 GPP_E4/DEVSLP0 XDP_JTAG_ISP_TCK 16 64
65 28 PCIE_CAMERA_D2R_P PCIE10_RXP H10
OUT
Camera IN
F27 GPP_E5/DEVSLP1 XDP_JTAG_ISP_TDI 16 64
28 PCIE_CAMERA_R2D_C_N PCIE10_TXN L8
OUT
OUT
H27 GPP_E6/DEVSLP2 TP_XDP_PCH_OBSDATA_A2 63
28 OUT
PCIE_CAMERA_R2D_C_P PCIE10_TXP
BI
R1610 1 A9 GPP_E0/SATAXPCIE0/SATAGP0 G11 TP_XDP_PCH_OBSDATA_D1 63

PCH_PCIE_RCOMP_N PCIE_RCOMPN
BI
100 B10 GPP_E1/SATAXPCIE1/SATAGP1 J11 TP_XDP_PCH_OBSDATA_D2 63
1% PCH_PCIE_RCOMP_P PCIE_RCOMPP
BI
1/20W PLACE_NEAR=U0500.B10:2.54mm GPP_E2/SATAXPCIE2/SATAGP2 N10 TP_XDP_PCH_OBSDATA_D3 BI 63
MF D51
201 2 TP_XDP_CPU_PRDY_L PROC_PRDY* (IPU)
GPP_E8/SATALED* H8
63 OUT
B55 TP_XDP_PCH_OBSDATA_B0 63
63 IN
TP_XDP_CPU_PREQ_L PROC_PREQ* (IPU)
BI
30 16 SMC_RUNTIME_SCI_L BF3 GPP_A7/PIRQA*

IN
CRITICAL
OMIT_TABLE
U0500
B SKL-Y-ULX
BGA
PP1V_SUS 9 13 19 48 50 61 B
SKL-Y PLACE_NEAR=U0500.P1:2.54mm
SYM 10 OF 20
1
R1662
CLOCK SIGNALS 2.7K
H35 1%
65 63 54 OUT
PCIE_CLK100M_SSD_N CLKOUT_PCIE_N1 CLKOUT_ITPXDP_N J34 TP_ITPXDP_CLK100MN 1/20W
MF
65 63 54 OUT
PCIE_CLK100M_SSD_P F35 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_P G34 TP_ITPXDP_CLK100MP 2 201
TBT_X_CLKREQ_L AV9 GPP_B6/SRCCLKREQ1* PPVRTC_G3H
GPD8/SUSCLK BA15
16 9 15 46 61
PM_CLK32K_SUSCLK_R OUT 31
PCIE_CLK100M_TEST_N J36 CLKOUT_PCIE_N2

XTAL24_IN M1
65
G36 SYSCLK_CLK24M_PCH 18 63 65
PCIE_CLK100M_TEST_P CLKOUT_PCIE_P2
IN
XTAL24_OUT L2 R1670 1 R1671
65
BD10 NC_PCH_CLK24M_XTALOUT 63
1
65 16 TEST_CLKREQ_L GPP_B7/SRCCLKREQ2*
OUT
20K 20K
J38 XCLK_BIASREF P1 PCH_DIFFCLK_BIASREF 1% 1%
TP_PCIE_CLK100M_TBT_BN CLKOUT_PCIE_N3 1/20W 1/20W
G38 MF MF
TP_PCIE_CLK100M_TBT_BP CLKOUT_PCIE_P3 RTCX1 BN19 SYSCLK_CLK32K_PCH IN 18 65 201 2 2 201
AP_CLKREQ_L AV5 GPP_B8/SRCCLKREQ3* RTCX2 BP18
65 25 16 IN NC
25 PCIE_CLK100M_AP_N H37 CLKOUT_PCIE_N4 SRTCRST* BH18 PCH_SRTCRST_L
OUT
25 PCIE_CLK100M_AP_P F37 CLKOUT_PCIE_P4 RTCRST* BN12 PCH_RTCRST_L
OUT
65 27 16 CAMERA_CLKREQ_L AV7 GPP_B9/SRCCLKREQ4*
IN
PCIE_CLK100M_CAMERA_N H39 CLKOUT_PCIE_N5

C1670 1 1 C1671
28 OUT
F39
1.0UF 1.0UF
PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 28 OUT
PCIE_CLK100M_CAMERA_P CLKOUT_PCIE_P5 20%
6.3V 2
20%
BC5 2 6.3V
PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 TP_PCH_CLKREQ5_L GPP_B10/SRCCLKREQ5* X5R
0201-1
X5R
0201-1
PP3V3_S0 5 6 14 15 17 19 23 26 27 31 33 BB10
34 35 39 46 50 51 53 61 67 59 16 IN
SSD_CLKREQ_L GPP_B5/SRCCLKREQ0*
R1611 100K 1 2
5% 1/32W MF 01005
SMC_RUNTIME_SCI_L 16 30
R1630 100K 1 2 XDP_USB_EXTA_OC_L 16 23 24 63 65
A R1631 100K 1 2
5% 1/32W MF 01005
USB_EXTB_OC_L 16 63 64
A
R1632 100K 1 2
5% 1/32W MF 01005
XDP_USB_EXTC_OC_L 16 64
SYNC_MASTER=DEVMLB SYNC_DATE=05/11/2015
R1633
PAGE TITLE
100K 5% 1/32W MF 01005
XDP_USB_EXTD_OC_L
1 2
5% 1/32W MF 01005
16 64
PCH PCIe/USB/CLK
R1640 100K 1 2 XDP_JTAG_ISP_TCK 16 64 DRAWING NUMBER SIZE
R1641 100K 1 2
5%
5%
1/32W
1/32W
MF
MF
01005
01005
XDP_JTAG_ISP_TDI 16 64
Apple Inc.
<SCH_NUM> D
R1650 47.0K 1 2 TBT_X_CLKREQ_L 16 R
REVISION
<E4LABEL>
R1651 47.0K 1 2
5% 1/32W MF 01005
TEST_CLKREQ_L 16 65
R1652 47.0K 1 2
5% 1/32W MF 01005
AP_CLKREQ_L 16 25 65
<BRANCH>
R1653 47.0K 1 2
5% 1/32W MF 01005
CAMERA_CLKREQ_L 16 27 65
R1655 47.0K 1 2
5%
5%
1/32W
1/32W
MF
MF
01005
01005
SSD_CLKREQ_L 16 59
PAGE
16 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
OMIT_TABLE
U0500
SKL-Y-ULX
BGA
SKL-Y
LPSS ISH
D 64 17 OUT
AUD_SPI_CS_L BC3 GPP_B15/GSPI0_CS*
SYM 6 OF 20
GPP_D9 P11 MLB_BOARD_ID4 17 D
64 17 AUD_SPI_CLK AW10 GPP_B16/GSPI0_CLK GPP_D10 T7 MLB_DEV_L 17
OUT
64 17 AUD_SPI_MISO AW6 GPP_B17/GSPI0_MISO GPP_D11 T5 PCH_BSSB_CLK 60
IN IN
64 17 AUD_SPI_MOSI BB4 GPP_B18/GSPI0_MOSI GPP_D12 T11 PCH_BSSB_DATA 60
OUT IN
(IPD-PLTRST#)
65 29 17 TPAD_SPI_CS_L BB2 GPP_B19/GSPI1_CS* GPP_D5/ISH_I2C0_SDA P7 MLB_BOARD_ID0 17
OUT
29 17 TPAD_SPI_CLK AW12 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL P5 MLB_BOARD_ID1 17
OUT
TPAD_SPI_MISO AW4 GPP_B21/GSPI1_MISO
GPP_D7/ISH_I2C1_SDA T9
29 17 IN
AW8 MLB_BOARD_ID2 17
TPAD_SPI_MOSI GPP_B22/GSPI1_MOSI
GPP_D8/ISH_I2C1_SCL T3
29 17 OUT
(IPD-PLTRST#) MLB_BOARD_ID3 17
PCH_BT_UART_D2R AC8 GPP_C8/UART0_RXD

GPP_F10/I2C5_SDA/ISH_I2C2_SDA AM7
65 26 17 IN
AA8 TP_PCH_GPP_F10
PCH_BT_UART_R2D GPP_C9/UART0_TXD
GPP_F11/I2C5_SCL/ISH_I2C2_SCL AT9
65 26 17 OUT
AA10 TP_PCH_GPP_F11
65 26 17 OUT
PCH_BT_UART_RTS_L GPP_C10/UART0_RTS*
65 26 17 PCH_BT_UART_CTS_L AA12 GPP_C11/UART0_CTS* GPP_D13/ISH_UART0_RXD/SML0BDATA U10 MLB_RAMCFG0 17
IN
GPP_D14/ISH_UART0_TXD/SML0BCLK U4 MLB_RAMCFG1
SSD_UART_D2R AD5 GPP_C20/UART2_RXD
17
65 63 17 IN
GPP_D15/ISH_UART0_RTS* U6 MLB_RAMCFG2
SSD_UART_R2D AD7 GPP_C21/UART2_TXD
17
65 63 17 OUT
GPP_D16/ISH_UART0_CTS* V9 MLB_RAMCFG3
LCD_PSR_EN AD3 GPP_C22/UART2_RTS*
17
64 17 OUT /SML0BALERT*
17 SSD_UART_CTS_L AD9 GPP_C23/UART2_CTS* GPP_C12/UART1_RXD/ISH_UART1_RXD AC6 SOC_UART_D2R 17 64
IN
GPP_C13/UART1_TXD/ISH_UART1_TXD AC4 SOC_UART_R2D
AP_S0IX_WAKE_SEL AD11 GPP_C16/I2C0_SDA
OUT 17 64
65 18 17 OUT
GPP_C14/UART1_RTS*/ISH_UART1_RTS* AB7 SOC_UART_RTS_L
AP_S0IX_WAKE_L AB3 GPP_C17/I2C0_SCL
OUT 17 64
65 18 17 IN
GPP_C15/UART1_CTS*/ISH_UART1_CTS* AB5 SOC_UART_CTS_L 17 64
IN
TBT_X_PLUG_EVENT_L AB9 GPP_C18/I2C1_SDA
64 17 IN
GPP_A18/ISH_GP0 BF11 SPIROM_USE_MLB
TBT_T_PLUG_EVENT_L AB11 GPP_C19/I2C1_SCL
BI 17 36
64 17 IN
GPP_A19/ISH_GP1 BD2 LCD_IRQ_L 17 53 65
IN
33 24 I2C_UPC_SDA AP3 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BJ1 TP_TBT_X_DPMUX_SEL
BI
33 24 I2C_UPC_SCL AP7 GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 BL3 TP_TBT_T_DPMUX_SEL
OUT
GPP_A22/ISH_GP4 BJ3 TPAD_SPI_IF_EN
UPC_I2C_INT_L AP5 GPP_F6/I2C3_SDA
OUT 17 29 65
33 24 IN BD4 TPAD_SPI_INT_L
C 65 54 17 OUT
SSD_BOOT_L AT7 GPP_F7/I2C3_SCL
GPP_A23/ISH_GP5
SX_EXIT_HOLDOFF/GPP_A12 BJ4 AUD_PWR_EN OUT
IN 17 29 65
17 39 65
C
TP_PCH_GPP_F8 AN4 GPP_F8/I2C4_SDA
/BM_BUSY*/ISH_GP6
TP_PCH_GPP_F9 AN6 GPP_F9/I2C4_SCL
CRITICAL
OMIT_TABLE
U0500
SKL-Y-ULX
BGA
SKL-Y
H29 SYM 9 OF 20 H31
NC CSI2_DN0 CSI2_CLKN0 NC
F29 CSI2_DP0 CSI2_CLKP0 F31
NC NC
F33 CSI2_DN1 CSI2_CLKN1 D31
NC NC
H33 CSI2_DP1 CSI2_CLKP1 B31
NC NC
J30 CSI2_DN2 CSI-2 CSI2_CLKN2 C34
NC NC
G30 CSI2_DP2 CSI2_CLKP2 A34
NC NC
J32 CSI2_DN3 CSI2_CLKN3 D39
NC NC
G32 CSI2_DP3 CSI2_CLKP3 B39
NC NC
CSI2_COMP A11 PCH_CSI2_COMP
D29 CSI2_DN4
NC GPP_D4/FLASHTRIG N4 TP_PCH_GPP_D4 CSI2
B29 CSI2_DP4
NC
NC
C32 CSI2_DN5
1
R1782
A32 AN12 PCH_SWD_IO 100
NC CSI2_DP5 GPP_F13/EMMC_DATA0 OUT 17 64 1%
C30 AP9 1/20W
CSI2_DN6 GPP_F14/EMMC_DATA1 PCH_SWD_MUX_SEL MF
B NC
B
OUT 17 64
A30 CSI2_DP6 GPP_F15/EMMC_DATA2 AN10 SOC_WAKE_L 2 201
NC OUT 17 64
D33 CSI2_DN7 GPP_F16/EMMC_DATA3 AJ10 TP_PCH_GPP_F16
NC
B33 CSI2_DP7 GPP_F17/EMMC_DATA4 AM9 TP_PCH_GPP_F17
NC PP3V3_SUS
GPP_F18/EMMC_DATA5 AL12 TP_PCH_GPP_F18 61 50 49 46 36 16 14 13 9
D35 PP1V8_SUS
EMMC
NC CSI2_DN8 AJ12 61 50 48 33 24 17 13 9
B35 GPP_F19/EMMC_DATA6 TP_PCH_GPP_F19
NC CSI2_DP8 AN8
67
27 26 23 19 17 16 15 14 6 5 PP3V3_S0
C36 GPP_F20/EMMC_DATA7 TP_PCH_GPP_F20 61 53 51 50 46 39 35 34 33 31
NC CSI2_DN9
A36 CSI2_DP9 GPP_F21/EMMC_RCLK AL10 TP_PCH_GPP_F21 MLB_DEV
NC
NC
D37 CSI2_DN10 GPP_F22/EMMC_CLK AL8 TP_PCH_GPP_F22 17 MLB_DEV_L R1750 1.00K 1 2
NC
B37 CSI2_DP10 GPP_F12/EMMC_CMD AM11 PCH_SWD_CLK OUT 17 64 64 17 SOC_UART_D2R R1770 47.0K 1 2
5% 1/32W MF 01005
NC
C38 CSI2_DN11
EMMC_RCOMP BC1 PCH_EMMC_RCOMP 64 17 SOC_UART_R2D R1771 47.0K 1 2
5% 1/32W MF 01005
PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31
NC
A38 CSI2_DP11
EMMC
64 17 SOC_UART_RTS_L R1772 47.0K 1 2
5% 1/32W MF 01005
PP1V8_SUS
33 34 35 39 46 50 51 53 61 67
SOC_UART_CTS_L R1773 47.0K 1 2
5% 1/32W MF 01005
R1795
9 13 17 24 33 48 50 61 64 17
1 5% 1/32W MF 01005
R1700 47.0K 1 2 AUD_SPI_CS_L 200 36 17 SPIROM_USE_MLB R1774 100K 1 2
R1701 47.0K 1 2
5% 1/32W MF 01005
AUD_SPI_CLK
17 64 1%
1/20W 65 53 17 LCD_IRQ_L R1775 100K 1 2
5% 1/32W MF 01005
R1702 47.0K 1 2
5% 1/32W MF 01005
AUD_SPI_MISO
17 64 MF
2 201 65 29 17 TPAD_SPI_IF_EN R1778 100K 1 2
5% 1/32W MF 01005
R1703 1.00K 1 2
5% 1/32W MF 01005
AUD_SPI_MOSI
17 64
65 29 17 TPAD_SPI_INT_L R1779 100K 1 2
5% 1/32W MF 01005
5% 1/32W MF 01005
17 64
65 39 17 AUD_PWR_EN R1780 100K 1 2
5% 1/32W MF 01005
R1705 47.0K 1 2 TPAD_SPI_CS_L 17 29 65 64 17 PCH_SWD_IO R1784 100K 1 2

5% 1/32W MF 01005
R1706 47.0K 1 2
5% 1/32W MF 01005
TPAD_SPI_CLK 17 29 64 17 PCH_SWD_MUX_SEL R1785 100K 1 2
5% 1/32W MF 01005
R1707 47.0K 1 2
5% 1/32W MF 01005
TPAD_SPI_MISO 17 29 64 17 SOC_WAKE_L R1786 100K 1 2
5% 1/32W MF 01005
R1708 150K 1 2
5%
5%
1/32W
1/20W
MF
MF
01005
201
TPAD_SPI_MOSI 17 29 64 17 PCH_SWD_CLK R1794 100K 1 2
5%
5%
1/32W
1/32W
MF
MF
01005
01005
R1710 47.0K 1 2 PCH_BT_UART_D2R 17 26 65 Board ID Straps RAM Configuration Straps
R1711 47.0K 1 2
5% 1/32W MF 01005
PCH_BT_UART_R2D 17 26 65
MLB_BOARD_ID0 MLB_RAMCFG0
R1712 47.0K 1 2
5% 1/32W MF 01005
PCH_BT_UART_RTS_L 17 26 65
17
MLB_BOARD_ID1
17
MLB_RAMCFG1
A R1713 47.0K 1 2
5%
5%
1/32W
1/32W
MF
MF
01005
01005
PCH_BT_UART_CTS_L 17 26 65
17
17 MLB_BOARD_ID2
17
17 MLB_RAMCFG2 SYNC_MASTER=DEVMLB SYNC_DATE=05/11/2015 A

R1715 47.0K 1 2 SSD_UART_D2R 17 63 65 17 MLB_BOARD_ID3 17 MLB_RAMCFG3 PAGE TITLE
R1716 47.0K 1 2
5% 1/32W MF 01005
SSD_UART_R2D 17 63 65 17 MLB_BOARD_ID4 14 MLB_RAMCFG4 PCH GPIO/LPSS
R1717 100K 1 2
5% 1/32W MF 01005
LCD_PSR_EN 17 64 BOARDID4_L BOARDID3_L BOARDID2_L BOARDID1_L BOARDID0_L RAMCFG4_L RAMCFG3_L RAMCFG2_L RAMCFG1_L RAMCFG0_L DRAWING NUMBER SIZE
R1718 47.0K 1 2
5%
5%
1/32W
1/32W
MF
MF
01005
01005
SSD_UART_CTS_L 17 R1759 1
R1758 1
R1757 1
R1756 1
R1755 1
R1769 1
R1768 1
R1767 1
R1766 1
R1765 1
Apple Inc.
<SCH_NUM> D
R1720 100K 1 2 AP_S0IX_WAKE_SEL 1.00K 1.00K 1.00K 1.00K 1.00K 1.00K 1.00K 1.00K 1.00K 1.00K REVISION
5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
R1721 100K 1 2
5% 1/32W MF 01005
AP_S0IX_WAKE_L
17 18 65
17 18 65
1/32W
MF
1/32W
MF
1/32W
MF
1/32W
MF
1/32W
MF
1/32W
MF
1/32W
MF
1/32W
MF
1/32W
MF
1/32W
MF
R
<E4LABEL>
R1722 100K 1 2
5% 1/32W MF 01005
TBT_X_PLUG_EVENT_L 17 64
01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005 2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
<BRANCH>
R1723 100K 1 2
5% 1/32W MF 01005
TBT_T_PLUG_EVENT_L 17 64
R1727 100K 1 2
5%
5%
1/32W
1/32W
MF
MF
01005
01005
SSD_BOOT_L 17 54 65
PAGE
17 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
System 32kHz / 12MHz / 24MHz Clock Generator
D
61 41 40 36 33 31 30 29 23 PP3V3_G3H
BYPASS=U1900.11:18:5MM
D
1 C1901
1.0UF
20%
2 6.3V
X5R
61 59 50 46 31 29 26 25 24 15 PP3V3_S4 0201-1
19 PP1V_SUSRS0SW_PCHCLK
VRTC 11
VDD 1
27 PP1V2_CAM_XTALPCIEVDD PP2V9_SYSCLK
VOLTAGE=2.9V BYPASS=U1900.17:18:5MM
PP1V8_S0SW_SSD_COLD
61 59 58 57 55 54
BYPASS=U1900.12:18:5MM
MIN_NECK_WIDTH=0.1000 1 C1900
BYPASS=U1900.02:18:5MM 2.2UF
BYPASS=U1900.05:18:5MM 20%
BYPASS=U1900.15:18:5MM 2 6.3V
X5R-CERM
C1903 1 C1904 1 C1905 1 C1906 1 U1900 0201
PCH ME Disable Strap
0.1UF 0.1UF 0.1UF 0.1UF SLG3AP3430
10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V STQFN
CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 12 VOUT 17
0201 0201 0201 0201 VIO_32K_B
2 VIOE_24M_A SPI_DESCRIPTOR_OVERRIDE_L
32.768K_A 10
IN 30
5
SYSCLK_CLK32K_PCH 16 65
VIOE_24M_B
15 32.768K_B 13 SYSCLK_CLK32K_CAMERA_BT_AP 25 65
VIOE_24M_C
1
8 24M_A 3
C1907 R1900
30 IN
SMC_CLK12M_EN OE_12M SYSCLK_CLK24M_PCH 16 63 65
G
9.5PF 24M_B 6 SYSCLK_CLK24M_CAMERA 27 65
2 1 0 19
SYSCLK_CLK24M_X2 1 2 SYSCLK_CLK24M_X2_R X2 24M_C 16 SYSCLK_CLK24M_SSD 54 65
5% NO STUFF 20 X1
+/-0.1PF 12M 7 SYSCLK_CLK12M_SMC PP1V5_S0 SPI_DESCRIPTOR_OVERRIDE
D
S
1/20W
1
R1901
30 65 61 49 46 39 13 IN
50V MF
CER-C0G GND
3
0201
0201 1M
5% 1
R1930
14
18
1/20W
4
9
1K
CRITICAL
MF
2 201 Q1930 5%
1
Y1900 DMP31D0UFB4
1/20W
MF
2
C 24MHZ-10PPM-8PF-40OHM DFN1006H4-3 2 201

C
4
2.5X2.0MM-SM
HDA_SDOUT_R
3
C1908 OUT 14
PCH IPD = 9-50k

9.5PF
1 2 SYSCLK_CLK24M_X1
+/-0.1PF PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
50V
CER-C0G NOTE: 30 PPM or better required for SKL PCH If high, ME is disabled. This allows for full re-flashing of SPI ROM.
0201
SMC controls strap enable to allow in-field control of strap setting.
***** Circuit does not support HDA voltage >3.3V.
PCIe Wake Muxing

60 59 50 49 48 46 45 15 13 9
67 61
PP3V3_S5 AP_S0IX_WAKE_SEL IN 17 65
SEL OUTPUT
CRITICAL
L PCIE_WAKE_L (B0)
C1910 1
U1910
1
R1910 0.1UF
10%
PI5A3157B H AP_S0IX_WAKE_L (B1)
100K 6.3V 6 SEL DFN
B1 2 AP_S0IX_WAKE_L
5%
1/20W CERM-X5R 2 OUT 17 65
MF 0201
1
2 201
B 1 VCC GND 5
B
0
65 25 AP_PCIE_WAKE_L 3 A B0 4 PCIE_WAKE_L 15
IN OUT
VER 1
A SYNC_MASTER=X260_ERIC SYNC_DATE=06/09/2015 A
PAGE TITLE
Chipset Support 1
DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
19 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Platform Reset Connections

Unbuffered
DP DDP Straps
65 30 26 19 15 14 5 IN
PLT_RST_L PLT_RST_L OUT 5 14 15 19 26 30 65
MAKE_BASE=TRUE
67
27 26 23 19 17 16 15 14 6 5
61 53 51 50 46 39 35 34 33 31
PP3V3_S0
R2000 1
2.2K
D
5%
1/20W
MF
D
201 2
5 PCH_DDPB_CTRLDATA
PCH 24MHz VIOE Options

PCH24M:SUS
61 50 48 16 13 9 PP1V_SUS R2050
1
0.00 2 PP1V_SUSRS0SW_PCHCLK 18 19
0%
1/32W PP1V_SUSRS0SW_PCHCLK 18 19
MF VOLTAGE=1.0V
01005 MIN_LINE_WIDTH=0.2000
MAKE_BASE=TRUE
HPD S0 Isolation
PCH24M:S0SW
R2051 PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31
PP1V_S0SW_PCHCLK 0.00 33 34 35 39 46 50 51 53 61 67
1 2 CRITICAL
2
3
VOLTAGE=1.0V
U2020
D
S
MIN_LINE_WIDTH=0.2000 0%
MIN_NECK_WIDTH=0.1000 1/32W
MF
74AUP1G08GX
SYM_VER_3 SOT1226
01005
5
PM_SLP_S0S3_L
G
DFN1006H4-3
B 1
46 50 51 63
DMN32D2LFB4 IN
4
DP_XA_HPD 23 24 60
DP_DDI1_HPD IN
Q2050 A 2
1
5 OUT
CRITICAL
BYPASS=U2020::5MM
3
C2020 1 1
R2021
0.1UF 100K
10% 5%
10V
X5R-CERM 2 1/20W
MF
0201
2 201
C C
B B
LPDDR3 Alias Support

21 20 19 PPVREF_S3_MEM_VREFDQ_A PPVREF_S3_MEM_VREFDQ_A 19 20 21
MAKE_BASE=TRUE VOLTAGE=0.6V
22 20 19 PPVREF_S3_MEM_VREFDQ_B PPVREF_S3_MEM_VREFDQ_B 19 20 22
22 21 20 19 PPVREF_S3_MEM_VREFCA PPVREF_S3_MEM_VREFCA 19 20 21 22
PPVREF_S3_MEM_VREFCA 19 20 21 22
PAGE TITLE
Project Chipset Support

DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
20 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
CPU-Based Margining
PP1V2_S3 8 12 21 22 47 50 61
VRef Dividers 1
R2221
8.2K
1%
1/20W
MF
R2223 2 201
CPU_DIMMA_VREFDQ 1
10 2 PPVREF_S3_MEM_VREFDQ_A
7 IN 19 21
1% PLACE_NEAR=R2221.2:1mm MIN_NECK_WIDTH=0.2000
1/20W
MF
201 R2222 1
8.2K
1%
C 1 C2220
0.022UF
1/20W
MF
201 2
C
10%
2 6.3V
X5R-CERM
0201 R2220
MEM_VREFDQ_A_RC 1
24.9 2
1
R2241
1%
8.2K
1%
1/20W 1/20W
MF MF
R2243 201
2 201
CPU_DIMMB_VREFDQ 1
10 2 PPVREF_S3_MEM_VREFDQ_B
7 IN 19 22
1/20W
MF
201 R2242 1
8.2K
1%
1 C2240 1/20W
MF
201 2
0.022UF
10%
2 6.3V
X5R-CERM
0201 R2240
MEM_VREFDQ_B_RC 1
24.9 2
1
R2261
1%
8.2K
1%
1/20W 1/20W
MF MF
R2263 201
2 201
CPU_DIMM_VREFCA 1
5.1 2 PPVREF_S3_MEM_VREFCA
7 IN 19 21 22
1/20W
MF
0201 R2262 1
8.2K
1%
1 C2260 1/20W
MF
201 2
B 0.022UF
10%
2 6.3V
B
X5R-CERM
0201 R2260
MEM_VREFCA_A_RC 1
24.9 2
1%
1/20W
MF
201
PAGE TITLE
LPDDR3 VREF MARGINING

DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
22 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL PP1V8_S3 BYPASS=U2300.A15::5mm CRITICAL

61 50 49 46 22 BYPASS=U2300.R1::5mm
B5 L2 BYPASS=U2300.A16::5mm R1 B1
7 IN
MEM_A_CAB<0> CA0_A OMIT_TABLE CA0_B MEM_A_CAA<0> IN 7 65 VDD1_A/B OMIT_TABLE VSS_A/B
7 IN
MEM_A_CAB<1> C5 CA1_A U2300 CA1_B L3 MEM_A_CAA<1> IN 7
T1 VDD1_A/B U2300 VSS_A/B C1
7 IN
MEM_A_CAB<2> D5 CA2_A BGA CA2_B L4 MEM_A_CAA<2> IN 7 C2340 1 C2341 1 1 C2342 1 C2343 B2 VDD1_A/B BGA VSS_A/B D1
7 MEM_A_CAB<3> B6 CA3_A SYM 1 OF 2 CA3_B K2 MEM_A_CAA<3> 7
10UF 10UF 10UF 10UF A15 VDD1_A/B SYM 2 OF 2 VSS_A/B F1
IN IN 20% 20% 20% 20%
MEM_A_CAB<4> C6 K3 MEM_A_CAA<4> 6.3V 2 6.3V 2 2 6.3V 2 6.3V A16 G1
ELPIDA
32GB-LPDDR3X64
ELPIDA
32GB-LPDDR3X64
CA4_A CA4_B VDD1_A/B VSS_A/B
D
7 IN IN 7 CERM-X5R CERM-X5R CERM-X5R CERM-X5R
D 7
7
IN
MEM_A_CAB<5>
MEM_A_CAB<6>
C9
D9
CA5_A
CA6_A
CA5_B
CA6_B
G3
G4
MEM_A_CAA<5>
MEM_A_CAA<6>
IN 7
7
0402-2 0402-2 0402-2
BYPASS=U2300.T1::5mm
0402-2 T16 VDD1_A/B VSS_A/B
VSS_A/B
M1
P1
IN IN
7 MEM_A_CAB<7> B10 CA7_A CA7_B F2 MEM_A_CAA<7> 7 VSS_A/B A2
IN IN
7 MEM_A_CAB<8> C10 CA8_A CA8_B F3 MEM_A_CAA<8> 7 VSS_A/B C2
IN IN
7 MEM_A_CAB<9> D10 CA9_A CA9_B F4 MEM_A_CAA<9> 7 VSS_A/B D2
IN IN
VSS_A/B A3
7 MEM_A_CLK_P<1> B8 CK_T_A CK_T_B H3 MEM_A_CLK_P<0> 7 65 VSS_A/B B3
IN IN
C8 BYPASS=U2300.B17::5mm D3
7 MEM_A_CLK_N<1> CK_C_A CK_C_B H2 MEM_A_CLK_N<0> 7 65 BYPASS=U2300.U2::5mm VSS_A/B
IN IN
61 50 47 22 21 20 12 8 PP1V2_S3 BYPASS=U2300.A11::5mm A4
BYPASS=U2300.R15::5mm H1 VSS_A/B
D6 VDD2_A/B B4
65 21 7 IN
MEM_A_CS_L<0> CS0_A* CS0_B* K4 MEM_A_CS_L<0> 7 21 65
L1 VSS_A/B
B7 VDD2_A/B C4
MEM_A_CS_L<1> CS1_A* CS1_B* J2 MEM_A_CS_L<1> VSS_A/B
21 7 IN 7 21
C2350 1 C2351 1 1 C2352 1 C2353 U2 VDD2_A/B
VSS_A/B D4
10UF 10UF 10UF 10UF C3 VDD2_A/B M4
MEM_A_CKE<2> C7 CKE0_A CKE0_B J3 MEM_A_CKE<0> 20% 20% 20% 20% VSS_A/B
7 IN IN 7 6.3V 6.3V 2 6.3V 2 6.3V U3 VDD2_A/B
D7 CERM-X5R 2 CERM-X5R 2 U4
7 IN
MEM_A_CKE<3> CKE1_A CKE1_B J4 MEM_A_CKE<1> IN 7 0402-2 0402-2
CERM-X5R
0402-2
CERM-X5R
0402-2 R15 VSS_A/B
VDD2_A/B A5
H16 VSS_A/B
N8 VDD2_A/B E5
21 7 IN
MEM_A_ODT<0> ODT_A ODT_B H13 MEM_A_ODT<0> 7 21
B17 VSS_A/B
VDD2_A/B F5
C17 VSS_A/B
N6 H14 VDD2_A/B G5
DM0_A DM0_B A7 VSS_A/B
P8 F13 VDD2_A/B H5
DM1_A DM1_B T8 VSS_A/B
P4 L14 VDD2_A/B J5
P11 D14 VDD2_A/B K5
DM3_A DM3_B VSS_A/B
VSS_A/B L5
62 7 MEM_A_DQ<6> N4 DQ0_A DQ0_B L15 MEM_A_DQ<39> 7 62 VSS_A/B M5
IN BI
62 7 MEM_A_DQ<7> T5 DQ1_A DQ1_B L16 MEM_A_DQ<37> 7 62 VSS_A/B A12
BI BI
62 7 MEM_A_DQ<2> R5 DQ2_A DQ2_B K13 MEM_A_DQ<33> 7 62 VSS_A/B D12
BI BI
62 7 MEM_A_DQ<3> P5 DQ3_A DQ3_B K14 MEM_A_DQ<36> 7 62 VSS_A/B E12
BI BI
MEM_A_DQ<1> N5 K15 MEM_A_DQ<38> F12
C 62 7
62 7
BI
MEM_A_DQ<4> T6
DQ4_A
DQ5_A
DQ4_B
DQ5_B K16 MEM_A_DQ<34>
BI 7 62
7 62 BYPASS=U2300.A9::5mm
VSS_A/B
VSS_A/B H12 C
BI BI PP1V2_S3
DDR B
DDR A
R6 J15 61 50 47 22 21 20 12 8 BYPASS=U2300.G2::5mm L12
62 7 BI
MEM_A_DQ<5> DQ6_A DQ6_B MEM_A_DQ<32> BI 7 62 BYPASS=U2300.E1::5mm A6 VSS_A/B
P6 J16 VDDCA_A/B U12
62 7 BI
MEM_A_DQ<0> DQ7_A DQ7_B MEM_A_DQ<35> BI 7 62
E1 VSS_A/B
T9 F14 VDDCA_A/B N13
MEM_A_DQ<8> DQ8_A DQ8_B MEM_A_DQ<47> VSS_A/B
62 7 BI
MEM_A_DQ<12> R9 DQ9_A DQ9_B F15 MEM_A_DQ<46>
BI 7 62
C2370 1 C2371 1 C2372 1 K1 VDDCA_A/B
VSS_A/B U13
62 7 BI BI 7 62
10UF 10UF 10UF G2 VDDCA_A/B A14
MEM_A_DQ<9> T10 DQ10_A DQ10_B F16 MEM_A_DQ<42> 20% 20% 20% VSS_A/B
62 7 BI BI 7 62 6.3V 6.3V 6.3V A9 VDDCA_A/B
MEM_A_DQ<14> R10 DQ11_B E13 MEM_A_DQ<41> CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 VSS_A/B P14
62 7 BI DQ11_A BI 7 62 0402-2 0402-2 0402-2 B9
P10 E14 VDDCA_A/B G15
62 7 BI
MEM_A_DQ<11> DQ12_A DQ12_B MEM_A_DQ<43> BI 7 62 VSS_A/B
62 7 MEM_A_DQ<15> N10 DQ13_A DQ13_B E15 MEM_A_DQ<45> 7 62 VSS_A/B H15
BI BI
62 7 MEM_A_DQ<13> T11 DQ14_A DQ14_B E16 MEM_A_DQ<40> 7 62 VSS_A/B T15
BI BI
62 7 MEM_A_DQ<10> R11 DQ15_A DQ15_B D13 MEM_A_DQ<44> 7 62 VSS_A/B U15
BI BI
62 7 MEM_A_DQ<20> T2 DQ16_A DQ16_B P15 MEM_A_DQ<52> 7 62 VSS_A/B G16
BI BI
62 7 MEM_A_DQ<19> R2 DQ17_A DQ17_B P16 MEM_A_DQ<51> 7 62 VSS_A/B R16
BI BI
62 7 MEM_A_DQ<16> P2 DQ18_A DQ18_B N14 MEM_A_DQ<55> 7 62 VSS_A/B U16
BI BI
N2 N15 BYPASS=U2300.A13::5mm D17
62 7 BI
MEM_A_DQ<17> DQ19_A DQ19_B MEM_A_DQ<54> BI 7 62 61 50 47 22 21 20 12 8 PP1V2_S3 VSS_A/B
62 7 MEM_A_DQ<22> T3 DQ20_A DQ20_B N16 MEM_A_DQ<53> 7 62
N1 VDDQ_A/B VSS_A/B F17
BI BI
62 7 MEM_A_DQ<18> R3 DQ21_A DQ21_B M13 MEM_A_DQ<48> 7 62
M2 VDDQ_A/B VSS_A/B J17
BI BI
62 7 BI
MEM_A_DQ<21> P3 DQ22_A DQ22_B M14 MEM_A_DQ<50> BI 7 62 C2380 1 M3 VDDQ_A/B VSS_A/B M17
62 7 MEM_A_DQ<23> N3 DQ23_A DQ23_B L13 MEM_A_DQ<49> 7 62
10UF U5 VDDQ_A/B VSS_A/B N17
BI BI 20%
MEM_A_DQ<24> N11 DQ24_A DQ24_B C13 MEM_A_DQ<57> 6.3V B12 VDDQ_A/B VSS_A/B R17
62 7 BI BI 7 62 CERM-X5R 2
62 7 MEM_A_DQ<30> N12 DQ25_A DQ25_B C14 MEM_A_DQ<62> 7 62
0402-2 C12 VDDQ_A/B VSS_A/B T17
BI BI
62 7 MEM_A_DQ<27> P12 DQ26_A DQ26_B C15 MEM_A_DQ<60> 7 62
G12 VDDQ_A/B VSS_A/B E6
BI BI
62 7 MEM_A_DQ<26> T13 DQ27_A DQ27_B C16 MEM_A_DQ<63> 7 62
K12 VDDQ_A/B VSS_A/B M6
BI BI
R13 B13 BYPASS=U2300.K17::5mm M12 U6
62 7 BI
MEM_A_DQ<28> DQ28_A DQ28_B MEM_A_DQ<59> BI 7 62 VDDQ_A/B VSS_A/B
62 7 MEM_A_DQ<31> P13 DQ29_A DQ29_B B14 MEM_A_DQ<56> 7 62
A13 VDDQ_A/B VSS_A/B E7
BI BI
MEM_A_DQ<25> T14 DQ30_A DQ30_B B15 MEM_A_DQ<61> U14 VDDQ_A/B VSS_A/B R7
B
62 7 BI
MEM_A_DQ<29> R14 DQ31_A DQ31_B B16 MEM_A_DQ<58>
BI 7 62
C2385 1
E17 VDDQ_A/B VSS_A/B T7 B
62 7 BI BI 7 62
10UF G17 A8
20% VDDQ_A/B VSS_A/B
6.3V 2
62 7 MEM_A_DQS_P<0> P7 DQS0_T_A DQS0_T_B J14 MEM_A_DQS_P<4> 7 62
CERM-X5R K17 VDDQ_A/B VSS_A/B E8
BI BI 0402-2
62 7 MEM_A_DQS_N<0> N7 DQS0_C_A DQS0_C_B J13 MEM_A_DQS_N<4> 7 62
L17 VDDQ_A/B VSS_A/B M8
BI BI
P17 VDDQ_A/B VSS_A/B R8
65 62 7 MEM_A_DQS_P<1> P9 DQS1_T_A DQS1_T_B G14 MEM_A_DQS_P<5> 7 62 BYPASS=U2300.U10::5mm M7 VDDQ_A/B VSS_A/B E9
BI BI
65 62 7 MEM_A_DQS_N<1> N9 DQS1_C_A DQS1_C_B G13 MEM_A_DQS_N<5> 7 62
U7 VDDQ_A/B VSS_A/B U9
BI BI
M10 VDDQ_A/B VSS_A/B E10
62 7 BI
MEM_A_DQS_P<2> T4 DQS2_T_A DQS2_T_B M16 MEM_A_DQS_P<6> BI 7 62 C2390 1 U10 VDDQ_A/B VSS_A/B E11
62 7 MEM_A_DQS_N<2> R4 DQS2_C_A DQS2_C_B M15 MEM_A_DQS_N<6> 7 62
10UF U11 VDDQ_A/B VSS_A/B M11
BI BI 20%
6.3V
CERM-X5R 2
62 7 MEM_A_DQS_P<3> T12 DQS3_T_A DQS3_T_B D16 MEM_A_DQS_P<7> 7 62
0402-2
BI BI
62 7 MEM_A_DQS_N<3> R12 DQS3_C_A DQS3_C_B D15 MEM_A_DQS_N<7> 7 62
BI BI
MEM_A_ZQ_B B11 ZQ_A ZQ_B E2 MEM_A_ZQ_A
22 21 20 19 PPVREF_S3_MEM_VREFCA A10 VREFCA_A VREFCA_B J1 PPVREF_S3_MEM_VREFCA 19 20 21 22
21 20 19 PPVREF_S3_MEM_VREFDQ_A U8 VREFDQ_A VREFDQ_B H17 PPVREF_S3_MEM_VREFDQ_A 19 20 21
R2300 1 C2310 1 1 C2311 NC

A1 NC NC A17
NC C2331 1 1 C2330 1
R2320
243 0.047UF 0.047UF U1 NC NC U17 0.047UF 0.047UF 243
1% 10% 10% NC NC 10% 10% 1%
1/20W 6.3V 2 2 6.3V E3 NC NC D8 6.3V 2 2 6.3V 1/20W
MF X5R X5R NC NC X5R X5R MF
201 2 201 201 E4 NC NC M9 201 201
NC NC 2 201
H4 NC NC C11
NC NC
J12 NC NC D11
NC NC
PAGE TITLE
LPDDR3 DRAM Channel A (0-63)

DRAWING NUMBER SIZE
<SCH_NUM> D
Apple Inc.
REVISION
R
<E4LABEL>
THE INFORMATION CONTAINED HEREIN IS THE <BRANCH>

23 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL PP1V8_S3 BYPASS=U2500.A15::5mm CRITICAL

61 50 49 46 21 BYPASS=U2500.R1::5mm
B5 L2 BYPASS=U2500.A16::5mm R1 B1
7 IN
MEM_B_CAB<0> CA0_A OMIT_TABLE CA0_B MEM_B_CAA<0> IN 7 VDD1_A/B OMIT_TABLE VSS_A/B
65 7 IN
MEM_B_CAB<1> C5 CA1_A U2500 CA1_B L3 MEM_B_CAA<1> IN 7
T1 VDD1_A/B U2500 VSS_A/B C1
7 IN
MEM_B_CAB<2> D5 CA2_A BGA CA2_B L4 MEM_B_CAA<2> IN 7 65 C2540 1 C2541 1 1 C2542 1 C2543 B2 VDD1_A/B BGA VSS_A/B D1
7 MEM_B_CAB<3> B6 CA3_A SYM 1 OF 2 CA3_B K2 MEM_B_CAA<3> 7 65
10UF 10UF 10UF 10UF A15 VDD1_A/B SYM 2 OF 2 VSS_A/B F1
IN IN 20% 20% 20% 20%
MEM_B_CAB<4> C6 K3 MEM_B_CAA<4> 6.3V 2 6.3V 2 2 6.3V 2 6.3V A16 G1
ELPIDA
32GB-LPDDR3X64
ELPIDA
32GB-LPDDR3X64
CA4_A CA4_B VDD1_A/B VSS_A/B
D
7 IN IN 7 CERM-X5R CERM-X5R CERM-X5R CERM-X5R
D 7
7
IN
MEM_B_CAB<5>
MEM_B_CAB<6>
C9
D9
CA5_A
CA6_A
CA5_B
CA6_B
G3
G4
MEM_B_CAA<5>
MEM_B_CAA<6>
IN 7
7
0402-2 0402-2 0402-2
BYPASS=U2500.T1::5mm
0402-2 T16 VDD1_A/B VSS_A/B
VSS_A/B
M1
P1
IN IN
7 MEM_B_CAB<7> B10 CA7_A CA7_B F2 MEM_B_CAA<7> 7 VSS_A/B A2
IN IN
7 MEM_B_CAB<8> C10 CA8_A CA8_B F3 MEM_B_CAA<8> 7 VSS_A/B C2
IN IN
7 MEM_B_CAB<9> D10 CA9_A CA9_B F4 MEM_B_CAA<9> 7 VSS_A/B D2
IN IN
VSS_A/B A3
7 MEM_B_CLK_P<1> B8 CK_T_A CK_T_B H3 MEM_B_CLK_P<0> 7 VSS_A/B B3
IN IN
C8 BYPASS=U2500.B17::5mm D3
7 MEM_B_CLK_N<1> CK_C_A CK_C_B H2 MEM_B_CLK_N<0> 7 BYPASS=U2500.U2::5mm VSS_A/B
IN IN
61 50 47 22 21 20 12 8 PP1V2_S3 BYPASS=U2500.A11::5mm A4
BYPASS=U2500.R15::5mm H1 VSS_A/B
D6 VDD2_A/B B4
22 7 IN
MEM_B_CS_L<0> CS0_A* CS0_B* K4 MEM_B_CS_L<0> 7 22
L1 VSS_A/B
B7 VDD2_A/B C4
MEM_B_CS_L<1> CS1_A* CS1_B* J2 MEM_B_CS_L<1> VSS_A/B
65 22 7 IN 7 22 65
C2550 1 C2551 1 1 C2552 1 C2553 U2 VDD2_A/B
VSS_A/B D4
10UF 10UF 10UF 10UF C3 VDD2_A/B M4
MEM_B_CKE<2> C7 CKE0_A CKE0_B J3 MEM_B_CKE<0> 20% 20% 20% 20% VSS_A/B
7 IN IN 7 6.3V 6.3V 2 6.3V 2 6.3V U3 VDD2_A/B
D7 CERM-X5R 2 CERM-X5R 2 U4
7 IN
MEM_B_CKE<3> CKE1_A CKE1_B J4 MEM_B_CKE<1> IN 7 65 0402-2 0402-2
CERM-X5R
0402-2
CERM-X5R
0402-2 R15 VSS_A/B
VDD2_A/B A5
H16 VSS_A/B
N8 VDD2_A/B E5
22 7 IN
MEM_B_ODT<0> ODT_A ODT_B H13 MEM_B_ODT<0> 7 22
B17 VSS_A/B
VDD2_A/B F5
C17 VSS_A/B
N6 H14 VDD2_A/B G5
P8 F13 VDD2_A/B H5
DM1_A DM1_B T8 VSS_A/B
P4 L14 VDD2_A/B J5
P11 D14 VDD2_A/B K5
DM3_A DM3_B VSS_A/B
VSS_A/B L5
62 7 MEM_B_DQ<2> N4 DQ0_A DQ0_B L15 MEM_B_DQ<22> 7 62 VSS_A/B M5
BI BI
62 7 MEM_B_DQ<0> T5 DQ1_A DQ1_B L16 MEM_B_DQ<16> 7 62 VSS_A/B A12
BI BI
62 7 MEM_B_DQ<4> R5 DQ2_A DQ2_B K13 MEM_B_DQ<18> 7 62 VSS_A/B D12
BI BI
62 7 MEM_B_DQ<1> P5 DQ3_A DQ3_B K14 MEM_B_DQ<23> 7 62 VSS_A/B E12
BI BI
MEM_B_DQ<6> N5 K15 MEM_B_DQ<17> F12
C 62 7
62 7
BI
MEM_B_DQ<5> T6
DQ4_A
DQ5_A
DQ4_B
DQ5_B K16 MEM_B_DQ<20>
BI 7 62
7 62 BYPASS=U2500.A9::5mm
VSS_A/B
VSS_A/B H12 C
BI BI PP1V2_S3
DDR B
DDR A
R6 J15 61 50 47 22 21 20 12 8 BYPASS=U2500.G2::5mm L12
62 7 BI
MEM_B_DQ<7> DQ6_A DQ6_B MEM_B_DQ<21> BI 7 62 BYPASS=U2500.E1::5mm A6 VSS_A/B
P6 J16 VDDCA_A/B U12
62 7 BI
MEM_B_DQ<3> DQ7_A DQ7_B MEM_B_DQ<19> BI 7 62
E1 VSS_A/B
T9 F14 VDDCA_A/B N13
MEM_B_DQ<11> DQ8_A DQ8_B MEM_B_DQ<25> VSS_A/B
62 7 BI
MEM_B_DQ<14> R9 DQ9_A DQ9_B F15 MEM_B_DQ<24>
BI 7 62
C2570 1 C2571 1 C2572 1 K1 VDDCA_A/B
VSS_A/B U13
62 7 BI BI 7 62
10UF 10UF 10UF G2 VDDCA_A/B A14
MEM_B_DQ<9> T10 DQ10_A DQ10_B F16 MEM_B_DQ<26> 20% 20% 20% VSS_A/B
62 7 BI BI 7 62 6.3V 6.3V 6.3V A9 VDDCA_A/B
MEM_B_DQ<15> R10 DQ11_B E13 MEM_B_DQ<30> CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 VSS_A/B P14
62 7 BI DQ11_A BI 7 62 0402-2 0402-2 0402-2 B9
P10 E14 VDDCA_A/B G15
62 7 BI
MEM_B_DQ<13> DQ12_A DQ12_B MEM_B_DQ<28> BI 7 62 VSS_A/B
62 7 MEM_B_DQ<10> N10 DQ13_A DQ13_B E15 MEM_B_DQ<29> 7 62 VSS_A/B H15
BI BI
62 7 MEM_B_DQ<8> T11 DQ14_A DQ14_B E16 MEM_B_DQ<31> 7 62 VSS_A/B T15
BI BI
65 62 7 MEM_B_DQ<12> R11 DQ15_A DQ15_B D13 MEM_B_DQ<27> 7 62 VSS_A/B U15
BI BI
62 7 MEM_B_DQ<35> T2 DQ16_A DQ16_B P15 MEM_B_DQ<55> 7 62 VSS_A/B G16
BI BI
62 7 MEM_B_DQ<37> R2 DQ17_A DQ17_B P16 MEM_B_DQ<50> 7 62 VSS_A/B R16
BI BI
62 7 MEM_B_DQ<33> P2 DQ18_A DQ18_B N14 MEM_B_DQ<48> 7 62 VSS_A/B U16
BI BI
N2 N15 BYPASS=U2500.A13::5mm D17
62 7 BI
MEM_B_DQ<32> DQ19_A DQ19_B MEM_B_DQ<53> BI 7 62 61 50 47 22 21 20 12 8 PP1V2_S3 VSS_A/B
62 7 MEM_B_DQ<38> T3 DQ20_A DQ20_B N16 MEM_B_DQ<51> 7 62
N1 VDDQ_A/B VSS_A/B F17
BI BI
62 7 MEM_B_DQ<39> R3 DQ21_A DQ21_B M13 MEM_B_DQ<52> 7 62
M2 VDDQ_A/B VSS_A/B J17
BI BI
62 7 BI
MEM_B_DQ<36> P3 DQ22_A DQ22_B M14 MEM_B_DQ<54> BI 7 62 C2580 1 M3 VDDQ_A/B VSS_A/B M17
62 7 MEM_B_DQ<34> N3 DQ23_A DQ23_B L13 MEM_B_DQ<49> 7 62
10UF U5 VDDQ_A/B VSS_A/B N17
BI BI 20%
62 7 MEM_B_DQ<47> N11 DQ24_A DQ24_B C13 MEM_B_DQ<57> 7 62
6.3V 2 B12 VDDQ_A/B VSS_A/B R17
BI BI CERM-X5R
62 7 MEM_B_DQ<45> N12 DQ25_A DQ25_B C14 MEM_B_DQ<56> 7 62
0402-2 C12 VDDQ_A/B VSS_A/B T17
BI BI
62 7 MEM_B_DQ<46> P12 DQ26_A DQ26_B C15 MEM_B_DQ<59> 7 62
G12 VDDQ_A/B VSS_A/B E6
BI BI
62 7 MEM_B_DQ<41> T13 DQ27_A DQ27_B C16 MEM_B_DQ<62> 7 62
K12 VDDQ_A/B VSS_A/B M6
BI BI
R13 B13 BYPASS=U2500.K17::5mm M12 U6
62 7 BI
MEM_B_DQ<43> DQ28_A DQ28_B MEM_B_DQ<60> BI 7 62 VDDQ_A/B VSS_A/B
62 7 MEM_B_DQ<42> P13 DQ29_A DQ29_B B14 MEM_B_DQ<61> 7 62
A13 VDDQ_A/B VSS_A/B E7
BI BI
MEM_B_DQ<40> T14 DQ30_A DQ30_B B15 MEM_B_DQ<58> U14 VDDQ_A/B VSS_A/B R7
B
62 7 BI
MEM_B_DQ<44> R14 DQ31_A DQ31_B B16 MEM_B_DQ<63>
BI 7 62
C2585 1
E17 VDDQ_A/B VSS_A/B T7 B
62 7 BI BI 7 62
10UF G17 A8
20% VDDQ_A/B VSS_A/B
6.3V 2
62 7 MEM_B_DQS_P<0> P7 DQS0_T_A DQS0_T_B J14 MEM_B_DQS_P<2> 7 62
CERM-X5R K17 VDDQ_A/B VSS_A/B E8
BI BI 0402-2
62 7 MEM_B_DQS_N<0> N7 DQS0_C_A DQS0_C_B J13 MEM_B_DQS_N<2> 7 62
L17 VDDQ_A/B VSS_A/B M8
BI BI
P17 VDDQ_A/B VSS_A/B R8
62 7 MEM_B_DQS_P<1> P9 DQS1_T_A DQS1_T_B G14 MEM_B_DQS_P<3> 7 62 BYPASS=U2500.U10::5mm M7 VDDQ_A/B VSS_A/B E9
BI BI
62 7 MEM_B_DQS_N<1> N9 DQS1_C_A DQS1_C_B G13 MEM_B_DQS_N<3> 7 62
U7 VDDQ_A/B VSS_A/B U9
BI BI
M10 VDDQ_A/B VSS_A/B E10
62 7 BI
MEM_B_DQS_P<4> T4 DQS2_T_A DQS2_T_B M16 MEM_B_DQS_P<6> BI 7 62 C2590 1 U10 VDDQ_A/B VSS_A/B E11
62 7 MEM_B_DQS_N<4> R4 DQS2_C_A DQS2_C_B M15 MEM_B_DQS_N<6> 7 62
10UF U11 VDDQ_A/B VSS_A/B M11
BI BI 20%
6.3V
CERM-X5R 2
62 7 MEM_B_DQS_P<5> T12 DQS3_T_A DQS3_T_B D16 MEM_B_DQS_P<7> 7 62
0402-2
BI BI
62 7 MEM_B_DQS_N<5> R12 DQS3_C_A DQS3_C_B D15 MEM_B_DQS_N<7> 7 62
BI BI
MEM_B_ZQ_B B11 ZQ_A ZQ_B E2 MEM_B_ZQ_A
22 21 20 19 PPVREF_S3_MEM_VREFCA A10 VREFCA_A VREFCA_B J1 PPVREF_S3_MEM_VREFCA 19 20 21 22
22 20 19 PPVREF_S3_MEM_VREFDQ_B U8 VREFDQ_A VREFDQ_B H17 PPVREF_S3_MEM_VREFDQ_B 19 20 22
R2500 1 C2510 1 1 C2511 NC

A1 NC NC A17
NC C2531 1 1 C2530 1
R2520
243 0.047UF 0.047UF U1 NC NC U17 0.047UF 0.047UF 243
1% 10% 10% NC NC 10% 10% 1%
1/20W 6.3V 2 2 6.3V E3 NC NC D8 6.3V 2 2 6.3V 1/20W
MF X5R X5R NC NC X5R X5R MF
201 2 201 201 E4 NC NC M9 201 201
NC NC 2 201
H4 NC NC C11
NC NC
J12 NC NC D11
NC NC
PAGE TITLE
LPDDR3 DRAM Channel B (0-63)

DRAWING NUMBER SIZE
<SCH_NUM> D
Apple Inc.
REVISION
R
<E4LABEL>

25 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Port Controller ROM

PP3V3_UPC_XA_LDO 24
'Ridge-less Support 1 C3090

R3091 1 1
R3093 R3092 1 1.0UF
GND 3.3K 3.3K 3.3K 20%
1
R3090 5% 5% 5% 2 6.3V
X5R
24 USBC_X_POC_RESET 1 2 100K R3013 3.3K 1/20W
MF
1/20W
MF
1/20W
MF 0201-1
A1
IN
1/20W 5% MF 201 5% 201 2 2 201 201 2
UPC_XA_HPD_RX 1 2 100K R3012 1/20W
MF VCC
D
24 IN
D
1/20W 5% MF 201 2 201
U3090
8MBIT-3.0V
W25Q80DV
23 UPC_XA_SPI_CLK_R C1 CLK WLCSP DI(IO0) D1 UPC_XA_SPI_MOSI_R 23
A2 DO(IO1) B2 UPC_XA_SPI_MISO_R 23
23 UPC_XA_SPI_CS_R_L CS*
OMIT_TABLE
DP Support UPC_XA_ROM_WP_L C2 WP*(IO2)
CRITICAL
UPC_XA_ROM_HOLD_L B1 HOLD*(IO3)
IN
DP_DDI1_ML_C_P<3..0> DP_XA_ML_C_P<3..0> OUT 5 60
MAKE_BASE=TRUE
DP_DDI1_ML_C_N<3..0> DP_XA_ML_C_N<3..0> 5 60 X260 DEV: SOIC 998-02804 GND
IN OUT
MAKE_BASE=TRUE
X260 POR: CSP 335S00084
D2
60 23 5 BI
DP_XA_AUXCH_C_P DP_XA_AUXCH_C_P BI 5 23 60
MAKE_BASE=TRUE REFERENCE: USON 998-01174
60 23 5 BI
DP_XA_AUXCH_C_N DP_XA_AUXCH_C_N BI 5 23 60
MAKE_BASE=TRUE
60 24 23 19 OUT
DP_XA_HPD DP_XA_HPD IN 19 23 24 60
MAKE_BASE=TRUE
23 UPC_XA_SPI_CLK_R R3095 30 1 2 UPC_XA_SPI_CLK IN 24
23 UPC_XA_SPI_CS_R_L R3096 30 1 2
5% 1/20W MF 201
UPC_XA_SPI_CS_L IN 24
23 UPC_XA_SPI_MOSI_R R3097 30 1 2
5% 1/20W MF 201
UPC_XA_SPI_MOSI IN 24
23 UPC_XA_SPI_MISO_R R3098 30 1 2
5% 1/20W MF 201
UPC_XA_SPI_MISO OUT 24
USB Support Place series R at T with dev debug header

5% 1/20W MF 201
USB_EXTA_P USB_EXTA_P Characterize series R on P0 Dev, hopefully remove for P0 POR

65 23 16 BI BI 16 23 65
MAKE_BASE=TRUE
65 23 16 BI
USB_EXTA_N USB_EXTA_N BI 16 23 65
MAKE_BASE=TRUE
65 63 24 23 16 IN
XDP_USB_EXTA_OC_L XDP_USB_EXTA_OC_L
MAKE_BASE=TRUE
16 23 24 63 65 Single Port Support
USB_EXTA_OC_L
C OUT 63
24 23 IN
UPC_XA_UART_RXTX UPC_XA_UART_RXTX 23 24
C
L3020
90-OHM-0.1A
24 23 OUT
UPC_XA_UART_RXTX MAKE_BASE=TRUE
EXCX4CE
SYM_VER-1
65 23 16 BI
USB_EXTA_P 1 24 23 4 USB_UPC_XA_F_P USB_UPC_XA_F_P BI 23 24
PLACE_NEAR=U3100.L5:5mm
MAKE_BASE=TRUE
USB_EXTA_N 2 3 USB_UPC_XA_F_N USB_UPC_XA_F_N

65 23 16 BI
24 23
PLACE_NEAR=U3100.K5:5mm
MAKE_BASE=TRUE
BI 23 24
Bring Up Support
NOSTUFF
61 41 40 36 33 31 30 29 18 PP3V3_G3H
R3061
1 2 0 PP3V3_UPC_VIN 23 24
1/20W 5% MF 0201
65 61 41 PP3V3R3V0_AON
R3062
1 2 0 PP3V3_UPC_VIN 23 24
Dead Battery Support 1/20W 5% MF 0201 MAKE_BASE=TRUE

VOLTAGE=3.3V
60 24 23 BI
USBC_XA_CC1 USBC_XA_CC1 BI 23 24 60 VIN_3V3 power currently required to drive POWER_GATE_EN
MAKE_BASE=TRUE
high. Future OTP update may enable usage of 3V3_G3H instead.
60 24 23 BI
USBC_XA_CC2 USBC_XA_CC2 BI 23 24 60
MAKE_BASE=TRUE
IN
GND
MAKE_BASE=TRUE
High Speed Mux Support

P1V2S5SW_HSMUX_EN P1V2S5SW_HSMUX_EN
B B
49 24 23 OUT 23 24 49
Debug Support MAKE_BASE=TRUE
60 24 23 USBC_XA_I2C_EN USBC_XA_I2C_EN 23 24 60
65 24 23 OUT
SMC_UART_TX SMC_UART_TX IN 23 24 65
IN
MAKE_BASE=TRUE
OUT
MAKE_BASE=TRUE
65 24 23 IN
SMC_UART_RX SMC_UART_RX OUT 23 24 65
MAKE_BASE=TRUE
63 54 24 23 IN
S3X_JTAG_TCK S3X_JTAG_TCK (SWCLK) OUT 23 24 54 63
MAKE_BASE=TRUE
Bansuri Support
63 54 24 23 BI
S3X_JTAG_TMS S3X_JTAG_TMS (SWDIO) BI 23 24 54 63
MAKE_BASE=TRUE
65 41 24 23 POWER_GATE_EN POWER_GATE_EN 23 24 41 65
63 59 24 23 SSD_DEBUG_UART_D2R SSD_DEBUG_UART_D2R 23 24 59 63
IN
MAKE_BASE=TRUE
OUT
OUT
MAKE_BASE=TRUE
IN
65 41 IN
HIPWR_EN
63 59 24 23 BI
SSD_DEBUG_UART_R2D SSD_DEBUG_UART_R2D
MAKE_BASE=TRUE
BI 23 24 59 63
1
R3071 1
R3070
100K 100K
5% 5%
1/20W 1/20W
IN
GND MF MF
MAKE_BASE=TRUE 2 201 2 201
67
27 26 23 19 17 16 15 14 6 5 PP3V3_S0 Q3033
61 53 51 50 46 39 35 34 33 31
2
DMN5L06VK-7
SOT563
G VER 5
5 IN
S0 PU on PCH page
PCH_UPC_XA_SWD_CLK S D6
G3H IPU in UPC
UPC_XA_SWD_CLK OUT 23 24
Other Support
1
UPC_XA_SWD_CLK 23 24
24 IN
UPC_XA_5V_EN
1/20W
1
5%
2 100K
MF 201
R3040
MAKE_BASE=TRUE
24 IN
TBT_X_RTD3_CIO_PWR_EN 1 2 100K R3041
A 67
PP3V3_S0 Q3033
1/20W 5% MF 201
SYNC_MASTER=X260_ERIC SYNC_DATE=06/04/2015
USB-C
A
27 26 23 19 17 16 15 14 6 5
61 53 51 50 46 39 35 34 33 31
5
DMN5L06VK-7 PAGE TITLE
G
SOT563
VER 5
F3050
USB-C Port Controller Support
DRAWING NUMBER SIZE
S0 PU on PCH page G3H IPU in UPC 4A-32V
<SCH_NUM> D
5 BI
PCH_UPC_XA_SWD_DATA S D3 UPC_XA_SWD_DATA BI 23 24 61 60 24 PPVBUS_LIO 1 2 PP20V_USBC_XA_VBUS_F 24 Apple Inc.
4 REVISION
R
UPC_XA_SWD_DATA 23 24 0603 <E4LABEL>
MAKE_BASE=TRUE

30 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PRIMARY ACE USB-C PORT CONTROLLER (UPC)
Q3100
D
FDPC4044
PWR-CLIP-33 D
G2
1 G1
S2
S1
5
3
2
8
FUSE 23 PP20V_USBC_XA_VBUS_F
Add on NCNC
support page MIN_LINE_WIDTH=0.6000
VOLTAGE=20V
PPDCIN_G3H 34 41 61 65
61 60 23 PPVBUS_LIO
MAX 100uF TOTAL ON RAIL
1 C3101 UPC_XA_GATE1
1UF
10% MIN_LINE_WIDTH=0.2000
2 35V UPC_XA_GATE2 MIN_NECK_WIDTH=0.2000
X5R VOLTAGE=3.3V
0402
PP3V3_UPC_XA_LDO 23 24
61 50 48 33 17 13 9 PP1V8_SUS VOUT_3V3 FOR RIDGE,

P1V2S5SW_HSMUX_EN 23 49 OR FLOAT IF UNUSED
23 PP3V3_UPC_VIN
PP1V8A_UPC_XA_LDO MIN_LINE_WIDTH=0.2000
GND MIN_NECK_WIDTH=0.2000
PP1V8D_UPC_XA_LDO VOLTAGE=1.8V
PP5V_S4 MIN_LINE_WIDTH=0.2000
CAP FOR PP_5V0 ON VR PAGE 38 37 29
67 63 61 53 50 46 45 42 PP1V1_UPC_XA_LDO_BMC MIN_NECK_WIDTH=0.2000
C3100
C3104
VOLTAGE=1.8V 1 C3106
C11
D11
PP_CABLE H10
H11
A11
B11
K11
J10
J11
1 1
LDO_3V3 G1
VIN_3V3 H1
VOUT_3V3 H2
A6
A7
A8
B7
VDDIO B1
LDO_1V8A K1
LDO_1V8D A2
LDO_BMC E1
0.47UF
10UF 1 C3105 1 C3108 VOLTAGE=1.1V 2.2UF 10%
PP_5V0
PP_5V0
PP_5V0
PP_5V0
PP_HV
PP_HV
PP_HV
VBUS
VBUS
VBUS
PP_HV
VBUS
20% 20% 2 6.3V
2 6.3V
CERM-X5R
1.0UF 10UF 2 4V
X5R-CERM
CERM-X5R
20% 20% 0201
0402-1 2 6.3V 2 6.3V 0201
X5R CERM-X5R
C 0201-1 0402-1
C
PP3V3_UPC_XA_LDO 23 24
E11 MRESET
23 IN
USBC_X_POC_RESET PRIMARY ONLY CRITICAL
60 23 OUT
USBC_XA_I2C_EN F11 RESET* PRIMARY ONLY U3100 OMIT_TABLE
TESTPOINTS MUST BE TP_UPC_XA_DBG_UART_TX CD3215A

2
3.3K 1 R3109 I2C_UPC_XA_DBG_CTL_SCL 24 60 PRESENT FOR GPIO0, GPIO1
B2
C2
GPIO0
BGA
5% 1/20W MF 201 (EVEN IN PRODUCTION) TP_UPC_XA_DBG_UART_RX GPIO1
2
3.3K 1 R3108 I2C_UPC_XA_DBG_CTL_SDA 24 60 USE GPIO2 FOR USB-C ANALOG AUDIO SUPPORT
23 BI
TBT_X_RTD3_CIO_PWR_EN D10
G11
GPIO2
5% 1/20W MF 201 ON DESIGNS WITHOUT AN AUDIO JACK CONNECTOR 65 41 23 BI
POWER_GATE_EN GPIO3 SS H7 UPC_XA_SS
USE GPIO3 FOR POWER_GATE_EN 60 23 19 DP_XA_HPD C10 GPIO4
SENSEP B10
OUT
HV FET/SENSE
ON BANSURI DESIGNS
23 UPC_XA_HPD_RX E10 GPIO5
SENSEN A10
1 C3109
23 OUT
UPC_XA_5V_EN G10 GPIO6 0.22UF
20%
32 31 30 25 SMC_PME_S4_DARK_L D7 GPIO7 HV_GATE1 B9 2 6.3V
OUT X5R
65 63 23 16 XDP_USB_EXTA_OC_L H6 GPIO8 HV_GATE2 A9 0201
OUT
GND F10 BUSPOWERZ

IN
DIGITAL CORE I/O AND CONTROL

GND I2C_ADDR UPC_XA_I2C_ADDR F1 I2C_ADDR C_CC1 L9 USBC_XA_CC1 23 24 60 MIN_NECK_WIDTH=0.2000
BI
PRIMARY ONLY G2 R_OSC
UPC_XA_R_OSC C_CC2 L10 USBC_XA_CC2 MIN_LINE_WIDTH=0.5000
R3102 1 BI 23 24 60
CRITICAL MIN_NECK_WIDTH=0.2000
5%
0 R3103 1 60 24 BI
I2C_UPC_XA_DBG_CTL_SCL E4 DEBUG_CTL1
D5 DEBUG_CTL2
RPD_G1 K9 USBC_XA_CC1 BI 23 24 60
1 C3114 1 C3113
1/20W 15K 60 24 BI
I2C_UPC_XA_DBG_CTL_SDA RPD_G2 K10 USBC_XA_CC2 BI 23 24 60
220PF 220PF
MF 0.1%
TYPE-C
201 2 1/20W 10% 10%
1M I2C_UPC_SDA D1 I2C_SDA1 C_USB_TP K6 USBC_XA_USB_TOP_P 2 16V 2 16V
1 2 R3105 UPC_XA_UART_RXTX 23 24
TF-LF
0201 2
33 17
33 17
BI
I2C_UPC_SCL D2 I2C_SCL1 C_USB_TN L6 USBC_XA_USB_TOP_N
BI 60
60
CER-X7R
0201
CER-X7R
0201
5% 1/20W MF 201 BI BI
NEED 0.1% C1 I2C_IRQ1*
33 17 UPC_I2C_INT_L
C_USB_BP K7 USBC_XA_USB_BOT_P
OUT
BI 60
33 30 SMBUS_SMC_4_G3_SDA A5 I2C_SDA2 C_USB_BN L7 USBC_XA_USB_BOT_N 60

BI BI
33 30 SMBUS_SMC_4_G3_SCL B5 I2C_SCL2
C_SBU1 K8 USBC_XA_SBU1
BI
TO SMC
B B
60
33 30 SMC_USBC_INT_L B6 I2C_IRQ2* BI
C_SBU2 L8 USBC_XA_SBU2
OUT
BI 60
23 UPC_XA_SPI_CLK A3 SPI_CLK
OUT
REAR PORT: 23 UPC_XA_SPI_MOSI B4 SPI_MOSI
NC L11
OUT
CONNECT UPC SPI TO ROM A4
FRONT PORT: 23 IN
UPC_XA_SPI_MISO SPI_MISO NC or GND to dissipate heat
GROUND UPC SPI B3
23 OUT
UPC_XA_SPI_CS_L SPI_SSZ
23 UPC_XA_SWD_DATA F4 SWD_DATA
23 UPC_XA_SWD_CLK G4 SWD_CLK
24 23 UPC_XA_UART_RXTX F2 UART_RX
IN
24 23 UPC_XA_UART_RXTX E2 UART_TX
OUT
PORT MUX
63 59 23 SSD_DEBUG_UART_D2R L4 LSX_R2P
IN
63 59 23 SSD_DEBUG_UART_R2D K4 LSX_P2R
OUT
23 USB_UPC_XA_F_P L5 USB_RP_P
BI
Add CMC on support page
for ridgeless design
CMC 23 BI
USB_UPC_XA_F_N K5 USB_RP_N
DP_XA_AUXCH_P J1 AUX_P
DP_XA_AUXCH_N J2 AUX_N
61 59 50 46 31 29 26 25 18 15 PP3V3_S4 L2
65 23 BI
SMC_UART_TX DEBUG1
65 23 SMC_UART_RX K2 DEBUG2
BI
PU to PP3V3_S4 if convenient L3
for layout.
Otherwise PU to PP3V3_UPC_XA_LDO
1
R3110 63 54 23 BI
S3X_JTAG_TCK
K3
DEBUG3
100K 63 54 23 BI
S3X_JTAG_TMS DEBUG4
5%
1/20W
MF
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2 201
A A
A1
D6
E5
E6
E7
F5
G5
H4
H5
G8
H8
L1
B8
D8
E8
F6
F7
F8
G6
G7
60 BI
SUGGESTION: SYNC_MASTER=X260_ERIC SYNC_DATE=06/04/2015
60 BI DEBUG1 = SMC_DEBUGPRT_TX_L (MOJO) PAGE TITLE
DEBUG2 = SMC_DEBUGPRT_RX_L (MOJO)
1
R3111
DEBUG3 =
DEBUG4 =
DIG_AUD_XA_P (DIGITAL AUDIO)
DIG_AUD_XA_N (DIGITAL AUDIO) USB-C PORT CONTROLLER A
DRAWING NUMBER SIZE
100K
5% <SCH_NUM> D
1/20W Apple Inc.
MF GND REVISION
2 201 R
<E4LABEL>
PIN D6 IS UNDOCUMENTED RESET
CAN GROUND PIN D6 IN PRODUCTION NOTICE OF PROPRIETARY PROPERTY: BRANCH

31 OF 130
SHEET
BOM_COST_GROUP=USB-C IV ALL RIGHTS RESERVED 24 OF 67
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
114
115
15 U3700 116
SMC_PME_S4_DARK_L 31
19 LBEE5UA1BL-717 117 OUT 24
30
32
23 LGA 118 NO_XNET_CONNECTION=1
24 (2 OF 2)
119 Q3730 D 3
26 120
61 59 50
25 24 18 15
46 31 29 26
PP3V3_S4 DMN32D2LFB4
DFN1006H4-3
27 121 SYM_VER_2
29 122 C3702 1 C3703 1 1 C3700 1 C3701 1 C3704 1 C3705 1 C3706 1 C3707

30 123 10UF 10UF 4.7UF 4.7UF 12PF 12PF 12PF 12PF 1 G S 2
20% 20% 20% 20% 5% 5% 5% 5%
32 124 6.3V 2 6.3V 2 2 6.3V 2 6.3V 2 25V 2 25V 2 25V 2 25V
D 33 CRITICAL 125
X5R
603
X5R
603
X5R-CERM1
402
X5R-CERM1
402
NP0-C0G
0201
NP0-C0G
0201
NP0-C0G
0201
NP0-C0G
0201 BT_DEV_WAKE
D
34 126
36 GND 127
1
R3730
37 128 100K
1%
38 129 1/20W
MF
40 130 SYSCLK_CLK32K_CAMERA_BT_AP 18 65
2 201
IN
57 131
59 132
64 133
67 134
R3704 1 1
R3780
1
R3701
69 135
1
R3703 C3780 1
10K 10K
10K
VDDIO_1P8 11
BATT_VCC 58
25
35
0.1UF 5%
72 136 10K 10% 5% 5% 1/20W
5% 6.3V 2 1/20W 1/20W MF
1/20W MF MF 2 201
BATT_RF_VCC
75 137 MF OMIT_TABLE CERM-X5R 201 2
8 0201 2 201 BT_GPIO4 10 BT_GPIO4
78 138 2 201
VCC 68 CLK32K_AP
81
139
140
U3780
AT93C66B-MAHM 48 ANT_SWITCH_CORE0 5 NC
82 NC FAST_UART_RX (GPIO11)
3
UDFN ANT_SWITCH_CORE1 2 NC
83
141 25 WLAN_ROM_MOSI DI DO 4 25 WLAN_ROM_MISO 54 FAST_UART_TX (GPIO12)
142 WLAN_ROM_CS 1 WLAN_ROM_CLK 53 (FW changed to BT HOST WAKE)
84 THRM_PAD
143
25
WLAN_ROM_CLK 2
CS
SK
ORG 6 WLAN_ROM_ORG 25
WLAN_ROM_CS 46
WL_GPIO_8
FAST_RTS_OUT
(GPIO8)
(GPIO7)
U3700 BT_WAKE 16
85
25 25
LBEE5UA1BL-717 BT_USB_DP 3 NC_USB_BTP
86
144 NC 7 NC LGA
145 65 30 IN
SMC_WIFI_PWR_EN 60 WLAN_REG_ON BT_USB_DN 4 NC_USB_BTN
87 SYM 1 OF 2
THRM
146 GND PAD
88 SMC_BT_PWR_EN 56 BT_REG_ON BT_UART_RXD 13 BT_UART_R2D
147 5 9 65 30 IN
CRITICAL IN 26
89 BT_UART_TXD 12 BT_UART_D2R
148 OUT 26
90 JTAG_WLAN_SEL 45 JTAG_SEL BT_UART_CTS* 9 BT_UART_CTS_L
149 IN 26
91 BT_UART_RTS* 8 BT_UART_RTS_L
150 OUT 26 65
92
C 93
151
152
R3700 1 R3702 1 BT_PCM_CLK 6 BT_SPI_CLK 25 C
94 10K 10K 18 BT_SPI_CS_L
153 5% 5% BT_PCM_SYNC 25
95 1/20W 1/20W 66 14
154 MF MF NC HSIC_WLAN_DATA BT_PCM_OUT BT_SPI_MOSI 25
96 201 2 201 2 65 7
THRM_PAD 155 NC HSIC_WLAN_STROBE BT_PCM_IN BT_SPI_MISO 25
97 25 WLAN_ROM_MOSI 47 HSIC_DEV_RDY (GPIO10)
156
98 65 14 AP_DEV_WAKE 61 HSIC_HOST_READY/PCIE_DEV_WAKE (GPIO1)
157 IN
99 TP_JTAG_WLAN_TCK 62 HSIC_RESUME_FAST_CTS_IN/JTAG_TCK (GPIO2) (GPIO9) WL_GPIO_9 52 WLAN_ROM_MISO 25
158
100
159
101
160
102 TP_JTAG_WLAN_TMS 63 JTAG_TMS (GPIO3) (GPIO13) WL_GPIO_13 51 SMC_WIFI_EVENT_L 30 31
161 BI
103 TP_JTAG_WLAN_TRST 44 JTAG_TRST (GPIO6)
162
104 JTAG_WLAN_TDI 43 SEC_IN/JTAG_TDI (GPIO4) (GPIO0) WL_HOST_WAKE 55
163 NC
105 TP_JTAG_WLAN_TDO 42 SEC_OUT/JTAG_TDO (GPIO5)
164
106 WLAN_PCIE_PME 79 AP_PCIE_WAKE_L 18 65
165 OUT
107 WLAN_PCIE_CLKREQ 80 AP_CLKREQ_L 16 65
166 OUT
108 15 BT_LOW_PWR_L 17 HOST_WAKE_BT (FW changed to BT DEVICE WAKE) WLAN_PERST 1 AP_RESET_L 14 65
167 IN IN
109 OMIT_TABLE
110
168
169
R3714
111 RF_G_0_DIPLEXER 1
0.00 2 RF_G_0_MATCH 22 2G_CORE0_ANT 77 PCIE_AP_R2D_P
170 WLAN_PCIE_RDP0
112 0% OMIT_TABLE 31 2G_CORE1_ANT WLAN_PCIE_RDN0 76 PCIE_AP_R2D_N
113 C3729 1
1/32W
MF
01005
1 C3721 WLAN_PCIE_TDP0 73 PCIE_AP_D2R_C_P
2PF 0.3PF 28 5G_CORE0_ANT WLAN_PCIE_TDN0 74 PCIE_AP_D2R_C_N
+/-0.1PF +/-0.1PF
CRITICAL 16V 2 16V 39 5G_CORE1_ANT WLAN_PCIE_REFCLKP 71 PCIE_CLK100M_AP_C_P
NP0-C0G 2 NP0-C0G
01005 01005 WLAN_PCIE_REFCLKN 70 PCIE_CLK100M_AP_C_N
CRITICAL U3710 NC
20 BT_GPIO3 (GPIO14) WL_UART_RX 50
NC
J3710 CRITICAL LFD2H2G45ML5D911 NC
21 BT_GPIO5 (GPIO15) WL_UART_TX 49
NC
20449-001E-03 LLP
B F-ST-SM R3710
0.00 OMIT_TABLE
NC
41 NC
B
5 1
1 RF_0_ANT 1 2 RF_0_ANT_MATCH_T P3 P1 R3712
NO STUFF 0% NO STUFF P2 3 RF_A_0_DIPLEXER 1
0.00 2 RF_A_0_MATCH
C3718 1
1/32W
MF 1 C3719
2
3
4
0.2PF 01005
0.2PF GND NO STUFF 0% NO STUFF
+/-0.1PF
16V
+/-0.1PF
2 16V
C3720 1
1/32W
MF
01005
1 C3730
NP0-C0G 2 NP0-C0G 0.2PF 0.2PF
6
4
2
01005 01005 +/-0.1PF +/-0.1PF

16V
NP0-C0G 2 2 16V
NP0-C0G 16 IN
PCIE_AP_R2D_C_P C3757 1 2
10% 16V X5R-CERM 0201
01005 01005 0.1UF
16 IN
PCIE_AP_R2D_C_N C3754 1 2
10% 16V X5R-CERM 0201
0.1UF
CRITICAL PCIE_AP_D2R_P C3752 1 2
OMIT_TABLE 16 OUT
10% 16V X5R-CERM 0201
CRITICAL U3720 R3724
0.00 PCIE_AP_D2R_N C3753
0.1UF
1 2
J3720 CRITICAL LFD2H2G45ML5D911 RF_G_1_DIPLEXER 1 2 RF_G_1_MATCH 16 OUT
0.1UF 10% 16V X5R-CERM 0201
20449-001E-03 LLP
F-ST-SM R3723 NO STUFF 0% CRITICAL PCIE_CLK100M_AP_P C3758 1 2
1 RF_1_ANT 1
0.00 2 RF_1_ANT_MATCH_T 5 P3 P1
1 C3728 1
1/32W
MF
01005
1 C3725 16 IN
100PF 5% 25V C0G 0201
0.2PF 0.3PF
NO STUFF 0% NO STUFF P2 3
+/-0.1PF
16V
+/-0.5PF
2 16V
16 IN
PCIE_CLK100M_AP_N C3759 1 2
C3727 1
1/32W
MF 1 C3726 NP0-C0G 2 CERM 100PF 5% 25V C0G 0201
2
3
4
01005 01005 01005

0.2PF 0.2PF GND
+/-0.1PF +/-0.1PF
16V
NP0-C0G 2 2 16V
NP0-C0G 59 50 46 31 29 26 25 24 18 15 PP3V3_S4
6
4
2
61
01005 01005
CRITICAL
R3725 R3773 1 1 C3770 1
R3771 1
R3772
8
0.00 100K VCC 0.1UF 100K 100K
RF_A_1_DIPLEXER 1 2 RF_A_1_MATCH 5% 10% 5% 5%
2 6.3V
NO STUFF OMIT_TABLE 1/20W
U3770 CERM-X5R 1/20W 1/20W
A
0%
A
MF 0201 MF MF
C3723 1
1/32W
MF
01005
1 C3724 201 2
512KBIT 2 201 2 201 SYNC_MASTER=DEVMLB SYNC_DATE=07/20/2015
0.2PF 0.2PF MX25V512EZUI-13G PAGE TITLE
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION +/-0.1PF
16V
NP0-C0G 2
01005
+/-0.1PF
2 16V
NP0-C0G
01005 25 BT_SPI_MOSI 5 SI/SIO0
USON WIFI/BT MODULE [37]
131S0259 1 CAP,7PF,+/-0.1PF,16V,01005 R3714 CRITICAL BT_SPI_MISO 2 SO/SIO1 3 BTROM_WP_L DRAWING NUMBER SIZE
152S1742 1 IND,FILM,1.6NH,+/-0.1NH,200MA,01005 C3721 CRITICAL

25
WP*
Apple Inc.
<SCH_NUM> D
25 BT_SPI_CS_L 1
CS* HOLD* 7 BTROM_HOLD_L REVISION
152S1544 1 IND,FILM,0.4NH,+/-0.1NH,270MA,01005 R3712 CRITICAL

25 BT_SPI_CLK 6 SCLK
OMIT_TABLE R
<E4LABEL>
THRM NOTICE OF PROPRIETARY PROPERTY: BRANCH
152S1564 1 IND,FILM,2.4NH,+/-0.1NH,200MA,01005 R3724 CRITICAL GND PAD
9
152S1720 1 IND,FILM,1.8NH,+/-0.1NH,270MA,01005 C3724 CRITICAL THE POSESSOR AGREES TO THE FOLLOWING: PAGE
37 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BT UART Isolation
PP3V3_S4 15 18 24 25 26 29 31 46 50 59
61
R38931 1
R3894
100K 100K
5% 5%
1/20W 1/20W
D
MF
201 2
MF
2 201
PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31
33 34 35 39 46 50 51 53 61 67 D
BYPASS=U3890::5mm
CRITICAL 8 1 C3890
VCC
0.1UF
10%
2 10V
U3890
74LVC2G126GN
X5R-CERM
0201
XSON
BT_UART_D2R 2 PCH_BT_UART_D2R
25 IN A1 Y1 6 OUT 17 65
1
1OE
BT_UART_RTS_L 5 PCH_BT_UART_CTS_L
65 25 IN A2 Y2 3 OUT 17 65
PLT_RST_L 7
65 30 26 19 15 14 5 IN 2OE
GND
4
PP3V3_S0 33 34 35 39 46
5 6 14 15 16 17
19 23 26 27 31
PP3V3_S4 15 18 24 25 26 29 31 46 50 59
61
50 51 53 61 67
EG: Replace with IPUs?

BYPASS=U3895::5mm
CRITICAL 8 1 C3895 R3895 1 1
R3896
0.1UF 100K 100K
VCC 10% 5% 5%
10V 1/20W 1/20W
U3895
74LVC2G126GN
2 X5R-CERM
0201
MF
201 2
MF
2 201
XSON
PCH_BT_UART_R2D 2 BT_UART_R2D
65 17 IN A1 Y1 6 OUT 25
1
1OE
C 65 17 IN
PCH_BT_UART_RTS_L 5
7
A2 Y2 3 BT_UART_CTS_L OUT 25 C
65 30 26 19 15 14 5 IN
PLT_RST_L 2OE
GND
4
B B
A SYNC_MASTER=J92_DEVMLB SYNC_DATE=05/13/2015 A
PAGE TITLE
WIFI/BT Support
DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
38 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
L3902
1.0UH-1.6A-55MOHM
BYPASS=U3900.K13::2.54MM
28 27 PP1V35_CAM 1 2 P1V35_CAM_SRVLXD_PHASE 27
MIN_LINE_WIDTH=0.6000 1008
VOLTAGE=1.35V
L3906
1 C3921 1 C3922 1 C3923 1 C3924 1 C3912 1 C3913 PLACE_NEAR=U3900.K13:4MM
22NH 1.0UF 0.1UF 1.0UF 0.1UF 4.7UF 4.7UF
20% 10% 20% 10% 20% 20%
2 6.3V
X5R 2 6.3V
CERM-X5R 2 6.3V
X5R 2 6.3V
CERM-X5R 2 6.3V 2 6.3V
PP1V35_DDR_CLK 1 2
0201-1 0201 0201-1 0201
X5R
402
X5R
402 27 PP1V8_CAM
U3900 VOLTAGE=1.35V 1 C3900 1
R3920 1
R3921
BCM15700A2KFEB4G 0.1UF 27 GND_CAM_PVSSD 100K 100K
10% 5% 5%
D N7
FBGA
SYM 3 OF 3
2 6.3V
CERM-X5R
0201
1/20W
MF
1/20W
MF D
N8 A4 L3903 2 201 2 201
MIPI_AGND 220-OHM-1.4A
N6 D4 I2C_CAM_SMBDBG_CLK
CRITICAL 1 2 PP1V2_CAM_XTALPCIEVDD 27
DDR_VDDIO
G4 PP0V675_CAM_VREF 28
0603
18 27
I2C_CAM_SMBDBG_DAT 27 L3901
C10 K4 MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000 1 C3930 1 C3931 1.0UH-1.6A-55MOHM
C7 PCIE_GND N4 VOLTAGE=0.675V 1 C3927 20%
1.0UF 10UF
20%
27 PP1V2_CAM 1 2 P1V2_CAM_SRVLXC_PHASE 27
0.1UF 2 6.3V 2 6.3V 1008
G14 DDR_VDDIO_CK G5
10%
2 6.3V
X5R
0201-1
CERM-X5R
0402-1
1 C3970 1 C3971 1 C3972 1 C3973 1 C3974 1 C3975 1 C3976 1 C3914 1 C3915 PLACE_NEAR=U3900.M13:4MM
CERM-X5R 0.1UF 1000PF 0.1UF 1000PF 0.1UF 0.1UF 12PF 4.7UF 4.7UF
M12 PMU_AVSS 0201 L3904 10%
2 6.3V
10%
2 16V
10%
2 6.3V
10%
2 16V
10%
2 6.3V
10%
2 6.3V
5%
2 25V
20%
2 6.3V
20%
2 6.3V
PLACE_NEAR=U3900.M13:2.54MM
DDR_VREF N5
220-OHM-1.4A CERM-X5R X7R-1 CERM-X5R X7R-1 CERM-X5R CERM-X5R NP0-C0G X5R X5R
0201 0201 0201 0201 0201 0201 0201 402 402
27 GND_CAM_PVSSC N13 1 2
P14 PCIE_VDD1P2 C8 PP1V2_CAM_PCIE_VDD_FLT 0603
P15 SR_PVSSC MIN_LINE_WIDTH=0.6000
1 C3932 1 C3933 BYPASS=U3900.F6::2.54MM BYPASS=U3900.F9::2.54MM
BYPASS=U3900.F6::2.54MM BYPASS=U3900.L9::2.54MM 27 GND_CAM_PVSSC
VOLTAGE=1.2V 1.0UF 10UF BYPASS=U3900.F9::2.54MM BYPASS=U3900.L9::2.54MM
R15 PCIE_PVDD1P2 D9 20% 20%
2 6.3V
X5R 2 6.3V
CERM-X5R
PP1V2_CAM_PCIE_PVDD_FLT 0201-1 0402-1
GND_CAM_PVSSD K15 DDR_AVDD1P8 J1
27
L12
VOLTAGE=1.2V
U3900
L13 MIPI_AVDD1P8 L7 PP1V8_CAM BCM15700A2KFEB4G
SR_PVSSD 27
FBGA
L14 SYM 1 OF 3
MIPI_CLK_P P7 MIPI_CP_CLK DEBUG_00 B11 TP_CAM_TEST_MODE0
L15 PLL_VDD1P8 D6
65 28 IN
1 C3919 1 C3918 1 C3916 1 C3917 1 C3910 1 C3951 65 28 IN
MIPI_CLK_N R7 MIPI_CM_CLK DEBUG_01 C14 TP_CAM_TEST_MODE1
(=PP3V3_S0_CAMERA) BYPASS=U3900.D7::2.54MM
0.1UF 1000PF 0.1UF 1000PF 0.1UF 0.1UF CRITICAL DEBUG_02 B14 TP_CAM_TEST_MODE2
A1 OTP_VDD3P3 D7 10% 10% 10% 10% 10% 10%
P8 MIPI_DP0 A15 TP_CAM_LV_JTAG_TCK
A6 2 6.3V
CERM-X5R 2 16V
X7R-1 2 6.3V
CERM-X5R 2 16V
X7R-1 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 65 28 IN
MIPI_DATA_P DEBUG_03
B6 M14
1 C3938 0201 0201 0201 0201 0201 0201 65 28 IN
MIPI_DATA_N R8 MIPI_DM0 DEBUG_04 E11 TP_CAM_LV_JTAG_TDI
1000PF DEBUG_05 E10 TP_CAM_LV_JTAG_TDO
D1 M15 10%
D5
SR_VDD_3P3C
N15
1 C3928 16V
2 X7R-1 BYPASS=U3900.J1::2.54MM BYPASS=U3900.L7::2.54MM
BYPASS=U3900.J1::2.54MM BYPASS=U3900.D6::2.54MM NC
P6 MIPI_DP1 DEBUG_06 F11 TP_CAM_LV_JTAG_TMS
4.7UF 0201 BYPASS=U3900.L7::2.54MM BYPASS=U3900.D6::2.54MM R6 MIPI_DM1 F10 TP_CAM_LV_JTAG_TRSTN
C E5 20%
2 6.3V
NC DEBUG_07
G11 C
G1 H14 X5R
402 XW3900
SM PCIE_CAMERA_R2D_P B7 PCIE_RDP0
DEBUG_08
DEBUG_09 G10
NC
G6 H15 28 IN NC
GND_CAM_PVSSC 1 2 PCIE_CAMERA_R2D_N A7 PCIE_RDN0 DEBUG_10 H11
G7 J13 27
28 IN NC
SR_VDD_3P3D MIN_NECK_WIDTH=0.2000 DEBUG_11 H10
G8 J14 VOLTAGE=0V NC
PCIE_CLK100M_CAMERA_C_P B10 PCIE_REFCLKP DEBUG_12 J10
G9 J15 28 IN NC
(=PP3V3_S0_CAMERA) PCIE_CLK100M_CAMERA_C_N A10 PCIE_REFCLKN DEBUG_13 K11
H5 28 IN NC
VSSC DEBUG_14 K10
H6 M13 P1V2_CAM_SRVLXC_PHASE 27 PLACE_NEAR=U3900.M14:2.54MM NC
PCIE_CAMERA_D2R_C_P A8 PCIE_TDP0 DEBUG_15 L11
H7 SR_VLXC_O N14 MIN_LINE_WIDTH=0.6000
DIDT=TRUE
1 C3926 28 OUT
PCIE_CAMERA_D2R_C_N B8 PCIE_TDN0 DEBUG_16 L10
NC
H8 4.7UF 27 PP1V8_CAM 28 OUT NC
20%
H9 K13 P1V35_CAM_SRVLXD_PHASE 2 6.3V
J5 SR_VLXD_O K14 MIN_LINE_WIDTH=0.6000
27 X5R
402 XW3901
SM NC
B9 PCIE_TESTP
DIDT=TRUE C9 PCIE_TESTN
J6 GND_CAM_PVSSD 1 2 NC
R3913 1 R3914 1
27
MIN_LINE_WIDTH=0.6000 50 51 GPIO_00 R12 TP_CAM_RAMCFG0
J7 VDD_1P35A F14 PP1V35_CAM PP3V3_S0 26 31
27 28 MIN_NECK_WIDTH=0.2000 5 6 14
A13 XTAL_P P12 TP_CAM_RAMCFG1
J8 VOLTAGE=0V 15 16 17 19 23
33 34 35 39 46
1K 1K 65 18 OUT
SYSCLK_CLK24M_CAMERA GPIO_01
5% 5% A12 XTAL_N P11 TP_CAM_RAMCFG2
53 61 67
1/20W 1/20W CLK25M_CAM_CLKN GPIO_02
J9 VDD_3P3A J11 MF MF P10 TP_CAM_GPIO3
K1 201 2 201 2 GPIO_03
PP1V2_CAM_XTALPCIEVDD 18 27
D15 P9
I2C_CAM_SMBDBG_CLK I2C_CLK_DBG GPIO_04
K5 VDD1P2_O F15 1 C3942 1 C3940 1 C3934 1 C3935 1 C3936 1 C3937 27
I2C_CAM_SCK R10 I2C_CLK_SENSOR GPIO_05 N11
NC
K6 4.7UF 0.1UF 1000PF 0.1UF 1000PF 0.1UF 53 OUT NC
PP1V8_CAM 20% 10% 10% 10% 10% 10% I2C_CAM_SMBDBG_DAT C15 I2C_DATA_DBG GPIO_06 N10
K7 VDD1P8_O G15 MIN_LINE_WIDTH=0.6000
27
2 6.3V 2 6.3V 16V
2 X7R-1 2 6.3V 2 16V 2 6.3V
27
NC
MIN_NECK_WIDTH=0.2000 X5R CERM-X5R CERM-X5R X7R-1 CERM-X5R I2C_CAM_SDA R9 I2C_DATA_SENSOR GPIO_07 N9
K8 402 0201 0201 0201 0201 0201 53 BI NC
K9 F6
VOLTAGE=1.8V 1 C3941 BYPASS=U3900::7mm BYPASS=U3900::3mm BYPASS=U3900::3mm CAM_XTAL:NO
2.2UF TP_CAM_JTAG_TCK F13 JTAG_TCK UARTCTS D13 CAM_UARTCTS
A14 F7 20%
2 6.3V
BYPASS=U3900::5mm BYPASS=U3900::5mm BYPASS=U3900::5mm
C3901 1
TP_CAM_JTAG_TDI E12 JTAG_TDI UARTRTS D14 TP_CAM_UARTRTS
27
M9 F8 CERM 100PF
402-LF 5% TP_CAM_JTAG_TDO F12 JTAG_TDO
N1 F9 1 C3939 25V 2
C0G TP_CAM_JTAG_TMS D12 JTAG_TMS UARTRXD E13 CAM_UARTRXD
P5 VDDC L6 1UF BYPASS=U3900.F15::2.54MM 0201 27
20% TP_CAM_JTAG_TRST_L D11 JTAG_TRST* UARTTXD E14 TP_CAM_UARTTXD
B R1
R5
L5
L8
2 10V
X6S-CERM
0201
27 PP1V8_CAM
TP_CAM_JTAG_SRST_L C11 JTAG_SRST* B
E9 L9 BYPASS=U3900.G15::2.54MM TEST_OUT J12 CAM_TEST_OUT 27
PP1V2_CAM 27
MIN_LINE_WIDTH=0.6000 CAMERA_CLKREQ_L P13 PCIE_CLKREQ* TEST_MODE M10 CAM_TEST_MODE
R3990 1
65 16 OUT 27
B12 XTAL_AVSS MIN_NECK_WIDTH=0.2000 R14 PCIE_RST*
B15 VOLTAGE=1.2V 65 14 CAMERA_RESET_L
STRAP_XTAL_FREQ C13 CAM_XTAL_FREQ
IN
100K
U3900 5%
1/20W
TP_CAM_PCIE_WAKE_L N12 PCIE_WAKE* 27
VDDO18 BCM15700A2KFEB4G MF STRAP_XTAL_SEL C12 CAM_XTAL_SEL

R11 201 2
27
FBGA CAM_PWR_SEL G12 PWR_MODE
SYM 2 OF 3
MEM_CAM_A<0> L3 DDR_AD00 DDR_DQ00 C2 MEM_CAM_DQ<0> CAM_DEBUG_RESET_L E15 RESET*
VSENSE_C M11
28 28
L3901:1 PP1V2_CAM 27
OUT
M4 E3
BI
R13
MEM_CAM_A<1> DDR_AD01 DDR_DQ01 MEM_CAM_DQ<1> SENSOR_WAKE*
VSENSE_D K12
28 28
L3902:1 PP1V35_CAM OUT BI
N3
R3901
27 28
MEM_CAM_A<2> DDR_AD02 DDR_DQ02 E4 MEM_CAM_DQ<2> 1 H12 SHUTDOWN*
28 OUT CRITICAL BI 28
28 MEM_CAM_A<3> M3 DDR_AD03 DDR_DQ03 D3 MEM_CAM_DQ<3> 28 100K

XTAL_AVDD1P2 B13 PP1V2_CAM_XTALPCIEVDD OUT BI
18 27
MEM_CAM_A<4> M1 F3 MEM_CAM_DQ<4> 5% PD = 1.35V
MIN_LINE_WIDTH=0.6000 28 OUT DDR_AD04 DDR_DQ04 BI 28 1/20W
MIN_NECK_WIDTH=0.2000 MF
VOLTAGE=1.2V
MAKE_BASE=TRUE
28 OUT
MEM_CAM_A<5> M2
P4
DDR_AD05 DDR_DQ05 F1
F4
MEM_CAM_DQ<5> BI 28 R3991 1 2 201
28 MEM_CAM_A<6> DDR_AD06 DDR_DQ06 MEM_CAM_DQ<6> 28 100K
PP1V2_CAM_XTALPCIEVDD 18 27
OUT
N2 F2
BI
5% 27 CAM_TEST_MODE
28 OUT
MEM_CAM_A<7> DDR_AD07 DDR_DQ07 MEM_CAM_DQ<7> BI 28 1/20W
P3 B5 MF
65 28 OUT
MEM_CAM_A<8> DDR_AD08 DDR_DQ08 MEM_CAM_DQ<8> BI 28 201 2 27 CAM_TEST_OUT
MEM_CAM_A<9> P2 DDR_AD09 DDR_DQ09 C3 MEM_CAM_DQ<9>
1 C3960 28 OUT
MEM_CAM_A<10> J4 DDR_AD10 DDR_DQ10 B1 MEM_CAM_DQ<10>
BI 28
CAM_SENSOR_WAKE_L NO STUFF
0.1UF 28 OUT BI 28 64 IN 1
R3910 1
R3911
10% 28 MEM_CAM_A<11> R2 DDR_AD11 DDR_DQ11 B4 MEM_CAM_DQ<11> 28 65 14 CAMERA_PWR_EN
2 6.3V
OUT BI IN
CERM-X5R MEM_CAM_A<12> L1 A5 MEM_CAM_DQ<12> 100K 100K
0201 28 OUT DDR_AD12 DDR_DQ12 BI 28 PU on PCH page 5% 5%
P1 C5 1/20W 1/20W
28 MEM_CAM_A<13> DDR_AD13 DDR_DQ13 MEM_CAM_DQ<13> 28 MF MF
OUT
R4 B2
BI PP1V8_CAM 27
2 201 2 201
28 OUT
MEM_CAM_A<14> DDR_AD14 DDR_DQ14 MEM_CAM_DQ<14> BI 28
DDR_DQ15 B3 MEM_CAM_DQ<15> 28
BI
MEM_CAM_BA<0> K3 DDR_BA0 CAM_FREQ:25M CAM_XTAL:YES
R3904 R3906
28 OUT 1 1
27 CAM_UARTCTS 28 MEM_CAM_BA<1> L2 DDR_BA1 DDR_DQS_P0 E2 MEM_CAM_DQS_P<0> 28 PU = 25MHz
OUT BI
K2 DDR_BA2 100K 100K
MEM_CAM_BA<2> DDR_DQS_N0 D2 MEM_CAM_DQS_N<0>
A 27 CAM_UARTRXD 28 OUT BI 28 5%
1/20W
MF
5%
1/20W
MF SYNC_MASTER=X260_ERIC SYNC_DATE=06/04/2015 A
MEM_CAM_CLK_P H2 DDR_CK_P0 DDR_DQS_P1 A2 MEM_CAM_DQS_P<1> 2 201 2 201 PAGE TITLE
R3975 R3976
28 28
1 1 OUT BI
51K 51K 28 OUT

MEM_CAM_CLK_N G2 DDR_CK_N0 DDR_DQS_N1 A3 MEM_CAM_DQS_N<1> BI 28 27 CAM_XTAL_FREQ CAM_XTAL_SEL 27 Camera 1 of 2
5% 5% CAM_FREQ:24M CAM_XTAL:NO DRAWING NUMBER SIZE
1/20W 1/20W
MF MF 28 OUT
MEM_CAM_DM<0> C1 DDR_DM0 DDR_RAS* H3 MEM_CAM_RAS_L OUT 28
PD = 24MHz
1
R3905 1
R3907 Apple Inc.
<SCH_NUM> D
2 201 2 201 MEM_CAM_DM<1> C4 DDR_DM1 DDR_WE* J2 MEM_CAM_WE_L 100K 100K REVISION
R3912
28 OUT OUT 28
5% 5%
240
DDR_CAS* H4 MEM_CAM_CAS_L OUT 28 1/20W
MF
1/20W
MF
R
<E4LABEL>
1 2 MEM_CAM_ZQ_S2 G3 DDR_ZQ DDR_RESET* R3 MEM_CAM_RESET_L NOTICE OF PROPRIETARY PROPERTY:
OUT 28
2 201 2 201 BRANCH
1%
1/20W
28 OUT
MEM_CAM_CKE J3 DDR_CKE THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
MF 65 28 MEM_CAM_CS_L L4 DDR_CS* THE POSESSOR AGREES TO THE FOLLOWING: PAGE
OUT
201
39 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PP1V35_CAM
27
BYPASS=U4000.A1::4mm BYPASS=U4000.B2::4mm BYPASS=U4000.D2::4mm BYPASS=U4000.K2::4mm

16 IN PCIE_CAMERA_R2D_C_P C4033 1 2
10%
PCIE_CAMERA_R2D_P
16V X5R-CERM 0201
OUT 27
0.1UF
1 C4002 1 C4003 1 C4004 1 C4005 1 C4006 1 C4007 1 C4008 1 C4009 PCIE_CAMERA_R2D_C_N C4032 1 2 PCIE_CAMERA_R2D_N
10UF 10UF 0.47UF 0.1UF 2.2UF 0.1UF 2.2UF 0.1UF 16 IN
10% 16V X5R-CERM 0201
OUT 27
20% 20% 20% 10% 20% 10% 20% 10% 0.1UF
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 4V
CERM-X5R-1 2 6.3V
CERM-X5R 2 10V
X5R-CERM 2 6.3V
CERM-X5R
10V
2 X5R-CERM 2 6.3V
CERM-X5R
0402-1 0402-1 201 0201
BYPASS=U4000.H9::4mm
402 0201
BYPASS=U4000.R9::4mm
402 0201 27 IN PCIE_CAMERA_D2R_C_P C4031 1 2
10%
PCIE_CAMERA_D2R_P
16V X5R-CERM 0201
OUT 16 65
D
27 PP0V675_CAM_VREF
27 IN PCIE_CAMERA_D2R_C_N C4030
0.1UF
1 2 PCIE_CAMERA_D2R_N OUT 16 65
D
10% 16V X5R-CERM 0201
0.1UF
R40221 PP0V675_MEM_CAM_VREFCA
16 IN PCIE_CLK100M_CAMERA_P C4061 1 2
10%
PCIE_CLK100M_CAMERA_C_P
16V X5R-CERM 0201
OUT 27
1K MIN_NECK_WIDTH=0.2000 0.1UF
1%
1/20W
VOLTAGE=0.675V
16 IN PCIE_CLK100M_CAMERA_N C4062 1 2 PCIE_CLK100M_CAMERA_C_N OUT 27
MF
201 2 C4010 1 1 C4011 0.1UF 10% 16V X5R-CERM 0201
0.1UF 0.1UF
10% 10%
6.3V 2 6.3V
CERM-X5R 2
R4023 1
0201
CERM-X5R
0201
VREFCA M8
G7
C1
C9
D2
H2
H9
D9
N1
N9
R1
R9
VREFDQ H1
A1
A8
E9
B2
K2
K8
F1
1K
1%
1/20W
MF R40021 VDDQ VDD
201 2 1K
5%
1/20W
MF
27 IN MEM_CAM_A<0>
MEM_CAM_A<1>
N3
P7
A0 U4000 J1
J9
NC
201 2 27 IN A1 4GB-DDR3L-1866-256MX16 NC
MEM_CAM_A<2> P3 A2 FBGA L1
27 IN NC NC
MEM_CAM_A<3> N2 A3 MT41K256M16LY-107-N L9
27 IN NC
MEM_CAM_A<4> P8 A4 CRITICAL M7
27 IN NC
27 MEM_CAM_A<5> P2 A5
IN
27 MEM_CAM_A<6> R8 A6 DQ0 E3 MEM_CAM_DQ<0> 27
IN BI
27 MEM_CAM_A<7> R2 A7 DQ1 F7 MEM_CAM_DQ<1> 27
IN BI
65 27 MEM_CAM_A<8> T8 A8 DQ2 F2 MEM_CAM_DQ<2> 27
IN BI
27 IN MEM_CAM_A<9> R3 A9 DQ3 F8 MEM_CAM_DQ<3> BI 27
27 IN MEM_CAM_A<10> L7 A10/AP DQ4 H3 MEM_CAM_DQ<4> BI 27
27 IN MEM_CAM_A<11> R7 A11 DQ5 H8 MEM_CAM_DQ<5> BI 27
27 IN MEM_CAM_A<12> N7 A12/BC* DQ6 G2 MEM_CAM_DQ<6> BI 27
27 IN MEM_CAM_A<13> T3 A13 DQ7 H7 MEM_CAM_DQ<7> BI 27
C 27 IN MEM_CAM_A<14> T7 A14 DQ8 D7

C3
MEM_CAM_DQ<10> BI 27 C
DQ9 MEM_CAM_DQ<9> BI 27
27 IN MEM_CAM_BA<0> M2 BA0 DQ10 C8 MEM_CAM_DQ<14> BI 27
27 IN MEM_CAM_BA<1> N8 BA1 DQ11 C2 MEM_CAM_DQ<11> BI 27
27 IN MEM_CAM_BA<2> M3 BA2 DQ12 A7 MEM_CAM_DQ<12> BI 27

27 IN
DQ13 A2 MEM_CAM_DQ<13> BI 27
MEM_CAM_RAS_L J3 RAS* DQ14 B8 MEM_CAM_DQ<15>

R4020
27 27
1 IN BI
27 IN
MEM_CAM_CAS_L K3 CAS* DQ15 A3 MEM_CAM_DQ<8> BI 27
84.5 MEM_CAM_WE_L L3
1% 27 IN WE*
1/20W
MF LDQS F3 MEM_CAM_DQS_P<0> BI 27
2 201 MEM_CAM_CLK_P J7 CK LDQS* G3 MEM_CAM_DQS_N<0> 27
BI
27 IN MEM_CAM_CLK_N K7 CK*
UDQS C7 MEM_CAM_DQS_P<1> BI 27
27 IN MEM_CAM_CKE K9 CKE UDQS* B7 MEM_CAM_DQS_N<1> BI 27
65 27 IN MEM_CAM_CS_L L2 CS*
MEM_CAM_ODT K1 ODT LDM E7 MEM_CAM_DM<0> IN 27
UDM D3 MEM_CAM_DM<1> IN 27
MEM_CAM_ZQ_DDR L8 ZQ
27 IN MEM_CAM_RESET_L T2 RESET*
VSSQ VSS
B1
B9
D1
D8
E2
E8
F9
G1
G9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
1
R4004
B 1%
240 B
1/20W
MF
2 201
CAMERA SENSOR L4009

90-OHM-0.1A-0.7-2GHZ
TAM0605
SYM_VER-1
53 MIPI_CLK_CONN_N 1 4 MIPI_CLK_N 27 65
IN OUT
53 IN MIPI_CLK_CONN_P 2 3 MIPI_CLK_P OUT 27 65
CRITICAL
L4007
90-OHM-0.1A-0.7-2GHZ
TAM0605
SYM_VER-1
53 MIPI_DATA_CONN_N 1 4 MIPI_DATA_N 27 65
IN OUT
53 MIPI_DATA_CONN_P 2 3 MIPI_DATA_P 27 65
IN OUT
A CRITICAL L4010 SYNC_MASTER=X260_KUMAR SYNC_DATE=06/16/2015 A

FERR-120-OHM-1.5A PAGE TITLE
53 PP5V_S0_ALSCAM_F
2
0402-LF
1 PP5V_S0 29 39 50 52 61 Camera 2 of 2
MIN_NECK_WIDTH=0.2000 77.2 mA nominal max DRAWING NUMBER SIZE
VOLTAGE=5V
96.2 mA peak
Apple Inc.
<SCH_NUM> D
C4013 1 REVISION
0.1UF R
<E4LABEL>
10%
10V 2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
X5R-CERM
0201 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
40 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
IPD ZIF CONNECTOR

D Bottom side contacts used
D
Pinout reversed from flex
518S0854
CRITICAL
J4801
502250-8041
F-RT-SM
44
42
R4802
1
15 2 TPAD_SPI_MISO OUT 17
1%
1
65 17 IN
TPAD_SPI_CS_L
3
2 TPAD_SPI_MISO_R
1/20W
MF R4801
65 17 TPAD_SPI_IF_EN 4
201 15
IN
5
TPAD_SPI_MOSI_R 2 1 TPAD_SPI_MOSI IN 17
6 TPAD_SPI_CLK_R 1%
SMC_PME_S4_WAKE_L 7 1/20W
32 31 30 OUT 8 TPAD_SPI_INT_L MF
PP3V3_S4_TPAD_F 9 OUT 17 65
201
29
10 PP3V3_S4_TPAD_F
11
R4803
29
TP_USB_TPADN 12
13
TP_USB_TPADP CRITICAL
30 29 SMC_ACTUATOR_DISABLE_L SMC_ACTUATOR_DISABLE_L 14 15
BI
PP5V_S4_TPAD_F 1 2 TPAD_SPI_CLK
MAKE_BASE=TRUE
39 33 30 BI
SMBUS_SMC_3_SDA 15
16 SMBUS_SMC_3_SCL
29
1%
IN 17
L4801
17 IN 30 33 39
1/20W FERR-120-OHM-1.5A
18 MF
19 201 PP3V3_G3H_KBD_F 2 1 PP3V3_G3H
20 SMC_LSOC_RST 29
18 23 30 31 33 36 40 41 61
PP3V3_G3H_KBD_F 21 OUT 29 41
MIN_NECK_WIDTH=0.2000 0402-LF
29
22 SMC_ONOFF_L VOLTAGE=3.3V
PP5V_S0_KBD_F 23 OUT 29 30 31 32 65
24
R4870
29
PP5V_S0_KBD_F 1
25
26 SMC_LID
29
100K C4801 1
27 OUT 29 30 31
5% 0.1UF
28 1/20W 10%
29 10V
30 MF X5R-CERM 2
31 2 201 0201
32
C 33
35
34 TP_USB_VBUS_EN C
36 CRITICAL
37
39
38 L4802
40 FERR-120-OHM-1.5A
41
29 PP3V3_S4_TPAD_F 2 1 PP3V3_S4 15 18 24 25 26 31 46 50 59 61
MIN_LINE_WIDTH=0.5000 0402-LF
43 MIN_NECK_WIDTH=0.2000
VOLTAGE=3.3V
45
C4802 1
0.1UF
10%
10V
X5R-CERM 2
0201
CRITICAL
L4803
FERR-120-OHM-1.5A
29 PP5V_S4_TPAD_F 2 1 PP5V_S4 24 37 38 42 45 46 50 53 61 63
MIN_LINE_WIDTH=0.5000 0402-LF
67
VOLTAGE=5V
CRITICAL CRITICAL
C4803 1
0.1UF
10%
F4800 L4800 10V
X5R-CERM 2
3A-6A-9V-0.05OHM 30-OHM-5A 0201
61 59 57 52 46 45 41 34 PPBUS_G3H 1 2 PPBUS_G3H_TPAD_FUSED 1 2 PPBUS_G3H_TPAD_FLT
MIN_LINE_WIDTH=0.6000 MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.1000 0603 MIN_NECK_WIDTH=0.1000 CRITICAL
0603 VOLTAGE=8.7V VOLTAGE=8.7V
1 C4800 L4804
B 0.1UF
10%
FERR-120-OHM-1.5A B
2 10V PP5V_S0_KBD_F 2 1 PP5V_S0
XW4801
SM
X5R-CERM
0201
29
MIN_NECK_WIDTH=0.2000 0402-LF
28 39 50 52 61
VOLTAGE=5V
1 2 GND_ACTUATOR
VOLTAGE=0V
C4804 1
0.1UF
10%
10V
X5R-CERM 2
0201
A BYPASS=J4801.20::1.5MM
BYPASS=J4801.22::1.5MM SYNC_MASTER=DEVMLB SYNC_DATE=05/11/2015 A
BYPASS=J4801.26::1.5MM PAGE TITLE
SMC_LSOC_RST
SMC_ONOFF_L
29 41
29 30 31 32 65
Keyboard & Trackpad Conn
DRAWING NUMBER SIZE
SMC_LID
D
29 30 31
<SCH_NUM>
Apple Inc.
1 C4810 1 C4811 1 C4812 R
REVISION
<E4LABEL>
100PF 100PF 100PF
5% 5% 5% NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 25V
C0G 2 25V
C0G 2 25V
C0G
0201 0201 0201 THE INFORMATION CONTAINED HEREIN IS THE <BRANCH>
48 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
U5000
TM4EA231H6ZXRI
LPC_AD<0> D10 BGA G4 SMC_DCIN_VSENSE
14 BI PL3 SYM 1 OF 2 PE3 IN 32 34
14 LPC_AD<1> B13 PL2 PE2 G3 SMC_DCIN_ISENSE 32 34

BI IN
14 LPC_AD<2> C11 PL1 PE1 G2 SMC_PBUS_VSENSE 32 34
BI IN
14 LPC_AD<3> A13 PL0 PE0 G1 SMC_BMON_ISENSE 32 34
BI IN
14 LPC_CLK24M_SMC H10 PM5 PD7 C2 NC_SMC_PPBUS_TPAD_ISENSE 32
IN IN
14 LPC_FRAME_L C12 PL4 PD6 C3 SMC_HS_COMPUTING_ISENSE 32 34
IN IN
65 26 19 15 14 5 PLT_RST_L C13 PL5 PD5 A1 SMC_CPUVCCCORE_VSENSE 32 34 PP3V3_G3H 18 23 29 31 33 36 40 41 61
IN IN
65 14 LPC_SERIRQ (OD) G10 PM4 PD4 A2 NC_SMC_CPUCOREVR_ISENSE 32
BI IN
14 OUT
LPC_CLKRUN_L (OD) G11 PM2 PE5 A3 SMC_CPUVCCGT_VSENSE IN 32 34 L5001
14 LPC_PWRDWN_L F10 PM0 PE4 B3 NC_SMC_CPUGTVR_ISENSE 32 BYPASS=U5000.E6::5MM BYPASS=U5000.F8::5MM
30-OHM-1.7A
IN IN
G12 A4 BYPASS=U5000.E6::5MM BYPASS=U5000.F6::5MM BYPASS=U5000.G6::5MM 1 2
16 OUT
SMC_RUNTIME_SCI_L PM1 PB4 NC_SMC_CPUSAREG_ISENSE IN 32 PP3V3_S5_SMC_VDDA
B11 B4 MIN_LINE_WIDTH=0.2000
65 15 OUT
SMC_WAKE_SCI_L PK5 PB5 NC_SMC_1VPCHREG_ISENSE IN 32 0402 MIN_NECK_WIDTH=0.1000
PD3 D4 NC_SMC_2V7_SSDNAND_ISENSE IN 32
1 C5002 1 C5003 1 C5004 1 C5005 1 C5006
1
R5002
VOLTAGE=3.3V 1 C5001
SMBUS_SMC_0_S0_SCL (OD) D13 PB2/I2C0SCL PD2 D3 NC_SMC_P3V3SSDS5REG_ISENSE 1M 0.1UF
53 33 BI IN 32
1.0UF 0.1UF 0.1UF 0.1UF 0.1UF 5% 10%
53 33 SMBUS_SMC_0_S0_SDA (OD) D12 PB3/I2C0SDA PD1 C1 NC_SMC_1V2S3REG_ISENSE 32
20% 10% 10% 10% 10% 1/20W 2 10V
2 6.3V 2 10V 2 10V 10V 2 10V X5R-CERM
BI IN
53 35 33 14 BI
SMBUS_SMC_1_S0_SCL (OD) N4 PA6 PD0 B1 NC_SMC_OTHER_HI_ISENSE IN 32
X5R
0201-1
X5R-CERM
0201
X5R-CERM
0201
2 X5R-CERM
0201
X5R-CERM
0201
MF
2 201 U5000 0201
53 35 33 14 SMBUS_SMC_1_S0_SDA (OD) L5 PA7 PK0 H4 NC_SMC_PPVCCPCOREREG_ISENSE 32 TM4EA231H6ZXRI
BI IN
33 NC_SMBUS_SMC_2_G3_SCL (OD) N10 PF6 PK1 H3 NC_SMC_PVCCIOCPUREG_ISENSE 32 BYPASS=U5000.H6::5MM BGA
BI IN
K8 H1 BYPASS=U5000.G8::5MM SYM 2 OF 2
33 NC_SMBUS_SMC_2_G3_SDA (OD) PF7 PK2 NC_SMC_WLAN_ISENSE 32
F11 B9
BI
N9 H2
IN
41 36 SMC_RESET_L RST* PC0/SWCLK/TCK SMC_TCK 31 36
39 33 29 SMBUS_SMC_3_SCL (OD) PG0 PK3 NC_SMC_LCDBKLT_ISENSE 32 BYPASS=U5000.H7::5MM
IN
C9
BI
M9 C4
IN
PC1/SWDIO/TMS SMC_TMS 31 36
SMBUS_SMC_3_SDA NC_SMC_P1V2S3MEM_ISENSE
C 39 33 29
33 24
BI
SMBUS_SMC_4_G3_SCL
(OD)
(OD) L9
PG1
PG2
PE7
PE6 C5 NC_SMC_P5V4REG_ISENSE
IN 32
32
1 C5007
0.1UF
1 C5008
0.1UF
1 C5009
0.1UF
31 25 BI
SMC_WIFI_EVENT_L (OD)
A11
M13
PK4 PC3/SWO/TDO C10
B10
SMC_TDO 31 C
BI
L8 B5
IN
SMC_WAKE_L WAKE* PC2/TDI SMC_TDI 31
33 24 SMBUS_SMC_4_G3_SDA (OD) PG3 PN1 NC_SMC_P3V3DSWS5_REG_ISENSE 32
10% 10% 10%
L13
2 10V 10V 2 10V NC_SMC_HIB_L
BI IN
N5 A5 X5R-CERM 2 X5R-CERM X5R-CERM HIB*
33 SMBUS_SMC_5_G3_SCL (OD) PG6 PN0 NC_SMC_PANEL_ISENSE 32 0201 0201 0201 NC B7 NC
BI IN
SMBUS_SMC_5_G3_SDA M5 OMIT_TABLE
33 (OD) PG7 K11
BI
M1 65 31 SMC_CLK32K XOSC0
OMIT_TABLE PC7 CPU_PROCHOT_L 6 31 42
IN
K12
H13 N1
IN
NC_SMC_XOSC1 XOSC1
64 NC_SMC_FAN_0_CTL PM6 PC6 SMC_VCCIO_CPU_DIV2 31
VDDA F3
OUT IN
64 NC_SMC_FAN_0_TACH H11 PM7 PC4 M3 PM_THRMTRIP_L 6 31
IN IN
SYSCLK_CLK12M_SMC F13 OSC0
64 NC_SMC_FAN_1_CTL A12 PK6 PC5 M2 SPI_DESCRIPTOR_OVERRIDE_L 18
65 18 IN
OUT OUT
NC_SMC_OSC1 F12 OSC1 VREFA+ E1 31 PP3V0_S5_AVREF_SMC
64 NC_SMC_FAN_1_TACH B12 PK7 PJ5 B6 CPU_CATERR_L 6 65
VREFA- E2
IN IN
31 SMC_TOPBLK_SWP_L K4 PN2 PJ4 A6 SMC_BT_PWR_EN 25 65
OUT OUT K13
65 34 32 OUT
SMC_SENSOR_PWR_EN A9 PN3
VBAT
GNDA F2
XW5000
SM
PA2/SSI0CLK N2 SMC_PM_G2_EN 46 51
OUT E6 VDDS GNDA F4
34
31 GND_SMC_AVSS 2 1
65 SMC_DEV_SUPPLY_L (IPU) L12 PN4 PA3/SSI0FSS N3 PM_DSW_PWRGD 15 65
IN OUT E7 VDDS
SMC_ACTUATOR_DISABLE_L (OD) M12 PN5 PA4/SSI0RX L4 SMC_DELAYED_PWRGD PLACE_NEAR=U5000.A10:4MM
29 BI OUT 31
F6 VDDS GND A10
NC_SMC_GFX_SELF_THROTTLE (IPD) N13 PN6 PA5/SSI0TX M4 SMC_PROCHOT
64 OUT OUT 31 65
F7 VDDS GND D5
NC_SYS_ONEWIRE L11 PN7
64 BI F8 VDDS GND D6
SMC_CLK12M_EN K3 PH2 PB0 E11 SMC_DEBUGPRT_RX_L
18 OUT
SMC_PCH_SUSACK_L (OD) K2 PH3 PB1 D11 SMC_DEBUGPRT_TX_L
IN 31 65
G6 VDDS GND D9 1 C5020 1 C5021
63 15 OUT OUT 31 65
G7 VDDS GND E5 0.01UF 1.0UF
PB6 E3 PM_RSMRST_L 10% 20%
IN 15 46 63
G8 VDDS GND E8 2 10V 2 6.3V
CPU_PECI_R C6 PJ7 PB7 E4 NC_SMC_GFX_THROTTLE_L (IPU) X5R-CERM X5R
31 BI BI 64
H6 VDDS GND E9 0201 0201-1
SMC_PECI_L C7 PJ6
31 OUT H7 VDDS GND E10
PF0 L10 NC_SPI_SMC_MISO BYPASS=U5000.E1:F2:1MM
IN 64
GND F5 BYPASS=U5000.E1:F2:1MM
SMC_CHGR_INT_L J10 PP0 PF1 N11 NC_SPI_SMC_MOSI
65 41 IN OUT 64
PP1V2_S5_SMC_VDDC D7 VDDC GND F9
NC_SMC_DP_HPD_L H12 PP1 PF2 N12 NC_SPI_SMC_CLK MIN_LINE_WIDTH=0.2000
64 IN OUT 64
MIN_NECK_WIDTH=0.1000 H9 VDDC GND G5
SMC_PME_S4_WAKE_L K6 PP2 PF3 M11 NC_SPI_SMC_CS_L VOLTAGE=1.2V
32 31 29 IN OUT 64
J1 VDDC GND G9
SMC_PME_S4_DARK_L J11 PP3 PF4 K10 S5_PWRGD
B B
32 31 25 24 45 46 51
IN IN J9 VDDC GND H5
46 31 SMC_PMIC_INT_L J12 PP4 PF5 M10 PMIC_SYS_PWROK 15 46 51
BI IN J13 VDDC GND H8
32 31 SMC_SENSOR_ALERT_L (OD) K7 PP5
IN
GND J5
64 IN
NC_SMC_ACTUATOR_ACTIVE_L A7 PP6 PG4 M8 SMC_CBC_ON IN 41 65
J6
GND
31 29 IN
SMC_LID L6 PP7 PG5 N8 NC_SMC_GFX_OVERTEMP (IPD) IN 64
J7
GND
GND J8
63 15 IN
SMC_PCH_SUSWARN_L D2 PQ0 PH0 L2 ALL_SYS_PWRGD IN 42 46 51
K9
GND
33 24 IN
SMC_USBC_INT_L D1 PQ1 PH1 L1 SMC_THRMTRIP OUT 31
65 63 41 34 31 SMC_BC_ACOK F1 PQ2
IN
67 46 15 PM_SLP_S0_L M6 PQ3 PH4 K1 PM_PWRBTN_L (OD) 15 BYPASS=U5000.H9::5MM BYPASS=U5000.H9::5MM BYPASS=U5000.J1::5MM BYPASS=U5000.J13::5MM
IN OUT
N6 J3 BYPASS=U5000.D7::5MM BYPASS=U5000.D7::5MM BYPASS=U5000.J9::5MM BYPASS=U5000.J9::5MM
65 51 50 49 46 15 IN
PM_SLP_S3_L PQ4 PH5 PM_SYSRST_L (OD) OUT 15
63 51 50 47 46 15 PM_SLP_S4_L L7 PQ5 PH6 J2 NC_TCON_BKLT_PWM 64

IN OUT
51 50 45 15 IN
PM_SLP_S5_L M7 PQ6 PH7 J4 SMC_ADAPTER_EN OUT 31
1 C5010 1 C5017 1 C5015 1 C5016 1 C5014 1 C5012 1 C5013 1 C5011
65 32 31 29 IN
SMC_ONOFF_L N7 PQ7 1.0UF 1.0UF 0.1UF 0.1UF 1.0UF 0.1UF 0.1UF 0.1UF
20% 20% 10% 10% 20% 10% 10% 10%
PJ0 D8 SMC_OOB1_D2R_L 59 2 6.3V 2 6.3V 2 10V 2 10V 2 6.3V 2 10V 2 10V 2 10V
IN X5R X5R X5R-CERM X5R-CERM X5R X5R-CERM X5R-CERM X5R-CERM
64 NC_WIFI_DEBUGPRT_R2D_L L3 PA0/U0RX PJ1 A8 SMC_OOB1_R2D_L 59 65
0201-1 0201-1 0201 0201 0201-1 0201 0201 0201
IN OUT
64 NC_WIFI_DEBUGPRT_D2R_L K5 PA1/U0TX PJ2 B8 NC_SMC_SOC_POR 64
OUT OUT
PJ3 C8 TP_SMC_DEBUGPRT_EN_L 63
OUT
63 TP_SMC_DEV_MLB (IPD when sampling) E13 PL7
IN
65 25 SMC_WIFI_PWR_EN E12 PL6 PM3 G13 PM_BATLOW_L 15
OUT OUT
NOTE:
SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.
A NOTE:
Unused pins have "SMC_Pxx" names. Unused SYNC_MASTER=DEVMLB SYNC_DATE=07/17/2015 A
PAGE TITLE
pins designed as outputs can be left floating,
those designated as inputs require pull-ups. SMC
DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
50 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SMC AVREF Supply PROCHOT/THRMTRIP Support PECI Support

U5165 PP1V_S3 6 8 12 15 31 42 50 61
REF3330
CRITICAL
QFN
CRITICAL R5158 Q5150 D 3
5 IN 100
36 33 31 30 29 23 18 PP3V3_G3H OUT 8 PP3V0_S5_AVREF_SMC 30 42 30 6 BI
CPU_PROCHOT_L 1 2 SMC_PROCHOT_L DMN32D2LFB4
61 41 40 MIN_LINE_WIDTH=0.0950 DFN1006H4-3
1%
NC0 1
NC
VOLTAGE=3.0V 1/20W
MF
Q5159
DMN5L06VK-7
SYM_VER_2
201 6 D
2
D
NC1
NC2 3
NC
NC
PLACE_NEAR=Q5159.6:5MM
SOT563
1 G S 2 D
VER 3
C5165 1 NC3 6
7
NC C5166 1 1 C5167 30 IN
SMC_PECI_L
1.0UF NC4 NC 10UF 0.1UF
4 GND
20% 20% 10% G 2 From SMC
6.3V 2 2 10V 1 S
X5R
0201-1
6.3V 2
CERM-X5R
0402-1
X5R-CERM
0201
R5134
SMC_PROCHOT CPU_PECI_R 1
43 2 CPU_PECI
IN 30 65 30 OUT BI 6
GND_SMC_AVSS To SMC 5%
1/20W From/To CPU/PCH
R5159
30 34
MIN_LINE_WIDTH=0.4000 NOSTUFF MF
VOLTAGE=0V 100 C5134 1
1
R5151 201
30 6 OUT
PM_THRMTRIP_L 1 2 SMC_THRMTRIP_L 47PF 330
5% 5%
1%
1/20W
MF
Q5159
DMN5L06VK-7
25V 2
C0G
1/20W
MF
201 3 D 0201 2 201
SOT563 PLACE_NEAR=Q5150.2:5MM
PLACE_NEAR=Q5159.3:5MM
VER 3
4 S G 5
SMC_THRMTRIP IN 30 31
C C
65 63 41 34 31 30 SMC_BC_ACOK SMC_BC_ACOK 30 31 34 41 63 65 61 50 42 31 15 12 8 6 PP1V_S3

MAKE_BASE=TRUE
1
R5197
100K
1%
1/20W
R5112 MF
2 201
PM_CLK32K_SUSCLK_R 1
22 2 SMC_CLK32K SMC_VCCIO_CPU_DIV2
16 IN OUT 30 65 30
Top-Block Swap 5%
1/20W
MF
201 1
R5196
PP3V3_S0 Place near CPU 100K
5 6 14 15 16 17 19 23 26 27 31 1%
33 34 35 39 46 50 51 53 61 67 1/20W
MF
2 201
R5182 1
1K
5%
1/20W
MF
201 2 R5183
SMC_TOPBLK_SWP_L 1
1K 2 PCH_STRP_TOPBLK_SWP_L
30 IN OUT 14
5%
1/20W
MF
201
B 61 41 40 36 33 31 30 29 23 18
61 59 50 46 29 26 25 24 18 15
PP3V3_G3H
PP3V3_S4
B
67
27 26 23 19 17 16 15 14 6 5
61 53 51 50 46 39 35 34 33 31
PP3V3_S0
32 30 29 SMC_PME_S4_WAKE_L R5166 100K 1 2
32 30 25 24 SMC_PME_S4_DARK_L R5167 100K 1 2
5% 1/20W MF 201
30 25 SMC_WIFI_EVENT_L R5168 100K 1 2

5% 1/20W MF 201
46 30 SMC_PMIC_INT_L R5169 100K 1 2

5% 1/20W MF 201
65 32 30 29 SMC_ONOFF_L R5170 10K 1 2

5% 1/20W MF 201
32 30 SMC_SENSOR_ALERT_L R5172 10K 1 2

5% 1/20W MF 201
30 29 SMC_LID R5171 330K 1 2

5% 1/20W MF 201
5% 1/20W MF 201
65 30 SMC_DEBUGPRT_TX_L R5175 20K 1 2

65 30 SMC_DEBUGPRT_RX_L R5176 20K 1 2
5% 1/20W MF 201
36 30 SMC_TMS R5177 10K 1 2

5% 1/20W MF 201
30 SMC_TDO R5178 10K 1 2

5% 1/20W MF 201
30 SMC_TDI R5179 10K 1 2

5% 1/20W MF 201
36 30 SMC_TCK R5180 10K 1 2

5% 1/20W MF 201
65 63 41 34 31 30 SMC_BC_ACOK R5187 100K 1 2

5% 1/20W MF 201
30 SMC_ADAPTER_EN R5185 100K 1 2

5% 1/20W MF 201
31 30 SMC_THRMTRIP R5186 10K 1 2

5% 1/20W MF 201
30 SMC_DELAYED_PWRGD R5191 100K 1 2

5% 1/20W MF 201
5% 1/20W MF 201
PAGE TITLE
SMC Shared Support

DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
51 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
34 32 30 SMC_DCIN_VSENSE SMC_DCIN_VSENSE 30 32 34
MAKE_BASE=TRUE
34 32 30 SMC_DCIN_ISENSE SMC_DCIN_ISENSE 30 32 34
MAKE_BASE=TRUE
34 32 30 SMC_PBUS_VSENSE SMC_PBUS_VSENSE 30 32 34
MAKE_BASE=TRUE
34 32 30 SMC_BMON_ISENSE SMC_BMON_ISENSE 30 32 34
MAKE_BASE=TRUE
32 30 NC_SMC_PPBUS_TPAD_ISENSE NC_SMC_PPBUS_TPAD_ISENSE 30 32
MAKE_BASE=TRUE
34 32 30 SMC_HS_COMPUTING_ISENSE SMC_HS_COMPUTING_ISENSE 30 32 34
MAKE_BASE=TRUE
34 32 30 SMC_CPUVCCCORE_VSENSE SMC_CPUVCCCORE_VSENSE 30 32 34
MAKE_BASE=TRUE
D
32 30 NC_SMC_CPUCOREVR_ISENSE NC_SMC_CPUCOREVR_ISENSE
MAKE_BASE=TRUE
30 32
D
34 32 30 SMC_CPUVCCGT_VSENSE SMC_CPUVCCGT_VSENSE 30 32 34
MAKE_BASE=TRUE
32 30 NC_SMC_CPUGTVR_ISENSE NC_SMC_CPUGTVR_ISENSE 30 32
MAKE_BASE=TRUE
32 30 NC_SMC_CPUSAREG_ISENSE NC_SMC_CPUSAREG_ISENSE 30 32
MAKE_BASE=TRUE
32 30 NC_SMC_1VPCHREG_ISENSE NC_SMC_1VPCHREG_ISENSE 30 32
MAKE_BASE=TRUE
32 30 NC_SMC_2V7_SSDNAND_ISENSE NC_SMC_2V7_SSDNAND_ISENSE 30 32
MAKE_BASE=TRUE
32 30 NC_SMC_P3V3SSDS5REG_ISENSE NC_SMC_P3V3SSDS5REG_ISENSE 30 32
MAKE_BASE=TRUE
32 30 NC_SMC_1V2S3REG_ISENSE NC_SMC_1V2S3REG_ISENSE 30 32
MAKE_BASE=TRUE
32 30 NC_SMC_OTHER_HI_ISENSE NC_SMC_OTHER_HI_ISENSE 30 32
MAKE_BASE=TRUE
32 30 NC_SMC_PPVCCPCOREREG_ISENSE NC_SMC_PPVCCPCOREREG_ISENSE 30 32
MAKE_BASE=TRUE
32 30 NC_SMC_PVCCIOCPUREG_ISENSE NC_SMC_PVCCIOCPUREG_ISENSE 30 32
MAKE_BASE=TRUE
32 30 NC_SMC_WLAN_ISENSE NC_SMC_WLAN_ISENSE 30 32
MAKE_BASE=TRUE
32 30 NC_SMC_LCDBKLT_ISENSE NC_SMC_LCDBKLT_ISENSE 30 32
MAKE_BASE=TRUE
32 30 NC_SMC_P1V2S3MEM_ISENSE NC_SMC_P1V2S3MEM_ISENSE 30 32
MAKE_BASE=TRUE
32 30 NC_SMC_P5V4REG_ISENSE NC_SMC_P5V4REG_ISENSE 30 32
MAKE_BASE=TRUE
32 30 NC_SMC_P3V3DSWS5_REG_ISENSE NC_SMC_P3V3DSWS5_REG_ISENSE 30 32
MAKE_BASE=TRUE
32 30 NC_SMC_PANEL_ISENSE NC_SMC_PANEL_ISENSE 30 32
MAKE_BASE=TRUE
C SMC_SENSOR_PWR_EN 30 32 34 65
C
65 34 32 30 SMC_SENSOR_PWR_EN SMC_SENSOR_PWR_EN 30 32 34 65
MAKE_BASE=TRUE
R5213
NAND_OVERTMP_ALERT_L 1
100 2
35 IN
5%
1/20W
MF
201
R5214
CPUTHMSNS_ALERT_L 1
100 2
35 IN
NOSTUFF 5%
1/20W
R5211 MF
201
CPUBMONSNS_ALERT_L 1
100 2 SMC_SENSOR_ALERT_L
35 IN OUT 30 31
5%
1/20W
MF
201
SMC_PME_S4_DARK_L
B B
32 31 30 25 24 IN
32 31 30 25 24 IN
SMC_PME_S4_DARK_L SMC_PME_S4_DARK_L OUT 24 25 30 31 32
MAKE_BASE=TRUE
32 31 30 29 IN
SMC_PME_S4_WAKE_L SMC_PME_S4_WAKE_L OUT 29 30 31 32
MAKE_BASE=TRUE
Debug Power "Buttons"

PLACE_SIDE=TOP
SILK_PART=PWR_BTN
R5226
RES
0603-NSP
2 1 SMC_ONOFF_L 29 30 31 65
OUT
PLACE_SIDE=BOTTOM
SILK_PART=PWR_BTN
R5225
RES
0603-NSP
2 1
PAGE TITLE
SMC Project Support

DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
52 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Sunrise Point LP S0 SMBus "0" Connections SMC "0" SMBus S0 Connections SMC "5" SMBus G3H Connections
67
27 26 23 19 17 16 15 14 6 5
61 53 51 50 46 39 35 34 33 31
PP3V3_S0 61 41 40 36 33 31 30 29 23 18 PP3V3_G3H
Pullups are on eDP

Wildcat Point LP R5300 1 1
R5301 SMC connector page and
Internal DP SMC R53801 1
R5381 Battery Charger
1K
5% 5%
1K gated by EDP_PANEL_PWR
U5000 R5382 2.0K
5% 5%
2.0K
U0500 1/20W 1/20W U5000 J8300 1
0 2
1/20W 1/20W BANSURI - U7100
MF MF (MASTER) MF MF
(MASTER) 201 2 2 201 (MASTER) 5% 0201
201 2 2 201 (Write: 0x12 Read: 0x13)
1/20W MF
SMBUS_PCH_CLK SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SCL SMBUS_SMC_5_G3_SCL SMBUS_SMC_5_G3_SCL_R SMBUS_SMC_5_G3_SCL_R
D
14 53 33 30 30 33 53 30 46 41 40 33 33 40 41
46
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
D SMBUS_PCH_DATA SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDA SMBUS_SMC_5_G3_SDA 46 41 40 33 SMBUS_SMC_5_G3_SDA_R SMBUS_SMC_5_G3_SDA_R 33 40 41
R5383
14 53 33 30 30 33 53 30
46
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
1
0 2
5% 0201
1/20W MF
Battery
J6950
SMC "4" SMBus G3H Connections (Write: 0x16 Read: 0x17)
SMBUS_SMC_5_G3_SCL_R 33 40 41
36 33 31 30 29 23 18
61 41 40
PP3V3_G3H 46
SMBUS_SMC_5_G3_SDA_R 33 40 41
46
UPC Port XA
SMC R5330 1 R5331 1 1
R5332
10K 2.2K 2.2K U3100
5% 5% 5%
U5000 1/20W
MF
1/20W
MF
1/20W
MF
(Write: 0x70 Read: 0X71) Banjo
(MASTER) 201 2 201 2 2 201 (All-Ace W:0xD6 R: 0xD7)
U7800
SMBUS_SMC_4_G3_SCL SMBUS_SMC_4_G3_SCL 24 30 33 (Write: 0x68 Read: 0x69)
Sunrise Point LP S0 I2C "2" Connections 33 30 24
MAKE_BASE=TRUE
SMBUS_SMC_4_G3_SDA SMBUS_SMC_4_G3_SDA 24 30 33 SMBUS_SMC_5_G3_SCL_R 33 40 41
46
MAKE_BASE=TRUE
61 50 48 24 17 13 9 PP1V8_SUS 33 30 24 SMC_USBC_INT_L SMC_USBC_INT_L 24 30 33 SMBUS_SMC_5_G3_SDA_R 33 40 41
46
MAKE_BASE=TRUE
UPC Port XA
Sunrise Point LP R5320 1 R5321 1 1
R5322
10K 4.7K 4.7K U3100
5% 5% 5%
U0500 1/20W 1/20W 1/20W (Write: 0x70 Read: 0X71)
MF MF MF
C
(MASTER) 201 2 201 2 2 201 (All-Ace W:0xD6 R: 0xD7)
SMC "3" SMBus S0 Connections C
33 24 17 I2C_UPC_SCL I2C_UPC_SCL 17 24 33
MAKE_BASE=TRUE
33 24 17 I2C_UPC_SDA I2C_UPC_SDA 17 24 33
67
27 26 23 19 17 16 15 14 6 5 PP3V3_S0
MAKE_BASE=TRUE 61 53 51 50 46 39 35 34 33 31
33 24 17 UPC_I2C_INT_L UPC_I2C_INT_L 17 24 33
MAKE_BASE=TRUE
SMC R53901 1
R5391 Trackpad
2.0K 2.0K
5% 5% J4800
U5000 1/20W 1/20W
MF MF (Write: 0x90 Read: 0x91)
(MASTER) 201 2 2 201
39 33 30 29 SMBUS_SMC_3_SCL SMBUS_SMC_3_SCL 29 30 33
SMC "2" SMBus Connections 39 33 30 29

MAKE_BASE=TRUE
SMBUS_SMC_3_SDA SMBUS_SMC_3_SDA
39
29 30 33
MAKE_BASE=TRUE 39
RIO
SMC Unused J6799
(Write: 0x?? Read: 0x??)
U5000 Uxxxx
(MASTER) SMBUS_SMC_3_SCL 29 30 33
39
33 30 NC_SMBUS_SMC_2_G3_SCL NC_SMBUS_SMC_2_G3_SCL 30
MAKE_BASE=TRUE 33 SMBUS_SMC_3_SDA 29 30 33
39
33 30 NC_SMBUS_SMC_2_G3_SDA NC_SMBUS_SMC_2_G3_SDA 30
33
MAKE_BASE=TRUE
B Sunrise Point LP S0 "SMLink 0" Connections B

67
27 26 23 19 17 16 15 14 6 5 PP3V3_S0
61 53 51 50 46 39 35 34 33 31
SMC S0 "1" SMBus Connections
Sunrise Point LP R53101 1
R5311 67
27 26 23 19 17 16 15 14 6 5
61 53 51 50 46 39 35 34 33 31
PP3V3_S0
8.2K 8.2K
5% 5%
U0500 1/20W 1/20W
MF MF
(MASTER) 201 2 2 201 SMC R53601 1
R5361 Sys Temp Sense & CPU HS Thr
SML_PCH_0_CLK 4.7K 4.7K
14 5% 5%
MAKE_BASE=TRUE U5000 1/20W 1/20W EMC1704-02: U5800
MF MF
14 SML_PCH_0_DATA (MASTER) 201 2 2 201 (Write: 0x98 Read: 0x99)
MAKE_BASE=TRUE
35 33 30 14 SMBUS_SMC_1_S0_SCL SMBUS_SMC_1_S0_SCL 14 30 33
53 MAKE_BASE=TRUE 35 53
35 33 30 14 SMBUS_SMC_1_S0_SDA SMBUS_SMC_1_S0_SDA 14 30 33
53 MAKE_BASE=TRUE 35 53
Sunrise Point LP S0 "SMLink 1" Connections

NAND Temp Sense
HPA0033AI: U5880
(Write: 0x92 Read: 0x93)
SMBUS_SMC_1_S0_SCL 14 30 33
35 53
Sunrise Point LP SMBUS_SMC_1_S0_SDA 14 30 33

35 53
U0500
A (Write: 0x88 Read: 0x89) SYNC_MASTER=DEVMLB SYNC_DATE=05/11/2015 A
PAGE TITLE
SMBUS_SMC_1_S0_SCL
35 33 30 14
53
35 33 30 14 SMBUS_SMC_1_S0_SDA ALS SMBus Connections
53 J4002 DRAWING NUMBER SIZE
(Write: 0x72 Read 0x73)

Apple Inc.
<SCH_NUM> D
REVISION
SMBUS_SMC_1_S0_SCL 14 30 33
35 53
R
<E4LABEL>
SMLink 1 is slave port to SMBUS_SMC_1_S0_SDA NOTICE OF PROPRIETARY PROPERTY: BRANCH
access PCH
14 30 33
<BRANCH>
53 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
POR VOLTAGE / CURRENT SENSORS : TO BE USED IN PRODUCTION
IC0R : COMPUTING High Side Current Sense

VP0R: PBUS Voltage Sense Enable & Filter
D
EDP Current :12A
D MAX Vdiff : 24 mV
67
27 26 23 19 17 16 15 14 6 5
61 53 51 50 46 39 35 34 33 31
PP3V3_S0
Q5400 GAIN : 100X
NTUD3169CZ BYPASS=U5450.3::5MM
SOT-963
PLACE_NEAR=R5450:5MM
1 C5450
3
N-CHANNEL 0.1UF
6 PBUSVSENS_EN_L V+ 10% PLACE_NEAR=U5000.B3:11mm
PPBUS_S5_HS_COMPUTING_ISNS 2 6.3V
D
61 48 47 44 43 42
U5450 CERM-X5R
R5455
R54021 CRITICAL INA214 6
0201
4.53K 2
100K R5450 2 4 34 ISNS_HS_COMPUTING_N 5 IN- SC70 OUT ISNS_HS_COMPUTING_IOUT 1 SMC_HS_COMPUTING_ISENSE 30 32
32 30 IN
SMC_SENSOR_PWR_EN 2 G 1%
OUT
65
S 1/20W 0.002 CRITICAL 1%
1/20W
PLACE_NEAR=U5000.B3:11mm
1
MF
201 2
1%
1W 34 ISNS_HS_COMPUTING_P 4 IN+
(100V/V)
REF 1 R54511 MF
201
1 C5455
Max VOut: 3V at 10.44V Input CYN
0612 1 3 20K 0.22UF
3 PBUS_S0_VSENSE 5% 20%
GND 1/20W PLACEMENT_NOTEs: 2 6.3V
X5R
D 61 59 57 52 46 45 41 34 29 PPBUS_G3H MF 0201
2
201 2
1
R5403 Place close to SMC
GND_SMC_AVSS 30 31 34
5 G
68K PLACE_NEAR=U5000.E2:11MM (For R and C)
1%
S 1/20W
57 52 46 45 41 34 29 PPBUS_G3H MF
61 59 RTHEVENIN = 19530 Ohms
2 201
4
R5401
100K
1
P-CHANNEL
R5404 1
SMC_PBUS_VSENSE
PLACE_NEAR=U5000.E2:11MM
OUT 30 32
Need to set gains for ULX

1%
1/20W
PLACE_NEAR=F7040.2:11MM
27.4K
1 C5404
0.047UF
MF
201 2
1%
1/20W
MF
10%
6.3V
2 X5R
EMC1704 Computing High Side GainPLACE_NEAR=U5460.3:1mm
Stage
201 2
PBUSVSENS_EN_L_DIV 201
67
PP3V3_S0 XW5460
27 26 23 19 17 16 15 14 6 5 SM
GND_SMC_AVSS 30 31 34 61 53 51 50 46 39 35 34 33 31
1 2 ISNS_HS_GAIN_P OUT 35
VD0R: DC-In Voltage Sense Enable & Filter PLACE_NEAR=U5000.E2:11MM

R54621
C 1K C
1 C5461 1%
1/20W
Q5410 0.1UF
10%
MF
201 2
NTUD3169CZ 2 6.3V
SOT-963 CERM-X5R ISNS_HS_GAIN_N 35
N-CHANNEL 0201 OUT
6 DCINVSENS_EN_L
D PLACE_NEAR=R7050:5MM R54611
R5412 1 27K
3
V+ 1%
65
SMC_BC_ACOK 2 G
137K 1/20W
31 30
63 41 IN
S
1%
1/20W
MF Max VOut: 3V at 21V Input CKPLUS_WAIVE=PdifPr_badTerm
U5460 MF
201 2
201 2 INA211 6
1 34 ISNS_HS_COMPUTING_P 5 IN- SC70 OUT ISNS_HS_GAIN_OUT
3 DCIN_S5_VSENSE CKPLUS_WAIVE=NdifPr_badTerm CRITICAL
D 34 ISNS_HS_COMPUTING_N 4 IN+
(500V/V)
REF 1 1
R5463
R54131 5%
20K
5 G
27.4K GND 1/20W
1% MF
2
S 1/20W 2 201
PPDCIN_G3H MF PLACE_NEAR=U5000.E1:11MM
41 24
65 61
4
201 2 RTHEVENIN = 4573 Ohms GAIN: 500X
P-CHANNEL SMC_DCIN_VSENSE 30 32
OUT
R54111 PLACE_NEAR=Q7010.2:11MM
R54141
100K
1% 4.53K
1 C5414
1/20W 1% 0.22UF
MF 1/20W 20%
201 2 MF 2 X5R 6.3V
201 2 0201
PDCINVSENS_EN_L_DIV
B B
VC0C : CPU VCC CORE Voltage Sense

XW5420
SM R5421
PPVCORE_S0_CPU 1 2 CPUVCCCORE_VSENSE_IN 1
4.53K 2 SMC_CPUVCCCORE_VSENSE
61 43 11 8 OUT 30 32
CHARGER BMON High Side Current Sense 1%

1/20W
MF
201
1 C5421
PLACE_NEAR=U5000.F2:11MM
0.22UF
20%
R5420 2 6.3V
X5R
0201
CHGR_BMON 1
300K 2 SMC_BMON_ISENSE
41 30 32
IN OUT
1% PLACE_NEAR=U5000.F2:11MM
1/20W
ISL6259 Gain: 36x MF
201
1 C5420
Scale: 2.78A / V 3300PF
10%
Max VOut: 3.3V at 9.167A 10V 2 X7R-CERM
EDP Current: 310A
0201
VCGC : CPU VCCGT Voltage Sense
DC-IN (AMON) Current Sense XW5421
SM R5422
PPVCORE_S0_GT 1 2 CPUVCCGT_VSENSE_IN 1
4.53K 2 SMC_CPUVCCGT_VSENSE
61 44 12 8 OUT 30 32
1%
A R5430 1/20W
MF 1 C5422 A
CHGR_AMON 1
45.3K 2 SMC_DCIN_ISENSE
201
0.22UF SYNC_MASTER=DEVMLB SYNC_DATE=07/06/2015
41 IN OUT 30 32
20% PAGE TITLE
2 6.3V
1%
1/20W
MF 1
C5430
X5R
0201 Voltage & Current Sensing
201
2.2NF GND_SMC_AVSS DRAWING NUMBER SIZE
Sense R is R7120, 20mOhm 10%

2 X5R-CERM
30 31 34
Apple Inc.
<SCH_NUM> D
ISL6259 Gain: 20x 10V REVISION
0201
Max VOut: 1.4V at 8.25A
R
<E4LABEL>
Scale: 2.5A / V NOTICE OF PROPRIETARY PROPERTY: BRANCH
EDP Current: 3.5A THE INFORMATION CONTAINED HEREIN IS THE

<BRANCH>
54 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
POR THERMAL SENSORS : TO BE USED IN PRODUCTION
D D
CPU Proximity, Inlet ,DDR and BMON THR Sensor
PLACE_NEAR=U5500.2:5mm VOLTAGE=3.3V
R5500 MIN_NECK_WIDTH=0.2000
67
PP3V3_S0 1
47 2 PP3V3_S0_CPUTHMSNS_R
27 26 23 19 17 16 15 14 6 5
61 53 51 50 46 39 35 34 33 31
5%
1/20W
MF
1 C5500
201 0.1UF
10%
PLACE_NEAR=U5500.3:5mm 2 6.3V
CERM-X5R
0201
INLET_THMSNS_D1_P 1
R5506
3 CRITICAL 100K
1
Placement note (Wireless Prox): 1
PLACE_NEAR=Q5530:3MM
C5530 NO_XNET_CONNECTION=1 C5501 1
VDD
5%
1/20W
Place Q5530 next to J3501 on Bot side

Q5530 1
47PF
PLACE_NEAR=U5500.2:5mm
2200PF
10% U5500
MF
2 201
BC846BLP 5% PLACE_NEAR=U5500.3:5mm
10V
X7R-CERM 2 EMC1704-2
DFN1006H4-3 2 25V
C0G 0201
2 QFN
0201 2 DP1 THERM* 9 CPUBMONSNS_ALERT_L 32
OUT
INLET_THMSNS_D1_N 3 DN1 ALERT* 10 CPUTHMSNS_ALERT_L 32
CPUTHMSNS_D2_P OUT
PLACE_NEAR=Q5510:3MM 4 DP2/DN3 SMDATA 11 SMBUS_SMC_1_S0_SDA

3 2 BI 14 30 33 35 53
1 C5511 C5563 1
Q5560 C5502 1 PLACE_NEAR=U5500.4:5mm
5 DN2/DP3 SMCLK 12 SMBUS_SMC_1_S0_SCL
Placement note (Charger Prox): Q5510 1
5%
47PF 47PF
5%
1 DFN1006H4-3 2200PF
10%
BI 14 30 33 35 53
BC846BLP 2 25V 25V 2 BC846BLP 10V 16 SENSE+ ADDR_SEL 6 CPUTHMSNS_ADDR_SEL

Place Q5510 near L7130 on TOP side
DFN1006H4-3 C0G C0G X7R-CERM 2 PLACE_NEAR=U5500.5:5mm
2 0201 0201 0201 15 SENSE-
PLACE_NEAR=Q5560:3MM 3 GPIO 7
CPUTHMSNS_D2_N 13 DUR_SEL
NC 1
R5505
34 OUT
ISNS_HS_GAIN_P 14 0
TH_SEL 5%
ISNS_HS_GAIN_N
C Placement note (DRAM Prox):
34 OUT
CPUTHMSNS_DUR_SEL GND THRM_PAD
1/20W
MF
2 0201
C
Place Q5560 between U2300 and U2500 on the Bot side CPUTHMSNS_TH_SEL
17
NOSTUFF NOSTUFF
Write Address: 0x98
R5503 1
R55041 Read Address: 0x99
10K 10K
5% 5%
1/20W 1/20W
MF MF
201 2 201 2 Placement note: (CPU Prox)
Place U5500 next to L7310/L7320 on the Top Side
NAND Temp Sensor

67
27 26 23 19 17 16 15 14 6 5
61 53 51 50 46 39 35 34 33 31
PP3V3_S0
PLACE_NEAR=U5580.5:5mm 1 C5560
0.1UF
B 10%
2 6.3V
CERM-X5R
B
0201
5
V+
U5580 Placement note: (NAND Prox)
HPA00330AI Place U5580 next to SSD Gumstick
SOT563
53 35 33 30 14 SMBUS_SMC_1_S0_SDA 6
SDA ADD0
4
53 35 33 30 14 SMBUS_SMC_1_S0_SCL 1
SCL ALERT
3 NAND_OVERTMP_ALERT_L OUT 32
GND
2
SENSORS
A SYNC_MASTER=X260_KUMAR SYNC_DATE=06/16/2015 A
PAGE TITLE
Temperature Sensing
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SPI ROM - Combo BGA Footprint (3 vendors)

Quad-IO Mode (Mode 0 & 3) supported.
PP3V3_SUS
61 50 49 46 17 16 14 13 9 SPI Frequency: 50MHz for CPU, 20MHz for SMC.
SPI+SWD SAM Connector
CRITICAL
BYPASS=U6101::3mm J6100
C6101
A1
1 BYPASS=U6100::3mm DF40PC-12DP-0.4V-51
0.1UF C6100 1 M-ST-SM
D
D 10%
2 16V
X5R-CERM
VCC
U6100 0.1UF
10% 61 41 40 33 31 30 29 23 18 PP3V3_G3H
14 13
0201 W25Q64FVBYIQ 16V

X5R-CERM 2 2 1
8
0201
VCC SI/SIO0/ SPI_ALT_MOSI 4 3 SPI_ALT_CLK
D1 36 36
U6101 36 SPI_MLB_CLK C1 SCLK/C/CLK DQ1/DO/IO1 SPI_MLB_MOSI 36
SPI_ALT_MISO 6 5 SPI_ALT_CS_L
SO/SIO1/ B2
36 36
74LVC1G99 SPI_MLB_MISO 36
2A SOT833 Y 7 SPI_MLBROM_CS_L A2 CS* DQO/DI/IO0 36 SPI_ALT_IO<2> 8 7 SPIROM_USE_MLB BI 17 36
36 SPI_MLB_CS_L 3B CRITICAL 36 SPI_ALT_IO<3> 10 9 SMC_TMS (SWDIO) 30 31

OE* 1 36 SPI_MLB_IO<2> C2 SIO2/W*/VPP/
BI
36 17 SPIROM_USE_MLB 5C DQ2/WP/IO2 41 30 SMC_RESET_L 12 11 SMC_TCK (SWCLK) 30 31
OUT OUT
6D 36 SPI_MLB_IO<3> B1 SIO3/HOLD*/
GND DQ3/IO3 6
NC 16 15
NC
7
4
1 3V-64MBIT NC NC
NC NC 8
2 WLBGA-COMBO-J92 NC NC
NC NC 9
3 NC NC 516S00024
PLACE_NEAR=U6100.1:12MM NC NC CRITICAL 10
4 NC NC
NC NC OMIT_TABLE 11
5 NC NC
NC NC 12
NC NC
GND/VSS
D2
C C
BootROM SPI Bus Series Termination

SPI_ALT_IO<3> 36
PLACE_NEAR=J6100.9:5MM
SPI_ALT_IO<2> 36
SPI_ALT_MISO 36
SPI_ALT_MOSI
SPI_ALT_CLK
36
36
Sam Card ROM Slave
SPI_ALT_CS_L 36
1
R6133 1
R6132 1
R6128 1
R6127 1
R6126 1
R6125
0 0 0 0 0 0
5% 5% 5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
MF MF MF MF MF MF
2 0201 2 0201 2 0201 2 0201 2 0201 2 0201
R6120
SPI_CS0_L 1
11 2 SPI_MLB_CS_L
14 IN 36
PLACE_NEAR=U6101.3:3MM
1%
1/20W
R6121 MF
201
SPI_CLK 1
11 2 SPI_MLB_CLK
14 IN 36
1%
1/20W
CPU Master MF
R6122 SPI ROM Slave
B 14 BI
SPI_MOSI
201
1
11 2 SPI_MLB_MOSI 36
B
(SPI_IO<0>) 1%
1/20W
R6123 MF
201
SPI_MISO 1
11 2 SPI_MLB_MISO
14 BI 36
1%
(SPI_IO<1>) 1/20W
MF
201 R6130
SPI_IO<2> 1
11 2 SPI_MLB_IO<2>
14 BI 36
1%
1/20W
R6131 MF
201
SPI_IO<3> 1
11 2 SPI_MLB_IO<3>
14 BI 36
1%
1/20W
MF
201
PAGE TITLE
SPI+SWD Debug Connector

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Left Speaker Amps

APPLE P/N 353S4265
D D
61 53 50 46 45 42 38 37 29 24 PP5V_S4
67 63
BYPASS=U6310.A2:C2:3 MM
1 C6310 CRITICAL
A2
0.1UF R6310 1 1
C6311
10%
VDD 47UF
2 16V 0
R6313 X5R-CERM
0201 U6310 5%
1/20W
20%
2 6.3V
AUD_SPKRAMP_MODE 1
0 2 AUD_SPKRAMP_MODE_LEFT1 MAX98357BEWL MF POLY-TANT
0805 SPKRAMP_LOUT1_P
39 38 37 IN 0201 2 OUT 39
WLP
5% CRITICAL
A1 SD_MODE* OUTP A3
R6312 1/20W
MF
AUD_SCLK_A 200 0201
AUD_SCLKA_LEFT1 C1 BCLK
39 38 37 IN
1 2 OUTN B3
1% SPKRAMP_LOUT1_N
C3 LRCLK GAIN_SLOT B2
R6314 OUT 39
1/20W L_AMP1_GAIN MIN_NECK_WIDTH=0.1000
MF MIN_LINE_WIDTH=0.4000
201 0 AUD_LRCLK_LEFT1 B1 DIN
AUD_LRCLK_A 1 2 NOSTUFF
R6315
39 38 37 IN 1
5% R6311 NOSTUFF
0
39 38 37 IN
AUD_SDOUT_A 1/20W
MF
1 2 AUD_SDOUT_LEFT1 GND 5%
0 1 C6312
0201 5%
1/20W 100PF
C2
1/20W
MF NOSTUFF 5%
2 0201 2 25V
MF
0201 1 C6313 C0G
0201
100PF
5%
2 25V
C0G
0201
C C
61 53 50 46 45 42 38 37 29 24 PP5V_S4
67 63
1 C6320 CRITICAL
A2
0.1UF LCHANNEL:1 1
R6320 1
C6321
10%
VDD 47UF
2 16V 0
R6323 X5R-CERM
0201 U6320 5%
1/20W
20%
2 6.3V
AUD_SPKRAMP_MODE 1
0 2 AUD_SPKRAMP_MODE_LEFT2 MAX98357BEWL MF POLY-TANT
0805
39 38 37 IN 0201 2
WLP MIN_NECK_WIDTH=0.1000
5% CRITICAL
A1 SD_MODE* OUTP A3
R6322
1/20W SPKRAMP_LOUT2_P OUT 39
MF
AUD_SCLK_A 200 AUD_SCLKA_LEFT2 0201
C1 BCLK
1 2 OUTN B3 SPKRAMP_LOUT2_N
R6324
39 38 37 IN OUT 39
1% AUD_LRCLK_LEFT2 C3 LRCLK GAIN_SLOT B2
1/20W 0 L_AMP2_GAIN
MF AUD_LRCLK_A 1 2
R6325
39 38 37 IN
201
B1 DIN
5%
0 AUD_SDOUT_LEFT2 1 LCHANNEL:0
AUD_SDOUT_A 1/20W 1 2 R6321
B B
39 38 37 IN
MF 0
0201 5% GND 5% NOSTUFF
1/20W 1/20W
MF
C6322
C2
MF 1
0201
2 0201
NOSTUFF 100PF
5%
2 25V
1 C6323 C0G
0201
100PF
5%
2 25V
C0G
0201
SPEAKER CONFIGS TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS
A A
TABLE_BOMGROUP_ITEM
EQ:2CH LCHANNEL:1,RCHANNEL:3
TABLE_BOMGROUP_ITEM
SYNC_MASTER=J92_DEVMLB SYNC_DATE=09/19/2013
EQ:4CH LCHANNEL:0,RCHANNEL:4 PAGE TITLE
AUDIO Left Speaker Amps

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D
Right Speaker Amps D
APPLE P/N 353S4265
61 53 50 46 45 42 38 37 29 24 PP5V_S4
67 63
1 C6410 CRITICAL
R6413
A2
0.1UF R6410 1 1
C6411
0 10%
39 38 37
AUD_SPKRAMP_MODE 1 2 AUD_SPKRAMP_MODE_RIGHT1 16V
2 X5R-CERM
VDD
100K 47UF
IN
5%
1/20W
0201 U6410 5%
1/20W
20%
2 6.3V
POLY-TANT
MF MAX98357BEWL MF
201 2 0805
0201 WLP SPKRAMP_ROUT1_P 39
OUT
CRITICAL
A1 SD_MODE*
R6412 OUTP A3
AUD_SCLK_A 200 AUD_SCLK_RIGHT1 C1 BCLK
1 2 OUTN B3
R6414
39 38 37 IN
1% AUD_LRCLK_RIGHT1 C3 LRCLK
1/20W 0 GAIN_SLOT B2 R_AMP1_GAIN SPKRAMP_ROUT1_N
OUT 39
MF AUD_LRCLK_A 1 2
R6415
39 38 37 IN MIN_NECK_WIDTH=0.1000
201
B1 DIN MIN_LINE_WIDTH=0.4000
5%
0 AUD_SDOUT_RIGHT1 1
NOSTUFF
39 38 37 IN
AUD_SDOUT_A 1/20W 1 2 R6411
MF
GND
100K NOSTUFF
0201 5%
1/20W
MF
5%
1/20W 1 C6412
C2
MF 100PF
C
0201
2 201 NOSTUFF 5%
2 25V
C
1 C6413 C0G
0201
100PF
5%
2 25V
C0G
0201
61 53 50 46 45 42 38 37 29 24 PP5V_S4
67 63
1 C6420 RCHANNEL:3 CRITICAL
A2
0.1UF R6420 1 1
C6421
10%
VDD 47UF
2 16V 100K
R6423 X5R-CERM
0201 U6420 5%
1/20W
20%
2 6.3V
AUD_SPKRAMP_MODE 1
0 2 AUD_SPKRAMP_MODE_RIGHT2 MAX98357BEWL MF POLY-TANT
0805
39 38 37 IN 201 2
WLP MIN_NECK_WIDTH=0.1000
5% CRITICAL
A1 SD_MODE* OUTP A3
R6422
1/20W SPKRAMP_ROUT2_P OUT 39
MF
B AUD_SCLK_A 1
200 2 AUD_SCLK_RIGHT2 0201
C1 BCLK OUTN B3 SPKRAMP_ROUT2_N B
R6424
39 38 37 IN OUT 39
1% AUD_LRCLK_RIGHT2 C3 LRCLK GAIN_SLOT B2
1/20W 0 R_AMP2_GAIN
MF AUD_LRCLK_A 1 2
R6425
39 38 37 IN
201
5% AUD_SDOUT_RIGHT2 B1 DIN RCHANNEL:4 NOSTUFF
0 1
R6421
39 38 37 IN
AUD_SDOUT_A 1/20W
MF
1 2
100K
1 C6422
0201 5% GND 5% 100PF
1/20W 1/20W NOSTUFF 5%
2 25V
MF
C6423
C2
MF 1 C0G
0201
2 201 0201
100PF
5%
2 25V
C0G
0201
PAGE TITLE
AUDIO Right Speaker Amps

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CODEC OUTPUT SIGNAL PATHS

FUNCTION VOLUME CONVERTER PIN COMPLEX MUTE CONTROL DET ASSIGNMENT
HP/LINE OUT 0X02 (2) 0X02 (2) 0X09 (9,A) 0X09 (A)
SPEAKERS 0X04 (4) 0X04 (4) 0X0B (11) GPIO_3 N/A
D D
CODEC INPUT SIGNAL PATHS

FUNCTION CONVERTER PIN COMPLEX VREF DET ASSIGNMENT
BUILT-IN MIC 0X06 (6) 0X0D (13,B,RIGHT) MIC_BIAS (80%) N/A
HEADSET MIC 0X06 (6) 0X0D (13,V22,B,LEFT) MIKEY MIKEY
LEFT SPEAKER CONN RIGHT SPEAKER CONN
SOUTHBRIDGE RESOURCE/PIN ALLOCATIONS 518S00014
516S0899 CRITICAL
FUNCTION NET NAME SB GPIO/INT CRITICAL
PERIPHERAL/EXTRACTION DETECT GPIO 3
AUD_IP_PERIPHERAL_DET J6751
MIKEY INTERRUPT AUD_I2C_INT_L GPIO 5 J6750 FF18-10A-R11AD-B-3H
F-RT-SM-A
MIKEY ENABLE AUD_IPHS_SWITCH_EN GPIO 16 AA07A-S010-VA1 11
F-ST-SM NC
MIKEY I2C BUS I2C_MIKEY_SDA/SCL PCH SMBUS 0 12
11 1 SPKRAMP_ROUT2_P 38
IN
2
37 IN
SPKRAMP_LOUT2_P 1 2 SPKRAMP_LOUT2_N IN 37
3 SPKRAMP_ROUT2_N IN 38
3 4 4
5 6 SPKRVNDR_L_ID 39
5
37 IN
SPKRAMP_LOUT1_P 7 8 SPKRAMP_LOUT1_N IN 37
6 SPKRVNDR_R_ID 39
9 10 7 SPKRAMP_ROUT1_P IN 38
8
13 9 SPKRAMP_ROUT1_N 38
IN
14 10
C 12
C
NC
CRITICAL
J6799
502250-8027
F-RT-SM
30
28
AUD_PWR_EN 1
65 17
2 AUD_SPKRAMP_MODE
AUD_LRCLK_A 3 37 38
38 37
4 AUD_SDOUT_A
PP5V_S0 5 37 38
61 52 50 29 28
6 AUD_SCLK_A
7 37 38
8 SMBUS_SMC_3_SDA
SMBUS_SMC_3_SCL 9 29 30 33
33 30 29
10 PP3V3_S0
B 11
B
5 6 14 15 16 17 19 23 26 27 31
14 HDA_BIT_CLK 12
33 34 35 46 50 51 53 61 67
HDA_SDOUT 13
14
14 HDA_SYNC
HDA_SDIN0 15 14
65 14
16 HDA_RST_L
PP1V5_S0 17 14
61 49 46 18 13
18
19
20
21
22
SPKRVNDR_L_ID 23
39
24 SPKRVNDR_R_ID
25 39
26
27
29
31
518S1034
RIO FLEX CONN
A SYNC_MASTER=CARA_J92 SYNC_DATE=04/17/2014 A
PAGE TITLE
AUDIO CONNECTORS
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3.3V G3H VR - Bansuri

D D
41 P3V3G3H_BOOT
DIDT=TRUE
C6994 1
33NF
10%
25V
CERM 2
402
61 41 PPVIN_G3H_P3V3G3H MIN_NECK_WIDTH=0.2000
P3V3G3H_BOOT_RC DIDT=TRUE
R6994 1
0
1 C6900 1 C6901 5%
1/20W
APN 152S1872
2.2UF 2.2UF MF CRITICAL
20%
2 35V
20%
2 35V
0201 2
L6995
X5R-CERM X5R-CERM 10UH-20%-0.85A-0.46OHM
0402 0402
41 P3V3G3H_SW 1 2 PP3V3_G3H 18 23 29 30 31 33 36 40 41 61
SWITCH_NODE=TRUE
DIDT=TRUE Vout = 3.3V
300mA Max Output
(Switcher limit)
C R6990 1 CRITICAL CRITICAL C
10 1 C6998 1 C6997
5%
1/20W 15UF 15UF
MF 20% 20%
201 2 2 6.3V 2 6.3V
X5R X5R
0402-1 0402-1
41 P3V3_G3H_REG_FB
Vout = 1.25V * (1 + Ra / Rb)
B B
Battery Connector
PPVBAT_G3H_CONN 41
C6951 1 1 C6950
1UF 0.1UF
10% 10%
16V 2 2 25V
CRITICAL X5R X5R
402 402
J6950
BATT-COMPRESSION-J92
ST-TH1
1 SMBUS_SMC_5_G3_SCL_R 33 41 46
IN
2 SYS_DETECT_L
3 SMBUS_SMC_5_G3_SDA_R 33 41 46
BI
4 NO STUFF PP3V3_G3H 18 23 29 30 31 33 36 40 41 61
CRITICAL
5
R6950 1
2
6 10K CRITICAL 3 D Q6950

5% DMN32D2LFB4
7 1/10W
MF-LF D6950 DFN1006H4-3
1
R6951 1
R6952
603 2 SYM_VER_2 10K 1M
RCLAMP3552T 5% 5%
1/20W 1/20W
SLP1006N3T MF MF
2 S G 1 2 201 2 201
Dim LED always lit when
3
SYS_DETECT
A SYS_DETECT_LED AON is energized
SYNC_MASTER=(J41_MLB) SYNC_DATE=03/16/2015 A
516-0343 CRITICAL CRITICAL PAGE TITLE
A
SW6900 D6900 Battery Connector & 3.3V G3Hot
WHITE-140MCD-0.005A-2.7V
SOX-152HNT 0402 DRAWING NUMBER SIZE
SM K
Apple Inc.
<SCH_NUM> D
1 2 REVISION
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Press switch to de-energize NOTICE OF PROPRIETARY PROPERTY: BRANCH
G3H rails on battery-only THE INFORMATION CONTAINED HEREIN IS THE

<BRANCH>
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Charger PMIC - Bansuri

FROM ADAPTER
65 61 34 24 PPDCIN_G3H
61 40 PPVIN_G3H_P3V3G3H PPVBAT_G3H_CONN 40 41
PP3V3_G3H R7004
D
61 40 36 33 31 30 29 23 18
4.7
D 65 61 23 PP3V3R3V0_AON CHGR_LDO_VDDA
1 2 CHGR_LDO_P5V0
41
R7001 5%
1/20W
0 MF
CHGR_LDO_VDDP 1 2 201
MIN_NECK_WIDTH=0.2000 5%
1/20W
C7004 1 C7005 1 C7007 1 MF
0201 R7021
C7000 1 C7001 1 C7006 1
VDDP_1 C1
VDDP_2 C7
VR_AON H2
VR1_3P3 H3
VCC_VR1 H7
1UF 1UF 0.1UF
VDDA B4
VBAT F5
1
10% 10% 10%
41 CHGR_CSI_P 1 2
25V
2 25V
2 35V
2 1UF 1UF 1UF CRITICAL
X5R X5R CER-X5R 10% 10% 10%
R7020
5%
3 1
0402-1 0402-1 0201 25V
X5R 2 25V
X5R 2 25V
X5R 2 NOSTUFF 1/20W
MF
CHGR_CSI_R_P
0402-1 0402-1 0402-1
C7020 1 201 0.020 OHM
1%
1
R7010 0.047UF 1/3W
U7000 CHGR_CSI_R_N N/A
10%
750K 6.3V
X5R 2
R7022 4 2 0306
1% 1
1/20W
MF
ISL95530HIZ-TR5664 41 CHGR_CSI_N 201 1 2
WCSP
2 201
5%
LX1 A1 CHGR_PHASE 1/20W
MF
G7 P_IN CRITICAL LX2 A7 CHGR_BOOST_SW 201
CHGR_ACIN D2 ACIN LX_VR1 H6 P3V3G3H_SW 40

1
C7022 1 C7021
LX_VR2 E6 1UF 1UF APN 376S1203
SMBUS_SMC_5_G3_SDA_R F1 SDA NC 0 10% 10%
46 40 33 BI
LX_VR2 E7 NC R7025 1 2 CHGR_BOOT1_RC 2
25V
2 25V
CRITICAL
46 40 33 SMBUS_SMC_5_G3_SCL_R E1 SCL X5R X5R
IN MIN_LINE_WIDTH=0.6000 MIN_LINE_WIDTH=0.6000
Q7010
5% MF 402 402
1
R7011 BOOT1 B1
MIN_NECK_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000
CHGR_BOOT1 1/20W 0201
B2 GPIO1 0 SIZ342JT
255K NC BOOT2 B7 CHGR_BOOT2 R7027 1 2 CHGR_BOOT2_RC
1% PWRPAIR-3X3
1/20W CHGR_BUCK_DH A2 GATE_Q1
5% MF
D1 2 PPDCIN_G3H_CHGR
BOOT_VR1 G6
65 41 MIN_NECK_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000
MF P3V3G3H_BOOT 1/20W 020140
CHGR_BUCK_DL A3 GATE_Q2 C7027 1 1 C7025 3 MIN_LINE_WIDTH=0.6000
2 201 65 41
BOOT_VR2 C6 MIN_NECK_WIDTH=0.2000
CRITICAL CRITICAL CRITICAL BYPASS=Q7010.2::1.5mm
65 41 CHGR_BOOST_DL A5 GATE_Q3 NC 0.1UF 0.1UF 4 VOLTAGE=18.5V
A6 C5
10%
25V
10%
25V 10 C7030 1
C7031 1
C7032 1 1
C7035 1
C7036 1
C7037
65 41 CHGR_BOOST_DH GATE_Q4 EN_VR2 2 2 1 G1 2.2UF 2.2UF 0.001UF
X7R-CERM-1 X7R-CERM-1
65 41 CHGR_BUCK_DH 6.8UF 6.8UF 6.8UF
0402 0402 20% 20% 20% 20% 20% 10%
POWER_GATE_EN E2 POWER_GATE_EN PGOOD_VR2 B6 NC
35V-0.15OHM 2 35V-0.15OHM 2 35V-0.15OHM 2 2
35V
2
35V
2
50V
65 24 23 IN MIN_NECK_WIDTH=0.2000
9
C C
X5R-CERM X5R-CERM X7R-CERM
(CHGR_PHASE) POLY-TANT POLY-TANT POLY-TANT
0402 0402 0402
CASE-B1S CASE-B1S CASE-B1S
CHGR_BGATE F3 BGATE FB_VR1 G5 P3V3_G3H_REG_FB 40
S1/D2
FB_VR2 D5 NC
DIDT=TRUE
CHGR_COMP B5 COMP
C3 LDO_3P0 H1 CHGR_LDO_P3V0
8 G2
41 CHGR_CSI_N CSIN MIN_LINE_WIDTH=0.6000 65 41 CHGR_BUCK_DL
LDO_5P0 H4 41 CHGR_LDO_P5V0
MIN_NECK_WIDTH=0.2000 MIN_LINE_WIDTH=0.6000
5
CHGR_CSI_P C2 CSIP
41
6
65 23 HIPWR_EN E3 HPWR_EN 1 APN 152S00224 S2 7
IN
G2 CRITICAL
CHGR_CSO_N CSON
AMON C4 CHGR_AMON
L7030
34 OUT
CHGR_BMON G3 BMON
OUT 34
2UH-20%-9.3A-0.024OHM
PIME062T CRITICAL
E4 ACOK D3 SMC_BC_ACOK OUT 30 31 34 63
29 IN
SMC_LSOC_RST SMC_RST_IN 65
F7040 TO SYSTEM
F4 HOST_RESET D4 TS_HOST_RST 2 CRITICAL 8AMP-32V-0.006OHM
SMC_RST_L SMC_RST*
CSOP F2 CHGR_CSO_P
Q7020 PPVBAT_G3H_CHGR_REG 1 2 PPBUS_G3H 29 34 41 45 46
52 57 59 61
F6 PBUS
CRITICAL CRITICAL
1 VIN CSD58879Q3D
R7060 1
100K
F7 PBUS CBC_ON E5 SMC_CBC_ON OUT 30 65 Q3D
VOLTAGE=8.6V
C7043 1 C7047 1 1 C7044 1 C7046 1
C7045
0603
5% 3
33UF 33UF 2.2UF 2.2UF 1000PF
1/20W IRQ_L G1 SMC_CHGR_INT_L 30 65
TG CHGR_BOOST_DH 41 65 20% 20% 20% 20% 10%
OUT
MF 6 MIN_LINE_WIDTH=0.6000 16V 2 16V 2 2 25V
X5R-CERM 2 25V
X5R-CERM 2
16V
X7R-1
201 2 MIN_NECK_WIDTH=0.2000 TANT TANT
CASE-B1S CASE-B1S 0402-1 0402-1 0201
7 4
SMC_RESET_L R7061 1 VSW TGR (CHGR_BOOST_SW)
PGND_VR2
PGND_VR2
PGND_VR1
36 30 OUT
10K CHGR_PHASE2 8 MIN_LINE_WIDTH=0.6000
46 45 41 34 29 PPBUS_G3H 5% MIN_LINE_WIDTH=0.6000 DIDT=TRUE
AGND
AGND
AGND
PGND
61 59 57 52 1/20W MIN_NECK_WIDTH=0.2000
PPBUS_G3H 29 34 41 45 46 52 57 59 MF DIDT=TRUE
61 201 2
BG 5
PGND
CHGR_BOOST_DL
1 C7019 41 65 CRITICAL
R7050
B3
G4
D1
A4
D6
D7
H5
C7016 1 2.2UF MIN_NECK_WIDTH=0.2000

20% 0.010 OHM
0.33UF 2 25V APN 376S1187 1%
9
10% X5R-CERM 1/3W
B
25V
X5R
0402
2 0402-1
2
N/A
0603-COMBO
1 PPVBAT_G3H_CHGR_R
B
4 3 MIN_LINE_WIDTH=0.6000
VOLTAGE=8.6V
R7051 NOSTUFF
1
(CHGR_CSO_P) 1 2 CHGR_CSO_R_P 1 C7018 C7017 1 1
C7014 1
C7013 1
C7012
1000PF 1 2 3 2.2UF 2.2UF 0.1UF 0.01UF
NOSTUFF MIN_NECK_WIDTH=0.1000 5%
1/20W 10% 20% 20% 10% 10%
C7050 1 MF 2 25V
X7R-CERM
S 25V
X5R-CERM 2 2
25V
X5R-CERM 2
25V
X5R 2
25V
X7R
0.047UF
201 (CHGR_BGATE) 4 G CRITICAL
Q7055
0201 0402-1 0402-1 402 402
10%
16V
2 R7052
X5R
1 SI7655DN
0201
(CHGR_CSO_N) 1 2 CHGR_CSO_R_N PWRPK-1212-8
1/20W
MF D APN 376S1179
201
5
TO/FROM BATTERY
C7011 1
0.01UF PPVBAT_G3H_CONN 40 41
10%
C7002 C7003 1 C7028 1 C7029 C7026
10V 1 1 1
X5R-CERM 2 PLACE_NEAR=U7000.F5:2.54mm MIN_NECK_WIDTH=0.1000
1 C7010
VOLTAGE=8.6V
0201 10UF 10UF 0.47UF 0.47UF 4700PF
20% 20% 10% 10% 10%
10V
2 2
10V
2 25V
2 25V
2
25V 0.1UF
X5R-CERM X5R-CERM CER-X5R CER-X5R CER-X5R 10%
0402-7 0402-7 0402 0402 0201 16V
2 X5R-CERM
0201
PAGE TITLE
PBus Supply & Battery Charger

DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
70 OF 130
SHEET
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
R7143 R7123
2.1K 2.32K 2
R7142 CPUGT_SENSE_P_R 1 2 CPUGT_FB 42 42 CPUCORE_FB 1 CPUCORE_SENSE_P_R R7122
0 1% 1% 0
8 IN
CPU_VCCGTSENSE_P 2 1
C7144 1/20W
MF
R7144 R7145 R7125 R7124
1/20W
MF C7124 2 1 CPU_VCCSENSE_P IN 8
5%
1/20W
680PF 201
499 2K 2K 499
201 680PF 5%
1/20W
MF 1 2 CPUGT_SENSE_P_RC 1 2 2 1 CPUGT_FB_RC CPUCORE_FB_RC 2 1 1 2 CPUCORE_SENSE_P_RC 1 2 MF
201 201
1% 1% 1% 1%
10% 10%
25V
X7R-CERM
1/20W
MF
201
1/20W
MF
201
1 C7143 C7123 1
1/20W
MF
201
1/20W
MF
201
25V
X7R-CERM
0201 820PF 680PF 0201
10% 10%
XW7140
SM
2 25V
X7R-CERM
25V
X7R-CERM 2 XW7120
SM
0201 0201
CPU_VCCGTSENSE_N 1 2 CPUGT_RTN CPUCORE_RTN 1 2 CPU_VCCSENSE_N
D
8 IN 42 42 IN 8
D C7141 1 1 C7142 C7122 1 1 C7121

330PF 330PF 330PF 330PF
10% 10% 10% 10%
16V 2 2 16V 16V 2 2 16V
X7R X7R X7R X7R
0201 0201 0201 0201
61 48 47 44 43 34 PPBUS_S5_HS_COMPUTING_ISNS R7101 R7100 PP5V_S4 24 29 37 38 45 46 50 53 61 63

10 1 67
C7151 1 2 PPVIN_S0_CPUVR_VIN
PP5V_S3_CPUVR_VCC
1 2
C7131
220PF 5%
1/16W
MIN_NECK_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 5%
1/16W
220PF
VOLTAGE=12.9V VOLTAGE=5V
44 42 IN
CPUGT_ISUMP
201 X7R-CERM 25V 10%
1 2
R7150 MF-LF
402
MF-LF
402 R7130 1 2
10%
CPUCORE_ISUMP
25V X7R-CERM 201
IN 42 43
249 249
44 IN
CPUGT_ISUMN 1 2 CPUGT_ISUMN_R 42
1 C7101 1 C7100 42 CPUCORE_ISUMN_R 1 2 CPUCORE_ISUMN IN 43
VIN 41
VCC 42
0.22UF 1UF
C7153 1%
1/20W 10% 10%
1%
1/20W C7133
0.01UF
R7151
MF
201 C7150 2 25V
X7R 2 10V
X5R C7130 MF
201
R7131
0.01UF
44 42 IN
CPUGT_ISEN1 2 1 3300PF 0402 402-1 3300PF 2 1 CPUCORE_ISEN1 IN 42 43
0201 X7R-CERM 10V 10% 1K CPUGT_ISUMN_RC 2 1 2 1 CPUCORE_ISUMN_RC 1K 10% 10V X7R-CERM 0201
C7154
2
1%
1
U7100 2
1%
1
C7134
0.01UF 1/20W
MF
10%
10V ISL95828HRTZ 10%
10V
1/20W
MF
0.01UF
44 42 CPUGT_ISEN2 2 1 201 X7R-CERM 65 44 CPUGT_FCCM 11 FCCM_B LLP FCCM_A 24 CPUCORE_FCCM 43 65
X7R-CERM 201 2 1 CPUCORE_ISEN2 42 43
IN 0201 OUT OUT 0201 IN
0201 X7R-CERM 10V 10% 10% 10V X7R-CERM 0201
CPUGT_PWM1 12 PWM1_B PWM1_A 25 CPUCORE_PWM1
C7152 1 65 44 OUT
CPUGT_PWM2 13 PWM2_B PWM2_A 26 CPUCORE_PWM2
OUT 43 65
1 C7132
0.01UF 65 44 OUT OUT 43 65
0.01UF
10% PWM3_A 27 10%
10V NC 2 10V
X7R-CERM 2 X7R-CERM
0201 44 42 CPUGT_ISUMP 7 ISUMP_B ISUMP_A 19 CPUCORE_ISUMP 42 43
0201
42 CPUGT_ISUMN_R 8 ISUMN_B ISUMN_A 20 CPUCORE_ISUMN_R 42
C7155 44 42 CPUGT_ISEN1 9 ISEN1_B ISEN1_A 21 CPUCORE_ISEN1 42 43

C7135
82PF CPUGT_ISEN2 10 22 CPUCORE_ISEN2 82PF
44 42 ISEN2_B ISEN2_A 42 43
1 2 CPUGT_COMP 42
23 42 CPUCORE_COMP 1 2
C 5%
4
ISEN3_A
16
5% C
C7156 25V
NP0-C0G
0201 R7155
42 CPUGT_COMP COMP_B COMP_A CPUCORE_COMP 42
R7135
25V
NP0-C0G
0201
C7136
6800PF 1K CPUGT_FB 5 17 CPUCORE_FB 1K 6800PF
42 FB_B FB_A 42
1 2 CPUGT_COMP_RC 1 2 1 2 CPUCORE_COMP_RC 1 2
1% 42 CPUGT_RTN 6 RTN_B RTN_A 18 CPUCORE_RTN 42
R7106 1%
10%
10V
1/20W
MF 1
100 2 CPU_PROCHOT_L
1/20W
MF
10%
10V
X7R-CERM 201 42 CPUGT_IMON 2 IMON_B IMON_A 14 CPUCORE_IMON 42
OUT 6 30 31
201 X7R-CERM
0201 1% 0201
1/20W
42 CPUGT_NTC 3 NTC_B NTC_A 15 CPUCORE_NTC 42 MF PP1V_S3 6 8 12 15 31 50 61
201
R7157 34 46
R7137
68.1K 2 65 43 CPUSA_FCCM FCCM_C VR_HOT* CPU_VR_PROCHOT_L 68.1K 2
1 CPUGT_IMON OUT
CPUCORE_IMON 1
R7103 R7105
42 42
1 1
35 PWM_C 47
1%
1/20W C7157 65 43 OUT
CPUSA_PWM VR_READY CPU_VR_READY OUT 46 63
100 45.3 C7137 1%
1/20W
MF 330PF CPUSA_ISUMP 32 48 ALL_SYS_PWRGD 1% 1% 330PF MF
201
1 2 43 42 ISUMP_C VR_ENABLE IN 30 46 51 1/20W 1/20W 1 2
201
33 MF MF
42 CPUSA_ISUMN_R ISUMN_C 201 2 2 201
10%
16V 42 CPUSA_COMP 29 COMP_C SDA 43 CPUVR_VIDSOUT R7102 1
10 2 CPU_VIDSOUT 8
10%
16V
X7R BI X7R
0201 1% 1/20W MF 201 0201
42 CPUSA_FB 30 FB_C ALERT* 44 CPU_VIDALERT_L 8
OUT
R7158 42 CPUSA_RTN 31 RTN_C SCLK 45 CPUVR_VIDSCLK R7104 1

49.9 2 CPU_VIDSCLK 8
R7138
IN
CPUGT_NTC_R 1
10K 2 CPUGT_NTC 1% 1/20W MF 201
CPUCORE_NTC 1
10K 2 CPUCORE_NTC_R
42
42 CPUSA_IMON 28 IMON_C PSYS 1 R7103.2: PLACE_NEAR=U7100.43:5.08mm
42
1% 1%
1
1/20W
40 R7105.2: PLACE_NEAR=U7100.45:5.08mm 1/20W
1
MF
201
CPUVR_PROG1 PROG1 MF
201
CPUVR_PROG2 39 PROG2
R7159 CPUVR_PROG3 38 R7139
THRM_PAD
PROG3
100KOHM CPUVR_PROG4 37 PROG4 100KOHM
0201 CPUVR_PROG5 36 PROG5 0201
2 2
B 1
R7111 1
R7112 1
R7113 1
R7114 1
R7115 B
49
110K 63.4K 1.87K 182K 100K
1% 1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W 1/20W
MF MF MF MF MF
2 201 2 201 2 201 2 201 2 201
C7175
82PF
42 CPUSA_COMP 1 2
5%
R7175
25V
NP0-C0G
0201
C7176
3.3K 1000PF
1 2 CPUSA_COMP_RC 1 2
1%
1/20W 10%
MF 16V
201 X7R-1
0201
R7177
CPUSA_IMON 1
57.6K 2
42
R7163 C7177 1%
1/20W
330PF MF
R7162 CPUSA_SENSE_P_R 2
1.18K 1 CPUSA_FB 42
C7171 1 2
201
0 1%
220PF
8 IN
CPU_VCCSASENSE_P 2 1
C7164 1/20W
MF
R7164 R7165
43 42 IN
CPUSA_ISUMP
201 X7R-CERM 25V 10%
1 2
R7170 10%
16V
5% 1500PF 201
CPUSA_ISUMN 255 CPUSA_ISUMN_R
X7R
1/20W
MF 2 1 CPUSA_SENSE_P_RC 1
499 2 2
2K 1 CPUSA_FB_RC 43 IN
1 2 42
0201
201 1%
1% 1% 1/20W
A
10%
10V
X7R
1/20W
MF
1/20W
MF 1 C7163 R7171
MF
201 C7170 A
0201
201 201
2200PF 1K 3300PF SYNC_MASTER=DEVMLB SYNC_DATE=07/06/2015
10% 2 1 CPUSA_ISUMN_RC 2 1 PAGE TITLE
XW7160
SM
25V
2 CER-X7R
1% CPU IMVP8 Regulator IC
0201 10%
8 IN
CPU_VCCSASENSE_N 1 2 CPUSA_RTN 42 C7172 1
1/20W
MF
201
10V
X7R-CERM DRAWING NUMBER SIZE
0.01UF 0201 <SCH_NUM> D
10% Apple Inc.
C7161 1 1 C7162 10V
X7R-CERM 2 REVISION
330PF 330PF 0201 R
<E4LABEL>
10% 10%
16V 2 2 16V NOTICE OF PROPRIETARY PROPERTY: BRANCH
X7R X7R
<BRANCH>
71 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Note:Vcore design requires 4x POSCAPs R7217 PP5V_S4RS0 43 44 61
3x shared from other VRs PP5V_S0_CPUCORE1 1
2.2 2
VOLTAGE=5V 1/20W
MF
CRITICAL
201 CPUCORE_BOOT1_R
MIN_LINE_WIDTH=0.2000 CRITICAL R7210
0.001
1 C7217 1 C7216 MIN_NECK_WIDTH=0.2000
DIDT=TRUE L7210 1%
1/2W
2.2UF 2.2UF 0.22UH-20%-12A-0.0045OHM
48 47
42 34 PPBUS_S5_HS_COMPUTING_ISNS Phase 1 20%
2 25V
20%
2 25V 1 2 PPVCORE_S0_CPU_PH1 2
MF
0306
1
VDRV 11
C7219
44 43
R7219 1
VCIN 2
61 X6S-CERM X6S-CERM 1 MIN_LINE_WIDTH=0.6000
0402 0402 PILE052T-SM MIN_NECK_WIDTH=0.2000 4 3
CRITICAL CRITICAL 0 0.22UF VOLTAGE=1.5V
10% 152S00217 CPUCORE_ISNS1_P
C7210 1 C7211 1 C7214 1 C7215 1 5%
1/16W
MF-LF
2 25V
X7R CPUCORE_ISNS1_N
OUT 64
33UF 33UF 2.2UF 2.2UF 43 64
U7210
0402 OUT
402 2
D
20%
16V 2
20%
16V 2
20%
25V
X6S-CERM 2
20%
25V
X6S-CERM 2 SIC535CD
NO_XNET_CONNECTION=1 D
TANT
CASE-B1S
TANT
CASE-B1S 0402 0402 CPUCORE_BOOT1 R7214
6
MLP4535 MIN_LINE_WIDTH=0.2000 2.2 CPUCORE_ISUMN
VIN BOOT 4 MIN_NECK_WIDTH=0.2000 1 2 OUT 42 43
DIDT=TRUE
1%
65 43 42 IN
CPUCORE_FCCM 1 ZCD_EN* PHASE 5 CPUCORE_BOOT1_RC 1/20W
MIN_LINE_WIDTH=0.2000 MF
8 MIN_NECK_WIDTH=0.2000 201
65 42 IN
CPUCORE_PWM1 12 PWM
CRITICAL
VSWH DIDT=TRUE NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 R7213
NC
3 NC GL 9
CPUCORE_PHASE1
MIN_LINE_WIDTH=0.6000 R7211 1 1
R7212 1
200K 2 CPUCORE_ISNS2_N 43 64
MIN_NECK_WIDTH=0.2000 1K 200K
GL 14 NC DIDT=TRUE 1% 1% 1%
7 PGND
10 PGND
SWITCH_NODE=TRUE 1/20W 1/20W 1/20W
13 CGND
MF MF MF
201 2 201
2 201
CPUCORE_GL1 65 NO_XNET_CONNECTION=1
CPUCORE_ISEN1 PPVCORE_S0_CPU
XW7210
SM CPUCORE_ISUMP
OUT 42 8 11 34 61
CPU VCORE
OUT 42 43
1 2
Vout = 1.50V max
GND_CPUCORE1_CGND
24A max load
VOLTAGE=0V
f = 750kHz
R7237 PP5V_S4RS0 43 44 61
PP5V_S0_CPUCORE2 1
2.2 2
VOLTAGE=5V 1/20W
MF
CRITICAL
201 CPUCORE_BOOT2_R
0.001
1 C7237 1 C7236 MIN_NECK_WIDTH=0.2000
DIDT=TRUE L7230 1%
1/2W
2.2UF 2.2UF 0.22UH-20%-12A-0.0045OHM
48 47
2 25V
20%
2 25V 1 2 PPVCORE_S0_CPU_PH2 1
MF
0306
2
C
VDRV 11
C C7239
44 43
R7239 1
VCIN 2
10% 152S00217 CPUCORE_ISNS2_P
C7230 1
C7231 1 C7234 1 C7235 1 5%
1/16W
MF-LF
2 25V
X7R CPUCORE_ISNS2_N
OUT 64
33UF 33UF 2.2UF 2.2UF 43 64
U7230
0402 OUT
20% 20% 402 2
20% 20% 25V 25V NO_XNET_CONNECTION=1
16V 2 16V 2 X6S-CERM 2 X6S-CERM 2 SIC535CD
TANT
CASE-B1S
TANT
CASE-B1S 0402 0402 CPUCORE_BOOT2 R7234
6
MLP4535 MIN_LINE_WIDTH=0.2000 2.2 CPUCORE_ISUMN
DIDT=TRUE
1%
65 43 42 IN
CPUCORE_FCCM 1 ZCD_EN* PHASE 5 CPUCORE_BOOT2_RC 1/20W
65 42 IN
CPUCORE_PWM2 12 PWM
CRITICAL
NC
3 NC GL 9
CPUCORE_PHASE2
R7232 1
200K 2 CPUCORE_ISNS1_N 43 64
7 PGND
10 PGND

13 CGND
MF MF MF
201 2 201
2 201
CPUCORE_GL2 65 NO_XNET_CONNECTION=1
CPUCORE_ISEN2
XW7230
SM CPUCORE_ISUMP
OUT 42
42 43
OUT
1 2
GND_CPUCORE2_CGND
VOLTAGE=0V
61 48 47 44 43 42 34 PPBUS_S5_HS_COMPUTING_ISNS
B CRITICAL
C7290 1 C7294 1 C7295 1
B
33UF 2.2UF 2.2UF
20% 20% 20%
16V 2 25V 25V
TANT X6S-CERM 2 X6S-CERM 2
CASE-B1S 0402 0402
CPU VCCSA
61 44 43 PP5V_S4RS0
CPUSA_BOOT_R
DIDT=TRUE
C7296 1
2.2UF CRITICAL
20%
25V R7299 1 1 C7299 Q7291
X6S-CERM 2 0 0.22UF
0402 10% CSD58873Q3D
5%
1/16W 2 25V Q3D CRITICAL XW7290
6
X7R
VCC
MF-LF
402 2 0402
VIN 1 CRITICAL R7290 1
SM
2 PPVCCSA_DDR_S0
U7290 0.003 8 11 61
CPUSA_BOOT L7290 1%
1/2W PLACE_NEAR=R7290:5MM
ISL6208D MIN_LINE_WIDTH=0.2000 3 TG 0.47UH-20%-8.5A-0.035OHM MF
DFN MIN_NECK_WIDTH=0.2000 0306
65 42 CPUSA_PWM 3 PWM BOOT 2 DIDT=TRUE 6 CPUSA_SW_LL 1 2 PPVCCSA_S0_CPU 2 1 PPVCCSA_S0 8 11 61
IN
4 TGR VSW 7 MIN_LINE_WIDTH=0.4000 PIMA032T-SM MIN_LINE_WIDTH=0.6000 4 3
65 42 IN
CPUSA_FCCM 7 FCCM UGATE 1
CPUSA_UGATE
DIDT=TRUE
SWITCH_NODE=TRUE
VOLTAGE=1.5V
CPUSA_ISNS_P OUT 64 Vout = 1.05V max
CRITICAL
PHASE 8
DIDT=TRUE
GATE_NODE=TRUE
CPUSA_ISNS_N OUT 64
4.1A max load
CPUSA_PHASE 5 BG f = 750kHz
PGND
THRM LGATE 5 DIDT=TRUE
GND PAD SWITCH_NODE=TRUE CPU & CHIPS
A CPUSA_LGATE A
9
4
MIN_LINE_WIDTH=0.4000 SYNC_MASTER=DEVMLB SYNC_DATE=05/19/2015

MIN_NECK_WIDTH=0.2000 PAGE TITLE
DIDT=TRUE
GATE_NODE=TRUE NO_XNET_CONNECTION=1
R72911 1
NO_XNET_CONNECTION=1
R7292
CPU VCore/VccSA Power Stage
DRAWING NUMBER SIZE
1K 0
1%
1/20W
5%
1/20W Apple Inc.
<SCH_NUM> D
MF MF REVISION
201 2 2 0201 R
<E4LABEL>
CPUSA_ISUMN OUT 42 NOTICE OF PROPRIETARY PROPERTY: BRANCH
CPUSA_ISUMP OUT 42 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
72 OF 130
SHEET
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
R7417 PP5V_S4RS0 43 44 61
PP5V_S0_CPUGT1 1
2.2 2
VOLTAGE=5V 1/20W
MF
CRITICAL
201 CPUGT_BOOT1_R
0.001
1 C7417 1 C7416 MIN_NECK_WIDTH=0.2000
DIDT=TRUE L7410 1%
1/2W
2.2UF 2.2UF 0.22UH-20%-12A-0.0045OHM
48 47
2 25V
20%
2 25V 1 2 PPVCCGT_S0_CPU_PH1 2
MF
0306
1
VDRV 11
C7419
44 43
R7419 1
VCIN 2
10% 152S00217 CPUGT_ISNS1_P
C7410 1
C7411 1 C7414 1 C7415 1 5%
1/16W
MF-LF
2 25V
X7R CPUGT_ISNS1_N
OUT 64
33UF 33UF 2.2UF 2.2UF 44 64
U7410
0402 OUT
402 2
D
20%
16V 2
20%
16V 2
20%
25V
X6S-CERM 2
20%
25V
X6S-CERM 2 SIC535CD
NO_XNET_CONNECTION=1 D
TANT
CASE-B1S
TANT
CASE-B1S 0402 0402 CPUGT_BOOT1 R7414
6
MLP4535 MIN_LINE_WIDTH=0.2000 2.2 CPUGT_ISUMN
DIDT=TRUE
1%
65 44 42 IN
CPUGT_FCCM 1 ZCD_EN* PHASE 5 CPUGT_BOOT1_RC 1/20W
65 42 IN
CPUGT_PWM1 12 PWM
CRITICAL
NC
3 NC GL 9
CPUGT_PHASE1
R7412 1
200K 2 CPUGT_ISNS2_N 44 64
7 PGND
10 PGND
13 CGND
MF MF MF
201 2 201
2 201
CPUGT_GL1 65 NO_XNET_CONNECTION=1
CPUGT_ISEN1 PPVCORE_S0_GT
XW7410
SM CPUGT_ISUMP
OUT 42 8 12 34 61
CPU VGT
OUT 42 44
1 2
Vout = 1.50V max
GND_CPUGT1_CGND
24A max load
VOLTAGE=0V
f = 750kHz
R7437 PP5V_S4RS0 43 44 61
PP5V_S0_CPUGT2 1
2.2 2
VOLTAGE=5V 1/20W
MF
CRITICAL
201 CPUGT_BOOT2_R
0.001
1 C7437 1 C7436 MIN_NECK_WIDTH=0.2000
DIDT=TRUE L7430 1%
1/2W
2.2UF 2.2UF 0.22UH-20%-12A-0.0045OHM
48 47
2 25V
20%
2 25V 1 2 PPVCCGT_S0_CPU_PH2 2
MF
0306
1
C
VDRV 11
C C7439
44 43
R7439 1
VCIN 2
10% 152S00217 CPUGT_ISNS2_P
C7430 1
C7431 1 C7434 1 C7435 1 5%
1/16W
MF-LF
2 25V
X7R CPUGT_ISNS2_N
OUT 64
33UF 33UF 2.2UF 2.2UF 44 64
U7430
0402 OUT
20% 20% 402 2
20% 20% 25V 25V
16V 2 16V 2 NO_XNET_CONNECTION=1
X6S-CERM 2 X6S-CERM 2 SIC535CD
TANT
CASE-B1S
TANT
CASE-B1S 0402 0402 CPUGT_BOOT2 R7434
6
MLP4535 MIN_LINE_WIDTH=0.2000 2.2 CPUGT_ISUMN
DIDT=TRUE
1%
65 44 42 IN
CPUGT_FCCM 1 ZCD_EN* PHASE 5 CPUGT_BOOT2_RC 1/20W
65 42 IN
CPUGT_PWM2 12 PWM
CRITICAL
NC
3 NC GL 9
CPUGT_PHASE2
R7432 1
200K 2 CPUGT_ISNS1_N 44 64
7 PGND
10 PGND

13 CGND
MF MF MF
201 2 201
2 201
CPUGT_GL2 65 NO_XNET_CONNECTION=1
CPUGT_ISEN2
XW7430
SM CPUGT_ISUMP
OUT 42
42 44
OUT
1 2
GND_CPUGT2_CGND
VOLTAGE=0V
B B
PAGE TITLE
CPU VccGT Power Stage

DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
74 OF 130
SHEET
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
D D
5.1V S4 3.3V S5 (DSW)
PPBUS_G3H 61 53 50 46 45 42 38 37 29 24 PP5V_S4
52 46 45 41 34 29
61 59 57 61 59 57 52 46 45 41 34 29 PPBUS_G3H 67 63

C7660 C7661
1 C7662 PP5V_S5
C7682 C7680 C7681
C7665 1
C7666 1 1 1 1
C7685 1 1
50 57 61
1
12PF
33UF
20%
33UF
20% 20%
2.2UF 2.2UF
20%
5%
25V
2 NP0-C0G
C7650 1
VOUT = 5V
12PF
5%
33UF
20%
2.2UF
20%
2.2UF
20%
16V 2 16V 2 2 25V
X6S-CERM 2 25V
X6S-CERM 0201
1UF CRITICAL100MA MAX OUTPUT 25V
NP0-C0G 2 16V 2 2 25V
X6S-CERM 2 25V
X6S-CERM
TANT TANT 10% TANT
CASE-B1S CASE-B1S 0402 0402 25V
X5R 2
1 C7651 0201 CASE-B1S 0402 0402
402 10UF
CRITICAL P5VP3V3_VREG3
20%
2 6.3V R7685 CRITICAL
L7670 P5VS4_TG CERM-X6S
0402 1
1 2 P3V3S5_TG L7690
1.5UH-20%-13A-0.0265OHM CRITICAL
P5VP3V3_VREF2
45 42 38 37 29 24 PP5V_S4 MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE 5%
1.8UH-20%-8.5A-0.0325OHM PP3V3_S5 61 67
9 13 15 18 46
1 2
67 63 61 53 50 46
Q7660 DIDT=TRUE
C7652 C7653
1/20W
MF
DIDT=TRUE
GATE_NODE=TRUE 1 2
48 49 50 59 60
23
29
22
13
PIMS062T-SM 1 1 201
2
VOUT = 5.1V FDPC1012S VOUT = 3.3V
0.22UF 2.2UF CRITICAL PIMA052T-SM
LLP 4.2 A MAX OUTPUT
Q7680
V5SW
VIN
VREG5
VREG3
VREF2
7.3 A MAX OUTPUT P5VS4_VBST_R 10%
10V
20% P3V3S5_VBST_R
CERM 2 2 10V
F = 400 KHZ
1 C7672 V+ 8
SWITCH_NODE=TRUE 402
X5R-CERM
402
SWITCH_NODE=TRUE
CSD58873Q3D
Q3D
F = 400 KHZ
12PF 1
R7669 R7689 1
5% V+ 9 6 SKIPSEL1 CRITICAL CRITICAL
CRITICAL CRITICAL 2 25V 1 CRITICAL 1 VIN 1
C7670
NP0-C0G
C7669 R7665 1 5% 19 SKIPSEL2 5%
C7689 C7690 1
C7695 1
1
C7675 1
10UF
0201
1 HSG
1
0.1UF 1 1/20W
MF 14 OCSEL U7650 EN 12 S5_PWR_EN 1/20W
MF 0.1UF
1
3 TG
10UF 150UF
150UF 20% 10% 5% 2 201 QFN
IN 45 51
201 2 10%
20%
10V 20%
20% 1/20W 6 X5R-CERM 2 6.3V 2
2 10V P5VS4_VSW 2 2 25V 25V
TPS51980A
2 6.3V TANT
POLY-TANT X5R-CERM 45
X6S-CERM MF
201 2 P5VS4_VBST 31 VBST1 VBST2 26 P3V3S5_VBST X6S-CERM 2 0402-1 CASE-B-SM
0402-1 3 SW 0201 0201 4 TGR VSW 7
PLACE_NEAR=L7670.1:3MM
CASE-B3-SM SWITCH_NODE=TRUE DIDT=TRUE DIDT=TRUE SWITCH_NODE=TRUE CRITICAL CRITICAL

CRITICAL CRITICAL
C7671
4 P5VS4_DRVH 1 DRVH1 DRVH2 24 P3V3S5_DRVH 8 P3V3S5_VSW 1 C7691 1
C7696
C7676 1 10UF
GATE_NODE=TRUE DIDT=TRUE DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.0950
MIN_NECK_WIDTH=0.0700 10UF 150UF
150UF P5VS4_VSW 32 SW1 P3V3S5_SW2 20%
C 20%
6.3V 2
20%
10V
X5R-CERM 2 LSG 7
SWITCH_NODE=TRUE
45
DIDT=TRUE
SW2 25
DIDT=TRUE SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000 5 BG
2 10V
X5R-CERM
0402-1
20%
2 6.3V
TANT C
POLY-TANT P5VS4_DRVL 30 DRVL1 DRVL2 27 P3V3S5_DRVL CASE-B-SM
PGND
CASE-B3-SM 0402-1 MIN_LINE_WIDTH=0.6000 GATE_NODE=TRUE DIDT=TRUE DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.0950
MIN_NECK_WIDTH=0.2000 MIN_NECK_WIDTH=0.0700
P5VS4_CSP1 7 CSP1 CSP2 18 P3V3S5_CSP2
C7673 P5VS4_CSN1 8 CSN1 CSN2 17 P3V3S5_CSN2 C7693
0.047UF 11 MODE P3V3S5_RF 0.022UF 376S1038
RF 3
GND
GND
GND
1 2 1 2 CRITICAL
CRITICAL CRITICAL
376S1147
P5VS4_VFB1 9 VFB1 VFB2 16 P3V3S5_VFB2 C7692 1
C7697 1
1
C7677 1
C7659 10% P5VS4_COMP1 10 COMP1 COMP2 15 P3V3S5_COMP2 10% 12PF 150UF
5
6
10
2 16V 16V 5% 20%

150UF
20%
150UF
20% XW7675
X7R-CERM
0402 PM_SLP_S5_L 4 EN1 EN2 21 S5_PWR_EN R7655 1 X5R-X7R-CERM
0402 2 25V 2
NP0-C0G 6.3V 2
TANT
XW7695
51 50 30 15 IN IN 45 51 0201
2 6.3V 2 6.3V 249K CASE-B-SM
POLY-TANT
CASE-B3-SM
SM
POLY-TANT
CASE-B3-SM R7673 63 46 OUT
P5VS4_PGOOD 5 PGOOD1 PGOOD2 20 S5_PWRGD OUT 30 46 51 1%
1/20W R7693 SM
1
1
1K 2 GND THRM_PAD MF
1
1K 2
201 2 1
1% 1%
28
33
P5VS4_VFB1_R 1/20W 1/20W P3V3S5_VFB2_R
2 2 R76721 MF
201 1
R7676 R76751 1
R7695 R76961 MF
201
1
R7692 2 2
1
R7677 XW7671 XW7670 9.09K
1% 10K
21.5K
1% 1%
10K 10K
1% 1%
15K XW7690 XW7691
10
SM SM 1/20W
MF
1%
1/20W
1/20W
MF PLACE_NEAR=U7650.28:1MM
1/20W
MF
1/20W
MF
1/20W
MF
SM SM
R76971
5% 1 1 201 2 MF 201 2 2 2 201 201 2 2 201 1 1 10
1/20W 2 201 5%
MF
2 201
P5VS4_CSP1_R DIDT=TRUE
P5VS4_COMP1_R XW7650
SM
P3V3S5_COMP2_R P3V3S5_CSP2_R DIDT=TRUE 1/20W
MF
C7658 1
P5VS4_VFB1_RR 1
201 2
12PF
5% C7678 1 1 C7679 C7699 1 1 C7698 P3V3S5_VFB2_RR
25V 2
NP0-C0G
220PF 1000PF 3300PF 330PF
2% 10% 10% 10%
0201 1
R7678 50V 2
C0G
0201
25V
2 X7R
0201
10V
X7R-CERM 2
0201
2 25V
X7R
0201 R76981
41.2K
1% (P5VP3V3_VREF2) (P5VP3V3_VREF2) 23.2K
1/20W 1%
MF 1/20W
2 201 MF
201 2
B GND_5V3V3_AGND
B
1
R7679 VOLTAGE=0V
R7699 1
10K
1% 10K
1/20W 1%
MF 1/20W
2 201 MF
201 2
NO STUFF NO STUFF NO STUFF

1
C7657 1
C7656 1
C7655
47UF 47UF 47UF
20% 20% 20%
2 6.3V 2 6.3V 2 6.3V
POLY-TANT POLY-TANT POLY-TANT
0805 0805 0805
A SYNC_MASTER=J92_MLB SYNC_DATE=03/20/2015 A
PAGE TITLE
5V & 3.3V Power Supplies

DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
76 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
46 PP3V3_PMICLDO
BANJO - PMIC Control 1
5%
R7860
100K
1/20W
MF
46 PP3V3_PMICLDO PP3V3_S5 9 13 15 18 45 46 48 49 50 59 60
2 201
CKPLUS_WAIVE=PWRTERM2GND 61 67 46 PMIC_SHUTDOWN_L
PLACE_NEAR=U7800.D1:2MM
C7839 1
1
PLACE_NEAR=U7800.L8:2MM
C7840 67
PP3V3_S0
2.2UF
D
27 26 23 19 17 16 15 14 6 5
ECVCC L1
D
61 53 51 50 46 39 35 34 33 31
10% 1UF
10V
X6S-CERM 2
0402
20%
2 10V
X6S-CERM
1
R7861
0201 100K
5%
1/20W
(OD)
MF
2 201
VDDPG D1
VDDLV L8
63 46 42 CPU_VR_READY
PP3V3_SUS
U7800 61 50 49 46 36 17 16 14 13 9
P650839A0C
PBGA U7800
1
R7810
2.2K
(8 OF 10) P650839A0C 5%
PBGA 1/20W
D11 ACOK CRITICAL MF
51 30 IN
SMC_PM_G2_EN (PP) DS3_VREN K13 NC (1 OF 10) 2 201
H2 PWRBTNIN CRITICAL 63 46 30 15 PM_RSMRST_L
46 PP3V3_PMICLDO OMIT_TABLE 1HZ K11 NC 46 PMIC_SHUTDOWN_L C7 SHUTDOWN* RESET* C8
NC
E5 VINPP OMIT_TABLE
61 59 57 52 46 45 41 34 29 PPBUS_G3H (OD) SYS_PWROK H11 PMIC_SYS_PWROK OUT 15 30 51 67 46 30 15 IN
PM_SLP_S0_L D9 STANDBY*
F1 BAT1 (OD) PCH_PWROK E11 PM_PCH_PWROK 15 46 61 50 49 46 36 17 16 14 13 9 PP3V3_SUS E7 VSA (PP) PGA D6 PVCCPCORE_EN 48
OUT OUT
G1 BAT2 61 50 49 22 21 PP1V8_S3 K9 VSB (PP) PGB C5 P1V8S3_EN 50
ALL_SYS_PWRGD G11 ALL_SYS_PWRGD OUT
(OD) 30 42 46 51
K8
PP3V3_PMICLDO PGC C6 TP_PMIC_PGC
OUT
46 VSC
E2 ACIN (OD) RSMRST_L_PWRGD J11 PM_RSMRST_L 15 30 46 63 51 46 45 30 S5_PWRGD E6 VSD (PP) PGD H3 TP_PMIC_PGD
OUT IN
67
27 26 23 19 17 16 15 14 6 5 PP3V3_S0 F4 VSE (PP) PGE C4 TP_PMIC_PGE
G3 VDCSNS PMIC_INT* D12 SMC_PMIC_INT_L 30 31 61 53 51 50 46 39 35 34 33 31
OUT
61 49 39 18 13 PP1V5_S0 E8 VSF (PP) PGF H4 TP_PMIC_PGF 59 50 49 48 46 45 18 15 13 9 PP3V3_S5
67 61 60
H9 EC_RST* J3 63 46 45 P5VS4_PGOOD J10 VSG (PP) PGG F3 TP_PMIC_PGG
GND NVDC*
IN
F5
65 51 50 49 46 30 15 PM_SLP_S3_L VSH (OD) PGH M6 PVCCIO_EN 46 47 50 31 29 26 25 24 18 15 PP3V3_S4
EC_ONOFF* K4
IN OUT
(LDO3V = 3S) 61 59
(GND = 2S)
PCH_PWRBTN* K2
65 48 IN
P1V8SUS_PGOOD B12
C11
ENA (OD) LVA L12 PM_SLP_S0S3_L OUT 19 46 50 51 63
1
R7801 1
R7802
63 51 50 47 30 15 IN
PM_SLP_S4_L ENB (OD) LVB L10 PM_PCH_PWROK 15 46 1K 1K
5% 5%
(OD) DPWROK K12 C12
C J13
ENC
END
1/20W
MF
2 201
1/20W
MF
2 201
C
ACSWON* J2 F10
51 50 48 15 IN
PM_SLP_SUS_L ENE 63 46 45 P5VS4_PGOOD
BAT1SWON* F2 65 51 50 49 46 30 15 IN
PM_SLP_S3_L J12 ENF
BAT2SWON* G2 B10 ENG 51 46 45 30 S5_PWRGD
CPU_VR_READY L11 ENH
VCCST_PWRGD E4
63 46 42
CPU_VCCST_PWRGD OUT 15
IN
67 46 30 15 PM_SLP_S0_L L6 ENLVA
IN
67
27 26 23 19 17 16 15 14 6 5
61 53 51 50 46 39 35 34 33 31
PP3V3_S0
1
R7804 1
R7805
10K 10K
61 46 16 15 9 PPVRTC_G3H 5% 5%
1/20W 1/20W
MF MF
PLACE_NEAR=U7800.C13:2MM
2 201 2 201
46 PP3V3_PMICLDO PP5V_G3H 46 47 48 61
1 C7880
1UF 46 15 PM_PCH_PWROK
20%
2 10V
BYPASS=U7800.E1::2MM BYPASS=U7800.M13::2MM
C7830 C7890
V3P3A_RTC C13
1 1 BYPASS=U7800.D3::2MM
X6S-CERM ALL_SYS_PWRGD
1UF 1UF
1 C7831 0201 51 46 42 30
20%
10V 2
20%
10V
1UF 59 50 49 48 46 45 18 15 13 9 PP3V3_S5
20%
X6S-CERM 2
67 61 60
X6S-CERM 2 10V
0201 0201 X6S-CERM
0201
1
R7807
100K
VDDIO1 M13
5%
VDD5_VPROGOTP D3
VDDIO0 E1
1/20W
MF
61 46 16 15 9 PPVRTC_G3H B13 VBATTBKUP U7800 (OD) TRIP* H10

2 201
P650839A0C PVCCIO_EN PVCCIO_EN

B B
47 46 46 47
MAKE_BASE=TRUE
J4 VCOMP
PBGA
A1 47 46 PVCCIO_EN
(10 OF 10) NC0 NC
NC1 A13
CRITICAL NC
NC2 N1
OMIT_TABLE NC
NC3 N13
NC
U7800
AGND
P650839A0C
PBGA
(7 OF 10)
F6
F7
F8
G5
G6
G7
G8
H5
H6
H7
H8
J5
J6
J7
J8
K6
K7
41 40 33 SMBUS_SMC_5_G3_SDA_R H1 SDA OMIT_TABLE TEMP_ALERT* L2
BI
41 40 33 SMBUS_SMC_5_G3_SCL_R J1 SCLK VOUT3V3SW M7

IN
R7837 46 PMIC_SLAVEADDR L3 SLAVEADDR LDO3V N8 PP3V3_PMICLDO 46
100K K3 EN3V3SW
1 2 PMIC_EN3V3SW VREF1V25 B1 PP1V25_PMICVREF 46
5%
CRITICAL
1/20W 63 46 45 P5VS4_PGOOD M5 EN5VSW LDO5V N7 PP5V_G3H 48
46 NOSTUFF
MF 47
201
61 53 50 45 42 38 37 29 24 PP5V_S4 N5 VIN5VSW
61
R7864
67 63
PMIC_SLAVEADDR 1
0 2 PP3V3_PMICLDO
46 46
M8 VINLDO3
5%
1/20W
AGND1
AGND2
AGND3
AGND4
61 59 57 52 46 45 41 34 29 PPBUS_G3H N6 VIN MF
201
PLACE_NEAR=U7800.M8:2MM PLACE_NEAR=U7800.N6:2MM
C7837 1 C7838 1 PLACE_NEAR=U7800.N7:2MM
1 C7836
PLACE_NEAR=U7800.N7:2MM
1 C7835
PLACE_NEAR=U7800.B1:2MM
1 C7834
PLACE_NEAR=U7800.N8:2MM
1 C7833
PLACE_NEAR=U7800.M7:2MM
1 C7832 67
PP3V3_S0
C1
K1
L13
D13
1.0UF 1.0UF 27 26 23 19 17 16 15 14 6 5
61 53 51 50 46 39 35 34 33 31
10%
25V 2
10%
25V 2
10UF 10UF 0.47UF 10UF 0.1UF
20% 20% 10% 20% 10%
X6S
0402
X6S
0402 2 6.3V
CERM-X6S
0402
2 6.3V
CERM-X6S
0402
2 10V
X7R
0402
2 6.3V
CERM-X6S
0402
2 25V
CERM-X7R
0402
1
R7808
100K
A 5%
1/20W
MF SYNC_MASTER=X260_ERIC SYNC_DATE=06/15/2015
A
2 20163 51 63 PAGE TITLE
PM_SLP_S0S3_L PM_SLP_S0S3_L 50
50 46 19
MAKE_BASE=TRUE
19
46
51 PMIC-1 & Power Control
DRAWING NUMBER SIZE
MAKE_BASE=TRUE Apple Inc.

<SCH_NUM> D
GND REVISION
PP3V3_PMICLDO PP1V25_PMICVREF
46
46
GND
R
<E4LABEL>
VOLTAGE=3.3V VOLTAGE=1.25V NOTICE OF PROPRIETARY PROPERTY: BRANCH

<BRANCH>
78 OF 130
SHEET
BOM_COST_GROUP=PLATFORM POWER IV ALL RIGHTS RESERVED 46 OF 67
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1.2V VDDQ (Banjo#1 VR4)

61 48 46 PP5V_G3H
CRITICAL
Q7900 C7900 1 C7901 1 1 C7902 1 C7903
1 C7909 U7800 CSD58879Q3D
Q3D
33UF
20%
33UF
20%
2.2UF
20%
2.2UF
20%
1UF P650839A0C 16V 2 16V 2 2 25V 2 25V
20%
2 16V
CER-X5R
PBGA
R7902 C7904 VIN 1
TANT
CASE-B1S
TANT
CASE-B1S
X6S-CERM
0402
X6S-CERM
0402
0201 (5 OF 10)
0 0.1UF
B4 VREGVR4 CRITICAL VBSTVR4 B3 P1V2_VBST 1 2 P1V2_VBST_R 1 2
D OMIT_TABLE
10%
3 TG
6 D
P1V2S3_ILIM_HS D2 ILIMVR4 DIDT=TRUE 1/20W
MF
201
DIDT=TRUE
25V
X6S-CERM 4 TGR VSW 7 L7900
DRVHVR4 A2 65 P1V2_DRVH 0201 0.68UH-20%-6.7A-0.0194OHM
8
R7900 1 IN
GND D4 DDRID SWVR4 A3 P1V2_SW MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE GATE_NODE=TRUE
P1V2_SW_LL 1 2 PP1V2_S3 8 12 20 21 22 50 61
13.3K
1% IN
GND E3 DDR_VTT_CTRL DRVLVR4 A5 65 P1V2_DRVL MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000 PIMS042T-SM Vout = 1.2V
1/20W
MF
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE GATE_NODE=TRUE
5 BG
SWITCH_NODE=TRUE
1
C7905 1
C7906 1 C7907 1 C7908 IccMax = 4.415A
PGND
201 2
270UF
20%
270UF
20%
20UF
20%
20UF
20% F = 960kHz
47 46 PVCCIO_EN B5 PGVR4 FBVR4+ C3 P1V2S3_FB_P 2 2V 2 2V 2 2.5V 2 2.5V
OUT TANT TANT X6S-CERM X6S-CERM
PM_SLP_S4_L C2 ENVR4 FBVR4- D5 P1V2S3_FB_N CASE-B2-SM CASE-B2-SM 0402 0402
9
63 51 50 46 30 15 IN
1
R7904
PGNDVR4
10
XW7900
2
5%
1/20W
MF
SM
2 201
A4
1
0.6V VTT (Banjo#1 LDO1)
C C
U7800
P650839A0C
PBGA
(9 OF 10)
A6 VINLDO1_0 VOUTLDO1_0 A8
B6 VINLDO1_1 VOUTLDO1_1 B8
CRITICAL
F9 VINLDO1S OMIT_TABLE
FBLDO1 D8
PGNDLDO1_0
PGNDLDO1_1
A7
B7
B B
0.85V VCCIO (Banjo#1 VR3) 61 48 47 44 43 42 34 PPBUS_S5_HS_COMPUTING_ISNS

CRITICAL C7960 1 1 C7961 1 C7962
PVCCIO_VBST_R Q7960 33UF
20%
2.2UF
20%
2.2UF
20%
CSD58879Q3D 16V 2 2 25V 2 25V
Q3D TANT X6S-CERM X6S-CERM
R7964
1 CASE-B1S 0402 0402
U7800 0
DIDT=TRUE
VIN 1
P650839A0C
PBGA
5%
1/20W
MF
1 C7963
(4 OF 10) 0.1UF 3 TG
2 201 10% GATE_NODE=TRUE
61 48 47 44 43 42 34 G9 VINVR3
PPBUS_S5_HS_COMPUTING_ISNS VBSTVR3 B11 PVCCIO_VBST 2 25V 6
CRITICAL X6S-CERM
0201 4 TGR VSW 7
OMIT_TABLE DIDT=TRUE 8 L7960
D10 ILIMVR3HS DRVHVR3
65 A12 PVCCIO_DRVH 0.68UH-20%-6.7A-0.0194OHM
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE
PVCCIO_ILIM_LS C9 ILIMVR3LS SWVR3 A11 PVCCIO_SW PVCCIO_SW_LL 1 2 PPVCCIO_S0 5 8 11 61
A9 PVCCIO_DRVL MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE SWITCH_NODE=TRUE 5 BG MIN_LINE_WIDTH=0.6000
PIMS042T-SM
PGND
DRVLVR3
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE GATE_NODE=TRUE DIDT=TRUE
1
C7964 1
C7965 1 C7966 1 C7967
R7961
SWITCH_NODE=TRUE
1
10.5K CKPLUS_WAIVE=MISS_N_DIFFPAIR
270UF
20% 20%
270UF 20UF
20%
20UF
20% Vout = 0.85V
9
B9 PGVR3 (PP) FBVR3+ C10 PVCCIO_FB_P 2 2V 2 2V 2 2.5V 2 2.5V

1%
1/20W
MF 47 46 IN
PVCCIO_EN
NC
E9 ENVR3 FBVR3- D7
TANT
CASE-B2-SM
TANT
CASE-B2-SM
X6S-CERM
0402
X6S-CERM
0402 IccMax = 3A
201 2
R7963 1 F = 900kHz
PGNDVR3
10
5%
1/20W
MF
A 201 2
A
A10
CPU_VCCIOSENSE_P IN 8
PAGE TITLE
CPU_VCCIOSENSE_N IN 8 PMIC-1 1.2V 0.6V VCCIO

DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
79 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1V (Banjo#1 VR1) 61 48 47 44 43 42 34 PPBUS_S5_HS_COMPUTING_ISNS
61 48 47 46 PP5V_G3H CRITICAL C8000 1 C8001 1 1 C8002

Q8000 33UF
20%
2.2UF
20%
2.2UF
20%
CSD58879Q3D 25V 2 25V
1 C8009 Q3D
16V 2
TANT
CASE-B1S
X6S-CERM 2
0402
X6S-CERM
0402
1UF P1VS4_VBST_R
20% VIN 1
2 16V
CER-X5R U7800 1
R8001
DIDT=TRUE
D
0201 P650839A0C
PBGA 5%
0
1/20W
1 C8003 3 TG D
(2 OF 10) MF 0.1UF 6
10%
M10 VREGVR1 VBSTVR1 M11 P1VSUS_VBST 2 201 2 25V 4 TGR VSW 7
X6S-CERM
DIDT=TRUE 0201 8 L8000
CRITICAL DRVHVR1
65 N12 P1VSUS_DRVH 0.68UH-20%-6.7A-0.0194OHM
MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE GATE_NODE=TRUE
P1VS4_ILIM_HS L9 ILIMVR1 OMIT_TABLE SWVR1 N11 P1VSUS_SW P1VSUS_SW_LL 1 2 PP1V_SUS 9 13 16 19 50 61
N9 P1VSUS_DRVL MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE SWITCH_NODE=TRUE 5 BG MIN_LINE_WIDTH=0.6000
PIMS042T-SM
PGND
DRVLVR1
R8000 1 SWITCH_NODE=TRUE
C8004 1 C8005 1 1
C8006 1 C8007 1 C8008
8.66K 270UF 100UF 100UF 20UF 20UF
9
1% M9 PGVR1 FBVR1+ K10 P1VSUS_FB_P 20% 20% 20% 20% 20%
NC 2 2.5V 2 2.5V
PGNDVR1
1/20W 2V 2 6.3V 2 2 6.3V
MF 48 PVCCPCORE_PGOOD M12 ENVR1 FBVR1- J9 P1VSUS_FB_N TANT TANT-POLY TANT-POLY X6S-CERM X6S-CERM
201 2 CASE-B2-SM CASE-A3-LLP CASE-A3-LLP 0402 0402
1
R8003
XW8000
2
10
5%
SM
N10
1/20W
MF
2 201 Vout = 1.0V
1
IccMax = 2.446A
F = 800kHz
C 1.8V (Banjo#1 VR2) C
U7800
P650839A0C
PBGA L8020
60 59 50 49 46 45 18 15 13 9 PP3V3_S5 (3 OF 10)
0.47UH-20%-4.0A-28MOHM PP1V8_SUS 9 13 17 24 33 50 61
67 61
F12 VINVR2_0 SWVR2_0 H12 P1V8SUS_SW 1 2
F13 VINVR2_1 SWVR2_1 H13 MIN_NECK_WIDTH=0.2000 PIFE25201B-SM
CRITICAL
DIDT=TRUE
SWITCH_NODE=TRUE
1
C8022 1 C8023 1 C8024
C8025 1 C8020 1 1 C8021 48 47 46
61
PP5V_G3H E13 VREGVR2 OMIT_TABLE 100UF
20% 20%
20UF 20UF
20%
47UF 2.2UF 2.2UF 2 6.3V 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
20% 20% 20% TANT-POLY
6.3V 2 25V 25V CASE-A3-LLP 0402 0402
POLY-TANT X6S-CERM 2 2 X6S-CERM
0805 0402 0402 1 C8029 65 46 OUT
P1V8SUS_PGOOD E12 PGVR2 FBVR2+ G10 P1V8SUS_FB_P
1UF PM_SLP_SUS_L F11 ENVR2 FBVR2- E10 P1V8SUS_FB_N
R8023 1
51 50 46 15 IN
20%
PGNDVR2_1
PGNDVR2_0
2 16V
CER-X5R R8021 1
100 Vout = 1.8V
0201
R8020 1 10 5%
100
5%
5%
1/20W
MF
1/20W
MF
201 2
IccMax = 0.314A
1/20W
MF
201 2
F = 2MHz
G12
G13
201 2
P1V8SUS_FB_P_RC
C8026 1
0.01UF
10%
10V
X7R-CERM 2
0201
B B
PCH CORE (Banjo#1 VR5) 61 48 47 44 43 42 34 PPBUS_S5_HS_COMPUTING_ISNS

CRITICAL
Q8050 C8013 1 1 C8014 1 C8015
CSD58879Q3D 33UF 2.2UF 2.2UF
Q3D 20% 20% 20%
16V 2 25V
2 X6S-CERM 2 25V
U7800 VIN 1
TANT
CASE-B1S 0402
X6S-CERM
0402
P650839A0C
PBGA
R8051 C8053 3 TG
(6 OF 10)
0 0.1UF
61 48 47 44 43 42 34 L7 VINVR5
PPBUS_S5_HS_COMPUTING_ISNS VBSTVR5 M3 PVCC_VBST 1 2 PVCC_VBST_R 1 2 6
4 TGR VSW 7
10%
CRITICAL
DIDT=TRUE 1/20W
MF
201
DIDT=TRUE
25V
X6S-CERM
8 L8050
K5 ILIMVR5HS DRVHVR5 M1 PVCC_DRVH 0201 1UH-20%-6.3A-0.027OHM
PVCCPCORE_ILIM_LS L5 ILIMVR5LS
OMIT_TABLE
SWVR5 N2 PVCC_SW MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE GATE_NODE=TRUE
PVCC_SW_LL 1 2 PPVCORE_SUS_PCH 9 61
Vout = Based on VID
DRVLVR5 N4 PVCC_DRVL MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE SWITCH_NODE=TRUE 5 BG MIN_LINE_WIDTH=0.6000
PIMS042T-SM IccMax = 1.1A
PGND
PVCCPCORE_PGOOD M4 PGVR5
SWITCH_NODE=TRUE
1
C8054 1
C8055 1 C8056 1 C8057 F = 800kHz
48
100UF 100UF 20UF 20UF
9
20% 20% 20% 20%

M2 ENVR5 2 6.3V 2 6.3V 2 2.5V 2 2.5V
PVCCPCORE_EN FBVR5+ G4 PVCC_FB_P X6S-CERM X6S-CERM
PGNDVR5
46 TANT-POLY TANT-POLY
CASE-A3-LLP CASE-A3-LLP 0402 0402
FBVR5- L4 PVCC_FB_N 1
R8053
10
XW8001
2
5%
A 1/20W
A
N3
MF
R8007 1
SM
2 201 SYNC_MASTER=DEVMLB SYNC_DATE=05/19/2015
5.49K PAGE TITLE
PMIC-1 1V 1.8V VCCPCH

1
1%
1/20W
MF
201 2 DRAWING NUMBER SIZE
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<BRANCH>
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SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1.5V S0 LDO
CRITICAL
U8170
D
TPS72015
D
SON
PP1V5_S0 13 18 39 46 61
61 50 46 36 17 16 14 13 9 PP3V3_SUS 4 BIAS
PP1V8_S3 6 IN OUT 1
Vout = 1.5V
61 50 46 22 21 IN
3 EN Max Current = 0.02A

65 51 50 46 30 15 IN
PM_SLP_S3_L NC 2 NC
THRM
C8170 1 C8171 1 GND PAD 1 C8172
1UF 1UF 5 7 2.2UF
10% 10% 10%
6.3V 6.3V 6.3V
CERM 2 CERM 2 2 X5R
402 402 402
BYPASS=U8170.4::1mm
BYPASS=U8170.6::1mm
1.2V S5 USB-C HS Mux

60 59 50 48 46 45 18 15 13 9
67 61
PP3V3_S5
CRITICAL CRITICAL
R8136 1 C8130 1 C8131 1
C
C 10K 10UF
20%
10UF
20%
1
VIN
CRITICAL
5%
1/20W 10V
X5R-CERM 2
10V
X5R-CERM 2 U8130
MF
201 2 0402-4 0402-4 ISL8009B L8130
R8137 DFN 1.0UH-20%-2.7A-0.056OHM PP1V2_S5SW 60 61
330K 2 EN
P1V2S5SW_HSMUX_EN 1 2 P1V2S5SW_HSMUX_EN_R CRITICAL LX 8 P1V2S5SW_SW 1 2
24 23 IN
5%
MIN_NECK_WIDTH=0.2000 0806 Vout = 1.2V
1/20W P1V2S5SW_PGOOD 3 POR VFB 6 SWITCH_NODE=TRUE CRITICAL
MF
201
DIDT=TRUE 1
R8131 1 C8135 150mA Max Output
4 SKIP RSI 5 10
5%
1/20W
20UF
20% f = 1.6MHZ
GND THRM_PAD MF 2 6.3V
201 CERM-X5R
7 9 2 0402
P1V2S5SW_FB_R CRITICAL
C8136 1
1
R8132 20UF
1 C8132 49.9K
20%
6.3V
22PF 1% CERM-X5R 2
5% 1/20W 0402
2 50V
C0G MF
0201 2 201
P1V2S5SW_FB <Ra>
1
R8133
100K
1%
1/20W
MF
Vout = 0.8V * (1 + Ra / Rb)
2 201
<Rb>
B B
PAGE TITLE
Misc Power Supplies

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SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
5V S0 Switch 1.8V S3 Switch 1.0V S0SW Switch

U8230 (LPDDR3) PP5V_S5
(VCCSTG)
TPS22930 61 57 50 45
PP1V_SUS 9 13 16 19 48 50 61
PP5V_S4 CSP
46 45 42 38 37 29 24
67 63 61 53
A2 VIN VOUT A1 PP5V_S0 U8250
28 29 39 52 61
PP1V8_SUS TPS22924 C8206 1 C8208 1
1
61 48 33 24 17 13 9
PM_SLP_S3_L B2 ON
CRITICAL EDP: 0.45 A A2
CSP
A1 PP1V8_S3 1.0UF 10UF
65 51 50 49 46 30 15 IN 21 22 46 49 61
20% VDD 20%
B2 VIN VOUT B1 6.3V 2 6.3V 2
GND EDP: 0.20 A X5R U8206 X6S
U8230 CRITICAL 0201-1
SLG5AP1635V
0402
B1
P1V8S3_EN C2 ON
C8230 1 Part TPS22930
46 IN
U8250 P1VS0_RAMP 7 CAP
STDFN
D 3
D 1.0UF
20% Type Load Switch C8250 1
GND
Part TPS22924C PM_SLP_S0S3_L 2 CRITICAL 5 PP1V_S0SW
D
C1
ON S
6.3V 2
X5R 1.0UF C8207 1 50 46 19
63 51 IN
EDP: 0.16 A
6 8 12 61 63
0201-1 R(on) 35 mOhm Typ 20%

6.3V 2 Type Load Switch 100PF GND
5%
@ 5V 44 mOhm Max X5R 25V 2 U8206
8
0201-1 R(on) 18.5 mOhm Typ C0G
0201
Current 2A Max @ 2.5V 25.8 mOhm Max Part SLG5AP1635V
Current 2A Max Type Load Switch
R(on) 20 mOhm Typ
@ 4V Vgs 28 mOhm Max
3.3V SUS Switch Current 2.5A Max
HSIO FET de-featured from SKL
leaving placeholder for CNL
U8220
48 46 45 18 15 13 9
67 61 60 59 50 49
PP3V3_S5
A2
TPS22924
VIN
CSP
VOUT
A1 PP3V3_SUS 9 13 14 16 17 36 46 49 61
1.0V SUSSW HSIO Switch
B2 B1 EDP: 0.20 A (VCCGATED)
CRITICAL PP5V_S5
61 57 50 45
PM_SLP_SUS_L C2 ON
51 48 46 15 IN
GND U8220 NOSTUFF
PP1V_SUS 9 13 16 19 48 50
61
NOSTUFF
C8220 1 Part TPS22924C C8205 1
C1
C8209
1
1
1.0UF 1.0UF VDD PLACE_NEAR=U8205:5MM 10UF
1
20% Type Load Switch 20%
6.3V 2
X5R
6.3V 2
X5R U8205 XW8205 20%
6.3V 2
0201-1 R(on) 18.5 mOhm Typ 0201-1 SM X6S
SLG5AP1643V D 2 0402
@ 2.5V 25.8 mOhm Max TDFN
1.2V S0SW Switch
2
D 3
CRITICAL
C Current 2A Max
15 IN
PCH_HSIO_PWR_EN 9 ON NOSTUFF S 5
7
PP1V_SUSSW_HSIO 9 13 61 C
(VCCPLL_OC) NOSTUFF S EDP: 2.12 A
R8240 R8205 1 GND
U8205
3.3V S4 Switch 0 100K
8
2 1 5%
5%
1/20W Part SLG5AP1643V
MF
1/20W 201 2
MF Type Load Switch
U8200 0201
R(on) 7.4 mOhm Typ
49 48 46 45 18 15 13 9
67 61 60 59 50
PP3V3_S5 TPS22924
CSP
U8240 @ 4V Vgs 10.6 mOhm Max
A2 A1 PP3V3_S4 15 18 24 25 26 29 31 46 59 61 61 47 22 21 20 12 8 PP1V2_S3 TPS22924
VIN VOUT CSP
B2 B1 EDP: 1.08 A A2 A1 PP1V2_S0SW 8 12 61 Current 6A Max
B2 VIN VOUT B1 HSIO has turn-on requirement of
CRITICAL EDP: 0.35 A
PM_SLP_S5_L C2 ON 10uS min and 200uS max
CRITICAL
51 45 30 15 IN
GND U8200 PM_SLP_S0S3_L C2 ON NOSTUFF
from EN to 0.95V
C8200 1 Part TPS22924C
63 51 50 46 19 IN
NOSTUFF GND U8220
C1
1.0UF C8240 1 Part TPS22924C
C1
20% Type Load Switch
6.3V 2
X5R
1.0UF
20% Type Load Switch
0201-1 R(on) 18.5 mOhm Typ 6.3V 2
X5R
@ 2.5V 25.8 mOhm Max 0201-1 R(on) 18.5 mOhm Typ
@ 2.5V 25.8 mOhm Max
Current 2A Max
Current 2A Max
3.3V S0 Switch 1.0V S3 Switch

(VCCST)
B U8210 61 57 50 45 PP5V_S5
PP1V_SUS
B
49 48 46 45 18 15 13 9 PP3V3_S5 TPS22924 9 13 16 19 48 50 61
67 61 60 59 50 CSP
A2 A1 PP3V3_S0
VIN VOUT
5 6 14 15 16 17 19 23 26 27 31
33 34 35 39 46 51 53 61 67 C8270 1
1
B2 B1 EDP: 0.94 A 1.0UF VDD
CRITICAL 20%
6.3V 2
PM_SLP_S3_L C2 ON X5R U8270
65 51 50 49 46 30 15 IN
GND U8210 0201-1
SLG5AP1635V
C8210 1 Part TPS22924C P1VS3_RAMP 7 STDFN 3
C1
CAP D
1.0UF CRITICAL
20% Type Load Switch PM_SLP_S4_L 2 ON S 5 PP1V_S3
6.3V 2
X5R C8271 1 46 30 15
63 51 47 IN
EDP: 0.20 A
6 8 12 15 31 42 61
0201-1 R(on) 18.5 mOhm Typ 100PF GND

5%
@ 2.5V 25.8 mOhm Max 25V 2 U8270
8
C0G
0201
Current 2A Max
Part SLG5AP1635V
Type Load Switch
R(on) 20 mOhm Typ
@ 4V Vgs 28 mOhm Max
Current 2.5A Max
PAGE TITLE
Power FETs
DRAWING NUMBER SIZE
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8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Mobile System Power State Table

State
Run (S0)
SMC_ADAPTER_EN
X
SMC_PM_G2_ENABLE
1
PM_SUS_EN
1
PM_SLP_S5_L
1
PM_SLP_S4_L
1
PM_SLP_S3_L
1
S5 Enables SUS & S4 Enables
Sleep (S3AC) 1 1 1 1 1 0 S5_PWR_EN 45 51
MAKE_BASE=TRUE
0 1 1 1 1 0 51 50 45 30 15 PM_SLP_S5_L PM_SLP_S5_L 15 30 45 50 51
Sleep (S3)
S5_PWR_EN OUT 45 51
IN
MAKE_BASE=TRUE
OUT
Deep Sleep (S4) 0
0
1
1
0
0
1
0
0
0
0
0
D8300
0201 S5_PWR_EN 45 51
Deep Sleep (S5) OUT
PM_SLP_S5_L 15 30 45 50 51
Battery Off (G3HotAC) toggle 3Hz 0 0 0 0 0 46 30 IN
SMC_PM_G2_EN A K OUT
Battery Off (G3Hot) 1 0 0 0 0 0

RB521ES-30
D D8301
0201
D
PM_SLP_SUS_L PM_SLP_SUS_L
R8300
51 50 48 46 15 15 46 48 50 51
59 STORAGE_LATCH A K 1 IN
MAKE_BASE=TRUE
OUT
IN
PM_SLP_SUS_L OUT 15 46 48 50 51
47K
RB521ES-30 5%
1/20W
S5 Power Good (3.3V DSW PGOOD based) MF
2 201 S3 Enables
63 51 50 47 46 30 15 IN
PM_SLP_S4_L PM_SLP_S4_L OUT 15 30 46 47 50 51 63
MAKE_BASE=TRUE
51 46 45 30 IN
S5_PWRGD S5_PWRGD OUT 30 45 46 51
MAKE_BASE=TRUE
S0 Enables
51 46 30 15 PMIC_SYS_PWROK PMIC_SYS_PWROK 15 30 46 51
MAKE_BASE=TRUE 65 51 50 49 46 30 15 IN
PM_SLP_S3_L PM_SLP_S3_L OUT 15 30 46 49 50 51 65
MAKE_BASE=TRUE
PM_SLP_S3_L 15 30 46 49 50 51 65
27 26 23 19 17 16 15 14 6 5
67 61 53 50 46 39 35 34 33 31
PP3V3_S0 OUT
PM_SLP_S3_L OUT 15 30 46 49 50 51 65
1
R8303
1K
5%
1/20W
MF
2 201
S0I Enables
51 46 30 15 PMIC_SYS_PWROK
63 51 50 46 19 IN
PM_SLP_S0S3_L PM_SLP_S0S3_L OUT 19 46 50 51 63
MAKE_BASE=TRUE
C 51 46 42 30 IN
ALL_SYS_PWRGD ALL_SYS_PWRGD OUT 30 42 46 51
C
MAKE_BASE=TRUE
B B
PAGE TITLE
Power Control
DRAWING NUMBER SIZE
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<SCH_NUM> D
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SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D 152S00220 D
CRITICAL
CRITICAL L8410 CRITICAL
Q8406
C8410, C8411 SHOULD BE PLACED MIRRORED
15UH-20%-1.8A-0.258OHM D8401
SOD-123
C8415, C8416 SHOULD BE PLACED MIRRORED C8418, C8419 SHOULD BE PLACED MIRRORED
CRITICAL FDC638APZ_SBMS001 PPBUS_SW_BKL 1 2 PPBUS_S0_LCDBKLT_PWR_SW A K PPVOUT_S0_LCDBKLT
CRITICAL
F8400
53
SSOT6-HF 6 MIN_LINE_WIDTH=2.0000 MIN_LINE_WIDTH=2.0000 MIN_LINE_WIDTH=0.5000
3AMP-32V-467 R8400 5
VOLTAGE=8.7V
PIME061H-SM1 MIN_NECK_WIDTH=0.2000
VOLTAGE=45V RB160M-60G CRITICAL CRITICAL CRITICAL CRITICAL
VOLTAGE=45V
0.025 2
59 57 46 45 41 34 29
61
PPBUS_G3H 1 2 PPBUS_S0_LCDBKLT_FUSED
1 PPBUS_SW_LCDBKLT_PWR
4
2
1 C8410 1 C8411 1 C8412 SWITCH_NODE=TRUE
DIDT=TRUE 1 C8415 1 C8416 1 C8418 1 C8419 1
C8417
MIN_NECK_WIDTH=0.2000 1% MIN_NECK_WIDTH=0.2000 4.7UF 4.7UF 0.1UF 2.2UF 2.2UF 2.2UF 2.2UF 0.001UF
603-HF VOLTAGE=8.7V 1/4W VOLTAGE=8.7V 1 10% 10% 10% 10% 10% 10% 10% 10%
FLM NOSTUFF 25V
2 X6S-CERM 2 25V
X6S-CERM 2 25V
X5R 2 50V
X5R 2 50V
X5R 2 50V
X5R 2 50V
X5R 2
50V
CERM
0603
3
1 C8401 0603-1 0603-1 0201 0603 0603 0603 0603 402
1
R8401 1000PF
1 C8400 80.6K
2%
2 25V
1000PF 1% C0G-NP0 C8425, C8426 SHOULD BE PLACED MIRRORED C8428, C8429 SHOULD BE PLACED MIRRORED
10% 1/20W 0201
2 16V
X7R-1 MF
0201 2 201 CRITICAL CRITICAL CRITICAL CRITICAL
1 C8425 1 C8426 1 C8428 1 C8429
2.2UF 2.2UF 2.2UF 2.2UF
LCDBKLT_EN_L R8410 2 10% 10% 10% 10%
PPLCDBKLT_VDDD 1
0 2 PP5V_S0 28 29 39 50 52 61
XW8401
SM
50V
2 X5R
0603
2 50V
X5R
0603
50V
2 X5R
0603
2 50V
X5R
0603
VOLTAGE=5V
5%
1/20W R8411 1
PPLCDBKLT_VDDA
MF
201 1
0 2
VOLTAGE=5V 1/20W
MF
1
R8402 201
1%
63.4K C8440 1 1 C8441
1/20W 1.0UF 1.0UF
MF 20% 20%
10V 2 10V
C 2 201 X5R-CERM 2
0201-1
X5R-CERM
0201-1 C
52 GND_BKLT_SGND
VDDA 18
VDDD 5
1
R8440
1M
5%
1/20W U8401
MF LLP
2 201 LP8548B1SQ-11
BKLT_SD 11 SD SW 2
(PPBUS_S0_BKLT_PWR_R) 9 VSENSE_N SW 1
(PPBUS_S0_BKLT_PWR_F) 10 VSENSE_P FB 21 BKL_FB
GD 4
19 NC
R8442 BKLT_SENSE_OUT SENSE_OUT
0 17 ISET_KEYB 20 NC
5 IN
EDP_BKLT_EN 1 2 BKLT_EN_R EN
5% NO STUFF PWM_KEYB 12 PWM_KEYB KEYB1 13
1/20W NC
MF
0201
1 C8442 15 SCL (IPU)
KEYB2 14 NC
33PF 16
5% SDA (IPU) SW2 6 NC
2 25V
NPO-C0G
0201 FB2 8 NC
52 GND_BKLT_SGND CRITICAL
353S4292
61 52 50 39 29 28 PP5V_S0 R8465 1
GND_SW2
10K
GND_SW
GND_SW
5%
GNDD
GNDA
1/20W
MF THRM
201 2 PAD
R8460 1 1
R8461
24
23
7
3
22
25
1.8K 1.8K
B 5%
1/20W
MF
5%
1/20W
MF
B
201 2 2 201
R8462
0
53 IN
I2C_BKLT_SCL 1 2 BKLT_SCL_R XW8400
SM
5%
1/20W R8463 1 2 GND_BKLT_SGND 52
I2C_BKLT_SDA
MF
0201 1
0 2 BKLT_SDA_R MIN_LINE_WIDTH=0.4000
53 BI MIN_NECK_WIDTH=0.2000
VOLTAGE=0V
5%
1/20W
MF
0201
PAGE TITLE
LCD Backlight Driver

DRAWING NUMBER SIZE
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<SCH_NUM> D
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8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LCD PANEL INTERFACE (eDP) + Camera (MIPI)

63 61 50 46 45 42 38 37 29 24
67
PP5V_S4
1
VDD
U8500
D SLG5AP1443V
TDFN Optional Sense R
D
R8515 LCD_PWR_SLEW 7 CAP D 3
goes here
EDP_PANEL_PWR 1
8.25K 2 PANEL_P5V_EN 2 CRITICAL 5 PP5V_S0SW_LCD PP5V_S0SW_LCD
53 5 IN ON S 53 61 61 53
1%
1/16W GND
MF-LF
402
8
D8517
1 C8511 1 C8512
R8517 0201 1 C8515 1 C8509 10%
0.1UF 10UF
20%
6.98K 2 1.0UF 4700PF
1 PANEL_P5V_EN_D A K
10% 10% 2 10V
X5R-CERM 2 10V
X5R-CERM
1% 2 6.3V
X5R-CERM 2 10V
X7R
0201 0402-7
1/16W RB521ES-30 0201-1 201
MF-LF
402 51 50 46 39
PP3V3_S0 U8510 PP3V3_S0SW_LCD
27 26 23 19 17 16 15 14 6
35 34 33
5
31 TPS22904 MIN_LINE_WIDTH=0.5000
67 61 53 CSP MIN_NECK_WIDTH=0.2000
R8516 A1 VIN VOUT A2 VOLTAGE=3.3V
26.7K 2 CRITICAL
1
R8580
1 PANEL_P3V3_EN B1 ON
GND U8320 5%
2.0K R8581 1
1% 1/20W 2.0K
1/16W
1 C8516 C8510 1 1 C8513 Part TPS22904
MF 5%
B2
MF-LF
402 2 201 1/20W
MF
1.0UF 1.0UF 15PF 201 2
10% 20% 5% Type Load Switch
2 6.3V
6.3V 2 2 16V
R8518 D8518
0201
X5R-CERM
0201-1
X5R
0201-1
NP0-C0G
01005 R(on) 75 mOhm Typ CRITICAL
1.1K PANEL_P3V3_EN_D K A
1
1%
2 @ 2.5V 110 mOhm Max
J8500
1/16W
MF-LF RB521ES-30 Current 500mA Max CFPA342-0250F
402 F-RT-SM-A
54
53
C 52
C
51
50
49
48
47
46
45
44
43
GND SHLD
42
41
40
EDP_PANEL_PWR 39
53 5 38
MIPI_CLK_CONN_P 37
28 OUT 36 MIPI_CLK_CONN_N
35 OUT 28
34 MIPI_DATA_CONN_P
MIPI_DATA_CONN_N 33 OUT 28
28 OUT 32
31
NC 30 PPVOUT_S0_LCDBKLT
PP5V_S0_ALSCAM_F 29 52
5 IN
DP_INT_ML_C_P<0> C8520 1 2 DP_INT_ML_P<0> 28
SMBUS_SMC_1_S0_SCL 27
28 SMBUS_SMC_1_S0_SDA BI 14 30 33 35
0.1UF 10% 16V 35 33 30 14 IN 26 I2C_CAM_SDA

X5R-CERM 0201 25 27
27 IN
I2C_CAM_SCK 24
BI
DP_INT_ML_C_N<0> C8521 1 2 DP_INT_ML_N<0> 23 EDP_BKLT_PWM IN 5 65

5 IN 53 22 SMBUS_SMC_0_S0_SDA
10% 16V 21 30 33
0.1UF X5R-CERM 0201 33 30 IN
SMBUS_SMC_0_S0_SCL 20
BI
19 I2C_BKLT_SCL IN 52
I2C_BKLT_SDA
5 IN
52 BI
17
18 LCD_IRQ_L OUT 17 65
0.1UF 10% 16V 16 DP_INT_ML_N<0>

X5R-CERM 0201 15 53
14
5 IN
DP_INT_ML_C_N<1> C8523 1 2
10% 16V
DP_INT_ML_N<1> 13
12 DP_INT_ML_P<1>
0.1UF 11 53
X5R-CERM 0201 10 DP_INT_ML_N<2>
9 53
5 IN
8
0.1UF 10% 16V 6 DP_INT_ML_P<3>
X5R-CERM0201 5 53
4
B 5 IN
DP_INT_ML_C_N<2> C8525 1 2
10% 16V
DP_INT_ML_N<2> 53
3
1
2
DP_INT_AUX_N 53
B
0.1UF X5R-CERM0201 5 OUT
DP_INT_HPD
5 IN
DP_INT_ML_C_P<3> C8526 1 2
10% 16V
DP_INT_ML_P<3> 53
Bottom side contacts used
C8500 1
0.1UF X5R-CERM 0201 1000PF
Pinout reversed from flex 10%
100V
5 IN
DP_INT_ML_C_N<3> C8527 1 2
10% 16V
DP_INT_ML_N<3> 518S00013 X7R-CERM 2
0603
0.1UF X5R-CERM 0201
5 BI
DP_INT_AUXCH_C_P C8528 1 2
10% 16V
53 DP_INT_AUX_P
0.1UF X5R-CERM 0201
5 BI
DP_INT_AUXCH_C_N C8529 1 2
10% 16V
DP_INT_AUX_N 53
0.1UF X5R-CERM 0201
67
27 26 23 19 17 16 15 14 6 5
61 53 51 50 46 39 35 34 33 31
PP3V3_S0
NO_XNET_CONNECTION=1
LCD Panel HPD & AUX strapping 1
R8503
1M
5%
1/20W
MF
2 201
53 DP_INT_AUX_N
53 DP_INT_AUX_P
NO_XNET_CONNECTION=1 PAGE TITLE
1
R8502
eDP Display Connector
DRAWING NUMBER SIZE
1M
5%
1/20W Apple Inc.
<SCH_NUM> D
MF REVISION
2 201 R
<E4LABEL>

<BRANCH>
85 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
U8600
S3X GND_VOID=TRUE
BGA C8610 0.22UF GND_VOID=TRUE
1 2 =PCIE_SSD_D2R_P<0> 63
OUT
SYM 3 OF 7
REFCLK_P A19 PCIE_CLK100M_SSD_P IN 16 63 65 GND_VOID=TRUE
REFCLK_M A18 PCIE_CLK100M_SSD_N 16 63 65
C8611 0.22UF GND_VOID=TRUE
IN 1 2 =PCIE_SSD_D2R_N<0> 63
OUT
PCIE_TX0_P A17 PCIE_SSD_D2R_C_P<0> GND_VOID=TRUE
D
PCIE_TX0_M A16 PCIE_SSD_D2R_C_N<0>
1 2 =PCIE_SSD_D2R_P<1> OUT 63 D
PRODUCT CAPACITY PCIE_TX1_P A15 PCIE_SSD_D2R_C_P<1> GND_VOID=TRUE
PCIE_TX1_M A14 PCIE_SSD_D2R_C_N<1> C8612 0.22UF GND_VOID=TRUE
CAPACITY2 CAPACITY1 CAPACITY0 1 2 =PCIE_SSD_D2R_N<1> 63
CONFIG OUT
R0864 R0863 R0862
PCIE_TX2_P A13 NC_PCIE_SSD_D2R_CP<2> OUT 63
GND_VOID=TRUE
PCIE_TX2_M A12 NC_PCIE_SSD_D2R_CN<2> 63
000 - 32GB NOSTUFF NOSTUFF NOSTUFF OUT
63 PCIE_SSD_R2D_P<0> 1 2 PCIE_SSD_R2D_C_P<0> 16
OUT IN
001 - 64GB NOSTUFF NOSTUFF ASSEMBLE PCIE_TX3_P A11 NC_PCIE_SSD_D2R_CP<3> OUT 63
GND_VOID=TRUE
010 - 128GB NOSTUFF ASSEMBLE NOSTUFF PCIE_TX3_M A10 NC_PCIE_SSD_D2R_CN<3> 63
OUT
63 PCIE_SSD_R2D_N<0> 1 2 PCIE_SSD_R2D_C_N<0> 16
011 - 256GB NOSTUFF ASSEMBLE ASSEMBLE OUT IN
100 - 512GB ASSEMBLE NOSTUFF NOSTUFF PCIE_RX0_P C17 =PCIE_SSD_R2D_P<0> IN 63

GND_VOID=TRUE
PCIE_RX0_M C16 =PCIE_SSD_R2D_N<0> 63
101 - 1024GB ASSEMBLE NOSTUFF ASSEMBLE IN
63 PCIE_SSD_R2D_P<1> 1 2 PCIE_SSD_R2D_C_P<1> 16
OUT IN
110 - 2048GB ASSEMBLE ASSEMBLE NOSTUFF PCIE_RX1_P C15 =PCIE_SSD_R2D_P<1> IN 63 GND_VOID=TRUE
111 - RESERVED ASSEMBLE ASSEMBLE ASSEMBLE PCIE_RX1_M C14 =PCIE_SSD_R2D_N<1> 63
IN
63 PCIE_SSD_R2D_N<1> 1 2 PCIE_SSD_R2D_C_N<1> 16
OUT IN
PCIE_RX2_P C13 NC_PCIE_SSD_R2DP<2> IN 63
PCIE_RX2_M C12 NC_PCIE_SSD_R2DN<2> IN 63
F18 61 59 58 57 55 54 18 PP1V8_S0SW_SSD_COLD
TP_S3X_DT0 DTO0 PCIE_RX3_P C11 NC_PCIE_SSD_R2DP<3> IN 63
TP_S3X_DT1 G18 DTO1 PCIE_RX3_M C10 NC_PCIE_SSD_R2DN<3>

R8676 R8677 R8674
63
IN 1 1 1
DDR_ATO J21 TP_S3X_DDR_ATO

1
R8604 10K 10K 0
100K 5% 5% 5%
5% 1/32W 1/32W 1/20W
BOOT_FROM_LPSR AF17 S3X_COLD_BOOT_L IN 59
1/20W
MF MF MF MF
2 201 2 01005 2 01005 2 201
CLK_IN AG18 SYSCLK_CLK24M_SSD IN 18 65
CLK_IN_SEL AD17 S3X_CLK_IN_SEL

OPERATION MODE (ODT, CLK FREQ, ETC)
PCIE_ATB0 G16 TP_S3X_PCIE_ATB0
OP_MODE2 OP_MODE1 OP_MODE0
CONFIG R8614 R8615 R8680 PCIE_ATB1 G17 TP_S3X_PCIE_ATB1
C 000 - TEABERRY NOSTUFF NOSTUFF NOSTUFF PCIE_CLKREQ* F12 S3X_PCIE_CLKREQ_L BI 59 C

001 - XB58 GS NOSTUFF NOSTUFF ASSEMBLE JTAG_TRST* AE18 TP_S3X_JTAG_TRST_L
AF18 PP1V8_S0SW_SSD_COLD 18 54 55 57 58 59 61
010 - RESERVED NOSTUFF ASSEMBLE NOSTUFF RESET* S3X_RESET_L 59
IN
011 - X260 NOSTUFF ASSEMBLE ASSEMBLE HOLD_RESET AH18 S3X_HOLD_RESET
100 - RESERVED ASSEMBLE NOSTUFF NOSTUFF PERST* E12 S3X_PERST_L
R8680
59
IN 1
101 - RESERVED ASSEMBLE NOSTUFF ASSEMBLE R8624 10K
JTAG_SEL AG20 S3X_JTAG_SEL 1 2 10K
110
111
-
-
RESERVED
RESERVED
ASSEMBLE
ASSEMBLE
ASSEMBLE
ASSEMBLE
NOSTUFF
ASSEMBLE JTAG_TCK AH19 S3X_JTAG_TCK IN
63
23 5%
1
R8612 5%
1/32W
AH17 24 1/32W 10K MF
JTAG_TDI TP_S3X_JTAG_TDI MF 5% 2 01005
AD20 01005 1/32W
JTAG_TDO TP_S3X_JTAG_TDO MF 59 54 S3X_PMIC_CTRL0
JTAG_TMS AF19 S3X_JTAG_TMS 23 24 63
2 01005
BI
I2C_SCL E8 S3X_I2C_SCL OUT 57 59
I2C_SDA F8 S3X_I2C_SDA
R8678 BI 57 59
AF20 61 59 58 57 55 54 18 PP1V8_S0SW_SSD_COLD
1
0 2 AK18 PMIC_CTRL0 S3X_PMIC_CTRL0 54 59
S3X_XI XI0 AE20 SANDISK_1Y CAPACITY0 CAPACITY1 CAPACITY2
AJ18 PMIC_CTRL1 S3X_PMIC_CTRL1
R8616 R8662 R8663 R8664
59
5% XO0 1 1 1 1
1/20W NC PMIC_CTRL2 AG17 TP_S3X_PMIC_CTRL2
MF AH20 10K 10K 10K 10K
201 PMIC_EXT_CLK_DIS S3X_PMIC_EXT_CLK_DIS 59 5% 5% 5% 5%
AD21 1/32W 1/32W 1/32W 1/32W
PMIC_LOW_PWR S3X_PMIC_LOW_PWR 59 MF MF MF MF
2 01005 2 01005 2 01005 2 01005
61 59 58 57 55 54 18 PP1V8_S0SW_SSD_COLD RET_LPSR_CLEAR AE17 S3X_RET_LPSR_CLEAR 59
SPI_CLK F11 S3X_SPI_CLK

1
R8615 SPI_CS* G12 SSD_BOOT_L IN 17 65
10K E11
PP1V8_S0SW_SSD_COLD 18 54 55 57 58 59 5% SPI_MISO NC
61 1/32W
MF SPI_MOSI G10
NC
2 01005 SPI_NOR_CLK E9
NC
B 1 C8657 1 C8658 SPI_NOR_CS* G11
NC B
0.01UF 0.01UF SPI_NOR_SIO0 H10
10% 10% NC
2 10V 2 10V
T26 ANI03_ZQ_PD SPI_NOR_SO1 C8 S3X_BOOTSTRAP3
X7R-CERM X7R-CERM NC
0201 0201 ANI03_ZQ T25 ANI03_ZQ_PU SPI_NOR_SO2 F10 S3X_BOOTSTRAP4
T5 ANI47_ZQ_PD SPI_NOR_SO3 G9 S3X_BOOTSTRAP5
ANI01_VREF NC
T6 E10
R8605 R8603
58
1 ANI47_ZQ_PU SPI_NOR_RFN
NC NC
ANI23_VREF 58 1%
34.8 1
3.01K 2 S3X_PCIE_REF H17 REXT UART0_RX B8 S3X_SMC_OOB_UART_R2D 59
R8629
1/20W A8 1
10K 2
MF 1% AD11 UART0_TX 59 S3X_SMC_OOB_UART_D2R
2 201
1/20W S3X_GPIO0 GPIO0 B7
MF AD10 UART1_RX S3X_DEBUG_UART_R2D IN 59 63 5%
201
NC GPIO1 A7 1/32W
59 IN
S3X_PFN AE11 GPIO2
UART1_TX S3X_DEBUG_UART_D2R OUT 59
R8673 MF
01005
10K
RETEN_EN H18 S3X_RET_EN_L IN 59 1 2 PP1V8_S0SW_SSD_COLD 18 54 55 57 58 59 61
01005 1/32W
AD12 S3X_DDR_PHY_DATA_VREF 5% MF
DDR_PHY_DATA_VREF
DDR_PHY_ZQ G21 S3X_DDR_PHY_ZQ
1 C8650 1 C8652 DDR_VREFI_ALIVE B23 S3X_DDR_VREFI_ALIVE
0.01UF 0.01UF J20
10% 10% DDR_VREFI_ZQ S3X_DDR_VREFI_ZQ
2 10V
X7R-CERM 2 10V
X7R-CERM AH16 S3X_DDR_VREFO
0201 0201 DDR_VREFO
DDR_ZQ B26 S3X_DDR_ZQ
DDR_CKE0 C20 S3X_DDR_CKE0
DDR_CKE1 C21 S3X_DDR_CKE1
NOSTUFF NOSTUFF
1 1 1 PLACE_NEAR=U8600.G21:3.0MM
R8610 R8611 R8607 1 C8620 1 C8621 1 C8622 1 C8623 1
1.00K 1.00K 240 R8608
5% 5% 1% 1000PF 1000PF 1000PF 1000PF 240
1/32W 1/32W 1/20W 10% 10% 10% 10% 1%
MF MF MF 2 16V
X7R-1 2 16V
X7R-1 2 16V
X7R-1 2 16V
X7R-1 1/20W
2 01005 2 01005 2 201 0201 0201 0201 0201 MF
A 2 PACK_TYPE=201
SYNC_MASTER=X260_EVAN SYNC_DATE=07/27/2015
A
PAGE TITLE
PLACE_NEAR=U8600.B26:3.0MM
BYPASS=U8600.J20::3.0MM
BYPASS=U8600.B23::3.0MM
BYPASS=U8600.AD12::3.0MM S3X CORE, PCIE
BYPASS=U8600.AH16::3.0MM DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
86 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U8600 OMIT_TABLE
S3X
BGA
SYM 4 OF 7
61 59 58 57 55 54 18 PP1V8_S0SW_SSD_COLDH15 PCI_AVDD_H VDD1 A28 61 59 PP1V8_S4SW_SSD_HOT
VDD1 AJ3
BYPASS=U8600.J14::1.5MM
61 59 PP0V9_S0SW_SSD_FIXED J13 PCI_VDD_1
VDD1 AJ28
1 C8710 1 C8711 1 C8712 1 C8713 1 C8714 OMIT_TABLE
J15 PCI_VDD_1 AK15
0.1UF 0.1UF 0.1UF 0.22UF 1.0UF
VDD1 10% 20% 20% 20% 20%
J12 PCI_VDD_1
VDD1 AK16 2 6.3V
X7R
6.3V
2 X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X6S-CERM 2 6.3V
X5R U8600
J14 PCI_VDD_1 0201 01005 01005 0201 0201-1 S3X
VDD1 B21
J17 BGA
1 C8766 1 C8718 1 C8717 PCI_VDD_2 AA11 R19
0.1UF 0.1UF 0.1UF J16 VDDRQ12_AC G19 PP1V2_S0SW_SSD_COLD 55 59 61 61 59 55 PP0V9_S0SW_SSD_CORE VDD SYM 5 OF 7 VDD
PCI_VDD_2
20% 20% 20%
VDDRQ12_AC H20 AA13 VDD VDD R21 1 C8740 1 C8741 1 C8742 1 C8743 1 C8744
D
6.3V
2 X5R-CERM
01005
2 6.3V
X5R-CERM
01005
2 6.3V
X5R-CERM
01005
H16 PCI_VDD_2
VDDRQ12_AC J19 AA15 VDD VDD R23
10%
0.1UF
10%
0.1UF 0.22UF
20%
0.22UF
20% 20%
0.22UF D
K13 PCI_VDD_CLK_1 AA17 VDD VDD T8 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
X7R X7R X6S-CERM X6S-CERM X6S-CERM
K15 PCI_VDD_CLK_1 VDDRQ12_AC_AON K18 PP1V2_S4SW_SSD_HOT 55 59 61
AA19 VDD VDD T10 0201 0201 0201 0201 0201
K12 PCI_VDD_CLK_1 AA21 VDD VDD T12
VDD2 B19 59 61
55 PP1V2_S4SW_SSD_HOT
K14 PCI_VDD_CLK_1 AA23 VDD VDD T14
VDD2 A23
K17 PCI_VDD_CLK_2 VDD2 A27
1 C8720 1 C8721 1 C8722 1 C8723 1 C8724 1 C8725 1 C8728 1 C8729 K22 VDD VDD T16
0.1UF 0.1UF 0.1UF 0.22UF 1.0UF 2.2UF 0.1UF 0.1UF L9 VDD VDD T18
K16 PCI_VDD_CLK_2 VDD2 AJ8 10%
2 6.3V 2
20%
6.3V
2
20%
6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V 2
20%
6.3V
20%
2 6.3V L11 VDD VDD T20
1 C8745 1 C8746 1 C8747 1 C8748 1 C8749
VDD2 AJ15 X7R X5R-CERM X5R-CERM X6S-CERM X5R X5R-CERM X5R-CERM X5R-CERM
L13
0.22UF 0.22UF 0.22UF 0.22UF 0.22UF
61 59 58 57 55 54 18 PP1V8_S0SW_SSD_COLDAB12 VDDIO18_DDR_PLL_D AJ16
0201 01005 01005 0201 0201-1 0201 01005 01005
VDD VDD T22 20%
6.3V
20%
6.3V
20% 20% 20%
AB16 VDD2 L15 U9 2 X6S-CERM 2 X6S-CERM 2 6.3V
X6S-CERM 2 6.3V
X6S-CERM
6.3V
2 X6S-CERM
VDDIO18_DDR_PLL_D AJ23 VDD VDD 0201 0201 0201 0201 0201
VDD2 BYPASS=U8600.K18::1.5MM L17 U11
K19 AK3 BYPASS=U8600.AJ15::1.5MM VDD VDD
VDDIO18_DDR_PLLAC VDD2 L19 U13
AK28 VDD VDD
AB30 VDD2 L21 U15
VDDIO_03 VDD VDD
AB29 VDDIO_03 VDD_03 J25 PP0V9_S0SW_SSD_CORE 61
PP1V2_S0SW_SSD_COLD L23 VDD VDD U17
AB28 VDDIO_03 VDD_03 L25
55
59
M8 VDD VDD U19
1 C8750 1 C8751 1 C8752 1 C8753
4.7UF 4.7UF 4.7UF 4.7UF
J30 VDDIO_03 VDD_03 R25 1 C8734 1 C8735 1 C8760 1 C8761 1 C8762 1 C8763 1 C8764 M10 VDD VDD U21 20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
AC25 VDDIO_03 VDD_03 AA25 0.1UF 0.22UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF M12 VDD VDD U23 X6S
0402
X6S
0402
X6S
0402
X6S
0402
20% 20% 20% 20% 20% 20% 20%
V26 VDDIO_03 VDD_03 U25 6.3V
2 X5R-CERM 2 6.3V 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 2 6.3V 2 6.3V 2 6.3V M14 VDD VDD V8
X5R X5R-CERM X5R-CERM X5R-CERM
W25 VDDIO_03 VDD_03 L24 01005 01005-1 01005 01005 01005 01005 01005 M16 VDD VDD V10
Y26 VDDIO_03 VDD_03 AB25 M18 VDD VDD V12
M26 R24 BYPASS=U8600.G19::1.5MM M20
VDDIO_03 VDD_03 VDD
P26 VDDIO_03 VDD_03 W24
BYPASS=U8600.H20::1.5MM
BYPASS=U8600.J19::1.5MM M22 VDD VDD V16
1 C8754 1 C8755 1 C8756 1 C8757
N9 V18
10UF 10UF 10UF 10UF
R27 VDDIO_03 VDD VDD 20% 20% 20% 20%
VDD_47 R7 2 4V 2 4V 2 4V 2 4V
J23 VDDIO_03 N11 VDD VDD V20 X6S X6S X6S X6S
VDD_47 L7 0402 0402 0402 0402
AB20 VDDIO_03 N13 VDD VDD V22
VDD_47 W7
AB22 VDDIO_03 N15 VDD VDD W9
VDD_47 AB6
AB24 N17 W11
C AC21
VDDIO_03
VDDIO_03
VDD_47 J6
L6
N19
VDD
VDD
VDD
VDD W13 C
AC23 VDD_47 N21 W15
VDDIO_03 R6 VDD VDD
K26 VDD_47 N23 W19
VDDIO_03 U6 VDD VDD
N25 VDDIO_03
VDD_47
VDD_47 AA6 L8700 P8 VDD VDD W21
AA27 VDDIO_03
22NH-5%-0.1A P10 VDD VDD W23
H22 VDDIO_03 VDD_PLL4 Y25 PP0V9_PLL_DVDD47 1 2 PP0V9_S0SW_SSD_CORE 55 59 61
P12 VDD VDD Y10
H24 V25 MIN_LINE_WIDTH=0.2000 01005 P14 Y12
VDDIO_03 VDD_PLL5 MIN_NECK_WIDTH=0.1000 VDD VDD
H26 VDDIO_03 VDD_PLL6 K25 VOLTAGE=0.9V
L8701 P16 VDD VDD Y14
J27 VDDIO_03 VDD_PLL7 P25 22NH-5%-0.1A P18 VDD VDD Y16
J28 VDDIO_03 VDD_PLL8 K6 PP0V9_PLL_DVDD811 1 2 PP0V9_S0SW_SSD_CORE 55 59 61
P20 VDD VDD Y18
J29 P6 MIN_LINE_WIDTH=0.2000 01005 P22 Y20
VDDIO_03 VDD_PLL9 MIN_NECK_WIDTH=0.1000 VDD VDD
L27 VDDIO_03 VDD_PLL10 Y6 VOLTAGE=0.9V
L8702 R9 VDD VDD Y22
N27 VDDIO_03 VDD_PLL11 V6 VOLTAGE=0.9V
MIN_NECK_WIDTH=0.1000 22NH-5%-0.1A R11 VDD
AB27 W18 MIN_LINE_WIDTH=0.2000 1 2 R13 VDD_S V14 TP_S3X_VDD_S
VDDIO_03 VDD_PLL_C PP0V9_PLL_C_DVDD03 PP0V9_S0SW_SSD_CORE VDD
U27 VDDIO_03 01005 R15 VDD
VDD18_EFUSE0 AA7 CKPLUS_WAIVE=PWRTERM2GND
W27 VDDIO_03 R17 VDD
VDD18_EFUSE1 AA8 CKPLUS_WAIVE=PWRTERM2GND
H5 VDDIO_47 VDD18_EFUSE2 AA9 CKPLUS_WAIVE=PWRTERM2GND
J1 VDDIO_47 VDD18_EFUSE3 AA10 CKPLUS_WAIVE=PWRTERM2GND
AB1 AB19
AB2
VDDIO_47 VDD18_XTAL PP1V8_S0SW_SSD_COLD 18 54 55 57
58 59 61 R8700
VDDIO_47 Y23 1
25.5 2
AB3 VDDA18_PLL4 55 PP1V8_PLL_AVDD47 PP1V8_S0SW_SSD_COLD
VDDIO_47 V24 MIN_LINE_WIDTH=0.2000
J7 VDDA18_PLL5 MIN_NECK_WIDTH=0.1000 1%
VDDIO_47 K23 VOLTAGE=1.8V 1/20W
J9 VDDA18_PLL6 MF
J11
VDDIO_47
VDDA18_PLL7 P24 201
R8701
VDDIO_47 K8 PP1V8_PLL_AVDD811 1
25.5 2
K10 VDDA18_PLL8
55 PP1V8_S0SW_SSD_COLD
VDDIO_47 P7 MIN_LINE_WIDTH=0.2000
VDDA18_PLL9 MIN_NECK_WIDTH=0.1000 1%
B AB4
AB7
VDDIO_47
VDDIO_47
VDDA18_PLL10 Y8 VOLTAGE=1.8V
BYPASS=U8600.W17::1.5MM
BYPASS=U8600.W17::1.5MM
1/20W
MF
201
B
VDDA18_PLL11 V7
J2
J3
VDDIO_47
VDDA18_PLL_C W17 PP1V8_PLL_C_AVDD R8702 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
VDDIO_47 Y19 1
25.5 2
J4 VDDA18_TS PP1V8_S0SW_SSD_COLD 117S0161 1 RES,MF,0 OHM,1/32W,01005I L8704 CRITICAL
VDDIO_47 MIN_LINE_WIDTH=0.2000
AB9 AB13 MIN_NECK_WIDTH=0.1000 1%
VDDIO_47 VDDRQ12 VOLTAGE=1.8V 1/20W
MF
K5 VDDIO_47 VDDRQ12 AC12
AB11 VDDIO_47 VDDRQ12 AC14
1 C8787 1 C8786 1 C8788
201
L4 VDDIO_47 VDDRQ12 AD13 20%

10UF
20%
10UF
10UF
1 C8798
2 4V 2 4V 20% 0.1UF
M5 VDDIO_47 VDDRQ12 AE14 X6S X6S 2 4V 10%
0402 0402 X6S 6.3V
1 C8700 1 C8701 1 C8702 1 C8703 N4 VDDIO_47 VDDRQ12 AF13 0402 2 X7R
0201 PP1V8_PLL_AVDD47
BYPASS=U8600.Y24::1.5MM
BYPASS=U8600.U24::1.5MM
0.1UF 0.1UF 0.22UF 0.22UF N6 VDDIO_47 VDDRQ12 AF15 55
BYPASS=U8600.N24::1.5MM
20% 20% 20% 20% S3X_VSSA18_PLL_C
6.3V 6.3V 6.3V 6.3V P5 VDDIO_47 VDDRQ12 AG14 56
2 X5R-CERM
01005
2 X5R-CERM
01005
2 X6S-CERM
0201
2 X6S-CERM
0201 R4 VDDIO_47 VDDRQ12 AH13 PP1V2_S0SW_SSD_COLD 55 59 61
1 C8790 1 C8791 1 C8792 1 C8793
U4
0.1UF 0.1UF 0.1UF 0.1UF
VDDIO_47 VDDRQ12 AH15 10% 10% 10% 10%
2 6.3V 2 6.3V 2 6.3V 6.3V
V5 VDDIO_47 VDDRQ12 AB15 1 C8730 1 C8731 1 C8732 1 C8733 1 C8736 1 C8737
S3X_VSSA18_PLL4
X7R
0201
X7R
0201
X7R
0201
2 X7R
0201
W4 VDDIO_47 VDDRQ12 AC16 0.1UF 0.22UF 1.0UF 2.2UF 0.1UF 0.1UF 56
10% 20% 20% 20% 20% 20%
S3X_VSSA18_PLL5
W6 VDDIO_47 VDDRQ12 AD15 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
2 6.3V 56
X7R X6S-CERM X5R X5R-CERM X5R-CERM X5R-CERM
AC6 AE16 0201 0201 0201-1 0201 01005 01005 56 S3X_VSSA18_PLL6
VDDIO_47 VDDRQ12
AC8 AG16 56 S3X_VSSA18_PLL7
VDDIO_47 VDDRQ12
1 C8704 1 C8705 1 C8706 1 C8707 Y5 VDDIO_47 VDDRQ12 AK13 BYPASS=U8600.AG14::1.5MM
BYPASS=U8600.AE16::1.5MM BYPASS=U8600.K7::1.5MM
BYPASS=U8600.N7::1.5MM
1.0UF 1.0UF 2.2UF 4.7UF AC10 VDDIO_47 VDDRQ12 AK4 55 PP1V8_PLL_AVDD811 BYPASS=U8600.Y7::1.5MM
20% 20% 20% 20% BYPASS=U8600.U7::1.5MM
2 6.3V 2 6.3V 2 6.3V 2 6.3V AA4 VDDIO_47 VDDRQ12 AK6
X5R X5R X5R-CERM X6S 1 C8709 1 C8785 1 C8708 1 C8726 1 C8727 1 C8789
0201-1 0201-1 0201 0402
A21 VDDCA
VDDRQ12 AK8
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
1 C8794 1 C8795 1 C8796 1 C8797
VDDRQ12 AK10 20% 20% 20% 20% 20% 20% 0.1UF 0.1UF 0.1UF 0.1UF
61 59 55 PP1V2_S4SW_SSD_HOT A25 VDDCA AK12 2 6.3V
2 6.3V
2 6.3V
2 6.3V
2 6.3V
2 6.3V 10% 10% 10% 10%
VDDRQ12 X5R-CERM
01005
X5R-CERM
01005
X5R-CERM
01005
X5R-CERM
01005
X5R-CERM
01005
X5R-CERM
01005 2 6.3V
X7R 2 6.3V
X7R 2 6.3V
X7R
6.3V
2 X7R
A VDDRQ12 AK14
AK17
56 S3X_VSSA18_PLL8 0201 0201 0201 0201
A
VDDRQ12 BYPASS=U8600.AK4::1.5MM 56 S3X_VSSA18_PLL9 PAGE TITLE
AK19
1 C8784 1 C8716
VDDRQ12
VDDRQ12 AK21
56 S3X_VSSA18_PLL10
S3X_VSSA18_PLL11 S3X_VDDR12_CK_PLANE
S3X POWER
C8781 C8782 C8783 C8780
56 55
0.1UF 0.1UF 1 1 1 1 BYPASS=U8600.K20::1.5MM DRAWING NUMBER SIZE
20% 20%
VDDRQ12 AK23
6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 0.1UF 0.22UF 0.1UF 0.1UF BYPASS=L8704.2::1.0MM
<SCH_NUM> D
AK25 Apple Inc.
01005 01005 VDDRQ12
AK27
10%
2 6.3V
X7R
20%
2 6.3V
X6S-CERM 2
20%
6.3V
2
20%
6.3V C8765 1 C8719 REVISION
VDDRQ12 X5R-CERM X5R-CERM
0.1UF 0.1UF
BYPASS=U8600.A21::1.5MM
0201 0201 01005 01005 BOMOPTION=OMIT_TABLE
1 2 20%
R
<E4LABEL>
BYPASS=U8600.A25::1.5MM
VDD12_DDRAC_CK K20 55 S3X_VDDR12_CK_PLANE L8704 6.3V
2 X5R-CERM NOTICE OF PROPRIETARY PROPERTY: BRANCH
1.0UF 22NH-5%-0.1A 20% 01005 <BRANCH>

C8715 61 6.3V THE INFORMATION CONTAINED HEREIN IS THE
1 2 1 2 59
55 PP1V2_S0SW_SSD_COLD X5R-CERM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
01005
6.3V X5R
20% 0201-1 BYPASS=U8600.K20::1.5MM
01005 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
87 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
55 S3X_VSSA18_PLL4 Y24 VSS_PLL4
U8600 VSS AG19
G23 VSS VSS P13 NC
H2 ANI4_IO0 U8600 ANI5_IO0 R2
NC
55 S3X_VSSA18_PLL5 U24 VSS_PLL5
S3X
VSS AG21
G24 VSS
U8600 VSS P15 NC
G3 ANI4_IO1 S3X ANI5_IO1 P3
NC
S3X_VSSA18_PLL6 K24 VSS_PLL6 VSS AG23 S3X G2 ANI4_IO2 BGA ANI5_IO2 P2
55
BGA G25 VSS VSS P17 NC NC
S3X_VSSA18_PLL7 N24 VSS_PLL7 VSS AG25 BGA G1 ANI4_IO3 SYM 2 OF 7 ANI5_IO3 P1
55
SYM 6 OF 7
G26 VSS VSS P19 NC NC
S3X_VSSA18_PLL8 K7 VSS_PLL8 VSS AG27 SYM 7 OF 7 D2 ANI4_IO4 ANI5_IO4 L2
55 G27 VSS VSS P21 NC NC
S3X_VSSA18_PLL9 N7 VSS_PLL9 VSS AG28 D1 ANI4_IO5 ANI5_IO5 L1
55 H3 VSS VSS P23 NC NC
S3X_VSSA18_PLL10 Y7 VSS_PLL10 VSS AH4 C2 ANI4_IO6 ANI5_IO6 K2
55 H4 VSS VSS P27 NC NC
S3X_VSSA18_PLL11 U7 VSS_PLL11 VSS AH14 C1 ANI4_IO7 ANI5_IO7 K1
55 H6 VSS VSS R3 NC NC
S3X_VSSA18_PLL_C V17 VSS_PLL_C VSS AH27
55 H7 VSS VSS R5 G6 ANI4_NCE(0) ANI5_NCE(0) B3
VSS AJ1 NC NC
A1 VSS H8 VSS VSS R8 E7 ANI4_NCE(1) ANI5_NCE(1) D4
D A2 VSS
VSS
VSS
AJ2
AJ4
H11 VSS VSS R10
NC
NC
E6 ANI4_NCE(2) ANI5_NCE(2) E4
NC
NC
D
A9 VSS H12 VSS VSS R12 G7 ANI4_NCE(3) ANI5_NCE(3) B4
VSS AJ6 NC NC
A20 VSS H13 VSS VSS R14 D8 ANI4_NCE(4) ANI5_NCE(4) A4
VSS AJ10 NC NC
A29 VSS H14 VSS VSS R16 A6 ANI4_NCE(5) ANI5_NCE(5) D5
VSS AJ12 NC NC
A30 VSS H19 VSS VSS R18 H9 ANI4_NCE(6) ANI5_NCE(6) B5
VSS AJ13 NC NC
AA5 VSS H21 VSS VSS R20 G8 ANI4_NCE(7) ANI5_NCE(7) A5
VSS AJ14 NC NC
AA12 VSS H23 VSS VSS R22
VSS AJ17 D7 ANI4_ALE ANI5_ALE F4
AA14 VSS H25 VSS VSS R26 NC NC
VSS AJ19 F6 ANI4_CLE ANI5_CLE A3
AA16 VSS H27 VSS VSS R28 NC NC
VSS AJ21 C3 ANI4_NWE ANI5_NWE K3
AA18 VSS H28 VSS VSS T3 NC NC
VSS AJ25 D6 ANI4_RNB ANI5_RNB C4
AA20 VSS J5 VSS VSS T4 NC NC
VSS AJ27
AA22 VSS J8 VSS VSS T7 B6 ANI4_PPM_IN ANI5_PPM_IN G5 NC
VSS AJ29 NC
AA24 VSS J10 VSS VSS T9 C6 ANI4_PPM_OUT ANI5_PPM_OUT E5 NC
VSS AJ30 NC
AA26 VSS J18 VSS VSS T11
VSS AK1 E2 ANI4_NRE_P ANI5_NRE_P M2 NC
AB5 VSS J22 VSS VSS T13 NC
VSS AK2 E1 ANI4_NRE_N ANI5_NRE_N M1 NC
AB8 VSS J24 VSS VSS T15 NC
VSS AK29
AB10 VSS J26 VSS VSS T17 F2 ANI4_DQS_P ANI5_DQS_P N2 NC
VSS AK30 NC
AB14 VSS K4 VSS VSS T19 F1 ANI4_DQS_N ANI5_DQS_N N1 NC
VSS B1 NC
AB17 VSS K9 VSS VSS T21
VSS B2 H1 ANI4_VREF ANI5_VREF R1 NC
AB18 VSS K11 VSS VSS T23 NC
VSS B9
AB21 VSS K21 VSS VSS T24 AC2 ANI6_IO0 ANI7_IO0 T2 NC
VSS B10 NC
AB23 VSS K27 VSS VSS T27 AD1 ANI6_IO1 ANI7_IO1 U1 NC
VSS B11 NC
AB26 VSS L3 VSS VSS T28 AD2 ANI6_IO2 ANI7_IO2 U2 NC
VSS B12 NC
AC3 VSS L5 VSS VSS U5 AD3 ANI6_IO3 ANI7_IO3 U3 NC
VSS B13 NC
AC4 VSS L8 VSS VSS U8 AG1 ANI6_IO4 ANI7_IO4 Y1 NC
VSS B14 NC
AC5 VSS L10 VSS VSS U10 AG2 ANI6_IO5 ANI7_IO5 Y2 NC
VSS B15 NC
AC7 L12 U12 AH1 ANI7_IO6 AA1 NC
C AC9
VSS
VSS
VSS B16
B17
L14
VSS
VSS
VSS
VSS U14
NC
NC
AH2
ANI6_IO6
ANI6_IO7 ANI7_IO7 AA2 NC
C
AC11 VSS L16 U16
VSS B18 VSS VSS AK11
AC13 VSS L18 U18 NC ANI6_NCE(0) ANI7_NCE(0) AK5 NC
VSS B27 VSS VSS AJ11
AC15 VSS L20 U20 NC ANI6_NCE(1) ANI7_NCE(1) AK7 NC
VSS B28 VSS VSS AH10
AC17 VSS L22 U22 NC ANI6_NCE(2) ANI7_NCE(2) AJ7 NC
VSS B29 VSS VSS AH9
AC18 VSS L26 U26 NC ANI6_NCE(3) ANI7_NCE(3) AJ5 NC
VSS B30 VSS VSS AH12
AC19 VSS L28 V3 NC ANI6_NCE(4) ANI7_NCE(4) AH5 NC
VSS C5 VSS VSS AH11
AC20 VSS M3 V4 NC ANI6_NCE(5) ANI7_NCE(5) AH7 NC
VSS C7 VSS VSS AG9
AC22 VSS M4 V9 NC ANI6_NCE(6) ANI7_NCE(6) AG7 NC
VSS C9 VSS VSS AG11
AC24 VSS M6 V11 NC ANI6_NCE(7) ANI7_NCE(7) AG5 NC
VSS C18 VSS VSS
AC26 VSS M7 V13 AJ9
VSS C22 VSS VSS NC ANI6_ALE ANI7_ALE AG6 NC
AC27 VSS M9 AK9
VSS C23 VSS NC ANI6_CLE ANI7_CLE AH6 NC
AC28 VSS M11 V19 AH3
VSS C24 VSS VSS NC ANI6_NWE ANI7_NWE AA3 NC
AD4 VSS M13 V21 AG12
VSS C25 VSS VSS NC ANI6_RNB ANI7_RNB AF6 NC
AD5 VSS M15 V23
VSS C26 VSS VSS AG10
AD6 VSS M17 V27 NC ANI6_PPM_IN ANI7_PPM_IN AG8 NC
VSS C27 VSS VSS AF10
AD7 VSS M19 V28 NC ANI6_PPM_OUT ANI7_PPM_OUT AH8 NC
VSS D3 VSS VSS
AD8 VSS M21 W3 AF1
VSS D9 VSS VSS NC ANI6_NRE_P ANI7_NRE_P W1 NC
AD9 VSS M23 W5 AF2
VSS D10 VSS VSS NC ANI6_NRE_N ANI7_NRE_N W2 NC
AD14 VSS M24 W8
VSS D11 VSS VSS AE1
AD16 VSS M25 W10 NC ANI6_DQS_P ANI7_DQS_P V1 NC
VSS D12 VSS VSS AE2
AD18 VSS M27 W12 NC ANI6_DQS_N ANI7_DQS_N V2 NC
VSS D13 VSS VSS
AD19 VSS M28 W14 AC1
VSS D14 VSS VSS NC ANI6_VREF ANI7_VREF T1 NC
AD24 VSS N3 W16
VSS D15 VSS VSS
AD25 VSS N5 W20
VSS D16 VSS VSS
AD26 VSS N8 W22
VSS VSS VSS
B AD27 VSS
VSS
VSS
D17
D18
N10 VSS VSS W26 B
AE3 VSS N12 VSS VSS W28
VSS D27
AE4 VSS N14 VSS VSS Y3
VSS D28
VSS E3
VSS E13
VSS E14
VSS E15
VSS E16
VSS E17
AE12 VSS P4 VSS VSS Y21
VSS E18
VSS E27
VSS E28
AE19 VSS
VSS F3 VSS_S V15 TP_S3X_VSS_S
AE21 VSS
VSS F5
AE22 VSS
VSS F7
AE23 VSS
VSS F9
AE25 VSS
VSS F13
AE26 VSS
VSS F14
AE27 VSS
VSS F15
AE28 VSS
VSS F16
AF3 VSS
VSS F17
AF4 VSS
VSS F19
AF5 VSS
VSS F20
AF7 VSS
VSS F22
AF8 VSS
VSS F24
AF9 VSS
A AF11 VSS
VSS F25
F26 SYNC_MASTER=DEVMLB SYNC_DATE=05/11/2015 A
AF12 VSS PAGE TITLE
VSS F27
VSS
AF14 VSS
VSS F28 S3X GND
AF16 VSS DRAWING NUMBER SIZE
VSS G4
AF27 VSS
VSS G13 Apple Inc.
<SCH_NUM> D
AF28 VSS REVISION
VSS G14
AG3 VSS
VSS G15
R
<E4LABEL>
AG4 VSS NOTICE OF PROPRIETARY PROPERTY: BRANCH
VSS G20
AG13 VSS
VSS G22 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
AG15 VSS THE POSESSOR AGREES TO THE FOLLOWING: PAGE
88 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DEVICE 2-WIRE ADDRESS ADD0 PIN CONNECTION

1001010 SDA
PLACE U9010 Opposite of S3X controller

61 59 58 55 54 18 PP1V8_S0SW_SSD_COLD
1 1
R9010 R9011 1 C9010 BYPASS=U9010.5::3.0MM
4.7K 4.7K 5 0.01UF
5% 5% 10%
1/20W 1/20W V+
MF MF 2 10V
D 2 201 2 201 U9010

HPA00330AI
X5R-CERM
0201 D
SOT563
S3X_I2C_SDA 6 4 S3X_I2C_SDA 59
59 57 54 BI SDA ADD0 54
57
S3X_I2C_SCL 1 3
59 54 BI SCL ALERT NC
GND
2
61 59 58 57 PP3V3R2V7_NAND_VCC 61 50 45 PP5V_S5 61 59 52 46 45 41 34 29
PPBUS_G3H
R9001 1 1
R9006 P2V7NAND_BOOT_RC C9003 1 C9002 1 1 C9000 1 C9001
2.2 2.2 MIN_LINE_WIDTH=0.3000 33UF 33UF 2.2UF 2.2UF
5% 5% MIN_NECK_WIDTH=0.2000 20% 20% 20% 20%
1/20W 1/20W DIDT=TRUE 16V 2 16V 2 2 25V
X5R-CERM 2 25V
X5R-CERM
MF MF PP2V7_NAND_PVCC TANT TANT
0402-1 0402-1
201 201 MIN_LINE_WIDTH=0.6000 CASE-B1S CASE-B1S
2 2
VOLTAGE=5V 1 C9016 1
PP2V7_NAND_VCC 1
C9021 R9009 0.1UF
2.2 10%
MIN_LINE_WIDTH=0.6000 10UF 16V
5% X7R-CERM 2
VOLTAGE=5V 6.3V 1/20W 0402
2 CERM-X6S MF
201 2
0402
CRITICAL
C
19
20
C 1
C9022
2.2UF VCC PVCC P2V7NAND_VBST
Q9001
CSD58879Q3D
R9003 1 1
R9031 10%
10V
U9000 MIN_LINE_WIDTH=0.3000
R9039
Q3D CRITICAL
10K
1%
10K
0.1%
2 X6S-CERM
0402
ISL95870AH
DIDT=TRUE
0 VIN 1 CRITICAL
R9030
2 1 0.003
1/20W
MF
1/20W
MF PICCOLO_VEN1 15 EN UTQFN
BOOT 18
P2V7NAND_DRVH_R
5%
P2V7NAND_DRVH
MIN_LINE_WIDTH=0.6000 L9000 1%
1/2W PP3V3R2V7_NAND_VCC
201 2 2 0201-1 59 IN MIN_NECK_WIDTH=0.2000
GATE_NODE=TRUE 1/20W
GATE_NODE=TRUE
3 TG 0.68UH-20%-6.7A-0.0194OHM MF 57 58 59 61
NO_XNET_CONNECTION=1 NO_XNET_CONNECTION=1 CRITICAL MF 0306

P2V7NAND_SENSE_DIV 10 FB UGATE 17
DIDT=TRUE
0201
DIDT=TRUE 6 P2V7NAND_SW_LL 1 2 P2V7NAND_R 1 2
4 TGR VSW 7 MIN_LINE_WIDTH=0.6000
MIN_NECK_WIDTH=0.2000 PIMS042T-SM MIN_LINE_WIDTH=0.6000
3 4
P2V7NAND_SREF 7 SREF PHASE 16 P2V7NAND_LL
8 SWITCH_NODE=TRUE
DIDT=TRUE
VOLTAGE=2.7V
P2V7NAND_VO 12 VO LGATE 1
SWITCH_NODE=TRUE
1
R9017 DIDT=TRUE
C9005 1 C9006 1 1
C9008 1
C9007 1 C9004
191K P2V7NAND_OCSET 11 OCSET
5 BG 10UF 10UF 150UF 150UF 12PF
PGND
0.1% 65 P2V7NAND_DRVL
1/20W 20% 20% 20% 20% 5%
PICCOLO_POK1 14 PGOOD
MIN_LINE_WIDTH=0.6000 10V 10V 2 6.3V 2 6.3V 2 25V
MF 59 OUT MIN_NECK_WIDTH=0.2000 X5R-CERM 2 X5R-CERM 2 POLY-TANT POLY-TANT NP0-C0G
2 0201 GATE_NODE=TRUE 0402-1 0402-1 CASE-B3-SM CASE-B3-SM 0201
P2V7NAND_RTN_DIV 4 RTN
DIDT=TRUE
9
13 P2V7NAND_P
FSEL
P2V7NAND_SET0 8 SET0
C9023 1
0.01UF P2V7NAND_SET1 9 SET1

P2V7NAND_N 1 C9009 1 C9011 1 C9012
10% 12PF 12PF 12PF
10V 5% 5% 5%
2
1 6 2 25V 2 25V 2 25V
R9018
X7R-CERM
0201 VID0 NP0-C0G NP0-C0G NP0-C0G
95.3K 0201 0201 0201
5
0.1%
1/20W
VID1 R9021 1
MF 1.87K NO_XNET_CONNECTION=1
2 0201 1%
GND PGND 1/20W
MF C9070
P2V7NAND_SET_R 2200PF
201 2
Vout = 2.85V
3
2
2 1
R9000
B 1
7.5K
2 10%
Freq = 1 MHz B
25V
1%
1/20W
CER-X7R
0201
1
R9072 Max OCP = 6.54 A
MF 1.87K
1 1
201 1% Nom OCP = 5.3 A
1 C9026 R9004 R9002 1 C9015
1/20W
10PF 1%
10K 10K
0.1% 10PF
MF
2 201 Min OCP = 4.1 A
5% 1/20W 1/20W 5%
2 50V
C0G MF MF 2 50V
C0G
0201 2 201 2 0201-1 0201
XW9000
SM
P2V7NAND_AGND 1 2
MIN_NECK_WIDTH=0.2000 PLACE_NEAR=U9000.3:1mm
VOLTAGE=0V
A SYNC_MASTER=X260_KUMAR SYNC_DATE=06/16/2015 A
PAGE TITLE
NAND VR, I2C ROM, TEMP SENSORS

DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
90 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
58 ANI0_IO<0> AC29 ANI0_IO0 U8600 ANI1_IO0 T29 ANI1_IO<0> 58

NAND INTERFACE 2/3 TOP
58 ANI0_IO<1> AD30 ANI0_IO1 S3X ANI1_IO1 U30 ANI1_IO<1> 58
AD29 U29 61 59 58 57 55 54 18 PP1V8_S0SW_SSD_COLD
58 ANI0_IO<2> ANI0_IO2 BGA ANI1_IO2 ANI1_IO<2> 58
58 ANI0_IO<3> AD28 ANI0_IO3 SYM 1 OF 7 ANI1_IO3 U28 ANI1_IO<3> 58 61 59 58 57 PP3V3R2V7_NAND_VCC

58 ANI0_IO<4> AG30 ANI0_IO4 ANI1_IO4 Y30 ANI1_IO<4> 58
ANI0_IO<5> AG29 ANI0_IO5 ANI1_IO5 Y29 ANI1_IO<5> C9124 1 C9125 1 C9126 1 C9133 1 C9134 1
C9121 C9122 C9123
58 58
C9120 1 1 1 1
ANI0_IO<6> AH30 ANI0_IO6 ANI1_IO6 AA30 ANI1_IO<6> 1.0UF 0.22UF 0.1UF 0.1UF 0.1UF
58
AH29 AA29
58
0.1UF 0.22UF 1.0UF 0.22UF 20% 20% 10% 10% 10%
58 ANI0_IO<7> ANI0_IO7 ANI1_IO7 ANI1_IO<7> 58
10% 20% 20% 20% 6.3V
2 6.3V
2 6.3V
2 6.3V
2 6.3V
2
6.3V
CERM-X5R 2 6.3V
X6S-CERM 2 2 6.3V
X5R 2 6.3V
X6S-CERM
X5R
0201-1
X6S-CERM
0201
CERM-X5R
0201
CERM-X5R
0201
CERM-X5R
0201
AG22 AJ24 0201 0201 0201-1 0201
58 ANI0_NCE<0>
AD23
ANI0_NCE(0) ANI1_NCE(0)
AG26
ANI1_NCE<0> 58
R9192 NOSTUFF
58 ANI0_NCE<1> ANI0_NCE(1) ANI1_NCE(1) ANI1_NCE<1> 58
NAND_ZQ_U9120 1
300 2
D
58 ANI0_NCE<2> AF21 ANI0_NCE(2) ANI1_NCE(2) AH26 ANI1_NCE<2> 58
D
OC0
OD0
OC8
OD8
OA8
OB0
OE0
OF8
AD22 AF24 1%
G3
58 ANI0_NCE<3> ANI0_NCE(3) ANI1_NCE(3) ANI1_NCE<3> 58 1/20W
AF22 AF26 MF
NC ANI0_NCE(4) ANI1_NCE(4) NC VPP 201
AF23 AK24 VCC VCCQ
NC ANI0_NCE(5) ANI1_NCE(5) NC
AJ20 AE24 OMIT_TABLE
NC ANI0_NCE(6) ANI1_NCE(6) NC N3
NC
AK20 ANI0_NCE(7) ANI1_NCE(7) AH24
NC
58
58
ANI2_IO<0>
ANI2_IO<1> N5
DQ0-0
DQ1-0
U9120 CE0* N1 ANI2_NCE<0> 58
LGA CLE-0 L7 ANI2_CLE

58 ANI0_ALE AH23 ANI0_ALE ANI1_ALE AK26 ANI1_ALE 58 58 ANI2_IO<2> M2 DQ2-0
58
PP1V8_S0SW_SSD_COLD 61
18 54 55
J7
TH58TFT1DFKLAVHDB2
NAND-DDR2-2CH-256GB-1YNM-3.3V
AK22 AG24 M6 ALE-0 ANI2_ALE 58 57 58 59
58 ANI0_CLE ANI0_CLE ANI1_CLE ANI1_CLE 58 58 ANI2_IO<3> DQ3-0 N7
AH28 AA28 L5 WE-0* ANI2_NWE 58
58 ANI0_NWE ANI0_NWE ANI1_NWE ANI1_NWE 58 58 ANI2_IO<4> DQ4-0
AJ22 AJ26
58 ANI0_RNB ANI0_RNB ANI1_RNB NC 58 ANI2_IO<5> K6
K2
DQ5-0
RE-0 J5 ANI2_NRE_N 58
1
R9102
AH22 AF25 58 ANI2_IO<6> DQ6-0 10K
NC ANI0_PPM_IN ANI1_PPM_IN NC J3 RE-0* H4 ANI2_NRE_P 58 5%
AH21 AH25 58 ANI2_IO<7> DQ7-0 1/20W
NC ANI0_PPM_OUT ANI1_PPM_OUT NC MF
DQS-0 M4 ANI2_DQS_P 2 201
58 ANI0_NRE_P AF30 ANI0_NRE_P ANI1_NRE_P W30 ANI1_NRE_P 58 58 ANI3_IO<0> A3 DQ0-1
58
AF29 W29 A5 DQS-0* L3 ANI2_DQS_N 58

58 ANI0_NRE_N ANI0_NRE_N ANI1_NRE_N ANI1_NRE_N 58 58 ANI3_IO<1> DQ1-1
ANI3_IO<2> B2 DQ2-1 RY/BY* H6 ANI2_RNB
58 ANI0_DQS_P AE30 ANI0_DQS_P ANI1_DQS_P V30 ANI1_DQS_P 58
58 58
ANI3_IO<3> B6 DQ3-1 WP* F6 NAND_WP_L

58 ANI0_DQS_N AE29 ANI0_DQS_N ANI1_DQS_N V29 ANI1_DQS_N 58
58 58 59
58 ANI3_IO<4> C5 DQ4-1
CE1* A1 ANI3_NCE<0>
58 54 ANI01_VREF AC30 ANI0_VREF ANI1_VREF T30 ANI01_VREF 54 58 58 ANI3_IO<5> D6 DQ5-1
58
OUT OUT
CLE-1 C7 ANI3_CLE 58
ANI3_IO<6> D2 DQ6-1
58 ANI2_IO<0> H29 ANI2_IO0 ANI3_IO0 R29 ANI3_IO<0> 58
58
ALE-1 E7 ANI3_ALE 58
ANI3_IO<7> E3 DQ7-1
ANI2_IO<1> G28 ANI2_IO1 ANI3_IO1 P28 ANI3_IO<1>
58
WE-1* A7 ANI3_NWE
58
58 ANI2_IO<2> G29 ANI2_IO2 ANI3_IO2 P29 ANI3_IO<2>

58
58
NAND INTERFACE 0/1 TOP 58
G0 RE-1 E5 ANI3_NRE_N
58 ANI2_IO<3> G30 ANI2_IO3 ANI3_IO3 P30 ANI3_IO<3> 58 PP1V8_S0SW_SSD_COLD 18 54 55 57 58 59 61 NC 58
G1 RE-1* F4 ANI3_NRE_P
58 ANI2_IO<4> D29 ANI2_IO4 ANI3_IO4 L29 ANI3_IO<4> 58
NC NC
58
61 59 58 57 PP3V3R2V7_NAND_VCC G5
58 ANI2_IO<5> D30 ANI2_IO5 ANI3_IO5 L30 ANI3_IO<5> 58
NC
C29 K29 NOSTUFF NC
G7 DQS-1 B4 ANI3_DQS_P 58
ANI2_IO<6> ANI2_IO6 ANI3_IO6 ANI3_IO<6>
C9101 C9102 C9103 C9104 C9105
58 58
1 1 1 1 1 1 1 1 1 DQS-1* C3
C 58 ANI2_IO<7> C30 ANI2_IO7 ANI3_IO7 K30 ANI3_IO<7> 58
C9100
0.1UF
10%
0.22UF
20%
1.0UF
20%
2.2UF
20%
1.0UF
20%
0.22UF
20%
C9106
0.1UF
10%
C9113
0.1UF
10%
C9114
0.1UF
10%
ANI3_DQS_N 58
C
58 ANI2_NCE<0> B22 ANI2_NCE(0) ANI3_NCE(0) A26 ANI3_NCE<0> 58
6.3V
2 6.3V
2 2 6.3V 2 6.3V 6.3V
2 6.3V
2 6.3V
2 6.3V
2 6.3V
2
CERM-X5R X6S-CERM X5R X6S X5R X6S-CERM CERM-X5R CERM-X5R CERM-X5R
58 ANI2_NCE<1> C19 ANI2_NCE(1) ANI3_NCE(1) D24 ANI3_NCE<1> 58
0201 0201 0201-1 0402 0201-1 0201 0201 0201 0201
D22 A24 VREF G8 ANI23_VREF

R9190 IN 54 58
58 ANI2_NCE<2> ANI2_NCE(2) ANI3_NCE(2) ANI3_NCE<2> 58 NOSTUFF
58 ANI2_NCE<3> E22 ANI2_NCE(3) ANI3_NCE(3) D25 ANI3_NCE<3> 58 300
NAND_ZQ_U9100 1 2
F21 ANI2_NCE(4) ANI3_NCE(4) D23 CE2* L1 ANI2_NCE<1>
NC NC 58
OC0
OD0
OC8
OD8
OA8
OB0
OE0
OF8
D19 E24 1%
C1
G3
NC ANI2_NCE(5) ANI3_NCE(5) NC
1/20W CE3* ANI3_NCE<1> 58
D21 D26 MF
ANI2_NCE(6) ANI3_NCE(6) VPP 201 CE4* J1 ANI2_NCE<2>
NC NC 58
E21 B25 VCC VCCQ E1
NC ANI2_NCE(7) ANI3_NCE(7) NC CE5* ANI3_NCE<2> 58
OMIT_TABLE H2
E20 E25 N3 CE6* ANI2_NCE<3> 58
58
58
ANI2_ALE
ANI2_CLE A22
ANI2_ALE
ANI2_CLE
ANI3_ALE
ANI3_CLE E26
ANI3_ALE
ANI3_CLE
58
58
58
58
ANI0_IO<0>
ANI0_IO<1> N5
DQ0-0
DQ1-0
U9100 CE0* N1 ANI0_NCE<0> 58 CE7* F2 ANI3_NCE<3> 58
C28 K28 M2 LGA CLE-0 L7 ANI0_CLE 58 VSS/VSSQ

58 ANI2_NWE ANI2_NWE ANI3_NWE ANI3_NWE 58 58 ANI0_IO<2> DQ2-0
ALE-0 J7
TH58TFT1DFKLAVHDB2
NAND-DDR2-2CH-256GB-1YNM-3.3V
D20 B24 ANI0_ALE 58
ANI2_RNB ANI2_RNB ANI3_RNB ANI0_IO<3> M6 DQ3-0 PP1V8_S0SW_SSD_COLD
D4
K4
OA0
OB8
OE8
OF0
58
NC 58
WE-0* N7 ANI0_NWE 58 18 54 55 57 58 59 61
ANI0_IO<4> L5 DQ4-0
E19 ANI2_PPM_IN ANI3_PPM_IN F23 58
NC NC ANI0_IO<5> K6 DQ5-0
B20 ANI2_PPM_OUT ANI3_PPM_OUT E23 58
RE-0 J5 ANI0_NRE_N NOSTUFF
NC NC
R9100 R9101
58
58 ANI0_IO<6> K2 DQ6-0 1 1
E29 M29 J3 RE-0* H4 ANI0_NRE_P 58
58 ANI2_NRE_P ANI2_NRE_P ANI3_NRE_P ANI3_NRE_P 58 58 ANI0_IO<7> DQ7-0 10K 1K
E30 M30 5% 5%
58 ANI2_NRE_N ANI2_NRE_N ANI3_NRE_N ANI3_NRE_N 58 1/20W 1/20W
A3 DQS-0 M4 ANI0_DQS_P 58 MF MF
F29 ANI1_IO<0> DQ0-1 2 201 2 201
ANI3_DQS_P N29
58
58 ANI2_DQS_P ANI2_DQS_P ANI3_DQS_P 58
A5 DQS-0* L3 ANI0_DQS_N 58
F30 ANI1_IO<1> DQ1-1
ANI3_DQS_N N30
58
58 ANI2_DQS_N ANI2_DQS_N ANI3_DQS_N 58
58 ANI1_IO<2> B2 DQ2-1 RY/BY* H6 58 ANI0_RNB
58 54 ANI23_VREF H30 ANI2_VREF ANI3_VREF R30 ANI23_VREF 54 58 58 ANI1_IO<3> B6 DQ3-1 WP* F6 59 58 NAND_WP_L
OUT OUT
58 ANI1_IO<4> C5 DQ4-1
CE1* A1 ANI1_NCE<0> 58
58 ANI1_IO<5> D6 DQ5-1
CLE-1 C7 ANI1_CLE 58
58 ANI1_IO<6> D2 DQ6-1
ALE-1 E7 ANI1_ALE
B B
58
58 ANI1_IO<7> E3 DQ7-1
WE-1* A7 ANI1_NWE 58
G0 RE-1 E5 ANI1_NRE_N
NC 58
G1 RE-1* F4 ANI1_NRE_P
NC NC
58
G5
NC
NC
G7 DQS-1 B4 ANI1_DQS_P 58
DQS-1* C3 ANI1_DQS_N 58
VREF G8 ANI01_VREF IN 54 58
CE2* L1 ANI0_NCE<1> 58
CE3* C1 ANI1_NCE<1> 58
CE4* J1 ANI0_NCE<2> 58
CE5* E1 ANI1_NCE<2> 58
CE6* H2 ANI0_NCE<3> 58
CE7* F2 ANI1_NCE<3> 58
VSS/VSSQ
D4
K4
OA0
OB8
OE8
OF0
61 59 58 57 PP3V3R2V7_NAND_VCC
A SYNC_MASTER=DEVMLB SYNC_DATE=05/13/2015
A
PAGE TITLE
1 C9191 1 C9192 1 C9193 1 C9194 NAND & ANI[3:0]

4.7UF 4.7UF 4.7UF 4.7UF DRAWING NUMBER SIZE
20% 20% 20% 20%
2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R Apple Inc.
<SCH_NUM> D
0402 0402 0402 0402 REVISION
R
<E4LABEL>

<BRANCH>
91 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PICCOLO I2C INTERFACE ADDRESSES
P0V9_FIXED_FB WRITE:78H
READ:79H U9300
D2331
U9300
D2331
1
R9300 WLCSP
SYM 4 OF 8
WLCSP CRITICAL 0
SYM 2 OF 8 5% S3X_PMIC_LOW_PWR
54 E7 PMIC_LOW_POWER
67 61 60 59
45 18 15 13 9
50 49 48 46
PP3V3_S5 M1 VDD_BUCK1
BUCK1_FB_DIS K3
L9300 1/16W
MF-LF 54 S3X_PMIC_EXT_CLK_DIS C6 PMIC_EXT_CLK_DIS C3
M2 VDD_BUCK1
1.0UH-20%-2.7A-0.056OHM 2 402 C4 PFN S3X_PFN OUT 54
S3X_PMIC_CTRL0 PMIC_CTRL0/DEBUG
R9357 J2
54
1
1 C9300 1 C9301 1 C9302 BUCK1_LX0 L1 P0V9_FIXED_SW
DIDT=TRUE
1 2 61 55 PP0V9_S0SW_SSD_FIXED
100K
1
R9358 54 S3X_PMIC_CTRL1 C5 PMIC_CTRL1
PERST*
RESET* D3
S3X_PERST_L
S3X_RESET_L
OUT 54
0.1UF 4.7UF 4.7UF H1

0806 100K E8 OUT 54
BUCK5_FB_DIS J3 RET_LPSR_CLEAR
P1V8_HOT_FB 5% S3X_RET_LPSR_CLEAR
VDD_BUCK5 G4
C9303 C9304 C9305
54
10% 20% 20% 1 1 1 1/20W 5% BOOT_FROM_LPSR S3X_COLD_BOOT_L 54
1/20W OUT
2 6.3V 2 6.3V 6.3V
2 X6S 2.2UF 2.2UF 20UF
MF MF
X7R X6S BUCK5_LX0 J1 2 201
D
P1V8_HOT_SW K2
2 201 S3X_PCIE_CLKREQ_L PCIE_CLKREQ_L_1.8V* LPDDR3_RET* C2 S3X_RET_EN_L
D
0201 0402 0402 20% 20% 20% 54 BI OUT 54
DIDT=TRUE
2 10V 2 10V 2 6.3V
VSS(VSS_BUCK1_5) K1 1
R9310 CER-X6S
0402
CER-X6S
0402
CERM-X5R
0402
S3X_I2C_SCL F5 I2C_SCL
0 57 54 IN
CRITICAL 5% 57 54 S3X_I2C_SDA F6 I2C_SDA
1/16W BI
L9310 MF-LF
2 402
1UH-20%-1.5A-0.175OHM
1 2 61
55 PP1V8_S4SW_SSD_HOT 59 50 49 48 46 45 18 15 13 9 PP3V3_S5
67 61 60
PIXW1210-SM
NOSTUFF
1 C9310 1 C9311 1 C9312 1 C9313
1
R9373
10K
20%
20UF
20%
4.7UF
10%
1000PF
5%
12PF 5%
1/20W
U9300
2 6.3V 2 6.3V 2 16V 2 25V MF D2331
CERM-X5R X6S X7R-1 NP0-C0G WLCSP
0402 0402 0201 0201 2 201
SYM 6 OF 8
54 S3X_DEBUG_UART_D2R G5 LS1P8_IN1 LS1P8_OUT1 G6 S3X_DEBUG_UART_R2D 54 63
IN OUT
54 S3X_SMC_OOB_UART_D2R G7 LS1P8_IN2 LS1P8_OUT2 G8 S3X_SMC_OOB_UART_R2D 54
IN OUT
63 24 23 SSD_DEBUG_UART_R2D H6 LS3P3_IN1 LS3P3_OUT1 H5 SSD_DEBUG_UART_D2R 23 24 63

IN OUT
P0V9_REG_FB 65 30 SMC_OOB1_R2D_L H8 LS3P3_IN2 LS3P3_OUT2 H7 SMC_OOB1_D2R_L 30
IN OUT
D8 VEN1 D7 PICCOLO_VEN1
U9300
1
R9320
59 57 IN
PICCOLO_POK1
PICCOLO_POK2 C8
POK1
POK2 VEN2 C7 NC_PICCOLO_VEN2
OUT 57 1
R9372
CRITICAL 0 59 10K
D2331 5% 5%
1/20W
WLCSP
SYM 1 OF 8
L9320 1/16W
MF-LF MF
2 201
1.0UH-20%-2.7A-55MOHM 2 402
67 61
L6 VDD_BUCK0_01 BUCK0_FB_DIS J4 1 2 61 59 58 57 PP3V3R2V7_NAND_VCC 49 48 46 45 18 15 13 9
PP3V3_S5
50
18
49 48
15 13 9 PP3V3_S5 M6 VDD_BUCK0_01
67 61 60 59 50
46
60
45
59 BUCK0_LX0 L5 P0V9_REG_SW0 PIFE25201B-SM
BUCK0_LX0 M5 DIDT=TRUE
L9321
1
R9376 1
R9375
1 C9320 1 C9321 BUCK0_LX1 L7
1.0UH-20%-2.7A-55MOHM
61 55 PP0V9_S0SW_SSD_CORE
1%
1K 20K
C
1.0UF 10UF 5%
C 20%
2 6.3V
20%
2 6.3V
BUCK0_LX1 M7 P0V9_REG_SW1 1 2 1/20W
MF
1/20W
MF
X5R CERM-X6S DIDT=TRUE PIFE25201B-SM 2 201 2 201
0201-1 0402 VSS(VSS_BUCK0) L8
VSS(VSS_BUCK0) M4
CRITICAL 1 C9322 1 C9323 1 C9324 1 C9325
22UF 22UF 22UF 22UF PICCOLO_POK1 PICCOLO_POK2
VSS(VSS_BUCK0) M8
57 59 59
20% 20% 20% 20%
2 10V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM
0603-1 0603-1 0603-1 0603-1
U9300 R9330
D2331 0
WLCSP 1 2
SYM 3 OF 8 CRITICAL
5%
61 60 59 50
PP3V3_S5 A2 BUCK3_FB_DIS D2 P1V2_HOT_FB
VDD_BUCK3 1/16W
L9330
45 18 15 13 9
49 48 46 MF-LF
67
402 1.0UH-20%-2.7A-0.056OHM
BUCK3_LX0 A3 59 50 49 48 46 45 18 15 13 9 PP3V3_S5 26 25 24 18 15 PP3V3_S4
67 61 60 61 50 46 31 29 PP3V3_S5
BUCK3_LX0 B3
59 50 49 48 46 45 18 15 13 9
P1V2_HOT_SW 1 2 61 59 55 PP1V2_S4SW_SSD_HOT 67 61 60
1 C9330 1 C9331 1 C9332 1 C9333 VSS(VSS_BUCK3_4) A4

DIDT=TRUE 0806
1 C9334 1 C9335 1 C9336
1.0UF 10UF 1.0UF 10UF R9384
20% 20% 20% 20% VSS(VSS_BUCK3_4) B4 R9340 22UF 22UF 12PF
1
2 6.3V
X5R 2 6.3V
CERM-X6S 2 6.3V
X5R 2 6.3V
CERM-X6S
A6
1
0 2
20%
2 10V
20%
2 10V
5%
2 25V 1
R9380 1
R9381 1
R9386 R9388 1 5%
10K
0201-1 0402 0201-1 0402 BUCK4_FB_DIS E5 P1V8_COLD_FB X5R-CERM X5R-CERM NP0-C0G 100K
B6
VDD_BUCK4_01
VDD_BUCK4_01
5%
1/16W
L9340 0603-1 0603-1 0201 10K 10K 0 5%
1/20W
MF
BUCK4_LX0 A5 MF-LF 1.0UH-20%-2.7A-55MOHM 5%
1/20W
5%
1/20W
5%
1/20W
1/20W
MF U9300 2 201
61 59 58
402 MF MF MF 201 2
BUCK4_LX0 B5 P1V8_COLD_SW0 1 2 57 55
54 18 PP1V8_S0SW_SSD_COLD D2331
2 201 2 201 2 201 WLCSP
DIDT=TRUE PIFE25201B-SM
BUCK4_LX1 A7 SYM 5 OF 8
B BUCK4_LX1 B7 P1V8_COLD_SW1 CRITICAL PICCOLO_PID0 J7
F7
PID0 PGOOD E3 PICCOLO_PGOOD B
DIDT=TRUE PICCOLO_PID1 PID1 WP* D6 PICCOLO_WP_L
VSS(VSS_BUCK4) A8 K8
SSD_SR_EN_L LPSR_EN* STORAGE_LATCH J8 STORAGE_LATCH
VSS(VSS_BUCK4) B8
65 15 IN OUT 51
PICCOLO_NOR_CS_L K7 NOR_CS*
1 C9340 1 C9341 1 C9342 1 C9343 1 C9344 24_CLK_REQ J6 TP_PICCOLO_24M_CLK_REQ
22UF 22UF 22UF 22UF 12PF STORAGE_EN L2 STORAGE_EN
20% 20% 20% 20% 5%
2 10V
X5R-CERM
0603-1
2 10V
X5R-CERM
0603-1
2 10V
X5R-CERM
0603-1
2 10V
X5R-CERM
0603-1
2 25V
NP0-C0G
0201
5 IN
SSD_RESET_L L4
K6
STORAGE_RST* R9385 1
PD* 0
5%
50 49 48 46 45 18 15 13 9 PP3V3_S5 1/20W
67 61 60 59
16 SSD_CLKREQ_L M3 PCIE_CLKREQ* MF
BI
201 2
61 59 58 57 55 54 18 PP1V8_S0SW_SSD_COLD PICCOLO_VPUMP
NAND_WP_L
1 C9350 1 C9351 1 C9352 1 C9354 C9345 1 C9346 1
58 OUT
10%
0.01UF 2.2UF
20% 20%
10UF 1 C9353 0.01UF 12PF 12PF
2 25V
X7R 2 10V
CER-X6S 2 6.3V
CERM-X6S
0.1UF 10% 5%
25V 2
5%
25V 2
10% 2 25V
402 0402 0402 2 6.3V X7R NP0-C0G NP0-C0G
R9387
H4
D5
B2
J5
X7R 402 0201 0201 46 45 18 15 13 9 PP3V3_S5

0201 67 61 60 59 50 49 48 100K
1 2 PD_L
V_BUF_1.8V
VCORE_A
VCORE_D
VPUMP
IUVD VDIVIDER: R2221 5%

3S - 215K 1/20W
MF
CRITICAL
2S - 348K
57
46
41 PPBUS_G3H
201
Q9351 D 3
29
34
DMN32D2LFB4
45 DFN1006H4-3
52 SYM_VER_2
U9300
61
R9350 1
D2331
1.3M WLCSP 1 G S 2
5% (PD AT PCH PAGE)
1/20W
F1
SYM 7 OF 8 SSD_PWR_EN_L
VREF G2
14 IN
MF 59 58 57 PP3V3R2V7_NAND_VCC VSENSE1 PICCOLO_VREF
201 2 61
A F3 VSENSE2 IREF F2 PICCOLO_IREF

A
PICCOLO_IUVD E2 IUVD VCC_DIS E1 PP3V3R2V7_NAND_VCC 57 58 59 61 PAGE TITLE
PICCOLO_VPP_OTP E6 VDD_RTC G1 PICCOLO_VDD_RTC U9300 PICCOLO PMIC

1 C9362 1
R9351 VPP_OTP
D2331 DRAWING NUMBER SIZE
0.01UF 348K PP1V2_S4SW_SSD_HOT A1 1.2V_COLD_OUT C1 PP1V2_S0SW_SSD_COLD WLCSP
10% 1% 61 59 55
B1
1.2V_COLD_IN 61 55
SYM 8 OF 8 Apple Inc.
<SCH_NUM> D
2 10V 1/20W 1.2V_COLD_IN PLACE_NEAR=U9300.F2:1.0MM D4 D1
X7R-CERM
0201
MF
2 201
1
R9355 1 C9356 1 C9358 1 C9359 1
R9360 E4
VSS VSS
H3
REVISION
<E4LABEL>
C9361
R
10K 1 VSS VSS

1% 22UF 0.01UF 0.1UF 200K F4 K5
1/20W 20% 10% 10% 1% 0.1UF VSS VSS NOTICE OF PROPRIETARY PROPERTY: BRANCH
MF 2 10V
X5R-CERM 2 10V
X5R-CERM 2 6.3V
X7R 1/20W 10% F8 VSS VSS L3 <BRANCH>
2 201 0603-1 0201 0201 MF 2 6.3V
X7R
2 201 0201 K4 VSS VSS H2 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
G3 VSS I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
93 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
USB-C B2B RECEPTACLE

516S00038
CRITICAL
J9600
BM28P0.6-44DS-0.35V
F-ST-SM
D
45 46
GND_VOID
D
24 23 BI
USBC_XA_CC1 1 2
3 4 TRUE USB3_EXTA_D2R_C_N 60
24 BI
USBC_XA_SBU1 5 6 TRUE USB3_EXTA_D2R_C_P 60
OMIT_TABLE OMIT_TABLE 61 49 PP1V2_S5SW 7 8

PCH_BSSB_DATA 9 10 TRUE USB3_EXTA_R2D_N
K D9600 K D9601 17
17
BI
PCH_BSSB_CLK 11 12 TRUE USB3_EXTA_R2D_P
60
60
OUT
GDZ5V1LP37 GDZ5V1LP37 PP3V3_S5 13 14
DFN0603 DFN0603 59 50 49 48 46 45 18 15 13 9
67 61
A A 24 23 IN
USBC_XA_I2C_EN 15 16 TRUE DP_XA_ML_P<0> 60
24 23 19 IN
DP_XA_HPD 17 18 TRUE DP_XA_ML_N<0> 60
24 IN
I2C_UPC_XA_DBG_CTL_SCL 19 20
24 BI
I2C_UPC_XA_DBG_CTL_SDA 21 22 USBC_XA_USB_TOP_N BI 24
23 24 USBC_XA_USB_TOP_P BI 24
24 BI
USBC_XA_USB_BOT_N 25 26
24 BI
USBC_XA_USB_BOT_P 27 28 TRUE DP_XA_ML_P<1> 60
29 30 TRUE DP_XA_ML_N<1> 60
60 24 BI
DP_XA_AUXCH_P 31 32
60 24 BI
DP_XA_AUXCH_N 33 34 TRUE DP_XA_ML_P<2> 60
24 BI
USBC_XA_SBU2 35 36 TRUE DP_XA_ML_N<2> 60
37 38
24 23 BI
USBC_XA_CC2 39 40 TRUE DP_XA_ML_P<3> 60
41 42 TRUE DP_XA_ML_N<3> 60
43 44
PPVBUS_LIO 47 48
K D9602 K D9603 61 24 23
C GDZ5V1LP37
DFN0603
GDZ5V1LP37
DFN0603 C
A A

371S00075 4 DIODE,ZENER,6.2V,250MW,DFN0603 D9600,D9601,D9602,D9603 CRITICAL
USB3 AC COUPLING
GND_VOID=TRUE (ALL CAPS)
65 16 OUT
USB3_EXTA_D2R_P C9620 1 2
10% 16V 0201
USB3_EXTA_D2R_C_P 60
0.1UF X5R-CERM
B 65 16 OUT
USB3_EXTA_D2R_N C9621 1 2
10% 16V 0201
USB3_EXTA_D2R_C_N 60
B
0.1UF X5R-CERM
16 IN
USB3_EXTA_R2D_C_P C9622 1 2
10% 16V 0201
USB3_EXTA_R2D_P 60
0.1UF X5R-CERM
16 IN
USB3_EXTA_R2D_C_N C9623 1 2
10% 16V 0201
USB3_EXTA_R2D_N 60
0.1UF X5R-CERM
DP SNK0 AC COUPLING
GND_VOID=TRUE (ALL CAPS)
23 5 IN
DP_XA_ML_C_P<0> C9630 1 2
10% 16V 0201
DP_XA_ML_P<0> 60
0.1UF X5R-CERM
23 5 IN
DP_XA_ML_C_N<0> C9631 1 2
10% 16V 0201
DP_XA_ML_N<0> 60
0.1UF X5R-CERM
23 5 IN
DP_XA_ML_C_P<1> C9632 1 2
10% 16V 0201
DP_XA_ML_P<1> 60
0.1UF X5R-CERM
23 5 IN
DP_XA_ML_C_N<1> C9633 1 2
10% 16V 0201
DP_XA_ML_N<1> 60
0.1UF X5R-CERM
23 5 IN
DP_XA_ML_C_P<2> C9634 1 2
10% 16V 0201
DP_XA_ML_P<2> 60
0.1UF X5R-CERM
23 5 IN
DP_XA_ML_C_N<2> C9635 1 2
10% 16V 0201
DP_XA_ML_N<2> 60
0.1UF X5R-CERM
23 5 IN
DP_XA_ML_C_P<3> C9636 1 2
10% 16V 0201
DP_XA_ML_P<3> 60
0.1UF X5R-CERM
DP_XA_ML_C_N<3> C9637 1 2 DP_XA_ML_N<3>
A 23 5 IN
0.1UF 10% 16V
X5R-CERM
0201
60
PAGE TITLE
23 5 BI
DP_XA_AUXCH_C_P C9638 1 2
10% 16V 0201
DP_XA_AUXCH_P BI 24 60 LIO Flex Connector
0.1UF X5R-CERM DRAWING NUMBER SIZE
23 5 BI
DP_XA_AUXCH_C_N C9639 1 2
10% 16V 0201
DP_XA_AUXCH_N BI 24 60
Apple Inc.
<SCH_NUM> D
0.1UF X5R-CERM REVISION
R
<E4LABEL>

<BRANCH>
96 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
"G3Hot" (Always-Present) Rails 3.3V Rails
1.2V Rails
61 59 57
41 34 29
52 46 45
PPBUS_G3H PPBUS_G3H 61
29 34 41 45 46 52 57 59
PP3V3_S5 PP3V3_S5
SSD Rails
MIN_LINE_WIDTH=0.6000 59 50 49 48 46 45 18 15 13 9 9 13 15 18 45 46 48 49 50 59 60
MIN_NECK_WIDTH=0.2000 67 61 60 MIN_LINE_WIDTH=0.6000 VOLTAGE=3.3V 61 67 61 50 47 22 21 20 12 8 PP1V2_S3 PP1V2_S3 8 12 20 21 22 47 50 61
VOLTAGE=8.6V MIN_NECK_WIDTH=0.1000 MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6000 61 59 58 57 PP3V3R2V7_NAND_VCC PP3V3R2V7_NAND_VCC 57 58 59
MAKE_BASE=TRUE MIN_NECK_WIDTH=0.1500 MIN_LINE_WIDTH=0.6000 61
PP3V3_S5 9 13 15 18 45 46 48 49 50 59 60 VOLTAGE=1.2V MIN_NECK_WIDTH=0.1000
PPBUS_G3H 29 34 41 45 46 52 57 59 61 61 67 MAKE_BASE=TRUE VOLTAGE=3.3V
PP3V3_S5 9 13 15 18 45 46 48 49 50 59 60 MAKE_BASE=TRUE
PPBUS_G3H 29 34 41 45 46 52 57 59 61 61 67
PP3V3_S5 9 13 15 18 45 46 48 49 50 59 60 PP1V2_S3 8 12 20 21 22 47 50 61 PP3V3R2V7_NAND_VCC 57 58 59
PPBUS_G3H 29 34 41 45 46 52 57 59 61 61 67 61
PP3V3_S5 9 13 15 18 45 46 48 49 50 59 60 PP1V2_S3 8 12 20 21 22 47 50 61
PPBUS_G3H 29 34 41 45 46 52 57 59 61 61 67
61
PP3V3_S5 9 13 15 18 45 46 48 49 50 59 60 PP1V2_S3 8 12 20 21 22 47 50 61 54 18 PP1V8_S0SW_SSD_COLD PP1V8_S0SW_SSD_COLD 18 54 55
PPBUS_G3H 29 34 41 45 46 52 57 59 61 61 67 61 59 58 57 55 MIN_LINE_WIDTH=0.0950 57 58 59
PP3V3_S5 9 13 15 18 45 46 48 49 50 59 60 PP1V2_S3 8 12 20 21 22 47 50 61 MIN_NECK_WIDTH=0.2000
PPBUS_G3H 29 34 41 45 46 52 57 59 61 61 67 VOLTAGE=1.8V
PP3V3_S5 9 13 15 18 45 46 48 49 50 59 60 PP1V2_S3 8 12 20 21 22 47 50 61 MAKE_BASE=TRUE
PPBUS_G3H 29 34 41 45 46 52 57 59 61 61 67
61
PP3V3_S5 9 13 15 18 45 46 48 49 50 59 60 PP1V2_S3 8 12 20 21 22 47 50 61 PP1V8_S0SW_SSD_COLD 18 54 55
PPBUS_G3H 61 67 57 58 59
D
29 34 41 45 46 52 57 59 61
PP3V3_S5 PP1V8_S0SW_SSD_COLD
D
9 13 15 18 45 46 48 49 50 59 60 18 54 55
PPBUS_G3H 29 34 41 45 46 52 57 59 61 61 67 57 58 59
PP3V3_S5 9 13 15 18 45 46 48 49 50 61 50 12 8 PP1V2_S0SW PP1V2_S0SW 8 12 50 61
61
59 60 61 67 MIN_LINE_WIDTH=0.6000 61 59 55 PP1V2_S0SW_SSD_COLD PP1V2_S0SW_SSD_COLD 55 59 61
PP3V3_S5 9 13 15 18 45 46 48 49 50 59 60 MIN_NECK_WIDTH=0.1000 MIN_LINE_WIDTH=0.0950
61 67 VOLTAGE=1.2V MIN_NECK_WIDTH=0.2000
61 41 40 PPVIN_G3H_P3V3G3H PPVIN_G3H_P3V3G3H 40 41 61 PP3V3_S5 9 13 15 18 45 46 48 49 50 59 60 MAKE_BASE=TRUE VOLTAGE=1.2V
MIN_LINE_WIDTH=0.6000 61 67 MAKE_BASE=TRUE
VOLTAGE=8.6V PP1V2_S0SW_SSD_COLD 55 59 61
MAKE_BASE=TRUE
61 PP1V2_S0SW 8 12 50 61
43 42 34 PPBUS_S5_HS_COMPUTING_ISNS PPBUS_S5_HS_COMPUTING_ISNS 34 42 43 44 47 48 61
48 47 44
MIN_LINE_WIDTH=0.6000 61 59 55 PP1V8_S4SW_SSD_HOT PP1V8_S4SW_SSD_HOT 55 59 61
MIN_NECK_WIDTH=0.2000 61 50 49 46 36 17 16 14 13 9 PP3V3_SUS PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 MIN_LINE_WIDTH=0.6000
VOLTAGE=8.6V MIN_LINE_WIDTH=0.6000 VOLTAGE=3.3V 61 60 49 PP1V2_S5SW PP1V2_S5SW 49 60 61 MIN_NECK_WIDTH=0.2000
MAKE_BASE=TRUE MIN_NECK_WIDTH=0.1000 MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6000 VOLTAGE=1.8V
MIN_NECK_WIDTH=0.1000 MAKE_BASE=TRUE
PPBUS_S5_HS_COMPUTING_ISNS 34 42 43 44 47 48 61 PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 VOLTAGE=1.2V
61 48 47 44 43 42 34 PPBUS_S5_HS_COMPUTING_ISNS MAKE_BASE=TRUE PP1V8_S4SW_SSD_HOT 55 59 61
PPBUS_S5_HS_COMPUTING_ISNS 34 42 43 44 47 48 61 PP3V3_SUS 9 13 14 16 17 36 46 49 50 61
PPBUS_S5_HS_COMPUTING_ISNS 34 42 43 44 47 48 61 PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 PP1V2_S5SW 49 60 61
61 48 47 44 43 42 34 PPBUS_S5_HS_COMPUTING_ISNS 61 59 55 PP1V2_S4SW_SSD_HOT PP1V2_S4SW_SSD_HOT 55 59 61
PPBUS_S5_HS_COMPUTING_ISNS 34 42 43 44 47 48 61 PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 MIN_LINE_WIDTH=0.6000
PPBUS_S5_HS_COMPUTING_ISNS 34 42 43 44 47 48 61 PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 VOLTAGE=1.2V
PP3V3_SUS
Chipset Rails MAKE_BASE=TRUE
9 13 14 16 17 36 46 49 50 61
60 24 23 PPVBUS_LIO PPVBUS_LIO 23 24 60 61 PP1V2_S4SW_SSD_HOT 55 59 61
61 MIN_LINE_WIDTH=0.6000 PP3V3_SUS 9 13 14 16 17 36 61 50 48 19 16 13 9 PP1V_SUS PP1V_SUS 9 13 16 19 48 50 61
MIN_NECK_WIDTH=0.1000 46 49 50 61 MIN_LINE_WIDTH=0.6000
61 60 24 23 PPVBUS_LIO VOLTAGE=20V PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 ? mA MIN_NECK_WIDTH=0.2000
MAKE_BASE=TRUE VOLTAGE=1.0V 61 59 55 PP0V9_S0SW_SSD_CORE PP0V9_S0SW_SSD_CORE 55 59 61
PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6000
PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 PP1V_SUS 9 13 16 19 48 50 61 VOLTAGE=0.9V
MAKE_BASE=TRUE
PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 PP1V_SUS 9 13 16 19 48 50 61
PP0V9_S0SW_SSD_CORE 55 59 61
PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 PP1V_SUS 9 13 16 19 48 50 61
41 34 24 PPDCIN_G3H PPDCIN_G3H 24 34 41 61 65 PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 PP1V_SUS 9 13 16 19 48 50 61

65 61 MIN_LINE_WIDTH=0.6000 61 59 55 PP0V9_S0SW_SSD_FIXED PP0V9_S0SW_SSD_FIXED 55 59 61
MIN_NECK_WIDTH=0.2000 PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 PP1V_SUS 9 13 16 19 48 50 61 MIN_LINE_WIDTH=0.6000
VOLTAGE=20V MIN_NECK_WIDTH=0.1500
MAKE_BASE=TRUE PP3V3_SUS 9 13 14 16 17 36 46 49 50 61 PP1V_SUS 9 13 16 19 48 50 61 VOLTAGE=0.9V
MAKE_BASE=TRUE
PPDCIN_G3H 24 34 41 61 65 PP1V_SUS 9 13 16 19 48 50 61
PP0V9_S0SW_SSD_FIXED 55 59 61
PPDCIN_G3H 24 34 41 61 65 PP1V_SUS 9 13 16 19 48 50 61
59 50 46 31 29 26 25 24 18 15 PP3V3_S4 PP3V3_S4 15 18 24 25 26 29 31 46 50 59 PP1V_SUS 9 13 16 19 48 50 61 CPU "VCORE" RAILS

C 41 40 36
29 23 18
33 31 30
PP3V3_G3H PP3V3_G3H
61
18 23 29 30 31 33 36 40 41 61
VOLTAGE=3.3V
MAKE_BASE=TRUE
61
PP1V_SUS 9 13 16 19 48 50 61 C
61
MIN_NECK_WIDTH=0.2000 PP3V3_S4 15 18 24 25 26 29 31 46 50 59 PP1V_SUS 9 13 16 19 48 50 61 61
VOLTAGE=3.42V 61 61 43 34 11 8 PPVCORE_S0_CPU PPVCORE_S0_CPU 8 11
MAKE_BASE=TRUE PP3V3_S4 15 18 24 25 26 29 31 46 50 59 PP1V_SUS 9 13 16 19 48 50 61 MIN_LINE_WIDTH=0.6000 34 43
PP3V3_S4 15 18 24 25 26 29 31 46 50 59 PP1V_SUS 9 13 16 19 48 50 61 VOLTAGE=1.8V
PP3V3_G3H 18 23 29 30 31 33 36 40 41 61 61 MAKE_BASE=TRUE
PP3V3_S4 15 18 24 25 26 29 31 46 50 59 PP1V_SUS 9 13 16 19 48 50 61 61
PP3V3_G3H 18 23 29 30 31 33 36 40 41 61 61 PPVCORE_S0_CPU 8 11
PP3V3_S4 15 18 24 25 26 29 31 46 50 59 PP1V_SUS 9 13 16 19 48 50 61 34 43
PP3V3_G3H 18 23 29 30 31 33 36 40 41 61 61 PPVCORE_S0_CPU 8 11
PP3V3_S4 15 18 24 25 26 29 31 46 50 59 PP1V_SUS 9 13 16 19 48 50 61 34 43
PP3V3_G3H 18 23 29 30 31 33 36 40 41 61 61 61
PP3V3_S4 15 18 24 25 26 29 31 46 50 59 PP1V_SUS 9 13 16 19 48 50 61
PP3V3_G3H 18 23 29 30 31 33 36 40 41 61
PP3V3_S4
61 GT "VCORE" RAILS
15 18 24 25 26 29 31 46 50 59
PP3V3_G3H 18 23 29 30 31 33 36 40 41 61 61
PP3V3_S4 15 18 24 25 26 29 31 46 50 59
PP3V3_G3H 18 23 29 30 31 33 36 40 41 61 61
61
61 50 13 9 PP1V_SUSSW_HSIO PP1V_SUSSW_HSIO 9 13 50 61 61 44 34 12 8 PPVCORE_S0_GT PPVCORE_S0_GT 8 12
PP3V3_G3H 18 23 29 30 31 33 36 40 41 61 MIN_LINE_WIDTH=0.6000 MIN_LINE_WIDTH=0.6000 34 44
? mA MIN_NECK_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000
PP3V3_G3H 18 23 29 30 31 33 36 40 41 61 VOLTAGE=1.0V VOLTAGE=1.8V
67 MAKE_BASE=TRUE MAKE_BASE=TRUE
27 26 23 19 17 16 15 14 6 5 PP3V3_S0 PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31 44 61
61 53 51 50 46 39 35 34 33 31 MIN_LINE_WIDTH=0.6000 VOLTAGE=3.3V 33 34 35 39 46 50 51 53 61 67 PP1V_SUSSW_HSIO 9 13 50 61 PPVCORE_S0_GT 8 12
MIN_NECK_WIDTH=0.1000 MAKE_BASE=TRUE 34
61
PP1V_SUSSW_HSIO 9 13 50 61 PPVCORE_S0_GT 8 12
61 41 23 PP3V3R3V0_AON PP3V3R3V0_AON 23 41 61 65 34 44
65 MIN_LINE_WIDTH=0.6000 PP1V_SUSSW_HSIO 9 13 50 61
MIN_NECK_WIDTH=0.1000 PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31
VOLTAGE=3.3V 33 34 35 39 46 50 51 53 61 67 PP1V_SUSSW_HSIO 9 13 50 61
MAKE_BASE=TRUE PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31
33 34 35 39 46 50 51 53 61 67
PCH "VCORE" RAILS
PP3V3R3V0_AON 23 41 61 65 PP3V3_S0
61 50 42 31 15 12 8 6 PP1V_S3 PP1V_S3 6 8 12 15 31 42 50 61 9 PPVCORE_SUS_PCH PPVCORE_SUS_PCH 9 48
PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31 MIN_LINE_WIDTH=0.6000 61 48 MIN_LINE_WIDTH=0.6000 61
33 34 35 39 46 50 51 53 61 67 ? mA MIN_NECK_WIDTH=0.2000 MIN_NECK_WIDTH=0.1000
PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31 VOLTAGE=1.0V VOLTAGE=1.8V
16 15 9 PPVRTC_G3H PPVRTC_G3H 9 15 16 46 61 33 34 35 39 46 50 51 53 61 67 MAKE_BASE=TRUE MAKE_BASE=TRUE
61 46 MIN_LINE_WIDTH=0.6000 PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31
MIN_NECK_WIDTH=0.2000 33 34 35 39 46 50 51 53 61 67 PP1V_S3 6 8 12 15 31 42 50 61 PPVCORE_SUS_PCH 9 48
VOLTAGE=3V PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31 61
MAKE_BASE=TRUE 33 34 35 39 46 50 51 53 61 67 PP1V_S3
RA000
6 8 12 15 31 42 50 61
PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31
PPVRTC_G3H 9 15 16 46 61 33 34 35 39 46 50 51 53 61 67 PP1V_S3 6 8 12 15 31 42 50 61
PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31
33 34 35 39 46 50 51 53 61 67 PP1V_S3 PP5V_S0 2
0 1 PP5V_S4RS0
6 8 12 15 31 42 50 61 28 43 44 61
PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31 61 52 50 39 29 MIN_LINE_WIDTH=0.5000
5V Rails PP3V3_S0
33 34 35 39 46 50 51 53 61 67 5%
1/20W
B B
VOLTAGE=5V
61 48 47 46 PP5V_G3H PP5V_G3H 46 47 48 61 53 61 67
MF MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5000 PP3V3_S0 5 6 14 15 16 17 19 23 63 61 50 12 8 6 PP1V_S0SW PP1V_S0SW 6 8 12 50 61 63 0201
MIN_NECK_WIDTH=0.2000 26 27 31 33 34 35 39 46 50 51 MIN_LINE_WIDTH=0.6000 PP5V_S4RS0
RA001
43 44 61
VOLTAGE=5V PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31 ? mA MIN_NECK_WIDTH=0.2000
MAKE_BASE=TRUE 33 34 35 39 46 50 51 53 61 67 VOLTAGE=1.0V PP5V_S4RS0 43 44 61
PP5V_G3H
PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31
33 34 35 39 46 50 51 53 61 67
MAKE_BASE=TRUE
PP5V_S4 2
0 1 PP5V_S4RS0
46 47 48 61 61 53 50 46 45 42 38 37 29 24 43 44 61
PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31 PP1V_S0SW 6 8 12 50 61 63 67 63
PP5V_G3H 46 47 48 61 33 34 35 39 46 50 51 53 61 67 5%
PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31 1/20W
PP5V_G3H 46 47 48 61 33 34 35 39 46 50 51 53 61 67 MF
PP3V3_S0 5 6 14 15 16 17 19 23 26 27 31 0201
PP5V_G3H 46 47 48 61 33 34 35 39 46 50 51 53 61 67
61 47 11 8 5 PPVCCIO_S0 PPVCCIO_S0 5 8 11 47 61 NO STUFF
61 57 50 45 PP5V_S5 PP5V_S5 45 50 57 61 ? mA MIN_NECK_WIDTH=0.2500
MIN_LINE_WIDTH=0.5000 VOLTAGE=1.0V
MIN_NECK_WIDTH=0.2000 MAKE_BASE=TRUE
VOLTAGE=5V
MAKE_BASE=TRUE 1.8V Rails PPVCCIO_S0 5 8 11 47 61
PP5V_S5 50 48 33 24 17 13 9 PP1V8_SUS PP1V8_SUS 9 13 17 24 33 48 50 61 PPVCCIO_S0 5 8 11 47 61

PP5V_S5 45 50 57 61 MIN_NECK_WIDTH=0.2000
VOLTAGE=1.8V
PP5V_S5 45 50 57 61 MAKE_BASE=TRUE
PP5V_S5 45 50 57 61 PP1V8_SUS 9 13 17 24 33 48 50 61 61 43 11 8 PPVCCSA_S0 PPVCCSA_S0 8 11 43 61
PP1V8_SUS 9 13 17 24 33 48 50 61 ? mA MIN_NECK_WIDTH=0.2000
61 53 PP5V_S0SW_LCD PP5V_S0SW_LCD 53 61 VOLTAGE=1.0V
MIN_LINE_WIDTH=0.5000 PP1V8_SUS 9 13 17 24 33 48 50 61 MAKE_BASE=TRUE
61 53 PP5V_S0SW_LCD VOLTAGE=5V PP1V8_SUS 9 13 17 24 33 48 50 61 PPVCCSA_S0 8 11 43 61
MAKE_BASE=TRUE
46 45 42 38 37 29 24 PP5V_S4 PP5V_S4 24 29 37 38 42 45 46 50 53 61
67 63 61 53 50 MIN_LINE_WIDTH=0.5000 63 67
PP1V8_S3 PP1V8_S3 PPVCCSA_DDR_S0 PPVCCSA_DDR_S0
VOLTAGE=5V
MAKE_BASE=TRUE
61 50 49 46 22 21
21 22 46 49 50 61 61 43 11 8
? mA
8 11 43 61
Digital Ground
PP5V_S4 24 29 37 38 42 45 46 50 53 61 VOLTAGE=1.8V VOLTAGE=1.0V
63 67 MAKE_BASE=TRUE MAKE_BASE=TRUE GND
PP5V_S4 24 29 37 38 42 45 46 50 53 61 MAKE_BASE=TRUE
63 67 PP1V8_S3 21 22 46 49 50 61 PPVCCSA_DDR_S0 8 11 43 61 MIN_NECK_WIDTH=0.1000
PP5V_S4 24 29 37 38 42 45 46 50 53 61 MIN_LINE_WIDTH=0.2000
63 67 PP1V8_S3 21 22 46 49 50 61 VOLTAGE=0V
PP5V_S4 24 29 37 38 42 45 46 50 53 61
63 67 PP1V8_S3 21 22 46 49 50 61
PP5V_S4 24 29 37 38 42 45 46 50 53 61
A A
63 67
PP5V_S4 24 29 37 38 42 45 46 50 53 61
67
63 67 SYNC_MASTER=X260_ERIC SYNC_DATE=06/09/2015
PP5V_S4 24 61 49 46 39 18 13 PP1V5_S0 PP1V5_S0 13 18 39 46 49 61
29 37 38 42 45 46 50 53 61 63 PAGE TITLE
VOLTAGE=1.5V
MAKE_BASE=TRUE
Power Aliases
DRAWING NUMBER SIZE
PP1V5_S0
PP1V5_S0
13 18 39 46 49 61
13 18 39 46 49 61 Apple Inc.
<SCH_NUM> D
61 52 50 39 29 28 PP5V_S0 PP5V_S0 28 29 39 50 52 61 REVISION
PP1V5_S0
VOLTAGE=5V PP1V5_S0
13 18 39 46 49 61
13 18 39 46 49 61
R
<E4LABEL>
MAKE_BASE=TRUE NOTICE OF PROPRIETARY PROPERTY: BRANCH
PP5V_S0 28 29 39 50 52 61 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
PP5V_S0 28 29 39 50 52 61 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
PP5V_S0 28 29 39 50 52 61
100 OF 130
PP5V_S0 28 29 39 50 52 61 SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Memory Bit/Byte Swizzle
MAKE_BASE MAKE_BASE
62 21 7 BI
MEM_A_DQ<39> TRUE MEM_A_DQ<39> BI 7 21 62 62 22 7 BI
MEM_B_DQ<22> TRUE MEM_B_DQ<22> BI 7 22 62
62 21 7 BI
62 21 7 BI
62 21 7 BI
D
62 21 7
62 21 7
BI
BI
MEM_A_DQ<38>
MEM_A_DQ<34>
TRUE
TRUE
MEM_A_DQ<38>
MEM_A_DQ<34>
BI
BI
7 21 62
7 21 62
62 22 7
62 22 7
BI
BI
MEM_B_DQ<17>
MEM_B_DQ<20>
TRUE
TRUE
MEM_B_DQ<17>
MEM_B_DQ<20>
BI
BI
7 22 62
7 22 62
D
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
C 62 21 7 BI
MEM_B_DQ<63> TRUE MEM_B_DQ<63> BI 7 22 62 C
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
MEM_A_DQ<10> TRUE MEM_A_DQ<10> BI 7 21 62 65 62 22 7 BI
MEM_B_DQ<12> TRUE MEM_B_DQ<12> BI 7 22 62 65
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
B 62 21 7
62 21 7
BI
BI
MEM_A_DQ<30>
MEM_A_DQ<27>
TRUE
TRUE
MEM_A_DQ<30>
MEM_A_DQ<27>
BI
BI
7 21 62
7 21 62
62 22 7
62 22 7
BI
BI
MEM_B_DQ<45>
MEM_B_DQ<46>
TRUE
TRUE
MEM_B_DQ<45>
MEM_B_DQ<46>
BI
BI
7 22 62
7 22 62
B
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
MEM_A_DQS_P<4> TRUE MEM_A_DQS_P<4> BI 7 21 62 62 22 7 BI
MEM_B_DQS_P<2> TRUE MEM_B_DQS_P<2> BI 7 22 62
62 21 7 BI
MEM_A_DQS_N<4> TRUE MEM_A_DQS_N<4> BI 7 21 62 62 22 7 BI
MEM_B_DQS_N<2> TRUE MEM_B_DQS_N<2> BI 7 22 62
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
65 62 21 7 BI
MEM_A_DQS_P<1> TRUE MEM_A_DQS_P<1> BI 7 21 62 65 62 22 7 BI
65 62 21 7 BI
MEM_A_DQS_N<1> TRUE MEM_A_DQS_N<1> BI 7 21 62 65 62 22 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
62 21 7 BI
PAGE TITLE
Memory Signal Swaps

DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
102 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MAKE_BASE
MAKE_BASE
63 6 NC_CPU_CFG0 TRUE NC_CPU_CFG0 6 63
63 6 NC_CPU_CFG1 TRUE NC_CPU_CFG1 6 63 63 6 NC_CPU_CFG11 TRUE NC_CPU_CFG11 6 63

63 46 42 CPU_VR_READY TRUE CPU_VR_READY 42 46 63
63 6 TP_CPU_CFG3 TRUE TP_CPU_CFG3 6 63 63 6 NC_CPU_CFG13 TRUE NC_CPU_CFG13 6 63
63 30 15 SMC_PCH_SUSWARN_L TRUE SMC_PCH_SUSWARN_L 15 30 63
63 30 15 SMC_PCH_SUSACK_L TRUE SMC_PCH_SUSACK_L 15 30 63
63 41 34 31 30 SMC_BC_ACOK TRUE SMC_BC_ACOK 30 31 34 41 63 65
65 63 6 NC_CPU_CFG7 TRUE NC_CPU_CFG7 6 63 63 6 NC_CPU_CFG16 TRUE NC_CPU_CFG16 6 63
65 24 23 16 XDP_USB_EXTA_OC_L TRUE USB_EXTA_OC_L 23 63 6 NC_CPU_CFG8 TRUE NC_CPU_CFG8 6 63 63 6 NC_CPU_CFG17 TRUE NC_CPU_CFG17 6 63
64 63 16 USB_EXTB_OC_L TRUE USB_EXTB_OC_L 16 63 64 63 6 NC_CPU_CFG9 TRUE NC_CPU_CFG9 6 63 63 6 NC_CPU_CFG18 TRUE NC_CPU_CFG18 6 63
63 46 30 15 PM_RSMRST_L TRUE PM_RSMRST_L 15 30 46 63 63 6 NC_CPU_CFG10 TRUE NC_CPU_CFG10 6 63 63 6 NC_CPU_CFG19 TRUE NC_CPU_CFG19 6 63
MAKE_BASE
D
GND TRUE GND
D
63 46 45 P5VS4_PGOOD TRUE P5VS4_PGOOD 45 46 63
67 63
42 38 37 29 24 PP5V_S4 PP5V_S4 24 29 37 38 42 45 46 50 53 61 XDP_BPM_L<3..0> TRUE TP_XDP_BPM_L<3..0> 6
61 53 50 46 45 63 67 61 50 12 8 6 PP1V_S0SW
63 16 TP_XDP_CPU_PRDY_L TRUE TP_XDP_CPU_PRDY_L 16 63
54 =PCIE_SSD_R2D_P<1..0> TRUE PCIE_SSD_R2D_P<1..0> 54
63 16 TP_XDP_CPU_PREQ_L TRUE TP_XDP_CPU_PREQ_L 16 63
54 =PCIE_SSD_R2D_N<1..0> TRUE PCIE_SSD_R2D_N<1..0> 54
63 6 XDP_CPUPCH_TCK TRUE XDP_CPUPCH_TCK 6 63
=PCIE_SSD_R2D_P<3..2> TRUE 1 NC_PCIE_SSD_R2DP<3..2> 54
63 6 XDP_CPUPCH_TDI TRUE XDP_CPUPCH_TDI 6 63
=PCIE_SSD_R2D_N<3..2> NC_PCIE_SSD_R2DN<3..2>
PCIE_SSD_R2D_C_P<3..2>
TRUE
TRUE
1
1 NC_PCIE_SSD_R2D_CP<3..2>
54
16
63 6 XDP_CPUPCH_TDO TRUE 63 6 XDP_CPUPCH_TDO RA300 51 1 2
5% 1/20W MF 201
63 6 XDP_CPUPCH_TMS TRUE XDP_CPUPCH_TMS 6 63
PCIE_SSD_R2D_C_N<3..2> TRUE 1 NC_PCIE_SSD_R2D_CN<3..2> 16
63 6 XDP_CPUPCH_TRST_L TRUE XDP_CPUPCH_TRST_L 6 63
54 =PCIE_SSD_D2R_P<1..0> TRUE PCIE_SSD_D2R_P<1..0> 16 65
63 16 TP_XDP_PCH_OBSDATA_A2 TRUE TP_XDP_PCH_OBSDATA_A2 16 63
54 =PCIE_SSD_D2R_N<1..0> TRUE PCIE_SSD_D2R_N<1..0> 16 65
63 6 TP_XDP_PCH_OBSDATA_A3 TRUE TP_XDP_PCH_OBSDATA_A3 6 63
PCIE_SSD_D2R_C_P<3..2> TRUE 1 NC_PCIE_SSD_D2R_CP<3..2> 54
63 16 TP_XDP_PCH_OBSDATA_B0 TRUE TP_XDP_PCH_OBSDATA_B0 16 63
PCIE_SSD_D2R_C_N<3..2> TRUE 1 NC_PCIE_SSD_D2R_CN<3..2> 54
63 14 TP_XDP_PCH_OBSDATA_C0 TRUE TP_XDP_PCH_OBSDATA_C0 14 63
PCIE_SSD_D2R_P<3..2> TRUE 1 NC_PCIE_SSD_D2RP<3..2> 16
PCIE_SSD_D2R_N<3..2> TRUE 1 NC_PCIE_SSD_D2RN<3..2> 16
65 63 54 16 PCIE_CLK100M_SSD_P TRUE PCIE_CLK100M_SSD_P 16 54 63 65
65 63 54 16 PCIE_CLK100M_SSD_N TRUE PCIE_CLK100M_SSD_N 16 54 63 65
63 14 TP_XDP_PCH_OBSDATA_D0 TRUE TP_XDP_PCH_OBSDATA_D0 14 63
63 59 54 S3X_DEBUG_UART_R2D TRUE S3X_DEBUG_UART_R2D 54 59 63 63 16 TP_XDP_PCH_OBSDATA_D1 TRUE TP_XDP_PCH_OBSDATA_D1 16 63
59 24 23 SSD_DEBUG_UART_D2R TRUE SSD_UART_D2R 17 65 63 16 TP_XDP_PCH_OBSDATA_D2 TRUE TP_XDP_PCH_OBSDATA_D2 16 63
59 24 23 SSD_DEBUG_UART_R2D TRUE SSD_UART_R2D 17 65 63 16 TP_XDP_PCH_OBSDATA_D3 TRUE TP_XDP_PCH_OBSDATA_D3 16 63
63 6 TP_XDP_PCH_OBSFN_C1 TRUE TP_XDP_PCH_OBSFN_C1 6 63

63 51 50 46 19 PM_SLP_S0S3_L TRUE PM_SLP_S0S3_L 19 46 50 51 63
63 6 TP_XDP_PCH_TCK TRUE TP_XDP_PCH_TCK 6 63
50 47 46 30 15 PM_SLP_S4_L TRUE PM_SLP_S4_L 15 30 46 47 50 51 63
63 51 63 6 XDP_CPUPCH_TDI TRUE XDP_CPUPCH_TDI 6 63
63 6 XDP_CPUPCH_TDO TRUE XDP_CPUPCH_TDO 6 63

SYSCLK_CLK24M_PCH SYSCLK_CLK24M_PCH
C 65 63 18 16
63 16 NC_PCH_CLK24M_XTALOUT
TRUE
TRUE NC_PCH_CLK24M_XTALOUT
16 18 63 65
16 63
63 6 XDP_CPUPCH_TMS TRUE XDP_CPUPCH_TMS 6 63 C
63 6 XDP_CPUPCH_TRST_L TRUE XDP_CPUPCH_TRST_L 6 63
NC_PCH_DDPC_CTRLDATA NC_PCH_DDPC_CTRLDATA
63 5 TRUE 5 63
63 6 XDP_CPUPCH_TCK TRUE 63 6 XDP_CPUPCH_TCK RA301 51 1 2
5% 1/20W MF 201
63 6 TP_ITP_PMODE TRUE TP_ITP_PMODE 6 63
63 7 TP_CPU_MEMVTT_PWR_EN TRUE TP_CPU_MEMVTT_PWR_EN 7 63
63 30 TP_SMC_DEV_MLB TRUE TP_SMC_DEV_MLB 30 63
54 24 23 S3X_JTAG_TCK TRUE TP_S3X_JTAG_TCK

54 24 23 S3X_JTAG_TMS TRUE TP_S3X_JTAG_TMS
63 30 TP_SMC_DEBUGPRT_EN_L TRUE TP_SMC_DEBUGPRT_EN_L 30 63
63 14 TP_SPKR_ID0 TRUE TP_SPKR_ID0 14 63
63 14 TP_SPKR_ID1 TRUE TP_SPKR_ID1 14 63
B B
PAGE TITLE
X260 Signal Aliases

DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
103 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NO_TEST Nets
NO_TEST
NC_PCH_BT_I2S_CLK TRUE NC_PCH_BT_I2S_CLK

D
64 14 14 64
D 64 14
64 14
NC_PCH_BT_I2S_D2R
NC_PCH_BT_I2S_R2D
TRUE
TRUE
NC_PCH_BT_I2S_D2R
NC_PCH_BT_I2S_R2D
14 64
14 64
64 14 NC_PCH_BT_I2S_SYNC TRUE NC_PCH_BT_I2S_SYNC 14 64
64 14 NC_HDA_SDIN1 TRUE NC_HDA_SDIN1 14 64
64 15 NC_PCI_PME_L TRUE NC_PCI_PME_L 15 64 CPU/PCH

64 14 NC_CLINK_CLK TRUE NC_CLINK_CLK 14 64
64 14 NC_CLINK_DATA TRUE NC_CLINK_DATA 14 64
64 14 NC_CLINK_RESET_L TRUE NC_CLINK_RESET_L 14 64
64 5 NC_DP_DDI2_AUXCH_CP TRUE NC_DP_DDI2_AUXCH_CP 5 64
64 5 NC_DP_DDI2_AUXCH_CN TRUE NC_DP_DDI2_AUXCH_CN 5 64
64 5 NC_DP_DDI2_ML_CP<0> TRUE NC_DP_DDI2_ML_CP<0> 5 64
64 5 NC_DP_DDI2_ML_CN<0> TRUE NC_DP_DDI2_ML_CN<0> 5 64
64 30 NC_TCON_BKLT_PWM TRUE NC_TCON_BKLT_PWM 30 64
64 30 NC_SMC_GFX_OVERTEMP TRUE NC_SMC_GFX_OVERTEMP 30 64
64 30 NC_SMC_GFX_THROTTLE_L TRUE NC_SMC_GFX_THROTTLE_L 30 64
64 30 NC_SMC_GFX_SELF_THROTTLE TRUE NC_SMC_GFX_SELF_THROTTLE 30 64
64 30 NC_SMC_FAN_0_CTL TRUE NC_SMC_FAN_0_CTL 30 64
64 30 NC_SMC_FAN_0_TACH TRUE NC_SMC_FAN_0_TACH 30 64
NC_SMC_FAN_1_CTL NC_SMC_FAN_1_CTL SMC

64 30 TRUE 30 64
NC_SMC_FAN_1_TACH NC_SMC_FAN_1_TACH
C 64 30
64 30 NC_SYS_ONEWIRE
TRUE
TRUE NC_SYS_ONEWIRE
30 64
30 64
C
64 30 NC_SMC_SOC_POR TRUE NC_SMC_SOC_POR 30 64
64 30 NC_SMC_DP_HPD_L TRUE NC_SMC_DP_HPD_L 30 64
64 30 NC_SPI_SMC_CLK TRUE NC_SPI_SMC_CLK 30 64
64 30 NC_SPI_SMC_CS_L TRUE NC_SPI_SMC_CS_L 30 64
64 30 NC_SPI_SMC_MISO TRUE NC_SPI_SMC_MISO 30 64
64 30 NC_SPI_SMC_MOSI TRUE NC_SPI_SMC_MOSI 30 64
64 30 NC_SMC_ACTUATOR_ACTIVE_L TRUE NC_SMC_ACTUATOR_ACTIVE_L 30 64
64 30 NC_WIFI_DEBUGPRT_R2D_L TRUE NC_WIFI_DEBUGPRT_R2D_L 30 64
64 30 NC_WIFI_DEBUGPRT_D2R_L TRUE NC_WIFI_DEBUGPRT_D2R_L 30 64
B B
Unused nets with offpage

(Nets with offpages not used on this project)
CAM_SENSOR_WAKE_L 27 CPUCORE_ISNS1_P OUT 43
I893
JTAG_ISP_TDO 5 CPUCORE_ISNS1_N OUT 43
I890
TBT_POC_RESET 5 CPUCORE_ISNS2_P OUT 43
I889
LCD_PSR_EN 17 CPUCORE_ISNS2_N OUT 43
I888
TBT_X_PLUG_EVENT_L 17 CPUSA_ISNS_P OUT 43
I887
TBT_T_PLUG_EVENT_L 17 CPUSA_ISNS_N OUT 43
I886
TBT_X_PCI_RESET_L 14 CPUGT_ISNS1_P OUT 44
I885
TBT_T_PCI_RESET_L 14 CPUGT_ISNS1_N OUT 44
I884
TBT_X_CIO_PWR_EN 14 CPUGT_ISNS2_P OUT 44
I883
TBT_T_CIO_PWR_EN 14 CPUGT_ISNS2_N OUT 44
I882
TBT_X_USB_PWR_EN 14 SOC_UART_D2R OUT 17
I881
TBT_T_USB_PWR_EN 14 SOC_UART_R2D OUT 17
I880
BT_PWRRST_L 6 SOC_UART_CTS_L OUT 17
I879
BT_TIMESTAMP 6 SOC_UART_RTS_L OUT 17
A I878
PCH_SWD_IO
PCH_SWD_MUX_SEL
17 CPU_CFG<4>
DP_DDI2_HPD
OUT 6
SYNC_MASTER=J92_DEVMLB SYNC_DATE=07/08/2014 A
I877 17 IN 5
PAGE TITLE
SOC_WAKE_L XDP_USB_EXTC_OC_L
I876
I875
PCH_SWD_CLK
17
17 XDP_USB_EXTD_OC_L
IN
IN
16
16
Func Test / No Test
DRAWING NUMBER SIZE
USB_EXTB_OC_L XDP_JTAG_ISP_TCK
17
I874
AUD_SPI_CS_L
16 63
XDP_JTAG_ISP_TDI
OUT 16
16 Apple Inc.
<SCH_NUM> D
OUT OUT
REVISION
AUD_SPI_CLK
17
17
OUT
AUD_SPI_MISO
R
<E4LABEL>
IN
AUD_SPI_MOSI
17 OUT
<BRANCH>
104 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
EE Chaz Probe Points SSD & WiFi Chamber Test Points
P2MM P2MM
PPA504 PP
1 SMC_CBC_ON 30 41
PPA577 PP
1 USB3_EXTA_D2R_N 16 60 TPA500
1 PPDCIN_G3H
SM SM A 24 34 41 61 65
P2MM P2MM SM-TPP635-TOP

1 SMC_CHGR_INT_L 1 USB3_EXTA_D2R_P
PPA505 PP
SM
30 41
PPA578 PP
SM
16 60
TPA501
1 PPDCIN_G3H
P2MM P2MM A 24 34 41 61 65
1 MEM_A_CAA<0> 1 CPU_CATERR_L SM-TPP635-TOP
PPA506 PP
SM
7 21
PPA579 PP
SM
6 30
TPA502
P2MM P2MM 1 PPDCIN_G3H
1 MEM_A_CLK_P<0> 1 MEM_B_CS_L<1> A 24 34 41 61 65
PPA507 PP 7 21
PPA581 PP 7 22
SM-TPP635-TOP
TPA503
SM SM
P2MM P2MM
1 MEM_A_CLK_N<0> 1 MEM_B_CKE<1> 1 PPDCIN_G3H
PPA508 PP 7 21
PPA582 PP 7 22 A 24 34 41 61 65
D
D SM
P2MM
1 MEM_A_CS_L<0>
SM
P2MM
1 MEM_B_CAB<1>
SM-TPP635-TOP
TPA504
PPA509 PP
SM
7 21
PPA583 PP
SM
7 22
A
1 GND
1 MEM_B_DQ<12> 1 MEM_B_CAA<2>
PPA510 PP
SM
7 22 62
PPA584 PP
SM
7 22
TPA505
1 GND
P2MM P2MM A
1 MEM_A_DQS_P<1> 1 MEM_B_CAA<3> SM-TPP635-TOP
PPA511 PP
SM
7 21 62
PPA587 PP
SM
7 22
TPA506
P2MM P2MM 1 SMC_ONOFF_L
1 MEM_A_DQS_N<1> 1 XDP_USB_EXTA_OC_L A 29 30 31 32
PPA512 PP 7 21 62
PPA594 PP 16 23 24 63
SM-TPP635-TOP
TPA507
SM SM
P2MM P2MM
1 AP_DEV_WAKE 1 USB_EXTA_P 1 SSD_BOOT_L
PPA513 PP
SM
14 25
PPA596 PP
SM
16 23 A
SM-TPP635-TOP
17 54
P2MM P2MM
PPA514 PP
1 AP_S0IX_WAKE_L 17 18
PPA597 PP
1 USB_EXTA_N 16 23 TPA508
1 SMC_DEV_SUPPLY_L
SM SM A 30

1 AP_S0IX_WAKE_SEL 1 PM_DSW_PWRGD
PPA515 PP
SM
17 18
PPA598 PP
SM
15 30
TPA509
1 GND
P2MM P2MM A
1 MIPI_CLK_P 1 AP_CLKREQ_L SM-TPP635-TOP
PPA517 PP
SM
27 28
PPA500 PP
SM
16 25
TPA510
P2MM P2MM 1 SMC_DEBUGPRT_TX_L
1 MIPI_DATA_P 1 AP_RESET_L A 30 31 65
PPA518 PP 27 28
PPA501 PP 14 25
SM-TPP635-TOP
TPA511
SM SM
P2MM P2MM
1 PCH_BT_UART_D2R 1 CAMERA_CLKREQ_L 1 SMC_DEBUGPRT_RX_L SYSCLK_CLK24M_CAMERA SYSCLK_CLK24M_CAMERA
PPA519 PP
SM
17 26
PPA502 PP
SM
16 27 A
SM-TPP635-TOP
30 31 65 65 27 18
MAKE_BASE=TRUE
18 27 65
P2MM P2MM
PPA520 PP
1 PCH_BT_UART_RTS_L 17 26
PPA503 PP
1 CAMERA_RESET_L 14 27 TPA512
1 SSD_UART_R2D SMC_UART_TX TRUE SMC_DEBUGPRT_TX_L
SM SM A 17 63 24 23 30 31 65
P2MM
1
P2MM
1
SM-TPP635-TOP 24 23 SMC_UART_RX TRUE SMC_DEBUGPRT_RX_L 30 31 65
PCIE_CAMERA_D2R_P CHGR_BOOST_DH
PPA522 PP
SM
16 28
PPA521 PP
SM
41
TPA513
1 SSD_UART_D2R
P2MM P2MM A 17 63
1 PCIE_CLK100M_SSD_P 1 CHGR_BOOST_DL SM-TPP635-TOP
PPA523 PP 16 54 63
PPA586 PP 41
TPA514
C
SM
P2MM
1 AUD_PWR_EN
SM
P2MM
1 CHGR_BUCK_DH A
1 PCIE_TEST_D2R_P PCIE_TEST_D2R_P 16 65 NO_TEST Nets C
PPA529 PP 17 39
PPA524 PP 41
SM-TPP635-TOP
MAKE_BASE=TRUE
TPA515
SM SM
P2MM P2MM NO_TEST
1 BT_UART_RTS_L 1 CHGR_BUCK_DL 1 PCIE_TEST_D2R_N PCIE_TEST_D2R_N
PPA530 PP
SM
25 26
PPA525 PP
SM
41 A
SM-TPP635-TOP
MAKE_BASE=TRUE
16 65
65 16 NC_USB3_EXTB_D2RP
MAKE_BASE
TRUE NC_USB3_EXTB_D2RP 16 65
P2MM P2MM
PPA531 PP
1 CAMERA_PWR_EN 14 27
PPA526 PP
1 CPUCORE_FCCM 42 43 TPA516
1 PCIE_TEST_R2D_P PCIE_TEST_R2D_P 65 16 NC_USB3_EXTB_D2RN TRUE NC_USB3_EXTB_D2RN 16 65
SM SM A MAKE_BASE=TRUE
16 65
65 16 NC_USB3_EXTB_R2D_CP TRUE NC_USB3_EXTB_R2D_CP 16 65 CPU/PCH
1 EDP_BKLT_PWM 1 CPUGT_FCCM NC_USB3_EXTB_R2D_CN NC_USB3_EXTB_R2D_CN
PPA533 PP
SM
5 53
PPA527 PP
SM
42 44
TPA517
1 PCIE_TEST_R2D_N PCIE_TEST_R2D_N
65 16
NC_USB_EXTBP
TRUE
TRUE NC_USB_EXTBP
16 65
P2MM P2MM A MAKE_BASE=TRUE

16 65 65 16 16 65
1 HDA_SDIN0 1 CPUSA_FCCM SM-TPP635-TOP NC_USB_EXTBN NC_USB_EXTBN
PPA534 PP
SM
14 39
PPA528 PP
SM
42 43
TPA518
65 16
65 16 NC_USB3_EXTC_D2RP
TRUE
TRUE NC_USB3_EXTC_D2RP
16 65
16 65
P2MM P2MM 1 PCIE_CLK100M_TEST_P PCIE_CLK100M_TEST_P
1 LCD_IRQ_L 1 CPUCORE_PWM1 A 16 65
NC_USB3_EXTC_D2RN NC_USB3_EXTC_D2RN
PPA537 PP 17 53
PPA532 PP 42 43
SM-TPP635-TOP
MAKE_BASE=TRUE 65 16
NC_USB3_EXTC_R2D_CP
TRUE
NC_USB3_EXTC_R2D_CP
16 65
TPA519 TRUE
SM SM 65 16 16 65
P2MM P2MM
1 MEM_CAM_A<8> 1 CPUCORE_PWM2 1 PCIE_CLK100M_TEST_N PCIE_CLK100M_TEST_N NC_USB3_EXTC_R2D_CN NC_USB3_EXTC_R2D_CN
PPA538 PP
SM
27 28
PPA535 PP
SM
42 43 A
SM-TPP635-TOP
MAKE_BASE=TRUE
16 65 65 16
65 16 NC_USB_EXTCP
TRUE
TRUE NC_USB_EXTCP
16 65
16 65
P2MM P2MM
PPA539 PP
1 MEM_CAM_CS_L 27 28
PPA536 PP
1 CPUGT_PWM1 42 44 TPA520
1 TEST_CLKREQ_L TEST_CLKREQ_L 65 16 NC_USB_EXTCN TRUE NC_USB_EXTCN 16 65
SM SM A MAKE_BASE=TRUE
16 65
65 16 NC_USB3_EXTD_D2RP TRUE NC_USB3_EXTD_D2RP 16 65
1 MIPI_CLK_N 1 CPUGT_PWM2 NC_USB3_EXTD_D2RN NC_USB3_EXTD_D2RN
PPA543 PP
SM
27 28
PPA540 PP
SM
42 44
TPA521
1 PLT_RST_L
65 16
NC_USB3_EXTD_R2D_CP
TRUE
TRUE NC_USB3_EXTD_R2D_CP
16 65
P2MM P2MM A 5 14 15 19 26 30 65 16 16 65
1 MIPI_DATA_N 1 CPUSA_PWM SM-TPP635-TOP NC_USB3_EXTD_R2D_CN NC_USB3_EXTD_R2D_CN
PPA544 PP
SM
27 28
PPA541 PP
SM
42 43
TPA522
65 16
65 16 NC_USB_EXTDP
TRUE
TRUE NC_USB_EXTDP
16 65
16 65
P2MM P2MM 1 USB_TEST_P USB_TEST_P
1 PCH_BT_UART_CTS_L 1 P1V2_DRVH A 16 65
NC_USB_EXTDN NC_USB_EXTDN
PPA545 PP 17 26
PPA542 PP 47
SM-TPP635-TOP
MAKE_BASE=TRUE 65 16 TRUE 16 65
TPA523
SM SM
P2MM P2MM
1 PCH_BT_UART_R2D 1 P1V2_DRVL 1 USB_TEST_N USB_TEST_N
PPA546 PP
SM
17 26
PPA547 PP
SM
47 A
SM-TPP635-TOP
MAKE_BASE=TRUE
16 65
P2MM P2MM
PPA548 PP
1 PCIE_CAMERA_D2R_N 16 28
PPA589 PP
1 PVCCIO_DRVH 47 TPA524
1 GND
SM SM A
B PPA549
P2MM
PP
1 PCIE_CLK100M_SSD_N 16 54 63
PPA588
P2MM
PP
1 PVCCIO_DRVL 47
SM-TPP635-TOP
TPA525
B
SM SM 1 GND
P2MM P2MM A
1 PCIE_SSD_D2R_N<0> 1 P1VSUS_DRVH SM-TPP635-TOP
PPA551 PP
SM
16 63
PPA550 PP
SM
48
TPA526
P2MM P2MM 1 POWER_GATE_EN
1 PCIE_SSD_D2R_P<0> 1 P1VSUS_DRVL A 23 24 41
PPA552 PP 16 63
PPA590 PP 48
SM-TPP635-TOP
TPA527
SM SM
P2MM P2MM
1 SMC_BT_PWR_EN 1 LPC_SERIRQ 1 PP3V3R3V0_AON
PPA560 PP
SM
25 30
PPA553 PP
SM
14 30 A
SM-TPP635-TOP
23 41 61
P2MM P2MM
PPA562 PP
1 SMC_OOB1_R2D_L 30 59
PPA554 PP
1 SMC_CLK32K 30 31 TPA528
1 HIPWR_EN
SM SM A 23 41

1 SMC_PROCHOT 1 SYSCLK_CLK32K_PCH
PPA563 PP
SM
30 31
PPA555 PP
SM
16 18
TPA529
1 PM_SLP_S3_L
P2MM P2MM A 15 30 46 49 50 51
1 SMC_SENSOR_PWR_EN 1 SYSCLK_CLK32K_CAMERA_BT_AP SM-TPP635-TOP
PPA564 PP
SM
30 32 34
PPA556 PP
SM
18 25
P2MM P2MM
1 SMC_WAKE_SCI_L 1 SYSCLK_CLK24M_PCH
PPA565 PP
SM
15 30
PPA557 PP
SM
16 18 63
P2MM P2MM
1 SMC_WIFI_PWR_EN 1 TPAD_SPI_IF_EN
PPA566 PP
SM
25 30
PPA558 PP
SM
17 29
P2MM P2MM
1 AP_PCIE_WAKE_L 1 CPUCORE_GL1
PPA567 PP
SM
18 25
PPA559 PP
SM
43
P2MM P2MM
1 SSD_SR_EN_L 1 CPUCORE_GL2
PPA569 PP
SM
15 59
PPA561 PP
SM
43
P2MM P2MM
1 SYSCLK_CLK12M_SMC 1 CPUGT_GL1
PPA570 PP
SM
18 30
PPA568 PP
SM
44
P2MM P2MM
1 SYSCLK_CLK24M_SSD 1 CPUGT_GL2
PPA571 PP 18 54
PPA573 PP 44
A
SM SM
PPA572
P2MM
PP
1 SYSCLK_CLK24M_CAMERA 18 27 65
PPA574
P2MM
PP
1 SMC_BC_ACOK 30 31 34 41 63 SYNC_MASTER=J41_MLB SYNC_DATE=10/24/2012 A
SM SM PAGE TITLE
PPA575
P2MM
PP
1 TPAD_SPI_CS_L 17 29
PPA580
P2MM
PP
1 P2V7NAND_DRVL 57 Project FCT/NC/Aliases
SM SM DRAWING NUMBER SIZE
P2MM P2MM
PPA576 PP
1 TPAD_SPI_INT_L 17 29
PPA585 PP
1 P1V8SUS_PGOOD 46 48
Apple Inc.
<SCH_NUM> D
SM SM REVISION
R
<E4LABEL>

<BRANCH>
105 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Reserved for Constraints!

Change List:
D <radar://component/633819> X260 HW EE Schematic | Proto 0 D
<radar://component/634034> X260 HW EE Schematic | Proto 1
<radar://component/634038> X260 HW EE Schematic | Proto 2
<radar://component/634042> X260 HW EE Schematic | EVT
<radar://component/634046> X260 HW EE Schematic | DVT
Kismet:
<afp://kismet.apple.com/Kismet-Projects/>
Useful Wiki Links:

Schematic Conventions - <https://hmts.ecs.apple.com/wiki/index.php/User:Wferry/SchConventions>
Schematic Design Wiki - <https://hmts.ecs.apple.com/wiki/index.php/Schematic_Design>
C C
Other Info:
Page Allocations - <radar:19817053> 2015 Mobile Mac Schematic Page Allocations
B B
A SYNC_MASTER=X260_KUMAR SYNC_DATE=06/23/2015
A
PAGE TITLE
Reference
DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
120 OF 130
SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power State Debug LEDs

PP3V3_S5 PP5V_S4 61 53 PP3V3_S0 PM_SLP_S0_L
59 50 49 48 46 45 18 15 13 9 46 45 42 38 37 29 24 23 19 17 16 15 14 6 5 46 30 15
61 60 63 61 53 50 51 50 46 39 35 34 33 31 27 26
RD098 1 RD096 1 RD095 1 RD094 1

20K 75K 20K 20K
5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W
MF MF MF MF
201 2 201 2 201 2 201 2
DBGLED_S5 DBGLED_S4 DBGLED_S0 DBGLED_S0I

D DEBUGLED DEBUGLED DEBUGLED DEBUGLED D
A A A A
DD097 DD096 DD095 DD094
GREEN-56MCD-2MA-2.65V GREEN-56MCD-2MA-2.65V GREEN-56MCD-2MA-2.65V GREEN-56MCD-2MA-2.65V
LTQH9G-SM LTQH9G-SM LTQH9G-SM LTQH9G-SM
K PLACE_SIDE=TOP K PLACE_SIDE=TOP K PLACE_SIDE=TOP K PLACE_SIDE=TOP
C C
B B
A SYNC_MASTER=MASTER SYNC_DATE=MASTER A
PAGE TITLE
Debug Support
DRAWING NUMBER SIZE
Apple Inc.
<SCH_NUM> D
REVISION
R
<E4LABEL>

<BRANCH>
130 OF 130
SHEET
8 7 6 5 4 3 2 1

820-00244-A CBB MLB 051-00532 Resolved

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820-00244-A CBB MLB 051-00532 Resolved

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8 7 6 5 4 3 2 1

X260 MLB - CBB

A ALIASES RESOLVED PRODUCT SAFETY REQUIREMENTS:

820-00244 1 PCBF,MLB,X260 PCB CRITICAL

BOM GROUP BOM OPTIONS PART NUMBER PART NUMBER

D 376S1053 376S0604 ALL Diodes alt to Fairchild

128S00031 128S00010 ALL Rohm alt to Sanyo

VENDOR CFG 1 CFG 0 TABLE_ALT_ITEM TABLE_ALT_ITEM

CPU DRAM SPD Straps HYNIX 0 0

152S00028 152S1751 ALL Murata alt to Taiyo Yuden

SAMSUNG 1 0 TABLE_ALT_ITEM TABLE_ALT_ITEM

MICRON 0 1 TABLE_ALT_ITEM TABLE_ALT_ITEM

ELPIDA 1 1 TABLE_ALT_ITEM TABLE_ALT_ITEM

SIZE CFG 3 CFG 2 TABLE_ALT_ITEM TABLE_ALT_ITEM

2GB 0 0 TABLE_ALT_ITEM TABLE_ALT_ITEM

4GB QDP 0 1 TABLE_ALT_ITEM TABLE_ALT_ITEM

4GB DDP 1 0 TABLE_ALT_ITEM TABLE_ALT_ITEM

8GB 1 1 TABLE_ALT_ITEM TABLE_ALT_ITEM

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION

SSD:128GB NAND:64GB,CAPACITY1 311S00004 311S0370 ALL OnSemi alt to NXP

C 341S00466 1 IC,NVM (VXXX) CBB, X260 U3090 CRITICAL UPCROM:PROG

333S00030 333S00016 ALL Hynix alt to Micron

SSD:512GB NAND:256GB,CAPACITY2 338S00175 338S1264 ALL Broadcom alt packaging

SSD:256GB_SAND NAND:128GB_SAND,CAPACITY0,CAPACITY1,SANDISK_1Y 107S00020 107S0276 ALL TFT alt to Cyntec

SSD:512GB_SAND NAND:256GB_SAND,CAPACITY2,SANDISK_1Y 107S00021 107S0284 ALL TFT alt to Cyntec

353S00773 353S4296 ALL Semtech alt to TI

311S00057 311S0612 ALL Diodes alt to NXP

155S00011 155S00008 ALL Murata alt to TDK

SSD Parts 138S0739 138S0706 ALL Samsung alt to Murata

138S0945 138S0706 ALL Kyocera alt to Murata

337S00175 1 IC,S3-X,B0 U8600 CRITICAL S3X:B0 TABLE_ALT_ITEM

138S00090 138S0943 ALL Taiyo alt to Murata

333S00017 1 IC,LPDDR3-1600,128MX8,1.8V,25NM,276 POP U8600_POP_DRAM CRITICAL SSDRAM:4GBIT TABLE_ALT_ITEM

138S00087 138S1086 ALL Taiyo alt to Murata

Module Parts 335S1030 2 NAND,TOG DDR2,2CH,64GB,1YNM,3.3V,LGA60 U9100,U9120 CRITICAL NAND:64GB

152S00347 152S00220 ALL Chilisin alt to Cyntec

138S00032 138S0831 ALL Taiyo alt to Murata

138S00049 138S0831 ALL Kyocera alt to Murata

152S00362 152S1129 ALL Cyntec alt to Murata

128S00039 128S00038 ALL NEC alt to Kemet

825-00162 1 LABEL,BARCODE,2D,1D,CONFIG,MLB,X260 LABEL

Board IDs TABLE_BOMGROUP_HEAD

BOM GROUP BOM OPTIONS

333S00053 2 IC,SDRAM,LPDDR-1866,32GBIT,253B FBGA U2300,U2500 CRITICAL DRAM_TYPE:HYNIX_8GB

A 333S00054 2 IC,SDRAM,LPDDR-1866,32GBIT,253B FBGA U2300,U2500 CRITICAL DRAM_TYPE:ELPIDA_8GB

BOM Configuration [2]

THE INFORMATION CONTAINED HEREIN IS THE

Top level BOM Variants TABLE_BOMGROUP_HEAD

BOM NUMBER BOM NAME BOM OPTIONS

639-6664 PCBA,MLB,1.3GHZ,EL 8GB,TOSH 256G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,SSD:256GB,WIFI:FCC

639-6665 PCBA,MLB,1.3GHZ,EL 8GB,TOSH 512G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,SSD:512GB,WIFI:FCC

639-6666 PCBA,MLB,1.3GHZ,HY 8GB,TOSH 256G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:HYN_8GB,SSD:256GB,WIFI:FCC

639-6667 PCBA,MLB,1.3GHZ,HY 8GB,TOSH 512G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:HYN_8GB,SSD:512GB,WIFI:FCC

639-6668 PCBA,MLB,1.3GHZ,SA 8GB,TOSH 256G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:SAM_8GB,SSD:256GB,WIFI:FCC

639-6669 PCBA,MLB,1.3GHZ,SA 8GB,TOSH 512G,WIFI FCC,X260

639-6670 PCBA,MLB,1.1GHZ,HY 8GB,TOSH 128G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.1GHZ,DRAM:HYN_8GB,SSD:128GB,WIFI:FCC

639-6671 PCBA,MLB,1.2GHZ,EL 8GB,TOSH 256G,WIFI ETSI,X260 ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,SSD:256GB,WIFI:ETSI

639-6672 PCBA,MLB,1.2GHZ,SA 8GB,TOSH 512G,WIFI APAC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:SAM_8GB,SSD:512GB,WIFI:APAC

639-6673 PCBA,MLB,1.2GHZ,EL 8GB,SAND 256G,WIFI ETSI,X260 ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,SSD:256GB_SAND,WIFI:ETSI

639-6674 PCBA,MLB,1.3GHZ,EL 8GB,SAND 256G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:ELP_8GB,SSD:256GB_SAND,WIFI:FCC

639-6675 PCBA,MLB,1.3GHZ,SA 8GB,SAND 512G,WIFI APAC,X260 ALTERNATE,CMN,CPU:1.3GHZ,DRAM:SAM_8GB,SSD:512GB_SAND,WIFI:APAC

639-6676 PCBA,MLB,1.2GHZ,EL 8GB,SAND 256G,WIFI FCC,X260 ALTERNATE,CMN,CPU:1.2GHZ,DRAM:ELP_8GB,SSD:256GB_SAND,WIFI:FCC