Apple Macbook Pro A1425 - 051 9216

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
<REV> <ECN> <ECO_DESCRIPTION> <ECODATE>
SCHEM,MLB,D1
8/8/12
(.csa) Date (.csa) Date
D Page
TABLE_TABLEOFCONTENTS_HEAD
Contents Sync Page
TABLE_TABLEOFCONTENTS_HEAD
Contents Sync D
1 MASTER 56 07/29/2011
TABLE_TABLEOFCONTENTS_ITEM
1 Table of Contents MASTER
46 Fan Connectors J5_MLB
2 02/15/2011 57 12/08/2011
2 System Block Diagram MASTER
47 KEYBOARD/TRACKPAD (1 OF 2) D2_MLB_KEPLER
3 06/30/2009 58 12/08/2011
3 Power Block Diagram K17_REF
48 KEYBOARD/TRACKPAD (2 OF 2) D2_MLB_KEPLER
4 MASTER 59 07/29/2011
4 Revision History MASTER
49 DIGITAL ACCELEROMETER & GYRO J5_MLB
5 MASTER 61 01/20/2012
5 BOM Configuration MASTER
50 SPI ROM J13_MLB
6 MASTER 62 06/06/2012
6 BOM Configuration MASTER
51 AUDIO: CODEC/REGULATOR D1_AUDIO
7 MASTER 63 06/06/2012
7 Functional / ICT Test MASTER
52 AUDIO: HEADPHONE FILTER D1_AUDIO
8 MASTER 66 06/06/2012
8 Power Aliases MASTER
53 AUDIO: SPEAKER AMP D1_AUDIO
9 01/27/2012 67 06/06/2012
9 Signal Aliases D1_MLB_TEST
54 AUDIO: JACK D1_AUDIO
10 07/14/2011 68 06/06/2012
10 CPU DMI/PEG/FDI/RSVD J30_MLB
55 AUDIO: JACK TRANSLATORS D1_AUDIO
11 07/14/2011 69 MASTER
11 CPU CLOCK/MISC/JTAG J30_MLB
56 DC-In & Battery Connectors MASTER
12 07/14/2011 70 MASTER
12 CPU DDR3 INTERFACES J30_MLB
57 PBus Supply & Battery Charger MASTER
13 07/14/2011 71 MASTER
13 CPU POWER J30_MLB
58 System Agent Supply MASTER
14 07/14/2011 72 MASTER
14 CPU GROUNDS J30_MLB
59 5V / 3.3V Power Supply MASTER
16 MASTER 73 MASTER
15 CPU DECOUPLING-I MASTER
60 1.5V DDR3 Supply MASTER
17 MASTER 74 MASTER
16 CPU DECOUPLING-II MASTER
61 CPU IMVP7 & AXG VCore Regulator MASTER
18 09/15/2011 75 MASTER
17 PCH SATA/PCIe/CLK/LPC/SPI 62 CPU IMVP7 & AXG VCore Output
C TABLE_TABLEOFCONTENTS_ITEM
18
19
PCH DMI/FDI/PM/Graphics
J13_MLB
J13_MLB
09/15/2011
63
76
CPUVCCIO (1.05V) Power Supply
MASTER
MASTER
MASTER C
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
20 09/15/2011 77 MASTER
19 PCH PCI/USB/TP/RSVD J13_MLB
64 Misc Power Supplies MASTER
21 09/15/2011 78 MASTER
20 PCH GPIO/MISC/NCTF J13_MLB
65 Power FETs MASTER
22 09/15/2011 79 MASTER
21 PCH POWER J13_MLB
66 Power Control 1/ENABLE MASTER
23 09/15/2011 90 07/11/2012
22 PCH GROUNDS J13_MLB
67 eDP Display Connector D1_SENSORS
24 09/15/2011 92 MASTER
23 PCH DECOUPLING J13_MLB
68 DDC Crossbar MASTER
25 07/14/2011 94 11/14/2011
24 CPU & PCH XDP J30_MLB
69 Thunderbolt Connector A J5_MLB_KEPLER
26 MASTER 96 11/14/2011
25 Chipset Support MASTER
70 Thunderbolt Connector B J5_MLB_KEPLER
27 08/17/2011 97 09/21/2011
26 USB HUB & MUX J5_AMD
71 LCD Backlight Driver (LP8545) J5_MLB_KEPLER
28 07/29/2011 100 09/13/2011
27 CPU Memory S3 Support J5_MLB
72 CPU Constraints J5_MLB
29 07/14/2011 101 09/13/2011
28 DDR3 SDRAM Bank A (Rank 0) J5_MLB
73 Memory Constraints J5_MLB
31 07/14/2011 102 09/21/2011
29 DDR3 SDRAM Bank B (Rank 0) J5_MLB
74 PCH Constraints 1 J5_MLB_KEPLER
33 MASTER 103 07/29/2011
30 DDR3 Termination MASTER
75 PCH Constraints 2 J5_MLB
34 07/29/2011 105 08/31/2011
31 DDR3/FRAMEBUF VREF MARGINING J5_MLB
76 Thunderbolt Constraints T29_CR
35 MASTER 106 07/29/2011
32 ALS/CAMERA CONNECTOR MASTER
77 SMC Constraints J5_MLB
36 11/14/2011 108 07/29/2011
33 Thunderbolt Host (1 of 2) J5_MLB_KEPLER
78 Project Specific Constraints J5_MLB
37 11/14/2011 109 07/29/2011
34 Thunderbolt Host (2 of 2) J5_MLB_KEPLER
79 PCB Rule Definitions J5_MLB
38 11/14/2011 132 07/11/2012
B TABLE_TABLEOFCONTENTS_ITEM
35
44
Thunderbolt Power Support J5_MLB_KEPLER
MASTER
80 Power Sensors: Extended D1_SENSORS B
36 RIO CONNECTORS MASTER
45 MASTER
37 SSD/HDD Connectors MASTER
46 08/24/2011
38 USB 3.0 CONNECTORS J5_AMD
49 02/20/2012
39 SMC D1_SENSORS
50 02/20/2012
40 SMC Support D1_SENSORS
51 02/20/2012
41 LPC+SPI Debug Connector D1_SENSORS
52 MASTER
42 SMBus Connections MASTER
53 02/20/2012
43 Power Sensor: Load Side D1_SENSORS
54 02/20/2012
44 Power Sensor: High Side D1_SENSORS
55 02/20/2012
45 Thermal Sensors D1_SENSORS
A A
DRAWING TITLE
SCHEM,MLB,D1
DRAWING NUMBER SIZE
Schematic / PCB #’s Apple Inc. <SCH_NUM> D
REVISION
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION R
<E4LABEL>
051-9216 1 SCHEM,MLB,D1 SCH CRITICAL NOTICE OF PROPRIETARY PROPERTY: BRANCH
820-3462 1 PCBF,MLB(NEW),D1 PCB CRITICAL

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
<BRANCH>
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
DRAWING I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 132
TITLE=MLB III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
ABBREV=ABBREV
LAST_MODIFIED=Thu Aug 9 12:34:09 2012 IV ALL RIGHTS RESERVED 1 OF 80
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J2500
XDP CONN
PG 23
U1000
INTEL CPU DDR3-1333/1600MHZ

U3100-U3170
2.X GHz
IVY BRIDGE 2C-35W Mem
PG 9-15
U2900-U2970 PG 28
J6900, J6950
D D
Mem
DC/BATT POWER SUPPLY
PG 27 PG 55 PG 56-65
U5550,U5570
GPIO FDI DMI RTC
TEMP SENSOR
PG 19 PG 17 PG 17 PG 16 PG 47
U5920,U5940
U2600
Motion Sensor/GYRO
MISC PG 48
SYSTEM CLK PG 19 U5340,U5350,U5360,U5370,U5400,U5410,Q5480

CLOCK BUFFER U6100
Q5490
POWER SENSE
PG 24 PG 42, 43
PG 16 SPI
SPI Boot ROM J5650,J5660
FAN CONN AND CONTROL

PG 49
PG 16 PG 45
U4510
SATA
1.05V/6GHZ. 0
REDRIVER INTEL U4900 I2C SMS ADC Fan Ser
PG 36 SATA Prt J5100
PANTHER POINT-MPCH SMC SPI LPC+SPI Conn

PG 16 LPC Port80,serial
PG 38
C J4500
PG 16
PG 40
C
SATA U1800
U9420 CONN
HDD J4410 U5701 J5700, J5713
MUX PG 36
RIO CONN
J9400 PG 68 U3600
PWR Bluetooth TP/KB TRACKPAD/
PortA CIO
PCIe x4 PG 16-21 PSOC KEYBOARD
DP/TBT LVDS OUT CTRL PG 35 PG 46 PG 46
PORT TBT Host PG 17 J3502
RGB OUT
CONN
PortB CIO DP DP OUT CAMERA
0 1 2 3 4 5 6 7 8 9 10 11 12 13
PG 68,69 U9620 PG 32,33
U4900
DVI OUT
(UP TO 14 DEVICES)
MUX PG 31
PG 69 TMDS OUT
SMC
J9000 PG 38
PG 17 U2700 1 2 3
USB
PG 18
USB
eDP eDP OUT HUB
CONN PG 17 PG 25
U2760 J4410
PG 66 EHCI USB RIO CONN

XHCI MUX
PCI PG 25 USB 3
PG 18 PG 35
J4410
1 2 3 4
USB 3
PG 18
RIO CONN HDMI J4600
HDMI PG 17
EXTERNAL A B
B PG 35 SMBUS USB 3
JTAG PG 16 PG37
PG 16
PCI-E
PEG (UP TO 8 LINES) HDA J2550
PG 16 PG 16 PG 16
2 1 From PCH PCH XDP
CONN
PG 23
U6201
AUDIO
Codec
PG 50
EXTMIC LINEIN HPOUT SPDIF MICIN LINEOUT
J4410
RIO CONN
Airport/SD Card U6750 U6610,U6620
U6630,U6640
MIC BIAS
PG 35
PG53 SPEAKER
A AMPs SYNC_MASTER=MASTER SYNC_DATE=02/15/2011 A
PG 52 PAGE TITLE
System Block Diagram

DRAWING NUMBER SIZE
Apple Inc. <SCH_NUM> D

REVISION
R
J6701 J5815
J6802
J6803
<E4LABEL>
PG 53 PG 47 PG 54 NOTICE OF PROPRIETARY PROPERTY: BRANCH
<BRANCH>
AUDIO THE POSESSOR AGREES TO THE FOLLOWING: PAGE
CONNs I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
2 OF 132
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 2 OF 80
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D6905
D1 POWER SYSTEM ARCHITECTURE
ENABLE
PPDCIN_G3H
PPDCIN_S5_P3V42G3H
3.425V G3HOT SMC PWRGD
R6920 LT3470A PP3V42_G3H
SN0903048 SMC_RESET_L
U6990
(PAGE 55)
U5010
P5V1_VIN ENABLE
(PAGE 39)
SMC_PBUS_VSENSE
LT3470A
U7090
J6900 (PAGE 56) F7040 V R7640
D F6905
PPBUS_G3H PP5V_S0
VCC 1.05V VOUT
A PP1V05_S0 D
ISL95874
R7020 PP5V1_CHGR_VDDP SMC_CPU_FSB_ISENSE
6A FUSE CPUVCCIOS0_EN
EN
U7600
AC DCIN(16.5V)
CPUVCCIOS0_PGOOD
ADAPTER A VIN
U7000 VOUT
PPVBAT_G3H (PAGE 62)
PGOOD
SMC_CPU_VSENSE
IN
SMC_DCIN_ISENSE ISL6259 SMC_CPU_ISENSE
V
PBUS SUPPLY/ R7050 CPU VCORE
VOUT A PPVCORE_S0_CPU
SMC_RESET_L
BATTERY CHARGER A VIN
MAX15119GTM
(PAGE 56)
SMC_BATT_ISENSE
CPUIMVP_VR_ON
VR_ON
U7400
VOUT
SMC_CPU_ISENSE
V SMC_CPU_VSENSE
PPVCORE_S0_AXG
J6950
Q7055
A SMC_GFX_VSENSE
PPVBATT_G3H_CONN PPVBAT_G3H_CHGR_R (PAGE 60)
Panther-POINT
(9 TO 12.6V)
PM_PWRBTN_L
PP5V_S0_CPUIMVP
V (PCH) PWRBTN#
3S2P
VDD SYS_RERST# PM_SYSRST_L

CPUIMVP_IMON
CHGR_BGATE IMON
CPUIMVP_IMONG
CPUIMVP_AXG_PWM2
PWN MAX17491
U7542
(PAGE 61)
A PPVCORE_S0_AXG
RSMRST# PM_RSMRST_L
IMONG
PGOOD CPUIMVP_PGOOD U1800
PGOODG CPUIMVP_AXG_PGOOD
www.qdzbwx.com PM_PCH_PWROK PLT_RERST_L
PLTRST#
C DDRREG_EN 1.5V
VIN VLDOIN PROCPWRGD
CPU_PWRGD
C
PP1V5R1V35_S3 PM_MEM_PWRGD
S5 VOUT1 DRAMPWROK
SMC Q5720 MEMVTT_EN

U7950 (PAGE 16~21)
PP5V_S5RS4_CUMUUS S3 0.75V PP0V75_S0_DDRVTT
VOUT2
U4900
SMC_PM_G2_EN TPS51916 TP_DDRREG_PGOOD
RC P3V3S5_EN
P60 U7300 PGOOD
DELAY P5VS4_EN
(PAGE 59)
(PAGE 38) P1V5CPU_EN
TBTAPWRSW_EN
SMC_S4_WAKESRC_EN ON SM_DRAMPWROK
TBTBPWRSW_EN VCCSLG5AP020
74LVG1G32
P3V3S4_EN PPVCCSA_S0_REG CPU
R5430 U7801 PP5V_S0
U7970 (PAGE 64) VCC VOUT
U1000 UNCOREPWRGOOD
(PAGE 65) P5VS4_EN ISL95875
PPBUS_S5_HS_OTHER_ISNS P1V5_CPU_EN PVCCSA_EN U7100
Panther-POINT A Q7801
EN
PGOOD
PVCCSA_PGOOD
(PAGE 9~13) RESET*
(PCH) PPVIN_S3_P1V5S3RS0_FET PP1V5_S3RS0_FET
(PAGE 57)
PM_SLP_S5_L PG 17
SLP_S5#(F6) Q7850
VIN VREG5 P1V5S3RS0FET_GATE
DDRREG_EN PG59 P5V3V3S4_EN 5V PP5V_S4 PP5V_S3_FET
EN1 VOUT1
RC
DELAY (L/H)
P5VS3_EN PG64 PP3V3_S5 PP3V3_S5

RC P3V3S5_EN 3.3V Q7860
DELAY EN2 VOUT2 P5V_S3_EN
(R/H) PP5V_S0_FET
P3V3S3_EN PG64
RC
DELAY TPS51980 Q7800
P1V2S3_EN U7201 SMC
B U1800 RC
DELAY
F9700
Q9706 (PAGE 60)
PGOOD
PP3V3_S4_FET
P5V_S0_EN
PP5V_S4_1V05BTS0
ALL_SYS_PWRGD B
PWRGD(P38)
TPAD_VBUS_EN PG46
RC
DELAY
P5V3V3_PGOOD P3V3_S4_EN S5_PWRGD
VIN RSMRST_IN(P38)
ISL8014A PP1V05_S0_P1V05BTREG_R RSMRST_OUT(P15) PM_RSMRST_L
PM_SLP_S4_L PG 17 Q7840 TBT_EN_LC_ISOL
LCD_BKLT_EN EN
SLP_S4#(K10)
PP5V_SUS_FET
U7720 P1V5S0_PGOOD SMC_ONOFF_L 99ms DLY
PWR_BUTTON(P90) CPUIMVP_VR_ON
&& BKLT_PLT_RST_L (PAGE 63) IMVP_VR_ON(P16)
P1V8S0_PGOOD
PM_SLP_S3_L PG 17 VIN
SLP_S3#(D4) P5VS4_PGOOD SYSRST(PA2) PM_SYSRST_L
P5VSUS_EN
LP8545SQX-EXTJ
(PAGE 16~21) PPBUS_S0_LCDBKLT_PWR PPVOUT_S0_LCDBKLT Q7810 PVCCSA_PGOOD PM_PWRBTN_L
U9701 P17(BTN_OUT)
EN PP3V3_S3
VOUT PM_SLP_S5_L
SLP_S5_L(P38)
(PAGE 70) CPUVCCIOS0_PGOOD SMC_RESET_L
PP3V3_S0_P1V5S0 PM_SLP_S4_L RES*
R7978 SLP_S4_L(P38)
PG65
P3V3S3_EN PM_SLP_S3_L
VIN SLP_S3_L(P38)
P1V5_S0_EN ISL8009B ALL_SYS_PWRGD
Q4260 Q7830 EN PP1V5_S0_REG
F4260 U7770 U4900
PP3V3_S0_FET
PPVP_FW (PAGE 63) PP3V3_S0 (PAGE 38)
P3V3_S0_EN
PM_SLP_S3_R_L PG67 PP3V3_S0_P1V8S0 PP5V_S0_VMON U7960
PP3V3_S0 && FWPORT_PWR_EN VMON_Q2
PP1V5_S3RS0_VMON 8
VMON_Q3
Q3880 IN
MAX15053EWL ISL88042IRTEZ R7962
P1V8_S0_EN PP1V8_S0_REG PP1V05_S0_VMON
Q7850 EN U7760 VMON_Q4
P5VS0_EN
A DELAY
RC PVCCSA_EN PG67 PP5VS3_FET (PAGE 63) (PAGE 67)
SYNC_MASTER=K17_REF SYNC_DATE=06/30/2009 A
PAGE TITLE
P3V3S0_EN T29_A_HV_EN
P5VS3_EN
PP3V3_SUS_P1V05SUSLDO Power Block Diagram
RC CPUVCCIOS0_EN PG67 DRAWING NUMBER SIZE
DELAY VIN Q7820
IN Apple Inc. <SCH_NUM> D
PBUSVSENS_EN LT3957 PP3V3_SUS_FET
TPS720105
PP1V05_SUS_LDO REVISION
EN R
U3890 U7740 <E4LABEL>
(PAGE 63) NOTICE OF PROPRIETARY PROPERTY: BRANCH
RC P1V8S0_EN PG67 TBT_S0_EN VOUT PP15V_TBT_REG
DELAY
(PAGE 34)
P3V3_SUS_EN
<BRANCH>
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
3 OF 132
P1V5S0_EN PG67 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
RC
DELAY
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
B B
A SYNC_MASTER=MASTER SYNC_DATE=MASTER A
PAGE TITLE
Revision History
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
NOTICE OF PROPRIETARY PROPERTY: BRANCH
<BRANCH>
4 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOM Variants Bar Code Labels / EEE #’s
BOM NUMBER BOM NAME BOM OPTIONS
TABLE_BOMGROUP_HEAD
Alternate Parts TABLE_ALT_HEAD
TABLE_BOMGROUP_ITEM
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

085-4094 DEV BOM,MLB,D1 D1_DEVEL:PVB PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PART NUMBER
TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM
607-9189 CMN PTS,PCBA,MLB,D1 D1_COMMON 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:DV7Q] CRITICAL EEEE:DV7Q 128S0364 128S0264 ALL Kemet alt to Sanyo
639-3288 PCBA,2.5G,SS 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:DWP2,RAM_6G_SAMSUNG_35NM_CH0_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:DWNY] CRITICAL EEEE:DWNY 128S0303 128S0353 ALL Panasonic alt to Sanyo
639-3289 PCBA,2.9G,SS 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:DWNY,RAM_6G_SAMSUNG_35NM_CH0_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:DWNW] CRITICAL EEEE:DWNW 376S0953 376S0958 ALL RENESAS ALT TO FAIRCHILD
639-3290 PCBA,2.5G,HYNIX 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:DWP0,RAM_6G_HYNIX_CH0_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:DWP0] CRITICAL EEEE:DWP0 128S0311 128S0329 ALL NEC ALT TO SANYO
639-3291 PCBA,2.9G,HYNIX 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:DWNW,RAM_6G_HYNIX_CH0_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:DWP2] CRITICAL EEEE:DWP2 353S3237 353S2192 ALL TI ALT TO INTERSIL
D 639-3694 PCBA,2.5G,SS 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F16P,RAM_4G_SAMSUNG_35NM_1600_S

TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F16M] CRITICAL EEEE:F16M 376S0977 376S0859 ALL Diodes alt to Toshiba
TABLE_ALT_ITEM
TABLE_ALT_ITEM
D
639-3695 PCBA,2.9G,SS 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F16M,RAM_4G_SAMSUNG_35NM_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F16N] CRITICAL EEEE:F16N 138S0722 138S0691 ALL Multi alt to Samsung
639-3696 PCBA,2.9G,HYNIX 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F16N,RAM_4G_HYNIX_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F16P] CRITICAL EEEE:F16P 197S0487 197S0485 ALL Epson alt to TXC
639-3697 PCBA,2.5G,HYNIX 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F16V,RAM_4G_HYNIX_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F16V] CRITICAL EEEE:F16V 197S0484 197S0485 ALL NDK alt to TXC
639-3773 PCBA,2.5G,ELPIDA 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F26M,RAM_6G_ELPIDA_CH0_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F26H] CRITICAL EEEE:F26H 197S0479 197S0486 ALL Epson alt to TXC
639-3772 PCBA,2.9G,ELPIDA 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F26J,RAM_6G_ELPIDA_CH0_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F26J] CRITICAL EEEE:F26J 197S0478 197S0486 ALL NDK alt to TXC
639-3770 PCBA,2.5G,ELPIDA 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F26L,RAM_4G_ELPIDA_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F26L] CRITICAL EEEE:F26L 197S0481 197S0480 ALL Epson alt to NDK
639-3771 PCBA,2.9G,ELPIDA 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F26H,RAM_4G_ELPIDA_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F26M] CRITICAL EEEE:F26M 376S0972 376S0612 ALL ROHM alt to Toshiba
639-3849 PCBA,2.5G,MICRON 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F2WT,RAM_6G_MICRON_CH0_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F2WQ] CRITICAL EEEE:F2WQ 376S1053 376S0604 ALL Diodes alt to Fairchild
639-3848 PCBA,2.9G,MICRON 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F2WR,RAM_6G_MICRON_CH0_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F2WR] CRITICAL EEEE:F2WR 376S1017 376S0612 ALL ROHM alt to Toshiba
639-3873 PCBA,2.6G,SS 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33H,RAM_6G_SAMSUNG_35NM_CH0_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F2WT] CRITICAL EEEE:F2WT 138S0624 138S0677 ALL Murata alt to Taiyo Yuden
639-3874 PCBA,2.8G,SS 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33P,RAM_6G_SAMSUNG_35NM_CH0_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F2WV] CRITICAL EEEE:F2WV 138S0681 138S0638 ALL Taiyo Yuden alt to Samsung
639-3875 PCBA,2.6G,HYNIX 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33L,RAM_6G_HYNIX_CH0_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F336] CRITICAL EEEE:F336 152S1703 152S1701 ALL Sumida alt to Cyntec
639-3876 PCBA,2.8G,HYNIX 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F339,RAM_6G_HYNIX_CH0_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F337] CRITICAL EEEE:F337 371S0730 371S0490 ALL Diodes alt to NXP
639-3881 PCBA,2.6G,SS 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33G,RAM_4G_SAMSUNG_35NM_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F338] CRITICAL EEEE:F338 138S0725 138S0724 ALL Samsung alt to Murata
639-3882 PCBA,2.8G,SS 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33C,RAM_4G_SAMSUNG_35NM_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F339] CRITICAL EEEE:F339 138S0727 138S0709 ALL Samsung alt to Murata
639-3884 PCBA,2.8G,HYNIX 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F337,RAM_4G_HYNIX_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F33C] CRITICAL EEEE:F33C 376S1080 376S0820 ALL Diodes alt to ON Semi
639-3883 PCBA,2.6G,HYNIX 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33D,RAM_4G_HYNIX_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F33D] CRITICAL EEEE:F33D 372S0186 372S0185 ALL NXP alt to Diodes
C 639-3877 PCBA,2.6G,ELPIDA 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33Q,RAM_6G_ELPIDA_CH0_1600_S

TABLE_BOMGROUP_ITEM
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F33F] CRITICAL EEEE:F33F 128S0363 128S0296 ALL NEC alt to Sanyo
TABLE_ALT_ITEM
C
639-3878 PCBA,2.8G,ELPIDA 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F338,RAM_6G_ELPIDA_CH0_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F33G] CRITICAL EEEE:F33G 376S0903 376S0796 ALL Fairchild alt to Siliconix
639-3885 PCBA,2.6G,ELPIDA 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33J,RAM_4G_ELPIDA_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F33H] CRITICAL EEEE:F33H 740S0144 740S0118 ALL Littlefuse alt to Polytronic
639-3886 PCBA,2.8G,ELPIDA 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33N,RAM_4G_ELPIDA_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F33J] CRITICAL EEEE:F33J 152S1539 152S1598 ALL Cyntec alt to Toko
639-3879 PCBA,2.6G,MICRON 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33M,RAM_6G_MICRON_CH0_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F33K] CRITICAL EEEE:F33K 152S1645 152S0461 ALL Cyntec alt to Vishay
639-3880 PCBA,2.8G,MICRON 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F336,RAM_6G_MICRON_CH0_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F33L] CRITICAL EEEE:F33L 155S0667 155S0583 ALL MAG LAYERS ALT TO MURATA
639-3846 PCBA,2.5G,MICRON 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F2WV,RAM_4G_MICRON_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F33M] CRITICAL EEEE:F33M 103S0305 103S0266 ALL Yageo alt to Cyntec
639-3847 PCBA,2.9G,MICRON 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F2WQ,RAM_4G_MICRON_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F33N] CRITICAL EEEE:F33N 112S0274 112S0254 ALL Yageo alt to Cyntec
639-3887 PCBA,2.6G,MICRON 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33K,RAM_4G_MICRON_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F33P] CRITICAL EEEE:F33P 376S1113 376S1110 ALL Diodes to AOS
639-3888 PCBA,2.8G,MICRON 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33F,RAM_4G_MICRON_1600_S 826-4393 1 LBL,P/N LABEL,PCB,28MM X 6 MM [EEEE:F33Q] CRITICAL EEEE:F33Q 155S0588 155S0367 ALL murata ALT TO MURATA
Module Parts D1 BOM GROUPS

TABLE_BOMGROUP_HEAD
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_ITEM
337S4181 1 IVB,QBP0,ES2,K0,2.3,35W,2+2,1.0,3M,BGA U1000 CRITICAL CPU_IVB_2C_2.3G_ES2 D1_COMMON ALTERNATE,COMMON,D1_COMMON1,D1_COMMON2,D1_PROGPARTS,D1_PVB

TABLE_BOMGROUP_ITEM
337S4182 1 IVB,QBP0,ES2,K0,2.6,35W,2+2,1.05,4M,BGA U1000 CRITICAL CPU_IVB_2C_2.6G_ES2 D1_COMMON1 CPUMEM:S0,SMC_DEBUG_YES,TBTBST:Y,TBTRTR:B1,TBTHV:P15V,HUB_2NONREM,USBHUB:2512B,AXG_PHASE2,TBTISNS:YES

TABLE_BOMGROUP_ITEM
337S4292 1 IVB,Q4CT,QS,L1,2.5,35W,2+2,1.1,3M,BGA U1000 CRITICAL CPU_IVB_2C_2.5G_QS D1_COMMON2 EDP:YES,PPDDR:1V35,LPCPLUS_CONN:YES,LPCPLUS_R:YES,CAPS:INT,BTPWR:S4,SKIP_5V3V3:AUDIBLE,TPAD_5V_LDO:S5,SMS

TABLE_BOMGROUP_ITEM
337S4300 1 IVB,QC96,QS,L1,2.6,35W,2+2,1.2,3M,BGA U1000 CRITICAL CPU_IVB_2C_2.6G_QS D1_PVB LOADISNS:NO,LCDBKLT:PROD,KBDBKLT:PROD

TABLE_BOMGROUP_ITEM
337S4302 1 IVB,QC94,QS,L1,2.8,35W,2+2,1.2,3M,BGA U1000 CRITICAL CPU_IVB_2C_2.8G_QS D1_PROGPARTS SMC_PROG:PVB,TBTROM:PROG,BOOTROM_PROG:PVB,TPAD_PSOC:PROG

TABLE_BOMGROUP_ITEM
B 337S4294 1 IVB,QC4M,QS,L1,2.9,35W,2+2,1.25,4M,BGA U1000 CRITICAL CPU_IVB_2C_2.9G_QS D1_BLANK

TABLE_BOMGROUP_ITEM
B
337S4264 1 IVB,S R0N0,PRQ,L1,2.5,35W,2+2,1.1,3M,BGA U1000 CRITICAL CPU_IVB_2C_2.5G D1_DEVEL:ENG ALTERNATE,IVB_PPT_XDP,LOADISNS:YES,S0PGOOD_ISL,DDRVREF_DAC,VREFDQ:M1_M3,VREFCA:LDO_DAC
TABLE_BOMGROUP_ITEM
337S4338 1 IVB,S R0MY,PRQ,L1,2.6,35W,2+2,1.2,3M,BGA U1000 CRITICAL CPU_IVB_2C_2.6G D1_DEVEL:PVB ALTERNATE,IVB_PPT_XDP,VREFDQ:M1_M3,VREFCA:LDO

TABLE_BOMGROUP_ITEM
337S4339 1 IVB,S R0MU,PRQ,L1,2.8,35W,2+2,1.2,3M,BGA U1000 CRITICAL CPU_IVB_2C_2.8G IVB_PPT_XDP XDP,XDP_CONN,XDP_CPU:BPM,XDP_PCH
337S4265 1 IVB,S R0MU,PRQ,L1,2.9,35W,2+2,1.25,4M,BGA U1000 CRITICAL CPU_IVB_2C_2.9G DDR3 SPD STRAPPINGS

TABLE_BOMGROUP_HEAD
337S4180 1 IC,PCH,PPT-MB SFF,ES2,B0 U1800 CRITICAL PCH_ES2 BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_ITEM
337S4235 1 IC,PCH,PPT-MB SFF,P-QS,C0 U1800 CRITICAL PCH_C0 RAM_4G_HYNIX_1600_S 4G_HYNIX_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

TABLE_BOMGROUP_ITEM
337S4283 1 IC,PCH,PPT-MB SFF,PRQ,C1 U1800 CRITICAL PCH_C1 RAM_2G_ELPIDA_1600_S 2G_ELPIDA_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

TABLE_BOMGROUP_ITEM
338S1113 1 IC,TBT,CR-4C,B1,PRQ,288FCBGA,12X12MM U3600 CRITICAL TBTRTR:B1 RAM_4G_SAMSUNG_28NM_1600_S 4G_SAMSUNG_28NM_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

TABLE_BOMGROUP_ITEM
333S0623 16 IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA CRITICAL

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170 2G_SAMSUNG_35NM_1600_S RAM_2G_MICRON_1600_S 2G_MICRON_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H
TABLE_BOMGROUP_ITEM
333S0622 16 IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA CRITICAL

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170 2G_HYNIX_1600_S RAM_4G_ELPIDA_1600_S 4G_ELPIDA_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L
TABLE_BOMGROUP_ITEM
333S0628 16 IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA CRITICAL

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170 2G_ELPIDA_1600_S RAM_4G_SAMSUNG_35NM_1600_S 4G_SAMSUNG_35NM_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H
TABLE_BOMGROUP_ITEM
333S0649 16 IC,SDRAM,DDR3-1600,256MX8,78FBGA,MICRON CRITICAL

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170 2G_MICRON_1600_S RAM_6G_SAMSUNG_35NM_CH0_1600_S 6G_SAMSUNG_35NM_CH0_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L
TABLE_BOMGROUP_ITEM
333S0625 16 IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX CRITICAL

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170 4G_HYNIX_1600_S RAM_4G_MICRON_1600_S 4G_MICRON_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
TABLE_BOMGROUP_ITEM
333S0629 16 IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA CRITICAL

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170 4G_ELPIDA_1600_S RAM_6G_MICRON_CH0_1600_S 6G_MICRON_CH0_1600_S,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L
TABLE_BOMGROUP_ITEM
333S0624 16 IC,SDRAM,DDR3-1600,512MX8,78FBGA,D35,SAMSUNG CRITICAL

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170 4G_SAMSUNG_35NM_1600_S RAM_6G_ELPIDA_CH0_1600_S 6G_ELPIDA_CH0_1600_S,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L
TABLE_BOMGROUP_ITEM
333S0623 8 IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170 CRITICAL 6G_SAMSUNG_35NM_CH0_1600_S RAM_6G_SAMSUNG_28NM_CH0_1600_S 6G_SAMSUNG_28NM_CH0_1600_S,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

TABLE_BOMGROUP_ITEM
6G_HYNIX_CH0_1600_S,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L
A 333S0624
333S0622
8
8
IC,SDRAM,DDR3-1600,512MX8,78FBGA,D35,SAMSUNG
IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA
U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970
U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170
CRITICAL
CRITICAL
6G_SAMSUNG_35NM_CH0_1600_S
6G_HYNIX_CH0_1600_S
RAM_6G_HYNIX_CH0_1600_S
RAM_2G_SAMSUNG_1600_S 2G_SAMSUNG_35NM_1600_S,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H
TABLE_BOMGROUP_ITEM
SYNC_MASTER=MASTER SYNC_DATE=MASTER A
PAGE TITLE
TABLE_BOMGROUP_ITEM
333S0625 8 IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970 CRITICAL 6G_HYNIX_CH0_1600_S RAM_2G_HYNIX_1600_S 2G_HYNIX_1600_S,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L BOM Configuration

333S0628 8 IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170 CRITICAL 6G_ELPIDA_CH0_1600_S Module Parts DRAWING NUMBER
<SCH_NUM> D
SIZE
333S0629 8 IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970 CRITICAL 6G_ELPIDA_CH0_1600_S PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
Apple Inc. REVISION
R
333S0660 16 IC,SDRAM,DDR3-1600,512MX8,78FBGA,MICRON CRITICAL

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170 4G_MICRON_1600_S 333S0642 16 IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG CRITICAL
U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170 4G_SAMSUNG_28NM_1600_S
<E4LABEL>
333S0649 8 IC,SDRAM,DDR3-1600,256MX8,78FBGA,MICRON U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170 CRITICAL 6G_MICRON_CH0_1600_S 333S0623 8 IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170 CRITICAL 6G_SAMSUNG_28NM_CH0_1600_S THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
333S0660 8 CRITICAL 333S0642 8 CRITICAL
IC,SDRAM,DDR3-1600,512MX8,78FBGA,MICRON U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970 6G_MICRON_CH0_1600_S IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970 6G_SAMSUNG_28NM_CH0_1600_S
5 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
PD Module Parts
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
860-1533 1 STDOFF,BMU,TOPSIDE,D1,SM J6950_63 CRITICAL
860-1530 1 STDOFF-1.9D2.93H-TH-0.85-1.2 J6950_64 CRITICAL
860-1529 1 STDOFF-1.80D1.53H-SM J6950_65 CRITICAL
825-7841 1 LBL,PART CONFIG,BOARDS,D2 CONFIG_LABEL CRITICAL
946-4350 1 D1 MLB LOCTITE UV GLUE 190024/S 0.24G EDGE_BOND CRITICAL
DEVELOPMENT/BASE BOMs
085-4094 1 D1 MLB DEVELOPMENT BOM DEVEL CRITICAL DEVEL_BOM
607-9189 1 D1 MLB BASE BOM BASE CRITICAL BASE_BOM

B B
SMC
341S3528 1 IC,SMC12,PROTO1,D1 U4900 CRITICAL SMC_PROG:PROTO
341S3404 1 IC,SMC,DEVELOPMENT-PIB,D1 U4900 CRITICAL SMC_PROG:PIB
341S3405 1 IC,SMC,DEVELOPMENT-FSB,D1 U4900 CRITICAL SMC_PROG:FSB
341S3406 1 IC,SMC,DEVELOPMENT-PVB,D1 U4900 CRITICAL SMC_PROG:PVB
EFI ROM
341S3571 1 IC,EF,ROM,PROTO1,D1 U6100 CRITICAL BOOTROM_PROG:PROTO
341S3603 1 IC,EFI,ROM,PIB, D1 U6100 CRITICAL BOOTROM_PROG:PIB
341S3636 1 IC,EFI,ROM,PIB2, D1 U6100 CRITICAL BOOTROM_PROG:PIB2
341S3650 1 IC,EFI,ROM,FSB, D1 U6100 CRITICAL BOOTROM_PROG:FSB
341SXXXX 1 IC,EFI,ROM,FSB2, D1 U6100 CRITICAL BOOTROM_PROG:FSB2
341S3667 1 IC,EFI,ROM,PVB, D1 U6100 CRITICAL BOOTROM_PROG:PVB
Programmables - All builds

335S0809 1 64 MBIT SPI SERIAL DUAL I/O FLASH,Macronix U6100 CRITICAL BOOTROM_BLANK
A 335S0803
341S3670
1
1
64 MBIT SPI SERIAL DUAL I/O FLASH,Numonyx
IC,TP PSOC,V224,PVB,D1
U6100
U5701
CRITICAL
CRITICAL
BOOTROM_BLANK
TPAD_PSOC:PROG
PAGE TITLE
337S2983 1 IC,TP PSOC,QFN,BLANK U5701 CRITICAL TPAD_PSOC:BLANK BOM Configuration

DRAWING NUMBER SIZE
341S3668 1 U3690 CRITICAL
IC,EEPROM,CR,V14.1,D1 PVB TBTROM:PROG

335S0865 1 IC,EEPROM,SERIAL,8KB,SOIC U3690 CRITICAL TBTROM:BLANK REVISION
R
338S1098 1 IC,SMC12-A3,LX4FS1AH5BBCIGA3 U4900 CRITICAL SMC_BLANK

<E4LABEL>
998-3919 1 SOCKET, SMC12 J4900 CRITICAL SMC_SOCKET THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
6 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J5713 (KEY BOARD CONN) POWER RAILS S2 CAMERA PCIE SIGNALS PCIE_ENET_R2D_C_P
PP3V3_S4 FUNC_TEST
ICT Test Points I1885
PCIE_ENET_R2D_C_N TRUE
Functional Test Points TRUE
PP3V42_G3H
7 8
NC_PCIE_CAMERA_D2RP
MAKE_BASE=TRUE
PCIE_EXCARD_D2R_N 17
I1884
TRUE
TRUE 7 8
TRUE PM_SLP_S3_L 7 18 27 36 39 66 CPU NO_TESTs NC_PCIE_CAMERA_D2RN TRUE PCIE_EXCARD_D2R_P 17
WS_KBD1 MAKE_BASE=TRUE
J5650 (LEFT FAN CONN)
TRUE 47
TRUE PP0V75_S0_DDRVTT 8 NC_PCIE_CAMERA_R2D_CN TRUE PCIE_EXCARD_R2D_C_N 17
WS_KBD2 TP_TBT_MONDC0 TRUE NC_TBT_MONDC0 MAKE_BASE=TRUE
FUNC_TEST
TRUE 47 33
MAKE_BASE=TRUE NC_PCIE_CAMERA_R2D_CP TRUE PCIE_EXCARD_R2D_C_P 17
3 TPs TRUE WS_KBD3 47 33 TP_TBT_MONDC1 TRUE NC_TBT_MONDC1 MAKE_BASE=TRUE TRUE
TRUE PP5V_S0 7 8 per Fan TRUE PP1V05_S0 8 MAKE_BASE=TRUE
TRUE WS_KBD4 47 33 TP_TBT_PCIE_RESET0_L TRUE NC_TBT_PCIE_RESET0_L
MAKE_BASE=TRUE NC_PCIE_CLK100M_CAMERAN PCIE_CLK100M_EXCARD_N 7 17 75
TRUE FAN_LT_PWM 46 TRUE WS_KBD5 47 33 TP_TBT_PCIE_RESET1_L TRUE NC_TBT_PCIE_RESET1_L MAKE_BASE=TRUE TRUE
MAKE_BASE=TRUE
TRUE FAN_LT_TACH 46 TRUE WS_KBD6 47 33 TP_TBT_PCIE_RESET2_L TRUE NC_TBT_PCIE_RESET2_L NC_PCIE_CLK100M_CAMERAP PCIE_CLK100M_EXCARD_P 7 17 75
MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE PCIE_AP_R2D_C_P
TRUE WS_KBD7 47 TRUE LED_RETURN_2 7 67 71 33 TP_TBT_PCIE_RESET3_L TRUE NC_TBT_PCIE_RESET3_L I1889
TRUE
J5660 (RIGHT FAN CONN) U1000 CHARZ TPS
WS_KBD8 LED_RETURN_3 TP_TBT_XTAL25OUT MAKE_BASE=TRUE
NC_TBT_XTAL25OUT I1888
PCIE_AP_R2D_C_N
P2MM
SM
TRUE 47 TRUE 7 67 71 33 TRUE NO_TEST NC NO_TESTs PCIE_AP_D2R_P TRUE
MAKE_BASE=TRUE
TRUE FAN_RT_PWM 75 33 9 PCIE_TBT_D2R_P<0> 1P2MM TRUE WS_KBD9 TRUE LED_RETURN_4 I1887
TRUE
46 I1919 PP
SM PP0700 47 7 67 71
TRUE NC_PCIE_5_D2RN PCIE_AP_D2R_N
D TRUE FAN_RT_TACH
GND
46 75 33 9
I1920
PCIE_TBT_D2R_N<0>
DMI_S2N_P<0>
1P2MM
PP
SM
1P2MM
PP0701 TRUE WS_KBD10
WS_KBD11
47 TRUE LED_RETURN_5
LED_RETURN_6
7 67 71
TP_DP_TBTSRC_ML_CP<3> TRUE NC_DP_TBTSRC_ML_CP<3>

I1671
I1670 TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_PCIE_5_D2RP
17
17 D I1886
PCIE_AP_D2R_PI_P
TRUE
TRUE 5 TPs
per Fan
I1922
DMI_S2N_N<0>
PP
SM
1P2MM
PP0702 TRUE
WS_KBD12
47 TRUE
GND
7 67 71 33
TP_DP_TBTSRC_ML_CN<3> MAKE_BASE=TRUE
TRUE NC_DP_TBTSRC_ML_CN<3> I1672 TRUE
MAKE_BASE=TRUE
NC_PCIE_5_R2D_CN 17
I1892
PCIE_AP_D2R_PI_N TRUE
I1921
DMI_CLK100M_CPU_P
PP
SM
1P2MM
PP0703 TRUE
WS_KBD13
47 TRUE
4 TPs
33
MAKE_BASE=TRUE I1673 TRUE
MAKE_BASE=TRUE
NC_PCIE_5_R2D_CP 17
I1893
PCIE_AP_R2D_PI_P TRUE
J3502 (ALS/CAMERA CONN)
I1980
DMI_CLK100M_CPU_N 1
PP
SM PP0721 TRUE
TRUE WS_KBD14
47
33 TP_DP_TBTSRC_ML_CP<2> TRUE NC_DP_TBTSRC_ML_CP<2>
MAKE_BASE=TRUE TRUE NC_PCIE_6_D2RN
I1895
PCIE_AP_R2D_PI_N TRUE
TRUE SMBUS_SMC_2_S3_SDA 7 39 42 77
I1979 PP
PP0722 TRUE WS_KBD15_CAP
47
47
33 TP_DP_TBTSRC_ML_CN<2> TRUE NC_DP_TBTSRC_ML_CN<2>
MAKE_BASE=TRUE
I1675
TRUE
MAKE_BASE=TRUE
NC_PCIE_6_D2RP
17
17
I1894
TRUE
I1503 I1674
U1800 CHARZ TPS MAKE_BASE=TRUE
TRUE SMBUS_SMC_2_S3_SCL 7 39 42 77 P2MM TRUE WS_KBD16_NUM 47 33 TP_DP_TBTSRC_ML_CP<1> TRUE NC_DP_TBTSRC_ML_CP<1> TRUE NC_PCIE_6_R2D_CN 17
I1502
72 18 SM MAKE_BASE=TRUE I1676
MAKE_BASE=TRUE PCIE_CLK100M_PCH_P
TRUE PP5V_S3_ALSCAMERA_F 7 32 10 DMI_N2S_P<0> 1P2MM TRUE WS_KBD17 TP_DP_TBTSRC_ML_CN<1> TRUE NC_DP_TBTSRC_ML_CN<1> TRUE NC_PCIE_6_R2D_CP I1896 TRUE
I1504 I1924
DMI_N2S_N<0>
PP
SM
1P2MM
PP0704 WS_KBD18
47
TRUE PP3V3_S0 7 8 78
33
MAKE_BASE=TRUE I1677
MAKE_BASE=TRUE
17
I1897
PCIE_CLK100M_PCH_N
I1923
SM PP0705
PP TRUE 47
TP_DP_TBTSRC_ML_CP<0> NC_DP_TBTSRC_ML_CP<0> NC_PCIE_7_D2RN PCIE_CLK100M_TBT_P TRUE
J4400 (RIO CABLE CONN) 33 TRUE TRUE 17
FDI_DATA_P<0> 1P2MM TRUE WS_KBD19 PP3V3_S3 MAKE_BASE=TRUE I1679
TRUE
I1531 TRUE PP3V3_S4 7 8
I1926
FDI_DATA_N<0>
PP
SM
1P2MM
PP0706 WS_KBD20
47
TRUE 7 8 33 TP_DP_TBTSRC_ML_CN<0> TRUE NC_DP_TBTSRC_ML_CN<0>
MAKE_BASE=TRUE I1678 TRUE
MAKE_BASE=TRUE
NC_PCIE_7_D2RP 17 I1901
PCIE_CLK100M_TBT_N
TRUE
TRUE PP3V3_S3 7 8
I1925 PP PP0707
SM
TRUE 47
TRUE
PP3V3_S5 8 78 TRUE NC_PCIE_7_R2D_CN 17
I1534 FDI_DATA_P<4> 1P2MM WS_KBD21 TP_DP_TBTSRC_AUXCH_CP TRUE NC_DP_TBTSRC_AUXCH_CP I1680
MAKE_BASE=TRUE
I1533 TRUE PP3V3_WLAN_F 7 36 40 80
I1927
FDI_DATA_N<4>
PP
SM
1P2MM
PP0708 TRUE
WS_KBD22
47
TRUE PP3V3_S5_AVREF_SMC 39 40
33
TP_DP_TBTSRC_AUXCH_CN MAKE_BASE=TRUE
TRUE NC_DP_TBTSRC_AUXCH_CN I1681 TRUE
MAKE_BASE=TRUE
NC_PCIE_7_R2D_CP 17
SM PP0709
PP TRUE 47 33
TRUE PP5V_S4 8
I1928
TRUE PP3V42_G3H 7 8 MAKE_BASE=TRUE PCH_CLK100M_SATA_P
I1535
75 36 17 7 PCIE_AP_D2R_P 1P2MM TRUE WS_KBD23 TRUE NC_PCIE_8_D2RN I1899
TRUE
SM PP0710
PP 47 17
TRUE PP1V5_S0 8
I1929
TRUE PP5V_S0 7 8
I1683
MAKE_BASE=TRUE
I1538
75 36 17 7 PCIE_AP_D2R_N 1P2MM TRUE WS_KBD_ONOFF_L TRUE NC_PCIE_8_D2RP
SM PP0711
PP 47 17
I1930
TRUE PP5V_S3 8 17 TP_SPI_CS1_L TRUE NC_SPI_CS1_L I1682
MAKE_BASE=TRUE
75 36 17 PCIE_ENET_D2R_P 1P2MM TRUE WS_LEFT_SHIFT_KBD 47 MAKE_BASE=TRUE TRUE NC_PCIE_8_R2D_CN
SM PP0712
PP 17
J4410 (RIO FLEX CONN)
I1931
TRUE PP5V_S5 8 20 TP_PCH_GPIO8 TRUE NC_PCH_GPIO8 I1684
MAKE_BASE=TRUE PCH_CLK33M_PCIIN
75 36 17 PCIE_ENET_D2R_N 1P2MM TRUE WS_LEFT_OPTION_KBD 47 MAKE_BASE=TRUE TRUE NC_PCIE_8_R2D_CP I1909
TRUE
TRUE USB_EXTB_OC_L
I1932
PCIE_CLK100M_TBT_P
PP
SM
1P2MM
PP0713 TRUE WS_CONTROL_KBD TRUE PPBUS_G3H 8 19 TP_PCH_STRP_BBS1 TRUE NC_PCH_STRP_BBS1
MAKE_BASE=TRUE
I1685
MAKE_BASE=TRUE
17
SM PP0723
24 36 47
I1512 I1984 PP
TRUE PPDCIN_G3H 8 19 TP_PCH_STRP_ESI_L TRUE NC_PCH_STRP_ESI_L
TRUE HDMI_IG_DDC_CLK PCIE_CLK100M_TBT_N 1 MAKE_BASE=TRUE TP_PCIE_CLK100M_PE4N TRUE NC_PCIE_CLK100M_PE4N PCIE_CLK100M_SSD_P
I1511
TRUE HDMI_IG_DDC_DATA
9 36
9 36
I1983 PP
PP0724 J5700 (IPD FLEX CONN)
19 TP_PCH_TP23 TRUE NC_PCH_TP23
MAKE_BASE=TRUE
17
17 TP_PCIE_CLK100M_PE4P MAKE_BASE=TRUE
TRUE NC_PCIE_CLK100M_PE4P
I1910
PCIE_CLK100M_SSD_N TRUE
I1513
TRUE PPVCORE_S0_CPU 8 19 TP_PCI_CLK33M_OUT2 TRUE NC_PCI_CLK33M_OUT2 MAKE_BASE=TRUE I1911
TRUE
TRUE HDMI_HPD_L 36 40 U4900 CHARZ TPS MAKE_BASE=TRUE PEG_CLK100M_P
I1515
P2MM TRUE PP3V3_S4 7 8 17 TP_PCIE_CLK100M_PEGAN TRUE NC_PCIE_CLK100M_PEGAN 17 TP_PCIE_CLK100M_PEBN TRUE NC_PCIE_CLK100M_PEBN I1904
TRUE
TRUE PM_SLP_S3_L 7 18 27 36 39 66 SM MAKE_BASE=TRUE MAKE_BASE=TRUE PEG_CLK100M_N
I1514
LPC_AD<0> 1P2MM TRUE Z2_CS_L TP_PCIE_CLK100M_PEGAP TRUE NC_PCIE_CLK100M_PEGAP TP_PCIE_CLK100M_PEBP TRUE NC_PCIE_CLK100M_PEBP I1903
TRUE
I1517 TRUE PM_SLP_S4_L 18 27 36 38 39 66
I1954
LPC_AD<1> PP0714
PP
SM
1P2MM TRUE Z2_MOSI
47
TRUE PPVTTDDR_S3
17
TP_PM_SLP_A_L TRUE
MAKE_BASE=TRUE
NC_PM_SLP_A_L
17
PCIE_CLK100M_ENET_P
TRUE
I1516 TRUE AP_CLKREQ_Q_L 7 36
I1956
LPC_AD<2> 1P2MM
PP0715
PP
SM
TRUE Z2_MISO
47 8 18
MAKE_BASE=TRUE
TP_PPVOUT_PCH_DCPSUSBYP TRUE NC_PPVOUT_PCH_DCPSUSBYP TP_SATA_C_D2RN TRUE NC_SATA_C_D2RN I1905
PCIE_CLK100M_ENET_N
SM PP0716
PP 47 21 17
TRUE ENET_RESET_L 25
I1955
DMI_S2N_P<3..1> 10 18 72 MAKE_BASE=TRUE MAKE_BASE=TRUE PCIE_CLK100M_AP_P TRUE
I1518
LPC_AD<3> 1P2MM TRUE Z2_SCLK I1828
TP_SMC_MPM5_LED_PWR TRUE NC_SMC_MPM5_LED_PWR TP_SATA_C_D2RP TRUE NC_SATA_C_D2RP I1917
TRUE
I1519 TRUE ENET_CLKREQ_L 17 36
I1958
LPC_FRAME_L
PP
SM
1P2MM
PP0717 Z2_HOST_INTN
47
I1829
DMI_S2N_N<3..1> TRUE 10
TRUE
39
18 72
TP_SMC_MPM5_LED_CHG MAKE_BASE=TRUE
TRUE NC_SMC_MPM5_LED_CHG
17
TP_SATA_C_R2D_CN MAKE_BASE=TRUE
TRUE NC_SATA_C_R2D_CN I1916
PCIE_CLK100M_AP_N
SD_PWR_EN I1957 PP
SM PP0718 TRUE 47
DMI_N2S_P<3..1> 39
MAKE_BASE=TRUE
17
PCIE_CLK100M_FW_P TRUE
TRUE 9 36 10 18 72 MAKE_BASE=TRUE
I1520
LPC_CLK33M_SMC 1 PP5V_S4_CUMULUS I1830 TP_SMS_INT2 NC_SMS_INT2 TP_SATA_C_R2D_CP NC_SATA_C_R2D_CP I1914
C I1522 TRUE
TRUE
SDCONN_STATE_CHANGE_SMC 25 40
PCIE_WAKE_L 7 18 36
I1959 PP
P2MM
PP0719
SM
TRUE
TRUE Z2_CLKIN
47
47
I1831
DMI_N2S_N<3..1> TRUE
TRUE
49
10 18 72
TRUE
MAKE_BASE=TRUE
PCIE_TBT_R2D_C_P<3..0> 9 33 75
17
17 TP_SATA_D_D2RN
TRUE
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
NC_SATA_D_D2RN C I1915
PCIE_CLK100M_FW_N TRUE
TRUE
PCIE_CLK100M_EXCARD_P
I1521 55 51 AUD_DMIC_SDA1 1 SMBUS_SMC_2_S3_SCL 7 39 42 77
I1820
TRUE TP_SATA_D_D2RP TRUE NC_SATA_D_D2RP I1913
TRUE
I1523 TRUE AP_CLKREQ_Q_L 7 36
I1972 PP
PP0720 TRUE
SMBUS_SMC_2_S3_SDA 7 39 I1822
PCIE_TBT_R2D_C_N<3..0> 9 33 75
17
TP_SATA_D_R2D_CN MAKE_BASE=TRUE
TRUE NC_SATA_D_R2D_CN I1912
PCIE_CLK100M_EXCARD_N
TRUE 42 77 TRUE 17
TRUE AP_RESET_CONN_L 7 36 PCIE_TBT_R2D_P<3..0> 33 75 MAKE_BASE=TRUE
I1524
J6701 (AUDIO JACK CONN) TRUE PSOC_SCLK 47
I1821
TRUE 17 TP_SATA_D_R2D_CP TRUE NC_SATA_D_R2D_CP
TRUE WIFI_EVENT_L 36 39 40 TBTBPWRSW_ISET_V3P3 70 PCIE_TBT_R2D_N<3..0> TRUE 33 75 MAKE_BASE=TRUE
I1525
TRUE AUD_CONN_SLEEVE 54 TRUE PSOC_MOSI 47
I1806
TRUE I1823
17 TP_SATA_E_D2RN TRUE NC_SATA_E_D2RN
TRUE USB_EXTB_P 26 36 74
I1631
PCIE_TBT_D2R_P<3..1> 9 33 75 MAKE_BASE=TRUE
I1526
TRUE AUD_CONN_MIC_XW 54 TRUE PSOC_MISO 47
I1827
TRUE 17 TP_SATA_E_D2RP TRUE NC_SATA_E_D2RP
TRUE USB_EXTB_N 26 36 74
I1633
PCIE_TBT_D2R_N<3..1> 9 33 75 MAKE_BASE=TRUE
I1527
TRUE AUD_CONN_SLEEVE_XW 54 TRUE PICKB_L 47 TBTBPWRSW_ISET_S0_R 70
I1826 TRUE 17 TP_SATA_E_R2D_CN TRUE NC_SATA_E_R2D_CN SATA_HDD_R2D_RDRIN_P
I1529 TRUE USB_BT_CONN_P 9 36 74
I1632
AUD_CONN_HP_LEFT 54 PSOC_F_CS_L
I1808
TBTBPWRSW_ISET_S3 TRUE I1824
PCIE_TBT_D2R_C_P<3..1> 33 75
TP_SATA_E_R2D_CP MAKE_BASE=TRUE
NC_SATA_E_R2D_CP
I1858
SATA_HDD_R2D_RDRIN_NTRUE
TRUE TRUE 47 70 TRUE 17 TRUE
TRUE USB_BT_CONN_N 9 36 74
I1634 I1809
TRUE PCIE_TBT_D2R_C_N<3..1> 33 75 MAKE_BASE=TRUE I1860
TRUE
I1528
I1636 TRUE AUD_CONN_TIPDET_INV I1629 TRUE Z2_KEY_ACT_L 47
I1825
TRUE 17 TP_SATA_F_D2RN TRUE NC_SATA_F_D2RN I1859
SATA_HDD_D2R_RDROUT_P
MAKE_BASE=TRUE TRUE
TRUE PP3V3_S0 7 8 78 J6900 (DC POWER CONN) 17 TP_SATA_F_D2RP TRUE NC_SATA_F_D2RP SATA_HDD_D2R_RDROUT_N
I1635 TBTAPWRSW_ISET_V3P3 69 MEM_A_DQ<0> 12 28 73 MAKE_BASE=TRUE I1861
TRUE
AUD_SPDIF_OUT_JACK 51 54 I1811
TRUE I1709 TP_SATA_F_R2D_CN NC_SATA_F_R2D_CN SATA_HDD_D2R_RDRIN_P
TRUE AP_RESET_CONN_L 7 36
I1637 TRUE
TRUE TDM_ONEWIRE_MPM MEM_A_DQ<12..2> TRUE 12 28 73
17 TRUE
TRUE
I1536 AUD_CONN_HP_RIGHT 54 I1657 TBTAPWRSW_ISET_S0 I1710 TP_SATA_F_R2D_CP NC_SATA_F_R2D_CP SATA_HDD_D2R_RDRIN_N
TRUE SMBUS_PCH_CLK 17 42 75
I1639 TRUE
TRUE ADAPTER_SENSE 56
I1812
TRUE
69
MEM_A_DQ<19..14> TRUE 12 28 73
17 TRUE
TRUE
I1540
AUD_CONN_TYPEDET 54 I1711
SATA_HDD_R2D_RDROUT_N
TRUE SMBUS_PCH_DATA 17 42 75
I1640 TRUE
TRUE PP18V5_DCIN_FUSE 56 MEM_A_DQ<24..21> TRUE 12 28 73
I1865
TRUE
I1541
AUD_CONN_MIC I1712
TP_CRT_IG_BLUE NC_CRT_IG_BLUE SATA_HDD_R2D_RDROUT_P
I1638 TRUE 54
TBTAPWRSW_ISET_S3 MEM_A_DQ<32..26> TRUE 18 TRUE
GND I1814 69 I1713 12 28 73
TP_CRT_IG_GREEN NC_CRT_IG_GREEN SATA_HDD_D2R_RC_P TRUE
TRUE
TBTAPWRSW_ISET_S3_RTRUE MEM_A_DQ<42..34> TRUE 18 TRUE
J4500 (SSD/HDD FLEX CONN) I1815
TRUE
69 I1714 12 28 73
TP_CRT_IG_RED NC_CRT_IG_RED SATA_HDD_D2R_RC_N TRUE
I1544 TRUE SMBUS_SMC_1_S0_SCL 39 42 77 J6802 (AUDIO LEFT SPEAKER CONN)
TBT_A_R2D_C_P<1..0> I1715
MEM_A_DQ<54..44> TRUE 12 28 73
18 TRUE
SATA_HDD_R2D_RC_N TRUE
33 69 76 TRUE
TRUE SMBUS_SMC_1_S0_SDA 39 42 77
I1834
TRUE MEM_A_DQ<56> 12 28 73
I1868
TRUE
SPKRCONN_L_OUT_P TBT_A_R2D_C_N<1..0> I1716 TP_CRT_IG_DDC_CLK NC_CRT_IG_DDC_CLK SATA_HDD_R2D_RC_P
I1644 TRUE 53 55 78
TRUE PP3V3_S0_SSD_FLT 37
I1835
TRUE
33 69 76
MEM_A_DQ<63..58> TRUE 12 28 73
18 TRUE
TRUE
I1646 TRUE SPKRCONN_L_OUT_N 53 55 78
I1566
I1836
TBT_A_R2D_P<1..0> 69 76
I1717
TRUE 18 TP_CRT_IG_DDC_DATA TRUE NC_CRT_IG_DDC_DATA
SPKRCONN_L_ID I1567 TRUE SMC_OOB1_TX_L 37 39 40
TBT_A_R2D_N<1..0> TRUE MAKE_BASE=TRUE
SATA_HDD_R2D_C_P
TRUE 51 55 69 76
I1648
TRUE SMC_OOB1_RX_L 37 39 40
I1837
TRUE MEM_B_DQ<2..0> 12 29 73
I1870
TRUE
SPKRCONN_SL_OUT_P I1569 I1719 TP_CRT_IG_HSYNC NC_CRT_IG_HSYNC SATA_HDD_R2D_C_N
I1647 TRUE 53 55 78
TRUE PP5V_S0_HDD_FLT 37 TBT_A_D2R_C_P<1> 69 76 MEM_B_DQ<13..4> TRUE 12 29 73
18 TRUE
TRUE
SPKRCONN_SL_OUT_N I1571 I1838
TRUE I1718
TP_CRT_IG_VSYNC NC_CRT_IG_VSYNC SATA_HDD_D2R_P
I1649 TRUE 53 55 78
TBT_A_D2R_C_N<1> 69 76 MEM_B_DQ<19..15> TRUE 12 29 73
18 TRUE
TRUE
J5815 (KBD BACKLIGHT CONN) I1839 I1720
SATA_HDD_D2R_N
TRUE GND TBT_A_D2R_C_P<0> TRUE
69 76 MEM_B_DQ<25..21> TRUE 12 29 73 17 TP_HDA_SDIN1 TRUE NC_HDA_SDIN1 I1873
TRUE
PP_KBD_BOOST_VOUT 48 FUNC_TEST I1840 I1722
I1630 TRUE
J6803 (AUDIO RIGHT SPEAKER CONN) TBT_A_D2R_C_N<0> TRUE
69 76 MEM_B_DQ<35..27> TRUE 12 29 73 17 TP_HDA_SDIN2 MAKE_BASE=TRUE
TRUE NC_HDA_SDIN2
KBDLED_CATHODE1 BKLT_EN I1841 I1721
I1493 TRUE 48 TRUE 71 TRUE MEM_B_DQ<40..37> TRUE 12 29 73 17 TP_HDA_SDIN3 MAKE_BASE=TRUE
TRUE NC_HDA_SDIN3
KBDLED_CATHODE2 SPKRCONN_R_OUT_P I1723
TRUE TRUE
MEM_B_DQ<47..42> TRUE MAKE_BASE=TRUE
B TRUE
48
SMC_KBDLED_PRESENT_L 48
I1653
I1654 TRUE SPKRCONN_R_OUT_N

53 55 78
53 55 78
TRUE LCD_BKLT_PWM 9 71 I1843
TBT_A_D2R_P<1>
TBT_A_D2R_N<1> TRUE
33 69 76
33 69 76
I1724
MEM_B_DQ<57..49> TRUE
12 29 73
12 29 73 18 TP_SDVO_TVCLKINN TRUE NC_SDVO_TVCLKINN

B
SPKRCONN_R_ID PM_CLKRUN_L I1842 I1725 SATA_SSDRHDD_D2R_P
I1652 TRUE 51 55 TRUE 7 18 39 41
TBT_A_D2R_P<0> TRUE MEM_B_DQ<63..59> TRUE 18 TP_SDVO_TVCLKINP MAKE_BASE=TRUE
TRUE NC_SDVO_TVCLKINP I1874
TRUE SPKRCONN_SR_OUT_P 53 55 78 TRUE PM_SYSRST_L 18 25 39
I1844
TRUE
33 69 76 I1726
TRUE
12 29 73
MAKE_BASE=TRUE SATA_SSDRHDD_D2R_N TRUE
I1651 TBT_A_D2R_N<0> I1875
TRUE SPKRCONN_SR_OUT_N 53 55 78
I1845
TRUE
33 69 76
18 TP_SDVO_STALLN TRUE NC_SDVO_STALLN SATA_SSDRHDD_R2D_P TRUE
I1655 NC_MEM_EVENT_L MAKE_BASE=TRUE I1876
I1656 TRUE GND I1846

TBT_B_R2D_C_P<1..0> 33 70 76
I1731
TRUE
40
18 TP_SDVO_STALLP TRUE NC_SDVO_STALLP I1877
SATA_SSDRHDD_R2D_N TRUE
TRUE MAKE_BASE=TRUE TRUE
TRUE SMC_ONOFF_L 39 40 47 TBT_B_R2D_C_N<1..0> 33 70 76
J9000 (EDP CONN) I1847
TRUE 18 TP_SDVO_INTN TRUE NC_SDVO_INTN
TBT_B_R2D_P<1..0> 70 76 HDMI_IG_CLK_C_P 9 36 78 MAKE_BASE=TRUE
I1848
TRUE
I1879
TRUE 18 TP_SDVO_INTP TRUE NC_SDVO_INTP
J6950 (MAIN BATT CONN) TBT_B_R2D_N<1..0> 70 76 HDMI_IG_CLK_C_N 9 36 78 MAKE_BASE=TRUE
I1849
TRUE
I1878
TRUE USB3_EXTA_RX_F_P
TRUE PPVBAT_G3H_CONN 56 57 TRUE PP5VR3V3_SW_LCD 67 TBT_B_D2R_C_P<0> 70 76 HDMI_IG_DATA_C_P<2..0> 9 36 78
I1960
TRUE
I1850
TRUE
I1881
TRUE 19 TP_PCI_PME_L TRUE NC_PCI_PME_L USB3_EXTA_RX_F_N
TRUE SMBUS_SMC_5_G3_SCL 39 42 J5100 (LPC + SPI CONN) TBT_B_D2R_C_N<0> 70 76 HDMI_IG_DATA_C_N<2..0> 9 36 78 MAKE_BASE=TRUE
I1961
TRUE
I1851
TRUE
I1880
TRUE 19 TP_PCI_CLK33M_OUT3 TRUE NC_PCI_CLK33M_OUT3 USB3_EXTA_RX_P
TRUE SMBUS_SMC_5_G3_SDA 39 42 TRUE PPVOUT_S0_LCDBKLT 67 71 80 2 TP needed TBT_B_D2R_C_P<1> 70 76 MAKE_BASE=TRUE I1962
TRUE
TRUE PP3V42_G3H 7 8
I1853
TRUE TRUE NC_ISNS_LCDBKLTN 80 USB3_EXTA_RX_N
TRUE SYS_DETECT_L_R I1601 TBT_B_D2R_C_N<1> 70 76
I1987
MAKE_BASE=TRUE
I1963
TRUE
TRUE LED_RETURN_6 7 67 71 TRUE PP5V_S0 7 8
I1854 TRUE TRUE NC_ISNS_LCDBKLTP 80
I1658 I1603 TBT_B_D2R_P<0> 33 70 76
I1986
MAKE_BASE=TRUE
TRUE LED_RETURN_5 7 67 71 TRUE LPC_CLK33M_LPCPLUS 25 41 75 I1852
TRUE TRUE NC_ISNS_WLANN 80
TRUE SYSDET1 I1659 I1602 TBT_B_D2R_N<0> 33 70 76
I1985
MAKE_BASE=TRUE USB3_EXTA_TX_C_P
I1818
TRUE LED_RETURN_4 7 67 71 TRUE LPC_AD<0> 7 17 39 41 75
I1855
TRUE TRUE PCIE_CLK100M_ENET_P 7 17 36 75 TRUE NC_ISNS_WLANP 80
I1964
TRUE
TRUE SYSDET_3_4 56
I1660 I1604
TBT_B_D2R_P<1> 33 70 76
I1542 I1988
MAKE_BASE=TRUE USB3_EXTA_TX_C_N
I1817
I1856
TRUE TRUE PCIE_CLK100M_ENET_N 7 17 36 75
I1966
TRUE
I1661 I1606
TBT_B_D2R_N<1> 33 70 76
I1543
TRUE NC_ISNS_LCD_PANELN 67 80 USB3_EXTA_TX_N
I1857
TRUE TRUE USB3_EXTB_TX_C_P 36 79 I1989
MAKE_BASE=TRUE
I1965
TRUE
I1662 I1605 I1545
TRUE NC_ISNS_LCD_PANELP 67 80 USB3_EXTA_RX_N
I1663 TRUE LED_RETURN_1 67 71 I1607 TRUE LPC_AD<3> 7 17 39 41 75 I1547 TRUE USB3_EXTB_TX_C_N 36 79 I1990
TRUE
J6801 (2 MIC CONN)
LCD_HPD_CONN SPI_ALT_MOSI PCIE_AP_D2R_P PCH ALIASES
TRUE 67 TRUE 41 TRUE 7 17 36 75
I1664 I1609
7 NC_LPC_DREQ0_L TP_LPC_DREQ0_L 7 17
TRUE CON_DMIC_PWR 55 TRUE LPCPLUS_GPIO 20 41 TRUE PCIE_AP_D2R_N 7 17 36 75 MAKE_BASE=TRUE TRUE
I1974 I1608 USB3_EXTB_RX_RC_P
TRUE CON_DMIC_SDA1 55 TRUE DP_INT_AUX_P 67 79 TRUE LPCPLUS_RESET_L 25 41 TRUE PCIE_AP_R2D_P 36 75 NC_LPC_DREQ1_L TP_LPC_DREQ1_L I1968
TRUE
I1975 I1669 I1611
MAKE_BASE=TRUE TRUE USB3_EXTB_RX_RC_N
TRUE CON_DMIC_CLK 55 TRUE DP_INT_AUX_N 67 79 TRUE SMC_TDO 39 40 41 TRUE PCIE_AP_R2D_N 36 75 24 TP_XDP_PCH_HOOK4 TRUE NC_XDP_PCH_HOOK4 I1970
TRUE
I1976 I1668 I1610
MAKE_BASE=TRUE 17 TP_CLINK_CLK TRUE NC_CLINK_CLK USB3_EXTB_RX_P
TRUE TP_SMC_TRST_L 41 24 TP_XDP_PCH_HOOK5 TRUE NC_XDP_PCH_HOOK5 MAKE_BASE=TRUE I1969
TRUE
I1612
MAKE_BASE=TRUE 17 TP_CLINK_DATA TRUE NC_CLINK_DATA USB3_EXTB_RX_N
TRUE TP_SMC_MD1 41 24 TP_XDP_PCH_OBSFN_B<0> TRUE NC_XDP_PCH_OBSFN_B<0> MAKE_BASE=TRUE
I1971
TRUE
J3401 & J3402 (AIRPORT/BT/CAMERA CONN) I1614
MAKE_BASE=TRUE 17 TP_CLINK_RESET_L TRUE NC_CLINK_RESET_L
I1613 TRUE SMC_TX_L 39 40 41 24 TP_XDP_PCH_OBSFN_B<1> TRUE NC_XDP_PCH_OBSFN_B<1> MAKE_BASE=TRUE
MAKE_BASE=TRUE
TRUE PCIE_CLK100M_AP_CONN_P 36 78
I1616 TRUE SPI_ALT_MISO 41 24 TP_XDP_PCH_OBSFN_A<0> TRUE NC_XDP_PCH_OBSFN_A<0>
A TRUE
TRUE
PCH_VSS_NCTF<19>
PCH_VSS_NCTF<19>
7
7
TRUE
TRUE
PCIE_CLK100M_AP_CONN_N 36
AP_CLKREQ_Q_L 7 36
78
I1615 TRUE
TRUE
LPC_FRAME_L
SPIROM_USE_MLB
7 17 39 41 75
20 41 50
24
24
TP_XDP_PCH_OBSFN_A<1>
TP_XDP_PCH_OBSFN_D<0>
MAKE_BASE=TRUE
TRUE NC_XDP_PCH_OBSFN_A<1>
MAKE_BASE=TRUE
TRUE NC_XDP_PCH_OBSFN_D<0> SYNC_MASTER=MASTER SYNC_DATE=MASTER A
I1617 PAGE TITLE
MAKE_BASE=TRUE
TRUE PCIE_WAKE_L TRUE PM_CLKRUN_L TP_XDP_PCH_OBSFN_D<1> TRUE NC_XDP_PCH_OBSFN_D<1>
J4600 (LEFT USB CONN)
TRUE AP_RESET_CONN_L
7 18 36
7 36
I1618
TRUE SPI_ALT_CLK
7 18 39 41
41
24
24 TP_XDP_PCH_TRST_L MAKE_BASE=TRUE
TRUE NC_XDP_PCH_TRST_L Functional / ICT Test
TRUE PP5V_S3_LTUSB_A_F 38
I1619
MAKE_BASE=TRUE DRAWING NUMBER SIZE
I1584
TRUE PP3V3_WLAN_F 7 36 40 80 TRUE SPI_ALT_CS_L 41
I1586 TRUE USB_LT1_N 38 74
TRUE PP5V_S3_ALSCAMERA_F 7 32
I1621
TRUE LPC_SERIRQ 17 39 41 21 TP_1V05_S0_PCH_VCCAPLLEXP NC_1V05_S0_PCH_VCCAPLLEXP
TRUE Apple Inc. <SCH_NUM> D
TRUE USB_LT1_P 38 74
I1620
MAKE_BASE=TRUE REVISION
I1585
TRUE SMBUS_SMC_2_S3_SDA 7 39 42 77 TRUE LPC_PWRDWN_L 51 TP_AUD_CODEC_MICBIAS TRUE NC_AUD_CODEC_MICBIAS
FUNC_TEST TRUE SMBUS_SMC_2_S3_SCL 7 39 42 77
I1622
TRUE SMC_TDI
18 25 39 41
39 40 41
MAKE_BASE=TRUE
R
<E4LABEL>
TRUE GND I1623
51 TP_AUD_MIC_INRP TRUE NC_AUD_MIC_INRP NOTICE OF PROPRIETARY PROPERTY: BRANCH
TRUE USB_CAMERA_CONN_P 32 74 TRUE SMC_TCK 39 40 41 MAKE_BASE=TRUE
TRUE GND
TRUE USB_CAMERA_CONN_N 32 74
I1624
TRUE SMC_RESET_L 39 40 41 57
51 TP_AUD_MIC_INRN TRUE
MAKE_BASE=TRUE
NC_AUD_MIC_INRN THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
TRUE GND I1626
TRUE SMC_ROMBOOT 40 41 51 7 AUD_SPDIF_IN TRUE AUD_SPDIF_IN 7 51
6 TPs
I1625
TRUE SMC_RX_L 39 40 41 71 TP_BKL_FAULT
MAKE_BASE=TRUE
TRUE NC_BKL_FAULT
7 OF 132
I1627
MAKE_BASE=TRUE SHEET
TRUE SMC_TMS 39 40 41 17 7 TP_LPC_DREQ0_L TRUE NC_LPC_DREQ0_L III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I1628
MAKE_BASE=TRUE IV ALL RIGHTS RESERVED 7 OF 80
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
57 56 =PPBUS_G3H PPBUS_G3H 7 59 =PP3V3_S5_REG PP3V3_S5 7 78 1.8V/1.5V/1.2V/1.05V Rails
MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 MM VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE 64 =PP1V8_S0_REG PP1V8_S0
G3H Rails VOLTAGE=12.8V MIN_LINE_WIDTH=0.6 MM
MAKE_BASE=TRUE 2A max supply MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V 56 =PP18V5_DCIN_ISOL PPDCIN_G3H_ISOL
=PPBUS_S0_LCDBKLT 71 =PP3V3_S0_P3V3S0FET 65 MAKE_BASE=TRUE MIN_LINE_WIDTH=0.3 MM VOLTAGE=18.5V
MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
=PPVIN_S5_HS_OTHER_ISNS_R 44 =PP3V3_S3_P3V3S3FET 65
=PP1V8R1V5_S0_PCH_VCCVRM 21 =PPDCIN_S5_CHGR_ISOL 57
=PPVIN_S5_HS_COMPUTING_ISNS_R 44 =PP3V3_S4_TBTAPWRSW 69
=PP1V8_S0_AUDIO =PPDCIN_S5_VSENSE 44
=PP3V3_S4_TBTBPWRSW 70
=PP1V8_S0_CPU_VCCPLL 15
=PPVIN_SW_TBTBST 35 =PP3V3_S4_P3V3S4FET 65
=PP1V8_S0_PCH_VCC_DFTERM 20 21 23
=PPBUS_S0_VSENSE 44 =PP3V3_S5_CPU_VCCDDR 27
=PPVDDIO_S0_SBCLK 25
=PPBUS_G3H_T25_R =PP3V3_S5_P3V3SUSFET 65
=PP3V3_S5_PCH 18
44 =PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS 15 13 =PP1V8_S0_CPU_VCCPLL_R PP1V8_S0_CPU_VCCPLL_R
MIN_LINE_WIDTH=0.6 mm =PP3V3_S5_PCHPWRGD 66 MIN_LINE_WIDTH=0.5 MM VOLTAGE=1.8V
MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
D VOLTAGE=12.8V
MAKE_BASE=TRUE
=PP3V3_S5_PCH_GPIO
=PP3V3_S5_PCH_VCCDSW
20
21 23
60 =PPDDR_S3_REG PP1V5R1V35_S3
MIN_LINE_WIDTH=0.2 mm
D
=PPVIN_S0_CPUIMVP 61 62 MIN_NECK_WIDTH=0.17 mm
=PP3V3_S5_PWRCTL 66 VOLTAGE=1.35V
=PPVIN_S3_DDRREG 60 MAKE_BASE=TRUE
=PP3V3_S5_SMCBATLOW 40
=PPVIN_S0_CPUVCCIOS0 63
=PP3V3_S5_SYSCLK 25
=PPVIN_S0_CPUAXG 62 =PPDDR_S3_MEMVREF 31
=PP3V3_S5_VMON 66
=PPVIN_S0_VCCSAS0 58 =PPVIN_S3_P1V5S3RS0_FET 65
=PP3V3_S5_XDP 24
=PP3V3_S5_P1V5S0 =PPVIN_S0_DDRREG_LDO 60
44 =PPVIN_S5_HS_OTHER_ISNS PPVIN_S5_HS_OTHER_ISNS
MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.8V =PPVIN_S3_MEM_ISNS_R 43
MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE
=PPVIN_S5_P5VP3V3 59
56 =PP18V5_DCIN_CONN PPDCIN_G3H 7
VOLTAGE=18.5V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25
MAKE_BASE=TRUE
MM
65 =PP3V3_S3_FET PP3V3_S3 7
=PPDCIN_S5_CHGR 57 MIN_LINE_WIDTH=0.50MM VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20MM MAKE_BASE=TRUE
56 =PP3V42_G3H_REG PP3V42_G3H 7 =PP3V3_S3_ISNS 43

VOLTAGE=3.42V
MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE =PP3V3_S3_MEMRESET 27 43 =PPVIN_S3_MEM_ISNS PP1V5R1V35_MEM
=PP3V3_S5_LPCPLUS 41 =PP3V3_S3_PCH_GPIO 19 25 MIN_NECK_WIDTH=0.17 mm
VOLTAGE=1.35V
=PP3V3_S5_SMC 39 40 =PP3V3_S3_RIO 36 MAKE_BASE=TRUE
=PP3V42_G3H_CHGR 57 66 =PP3V3_S3_SMBUS_SMC_2_S3 42 =PP1V5R1V35_S3_MEM_A 28
=PP3V42_G3H_ONEWIREPROT 56 =PP3V3_S3_SMBUS_SMC_3 42 =PP1V5R1V35_S3_MEM_B 29
=PP3V42_G3H_PWRCTL 66 =PP1V5_S3_MEMRESET 27
=PP3V42_G3H_BMU
=PP3V42_G3H_SMBUS_SMC_5 42 =PP3V3_S3_USBMUX 26
54 =PP3V42_G3H_AUDIO
=PP3V42_G3H_SMCUSBMUX 38 =PP3V3_S3_USB_HUB 26 65 =PP1V5_S3RS0_FET PP1V5_S3RS0_CPUDDR 78
=PP3V42_G3H_TDM MIN_LINE_WIDTH=0.6 MM
=PP3V42_G3H_TPAD 47 =PP3V3_S3_USB_RESET 26 MIN_NECK_WIDTH=0.2 MM
40 =PP3V42_S3_HALL VOLTAGE=1.5V
=PPVIN_S5_SMCVREF 40 =PP3V3_S3_VREFMRGN 31 MAKE_BASE=TRUE
For PCH RTC Power =PPVBAT_G3_SYSCLK 25 =PP3V3_S3_WLAN 36 66 =PP1V5_S3RS0_VMON 66
=PP3V3_S3_GYRO =PP1V5R1V35_S3_CPU_VCCDDR 11
C 25 =PPVRTC_G3_OUT PPVRTC_G3H
MIN_LINE_WIDTH=0.3
VOLTAGE=3.42V
MM
MAKE_BASE=TRUE
=PP3V3_S3_SMS
49
49
64 =PP1V5_S0_REG PP1V5_S0 7
13 16 27
C
=PP3V3_S3_SDBUF 25 MIN_LINE_WIDTH=0.6 MM
5V Rails =PPVRTC_G3_PCH 17 18 21 MIN_NECK_WIDTH=0.15 MM
=PP3V3_S3_CAMERA VOLTAGE=1.5V
59 =PP5V_S5_LDO PP5V_S5 7 MAKE_BASE=TRUE
=PP3V3_S3_P1V2S3
VOLTAGE=5V
MAKE_BASE=TRUE
=PP3V3_S3_P1V8S3 =PP1V5_S0_AUDIO 51
TBT Rails (off when no cable)
=PP5V_S5_P1V5S3RS0FET 65 PPVIN_SW_TBTBST 35
=PP3V3_S3_BT 36 =PP3V3R1V5_S0_PCH_VCCSUSHDA 21 23 25
I1709
=PP5V_S5_P5VSUSFET 65 MIN_NECK_WIDTH=0.25 mm
=PP1V5_S0_RDRVR 36 VOLTAGE=12.8V
=PP5V_S5_TPAD 47
65 =PP5V_SUS_FET PP5V_SUS 60 31 =PPVTT_S3_DDR_BUF PPVTTDDR_S3 7 35 =PP15V_TBT_REG PP15V_TBT

VOLTAGE=5V 65 =PP3V3_S0_FET PP3V3_S0 7 78 MIN_LINE_WIDTH=0.3 MM MIN_LINE_WIDTH=0.4 mm
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.5 MM VOLTAGE=3.3V MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.075 mmMAKE_BASE=TRUE VOLTAGE=0.675V VOLTAGE=15V
=PP5V_SUS_PCH 23 MAKE_BASE=TRUE MAKE_BASE=TRUE
=PP3V3_S0_AUDIO 51 55
=PPHV_SW_TBTAPWRSW 69
59 =PP5V_S4_REG PP5V_S4 7 =PP3V3_S0_AUDIO_DIG 51 54
MIN_LINE_WIDTH=0.5 mmVOLTAGE=5V 60 =PPVTT_S0_DDR_LDO PP0V75_S0_DDRVTT 7 =PPHV_SW_TBTBPWRSW 70
MIN_NECK_WIDTH=0.2 mmMAKE_BASE=TRUE =PP3V3_S0_BKL_VDDIO 71 MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm
=PP5V_S0_LCD 67 =PP3V3_S0_CPUTHMSNS 45 VOLTAGE=0.675V
MAKE_BASE=TRUE 35 =PP3V3_TBTLC_FET PP3V3_TBTLC
=PP5V_S3_LTUSB 38 =PP3V3_S0_P1V5S0 64 MIN_LINE_WIDTH=0.4 MM
=PP0V75_S0_MEM_VTT_A 30 MIN_NECK_WIDTH=0.2 MM
=PP5V_S4_P5VS0FET 65 =PP3V3_S0_P1V8S0 64 VOLTAGE=3.3V
=PP0V75_S0_MEM_VTT_B 30 MAKE_BASE=TRUE
=PP5V_S4_P5VS3FET 65 =PP3V3_S0_BKLI2C
=PPVTT_S0_VTTCLAMP 27 =PP3V3_TBT_PCH_GPIO 8 17 20
=PP5V_S4_AUDIO 55 =PP3V3_S0_DDCMUX 68
=PP3V3_TBTLC_RTR 33 34 35
=PP5V_S4_RIO 36 =PP3V3_S0_FAN_LT 46 64 =PP1V05_SUS_LDO PP1V05_SUS
MIN_LINE_WIDTH=0.4 MM =PPVDDIO_TBT_CLK 25
=PP5V_S4_P1V05TBTS0 64 =PP3V3_S0_FAN_RT 46 MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V =PP3V3_TBT_PCH_GPIO 8 17 20
=PP5V_S4_TPAD 47 =PP3V3_S0_GPUTHMSNS 45 MAKE_BASE=TRUE
=PP3V3_S0_HS_ISNS =PP1V05_SUS_PCH_JTAG 24
=PP3V3_S0_IMVPISNS 43 63 =PPCPUVCCIO_S0_REG PP1V05_S0 7

65 =PP5V_S3_FET PP5V_S3 7 MIN_LINE_WIDTH=0.6 MM 80 64 =PP1V05_S0_P1V05TBTREG_R PP1V05_S0_P1V05TBTREG_R
MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V =PP3V3_S0_ISNS 43 80 MIN_NECK_WIDTH=0.15 MM MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE =PP3V3_S0_CPU_VCCIO_SEL VOLTAGE=1.05V MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE
13 MAKE_BASE=TRUE
=PP5V_S3_ISNS
B =PP5V_S3_ALSCAMERA
=PP5V_S3_DDRREG
32
=PP3V3_S0_LCD
=PP3V3_S0_P3V3TBTFET
67
35
=PP1V05_S0_CPU_VCCIO
=PPVCCIO_S0_XDP
10 11 13 15
24
80 35 =PP1V05_S0_P1V05TBTREG PP1V05_S0_P1V05TBTREG
VOLTAGE=1.05V
MAKE_BASE=TRUE
B
60
=PP3V3_S0_PCH 17 23 =PPVCCIO_S0_CPUIMVP 61 =PP1V05_TBTLC_RTR 34
=PP5V_S3_DEBUG_ADC_AVDD
=PP3V3_S0_PCH_GPIO 17 18 19 20 25 35 =PPVCCIO_S0_SMC 40 =PP1V05_TBTLC 35
=PP5V_S3_DEBUG_ADC_DVDD
=PP3V3_S0_PCH_VCC3_3_CLK 23 =PP1V05_S0_VMON 66 35 =PP1V05_TBTCIO_FET PP1V05_TBTCIO
=PP5V_S3_DEBUG_ISNS MIN_LINE_WIDTH=0.4 mm
=PP3V3_S0_PCH_VCC3_3_GPIO =PP1V05_S0_RMC MIN_NECK_WIDTH=0.2 mm
=PP5V_S3_MEMRESET 27 VOLTAGE=1.05V
=PP3V3_S0_PCH_VCC3_3_HVCMOS =PP1V05_S0_PCH_VCCIO_PLLPCIE MAKE_BASE=TRUE
=PP3V3_S0_PCH_VCC3_3_PCI =PP1V05_S0_PCH_VCCADPLL 23 =PP1V05_TBTCIO_RTR 34
=PP3V3_S0_PCH_VCC3_3_SATA =PP1V05_S0_PCH_VCCIO 21 23
65 =PP5V_S0_FET PP5V_S0 7
MIN_LINE_WIDTH=0.4 MM VOLTAGE=5V =PP3V3_S0_PCH_VCCADAC 23 =PP1V05_S0_PCH_VCCIO_PCIE 18 Chipset "VCore" Rails
=PP3V3_S0_PCH_VCC3_3 21 23 =PP1V05_S0_PCH_VCCIO_SATA 17 23 62 =PPVCORE_S0_CPU_REG PPVCORE_S0_CPU 7
=PP5V_S0_AUDIO_XW 9 MAKE_BASE=TRUE
51 =PP5V_S0_AUDIO =PP3V3_S0_PWRCTL 9 66 =PP1V05_S0_PCH_VCCIO_CLK 8 MIN_NECK_WIDTH=0.25 VOLTAGE=1.25V
MM
=PP5V_S0_BKL 71
=PP3V3_S0_RSTBUF 25 =PP1V05_S0_PCH_VCCIO_USB =PPVCORE_S0_CPU 10 13 15 43
=PP5V_S0_CPUIMVP 61 62
=PP3V3_S0_SATAMUX =PP1V05_S0_PCH_VCC_CORE 21 23
=PP5V_S0_CPUVCCIOS0 63 62 =PPVCORE_S0_AXG_REG PPVCORE_S0_AXG
=PP3V3_S0_SB_PM 25 66 =PP1V05_S0_PCH_VCCASW 21 23 MIN_LINE_WIDTH=0.6 MAKE_BASE=TRUE
MM
=PP5V_S0_FAN_LT 46 MIN_NECK_WIDTH=0.2 VOLTAGE=1.05V
MM
=PP3V3_S0_SMBUS_PCH 42 =PP1V05_S0_PCH_VCCIO_CLK 8
=PP5V_S0_FAN_RT 46 =PPVCORE_S0_CPU_VCCAXG 10 13 16 43
=PP3V3_S0_SMBUS_SMC_0_S0 42 =PP1V05_S0_PCH_VCCDIFFCLK 17 21 23
=PP5V_S0_KBDLED 48
=PP3V3_S0_SMBUS_SMC_1_S0 42 =PP1V05_S0_PCH 17 23 16 13 =PP1V5_S3_CPU_VCCDQ PP1V5_S3_CPU_VCCDQ
=PP5V_S0_LPCPLUS 41 MIN_LINE_WIDTH=0.6 MAKE_BASE=TRUE
MM
=PP3V3_S0_SSD 37 =PP1V05_S0_PCH_VCCSSC 21 23 MIN_NECK_WIDTH=0.2 VOLTAGE=1.5V
MM
=PP5V_S0_PCH 23 25
=PP3V3_S0_SYSCLK 25 =PP1V05_S0_PCH_V_PROC_IO 21 23
=PP5V_S0_HDD 37 15 13 =PP1V05_S0_CPU_VCCPQE PP1V05_S0_CPU_VCCPQE
=PP3V3_S0_TBTI2C =PP1V05_S0_PCH_VCCIO_PLLUSB MIN_LINE_WIDTH=0.6 VOLTAGE=1.05V
MM
=PP5V_S0_RMC MIN_NECK_WIDTH=0.2 MAKE_BASE=TRUE
MM
=PP3V3_S0_TBTPWRCTL 35 =PP1V05_S0_PCH_VCC_DMI 21 23
=PP5V_S0_VCCSAS0 58 80 58 =PPVCCSA_S0_REG PPVCCSA_S0_REG
=PP3V3_S0_HDMI 36 =PP1V05_S0_PCH_VCCIO_PLLFDI MIN_LINE_WIDTH=0.6 VOLTAGE=0.9V
MM
3.3V Rails =PP5V_S0_VMON 66 MIN_NECK_WIDTH=0.2 MAKE_BASE=TRUE
MM
=PP3V3_S0_TPAD 48 =PP1V05_S0_PCH_VCCDMI_FDI
=PPVCCSA_S0_CPU 13 16
65 =PP3V3_S4_FET PP3V3_S4 7 =PP3V3_S0_VMON 66
MIN_LINE_WIDTH=0.6 MM VOLTAGE=3.3V
A 35 34 33
36
=PP3V3_S4_TBT
=PP3V3_S4_RIO
=PP3V3_S4_TPAD 47
=PP3V3_S0_XDP
=PP3V3_S0_DDR3THMSNS
24
=PP3V3_S4_SMC 25 36 40
PAGE TITLE
=PP3V3_S0_SPKRTHMSNS
=PP3V3_S4_BT 36
=PP3V3_S0_HS_COMPUTING_ISNS 44
Power Aliases
=PP3V3_S0_HS_OTHER_ISNS DRAWING NUMBER SIZE
65 =PP3V3_SUS_FET PP3V3_SUS
MIN_LINE_WIDTH=0.6 MM VOLTAGE=3.3V =PP3V3_S0_PCH_STRAPS
44
20 Apple Inc. <SCH_NUM> D

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE REVISION
=PPBUS_G3H_T25 PPBUS_G3H_T25_PWR R
=PP3V3_SUS_P1V05SUSLDO 64 MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4
MIN_NECK_WIDTH=0.2
MM
VOLTAGE=12.8V
MM
<E4LABEL>
=PP3V3_SUS_PCH_VCCSUS 21 23 NOTICE OF PROPRIETARY PROPERTY: BRANCH
=PP3V3_SUS_PCH
23
=PP3V3_SUS_PCH_VCCSUS_GPIO Backlight Rails THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
=PP3V3_SUS_PCH_GPIO 17 18 19 20 80 =PPBUS_SW_BKL PPBUS_SW_BKL THE POSESSOR AGREES TO THE FOLLOWING: PAGE
=PP3V3_SUS_ROM MIN_LINE_WIDTH=0.5
MAKE_BASE=TRUE
MM
23 21
50
=PP3V3_SUS_PCH_VCC_SPI
=PP3V3_SUS_PCH_VCCSUS_USB 21 23 MIN_NECK_WIDTH=0.25
VOLTAGE=12.6V
MM I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
8 OF 132
=PP3V3_SUS_CNTRL 66 PPBUS_S0_LCDBKLT_PWR 71
=PP3V3_SUS_SMC 40 IV ALL RIGHTS RESERVED 8 OF 80
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
eDP signals
Frame Holes
ZT0940 CPU signals
79 67 DP_INT_AUX_C_P TP_EDP_AUX_P 10
4P5R2P3-3P5B MAKE_BASE=TRUE
27 MEMVTT_EN =DDRVTT_EN 27 60
1 79 67 DP_INT_AUX_C_N TP_EDP_AUX_N 10 MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_INT_ML_C_P<3..0> TP_EDP_TX_P<3..0>
ZT0960 79 67
MAKE_BASE=TRUE
10
T29 Signals Through PEG
NC_CPU_THERMDN CPU_THERMD_N
4P5R2P3-3P5B 79 67 DP_INT_ML_C_N<3..0> TP_EDP_TX_N<3..0> 10 MAKE_BASE=TRUE NO_TEST=TRUE
10 78
1 MAKE_BASE=TRUE
75 33 7 PCIE_TBT_D2R_P<3..0> =PEG_D2R_P<11..8> 10 NC_CPU_THERMDP CPU_THERMD_P 10 78
MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE
75 33 7 PCIE_TBT_D2R_N<3..0> =PEG_D2R_N<11..8> 10
MAKE_BASE=TRUE
NC_LCD_FSS LCD_FSS 67
Bosses for limiting deflection 75 33 7 PCIE_TBT_R2D_C_P<3..0> =PEG_R2D_C_P<11..8> 10 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
SH0910 APN:860-1557 PCIE_TBT_R2D_C_N<3..0> =PEG_R2D_C_N<11..8>
D
D 2.8OD1.2ID-2.25H-SM-D1 71 7 LCD_BKLT_PWM
MAKE_BASE=TRUE
LVDS_IG_BKL_PWM 18
75 33 7
MAKE_BASE=TRUE
10
1
71 LCD_BKLT_EN LVDS_IG_BKL_ON 18 SD_PWR_EN_PCH ENET_LOW_PWR_PCH 20 24 25
MAKE_BASE=TRUE MAKE_BASE=TRUE
67 LCD_PWR_EN LVDS_IG_PANEL_PWR 18 36 7 SD_PWR_EN ENET_LOW_PWR 25
SH0911 MAKE_BASE=TRUE MAKE_BASE=TRUE
2.8OD1.2ID-2.25H-SM-D1 TP_FW_PWR_EN FW_PWR_EN 25 NC_PCIE_CLK100M_SSDN PCIE_CLK100M_SSD_N 7 17 75
MAKE_BASE=TRUE MAKE_BASE=TRUE TRUE
1
1 1 NC_PCIE_CLK100M_SSDP PCIE_CLK100M_SSD_P 7 17 75
SH0950 SH0951 MAKE_BASE=TRUE TRUE
SH0912 SM SM NC_PCIE_CLK100M_FWN
MAKE_BASE=TRUE TRUE
PCIE_CLK100M_FW_N 7 17 75
2.8OD1.2ID-2.25H-SM-D1
NC_PCIE_CLK100M_FWP PCIE_CLK100M_FW_P 7 17 75
1 SHLD-D1-USB MAKE_BASE=TRUE TRUE
SHLD-D1-MLB-T29 Unused PEG signals
NC_PCIE_FW_D2RN PCIE_FW_D2R_N 17
NC_PEG_D2RP<15..12> =PEG_D2R_P<15..12> 10 MAKE_BASE=TRUE NO_TEST=TRUE
SH0913 MAKE_BASE=TRUE NO_TEST=TRUE
NC_PCIE_FW_D2RP PCIE_FW_D2R_P
2.8OD1.2ID-2.25H-SM-D1 D1 THERMAL MODULE STANDOFF (860-1439) NC_PEG_D2RN<15..12> =PEG_D2R_N<15..12> 10 MAKE_BASE=TRUE NO_TEST=TRUE
17
MAKE_BASE=TRUE NO_TEST=TRUE
1 NC_PCIE_FW_R2D_CN PCIE_FW_R2D_C_N
SH0920 SH0921 NC_PEG_R2D_CP<15..12>
=PEG_R2D_C_P<15..12> 10 MAKE_BASE=TRUE NO_TEST=TRUE
17
STDOFF-4.5OD2.15H-SM STDOFF-4.5OD2.15H-SM NC_PCIE_FW_R2D_CP PCIE_FW_R2D_C_P 17

NC_PEG_R2D_CN<15..12> =PEG_R2D_C_N<15..12> 10 MAKE_BASE=TRUE NO_TEST=TRUE
1 1 CR SFF DG v1p0 Table 3-56 mapping for HDMI MAKE_BASE=TRUE NO_TEST=TRUE
Unused GPU signals
78 36 7 HDMI_IG_CLK_C_P TP_DP_IG_B_MLP<3> 18
MAKE_BASE=TRUE
NC_PEG_D2RP<7..0> =PEG_D2R_P<7..0> 10 Unused SATA ODD Signals
78 36 7 HDMI_IG_CLK_C_N TP_DP_IG_B_MLN<3> 18 MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
SH0926 SH0927 NC_PEG_D2RN<7..0>
MAKE_BASE=TRUE
NO_TEST=TRUE
=PEG_D2R_N<7..0> 10
NC_SATA_ODD_D2RN SATA_ODD_D2R_N 17
STDOFF-4.5OD2.15H-SM STDOFF-4.5OD2.15H-SM MAKE_BASE=TRUE NO_TEST=TRUE
78 36 7 HDMI_IG_DATA_C_P<2..0> TP_DP_IG_B_MLP<0..2> 18 NC_PEG_R2D_CP<7..0> =PEG_R2D_C_P<7..0> 10
1 1
TH0900 MAKE_BASE=TRUE MAKE_BASE=TRUE
NO_TEST=TRUE NC_SATA_ODD_D2RP SATA_ODD_D2R_P 17
TH-NSP 78 36 7 HDMI_IG_DATA_C_N<2..0> TP_DP_IG_B_MLN<0..2> 18 NC_PEG_R2D_CN<7..0> =PEG_R2D_C_N<7..0> 10
1 MAKE_BASE=TRUE MAKE_BASE=TRUE
NO_TEST=TRUE NC_SATA_ODD_R2D_CN SATA_ODD_R2D_C_N 17
SL-1.1X0.5-1.4x0.8 MAKE_BASE=TRUE NO_TEST=TRUE
HDMI_IG_DDC_CLK DPA_IG_DDC_CLK
C D1 BMU MODULE STANDOFFS
36 7
MAKE_BASE=TRUE
HDMI_IG_DDC_DATA DPA_IG_DDC_DATA
18
NC_DPA_IG_AUX_CHP DPA_IG_AUX_CH_P
NC_SATA_ODD_R2D_CP
SATA_ODD_R2D_C_P 17 C
TH0903 APN:862-0118 MAKE_BASE=TRUE
18
18
SH0928 SH0963 TH-NSP

1 HDMI_HPD DPA_IG_HPD NC_DPA_IG_AUX_CHN DPA_IG_AUX_CH_N
STDOFF-4.5OD1.73H-SM STDOFF-4.5OD2.33H-SM 36
MAKE_BASE=TRUE
18
18
SL-1.1X0.5-1.4x0.8
APN: 860-1490 1 1 Unused Memory Signals
TH0904 NC_PEG_CLK100MN PEG_CLK100M_N 7 17 75
TH-NSP MAKE_BASE=TRUE NO_TEST=TRUE NC_MEM_A_CLKP<1> MEM_A_CLK_P<1> 12
1 MAKE_BASE=TRUE NO_TEST=TRUE
SH0963 is BMU standoff with flange. 860-1534 APN:998-3975
SL-1.1X0.45-1.4x0.75
NC_PEG_CLK100MP
PEG_CLK100M_P 7 17 75
NC_MEM_A_CLKN<1> MEM_A_CLK_N<1> 12
UNUSED USB SIGNALS
TH0900 for upper TBT can gnd slot TH0905 79 33 DP_TBTSNK0_AUXCH_C_P
MAKE_BASE=TRUE
DPB_IG_AUX_CH_P 18
NC_USB3_EXTC_TXP USB3_EXTC_TX_P 19
NC_MEM_B_CLKP<1>
MEM_B_CLK_P<1> 12
TH-NSP MAKE_BASE=TRUE NO_TEST=TRUE
1 79 33 DP_TBTSNK0_AUXCH_C_N DPB_IG_AUX_CH_N 18 NC_MEM_B_CLKN<1> MEM_B_CLK_N<1> 12
MAKE_BASE=TRUE NC_USB3_EXTC_TXN USB3_EXTC_TX_N 19 MAKE_BASE=TRUE NO_TEST=TRUE
TH0903 for lower TBT can gnd slot SL-1.1X0.45-1.4x0.75 MAKE_BASE=TRUE NO_TEST=TRUE
NC_USB3_EXTC_RXP USB3_EXTC_RX_P 19
79 33 DP_TBTSNK0_ML_C_P<3..0> TP_DP_IG_C_MLP<3..0> 18 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
TH0904,5 for USB can gnd slot 79 33 DP_TBTSNK0_ML_C_N<3..0> TP_DP_IG_C_MLN<3..0> 18
NC_USB3_EXTC_RXN
USB3_EXTC_RX_N 19
MAKE_BASE=TRUE
NC_USB_EXTCP USB_EXTC_P 19
68 DP_TBTSNK0_DDC_CLK DPB_IG_DDC_CLK 18 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_EXTCN USB_EXTC_N 19
68 DP_TBTSNK0_DDC_DATA DPB_IG_DDC_DATA 18 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB3_EXTD_TXP USB3_EXTD_TX_P 19
33 DP_TBTSNK0_HPD DPB_IG_HPD 18 MAKE_BASE=TRUE NO_TEST=TRUE
FAN BOSSES (4X 860-1327) MAKE_BASE=TRUE
NC_USB3_EXTD_TXN USB3_EXTD_TX_N 19
SH0922 SH0923 SH0924 SH0925 79 33 DP_TBTSNK1_AUXCH_C_P
MAKE_BASE=TRUE
TP_DP_IG_D_AUXP 18
NC_USB3_EXTD_RXP USB3_EXTD_RX_P
STDOFF-4.5OD1.8H-SM STDOFF-4.5OD1.8H-SM STDOFF-4.5OD1.8H-SM MAKE_BASE=TRUE NO_TEST=TRUE
19
STDOFF-4.5OD1.8H-SM 79 33 DP_TBTSNK1_AUXCH_C_N TP_DP_IG_D_AUXN 18
1 1 1 MAKE_BASE=TRUE NC_USB3_EXTD_RXN USB3_EXTD_RX_N 19
1 MAKE_BASE=TRUE NO_TEST=TRUE
NC_USB_EXTD_EHCIP USB_EXTD_EHCI_P 19
79 33 DP_TBTSNK1_ML_C_P<3..0> TP_DP_IG_D_MLP<3..0> 18 MAKE_BASE=TRUE NO_TEST=TRUE
B 79 33
MAKE_BASE=TRUE
DP_TBTSNK1_ML_C_N<3..0> TP_DP_IG_D_MLN<3..0> 18
NC_USB_EXTD_EHCIN
USB_EXTD_EHCI_N 19 B
SH0932 SH0933 MAKE_BASE=TRUE
NC_USB_4N TP_USB_4N 19
POGO-2.3OD-5.5H-SM-LOW-FORCE
POGO-2.3OD-4.1H-SM-LOW-FORCE 68 DP_TBTSNK1_DDC_CLK TP_DP_IG_D_CTRL_CLK 18 MAKE_BASE=TRUE NO_TEST=TRUE
SM SM MAKE_BASE=TRUE
NC_USB_4P TP_USB_4P 19
68 DP_TBTSNK1_DDC_DATA TP_DP_IG_D_CTRL_DATA 18 MAKE_BASE=TRUE NO_TEST=TRUE
D1 POGO PINS (870-2451) 1 1 MAKE_BASE=TRUE
NC_USB_SDN TP_USB_SDN 19
33 DP_TBTSNK1_HPD TP_DP_IG_D_HPD 18 MAKE_BASE=TRUE NO_TEST=TRUE
MAKE_BASE=TRUE
NC_USB_SDP TP_USB_SDP 19
SH0934 SH0935 SH0936 SH0937 MAKE_BASE=TRUE NO_TEST=TRUE
POGO-2.3OD-5.5H-SM-LOW-FORCE POGO-2.3OD-5.5H-SM-LOW-FORCE NC_USB_WLANN TP_USB_WLANN 19
SM SM SM SM MAKE_BASE=TRUE NO_TEST=TRUE
NC_USB_WLANP TP_USB_WLANP 19
1 1 1 1 MAKE_BASE=TRUE NO_TEST=TRUE
NC_USB_BT_HSN TP_USB_BT_HSN 19
NC_USB_BT_HSP TP_USB_BT_HSP 19 66 8 =PP3V3_S0_PWRCTL
D1 ELIPTICAL SLOT HOLES NC_USB_12N TP_USB_12N 19
ZT0931 NC_USB_12P TP_USB_12P R09911
ZT0930 ZT0920 TH-NSP MAKE_BASE=TRUE NO_TEST=TRUE
19
10K
5%
Unused PGOOD signal
TH-NSP TH-NSP 1 NC_USB_13N TP_USB_13N 19 1/20W
1 1 MAKE_BASE=TRUE NO_TEST=TRUE MF
SL-3.9X2.3-4.2x2.6 NC_USB_13P TP_USB_13P 201 2
SL-3.9X2.3-4.2x2.6 SL-2.8X1.8-3.1x2.1 19
NC_PCH_GPIO64_CLKOUTFLEX0 TRUE TP_PCH_GPIO64_CLKOUTFLEX0 17
MAKE_BASE=TRUE CPUIMVP_AXG_PGOOD 61
MAKE_BASE=TRUE
MAKE_BASE=TRUE TP_P1V5S3RS0_RAMP_DONE P1V5S3RS0_RAMP_DONE 65
NC_PCH_GPIO67_CLKOUTFLEX3 TRUE TP_PCH_GPIO67_CLKOUTFLEX3 17 MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_DDRREG_PGOOD DDRREG_PGOOD 60
USB SIGNALS MAKE_BASE=TRUE
MLB_RAMCFG3
20
USB_BT_P USBHUB_DN1_P
A 20 MLB_RAMCFG2 RAMCFG3:L
74 36 7
MAKE_BASE=TRUE
26
SYNC_MASTER=D1_MLB_TEST SYNC_DATE=01/27/2012 A
RAMCFG2:L R09131 74 36 7 USB_BT_N
MAKE_BASE=TRUE
USBHUB_DN1_N 26
PAGE TITLE
MLB_RAMCFG1 1K
20
RAMCFG1:L R0912
1 5%
1/20W 8 =PP5V_S0_AUDIO_XW 74 47 USB_TPAD_P
MAKE_BASE=TRUE
USBHUB_DN2_P 26 Signal Aliases
20 MLB_RAMCFG0 1 1K MF DRAWING NUMBER SIZE
R0911 5% 201 2 USB_TPAD_N USBHUB_DN2_N
RAMCFG0:L
1K
1/20W
MF
GND
MIN_LINE_WIDTH=0.6MM
74 47
MAKE_BASE=TRUE
26

R0910 1 5%
1/20W
201 2 MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V
XW0902
SM
74 39 USB_SMC_P
MAKE_BASE=TRUE
USBHUB_DN3_P 26
R
REVISION
1K
5%
MF
201 2 1 2 PP5V_S0_AUDIO_AMP_L 53 74 39 USB_SMC_N USBHUB_DN3_N 26
<E4LABEL>
1/20W MIN_LINE_WIDTH=0.6MM MAKE_BASE=TRUE NOTICE OF PROPRIETARY PROPERTY: BRANCH
MF MIN_NECK_WIDTH=0.2MM
201 2
XW0903 VOLTAGE=5V 78 PU_USBHUB_DN4_P
MAKE_BASE=TRUE
USBHUB_DN4_P 26 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
SM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
Digital Ground 1 2 PP5V_S0_AUDIO_AMP_R 53
78 PU_USBHUB_DN4_N
MAKE_BASE=TRUE
USBHUB_DN4_N 26
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 9 OF 132
MIN_LINE_WIDTH=0.6MM II NOT TO REPRODUCE OR COPY IT
MIN_NECK_WIDTH=0.2MM III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
VOLTAGE=5V
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.
OMIT_TABLE OMIT_TABLE
CRITICAL R1010 CRITICAL MIN_LINE_WIDTH=0.3 MM
24.9 MIN_NECK_WIDTH=0.2 MM
72 CPU_PEG_COMP 1 2 =PP1V05_S0_CPU_VCCIO 8 10 11 13 15 VOLTAGE=0.75V
PLACE_NEAR=U1000.G3:12.7MM
72 18 7 DMI_S2N_N<0> M2 DMI_RX_0* U1000 PEG_ICOMPI G3 1% 72 24 10 CPU_CFG<0> B50 CFG_0 SA_DIMM_VREFDQ BE7 PPCPU_MEM_VREFDQ_A 31 72
IN 1/16W
IN OUT
72 18 7 DMI_S2N_N<1> P6 DMI_RX_1* IVY-BRIDGE PEG_ICOMPO G1 MF-LF 72 24 10 CPU_CFG<1> C51 CFG_1 SB_DIMM_VREFDQ BG7 PPCPU_MEM_VREFDQ_B 31 72
IN 402
IN OUT
72 18 7 IN DMI_S2N_N<2> P1 DMI_RX_2* 2C-35W PEG_RCOMPO G4 72 24 10 IN CPU_CFG<2> B54 CFG_2 MIN_LINE_WIDTH=0.3 MM
BGA U1000 RSVD_30 N42 MIN_NECK_WIDTH=0.2 MM
72 18 7 IN DMI_S2N_N<3> P10 DMI_RX_3* 72 24 10 IN CPU_CFG<3> D53 CFG_3 NC VOLTAGE=0.75V
(1 OF 9) PEG_RX_0* H22 =PEG_D2R_N<0> BGA RSVD_31 L42
9
NC
D 72 18 7 IN DMI_S2N_P<0> N3 DMI_RX_0 PEG_RX_1* J21 =PEG_D2R_N<1>
IN
IN 9
72 24 10
72 24 10
IN
IN
CPU_CFG<4>
CPU_CFG<5>
A51
C53
CFG_4
CFG_5
(5 OF 9)
RESERVED RSVD_32 L45
L47
NC D
72 18 7 DMI_S2N_P<1> P7 DMI_RX_1 PEG_RX_2* B22 =PEG_D2R_N<2> 9 RSVD_33 NC
IVY-BRIDGE
2C-35W
IN IN CPU_CFG<6> C55
72 24 10 IN CFG_6
72 18 7 IN DMI_S2N_P<2> P3 DMI_RX_2 PEG_RX_3* D21 =PEG_D2R_N<3> IN 9
H49 M13
72 24 10 IN CPU_CFG<7> CFG_7 RSVD_34 NC
72 18 7 IN DMI_S2N_P<3> P11 DMI_RX_3 PEG_RX_4* A19 =PEG_D2R_N<4> IN 9
A55 M14
72 24 IN CPU_CFG<8> CFG_8 RSVD_35 NC
PEG_RX_5* D17 =PEG_D2R_N<5> IN 9 PLACE_NEAR=U1000.H43:50.8MM H51 U14
72 18 7 OUT DMI_N2S_N<0> K1 DMI_TX_0* 72 24 IN CPU_CFG<9> CFG_9 RSVD_36 NC
PEG_RX_6* B14 =PEG_D2R_N<6> IN 9
PLACE_SIDE=TOP
K49 W14
72 18 7 OUT DMI_N2S_N<1> M8 DMI_TX_1* 72 24 IN CPU_CFG<10> CFG_10 RSVD_37 NC
PEG_RX_7* D13 =PEG_D2R_N<7> IN 9 =PPVCORE_S0_CPU 8 13 15 43
K53 P13
72 18 7 OUT DMI_N2S_N<2> N4 DMI_TX_2* 72 24 IN CPU_CFG<11> CFG_11 RSVD_38 NC
A11 =PEG_D2R_N<8>
DMI
PEG_RX_8* IN 9
F53
72 18 7 OUT DMI_N2S_N<3> R2 DMI_TX_3* =PPVCORE_S0_CPU_VCCAXG 8 13 72 24 IN CPU_CFG<12> CFG_12
PEG_RX_9* B10 =PEG_D2R_N<9> IN 9 NOSTUFF NOSTUFF 16 43
G53 RSVD_39 AT49NC
72 24 IN CPU_CFG<13> CFG_13
72 18 7 OUT DMI_N2S_P<0> K3 DMI_TX_0 PEG_RX_10* G8 =PEG_D2R_N<10> IN 9 R1064 1 1
R1070 L51 RSVD_40 K24 NC
72 24 IN CPU_CFG<14> CFG_14
72 18 7 OUT DMI_N2S_P<1> M7 DMI_TX_1 PEG_RX_11* A8 =PEG_D2R_N<11> IN 9 49.9 49.9 F51 AH2
1% 1% 72 24 IN CPU_CFG<15> CFG_15 RSVD_41 NC
72 18 7 OUT DMI_N2S_P<2> P4 DMI_TX_2 PEG_RX_12* B6 =PEG_D2R_N<12> IN 9 1/16W 1/16W
D52 AG13
MF-LF MF-LF 72 24 10 IN CPU_CFG<16> CFG_16 RSVD_42 NC
72 18 7 OUT DMI_N2S_P<3> T3 DMI_TX_3 PEG_RX_13* H8 =PEG_D2R_N<13> IN 9 402 402
L53 AM14
2 2 72 24 IN CPU_CFG<17> CFG_17 RSVD_43 NC
PEG_RX_14* E5 =PEG_D2R_N<14> IN 9 PLACE_NEAR=U1000.H45:50.8MM AM15
RSVD_44 NC
72 18 7 OUT FDI_DATA_N<0> U7 FDI0_TX_0* PEG_RX_15* K7 =PEG_D2R_N<15> IN 9
PLACE_SIDE=TOP
H43 VCC_VAL_SENSE
CPU_VCC_VALSENSE_P
72 18 OUT FDI_DATA_N<1> W11 FDI0_TX_1* Note. VOLTAGE=1.25V K43 VSS_VAL_SENSE RSVD_45 N50 NC
PEG_RX_0 K22 =PEG_D2R_P<0> IN 9 CPU_VCC_VALSENSE_N
FDI_DATA_N<2> W1
INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

72 18 OUT FDI0_TX_2* Note. VOLTAGE=0V
PEG_RX_1 K19 =PEG_D2R_P<1> IN 9
H45 VAXG_VAL_SENSE
72 18 OUT FDI_DATA_N<3> AA6 FDI0_TX_3* CPU_AXG_VALSENSE_P
PEG_RX_2 C21 =PEG_D2R_P<2> IN 9 Note. VOLTAGE=1.05V K45 VSSAXG_VAL_SENSE
FDI_DATA_N<4> W6 D19 =PEG_D2R_P<3> CPU_AXG_VALSENSE_N
72 18 7 OUT FDI1_TX_0* PEG_RX_3 IN 9 Note. VOLTAGE=0V
72 18 FDI_DATA_N<5> V4 FDI1_TX_1* PEG_RX_4 C19 =PEG_D2R_P<4> 9 TP_CPU_VCC_DIE_SENSE F48 VCC_DIE_SENSE
OUT IN
NOSTUFF NOSTUFF
72 18 OUT FDI_DATA_N<6> Y2 FDI1_TX_2* PEG_RX_5 D16 =PEG_D2R_P<5> IN 9
1 1 A4
FDI_DATA_N<7> AC9 C13 =PEG_D2R_P<6> R1065 R1071 CPU_THERMD_P H48 RSVD_6 DC_TEST_A4 TP_CPU_DC_TEST_A4
72 18 OUT FDI1_TX_3* PEG_RX_6 IN 9 78 9 OUT C4
D12 =PEG_D2R_P<7>
49.9 49.9
CPU_THERMD_N K48 RSVD_7 DC_TEST_C4 CPU_DC_TEST_C4_D3
PEG_RX_7 IN 9 1% 1% 78 9 OUT D3
72 18 7 OUT FDI_DATA_P<0> U6 FDI0_TX_0 1/16W 1/16W DC_TEST_D3
PEG_RX_8 C11 =PEG_D2R_P<8> IN 9 MF-LF NOTE: Intel does not recommend to use
MF-LF
BA19 D1
72 18 OUT FDI_DATA_P<1> W10 FDI0_TX_1 402 402this alnalog sense due to accuracy concern.NC RSVD_8 DC_TEST_D1 TP_CPU_DC_TEST_D1
=PEG_D2R_P<9>
PCI EXPRESS BASED INTERFACE SIGNALS

PEG_RX_9 C9 9
2 2
FDI_DATA_P<2> W3 IN AV19 A58 TP_CPU_DC_TEST_A58
72 18 OUT FDI0_TX_2 PLACE_NEAR=U1000.K45:50.8MM NC RSVD_9 DC_TEST_A58
PEG_RX_10 F8 =PEG_D2R_P<10> IN 9 PLACE_SIDE=TOP
AT21 A59 CPU_DC_TEST_C59_A59
FDI_DATA_P<3> AA7
C 72 18
72 18 7
OUT
FDI_DATA_P<4> W7
FDI0_TX_3
FDI1_TX_0
PEG_RX_11
PEG_RX_12
C8
C5
=PEG_D2R_P<11>
=PEG_D2R_P<12>
IN 9
9
NC
BB21
NC
RSVD_10
RSVD_11
DC_TEST_A59
DC_TEST_C59 C59 C
OUT IN BB19 A61 CPU_DC_TEST_C61_A61
PLACE_NEAR=U1000.K43:50.8MM NC RSVD_12 DC_TEST_A61
72 18 OUT FDI_DATA_P<5> T4 FDI1_TX_1 PEG_RX_13 H6 =PEG_D2R_P<13> IN 9 PLACE_SIDE=TOP AY21 C61
NC RSVD_13 DC_TEST_C61
72 18 OUT FDI_DATA_P<6> AA3 FDI1_TX_2 PEG_RX_14 F6 =PEG_D2R_P<14> IN 9
BA22 D61 TP_CPU_DC_TEST_D61
NOTE: Intel validation sense lines per NC RSVD_14 DC_TEST_D61
72 18 OUT FDI_DATA_P<7> AC8 FDI1_TX_3 PEG_RX_15 K6 =PEG_D2R_P<15> IN 9
AY22 BD61 TP_CPU_DC_TEST_BD61
doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1. NC RSVD_15 DC_TEST_BD61
FDI_FSYNC<0> AA11 FDI0_FSYNC PEG_TX_0* G22 =PEG_R2D_C_N<0> AU19 RSVD_16 DC_TEST_BE61 BE61 CPU_DC_TEST_BE59_BE61
72 18 IN OUT 9
NC
FDI_FSYNC<1> AC12 FDI1_FSYNC PEG_TX_1* C23 =PEG_R2D_C_N<1> AU21 RSVD_17 DC_TEST_BE59 BE59
72 18 IN OUT 9
NC
PEG_TX_2* D23 =PEG_R2D_C_N<2> BD21 RSVD_18 DC_TEST_BG61 BG61 CPU_DC_TEST_BG59_BG61
72 18 FDI_INT U11 FDI_INT
OUT 9
NC
IN F21 =PEG_R2D_C_N<3> BD22 BG59
PEG_TX_3* OUT 9
NC RSVD_19 DC_TEST_BG59
11 10 8 =PP1V05_S0_CPU_VCCIO BD25 BG58 TP_CPU_DC_TEST_BG58
15 13 72 18 IN FDI_LSYNC<0> AA10 FDI0_LSYNC PEG_TX_4* H19 =PEG_R2D_C_N<4> OUT 9
NC RSVD_20 DC_TEST_BG58
R1030 FDI_LSYNC<1> AG8 FDI1_LSYNC PEG_TX_5* C17 =PEG_R2D_C_N<5> BD26 RSVD_21 DC_TEST_BG4 BG4 TP_CPU_DC_TEST_BG4
72
24.9
18 IN OUT 9
NC
1 2 72 CPU_EDP_COMP PEG_TX_6* K15 =PEG_R2D_C_N<6> BG22 RSVD_22 DC_TEST_BG3 BG3 CPU_DC_TEST_C4_BE3_BG3
OUT 9
NC
1% AD2 EDP_ICOMPO PEG_TX_7* F17 =PEG_R2D_C_N<7> 9
BE22 RSVD_23 DC_TEST_BE3 BE3
1/16W
PLACE_NEAR=U1000.AF3:12.7MM OUT NC
MF-LF AF3 EDP_COMPIO PEG_TX_8* F14 =PEG_R2D_C_N<8> BG26 RSVD_24 DC_TEST_BG1 BG1 CPU_DC_TEST_C4_BE1_BG1
402
OUT 9
NC
PEG_TX_9* A15 =PEG_R2D_C_N<9> BE26 RSVD_25 DC_TEST_BE1 BE1
OUT 9
NC
EMBEDDED DISPLAY PORT
EDP_HPD_L AG11 EDP_HPD BF23 BD1

OMIT_TABLE PEG_TX_10* J14 =PEG_R2D_C_N<10> OUT 9
NC RSVD_26 DC_TEST_BD1 TP_CPU_DC_TEST_BD1
R1031 TP_EDP_AUX_N AG4 EDP_AUX* PEG_TX_11* H13 =PEG_R2D_C_N<11> BE24 RSVD_27
10K
9 OUT 9
NC
1 2 9 TP_EDP_AUX_P AF4 EDP_AUX PEG_TX_12* M10 =PEG_R2D_C_N<12> OUT 9
1% PLACE_NEAR=U1000.AG11:12.7MM PEG_TX_13* F10 =PEG_R2D_C_N<13> OUT 9

1/16W 9 TP_EDP_TX_N<0> AC3 EDP_TX_0*
MF-LF PEG_TX_14* D9 =PEG_R2D_C_N<14> OUT 9
402 9 TP_EDP_TX_N<1> AC4 EDP_TX_1*
PEG_TX_15* J4 =PEG_R2D_C_N<15> OUT 9
9 TP_EDP_TX_N<2> AE11 EDP_TX_2*
9 TP_EDP_TX_N<3> AE7 EDP_TX_3* PEG_TX_0 F22 =PEG_R2D_C_P<0> OUT 9
PEG_TX_1 A23 =PEG_R2D_C_P<1> OUT 9

9 TP_EDP_TX_P<0> AC1 EDP_TX_0
PEG_TX_2 D24 =PEG_R2D_C_P<2> OUT 9
9 TP_EDP_TX_P<1> AA4 EDP_TX_1
PEG_TX_3 E21 =PEG_R2D_C_P<3> OUT 9
9 TP_EDP_TX_P<2> AE10 EDP_TX_2
B 9 TP_EDP_TX_P<3> AE6 EDP_TX_3
PEG_TX_4
PEG_TX_5
G19
B18
=PEG_R2D_C_P<4>
=PEG_R2D_C_P<5>
OUT
OUT
9
9
B
PEG_TX_6 K17 =PEG_R2D_C_P<6> OUT 9
3
PEG_TX_7 G17 =PEG_R2D_C_P<7> OUT 9
D PEG_TX_8 E14 =PEG_R2D_C_P<8> OUT 9
Q1031 PEG_TX_9 C15 =PEG_R2D_C_P<9> OUT 9
67 IN LCD_HPD 1 G DMN5L06TK PEG_TX_10 K13 =PEG_R2D_C_P<10> OUT 9

S SOT523 PEG_TX_11 G13 =PEG_R2D_C_P<11> 9
OUT
SYM_VER_1
2 PEG_TX_13 G10 =PEG_R2D_C_P<13> OUT 9

EDP:YES D8 =PEG_R2D_C_P<14>
PEG_TX_14 OUT 9
72 24 10 CPU_CFG<16>
72 24 10 CPU_CFG<7>
72 24 10 CPU_CFG<6> 72 24 10 CPU_CFG<3>
72 24 10 CPU_CFG<5> 72 24 10 CPU_CFG<1>
72 24 10 CPU_CFG<4> 72 24 10 CPU_CFG<0>
72 24 10 CPU_CFG<2>
NOSTUFF EDP:YES NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF NOSTUFF
1 1 1 1 1 1 1 1 1
116S0066 1 R1031 EDP:YES
R1042 R1044 R1045 R1046 R1047 R1040 R1041 R1043 R1049 RES,MTL FILM,1/16W,1K,0402,SMD,LF
1K 1K 1K 1K 1K 1K 1K 1K 1K
5% 5% 5% 5% 5% 5% 5% 5% 5% 116S0090 1 RES,MTL FILM,1/16W,10K,0402,SMD,LF R1031 EDP:NO
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
A MF
201
2
MF
201
2
MF
201
2
MF
201
2
MF
201
2
MF
201
2
MF
201
2
201
MF
2
MF
201
2
SYNC_MASTER=J30_MLB SYNC_DATE=07/14/2011 A
PAGE TITLE
Intel Doc 460452 ChiefRiver Platform design guild rev1.0 section 2.2.12 recommendation.
CPU DMI/PEG/FDI/RSVD
DRAWING NUMBER SIZE
These can be Placed close to J2500 and Only for debug access
NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating
even if internal Graphics is disabled since they are Apple Inc. <SCH_NUM> D
shared with other interfaces. REVISION
FOR IVYBRIDGE PROCESSOR R
<E4LABEL>
CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS NOTICE OF PROPRIETARY PROPERTY: BRANCH
NOTE: The EDP_HPD processor input is a low voltage active low signal.
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4 Therefore, an inverting level shifter is required on the motherboard
to convert the active high signal from Embedded DisplayPort sink device
<BRANCH>
CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED to low voltage signals for the processor THE POSESSOR AGREES TO THE FOLLOWING: PAGE
(refer to latest Processor EDS for DC specifications).
CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED
If HPD is disabled while eDP interface is still enabled,
10 OF 132
CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
This signal can be left as no-connect if entire eDP interface is disabled.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
=PP1V05_S0_CPU_VCCIO OMIT_TABLE
15 13 11 10 8 CRITICAL
U1000
NOSTUFF
1 1
NOSTUFF
1
NOSTUFF IVY-BRIDGE
R1100 R1104 R1102 2C-35W
1K 51 1K
1
R1101 5% 5% 5% BGA BCLK J3 DMI_CLK100M_CPU_P IN 7 17 72
1/20W 1/20W 1/20W
62 MF MF MF
(2 OF 9) BCLK* H2 DMI_CLK100M_CPU_N 7 17 72
IN
5% 201 201 201
2 2 2
1/20W
MF
C57 PROC_DETECT* DPLL_REF_CLK AG3 DPLL_REF_CLK_P IN 17 72
2
201
NC DPLL_REF_CLK* AG1 DPLL_REF_CLK_N 17 72
CLOCKS
IN
72 20 OUT CPU_PROC_SEL_L F49 PROC_SELECT*
BCLK_ITP N59 ITPCPU_CLK100M_P IN 17 72
C 72 39 CPU_CATERR_L C49 CATERR*

BCLK_ITP* N58 ITPCPU_CLK100M_N IN 17 72 C
OUT
(IPU) PRDY* N53 XDP_CPU_PRDY_L OUT 24 72
72 40 20 BI CPU_PECI A48 PECI (IPU) PREQ* N55 XDP_CPU_PREQ_L IN 24 72

R1103
THERMAL
56
72 61 40 39 BI CPU_PROCHOT_L 2 1 CPU_PROCHOT_R_L C45 PROCHOT* (IPU) TCK L56 XDP_CPU_TCK IN 24 72
5% (IPU) TMS L55 XDP_CPU_TMS IN 24 72

27 16 13 8 =PP1V5R1V35_S3_CPU_VCCDDR 1/20W
MF 72 40 20 PM_THRMTRIP_L D45 THERMTRIP* (IPU) TRST* J58 XDP_CPU_TRST_L 24 72
201
OUT IN
1
R1120 XDP_CPU_TDI
200
(IPU) TDI M60 IN 24 72
72 18 IN PM_SYNC C48 PM_SYNC
1%
1/16W
TDO L59 XDP_CPU_TDO OUT 24 72
MF-LF
R1121 72 24 20 IN CPU_PWRGD B46 UNCOREPWRGOOD
PWR MGMT
402
JTAG & BPM

2
130 DBR* K58 XDP_DBRESET_L OUT 24 25 72
72 27 18 IN PM_MEM_PWRGD 2 1 PM_MEM_PWRGD_R BE45 SM_DRAMPWROK
1%
1/16W PLT_RESET_LS1V1_L D44 RESET* (IPU) BPM_0* G58 XDP_BPM_L<0> BI 24 72
MF-LF
402 (IPU) BPM_1* E55 XDP_BPM_L<1> BI 24 72
27 OUT =MEM_RESET_L AT30 SM_DRAMRST* (IPU) BPM_2* E59 XDP_BPM_L<2> BI 24 72
DDR3 MISC
(IPU) BPM_3* G55 XDP_BPM_L<3> BI 24 72
72 CPU_SM_RCOMP<0> BF44 SM_RCOMP_0
(IPU) BPM_4* G59 XDP_BPM_L<4> BI 24 72
72 CPU_SM_RCOMP<1> BE43 SM_RCOMP_1
(IPU) BPM_5* H60 XDP_BPM_L<5> BI 24 72
72 CPU_SM_RCOMP<2> BG43 SM_RCOMP_2
(IPU) BPM_6* J59 XDP_BPM_L<6> BI 24 72
(IPU) BPM_7* J61 XDP_BPM_L<7> BI 24 72
15 13 11 10 8
=PP1V05_S0_CPU_VCCIO
1 NOSTUFF
R1115
1 1 1
4.99K 1
1%
R1112 R1113 R1114 R1111
B R1126 1
75
140
1%
1/16W
25.5
1%
1/16W
200
1%
1/16W
2
1/20W
MF
201
10K
5%
1/20W
B
1% MF-LF MF-LF MF-LF MF
1/16W 402 402 402 201
2 2 2 2
MF-LF
402
2 R1125
43.2
25 24 IN CPU_RESET_L 2 1
1%
1/20W
MF
201
A SYNC_MASTER=J30_MLB SYNC_DATE=07/14/2011 A
PAGE TITLE
CPU CLOCK/MISC/JTAG
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
11 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL CRITICAL
73 28 7 BI MEM_A_DQ<0> AG6 SA_DQ_0 U1000 SA_CK_0 AU36 MEM_A_CLK_P<0> OUT 28 30 73 73 29 7 BI MEM_B_DQ<0> AL4 SB_DQ_0 U1000 SB_CK_0 BA34 MEM_B_CLK_P<0> OUT 29 30 73
73 28 MEM_A_DQ<1> AJ6 SA_DQ_1 BGA SA_CK_0* AV36 MEM_A_CLK_N<0> 28 30 73 73 29 7 MEM_B_DQ<1> AL1 SB_DQ_1 BGA SB_CK_0* AY34 MEM_B_CLK_N<0> 29 30 73
BI OUT BI OUT
(3 OF 9) (4 OF 9)
73 28 7 BI MEM_A_DQ<2> AP11 SA_DQ_2 73 29 7 BI MEM_B_DQ<2> AN3 SB_DQ_2
SA_CKE_0 AY26 MEM_A_CKE<0> 28 30 73 SB_CKE_0 AR22 MEM_B_CKE<0> 29 30 73
2C-35W
IVY-BRIDGE
2C-35W
MEM_A_DQ<3> AL6 OUT MEM_B_DQ<3> AR4 OUT
IVY-BRIDGE
73 28 7 BI SA_DQ_3 73 29 BI SB_DQ_3
D 73 28 7
73 28 7
BI
BI
MEM_A_DQ<4>
MEM_A_DQ<5>
AJ10
AJ8
SA_DQ_4
SA_DQ_5
SA_CK_1 AT40 MEM_A_CLK_P<1> OUT 9
73 29 7
73 29 7
BI
BI
MEM_B_DQ<4>
MEM_B_DQ<5>
AK4
AK3
SB_DQ_4
SB_DQ_5
SB_CK_1 BA36 MEM_B_CLK_P<1> OUT 9 D
SA_CK_1* AU40 MEM_A_CLK_N<1> OUT 9 SB_CK_1* BB36 MEM_B_CLK_N<1> OUT 9
73 28 7 BI MEM_A_DQ<6> AL8 SA_DQ_6 73 29 7 BI MEM_B_DQ<6> AN4 SB_DQ_6
73 28 7 BI MEM_A_DQ<7> AL7 SA_DQ_7 SA_CKE_1 BB26 MEM_A_CKE<1> OUT 28 30 73 73 29 7 BI MEM_B_DQ<7> AR1 SB_DQ_7 SB_CKE_1 BF27 MEM_B_CKE<1> OUT 29 30 73
73 28 7 BI MEM_A_DQ<8> AR11 SA_DQ_8 73 29 7 BI MEM_B_DQ<8> AU4 SB_DQ_8

73 28 7 BI MEM_A_DQ<9> AP6 SA_DQ_9 SA_CS_0* BB40 MEM_A_CS_L<0> OUT 28 30 73 73 29 7 BI MEM_B_DQ<9> AT2 SB_DQ_9 SB_CS_0* BE41 MEM_B_CS_L<0> OUT 29 30 73
73 28 7 BI MEM_A_DQ<10> AU6 SA_DQ_10 SA_CS_1* BC41 MEM_A_CS_L<1> OUT 28 30 73 73 29 7 BI MEM_B_DQ<10> AV4 SB_DQ_10 SB_CS_1* BE47 MEM_B_CS_L<1> OUT 29 30 73
73 28 7 BI MEM_A_DQ<11> AV9 SA_DQ_11 73 29 7 BI MEM_B_DQ<11> BA4 SB_DQ_11

73 28 7 BI MEM_A_DQ<12> AR6 SA_DQ_12 SA_ODT_0 AY40 MEM_A_ODT<0> OUT 28 30 73 73 29 7 BI MEM_B_DQ<12> AU3 SB_DQ_12 SB_ODT_0 AT43 MEM_B_ODT<0> OUT 29 30 73
73 28 BI MEM_A_DQ<13> AP8 SA_DQ_13 SA_ODT_1 BA41 MEM_A_ODT<1> OUT 28 30 73 73 29 7 BI MEM_B_DQ<13> AR3 SB_DQ_13 SB_ODT_1 BG47 MEM_B_ODT<1> OUT 29 30 73
MEMORY CHANNEL B
73 28 7 BI MEM_A_DQ<14> AT13 SA_DQ_14 73 29 BI MEM_B_DQ<14> AY2 SB_DQ_14
73 28 7 BI MEM_A_DQ<15> AU13 SA_DQ_15 SA_DQS_0* AL11 MEM_A_DQS_N<0> BI 28 73 73 29 7 BI MEM_B_DQ<15> BA3 SB_DQ_15 SB_DQS_0* AL3 MEM_B_DQS_N<0> BI 29 73
73 28 7 BI MEM_A_DQ<16> BC7 SA_DQ_16 SA_DQS_1* AR8 MEM_A_DQS_N<1> BI 28 73 73 29 7 BI MEM_B_DQ<16> BE9 SB_DQ_16 SB_DQS_1* AV3 MEM_B_DQS_N<1> BI 29 73
73 28 7 BI MEM_A_DQ<17> BB7 SA_DQ_17 SA_DQS_2* AV11 MEM_A_DQS_N<2> BI 28 73 73 29 7 BI MEM_B_DQ<17> BD9 SB_DQ_17 SB_DQS_2* BG11 MEM_B_DQS_N<2> BI 29 73
73 28 7 BI MEM_A_DQ<18> BA13 SA_DQ_18 SA_DQS_3* AT17 MEM_A_DQS_N<3> BI 28 73 73 29 7 BI MEM_B_DQ<18> BD13 SB_DQ_18 SB_DQS_3* BD17 MEM_B_DQS_N<3> BI 29 73
73 28 7 BI MEM_A_DQ<19> BB11 SA_DQ_19 SA_DQS_4* AV45 MEM_A_DQS_N<4> BI 28 73 73 29 7 BI MEM_B_DQ<19> BF12 SB_DQ_19 SB_DQS_4* BG51 MEM_B_DQS_N<4> BI 29 73
73 28 BI MEM_A_DQ<20> BA7 SA_DQ_20 SA_DQS_5* AY51 MEM_A_DQS_N<5> BI 28 73 73 29 BI MEM_B_DQ<20> BF8 SB_DQ_20 SB_DQS_5* BA59 MEM_B_DQS_N<5> BI 29 73
73 28 7 BI MEM_A_DQ<21> BA9 SA_DQ_21 SA_DQS_6* AT55 MEM_A_DQS_N<6> BI 28 73 73 29 7 BI MEM_B_DQ<21> BD10 SB_DQ_21 SB_DQS_6* AT60 MEM_B_DQS_N<6> BI 29 73
MEMORY CHANNEL A
73 28 7 BI MEM_A_DQ<22> BB9 SA_DQ_22 SA_DQS_7* AK55 MEM_A_DQS_N<7> BI 28 73 73 29 7 BI MEM_B_DQ<22> BD14 SB_DQ_22 SB_DQS_7* AK59 MEM_B_DQS_N<7> BI 29 73
73 28 7 BI MEM_A_DQ<23> AY13 SA_DQ_23 73 29 7 BI MEM_B_DQ<23> BE13 SB_DQ_23

73 28 7 BI MEM_A_DQ<24> AV14 SA_DQ_24 SA_DQS_0 AJ11 MEM_A_DQS_P<0> BI 28 73 73 29 7 BI MEM_B_DQ<24> BF16 SB_DQ_24 SB_DQS_0 AM2 MEM_B_DQS_P<0> BI 29 73
73 28 BI MEM_A_DQ<25> AR14 SA_DQ_25 SA_DQS_1 AR10 MEM_A_DQS_P<1> BI 28 73 73 29 7 BI MEM_B_DQ<25> BE17 SB_DQ_25 SB_DQS_1 AV1 MEM_B_DQS_P<1> BI 29 73
73 28 7 BI MEM_A_DQ<26> AY17 SA_DQ_26 SA_DQS_2 AY11 MEM_A_DQS_P<2> BI 28 73 73 29 BI MEM_B_DQ<26> BE18 SB_DQ_26 SB_DQS_2 BE11 MEM_B_DQS_P<2> BI 29 73
73 28 7 BI MEM_A_DQ<27> AR19 SA_DQ_27 SA_DQS_3 AU17 MEM_A_DQS_P<3> BI 28 73 73 29 7 BI MEM_B_DQ<27> BE21 SB_DQ_27 SB_DQS_3 BD18 MEM_B_DQS_P<3> BI 29 73
73 28 7 BI MEM_A_DQ<28> BA14 SA_DQ_28 SA_DQS_4 AW45 MEM_A_DQS_P<4> BI 28 73 73 29 7 BI MEM_B_DQ<28> BE14 SB_DQ_28 SB_DQS_4 BE51 MEM_B_DQS_P<4> BI 29 73
73 28 7 BI MEM_A_DQ<29> AU14 SA_DQ_29 SA_DQS_5 AV51 MEM_A_DQS_P<5> BI 28 73 73 29 7 BI MEM_B_DQ<29> BG14 SB_DQ_29 SB_DQS_5 BA61 MEM_B_DQS_P<5> BI 29 73
73 28 7 BI MEM_A_DQ<30> BB14 SA_DQ_30 SA_DQS_6 AT56 MEM_A_DQS_P<6> BI 28 73 73 29 7 BI MEM_B_DQ<30> BG18 SB_DQ_30 SB_DQS_6 AR59 MEM_B_DQS_P<6> BI 29 73
C 73 28 7
73 28 7
BI MEM_A_DQ<31>
MEM_A_DQ<32>
BB17
BA45
SA_DQ_31
SA_DQ_32
SA_DQS_7 AK54 MEM_A_DQS_P<7> BI 28 73 73 29 7
73 29 7
BI MEM_B_DQ<31>
MEM_B_DQ<32>
BF19
BD50
SB_DQ_31
SB_DQ_32
SB_DQS_7 AK61 MEM_B_DQS_P<7> BI 29 73 C
BI BI
73 28 BI MEM_A_DQ<33> AR43 SA_DQ_33 SA_MA_0 BG35 MEM_A_A<0> OUT 28 30 73 73 29 7 BI MEM_B_DQ<33> BF48 SB_DQ_33 SB_MA_0 BF32 MEM_B_A<0> OUT 29 30 73
73 28 7 BI MEM_A_DQ<34> AW48 SA_DQ_34 SA_MA_1 BB34 MEM_A_A<1> OUT 28 30 73 73 29 7 BI MEM_B_DQ<34> BD53 SB_DQ_34 SB_MA_1 BE33 MEM_B_A<1> OUT 29 30 73
73 28 7 BI MEM_A_DQ<35> BC48 SA_DQ_35 SA_MA_2 BE35 MEM_A_A<2> OUT 28 30 73 73 29 7 BI MEM_B_DQ<35> BF52 SB_DQ_35 SB_MA_2 BD33 MEM_B_A<2> OUT 29 30 73
73 28 7 BI MEM_A_DQ<36> BC45 SA_DQ_36 SA_MA_3 BD35 MEM_A_A<3> OUT 28 30 73 73 29 BI MEM_B_DQ<36> BD49 SB_DQ_36 SB_MA_3 AU30 MEM_B_A<3> OUT 29 30 73
73 28 7 BI MEM_A_DQ<37> AR45 SA_DQ_37 SA_MA_4 AT34 MEM_A_A<4> OUT 28 30 73 73 29 7 BI MEM_B_DQ<37> BE49 SB_DQ_37 SB_MA_4 BD30 MEM_B_A<4> OUT 29 30 73
73 28 7 BI MEM_A_DQ<38> AT48 SA_DQ_38 SA_MA_5 AU34 MEM_A_A<5> OUT 28 30 73 73 29 7 BI MEM_B_DQ<38> BD54 SB_DQ_38 SB_MA_5 AV30 MEM_B_A<5> OUT 29 30 73
73 28 7 BI MEM_A_DQ<39> AY48 SA_DQ_39 SA_MA_6 BB32 MEM_A_A<6> OUT 28 30 73 73 29 7 BI MEM_B_DQ<39> BE53 SB_DQ_39 SB_MA_6 BG30 MEM_B_A<6> OUT 29 30 73
73 28 7 BI MEM_A_DQ<40> BA49 SA_DQ_40 SA_MA_7 AT32 MEM_A_A<7> OUT 28 30 73 73 29 7 BI MEM_B_DQ<40> BF56 SB_DQ_40 SB_MA_7 BD29 MEM_B_A<7> OUT 29 30 73
73 28 7 BI MEM_A_DQ<41> AV49 SA_DQ_41 SA_MA_8 AY32 MEM_A_A<8> OUT 28 30 73 73 29 BI MEM_B_DQ<41> BE57 SB_DQ_41 SB_MA_8 BE30 MEM_B_A<8> OUT 29 30 73
73 28 7 BI MEM_A_DQ<42> BB51 SA_DQ_42 SA_MA_9 AV32 MEM_A_A<9> OUT 28 30 73 73 29 7 BI MEM_B_DQ<42> BC59 SB_DQ_42 SB_MA_9 BE28 MEM_B_A<9> OUT 29 30 73
73 28 BI MEM_A_DQ<43> AY53 SA_DQ_43 SA_MA_10 BE37 MEM_A_A<10> OUT 28 30 73 73 29 7 BI MEM_B_DQ<43> AY60 SB_DQ_43 SB_MA_10 BD43 MEM_B_A<10> OUT 29 30 73
73 28 7 BI MEM_A_DQ<44> BB49 SA_DQ_44 SA_MA_11 BA30 MEM_A_A<11> OUT 28 30 73 73 29 7 BI MEM_B_DQ<44> BE54 SB_DQ_44 SB_MA_11 AT28 MEM_B_A<11> OUT 29 30 73
73 28 7 BI MEM_A_DQ<45> AU49 SA_DQ_45 SA_MA_12 BC30 MEM_A_A<12> OUT 28 30 73 73 29 7 BI MEM_B_DQ<45> BG54 SB_DQ_45 SB_MA_12 AV28 MEM_B_A<12> OUT 29 30 73
73 28 7 BI MEM_A_DQ<46> BA53 SA_DQ_46 SA_MA_13 AW41 MEM_A_A<13> OUT 28 30 73 73 29 7 BI MEM_B_DQ<46> BA58 SB_DQ_46 SB_MA_13 BD46 MEM_B_A<13> OUT 29 30 73
73 28 7 BI MEM_A_DQ<47> BB55 SA_DQ_47 SA_MA_14 AY28 MEM_A_A<14> OUT 28 30 73 73 29 7 BI MEM_B_DQ<47> AW59 SB_DQ_47 SB_MA_14 AT26 MEM_B_A<14> OUT 29 30 73
73 28 7 BI MEM_A_DQ<48> BA55 SA_DQ_48 SA_MA_15 AU26 MEM_A_A<15> OUT 28 30 73 73 29 BI MEM_B_DQ<48> AW58 SB_DQ_48 SB_MA_15 AU22 MEM_B_A<15> OUT 29 30 73
73 28 7 BI MEM_A_DQ<49> AV56 SA_DQ_49 73 29 7 BI MEM_B_DQ<49> AU58 SB_DQ_49

73 28 7 BI MEM_A_DQ<52> AV54 SA_DQ_52 73 29 7 BI MEM_B_DQ<52> AU59 SB_DQ_52
73 28 7 BI MEM_A_DQ<53> AT54 SA_DQ_53 73 29 7 BI MEM_B_DQ<53> AU61 SB_DQ_53
73 28 BI MEM_A_DQ<55> AP52 SA_DQ_55 73 29 7 BI MEM_B_DQ<55> AR58 SB_DQ_55
73 28 7 BI MEM_A_DQ<56> AN57 SA_DQ_56 73 29 7 BI MEM_B_DQ<56> AK58 SB_DQ_56
B 73 28
73 28 7
BI
BI
MEM_A_DQ<57>
MEM_A_DQ<58>
AN53
AG56
SA_DQ_57
SA_DQ_58
73 29 7
73 29
BI
BI
MEM_B_DQ<57>
MEM_B_DQ<58>
AL58
AG58
SB_DQ_57
SB_DQ_58
B
73 28 7 BI MEM_A_DQ<59> AG53 SA_DQ_59 73 29 7 BI MEM_B_DQ<59> AG59 SB_DQ_59
73 28 7 BI MEM_A_DQ<60> AN55 SA_DQ_60 73 29 7 BI MEM_B_DQ<60> AM60 SB_DQ_60
73 28 7 BI MEM_A_DQ<61> AN52 SA_DQ_61 73 29 7 BI MEM_B_DQ<61> AL59 SB_DQ_61
73 28 7 BI MEM_A_DQ<62> AG55 SA_DQ_62 73 29 7 BI MEM_B_DQ<62> AF61 SB_DQ_62
73 28 7 BI MEM_A_DQ<63> AK56 SA_DQ_63 73 29 7 BI MEM_B_DQ<63> AH60 SB_DQ_63
73 30 28 OUT MEM_A_BA<0> BD37 SA_BS_0 73 30 29 OUT MEM_B_BA<0> BG39 SB_BS_0

73 30 28 OUT MEM_A_BA<1> BF36 SA_BS_1 73 30 29 OUT MEM_B_BA<1> BD42 SB_BS_1
73 30 28 OUT MEM_A_BA<2> BA28 SA_BS_2 73 30 29 OUT MEM_B_BA<2> AT22 SB_BS_2
73 30 28 OUT MEM_A_CAS_L BE39 SA_CAS* 73 30 29 OUT MEM_B_CAS_L AV43 SB_CAS*

73 30 28 OUT MEM_A_RAS_L BD39 SA_RAS* 73 30 29 OUT MEM_B_RAS_L BF40 SB_RAS*
73 30 28 OUT MEM_A_WE_L AT41 SA_WE* 73 30 29 OUT MEM_B_WE_L BD45 SB_WE*
PAGE TITLE
CPU DDR3 INTERFACES

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
12 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP1V5R1V35_S3_CPU_VCCDDR
43 16 13 10 8
=PPVCORE_S0_CPU_VCCAXG OMIT_TABLE
8 11 13 16 27
CRITICAL
=PPVCORE_S0_CPU OMIT_TABLE
15 13 10 8
43 CRITICAL
=PP1V05_S0_CPU_VCCIO 8 10 11 13 15
AA46 VAXG_1 U1000
(NOT controlled by VCCIO_SEL)
AB47 VAXG_2 BGA
A26 Fixed at 1.05V (7 OF 9)
VCC_1 U1000 VCCIO_1 AF46 AB50 VAXG_3 VDDQ_1 AJ28
D
IVY-BRIDGE
2C-35W
D A29
A31
VCC_2
VCC_3
BGA
(6 OF 9)
VCCIO_3
VCCIO_4
AG48
AG50
AB51 VAXG_4
AB52 VAXG_5
VDDQ_2
VDDQ_3
AJ33
AJ36
A34 AG51 AB53 VAXG_6 AJ40
IVY-BRIDGE
2C-35W
VCC_4 VCCIO_5 VDDQ_4
A35 VCC_5 VCCIO_6 AJ17 AB55 VAXG_7 VDDQ_5 AL30
C26 VCC_9 VCCIO_10 AJ47 AC61 VAXG_11 VDDQ_9 AM33
C27 VCC_10 VCCIO_11 AK50 AD47 VAXG_12 VDDQ_10 AM36
C32 VCC_11 VCCIO_12 AK51 AD48 VAXG_13 VDDQ_11 AM40
C34 AL14 AD50 VAXG_14 AN30
DDR3-1.5V RAILS
C37 VCC_13 VCCIO_14 AL15 AD51 VAXG_15 VDDQ_13 AN34
C39 AL16 AD52 VAXG_16 AN38
GRPHICS
C42 VCC_15 VCCIO_16 AL20 AD53 VAXG_17 VDDQ_15 AR26
D27 AL22 AD55 VAXG_18 AR28
16 13 8
=PPVCCSA_S0_CPU
D32 VCC_17 VCCIO_18 AL26 AD56 VAXG_19 VDDQ_17 AR30
27 16 13 11 8
=PP1V5R1V35_S3_CPU_VCCDDR
D39 VCC_20 VCCIO_21 AM16 AE46 VAXG_22 VDDQ_20 AR36
D42 VCC_21 VCCIO_22 AM17 N45 VAXG_23 VDDQ_21 AR40 R13821
E26 AM21 P47 VAXG_24 AV41 PLACE_NEAR=U1000.U10:50.8mm 100
VCC_22 VCCIO_23 (IPU) VDDQ_22 1%
E28 1/16W
VCC_23 VCCIO_24 AM43 P48 VAXG_25 VDDQ_23 AW26 MF-LF
E32 VCC_24 VCCIO_25 AM47 P50 VAXG_26 VDDQ_24 BA40 R13801 402
2
E34 AN20 P51 VAXG_27 BB28 PLACE_NEAR=U1000.BC43:50.8mm 100
VCC_25 VCCIO_26 VDDQ_25 PLACE_SIDE=TOP 1%
E37 1/16W
VCC_26 VCCIO_27 AN42 P52 VAXG_28 VDDQ_26 BG33 MF-LF
E38 402
VCC_27 VCCIO_28 AN45 P53 VAXG_29 2
QUIET
PEG AND DDR
F25
RAIL
AN48 P55 VAXG_30 AM28 =PP1V5_S3_CPU_VCCDQ
C F26
VCC_28
VCC_29
VCCIO_29
VCCIO_30 AA14
P56 VAXG_31
VCCDQ_1
VCCDQ_2 AN26
8 16
C
F28 VCC_30 P61 VAXG_32
VCCIO_31 AA15
F32 VCC_31 T48 VAXG_33 VDDQ_SENSE BC43 CPU_VDDQ_SENSE_P
VCCIO_32 AB17 Note. VOLTAGE=1.05V
F34 VCC_32 T58 VAXG_34 VSS_SENSE_VDDQ BA43 CPU_VDDQ_SENSE_N
SENSE
VCCIO_33 AB20
LINE
F37 T59 VAXG_35 Note. VOLTAGE=0V
VCC_33 AC13 U10
F38 VCCIO_34 T61 VAXG_36 VCCSA_SENSE CPU_VCCSASENSE OUT 58 72
VCC_34 AD16
F42 VCCIO_35 U46 VAXG_37
VCC_35 AD18 D48 CPU_VCCSA_VID<0>
G42 VCCIO_36 V47 VAXG_38 VCCSA_VID_0 58 72
VCC_36 AD21 D49 CPU_VCCSA_VID<1>
CORE SUPLLY
H25 VCCIO_37 V48 VAXG_39 (IPU) VCCSA_VID_1 OUT 58 72

VCC_37 AE14
H26 VCCIO_38 V50 VAXG_40
VCC_38
H28 VCCIO_39 AE15
V51 VAXG_41 SM_VREF AY43 CPU_SM_VREF
VOLTAGE=0.75V
13
VCC_39 AF16
H29 VCC_40
VCCIO_40 V52 VAXG_42 R13811
VCCIO_41 AF18 PLACE_NEAR=U1000.BA43:50.8mm 100
H32 VCC_41 V53 VAXG_43 PLACE_SIDE=TOP 1%
VCCIO_42 AF20 1/16W
H34 VCC_42 V55 VAXG_44 MF-LF
VCCIO_43 AG15 402
H35 VCC_43 V56 VAXG_45 1 1 2
VCCIO_44 AG16 R1314 R1313
H37 VCC_44 V58 VAXG_46 10K 10K
VCCIO_45 AG17 5% 5%
H38 VCC_45 V59 VAXG_47
VCCIO_46 AG20 =PP3V3_S0_CPU_VCCIO_SEL 8
1/20W
MF
1/20W
MF
H40 VCC_46 NOSTUFF W50 VAXG_48 201 201
VCCIO_47 AG21 2 2
J25 =PPVCORE_S0_CPU_VCCAXG W51 VAXG_49
VCC_47
VCCIO_48 AJ14 R13201 =PP1V05_S0_CPU_VCCIO 8 10 11 13 15 43 16 13 10 8
J26 VCC_48 10K W52 VAXG_50
VCCIO_49 AJ15 5%
J28 VCC_49 1/20W PLACE_NEAR=R1310.2:2.54mm W53 VAXG_51
1
J29 VCC_50 VCCIO_50 W16 MF R1302 1 W55 VAXG_52
201 2
130 PLACE_NEAR=U1000.C44:2.54mm R1300
J32 W17 W56 VAXG_53
VCC_51 VCCIO_51
IVB supports 1.05V VCCIO.
1%
1/16W
75
1%
R13701 PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.
J34 VCC_52 VCCIO_SEL can be NC. MF-LF 1/20W PLACE_NEAR=U1000.F45:50.8mm 100 W61 VAXG_54
J35 BC22 2 402 43 MF PLACE_SIDE=TOP 1%
Y48 VAXG_55
VCC_53 VCCIO_SEL CPU_VCCIO_SEL R1310 2 201 1/16W
MF-LF
J37 VCC_54 201 1/20W 1 2 5% MF CPU_VIDALERT_L 61 72 402 2 Y61 VAXG_56
B J38 AM25 =PP1V05_S0_CPU_VCCPQE
IN
B
QUIET
VCC_55 VCCPQE_1 =PP1V5R1V35_S3_CPU_VCCDDR

RAIL
8 15 PLACE_NEAR=U1000.A44:38mm 27 16 13 11 8
J40
SENSE
VCC_56 VCCPQE_2 AN22 CPU_AXG_SENSE_P F45 VAXG_SENSE
LINE
R1311 72 61 OUT Note. VOLTAGE=1.05V
J42 VCC_57 0 1 2 5% CPU_VIDSCLK CPU_AXG_SENSE_N G45 VSSAXG_SENSE 1
201 1/20W MF
OUT 61 72 72 61 OUT
Note. VOLTAGE=0V
R1330
K26 VCC_58 VIDALERT* A44 CPU_VIDALERT_L_R 1K
SVID
K27 B43 CPU_VIDSCLK_R BB3 VCCPLL_1 PLACE_NEAR=U1000.BJ44:2.54mm 1%

VCC_59 VIDSCLK R1312 15 8 =PP1V8_S0_CPU_VCCPLL_R 1/16W
1.8V
RAIL
MF-LF
K29 VCC_60 VIDSOUT C44 CPU_VIDSOUT_R 201 1/20W 0 1 2 5% MF CPU_VIDSOUT BI 61 72
BC1 VCCPLL_2 402
2
K32 VCC_61 BC4 VCCPLL_3
K34 F43
CPU_SM_VREF 13
VCC_62 VCC_SENSE CPU_VCCSENSE_P 16 13 8 =PPVCCSA_S0_CPU
SENSE
LINES
K35 G43 =PPVCORE_S0_CPU 8 10 13 15 43

L17 VCCSA_1
VCC_63 VSS_SENSE CPU_VCCSENSE_N
=PP1V05_S0_CPU_VCCIO 8 10 11 13 15
R13711 R13311 1 C1330
K37 VCC_64 PLACE_NEAR=U1000.G45:50.8mm 100 L21 VCCSA_2 PLACE_NEAR=U1000.BJ44:2.54mm 1K
VCCIO_SENSE AN16 CPU_VCCIOSENSE_P PLACE_SIDE=TOP 1% 1% 0.1UF
K39 VCC_66 1/16W
N16 VCCSA_3 1/16W 10%
VSS_SENSE_VCCIO AN17 CPU_VCCIOSENSE_N MF-LF MF-LF
16V
2 X7R-CERM
K42 VCC_67 402 N20 VCCSA_4 402
1 1 2 2 0402
L25 VCC_68 R1360 R1362 N22 VCCSA_5
L28 PLACE_NEAR=U1000.F43:50.8mm 100 100 PLACE_NEAR=U1000.AN16:50.8mm P17 VCCSA_6
SA RAIL
VCC_69 PLACE_SIDE=TOP 1% 1% PLACE_SIDE=TOP
1/16W 1/16W
L33 VCC_70 MF-LF MF-LF
P20 VCCSA_7 PLACE_NEAR=U1000.BJ44:2.54mm
402
L36 VCC_71 2 2 402 R16 VCCSA_8
L40 PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side. R18 VCCSA_9
VCC_72
N26 Note. VOLTAGE=1.25V OUT 61 72
R21 VCCSA_10
VCC_73
OUT 61 72
N30 VCC_74 Note. VOLTAGE=0V U15 VCCSA_11
N34 VCC_75 Note. VOLTAGE=1.05V 63 72
V16 VCCSA_12
OUT
N38 VCC_76 63 72
V17 VCCSA_13
OUT
Note. VOLTAGE=0V V18 VCCSA_14
V21 VCCSA_15
W20 VCCSA_16
R13611 1
R1363
100
A PLACE_NEAR=U1000.G43:50.8mm
PLACE_SIDE=TOP 1%
1/16W
MF-LF
100
1%
1/16W
MF-LF
PLACE_NEAR=U1000.AN17:50.8mm
PLACE_SIDE=TOP
402 2 402
PAGE TITLE
2
CPU POWER
DRAWING NUMBER SIZE

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side. REVISION
R
<E4LABEL>
<BRANCH>
13 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
CRITICAL
OMIT_TABLE
CRITICAL A9 VSS U1000 VSS AM34
A13 VSS BGA VSS AM38
BG13 VSS U1000 VSS M11
A17 VSS (8 OF 9) VSS AM42
BG17 VSS BGA VSS M15
(9 OF 9) A21 VSS VSS VSS AM45
BG21 VSS VSS M58
IVY-BRIDGE
2C-35W
VSS A25 VSS VSS AM48
BG24 VSS VSS N1
IVY-BRIDGE
2C-35W
A28 VSS VSS AM58
D
BG28 VSS
BG37 VSS
VSS
VSS
N17
N21
A33 VSS
A37 VSS
VSS AN1
AN21
D
BG41 VSS N25 VSS
VSS A40 VSS AN25
BG45 VSS N28 VSS
VSS A45 VSS AN28
BG49 VSS N33 VSS
VSS A49 VSS AN33
BG53 VSS N36 VSS
VSS A53 VSS AN36
C29 VSS N40 VSS
VSS AA1 VSS AN40
C35 VSS N43 VSS
VSS AA8 VSS AN43
C40 VSS N47 VSS
VSS AA13 VSS AN47
D4 VSS N48 VSS
VSS AA50 VSS AN50
D6 VSS N51 VSS
VSS AA51 VSS AN54
D10 VSS N52 VSS
VSS AA52 VSS AP7
D14 VSS N56 VSS
VSS AA53 VSS AP10
D18 VSS N61 VSS
VSS AA55 VSS AP51
D22 VSS P9 VSS
VSS AA56 VSS AP55
D26 VSS P14 VSS
VSS AB16 VSS AR7
D29 VSS P16 VSS
VSS AB18 VSS AR13
D35 VSS P18 VSS
VSS AB21 VSS AR17
D40 VSS P21 VSS
VSS AB48 VSS AR21
D43 VSS P58 VSS
VSS AB61 VSS AR41
D46 VSS P59 VSS
VSS AC6 VSS AR48
D50 VSS R4 VSS
VSS AC10 VSS AR61
D54 VSS R17 VSS
VSS AC14 VSS AT4
D58 VSS R20 VSS
VSS AC46 VSS AT14
E3 VSS R46 VSS
VSS AD4 VSS AT19
E25 VSS T1 VSS
VSS AD17 VSS AT36
E29 VSS T47 VSS
VSS AD20 VSS AT45
C E35 VSS
E40 VSS
VSS
VSS
T50
T51
AD61 VSS
VSS
VSS AT52 C
AE8 VSS VSS AT58
F13 VSS VSS T52
AE13 VSS VSS AU1
F15 VSS VSS T53
AF1 VSS VSS AU7
F19 VSS VSS T55
AF17 VSS VSS AU11
F29 VSS VSS T56
AF21 VSS VSS AU28
F35 VSS VSS U8
AF47 VSS VSS AU32
F40 VSS VSS U13
AF48 VSS VSS AU51
F55 VSS VSS V20
AF50 VSS VSS AV17
G6 VSS VSS V61
AF51 VSS VSS AV21
G48 VSS VSS W8
AF52 VSS VSS AV22
G51 VSS VSS W13
AF53 VSS VSS AV34
G61 VSS VSS W15
AF55 VSS VSS AV40
H4 VSS VSS W18
AF56 VSS VSS AV48
H10 VSS VSS W21
AF58 VSS VSS AV55
H14 VSS VSS W46
AF59 VSS VSS AW7
H17 VSS VSS Y4
AG7 VSS VSS AW13
H21 VSS VSS Y47
AG10 VSS VSS AW43
H53 VSS VSS Y58
AG14 VSS VSS AW61
H58 VSS VSS Y59
AG18 VSS VSS AY4
J1 VSS
AG47 VSS VSS AY9
J49 VSS
AG52 VSS VSS AY14
J55 VSS
AG61 VSS VSS AY19
K8 VSS
AH4 VSS VSS AY30
K11 VSS
AH58 VSS VSS AY36
K21 VSS VSS_NCTF A5
AJ7 VSS VSS AY41
B K51 VSS
L16 VSS
VSS_NCTF
VSS_NCTF
A57
BC61
AJ13 VSS
AJ16 VSS
VSS AY45
AY49
B
L20 VSS BD3 VSS
VSS_NCTF AJ20 VSS AY55
L22 VSS BD59 VSS
VSS_NCTF AJ22 VSS AY58
L26 VSS BE4 VSS
VSS_NCTF AJ26 VSS BA1
L30 VSS BE58 VSS
L34 VSS BG5 VSS
L38 VSS BG57 VSS
L43 VSS C3 VSS
L48 VSS C58 VSS
L61 VSS D59 VSS
M4 VSS E1 VSS
VSS_NCTF AK1 VSS BA51
M6 VSS E61 VSS
VSS_NCTF AK52 VSS BB53
VSS
AL10 VSS VSS BC5
AL13 VSS VSS BC13
AL17 VSS VSS BC57
AL21 VSS VSS BD8
AL25 VSS VSS BD12
AL28 VSS VSS BD16
AL33 VSS VSS BD19
AL36 VSS VSS BD23
AL40 VSS VSS BD27
AL43 VSS VSS BD32
AL47 VSS VSS BD36
AL61 VSS VSS BD40
AM4 VSS BD44
A AM13 VSS
VSS
VSS BD48 SYNC_MASTER=J30_MLB SYNC_DATE=07/14/2011 A
AM20 VSS VSS BD52 PAGE TITLE
AM22 VSS VSS BD56 CPU GROUNDS
AM26 VSS VSS BE5 DRAWING NUMBER SIZE
AM30 VSS VSS BG9
REVISION
R
<E4LABEL>
<BRANCH>
14 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
All INTEL recommendations from Intel doc #458544 Chief River Platform Power Design Guide v0p9
CPU VCORE DECOUPLING

Intel recommendation (Table 7-2): Option 2: 35x 2.2uF, 12x 22uF, 4x 470uF, or Option 3: 35x 2.2uF, 6x 22uF, 6x 330 uF
43 13 10 8 =PPVCORE_S0_CPU CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 C1600 1 C1604 1 C1606 1 C1607 1 C1608 1 C1609 1 C1610 1 C1612 1 C1613 1 C1615 1 C1617 1 C1623 1 C1624
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
D
402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2
D
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 C1625 1 C1627 1 C1628 1 C1631 1 C1632 1 C1635 1 C1637 1 C1638 1 C1639 1 C1640 1 C1641 1 C1642 1 C1643 1 C1644 1 C1645 1 C1647 1 C1648
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2 402-2
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 C1650 1 C1651 1 C1652 C1653 1 C1654

1
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20%
2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
402-2 402-2 402-2 402-2 402-2
PLACEMENT_NOTE (C1655-C1666):
Place close to U1000 on top side.
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF
1 C1646 1 C168F 1 C16A0 1 C1655 1 C1656 1 C1657 1 C1658 1 C1659 1 C1660 1 C1661 1 C1662 1 C1663 1 C1664 1 C1665 1 C1666 1 C166A 1 C166B 1 C166C 1 C166D 1 C166E 1 C166F 1 C165A 1 C165B 1 C1667 1 C1674
20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V
2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
C PLACEMENT_NOTE (C1667-C1679):
Place close to U1000 on bottom side.
C
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF
1 C16A1 1 C16A2 1 C16A3 1 C1675 1 C1668 1 C1669 1 C1670 1 C1671 1 C1672 1 C1673 1 C1649 1 C164A 1 C1676 1 C1677 1 C1678 1 C1679 1 C165C 1 C165D 1 C165E 1 C165F 1 C164E 1 C164B 1 C164C 1 C164D 1 C164F
20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V
2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
Place near inductors on bottom side.
1
C1680 1
C1681 1
C1682 1
C1683 1
C168D 1
C168E
470UF-4MOHM 470UF-4MOHM 470UF-4MOHM 470UF-4MOHM 270UF 270UF
20% 20% 20% 20% 20% 20%
3 2 2.0V 3 2 2.0V 3 2 2.0V 3 2 2.0V 2 2V 2 2V
POLY-TANT POLY-TANT POLY-TANT POLY-TANT TANT TANT
D2T-SM1 D2T-SM1 D2T-SM1 D2T-SM1 CASE-B2-SM CASE-B2-SM
CPU VCCIO/VCCPQ DECOUPLING

Intel recommendation (Table 7-7): 26x 1uF, 10x 10uF, 2x 330uF CPU VCCPLL DECOUPLING
PLACEMENT_NOTE (C1684-C167F): Intel recommendation (table 7-5): 2x 1uF, 1x 330uF
Place on bottom side of U1000
U100.
13 11 10 8 =PP1V05_S0_CPU_VCCIO
B 1
C1684
1UF
1
C1685
1UF
1
C1686
1UF
1
C1687
1UF
1
C1688
1UF
1
C1689
1UF
1
C1690
1UF
1
C1691
1UF
1
C1692
1UF
1
C1693
1UF
1
C1694
1UF
1
C1695
1UF
1
C1696
1UF 8 =PP1V8_S0_CPU_VCCPLL 1
R1600
0
2
=PP1V8_S0_CPU_VCCPLL_R 8 13
B
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 5%
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V PLACE_NEAR=U1000.AK61:5mm PLACE_NEAR=U1000.AK61:5mm
2 2 2 2 2 2 2 2 2 2 2 2 2 1/16W
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402
MF-LF
402
1
C160X 1
C160Y 1
C160Z 1
C168C
1UF
10%
1UF
10%
270UF 270UF
20% 20%
10V 10V
2 X5R
2 X5R
2 2V 2 2V
PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA TANT TANT
402 402 CASE-B2-SM CASE-B2-SM
PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA
1
C1697 1
C1698 1
C1699 1
C169A 1
C169B 1
C169C 1
C169D 1
C169E 1
C169F 1
C161A 1
C161B 1
C161C 1
C161D
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF CPU VCCPLL Low pass filter
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
Place near U1000 on bottom side
1
C161E 1
C161F 1 C162A 1 C162B 1 C162C 1 C162D 1 C162E 1 C167A 1 C167B 1 C167C
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1
1
C167D 1
C167E 1
C168A 1
C168B
270UF 270UF 270UF 270UF
20% 20% 20% 20%
2 2V 2 2V 2 2V 2 2V
TANT TANT TANT TANT
A CASE-B2-SM CASE-B2-SM CASE-B2-SM CASE-B2-SM
PAGE TITLE
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

CPU DECOUPLING-I
DRAWING NUMBER SIZE
R1601
0.010 Apple Inc. <SCH_NUM> D
1 2 =PP1V05_S0_CPU_VCCPQE 8 13 REVISION
R
1%
1/4W 1
C167F
<E4LABEL>
MF
0603 1UF
2
10%
10V
Note:The smallest 10mOhm available in the library are 0805s THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
X5R
402 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
16 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VAXG DECOUPLING
Intel recommendation (Table 7-4) for GT2 3.9mOhm LL: 11x 1uF, 6x 10uF, 6x 22uF, 2x 470uF
43 13 10 8 =PPVCORE_S0_CPU_VCCAXG
Place on bottom side of U1000
U100.
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 C1700 1 C1701 1 C1702 1 C1703 1 C1704 1 C1705 1 C1706 1 C1707 1 C1708 1 C1709 1 C1710
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
D 2
10V
X5R-CERM
0402
2
10V
X5R-CERM
0402
2
10V
X5R-CERM
0402
2
10V
X5R-CERM
0402
2
10V
X5R-CERM
0402
2
10V
X5R-CERM
0402
2
10V
X5R-CERM
0402
2
10V
X5R-CERM
0402
2
10V
X5R-CERM
0402
2
10V
X5R-CERM
0402
2
10V
X5R-CERM
0402
D
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

1 C1711 1 C1712 1 C1713 1 C1714 1 C1715 1 C1716
10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
0402-1 0402-1 0402-1 0402-1 0402-1 0402-1
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF
1 C1717 1 C1718 1 C1719 1 C1720 1 C1721 1 C1722 1 C1725 1 C1726 1 C1727 1 C1728 1 C1729 1 C172A
20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF 20UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V 2V
2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM 2 X6T-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 0402
Place near inductors on bottom side.
1 1
C1723 C1724
C 3 2
470UF-4MOHM
20%
2.0V
POLY-TANT
3 2
470UF-4MOHM
20%
2.0V
POLY-TANT
C
D2T-SM1 D2T-SM1
CPU VDDQ/VCCDQ DECOUPLING

Intel recommendation (Table 7-11): 10x 1uF, 8x 10uF, 1x 330uF
27 13 11 8 =PP1V5R1V35_S3_CPU_VCCDDR
Place on bottom side of U100.
U1000
CPU VCCSA DECOUPLING
1
C1738 1
C1739 1
C1740 1
C1741 1
C1742 1
C1743 1
C1744 1
C1745 1
C1746 1
C1747 Intel recommendation (Table 7-9): 5x 1uf, 5x 10uf, 1x 330uf
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF PLACEMENT_NOTE (C1758-C1762):
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM
0402 0402 0402 0402 0402 0402 0402 0402 0402 0402 =PPVCCSA_S0_CPU
13 8 Place on bottom side of U1000
U100.
Place close to U1000 on bottom side
1 1 1 1 1 1 1 1
1
C1758 1
C1759 1
C1760 1
C1761 1
C1762
C1748 C1749 C1750 C1751 C1752 C1753 C1754 C1755 1UF 1UF 1UF 1UF 1UF
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10% 10% 10% 10% 10%
20% 20% 20% 20% 20% 20% 20% 20% 10V 10V 10V 10V 10V
2 2 2 2 2
B 2
6.3V
CERM-X5R
0402-1
2
6.3V
CERM-X5R
0402-1
2
6.3V
CERM-X5R
0402-1
2
6.3V
CERM-X5R
0402-1
2
6.3V
CERM-X5R
0402-1
2
6.3V
CERM-X5R
0402-1
2
6.3V
CERM-X5R
0402-1
2
6.3V
CERM-X5R
0402-1
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402
X5R-CERM
0402 B
1 1 1 1 1 1 1
C1756 C1770 C1763 C1764 C1765 C1766 C1767
270UF 270UF 10UF
20%
10UF
20%
10UF
20%
10UF
20%
10UF
20%
20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V
2 2V 2 2V 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
TANT TANT
CASE-B2-SM CASE-B2-SM 0402-1 0402-1 0402-1 0402-1 0402-1
Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402
R1702
1
C1768 1
C1769
270UF 270UF
0.010 20% 20%
1 2 =PP1V5_S3_CPU_VCCDQ 8 13 2 2V 2 2V
TANT TANT
1% CASE-B2-SM CASE-B2-SM
1/4W
1
MF
0603
C1757
1UF
10%
10V
2 X5R
402
PAGE TITLE
CPU DECOUPLING-II
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
17 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
U1800 OMIT_TABLE
PCH-PPT-MB-SFF-ES1
74 25 IN SYSCLK_CLK32K_RTC A19 RTCX1 BGA
QP8D-MM915462
FWH0/LAD0 A37 LPC_AD_R<0> 17 75 36 7 IN PCIE_ENET_D2R_N BJ33 PERN1 U1800 SMBALERT*/GPIO11 H12 SMBUS_PCH_ALERT_L 17
NC
C19 RTCX2 FWH1/LAD1 A39 LPC_AD_R<1> 17 75 36 7 IN PCIE_ENET_D2R_P BL33 PERP1 PCH-PPT-MB-SFF-ES1 SMBCLK F17 SMBUS_PCH_CLK OUT 7 42 75
(1 OF 10) BGA
FWH2/LAD2 C39 LPC_AD_R<2> 17 75 36 7 OUT PCIE_ENET_R2D_C_N BB30 PETN1 SMBDATA F10 SMBUS_PCH_DATA BI 7 42 75
=PP3V3_S0_PCH 8 23 QP8D-MM915462
FWH3/LAD3 C37 LPC_AD_R<3> 17 75 36 7 OUT PCIE_ENET_R2D_C_P AY30 PETP1
(IPU) (2 OF 10)
RTC_RESET_L F19 RTCRST* FWH4/LFRAME* K40 LPC_FRAME_R_L
LPC
17 17
1
R1820
RTC
PCIE_AP_D2R_N BJ35 SML0ALERT*/GPIO60 H22 USB_EXTB_SEL_XHCI
SMBUS
75 36 7 IN PERN2 OUT 17 26
10K
17 PCH_SRTCRST_L A23 SRTCRST* (IPU) LDRQ0* H40 TP_LPC_DREQ0_L 7 5% 75 36 7 IN PCIE_AP_D2R_P BL35 PERP2 SML0CLK K12 SML_PCH_0_CLK OUT 42 75
1/20W
LDRQ1*/GPIO23 F37 TBT_PWR_EN_PCH OUT 25 MF 75 36 7 OUT PCIE_AP_R2D_C_N BB33 PETN2 SML0DATA A9 SML_PCH_0_DATA BI 42 75
(IPU) 2 201
D 17 PCH_INTRUDER_L K22 INTRUDER*
SERIRQ Y4 LPC_SERIRQ BI 7 39 41
75 36 7 OUT PCIE_AP_R2D_C_P AY33 PETP2
D
17 PCH_INTVRMEN_L C21 INTVRMEN 9 IN PCIE_FW_D2R_N BH36 PERN3 SML1ALERT*/PCHHOT*/GPIO74 C9 USB_EXTD_SEL_XHCI OUT 17
SATA0RXN AN3 SATA_HDD_D2R_N IN 7 37 74 9 IN PCIE_FW_D2R_P BK36 PERP3 SML1CLK/GPIO58 D12 SML_PCH_1_CLK OUT 42 75
SATA0RXP AN1 SATA_HDD_D2R_P IN 7 37 74 9 OUT PCIE_FW_R2D_C_N BF33 PETN3 SML1DATA/GPIO75 C11 SML_PCH_1_DATA BI 42 75
75 17 HDA_BIT_CLK_R H35 HDA_BCLK SATA0TXN AU3 SATA_HDD_R2D_C_N OUT 7 37 74 9 OUT PCIE_FW_R2D_C_P BD33 PETP3
VSel strap not functional (VCCVRM = 1.8V) SATA0TXP AU1 SATA_HDD_R2D_C_P OUT 7 37 74
HDA_SYNC_R H37 HDA_SYNC PCIE_EXCARD_D2R_N BJ37 PERN4
IHDA
C-LINK
75 17 7 IN
(IPD-BOOT)
SATA1RXN AN6 SATA_ODD_D2R_N IN 9 7 IN PCIE_EXCARD_D2R_P BL37 PERP4
17 PCH_SPKR N1 SPKR SATA1RXP AN8 SATA_ODD_D2R_P IN 9 7 OUT PCIE_EXCARD_R2D_C_N BD35 PETN4 (IPU/IPD) CL_CLK1 L3 TP_CLINK_CLK 7
(IPD-PLTRST#)
SATA1TXN AR3 SATA_ODD_R2D_C_N OUT 9 7 OUT PCIE_EXCARD_R2D_C_P BF35 PETP4 (IPU/IPD) CL_DATA1 J1 TP_CLINK_DATA 7
PCI-E*
75 17 HDA_RST_R_L F35 HDA_RST* SATA1TXP AR1 SATA_ODD_R2D_C_P OUT 9 CL_RST1* M8 TP_CLINK_RESET_L 7
7 NC_PCIE_5_D2RN BJ39 PERN5

75 51 IN HDA_SDIN0 D36 HDA_SDIN0 (IPD) SATA2RXN AD4 TP_SATA_C_D2RN 7 7 NC_PCIE_5_D2RP BL39 PERP5
7 TP_HDA_SDIN1 B36 HDA_SDIN1 (IPD) SATA2RXP AD2 TP_SATA_C_D2RP 7 7 NC_PCIE_5_R2D_CN AY35 PETN5
7 TP_HDA_SDIN2 C35 HDA_SDIN2 (IPD) SATA2TXN AL3 TP_SATA_C_R2D_CN 7 7 NC_PCIE_5_R2D_CP BB35 PETP5 PEG_A_CLKRQ*/GPIO47 R8 PEGCLKRQA_L_GPIO47 17
7 TP_HDA_SDIN3 A35 HDA_SDIN3 (IPD) SATA2TXP AL1 TP_SATA_C_R2D_CP 7 CLKOUT_PEG_A_N AF44 TP_PCIE_CLK100M_PEGAN 7
7 NC_PCIE_6_D2RN BH40 PERN6 CLKOUT_PEG_A_P AF46 TP_PCIE_CLK100M_PEGAP 7
75 25 17 HDA_SDOUT_R K37 HDA_SDO (IPD-BOOT) SATA3RXN AD8 TP_SATA_D_D2RN 7 7 NC_PCIE_6_D2RP BK40 PERP6
TP_SATA_D_D2RP NC_PCIE_6_R2D_CN
SATA
SATA3RXP AD6 7 7 BD37 PETN6
20 17 OUT JTAG_ISP_TMS K35 HDA_DOCK_EN*/GPIO33 SATA3TXN AG3 TP_SATA_D_R2D_CN 7 7 NC_PCIE_6_R2D_CP BF37 PETP6 CLKOUT_DMI_N BB24 DMI_CLK100M_CPU_N OUT 7 11 72
17 IN ENET_MEDIA_SENSE_RDIV M35 HDA_DOCK_RST*/GPIO13 SATA3TXP AG1 TP_SATA_D_R2D_CP 7 CLKOUT_DMI_P AY24 DMI_CLK100M_CPU_P OUT 7 11 72
7 NC_PCIE_7_D2RN BJ41 PERN7

SATA4RXN AE3 TP_SATA_E_D2RN 7 7 NC_PCIE_7_D2RP BL41 PERP7
24 IN XDP_PCH_TCK M17 JTAG_TCK (IPD) JTAG SATA4RXP AE1 TP_SATA_E_D2RP 7 7 NC_PCIE_7_R2D_CN AY37 PETN7 CLKOUT_DP_N AN10 DPLL_REF_CLK_N OUT 11 72
=PP1V05_S0_PCH_VCCIO_SATA 8 23
SATA4TXN AH8 TP_SATA_E_R2D_CN 7 7 NC_PCIE_7_R2D_CP BB37 PETP7 CLKOUT_DP_P AN12 DPLL_REF_CLK_P OUT 11 72
PLACE_NEAR=U1800.AB10:2.54mm
24 IN XDP_PCH_TMS M15 JTAG_TMS (IPU) SATA4TXP AH6 TP_SATA_E_R2D_CP 7
1
C 24 XDP_PCH_TDI U12 JTAG_TDI (IPU) SATA5RXN AC3 TP_SATA_F_D2RN 7
R1830
37.4
1%
7
7
NC_PCIE_8_D2RN
NC_PCIE_8_D2RP
BJ43
BL43
PERN8
PERP8 CLKIN_DMI_N BD17 PCIE_CLK100M_PCH_N 7 17 75
C
IN IN
1/20W
SATA5RXP AC1 TP_SATA_F_D2RP 7 MF 7 NC_PCIE_8_R2D_CN AY40 PETN8 CLKIN_DMI_P BF17 PCIE_CLK100M_PCH_P IN 7 17 75
24 XDP_PCH_TDO M12 JTAG_TDO SATA5TXN AJ3 TP_SATA_F_R2D_CN 7

2 201 7 NC_PCIE_8_R2D_CP BB40 PETP8
OUT =PP1V05_S0_PCH 8 23
SATA5TXP AJ1 TP_SATA_F_R2D_CP 7
1 75 36 7 OUT PCIE_CLK100M_ENET_N AD48 CLKOUT_PCIE0N CLKIN_GND1_N BB26 PCH_CLKIN_GNDN1 17
SATAICOMPO AB10 74 PCH_SATAICOMP R1831 75 36 7 OUT PCIE_CLK100M_ENET_P Controlled by PCIECLKRQ5#

AD50 CLKOUT_PCIE0P CLKIN_GND1_P AY26 PCH_CLKIN_GNDP1 17
49.9
75 41 OUT SPI_CLK_R AD12 SPI_CLK SATAICOMPI AB12 1% 17 IN SSD_CLKREQ_L M4 PCIECLKRQ0*/GPIO73
1/20W
SPI
MF
75 41 SPI_CS0_R_L AB8 SPI_CS0* SATA3RCOMPO AF10 2 201 75 9 7 PCIE_CLK100M_FW_N AE49 CLKOUT_PCIE1N CLKIN_DOT_96N M24 PCH_CLK96M_DOT_N 17 75
OUT IN
CLOCKS
PLACE_NEAR=U1800.AF12:2.54mm
SATA3COMPI AF12 74 PCH_SATA3COMP 75 9 7 PCIE_CLK100M_FW_P AE51 CLKOUT_PCIE1P CLKIN_DOT_96P K24 PCH_CLK96M_DOT_P IN 17 75
7 TP_SPI_CS1_L AB6 SPI_CS1* SATA3RBIAS AH4 PCH_SATA3RBIAS 17 FW_CLKREQ_L U8 PCIECLKRQ1*/GPIO18

PLACE_NEAR=U1800.AH4:2.54mm
SPI_MOSI_R W8 SPI_MOSI (IPD-BOOT) SATALED* W10 PCH_SATALED_L 1 PCIE_CLK100M_AP_N AD40 CLKOUT_PCIE2N CLKIN_SATA_N AK8 PCH_CLK100M_SATA_N
75 41 OUT 17 R1832 75 36 7 OUT IN 17 75
750 75 36 7 OUT PCIE_CLK100M_AP_P AD42 CLKOUT_PCIE2P CLKIN_SATA_P AK6 PCH_CLK100M_SATA_P IN 7 17 75

1%
75 41 IN SPI_MISO Y2 SPI_MISO (IPU) SATA0GP/GPIO21 M2 XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL OUT 24 1/20W 36 17 IN AP_CLKREQ_L T4 PCIECLKRQ2*/GPIO20
MF
(IPU) SATA1GP/GPIO19 R1 XDP_DC3_PCH_GPIO19_SATARDRVR_EN OUT 24
2 201
75 7 OUT PCIE_CLK100M_EXCARD_N AA49 CLKOUT_PCIE3N REFCLK14IN J49 PCH_CLK14P3M_REFCLK IN 17 75
75 7 OUT PCIE_CLK100M_EXCARD_P AA51 CLKOUT_PCIE3P

=PPVRTC_G3_PCH 17 IN EXCARD_CLKREQ_L B8 PCIECLKRQ3*/GPIO25
21 18 8
CLKIN_PCILOOPBACK E51 PCH_CLK33M_PCIIN IN 7 25 75
TP_PCIE_CLK100M_PE4NY48
7 CLKOUT_PCIE4N DOES THIS NEED LENGTH MATCH???
TP_PCIE_CLK100M_PE4PY50
7 CLKOUT_PCIE4P
R18021 1
R1803 17 OUT JTAG_DPMUXUC_TRST_L M19 PCIECLKRQ4*/GPIO26 XTAL25_IN W49 SYSCLK_CLK25M_SB_R 17 74
20K 20K
5% 5% XTAL25_OUT W51
1 1 1/20W 1/20W 17 LPC_AD_R<0> R1860 33 1 2 LPC_AD<0> BI 7 39 41 75
PCIE_CLK100M_SSD_N AB40 CLKOUT_PCIE5N
NC
R1800 R1801 MF
201 2
MF
2 201 17 LPC_AD_R<1> R1861 33 1 2 5% 1/20W MF 201
LPC_AD<1> 7 39 41 75
75 9 7 OUT
23 21 8 =PP1V05_S0_PCH_VCCDIFFCLK
B 330K
5%
1/20W
1M
5%
1/20W
17 LPC_AD_R<2> R1862 33 1 2
5%
5%
1/20W
1/20W
MF
MF
201
201
LPC_AD<2>
BI
BI 7 39 41 75
75 9 7 OUT PCIE_CLK100M_SSD_P
ENET_CLKREQ_L
AB42 CLKOUT_PCIE5P
K8 PCIECLKRQ5*/GPIO44
B
MF
201 2
MF RTC_RESET_L 17 17 LPC_AD_R<3> R1863 33 1 2 LPC_AD<3> BI 7 39 41 75
36 17 7 IN
(IPU-RSMRST#) R18901
2 201 PCH_SRTCRST_L 17 17 LPC_FRAME_R_L R1864 33 1 2 5% 1/20W MF 201
LPC_FRAME_L 7 39 41 75 90.9
OUT TP_PCIE_CLK100M_PEBN
AF40
5% 1/20W MF 201 7 CLKOUT_PEG_B_N 1%
PCH_INTRUDER_L 17 1/20W
TP_PCIE_CLK100M_PEBP
AF42 CLKOUT_PEG_B_P MF
PCH_INTVRMEN_L 17 75 17 HDA_BIT_CLK_R R1810 33 1
PLACE_NEAR=U1800.H35:1.27mm
2
5% 1/20W MF 201
HDA_BIT_CLK OUT 51 75
7
PEGCLKRQB_L_GPIO56 C4 PEG_B_CLKRQ*/GPIO56
201 2
17 PLACE_NEAR=U1800.AC49:2.54mm
C1802 1 1 C1803 75 17 HDA_SYNC_R R1811 33 1
2
5% 1/20W MF 201
HDA_SYNC OUT 51 75 XCLK_RCOMP AC49 PCH_XCLK_RCOMP
1.0UF 1.0UF PEG_CLK100M_N AB44 CLKOUT_PCIE6N
20%
6.3V 2
20%
2 6.3V
75 17 HDA_RST_R_L R1812 33 1
PLACE_NEAR=U1800.F35:1.27mm
2
5% 1/20W MF 201
HDA_RST_L OUT 51 75
75 9 7
75 9 7
OUT
PEG_CLK100M_P AB46 CLKOUT_PCIE6P
X5R X5R OUT
0201-MUR 0201-MUR 75 25 17 HDA_SDOUT_R R1813 33 1
PLACE_NEAR=U1800.K37:1.27mm
2
5% 1/20W MF 201
HDA_SDOUT OUT 51 75 17 IN PEG_CLKREQ_L J3 PCIECLKRQ6*/GPIO45 CLKOUTFLEX0/GPIO64 H50
(IPD-PWROK)
TP_PCH_GPIO64_CLKOUTFLEX0 9
CLOCKS
=PP3V3_SUS_PCH_GPIO 8 18 19 20
FLEX
=PP3V3_S0_PCH_GPIO 8 18 19 20 25 35 NO STUFF 75 33 7 OUT PCIE_CLK100M_TBT_N W44 CLKOUT_PCIE7N CLKOUTFLEX1/GPIO65 D48 TP_PCH_GPIO65_CLKOUTFLEX1 9
(IPD-PWROK)
=PP3V3_TBT_PCH_GPIO 8 20 R1840 75 33 7 OUT PCIE_CLK100M_TBT_P W46 CLKOUT_PCIE7P
NO STUFF 0 35 17 IN TBT_CLKREQ_L H4 PCIECLKRQ7*/GPIO46 CLKOUTFLEX2/GPIO66 G49 TP_PCH_GPIO66_CLKOUTFLEX2 9
ITPCPU_CLK100M_N 1 2 (IPU-RSMRST#) (IPD-PWROK)
R1876 10K 1 2
5% 1/20W MF 201
JTAG_ISP_TMS 17 20
72 11
NO STUFF 5%
1/20W ITPXDP_CLK100M_N AR12 CLKOUT_ITPXDP_N CLKOUTFLEX3/GPIO67 J51 TP_PCH_GPIO67_CLKOUTFLEX3
R1877 4.7K 1 2
5% 1/20W MF 201
PCH_SPKR 17
R1841 MF
201
72 24
72 24 ITPXDP_CLK100M_P AR10 CLKOUT_ITPXDP_P (IPD-PWROK)

9
R1878 10K 1 2
5% 1/20W MF 201
PCH_SATALED_L 17
72 11 ITPCPU_CLK100M_P 1
0 2
R1834 10K 1 2
5% 1/20W MF 201
DP_AUXCH_ISOL 24 25 5%
1/20W
R1833 10K 1 2
5% 1/20W MF 201
SATARDRVR_EN 24 MF
201
R1842 10K 1 2 FW_CLKREQ_L 17
R1885
2 5% 1/20W MF 201 SYSCLK_CLK25M_SB 1 2 SYSCLK_CLK25M_SB_R
R1869 10K 1
5% 1/20W MF 201
AP_CLKREQ_L 17 36
74 25 IN
201 6041/20W
MF 1.8V -> 1.1V
17 74
R1844 10K 1 2 EXCARD_CLKREQ_L 17 1% 1

R1845 10K 1 2
5% 1/20W MF 201
JTAG_DPMUXUC_TRST_L 17 Unused clock terminations for FCIM Mode PLACE_NEAR=U1800.W49:5.1mm R1886
2 5% 1/20W MF 201 1K
R1847 10K 1
5% 1/20W MF 201
ENET_CLKREQ_L 7 17 36
PCH_CLK96M_DOT_P R1891 10K 1 2 1%
1/20W
R1814 10K 2 1 PEG_CLKREQ_L 75 17
A R1815 10K 1 2 5% 1/20W MF 201

TBT_CLKREQ_L
17
17 35
75 17 PCH_CLK96M_DOT_N R1892 10K 1 2 5%
5%
1/20W
1/20W
MF
MF
201
201
MF
2 201 SYNC_MASTER=J13_MLB SYNC_DATE=09/15/2011 A
R1843 10K 1 2 5% 1/20W MF 201
SSD_CLKREQ_L 17 75 17 7 PCH_CLK100M_SATA_P R1893 10K 1 2 PAGE TITLE
5% 1/20W MF 201 2 5% 1/20W MF 201
R1846 10K 1 2 PEGCLKRQA_L_GPIO47 75 17 PCH_CLK100M_SATA_N R1894 10K 1 PCH SATA/PCIe/CLK/LPC/SPI
17 5% 1/20W MF 201
R1848 10K 1 2 5% 1/20W MF 201
PEGCLKRQB_L_GPIO56 PCIE_CLK100M_PCH_P R1895 10K 1 2 DRAWING NUMBER SIZE
R1853 10K 1 2
5% 1/20W MF 201
SMBUS_PCH_ALERT_L
17
17
75 17 7
75 17 7 PCIE_CLK100M_PCH_N R1896 10K 1 2

5% 1/20W MF 201
R1854 10K 1 2 5% 1/20W MF 201
USB_EXTB_SEL_XHCI 5% 1/20W MF 201 REVISION
R1855 10K 1 2 5% 1/20W MF 201

USB_EXTD_SEL_XHCI
17 26
17
75 17 PCH_CLK14P3M_REFCLK R1897 10K 1 2
5% 1/20W MF 201
R
<E4LABEL>
5% 1/20W MF 201 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R1879 10K 1 2
5% 1/20W MF 201
ENET_MEDIA_SENSE_RDIV 17 17 PCH_CLKIN_GNDP1 R1870 10K 1 2 THE INFORMATION CONTAINED HEREIN IS THE <BRANCH>
17 PCH_CLKIN_GNDN1 R1871 10K 1 2 5% 1/20W MF 201 PROPRIETARY PROPERTY OF APPLE INC.
Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V. 5% 1/20W MF 201
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
18 OF 132
If HDA = S0, must also ensure that signal cannot be high in S3.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP3V3_SUS_PCH_GPIO 8 17 18 19 20
=PP1V05_S0_PCH_VCCIO_PCIE 8
PLACE_NEAR=U1800.BF19:12.7mm
R19051 1
R1900
10K 49.9 OMIT_TABLE OMIT_TABLE
5% 1%
1/20W 1/20W
MF
201 2
MF U1800 U1800
2 201 PCH-PPT-MB-SFF-ES1 PCH-PPT-MB-SFF-ES1
72 10 7 DMI_N2S_N<0> BL21 DMI0RXN BGA FDI_RXN0 BL13 FDI_DATA_N<0> 7 10 72 9 LVDS_IG_BKL_ON M44 L_BKLTEN BGA SDVO_TVCLKINN AU40 TP_SDVO_TVCLKINN 7
IN IN OUT
QP8D-MM915462 QP8D-MM915462 (IPD)
72 10 7 IN DMI_N2S_N<1> BL23 DMI1RXN FDI_RXN1 BJ15 FDI_DATA_N<1> IN 10 72 9 OUT LVDS_IG_PANEL_PWR M42 L_VDD_EN SDVO_TVCLKINP AU42 TP_SDVO_TVCLKINP 7
(3 OF 10) (4 OF 10) (IPD)
D 72 10 7
72 10 7
IN
IN
DMI_N2S_N<2>
DMI_N2S_N<3>
BJ19
BL17
DMI2RXN
DMI3RXN
FDI_RXN2
FDI_RXN3
BD12
BJ11
FDI_DATA_N<2>
FDI_DATA_N<3>
IN
IN
10 72
10 72
R1955 1 9 OUT LVDS_IG_BKL_PWM L49 L_BKLTCTL SDVO_STALLN AR51 TP_SDVO_STALLN 7
D
(IPD)
FDI_RXN4 AY15 FDI_DATA_N<4> IN 7 10 72 100K SDVO_STALLP AR49 TP_SDVO_STALLP 7
5% (IPD)
72 10 7 IN DMI_N2S_P<0> BJ21 DMI0RXP FDI_RXN5 AY12 FDI_DATA_N<5> IN 10 72 1/20W NC
L51 L_DDC_CLK
MF
72 10 7 IN DMI_N2S_P<1> BJ23 DMI1RXP FDI_RXN6 BJ9 FDI_DATA_N<6> IN 10 72 201 2 NC
K46 L_DDC_DATA SDVO_INTN AT50 TP_SDVO_INTN 7
(IPD-PLTRST#) (IPD)
72 10 7 IN DMI_N2S_P<2> BL19 DMI2RXP FDI_RXN7 BF10 FDI_DATA_N<7> IN 10 72 SDVO_INTP AT48 TP_SDVO_INTP 7
(IPD)
72 10 7 IN DMI_N2S_P<3> BJ17 DMI3RXP NC
R42 L_CTRL_CLK
FDI_RXP0 BJ13 FDI_DATA_P<0> IN 7 10 72
NC
M40 L_CTRL_DATA SDVO_CTRLCLK W42 DPA_IG_DDC_CLK 9
72 10 7 OUT DMI_S2N_N<0> BD22 DMI0TXN FDI_RXP1 BL15 FDI_DATA_P<1> IN 10 72 SDVO_CTRLDATA R44 DPA_IG_DDC_DATA 9
(IPD-PLTRST#)
DMI_S2N_N<1> FDI_DATA_P<2>
DMI
FDI
BB22 DMI1TXN FDI_RXP2 BF12 AH42 LVD_IBG
72 10 7 OUT IN 10 72
NC
72 10 7 OUT DMI_S2N_N<2> BB19 DMI2TXN FDI_RXP3 BL11 FDI_DATA_P<3> IN 10 72
NC
AH40 LVD_VBG DDPB_AUXN AW51 DPA_IG_AUX_CH_N 9
72 10 7 OUT DMI_S2N_N<3> BB17 DMI3TXN FDI_RXP4 BB15 FDI_DATA_P<4> IN 7 10 72 DDPB_AUXP AW49 DPA_IG_AUX_CH_P 9
FDI_RXP5 BB12 FDI_DATA_P<5> IN 10 72

NC
AG51 LVD_VREFH DDPB_HPD AY42 DPA_IG_HPD 9
DMI_S2N_P<0> BF22 DMI0TXP FDI_RXP6 BL9 FDI_DATA_P<6> AG49 LVD_VREFL
DIGITAL DISPLAY INTERFACE

72 10 7 OUT IN 10 72
NC
72 10 7 OUT DMI_S2N_P<1> AY22 DMI1TXP FDI_RXP7 BD10 FDI_DATA_P<7> IN 10 72 DDPB_0N AY48 TP_DP_IG_B_MLN<0> 9
LVDS
72 10 7 OUT DMI_S2N_P<2> AY19 DMI2TXP NC
AK44 LVDSA_CLK* DDPB_0P AY50 TP_DP_IG_B_MLP<0> 9
72 10 7 OUT DMI_S2N_P<3> AY17 DMI3TXP FDI_INT BB10 FDI_INT OUT 10 72

NC
AK46 LVDSA_CLK DDPB_1N AY44 TP_DP_IG_B_MLN<1> 9
DDPB_1P AY46 TP_DP_IG_B_MLP<1> 9
FDI_FSYNC0 BH12 FDI_FSYNC<0> OUT 10 72

NC
AR46 LVDSA_DATA0* DDPB_2N BB44 TP_DP_IG_B_MLN<2> 9
=PPVRTC_G3_PCH 8 17 21
PCH_DMI_COMP BF19 DMI_ZCOMP FDI_FSYNC1 BK8 FDI_FSYNC<1> OUT 10 72
NC
AN49 LVDSA_DATA1* DDPB_2P BB46 TP_DP_IG_B_MLP<2> 9
BD19 DMI_IRCOMP
1 NC
AN44 LVDSA_DATA2* DDPB_3N BA49 TP_DP_IG_B_MLN<3> 9
FDI_LSYNC0 BK12 FDI_LSYNC<0> OUT 10 72

R1915 NC
AK40 LVDSA_DATA3* DDPB_3P BA51 TP_DP_IG_B_MLP<3> 9
PCH_DMI2RBIAS BK20 DMI2RBIAS FDI_LSYNC<1> 390K

FDI_LSYNC1 BH8 OUT 10 72 5%
1/20W
PLACE_NEAR=U1800.BK20:2.54mm MF NC
AR44 LVDSA_DATA0 DDPC_CTRLCLK T50 DPB_IG_DDC_CLK 9
1 2 201 AN51 DDPC_CTRLDATA U44 DPB_IG_DDC_DATA
R1920 NC LVDSA_DATA1
(IPD-PLTRST#)
9
SYSTEM POWER
750 DSWVRMEN F22 PCH_DSWVRMEN AN46 LVDSA_DATA2
MANAGEMENT
1% NC
1/20W 18 PCH_SUSACK_L F15 SUSACK* (IPU)
NC
AK42 LVDSA_DATA3 DDPC_AUXN AU51 DPB_IG_AUX_CH_N 9
C MF
2 201
PM_SYSRST_L L1 SYS_RESET*
DPWROK A21 PM_DSW_PWRGD IN 39
AH46 LVDSB_CLK*
DDPC_AUXP AU49
DDPC_HPD BE46
DPB_IG_AUX_CH_P
DPB_IG_HPD
9 C
39 25 7 IN NC 9
WAKE* D8 PCIE_WAKE_L 1 AH44 LVDSB_CLK

IN 7 18 36 R1909 NC
66 39 24 IN PM_PCH_SYS_PWROK M10 SYS_PWROK 100K DDPC_0N BC49 TP_DP_IG_C_MLN<0> 9
5%
CLKRUN*/GPIO32 T2 PM_CLKRUN_L BI 7 18 39 41 1/20W NC
AM50 LVDSB_DATA0* DDPC_0P BC51 TP_DP_IG_C_MLP<0> 9
MF
66 25 IN PM_PCH_PWROK M22 PWROK
2 201 NC
AL49 LVDSB_DATA1* DDPC_1N BD48 TP_DP_IG_C_MLN<1> 9
SUS_STAT*/GPIO61 G6 LPC_PWRDWN_L OUT 7 25 39 41

NC
AJ51 LVDSB_DATA2* DDPC_1P BD50 TP_DP_IG_C_MLP<1> 9
66 IN PM_PCH_APWROK G3 APWROK
NC
AH50 LVDSB_DATA3* DDPC_2N BF46 TP_DP_IG_C_MLN<2> 9
SUSCLK/GPIO62 D3 PM_CLK32K_SUSCLK_R OUT 40 DDPC_2P BF45 TP_DP_IG_C_MLP<2> 9
72 27 11 OUT PM_MEM_PWRGD B12 DRAMPWROK

NC
AM48 LVDSB_DATA0 DDPC_3N BE49 TP_DP_IG_C_MLN<3> 9
SLP_S5*/GPIO63 F6 PM_SLP_S5_L OUT 18 39 66

NC
AL51 LVDSB_DATA1 DDPC_3P BE51 TP_DP_IG_C_MLP<3> 9
66 IN PM_RSMRST_L B20 RSMRST* SLP_S4* K10 PM_SLP_S4_L OUT 7 18 27 36 38 39 66

NC
AJ49 LVDSB_DATA2
SLP_S3* D4 PM_SLP_S3_L OUT 7 18 27 36 39 66
NC
AH48 LVDSB_DATA3 DDPD_CTRLCLK M48 TP_DP_IG_D_CTRL_CLK 9
18 PCH_SUSWARN_L C13 SUSWARN*/SUSPWRDNACK/GPIO30 DDPD_CTRLDATA U42 TP_DP_IG_D_CTRL_DATA 9

(IPD-PLTRST#)
SLP_A* C7 TP_PM_SLP_A_L 7
39 24 18 IN PM_PWRBTN_L K19 PWRBTN* (IPU) 7 TP_CRT_IG_BLUE M46 CRT_BLUE DDPD_AUXN AU46 TP_DP_IG_D_AUXN 9
SLP_SUS* A15 PM_SLP_SUS_L OUT 18 66 7 TP_CRT_IG_GREEN R46 CRT_GREEN DDPD_AUXP AU44 TP_DP_IG_D_AUXP 9
66 40 39 IN SMC_ADAPTER_EN H19 ACPRESENT/GPIO31 7 TP_CRT_IG_RED U46 CRT_RED DDPD_HPD BK44 TP_DP_IG_D_HPD 9

(IPD-DeepS4/S5)
PM_SYNC
CRT
PMSYNCH BB8 OUT 11 72
40 IN PM_BATLOW_L H10 BATLOW*/GPIO72 (IPU) 7 TP_CRT_IG_DDC_CLK R49 CRT_DDC_CLK DDPD_0N BG51 TP_DP_IG_D_MLN<0> 9
SLP_LAN*/GPIO29 A7 PCH_GPIO29 OUT 18 7 TP_CRT_IG_DDC_DATA N49 CRT_DDC_DATA DDPD_0P BG49 TP_DP_IG_D_MLP<0> 9
PCH_RI_L F12 RI* DDPD_1N BF42 TP_DP_IG_D_MLN<1> 9
7 TP_CRT_IG_HSYNC M50 CRT_HSYNC DDPD_1P BD42 TP_DP_IG_D_MLP<1> 9
7 TP_CRT_IG_VSYNC N51 CRT_VSYNC DDPD_2N BJ47 TP_DP_IG_D_MLN<2> 9
DDPD_2P BL47 TP_DP_IG_D_MLP<2> 9
PCH_DAC_IREF R51 DAC_IREF DDPD_3N BL45 TP_DP_IG_D_MLN<3> 9
B 1
PLACE_NEAR=U1800.R51:2.54mm
R1951
T48 CRT_IRTN DDPD_3P BJ45 TP_DP_IG_D_MLP<3> 9
B
1K
5%
1/20W
MF
2 201
20 19 18 17 8 =PP3V3_SUS_PCH_GPIO
R19831
10K
5%
1/20W
MF
201 2 R1986
0
18 PCH_SUSWARN_L 2 1 PCH_SUSACK_L 18
5%
1/20W
MF
201
=PP3V3_SUS_PCH_GPIO 8 17 18 19 20
=PP3V3_S0_PCH_GPIO 8 17 19 20 25 35
=PP3V3_S5_PCH 8
R1985 1K 1 2
5% 1/20W MF 201
PM_PWRBTN_L 18 24 39
R1991 8.2K 1 2 PM_CLKRUN_L 7 18 39 41

5% 1/20W MF 201
R1982 10K 1 2 PCH_GPIO29
A R1925 1K 1 2
5% 1/20W MF 201
PCIE_WAKE_L
18
7 18 36
5% 1/20W MF 201 PAGE TITLE
PCH DMI/FDI/PM/Graphics
R1924 100K 2 1
5% 1/20W MF 201
PM_SLP_S3_L 7 18 27 36 39 66
DRAWING NUMBER
<SCH_NUM> D
SIZE
R1921 100K 2 1
5% 1/20W MF 201
PM_SLP_S4_L 7 18 27 36 38 39 66 Apple Inc. REVISION
R1922 100K 2 1
5% 1/20W MF 201
PM_SLP_S5_L 18 39 66 R
<E4LABEL>
R1923 100K 2 1
5% 1/20W MF 201
PM_SLP_SUS_L 18 66
<BRANCH>
19 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
NC BH24 TP1 U1800 AU6
NC
BK24 TP2 PCH-PPT-MB-SFF-ES1 AU8
NC NC
BH20 TP3 BGA AW1
NC QP8D-MM915462 NC
BK16 TP4 AW3
NC (5 OF 10) NC
BH16 TP5 AY2
NC NC
AN42 TP6 AY4
NC NC
AN40 TP7 AY6
NC NC
AR40 TP8 AY8
NC NC
AR42 TP9 BA1
NC NC
D20 TP10 BA3
NC NC
D NC
M30
E3
TP11 BB6
BC1
NC D
NC TP12 NC
AM4 TP13 RSVD BC3
NC NC
AT4 TP14 BD2
NC NC
AT2 TP15 BD4
NC NC
AD10 TP16 BE1
NC NC
B24 TP17 BE3
NC NC
D24 TP18 BE6
NC NC
AD44 TP19 BF6
NC NC
AD46 TP20 BF7
NC NC
BJ48 TP21 BG1
NC NC
BL7 TP22 BG3
NC NC
7 TP_PCH_TP23 W40 TP23 BH3
NC
K30 TP24 BH4
NC NC
BJ4
NC
BJ5
NC
BH49 TP41 BJ7
NC NC
BB42 TP42 BK6
NC NC
BL5
NC
74 38 7 IN USB3_EXTA_RX_N BJ25 USB3RN1 USBP0N F24 USB_EXTA_N BI 38 74
USB3_EXTC_RX_N BJ27 USB_EXTA_P Ext A (XHCI/EHCI)

9 IN USB3RN2 USBP0P H24 BI 38 74
74 36 7 IN USB3_EXTB_RX_N BJ31 USB3RN3

9 IN USB3_EXTD_RX_N BJ29 USB3RN4 USBP1N C25 USB_EXTC_N BI 9
USB_EXTC_P Ext C (XHCI/EHCI)

USBP1P A25 BI 9
74 38 7 IN USB3_EXTA_RX_P BL25 USB3RP1

USB3_EXTC_RX_P BL27 USBP2N C27 USB_EXTB_XHCI_N
C 74 36 7
9 IN
IN USB3_EXTB_RX_P BL31
USB3RP2
USB3RP3 USBP2P A27 USB_EXTB_XHCI_P
BI
BI
26 74
26 74
Ext B (XHCI) C
9 IN USB3_EXTD_RX_P BL29 USB3RP4
USBP3N H28 USB_EXTD_XHCI_N BI 26 74
USB3_EXTA_TX_N BF26 USB_EXTD_XHCI_P Ext D (XHCI) (Mobiles: Trackpad)

74 38 7 OUT USB3TN1 USBP3P F28 BI 26 74
USB
9 OUT USB3_EXTC_TX_N BB28 USB3TN2
74 36 OUT USB3_EXTB_TX_N BF28 USB3TN3 USBP4N M26 TP_USB_4N 9
USB3_EXTD_TX_N BF30 TP_USB_4P Unused

9 OUT USB3TN4 USBP4P K26 9
74 38 OUT USB3_EXTA_TX_P BD26 USB3TP1 USBP5N D28 TP_USB_SDN 9
USB3_EXTC_TX_P AY28 TP_USB_SDP RSVD: SD

9 OUT USB3TP2 USBP5P B28 9
74 36 OUT USB3_EXTB_TX_P BD28 USB3TP3

9 OUT USB3_EXTD_TX_P BD30 USB3TP4 USBP6N H26 TP_USB_WLANN 9
TP_USB_WLANP RSVD: WiFi

USBP6P F26 9
35 25 20 19 18 17 8 =PP3V3_S0_PCH_GPIO USBP7N D32 USB_HUB_UP_N BI 26 74
R2010 10K PCI_INTA_L D49 USB_HUB_UP_P USB Hub (All LS/FS Devices)
1 2 PIRQA* USBP7P B32 BI 26 74
2 5% 1/20W MF 201
PCI
R2011 10K 1 PCI_INTB_L C48 PIRQB*
R2012 10K 1 2 5% 1/20W MF 201
PCI_INTC_L C47 PIRQC* USBP8N M28 USB_CAMERA_N BI 32 74 Camera
R2013 10K 1 2 5% 1/20W MF 201
PCI_INTD_L C45 PIRQD* USBP8P K28 USB_CAMERA_P BI 32 74
5% 1/20W MF 201
USBP9N C29 USB_EXTB_EHCI_N BI 26 74
JTAG_GMUX_TMS G46 REQ1*/GPIO50 USB_EXTB_EHCI_P Ext B (EHCI)

19 OUT USBP9P A29 BI 26 74
19 OUT BLC_I2C_MUX_SEL K44 REQ2*/GPIO52

19 OUT USE_HDD_OOB_L F46 REQ3*/GPIO54 USBP10N C31 USB_EXTD_EHCI_N BI 9
USBP10P A31 USB_EXTD_EHCI_P BI 9 Ext D (EHCI)
B 7 TP_PCH_STRP_BBS1 F42 GNT1*/GPIO51 USBP11N H33 TP_USB_BT_HSN 9 B

NO STUFF 7 TP_PCH_STRP_ESI_L H42 GNT2*/GPIO53 USBP11P F33 TP_USB_BT_HSP 9 RSVD: BT (HS)
R2054 10K 2 1
5% 1/20W MF 201
PCH_STRP_TOPBLK_SWP_L D44 GNT3*/GPIO55
(IPU-PCIERST#) USBP12N H30 TP_USB_12N 9
TP_USB_12P Unused
USBP12P F30 9
19 IN BLC_GPIO A47 PIRQE*/GPIO2

55 19 IN AUD_IP_PERIPHERAL_DET C41 PIRQF*/GPIO3 USBP13N M33 TP_USB_13N 9
TBT_PWR_REQ_L F45 TP_USB_13P Unused

33 19 IN PIRQG*/GPIO4 USBP13P K33 9
(IPD)
54 19 IN AUD_I2C_INT_L F40 PIRQH*/GPIO5
USBRBIAS* C33 74 PCH_USB_RBIAS
PLACE_NEAR=U1800.A33:2.54mm
USBRBIAS A33 1
7 TP_PCI_PME_L H2 PME* (IPU) R2070
C17 XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L 22.6
OC0*/GPIO59 IN 19 24 1%
27 25 OUT PLT_RESET_L F7 PLTRSTB* 1/20W
OC1*/GPIO40 A17 XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L IN 19 24 MF
2 201
OC2*/GPIO41 A13 XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L IN 19 24
=PP3V3_S3_PCH_GPIO 8 25
75 25 OUT LPC_CLK33M_SMC_R G51 CLKOUT_PCI0 OC3*/GPIO42 D16 XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L IN 19 24
=PP3V3_S0_PCH_GPIO 8 17 18 19 20 25 35
25 OUT LPC_CLK33M_LPCPLUS_R E49 CLKOUT_PCI1 OC4*/GPIO43 A11 XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L IN 24
TP_PCI_CLK33M_OUT2 H48 CLKOUT_PCI2 OC5*/GPIO9 B16 XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

R2016 10K 1 2
5% 1/20W MF 201
JTAG_GMUX_TMS 19
7
TP_PCI_CLK33M_OUT3 J43 CLKOUT_PCI3 OC6*/GPIO10 C23 XDP_DB2_PCH_GPIO10_AP_PWR_EN

IN 24
R2017 10K 1 2
5% 1/20W MF 201
BLC_I2C_MUX_SEL 19
7
PCH_CLK33M_PCIOUT G45 CLKOUT_PCI4 OC7*/GPIO14 H15 XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

OUT 24
R2018 10K 1 2
5% 1/20W MF 201
USE_HDD_OOB_L 19
25 OUT
(IPD) IN 19 24
R2030 10K 1 2
5% 1/20W MF 201
BLC_GPIO 19
NO STUFF Redundant to pull-up on audio page

R2014 10K 1 2 AUD_IP_PERIPHERAL_DET 19 55
5% 1/20W MF 201
R2031 10K 1 2 TBT_PWR_REQ_L 19 33
A NO STUFF
5% 1/20W MF 201
Redundant to pull-up on audio page SYNC_MASTER=J13_MLB SYNC_DATE=09/15/2011 A
R2033 10K 1 2
5% 1/20W MF
AUD_I2C_INT_L
201
19 54
PAGE TITLE
PCH PCI/USB/TP/RSVD
R2069 10K 1 2
5% 1/20W
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
MF 201
19 24 DRAWING NUMBER SIZE
R2060 10K 1 2 XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L 19 24 Apple Inc. <SCH_NUM> D

R2061 10K 1 2 5% 1/20W MF 201
XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L 19 24 R
REVISION
5% 1/20W MF 201 <E4LABEL>
R2062 10K 1 2 XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L 19 24 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R2068 10K 1 2 5% 1/20W MF 201
XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L 19 24 THE INFORMATION CONTAINED HEREIN IS THE <BRANCH>
5% 1/20W MF 201 PROPRIETARY PROPERTY OF APPLE INC.
R2067 10K 2 1
5% 1/20W MF 201
AP_PWR_EN 24 36 66 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
20 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS

TABLE_BOMGROUP_ITEM
RAMCFG_SLOT RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H
Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.
D Systems with chip-down memory should add pull-downs on another page and set straps per software. D
35 25 20 19 18 17 8 =PP3V3_S0_PCH_GPIO
RAMCFG3:H RAMCFG2:H RAMCFG1:H RAMCFG0:H

R2574 is 1K series resistor between U2100 output and PCH input to reduce the current between the two drivers.. R21721 1
R2173 R21741 1
R2175
OMIT_TABLE 10K 10K 10K 10K
5% 5% 5% 5%
1/20W 1/20W 1/20W 1/20W
U1800 MF
201 2
MF MF MF
PCH-PPT-MB-SFF-ES1 2 201 201 2 2 201
24 XDP_FC1_TBT_CIO_PLUG_EVENT W1 BMBUSY*/GPIO0 BGA GPIO68 K42 9 MLB_RAMCFG3
IN
QP8D-MM915462
20 IN FW_PME_L B40 GPIO1 GPIO69 A43 9 MLB_RAMCFG2
(6 OF 10)
20 IN DPMUX_UC_IRQ C43 GPIO6 GPIO70 D40 9 MLB_RAMCFG1
39 20 IN SMC_RUNTIME_SCI_L A45 GPIO7 GPIO71 A41 9 MLB_RAMCFG0
7 TP_PCH_GPIO8 H17 GPIO8 (IPU-RSMRST#)
20 OUT WOL_EN C5 LAN_PHY_PWR_CTRL/GPIO12
24 IN
XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L K6 GPIO15 (IPU) A20GATE U3 PCH_A20GATE 20
24 OUT XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH AA3 SATA4GP/GPIO16 NO STUFF

LPCPLUS_GPIO B44 GPIO17 PECI AU12 PCH_PECI R2170 43 1 2 CPU_PECI
GPIO
41 20 7 BI (IPD) BI 11 40 72
5% 1/20W
ODD_PWR_EN_L W3 SCLOCK/GPIO22 MF 201
CPU/MISC
20 OUT
33 20 TBT_GO2SX_BIDIR K15 GPIO24 RCIN* U6 PCH_RCIN_L 20
39 20 IN SMC_WAKE_SCI_L C15 GPIO27 (IPU-DeepS4/S5)

=PP1V8_S0_PCH_VCC_DFTERM
24 OUT XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L G1 GPIO28 (IPU-RSMRST#) PROCPWRGD AU10 PCH_PROCPWRGD R2140 0 1 2 CPU_PWRGD
5% 1/20W OUT 11 24 72
8 21 23
35 OUT TBT_SW_RESET_L R2180 0 1 2 20 TBT_SW_RESET_R_L R3 STP_PCI*/GPIO34 MF 201 1

5%
MF
1/20W
201 24 OUT XDP_DC1_PCH_GPIO35_MXM_GOOD W12 GPIO35 THRMTRIP* BC9 40 PM_THRMTRIP_L_R R2156 390 1 2 PM_THRMTRIP_L IN 11 40 72
R2179
5% 1/20W 2.2K
24 20 OUT XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL W6 SATA2GP/GPIO36 MF 201 5%
(IPD-PLTRST#) 1/20W
24 OUT XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK M6 SATA3GP/GPIO37 INIT3_3V* R6 PCH_INIT3V3_L MF
JTAG_ISP_TDO N3 (IPD-PLTRST#) (IPU)
R2178 2 201
C 20
20
IN
OUT JTAG_ISP_TDI U10
SLOAD/GPIO38
SDATAOUT0/GPIO39 DF_TVS BC7
(IPD-PLTRST#?)
PCH_DF_TVS 2
1K 1 CPU_PROC_SEL_L 11 72
C
25 20 OUT FW_PWR_EN_PCH U1 SDATAOUT1/GPIO48 5% DF_TVS:DMI & FDI Term Voltage
1/20W
24 OUT XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH AA1 SATA5GP/GPIO49 TS_VSS1 AK10 MF Set to Vss when Low
201
50 41 20 7 BI SPIROM_USE_MLB K17 GPIO57 TS_VSS2 AH12 Set to Vcc when High
AK12 NO STUFF
TS_VSS3
A4 TS_VSS4 AH10 R21301
A5
1K This has internal pull up and should not pulled low.
5%
A48 1/20W THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.
NC_1 U40 NC MF
A49 201 2
A51
BH1 BL48
NCTF
BH51 BL49
VSS_NCTF
BJ1 BL51
BJ3 C3 35 25 20 19 18 17 8 =PP3V3_S0_PCH_GPIO
BJ49
VSS_NCTF
C49 C2113 1
BJ51 C51 0.1UF
10%
BL1 D1 16V CRITICAL
TBT_PWR_EN goes high for JTAG Programming
X5R-CERM 2 74LVC1G08
BL3 D51 0201 6
2 SOT891
BL4 E1
4 TBT_CIO_PLUG_EVENT_ISOL
1
U2100 OUT 24
33 IN TBT_CIO_PLUG_EVENT 08
NC
5 3
1
R2160
10K NC
5%
1/20W
MF
2 201
B B
JTAG Isolation due to glitch in and out of sleep
NOTE: TCK from PCH is Push-Pull CMOS

NOTE: TMS/TDI from PCH is Open Drain CRITICAL
NOTE: TDO from CR is Push-Pull CMOS
20 8 =PP3V3_S0_PCH_STRAPS
=PP3V3_TBT_PCH_GPIO 8 17 20
CRITICAL 1
Q2162 1
20 8 =PP3V3_S0_PCH_STRAPS R2186SSM6N15AFE R2162
G 2
=PP3V3_S5_PCH_GPIO 8 =PP3V3_TBT_PCH_GPIO 8 17 20 10K 10K
1
Q2160 1
5%
1/20W
SOT563 5%
1/20W
=PP3V3_S0_PCH_GPIO 8 17 18 19 20 25 35
R2188SSM6N15AFE R2163 MF
2 201
MF
2 201
G 2
10K 10K
6 D
1 S
5% SOT563 5% 20 OUT JTAG_ISP_TDO JTAG_TBT_TDO IN 33
1/20W 1/20W
MF MF
2 201 2 201
6 D
1 S
17 IN JTAG_ISP_TMS JTAG_TBT_TMS OUT 33
CRITICAL
R2185 10K 1 2 FW_PME_L 20 CRITICAL 20 8 =PP3V3_S0_PCH_STRAPS
=PP3V3_TBT_PCH_GPIO
R2196 10K 1 2 5% 1/20W MF 201
SMC_RUNTIME_SCI_L =PP3V3_S0_PCH_STRAPS 8 17 20
20 39 20 8
=PP3V3_TBT_PCH_GPIO Q2162
R2190 100K 1 2 5% 1/20W MF 201
LPCPLUS_GPIO 7 20 41 Q2160
8 17 20
1
R2113SSM6N15AFE 1
R2164
5% 1/20W MF 201
G 5
1 1 10K 10K
NO STUFF Must stuff R2197 when R2180 NO STUFFed. R2199SSM6N15AFE G 5 R2161 5% SOT563 5%
10K 10K 1/20W 1/20W
R2197 10K 1 2 TBT_SW_RESET_R_L 20 5% SOT563 5% MF MF
R2184 10K 1 2 5% 1/20W MF 201
FW_PWR_EN_PCH 20 25
1/20W
MF
1/20W
MF 2 201 2 201
3 D
4 S
5% 1/20W MF 201 2 201 2 201 24 IN JTAG_ISP_TCK JTAG_TBT_TCK OUT 33
R2150 10K
3 D
4 S
1 2 PCH_A20GATE 20 20 IN JTAG_ISP_TDI JTAG_TBT_TDI OUT 33
R2155 10K 1 2 5% 1/20W MF 201

PCH_RCIN_L 20
5% 1/20W MF 201
R2194 10K 1 2 WOL_EN
A R2192 10K 1 2 5% 1/20W MF 201
TBT_GO2SX_BIDIR
20
20 33 SYNC_MASTER=J13_MLB SYNC_DATE=09/15/2011 A
R2193 100K 1 2 5% 1/20W MF 201
SPIROM_USE_MLB 7 20 41 50
PAGE TITLE
R2191 10K 1 2
5% 1/20W MF 201
SMC_WAKE_SCI_L 20 39
PCH GPIO/MISC/NCTF
5% 1/20W MF 201 DRAWING NUMBER SIZE
R2111 20K 2 1
5% 1/20W MF 201
DPMUX_UC_IRQ 20
R2195 100K 2 1
5% 1/20W MF 201
AUD_IPHS_SWITCH_EN_PCH 24 25 REVISION
R2112 10K 2 1
5% 1/20W MF 201
ODD_PWR_EN_L 20
R
<E4LABEL>
R2198 10K 2 1
5% 1/20W MF
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL
201
20 24 NOTICE OF PROPRIETARY PROPERTY: BRANCH
<BRANCH>
R2116 10K 2 1
5% 1/20W MF 201
ENET_LOW_PWR_PCH 9 24 25 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
21 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
OMIT_TABLE =PP1V05_S0_PCH_VCC_CORE OMIT_TABLE

23 8
VCCACLK pin left as NC per DG NC

AC51 VCCACLK U1800 V5REF_SUS M37 =PP5V_SUS_PCH_V5REFSUS 23 1.44 A Max, 474mA Idle AB21 U1800
PCH-PPT-MB-SFF-ES1 AB23 PCH-PPT-MB-SFF-ES1
23 8 =PP3V3_S5_PCH_VCCDSW R12 VCCDSW3_3 BGA U27 =PP3V3_SUS_PCH_VCCSUS_USB 8 23 AC21 BGA
QP8D-MM915462 VCCPUSB U29 AC23 QP8D-MM915462
(8 OF 10) (7 OF 10)
7 TP_PPVOUT_PCH_DCPSUSBYP R10 DCPSUSBYP AE21 VCCADAC U51 PP3V3_S0_PCH_VCCA_DAC_F 23
CRT
USB AE23 VSSA_DAC V50
VCCAPLLDMI2 pin left as NC per DG AW31 VCCAPLLDMI2 =PP5V_S0_PCH_V5REF
NC V5REF N36 23
AF21
PCH output, for decoupling only AF23 AF33 pwrterm2gnd
PCI/GPIO/LPC
PLACE_NEAR=U1800.R15:2.54mm VCCALVDS
PPVOUT_G3_PCH_DCPRTC R15 AG21 AG33 pwrterm2gnd
VCC CORE
SATA
MIN_LINE_WIDTH=0.2 mm U15 DCPRTC
AL24 mm
MIN_NECK_WIDTH=0.2 left as NC per DG VCCAPLL_SATA3 AM2 NC NC-ed per DG
AG23 AC33
C2210 1 VOLTAGE=3.3V AG25 VSSALVDS AE33
LVDS
0.1UF 23 PP1V05_S0_PCH_VCCADPLLA_F BF40 VCCADPLLA AG27 VCCCORE
10%
HDA
16V PP1V05_S0_PCH_VCCADPLLB_F BD40 VCCADPLLB VCCSUSHDA V31 =PP3V3R1V5_S0_PCH_VCCSUSHDA AJ21 AF37 pwrterm2gnd
X5R-CERM 2 23
10 mA Max, 1mA Idle
8 23 25
0201 AJ23 AG37 pwrterm2gnd
CLK/MISC
23 17 8 =PP1V05_S0_PCH_VCCDIFFCLK AC37 AA13 =PP1V05_S0_PCH_VCCIO 8 21 23
AJ25 VCCTX_LVDS AG39 pwrterm2gnd
55mA Max, 5mA Idle AE37 AB15 AJ27 AJ37 pwrterm2gnd
VCCDIFFCLKN
AE39 AC13 AJ29
AC15 AJ31 AM23 =PP1V05_S0_PCH_VCC_DMI 8 23
C =PP1V05_S0_PCH_VCCSSC AC35 VCCSSC AF15 AK29 VCCDMI AU15 C
DMI
23 8
AG13 AK31 AW16
PPVOUT_S0_PCH_DCPSST U17 DCPSST AG15 AK33 VCCADMI_VRM AU21 =PP1V8R1V5_S0_PCH_VCCVRM 8 21
MIN_NECK_WIDTH=0.2 mm VCCIO AJ17 AM33 =PP1V8_S0_PCH_VCC_DFTERM 8 20 23
VOLTAGE=3.3V
C2222 1 23 PP1V05_S0_PCH_VCCCLKDMI_F AP39 VCCCLKDMI AK21 AM35 AJ13
0.1UF PLACE_NEAR=U1800.U17:2.54mm N18 AJ15
10%
DFT/SPI
16V =PP1V05_S0_PCH_V_PROC_IO AM17 V_PROC_IO R23 VCCDFTERM AK15
RTC CPU
X5R-CERM 2 23 8
0201 R25 AL13
N16 VCCRTC U23 7 TP_1V05_S0_PCH_VCCAPLLEXP AP19 VCCAPLLEXP
U25 VCCSPI Y19 =PP3V3_SUS_PCH_VCC_SPI 8 23
23 8 =PP1V05_S0_PCH_VCCASW AB27 23 21 8 =PP1V05_S0_PCH_VCCIO AM21

AB29 AM27 =PP3V3_SUS_PCH_VCCSUS 8 23
AP27 AP13
NC
FDI
AB31 N27 AR15 VCCAFDIPLL AP15
NC
AC27 R27 AR23 VCCAFDI_VRM AU19 =PP1V8R1V5_S0_PCH_VCCVRM 8 21
18 17 8 =PPVRTC_G3_PCH
VCCIO
AC29 R29 AR25
AC31 VCCSUS3_3 R33 AR27 AB19 =PP3V3_S0_PCH_VCC3_3
C2231 1 1 C2232 1 C2233 AE27 R35 AR29 VCCIO AC19
8 23
1UF 0.1UF 0.1UF

20% 10% 10% AE29 U33 AT13 AF6
6.3V 2 2 16V 2 16V
X5R X5R-CERM X5R-CERM AE31 U35 AU23 BK28
0201 0201 0201
PLACE_NEAR=U1800.N16:2.54mm R19 AU25 VCC3_3 R40
PLACE_NEAR=U1800.N16:2.54mm U19 AR33 AU27 T39
NC
PLACE_NEAR=U1800.N16:2.54mm U21 VCCASW AU31 AU29 U37
NC
V19 DCPSUS AU33 AU35 V37 PP3V3_S0_PCH_VCC3_3_CLK_F
NC 23
V21 V13 AW34 V39
NC
V23
V25 AC39 =PP1V8R1V5_S0_PCH_VCCVRM 8 21
B Y21
Y23
AE19
AF17
B
Y25 VCCVRM AW18
Y27 AW21
Y29
Y31
PCH output, for decoupling only
PAGE TITLE
PCH POWER
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
22 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE
OMIT_TABLE
AA7 U1800 AP2
BC23 U1800 G39
AA9 PCH-PPT-MB-SFF-ES1 AP4

BC25 PCH-PPT-MB-SFF-ES1 G41
BC27 BGA G43
AA11 BGA AP7 QP8D-MM915462
QP8D-MM915462 BC29 J7
AA39 AP9 (10 OF 10)
(9 OF 10) BC31 J9
AA41 AP11
BC34 J11
AA43 AP17
BC36 J13
AA45 AP21
D AB2
AB4
AP23
AP25
BC39
BC41
J16
J18
D
BC43 J21
AB17 AP29
BC45 J23
AB25 AP31
BD15 J25
AB33 AP33
BD24 J27
AB35 AP35
BE7 J29
AB37 AP37
BE9 J31
AB48 AP41
BE11 J34
AB50 AP43
BE13 J36
AC7 AP45
BE16 J39
AC9 AP48
BE18 J41
AC11 AP50
BE21 J45
AC17 AR6
BE23 K2
AC25 AR8
BE25 K4
AC41 AR17
BE27 K48
AC43 AR19
BE29 K50
AC45 AR21
BE31 L7
AE7 AR31
BE34 L9
AE9 AR35
BE36 L11
AE11 AR37
BE39 L13
AE13 AT7
BE41 L16
AE15 AT9
BE43 L18
AE17 AT11
BE45 L21
AE25 AT39
BF2 L23
AE35 AT41
BF4 L25
AE41 AT43
BF15 L27
AE43 AT45
C AE45 AU17
BF24
BF48
L29
L31
C
AF2 AU37
BF50 L34
AF4 AV2
BH6 L36
AF8 AV4
BH10 L39
AF19 AV48
BH14 VSS VSS L41
AF25 AV50
BH18 L43
AF27 AW7
BH22 L45
AF29 VSS VSS AW9
BH26 N7
AF31 AW11
BH28 N9
AF35 AW13
BH30 N11
AF48 AW23
BH32 N13
AF50 AW25
BH34 N21
AG7 AW27
BH38 N23
AG9 AW29
BH42 N25
AG11 AW36
BH44 N29
AG17 AW39
BH46 N31
AG19 AW41
BH48 N34
AG29 AW43
BK10 N39
AG31 AW45
BK14 N41
AG35 AY10
BK18 N43
AG41 B6
BK22 N45
AG43 B10
BK26 P2
AG45 B14
BK30 P4
AH2 B18
BK32 P48
AJ7 B22
BK34 P50
AJ9 B26
B AJ11
AJ19
B30
B34
BK38
BK42
R17
R21
B
BK46 R31
AJ33 B38
D6 R37
AJ35 B42
D10 T7
AJ39 B46
D14 T9
AJ41 BA7
D18 T11
AJ43 BA9
D22 T13
AJ45 BA11
D26 T41
AK2 BA13
D30 T43
AK4 BA16
D34 T45
AK17 BA18
D38 U31
AK19 BA21
D42 U49
AK23 BA23
D46 V2
AK25 BA25
F2 V4
AK27 BA27
F4 V7
AK35 BA29
F48 V9
AK37 BA31
F50 V11
AK48 BA34
G7 V15
AK50 BA36
G9 V17
AL7 BA39
G11 V27
AL9 BA41
G13 V29
AL11 BA43
G16 V33
AL39 BA45
G18 V35
AL41 BB2
G21 V41
AL43 BB4
G23 V43
AL45 BB48
A AM15 BB50
G25
G27
V45
V48 SYNC_MASTER=J13_MLB SYNC_DATE=09/15/2011 A
AM19 BC11 PAGE TITLE
G29 Y15
AM25
AM29
BC13
BC16
G31 Y17 PCH GROUNDS
G34 Y33 DRAWING NUMBER SIZE
AM31 BC18
G36 Y35 Apple Inc. <SCH_NUM> D
AM37 BC21 REVISION
Y37 R
<E4LABEL>
<BRANCH>
23 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH VCCIO BYPASS
L2406 17 8 =PP1V05_S0_PCH_VCCIO_SATA (PCH USB 1.05V PWR)
10UH-0.12A-0.36OHM PCH VCCSUS3_3 BYPASS

21 20 8 =PP1V8_S0_PCH_VCC_DFTERM 21 8 =PP3V3_SUS_PCH_VCCSUS_USB
17 8 =PP1V05_S0_PCH 1 2 PP1V05_S0_PCH_VCCCLKDMI_F
21 (PCH SUSPEND USB 3.3V PWR)
1 C2444 1 C2452
0603 MIN_NECK_WIDTH=0.25MM 23 21 8 =PP3V3_SUS_PCH_VCCSUS 1 C2440 1UF 1UF 1 C2446
VOLTAGE=1.05V 20% 20%
MAKE_BASE=TRUE PLACE_NEAR=U1800.AJ13:2.54mm
0.1UF 2 6.3V
X5R 2 6.3V
X5R
PLACE_NEAR=U1800.U27:2.54mm
1UF
10% 20%
1 C2411
1 C2484 1 C2413 2 16V
X5R-CERM
0201 0201 2 6.3V
X5R
0.1UF 0.1UF 0201 0201
10UF 10% 10%
PLACE_NEAR=U1800.AP39:2.54mm 20%
6.3V 2 16V
X5R-CERM
16V
2 X5R-CERM
2 CERM-X5R 0201 0201
0402-2
D
PLACE_NEAR=U1800.R27:2.54mm
PCH VCCSUSHDA BYPASS
(PCH HD Audio 3.3V/1.5V PWR)

PLACE_NEAR=U1800.AG13:2.54mm
D
PLACE_NEAR=U1800.N27:2.54mm
25 21 8 =PP3V3R1V5_S0_PCH_VCCSUSHDA
23 21 8 =PP3V3_SUS_PCH_VCCSUS
21 8 =PP1V05_S0_PCH_VCCSSC
1 C2441
0.1UF 1 C2476
PLACE_NEAR=U1800.V31:2.54mm 10%
2 16V
1 C2475 1UF
21 8 =PP1V05_S0_PCH_V_PROC_IO X5R-CERM
0201
1UF 20%
20% 2 6.3V
R2450 2 6.3V
X5R PLACE_NEAR=U1800.R33:2.54mm
X5R
0201
PLACE_NEAR=U1800.AC35:2.54mm 0201
=PP3V3_S0_PCH_VCCADAC 1
0 2 PP3V3_S0_PCH_VCCA_DAC_F
8
5%
MAKE_BASE=TRUE
21
C2416 1 1 C2417 1 C2430
1/20W MIN_NECK_WIDTH=0.2 MM 4.7UF 0.1UF 0.1UF
MF VOLTAGE=3.3V 20% 10% 10%
201 6.3V 2 16V
2 X5R-CERM 16V
2 X5R-CERM
PLACE_NEAR=U1800.AM17:2.54mm
X5R
402 0201 0201
21 8 =PP3V3_SUS_PCH_VCC_SPI
C2450 1 C2451 1 C2455 1

1 C2442
1UF
10UF 0.1UF 0.01UF PLACE_NEAR=U1800.Y19:2.54mm
20% 21 17 8 =PP1V05_S0_PCH_VCCDIFFCLK 23 21 8 =PP1V05_S0_PCH_VCCIO
20% 10% 10% 6.3V
2 X5R
6.3V 16V 16V
CERM-X5R 2 X5R-CERM 2 X5R-CERM 2 0201 1 C2469
0402-2 0201 0201 1 C2434 1UF
PCH VCCIO BYPASS
1UF PLACE_NEAR=U1800.AJ17:2.54mm
20%
20% 6.3V
2 X5R
23 21 8 =PP1V05_S0_PCH_VCC_DMI PLACE_NEAR=U1800.AC37:2.54mm 6.3V
2 X5R
PLACE_NEAR=U1800.U51:2.54mm 0201
PLACE_NEAR=U1800.U51:2.54mm 0201
PLACE_NEAR=U1800.U51:2.54mm
1 C2419
1UF
20%
23 21 8 =PP1V05_S0_PCH_VCC_DMI 2 6.3V
X5R
PLACE_NEAR=U1800.AM23:2.54mm 0201 21 8 =PP3V3_S5_PCH_VCCDSW
C 1 C2418 C2499 1
C
1UF
20% PCH VCC3_3 BYPASS
0.1UF
17 8 =PP3V3_S0_PCH 6.3V
2 X5R
PLACE_NEAR=U1800.R12:2.54mm 10%
16V
25 8 =PP5V_S0_PCH 0201 (PCH PCI 3.3V PWR)
X5R-CERM 2 PCH VCCCORE BYPASS
PCH V5REF Filter & Follower 0201 21 8
(PCH 1.05V CORE PWR)
=PP1V05_S0_PCH_VCC_CORE
1
1 mA (PCH Reference for 5V Tolerance on PCI) PLACE_NEAR=U1800.AW16:2.54mm

1
R2405 5 D2400 1 C2481 1 C2482 1 C2483 C2460 1
100 NC 1UF 1UF 1UF 10UF
5% BAT54DW-X-G
NC
1/20W SOT-363 20% 20% 20% 20%

MF 6 2 6.3V
X5R 2 6.3V
X5R
6.3V
2 X5R 6.3V
CERM-X5R 2
201 0201 0201 0201 0402-2
NEED PWR CONSTRAINT
2
PP5V_S0_PCH_V5REF
MIN_NECK_WIDTH=0.25MM <1 MA L2451 PLACE_NEAR=U1800.AB21:2.54mm
C2439 1 VOLTAGE=5V
MAKE_BASE=TRUE R2451 10UH-0.12A-0.36OHM PLACE_NEAR=U1800.AB21:2.54mm
1UF 1
10% =PP5V_S0_PCH_V5REF 21 8 =PP3V3_S0_PCH_VCC3_3_CLK 1 2 PP3V3_S0_PCH_VCC3_3_CLK_R 1 21 2 PP3V3_S0_PCH_VCC3_3_CLK_F
PLACE_NEAR=U1800.N36:2.54mm 10V 2 MIN_LINE_WIDTH=0.4 MM 0603 MIN_LINE_WIDTH=0.4 MM
5% MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM
X5R
402 1/16W
MF-LF
VOLTAGE=3.3V
C2453 1 VOLTAGE=3.3V C24541
402 1UF
10UF 10%
10V 2
20%
6.3V X5R
CERM-X5R 2 402
0402-1 23 21 8 =PP1V05_S0_PCH_VCCIO
PLACE_NEAR=U1800.V37:2.54mm
PLACE_NEAR=U1800.V37:2.54mm
=PP3V3_SUS_PCH
1 C2429 1 C2414 1 C2407 1 C2463 C2401 1
8
1UF 1UF 1UF 1UF 10UF
=PP5V_SUS_PCH PCH VCCADPLLA Filter 20% 20% 20% 20% 20%
8 PCH V5REF_SUS Filter & Follower
L2460 2 6.3V
X5R 2 6.3V
X5R
6.3V
2 X5R 6.3V
2 X5R 6.3V
CERM-X5R 2
1
1 mA S0-S5
4
(PCH Reference for 5V Tolerance on USB)
R2460 10UH-0.12A-0.36OHM (PCH DPLLA PWR) 0201 0201 0201 0201 0402-2
R2404 0
B 5%
10 NC
2 D2400
BAT54DW-X-G
8 =PP1V05_S0_PCH_VCCADPLL 1
5%
2 PP1V05_S0_PCH_VCCADPLLA_R 1
2
0603
PP1V05_S0_PCH_VCCADPLLA_F
MIN_NECK_WIDTH=0.2 MM 68 mA
21
B
NC
1/20W SOT-363 1/16W VOLTAGE=1.05V VOLTAGE=1.05V

MF 3 MF-LF
201 NEED PWR CONSTRAINT 402 1 C2403 1 C2402 1 C2461
100UF 100UF PLACE_NEAR=U1800.AR25:2.54mm
2
1UF PLACE_NEAR=U1800.AU25:2.54mm
PP5V_SUS_PCH_V5REFSUS 20%
6.3V
20%
6.3V 20% PLACE_NEAR=U1800.BF40:2.54MM PLACE_NEAR=U1800.AU29:2.54mm
MIN_LINE_WIDTH=0.3MM 2 CERM-X5R 2 CERM-X5R PLACE_NEAR=U1800.AR29:2.54mm
MIN_NECK_WIDTH=0.25MM PLACE_NEAR=U1800.BF40:2.54MM 1206-1 1206-1 2 6.3V
X5R PLACE_NEAR=U1800.AU27:2.54mm
VOLTAGE=5V PLACE_NEAR=U1800.BF40:2.54MM
C2438 1 MAKE_BASE=TRUE 0201
0.1UF =PP5V_SUS_PCH_V5REFSUS
PLACE_NEAR=U1800.M37:2.54mm
20% 21
10V
CERM 2
402 21 8 =PP1V05_S0_PCH_VCCASW
PCH VCCADPLLB Filter
L2465
R2465 10UH-0.12A-0.36OHM (PCH DPLLB PWR)
0
1 2 PP1V05_S0_PCH_VCCADPLLB_R
1 2 PP1V05_S0_PCH_VCCADPLLB_F
21
1 C2426 1 C2456 1 C2496 C2428 1 C2420 1
5% MIN_NECK_WIDTH=0.2 MM 0603 MIN_NECK_WIDTH=0.2 MM 69 mA 1UF 1UF 1UF 22UF 22UF
1/16W VOLTAGE=1.05V VOLTAGE=1.05V 20% 20% 20% 20% 20%
MF-LF 2 6.3V
X5R
6.3V
2 X5R 2 6.3V
X5R
6.3V
X5R-CERM1 2
6.3V
X5R-CERM1 2
23 21 8 =PP3V3_S0_PCH_VCC3_3 402 0201 0201 0201
23 21 8 =PP3V3_S0_PCH_VCC3_3 0603 0603
23 21 8 =PP3V3_S0_PCH_VCC3_3 1 C2462
1 C2465 1 C2466
100UF 1UF
1 C2422 100UF 20% 20%
PLACE_NEAR=U1800.BD40:2.54MM
1 C2421 1 C2423 0.1UF PLACE_NEAR=U1800.BD40:2.54MM
20%
2 6.3V
6.3V
2 CERM-X5R
6.3V
2 X5R
0.1UF 0.1UF 10% CERM-X5R 1206-1 0201 PLACE_NEAR=U1800.AB27:2.54mm
2 16V 1206-1 PLACE_NEAR=U1800.AB27:2.54mm

10% 10% PLACE_NEAR=U1800.BD40:2.54MM
2 16V 2 16V X5R-CERM PLACE_NEAR=U1800.AB27:2.54mm
X5R-CERM X5R-CERM PLACE_NEAR=U1800.AB19:2.54mm 0201 PLACE_NEAR=U1800.AB27:2.54mm
0201 PLACE_NEAR=U1800.AF6:2.54mm 0201 PLACE_NEAR=U1800.AB27:2.54mm
PLACE_NEAR=U1800.BK28:2.54mm
A 23 21 8 =PP3V3_S0_PCH_VCC3_3 SYNC_MASTER=J13_MLB SYNC_DATE=09/15/2011 A

PAGE TITLE
1 C2424 =PP3V3_S0_PCH_VCC3_3 PCH DECOUPLING
0.1UF 23 21 8
DRAWING NUMBER SIZE
10%
2 16V
X5R-CERM 1 C2486 1 C2485 Apple Inc. <SCH_NUM> D
0201 REVISION
PLACE_NEAR=U1800.T39:2.54mm 0.1UF 0.1UF R
10%
2 16V
10%
2 16V
<E4LABEL>
X5R-CERM X5R-CERM NOTICE OF PROPRIETARY PROPERTY: BRANCH
0201 0201
PLACE_NEAR=U1800.AC19:2.54mm PLACE_NEAR=U1800.R40:2.54mm THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
24 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
24 8 =PPVCCIO_S0_XDP CPU Micro2-XDP 24 8 =PPVCCIO_S0_XDP
CRITICAL NOTE: This is not the standard XDP pinout. XDP PLACE_NEAR=J2500.52:2.54mm
XDP_CONN Use with 921-0133 Adapter Flex to 72 24 11 XDP_CPU_TDO R2510 51 2 1
5% 1/20W MF 201
=PP3V3_S0_XDP J2500 support chipset debug.
8 XDP PLACE_NEAR=U1000.K61:2.54mm
DF40RC-60DP-0.4V XDP_CPU_TDI R2511 51
NO STUFF M-ST-SM1 72 24 11 2 1
5% 1/20W MF 201
R25401 62 61 XDP PLACE_NEAR=U1000.H59:2.54mm
1K
5%
1/16W
72 24 11 XDP_CPU_TMS R2512 51 2 1
5% 1/20W MF 201
MF-LF 2 1
402 2 XDP PLACE_NEAR=U1000.J58:2.54mm
72 11 XDP_CPU_PREQ_L OBSFN_A0 4 3 OBSFN_C0 CPU_CFG<16> 10 72 72 24 11 XDP_CPU_TCK R2513 51 2 1
D 72 11
BI
IN XDP_CPU_PRDY_L OBSFN_A1 6
8
5
7
OBSFN_C1 CPU_CFG<17>
IN
IN 10 72
XDP
5% 1/20W MF 201
D
(R2560-R2563) 72 11 XDP_BPM_L<0> OBSDATA_A0 10 9 OBSDATA_C0 CPU_CFG<0> 10 24 72
72 24 11 XDP_CPU_TRST_L R2514 51 2 1
5% 1/20W MF 201
IN IN
XDP_CPU:BPM 72 11 XDP_BPM_L<1> OBSDATA_A1 12 11 OBSDATA_C1 CPU_CFG<1> 10 72
IN IN
72 11 IN XDP_BPM_L<4> R2560 0 1 2 14 13
72 11 IN XDP_BPM_L<5> R2561 0 1 2 5% 1/20W MF 201
72 11 IN XDP_BPM_L<2> OBSDATA_A2 16 15 OBSDATA_C2 CPU_CFG<2> IN 10 72
72 11 IN XDP_BPM_L<6> R2562 0 1 2 5% 1/20W MF 201

72 11 IN XDP_BPM_L<3> OBSDATA_A3 18 17 OBSDATA_C3 CPU_CFG<3> IN 10 72
5% 1/20W MF 201
72 11 IN XDP_BPM_L<7> R2563 0 1 2
5% 1/20W MF 201
20 19
72 10 CPU_CFG<10> OBSFN_B0 22 21 OBSFN_D0 CPU_CFG<8> 10 72
IN IN
(R2564-R2567) 72 10 CPU_CFG<11> OBSFN_B1 24 23 OBSFN_D1 CPU_CFG<9> 10 72
IN IN
XDP_CPU:CFG 26 25
72 10 IN CPU_CFG<12> R2564 0 1 2 XDP_OBSDATA_B<0> OBSDATA_B0 28 27 OBSDATA_D0 CPU_CFG<4> IN 10 72
72 10 IN CPU_CFG<13> R2565 0 1 2 5% 1/20W MF 201

XDP_OBSDATA_B<1> OBSDATA_B1 30 29 OBSDATA_D1 CPU_CFG<5> IN 10 72
72 10 IN CPU_CFG<14> R2566 0 1 2 5% 1/20W MF 201 32 31

5% 1/20W MF 201
72 10 IN CPU_CFG<15> R2567 0 1 2
5% 1/20W MF 201
XDP_OBSDATA_B<2> OBSDATA_B2 34 33 OBSDATA_D2 CPU_CFG<6> IN 10 72
XDP PLACE_NEAR=R1841.1:2.54mm
XDP_OBSDATA_B<3> OBSDATA_B3 36 35 OBSDATA_D3 CPU_CFG<7>
XDP 38 37
IN 10 72
R2515 0 1 2 ITPXDP_CLK100M_P
5% 1/20W MF 201 IN 17 72
72 20 11 IN CPU_PWRGD R2500 1K 1 2
5% 1/20W MF 201
72 XDP_CPU_PWRGD PWRGD/HOOK0 40 39 ITPCLK/HOOK4 72 XDP_CPU_CLK100M_P XDP PLACE_NEAR=R1840.1:2.54mm
PLACE_NEAR=U1000.C60:2.54mm XDP_CPU_PWRBTN_L 42 41 R2516 0 1
HOOK1 ITPCLK#/HOOK5 72 XDP_CPU_CLK100M_N 2 ITPXDP_CLK100M_N IN 17 72
XDP 44 43 5% 1/20W MF 201
PM_PWRBTN_L R2502 0 1 2
VCC_OBS_AB VCC_OBS_CD
39 24 18 OUT
PLACE_NEAR=U4900.P17:2.54mm 5% 1/20W MF 201 XDP_CPU_CFG<0> HOOK2 46 45 RESET#/HOOK6 XDP_CPURST_L XDP PLACE_NEAR=U1000.G3:2.54mm
XDP XDP_VR_READY HOOK3 48 47 DBR#/HOOK7 XDP_DBRESET_L OUT 11 24 25 72 R2505 1K 1 2 CPU_RESET_L
5% 1/20W MF 201 IN 11 25
72 24 10 OUT CPU_CFG<0> R2501 1K 1 2

5% 1/20W MF 201
50 49 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
PLACE_NEAR=U1000.B57:2.54mm =SMBUS_XDP_SDA 52 51 XDP_CPU_TDO
42 24 BI SDA TDO IN 11 24 72
XDP =SMBUS_XDP_SCL 54 53 XDP_CPU_TRST_L
PM_PCH_SYS_PWROK R2504 330 1 2 42 24 IN SCL TRSTn OUT 11 24 72
66 39 18 OUT
5% 1/20W MF 201 TCK1 56 55 TDI XDP_CPU_TDI
NC OUT 11 24 72
XDP_CPU_TCK TCK0 58 57 TMS XDP_CPU_TMS
C 72 24 11
R2581
OUT
R2580
60 59 XDP_PRESENT#
OUT 11 24 72
C
(R2520-R2537) 1 2 1 2 XDP XDP
1/20W 5% 1/20W 5%
XDP SIGNALS XDP
PCH SIGNALS 201 1K MF 201 1K MF C2500 1
64 63
1 C2501 PCH SIGNALS Non-XDP Signals
0.1UF 0.1UF
24 OUT XDP_DA0_USB_EXTA_OC_L R2520 33 1 2
5% 1/20W MF 201
XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L IN 19 24
10%
16V
10%
16V
24 XDP_DA1_USB_EXTB_OC_L R2521 33 1 2 XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L 19 24
X7R-CERM 2 518S0847 2 X7R-CERM
OUT IN 0402 0402
24 OUT XDP_DA2_USB_EXTC_OC_L R2522 33 1 2 5% 1/20W MF 201
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L IN 19 24 19 OUT XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L R2590 0 1 2 USB_EXTA_OC_L IN 38
24 OUT XDP_DA3_USB_EXTD_OC_L R2523 33 1 2 5% 1/20W MF 201

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L IN 19 24 19 OUT XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L R2591 0 1 2 5% 1/20W MF 201
USB_EXTB_OC_L IN 7 36
5% 1/20W MF 201 5% 1/20W MF 201
24 19 IN XDP_DB2_PCH_GPIO10_AP_PWR_EN R2596 0 1 2
5% 1/20W MF 201
AP_PWR_EN OUT 19 36 66
24 OUT XDP_DB0_USB_EXTB_OC_EHCI_L R2524 33 1 2 XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L IN 19 24 19 OUT XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE R2597 0 1 2 SDCONN_STATE_CHANGE IN 25

5% 1/20W MF 201 5% 1/20W MF 201
24 OUT XDP_DB1_USB_EXTD_OC_EHCI_L R2525 33 1 2
5% 1/20W MF
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L
201 IN 19
NOTE: This is not the standard XDP pinout. XDP_DC3_PCH_GPIO19_SATARDRVR_EN R2573 0 1 2 SATARDRVR_EN
24 IN XDP_DB2_AP_PWR_EN R2526 33 1 2
5% 1/20W MF 201
XDP_DB2_PCH_GPIO10_AP_PWR_EN OUT 19 24
Use with 921-0133 Adapter Flex to
24 17 IN
5% 1/20W MF 201 OUT 17
24 OUT XDP_DB3_SDCONN_STATE_CHANGE R2527 33 1 2

5% 1/20W
XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE
MF 201 IN 19 24
support chipset debug. XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L R2570 0 1 2 ISOLATE_CPU_MEM_L
24 OUT XDP_FC0_MEM_VDD_SEL_1V5_L R2528 33 1 2
5% 1/20W MF
XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L
201 IN 20 24
24 20 OUT
5% 1/20W MF 201
OUT 27
24 17 IN XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL R2572 0 1 2
5% 1/20W MF 201
DP_AUXCH_ISOL OUT 17 25
24 OUT XDP_FC1 R2529 33 1 2

5% 1/20W MF 201
XDP_FC1_TBT_CIO_PLUG_EVENT IN 20 24
24 20 XDP_FC1_TBT_CIO_PLUG_EVENT R2574 1K 1 2 TBT_CIO_PLUG_EVENT_ISOL 20
OUT IN
5% 1/20W MF 201
24 IN XDP_DC0_ISOLATE_CPU_MEM_L R2530 33 1 2 XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L OUT 20 24
24 IN XDP_DC1_MXM_GOOD R2531 33 1 2 5%
5%
1/20W
1/20W
MF
MF
201
201
XDP_DC1_PCH_GPIO35_MXM_GOOD OUT 20 PCH Micro2-XDP =PP3V3_S5_XDP 8
PPDDR:1V5
24 IN XDP_DC2_DP_AUXCH_ISOL R2532 33 1 2 XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL OUT 17 24
XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L R2595 0 1 2 MEM_VDD_SEL_1V5_L
5% 1/20W MF 201
24 IN XDP_DC3_SATARDRVR_EN R2533 33 1 2
5% 1/20W MF 201
XDP_DC3_PCH_GPIO19_SATARDRVR_EN OUT 17 24 CRITICAL
24 20 IN
5% 1/20W MF 201
OUT 60
24 IN XDP_DD0_DP_GPU_TBT_SEL R2534 33 1 2
5% 1/20W MF
XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL OUT
201
20 XDP_CONN
24 IN XDP_DD1_JTAG_ISP_TCK R2535 33 1 2 XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK OUT 20 24 J2550
5% 1/20W MF 201
DF40RC-60DP-0.4V
M-ST-SM1
24 20 OUT XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK R2575 0 1 2 JTAG_ISP_TCK OUT 20
24 IN XDP_DD2_AUD_IPHS_SWITCH_EN R2536 33 1 2 XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH OUT 20 24 24 20 OUT XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH R2576 0 1 2 5% 1/20W MF 201

AUD_IPHS_SWITCH_EN_PCH OUT 20 25
5% 1/20W MF 201 5% 1/20W MF 201
24 IN XDP_DD3_ENET_LOW_PWR R2537 33 1 2
5% 1/20W
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH
MF 201 OUT 20 24
62 61 24 20 OUT XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH R2577 0 1 2
5% 1/20W MF
ENET_LOW_PWR_PCH
201 OUT 9 20 25
B PCH/XDP Signal Isolation Notes: 2 1

B
- Following Intel’s Debug Prot Design Guid for HR and CR v1.3 7 TP_XDP_PCH_OBSFN_A<0> OBSFN_A0 4 3 OBSFN_C0 XDP_FC0_MEM_VDD_SEL_1V5_L 24
doc id 404081. 7 TP_XDP_PCH_OBSFN_A<1> OBSFN_A1 6 5 OBSFN_C1 XDP_FC1 24
Initially, stuffing both 33 and 0 ohms and validate whether 8 7

it is functional in that state, else add BOM options. 24 XDP_DA0_USB_EXTA_OC_L OBSDATA_A0 10 9 OBSDATA_C0 XDP_DC0_ISOLATE_CPU_MEM_L 24
- For isolated GPIOs: 24 XDP_DA1_USB_EXTB_OC_L OBSDATA_A1 12 11 OBSDATA_C1 XDP_DC1_MXM_GOOD 24
- ’Output’ non-XDP signals require pulls. 14 13

- ’Output’ PCH/XDP signals require pulls. 24 XDP_DA2_USB_EXTC_OC_L OBSDATA_A2 16 15 OBSDATA_C2 XDP_DC2_DP_AUXCH_ISOL 24
24 XDP_DA3_USB_EXTD_OC_L OBSDATA_A3 18 17 OBSDATA_C3 XDP_DC3_SATARDRVR_EN 24

20 19 8 =PP1V05_SUS_PCH_JTAG
7 TP_XDP_PCH_OBSFN_B<0> OBSFN_B0 22 21 OBSFN_D0 TP_XDP_PCH_OBSFN_D<0> 7
7 TP_XDP_PCH_OBSFN_B<1> OBSFN_B1 24 23 OBSFN_D1 TP_XDP_PCH_OBSFN_D<1> 7 XDP PLACE_NEAR=J2550.52:2.54mm

26 25 24 17 XDP_PCH_TDO R2550 51 2 1
28 27 5% 1/20W MF 201
R252x, R253x, R257x and R259x should be placed where signal path 24 XDP_DB0_USB_EXTB_OC_EHCI_L OBSDATA_B0 OBSDATA_D0 XDP_DD0_DP_GPU_TBT_SEL 24
XDP_DB1_USB_EXTD_OC_EHCI_L 30 29 XDP_DD1_JTAG_ISP_TCK XDP PLACE_NEAR=U1800.K5:2.54mm

needs to split between route from PCH to J2550 24 OBSDATA_B1 OBSDATA_D1 24
XDP_PCH_TDI R2551 51 2 1
24 17
and path to non-XDP signal destination. 32 31 5% 1/20W MF 201
24 XDP_DB2_AP_PWR_EN OBSDATA_B2 34 33 OBSDATA_D2 XDP_DD2_AUD_IPHS_SWITCH_EN 24 XDP PLACE_NEAR=U1800.H7:2.54mm
24 XDP_DB3_SDCONN_STATE_CHANGE OBSDATA_B3 36 35 OBSDATA_D3 XDP_DD3_ENET_LOW_PWR 24 24 17 XDP_PCH_TMS R2552 51 2 1
5% 1/20W MF 201
XDP 38 37
ALL_SYS_PWRGD R2584 1K 1 2 XDP_PCH_S5_PWRGD 40 39 TP_XDP_PCH_HOOK4 XDP PLACE_NEAR=U1800.J3:2.54mm
66 39 IN PWRGD/HOOK0 ITPCLK/HOOK4 7
XDP_PCH_TCK R2556 51 2 1
PLACE_NEAR=J2550.39:2.54mm 5% 1/20W MF 201 42 41 24 17
XDP_PCH_PWRBTN_L HOOK1 ITPCLK#/HOOK5 TP_XDP_PCH_HOOK5 7 5% 1/20W MF 201
XDP 44 43
PM_PWRBTN_L R2585 0 1 2 VCC_OBS_AB VCC_OBS_CD
39 24 18 OUT
PLACE_NEAR=U4900.P17:2.54mm 5% 1/20W MF 201 TP_XDPPCH_HOOK2 HOOK2 46 45 RESET#/HOOK6 XDPPCH_PLTRST_L 1K series R on PCH Support Page
IN 25
TP_XDPPCH_HOOK3 HOOK3 48 47 DBR#/HOOK7 XDP_DBRESET_L OUT 11 24 25 72
50 49 NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page
A 42 24
42 24
BI =SMBUS_XDP_SDA
=SMBUS_XDP_SCL
SDA
SCL
52
54
51
53
TDO
TRSTn
XDP_PCH_TDO
TP_XDP_PCH_TRST_L 7
IN 17 24
IN PAGE TITLE
56 55 XDP_PCH_TDI
24 17 OUT XDP_PCH_TCK
TCK1
TCK0
NC
58 57
TDI
TMS XDP_PCH_TMS
OUT 17 24
OUT 17 24
CPU & PCH XDP
XDP_PRESENT#
XDP XDP Apple Inc. <SCH_NUM> D
REVISION
C2580 1 64 63
1 C2581 R
<E4LABEL>
0.1UF 0.1UF
10% 10% NOTICE OF PROPRIETARY PROPERTY: BRANCH
16V 16V
X7R-CERM 2 518S0847 2 X7R-CERM
THE INFORMATION CONTAINED HEREIN IS THE <BRANCH>
0402 0402 PROPRIETARY PROPERTY OF APPLE INC.
25 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPIO Glitch Prevention PCH Reset Button Platform Reset Connections
25 19 8 =PP3V3_S3_PCH_GPIO
66 8 =PP3V3_S0_SB_PM
1
Unbuffered R2681
33
LPC_RESET_L OUT 75
R2695 PLT_RESET_L 1 2 LPCPLUS_RESET_L

CRITICAL 8 1 C2650 10K
27 19 IN
MAKE_BASE=TRUE
5%
MAKE_BASE=TRUE OUT 7 41
0.1UF 1/16W
VCC 20%
10V XDP
5%
1/16W MF-LF R2683
U2650 2 CERM MF-LF 402
1
33 2 SMC_LRESET_L
SOT833
08
402 R2696 2 402 OUT 39
0 5%
74LVC2G08GT
24 20 9 ENET_LOW_PWR_PCH 1 7 ENET_LOW_PWR 9 72 24 11 XDP_DBRESET_L 1 2 PM_SYSRST_L 7 18 39 1/16W
IN A1 Y1 OUT IN OUT MF-LF
66 25 18 PM_PCH_PWROK 2
B1 5% OMIT R2671 402
D 20
IN
IN FW_PWR_EN_PCH 5
6
A2 Y2
3 FW_PWR_EN OUT 9
1/16W
MF-LF
402
1
R2697 1
0 2 PCA9557D_RESET_L OUT 31 D
B2 0 5%
1/16W
XDP
5%
1/16W MF-LF R2689
GND MF-LF 402
4 2 402 1K
1 2 XDPPCH_PLTRST_L OUT 24
SILK_PART=SYS RESET 5%
1/16W
MF-LF
402
25 19 8 =PP3V3_S3_PCH_GPIO
SDCONN_STATE_CHANGE ISOLATION
CRITICAL 8 1 C2652 =PP3V3_S3_SDBUF =PP3V3_S0_RSTBUF Buffered
0.1UF 8 25 8
VCC 20%
U2652 10V
2 CERM 24 OUT SDCONN_STATE_CHANGE 1 C2630
SOT833 402 0.1UF CRITICAL
08 10%
74LVC2G08GT
17 IN TBT_PWR_EN_PCH 1
A1 Y1
7 TBT_PWR_EN OUT 33 CRITICAL 2 6.3V
X5R =PP3V3_S4_SMC 8 25 36 40
1
5 MC74VHC1G08 R2686
2 TC7SZ08AFEAPE 201 SC70-HF =ENET_RESET_L OUT 36
41 39 18 7 IN LPC_PWRDWN_L B1 0
24 20 IN AUD_IPHS_SWITCH_EN_PCH 5
A2 Y2
3 AUD_IPHS_SWITCH_EN OUT 54
5
SOT665
2 R26411 2
U2680 4 PLT_RST_BUF_L
MAKE_BASE=TRUE
1 2 ENET_RESET_L
MAKE_BASE=TRUE
7
6 A 5%
66 25 18 IN PM_PCH_PWROK B2 4 470K 1 1/16W
U2630
Y 5%
1/20W 3 R2680 MF-LF
402
GND B
1 MF
201 2
C2680 1 100K
5%
=TBT_RESET_L OUT 35
4 0.1UF 1/16W
3 20% Series R on Pg38, R3803
10V
CERM 2
MF-LF
2 402
R2688
402 0
SDCONN_STATE_CHANGE_RIO IN 36 1 2 AP_RESET_L OUT 36
5%
1/16W R2693
40 36 25 8 =PP3V3_S4_SMC MF-LF
0
C R26401 Q2640
402
1
5%
2 BKLT_PLT_RST_L OUT 71 C
470K SSM6N37FEAPE 1/16W
33 MHz Clock Series Termination 5% MF-LF
G 2
1/20W SOT563 402
MF
201 2
Q2640
SSM6N37FEAPE Buffered CPU reset
S
G 5
=PP3V3_S0_RSTBUF
6
SOT563 25 8
1
40 7 OUT SDCONN_STATE_CHANGE_SMC
R2655 SDCONN_STATE_CHANGE_INV CRITICAL
PLACE_NEAR=U1800.G51:5.1MM
S
LPC_CLK33M_SMC_R 1
12 2 LPC_CLK33M_SMC 5 U2690
3
75 19 7 39 75
4
IN OUT
5%
74LVC1G07
SC70
1/20W R2630 2 4
MF
R2656 PLT_RST_CPU_BUF_L CPU_RESET_L OUT 11 24
201 10K MAKE_BASE=TRUE
19 LPC_CLK33M_LPCPLUS_R PLACE_NEAR=U1800.E49:5.1MM
1
22 2 LPC_CLK33M_LPCPLUS 7 41 75
35 20 19 18 17 8 =PP3V3_S0_PCH_GPIO 1 2 DP_AUXIO_EN INVERSION NC VTT voltage divider on CPU page
IN OUT 1
5%
5%
1/20W 1 3 R2690
1/20W
MF
MF
201 DP_AUXIO_ENOUT C2690 1 100K
5%
201 CRITICAL
69 70
0.1UF NC 1/16W
20% MF-LF
10V
Q2630
SOD-VESM-HF
D 3 CERM 2
402
2 402
SSM3K15FV C2639 1
R2659 0.1UF
10%
PLACE_NEAR=U1800.G45:2.54MM:5.1MM 22 16V
19 IN PCH_CLK33M_PCIOUT 1 2 PCH_CLK33M_PCIIN OUT 7 17 75 X5R-CERM 2
5% 1 G S 2 0201
1/20W
MF
201 24 17 IN DP_AUXCH_ISOL
B System RTC Power Source & 32kHz / 25MHz Clock Generator PCH ME Disable Strap B
=PPVBAT_G3_SYSCLK PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.
8
VDDIO_25M_A: SB power rail for XTAL circuit. If high, ME is disabled. This allows for full re-flashing of SPI ROM.
Coin-Cell: VBAT (300-ohm & 10uF RC)
VDDIO_25M_B: Ethernet power rail for XTAL circuit. SMC controls strap enable to allow in-field control of strap setting.
No Coin-Cell: 3.42V G3Hot (no RC)
VDDIO_25M_C: Thunderbolt power rail for XTAL circuit. Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.
8 =PP3V3_S5_SYSCLK
NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered. 23 8 =PP5V_S0_PCH
Coin-Cell & G3Hot: 3.42V G3Hot
Coin-Cell & No G3Hot: 3.3V S5 1
No Coin-Cell: 3.3V S5 R2620
100K
GreenClk 25MHz Power 8 =PP3V3_S0_SYSCLK No bypass necessary 5%
1/20W
Q2620 MF
NO STUFF SSM6N37FEAPE 2 201
G 5
R2607 SOT563 SPI_DESCRIPTOR_OVERRIDE_LS5V
0
1 2 GND_SYSCLK_25M_B
MIN_LINE_WIDTH=0.3MM 23 21 8 =PP3V3R1V5_S0_PCH_VCCSUSHDA
Ethernet XTAL Power (Unused on J5) 5% MIN_NECK_WIDTH=0.2MM
4 S
1/16W VOLTAGE=0V SPI_DESCRIPTOR_OVERRIDE
+3.42V 13
SB XTAL Power =PPVDDIO_S0_SBCLK MF-LF

VDD_25M 5
+V3.3A 2
3
8
402
TBT XTAL Power 8 =PPVDDIO_TBT_CLK 1
VBAT and +V3.3A are R2621
internally ORed to Q2620 D 6 1K
SSM6N37FEAPE 5%
NO STUFF 1 create VDD_RTC_OUT. SOT563
1/20W
C2624 1 C2622 1 C2620 1 R2608 C2602 1 MF
2 201
0.1UF 0.1UF 0.1UF 5%
0 1UF U2600 +V3.3A should be first
20% 20% 20% 1/16W 10% SLG3NB148A available ~3.3V power HDA_SDOUT_R 17 75
10V 10V 10V 10V 2 OUT
CERM 2 CERM 2 CERM 2 MF-LF X5R TQFN to reduce VBAT draw.
2 G S 1
IPD = 9-50k
402 402 402 2 402 402-1 CRITICAL
11 40 39 IN SPI_DESCRIPTOR_OVERRIDE_L
VDDIO_25M_A 32KHZ_A 12 SYSCLK_CLK32K_RTC OUT 17 74
CRITICAL 6
A C2605 14
VDDIO_25M_B
VDDIO_25M_C 25MHZ_A 9 SYSCLK_CLK25M_SB OUT 17 74 SYNC_MASTER=MASTER SYNC_DATE=MASTER A
12PF R2605 25MHZ_B 8 TP_SYSCLK_CLK25M_ENET PAGE TITLE
0
2 1 SYSCLK_CLK25M_X2 1 2 SYSCLK_CLK25M_X2_R 3
4
X2 25MHZ_C 15 SYSCLK_CLK25M_TBT OUT 33 74 Chipset Support
5% 5% NO STUFF X1 =PPVRTC_G3_OUT 8 DRAWING NUMBER SIZE
CRITICAL 1/16W
50V MF-LF 1
R2606 VDD_RTC_OUT 1 For SB RTC Power <SCH_NUM> D
1
CERM
402 NC Y2605 402
1M
Apple Inc. REVISION
4 2
CRITICAL 5% GND THRM

NC 3.2X2.5MM-SM 1/16W PAD 1 C2610 R
<E4LABEL>
C2606 25.000MHZ-20PPM-12PF-85C MF-LF
10
16
17
1UF
3
NOTICE OF PROPRIETARY PROPERTY:

7
12PF 2 402 10% BRANCH
1 2 SYSCLK_CLK25M_X1 2 6.3V
CERM THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
NOTE: 30 PPM crystal required
5%
50V
26 OF 132
CERM SHEET
402 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS

TABLE_BOMGROUP_ITEM
HUB_ALLREM HUB_NONREM1_0,HUB_NONREM0_0
TABLE_BOMGROUP_ITEM
HUB_1NONREM HUB_NONREM1_0,HUB_NONREM0_1
TABLE_BOMGROUP_ITEM
HUB_2NONREM HUB_NONREM1_1,HUB_NONREM0_0
USB MUX FOR LS/FS INTERNAL DEVICES HUB_3NONREM HUB_NONREM1_1,HUB_NONREM0_1
TABLE_BOMGROUP_ITEM
NON_REM 1 : NON_REM 0 STRAP PIN CFG

BYPASS=U2700.5::2MM
D 26 8 =PP3V3_S3_USB_HUB BYPASS=U27000.5::5MM 0
0
1
1
:
:
:
:
0
1
0
1
ALL PORTS ARE REMOVABLE
PORT 1 IS NON REMOVABLE
PORT 1&2 ARE NON REMOVABLE
PORT 1&2&3 ARE NON REMOVABLE
D
C2700 1 C2701 1 1 C2702 1 C2703 CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STRAPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H
4.7UF 0.1UF 0.1UF 0.1UF
20% 10% 10% 10% TABLE_5_HEAD
6.3V 2 16V 2 16V 16V

X5R X7R-CERM 2 X7R-CERM 2 X7R-CERM PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
603 0402 0402 0402
197S0485 1 XTAL,24MHZ,60PPM,16PF,2.5X2X0.55MM,90C Y2700 CRITICAL
TABLE_5_ITEM
BOM TABLE TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

BYPASS=U2700.15::2MM CRITICAL USBHUB:2514B
TABLE_5_ITEM
338S0824 1 USB HUB 2514B U2700

BYPASS=U2700.10::2MM
CRITICAL USBHUB:2513B
TABLE_5_ITEM
BYPASS=U2700.23::5MM BYPASS=U2700.23::2MM 338S0923 1 USB HUB 2513B U2700

CRITICAL USBHUB:2512B
TABLE_5_ITEM
338S0983 1 USB HUB 2512B U2700

C2704 1 C2705 1 C2706 1 C2708 1 PPUSB_HUB2_VDD1V8
4.7UF 0.1UF 0.1UF 0.1UF MIN_LINE_WIDTH=0.4MM D1,D2 ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B
20% 10% 10% 10% MIN_NECK_WIDTH=0.2MM
6.3V 2 16V 16V 16V J3X ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B
X5R X7R-CERM 2 X7R-CERM 2 X7R-CERM 2 VOLTAGE=1.8V 1 C2713 1 C2714
603 0402 0402 0402 PPUSB_HUB2_VDD1V8PLL
MIN_LINE_WIDTH=0.4MM 0.1UF 1UF
MIN_NECK_WIDTH=0.2MM 10% 10%
10
15
23
29
36
14
34
CRITICAL 2 16V 16V
5
VOLTAGE=1.8V 2 X5R
Y2700 BYPASS=U2700.36::2MM 1 C2711 1 C2712 X7R-CERM
0402 402
OMIT_TABLE 0.1UF 1UF
CRFILT
PLLFILT
SM-2 BYPASS=U2650.29::2MM VDD33
24.000MHZ-16PF 10% 10%
16V
2 X7R-CERM 2 16V
1 3 X5R
CRITICAL 0402 402
2 4 CRITICAL SYM VER 1 =PP3V3_S3_USB_HUB
C2709 1 U2700
8 26
NC
NC
18PF 1 C2710
5% USB2513B NOSTUFFNOSTUFF NOSTUFFNOSTUFF NOSTUFF NOSTUFF
50V 18PF 1
R27161R2717 1
R27181R2719 1
R2722 1R2723
CERM 2
402 R2700 5% R2701 QFN
2 50V
CERM 100 11 10K 10K 10K 10K 10K 10K
HUB_NONREM1_1 HUB_NONREM0_1 1M 402 1 2 USB_HUB_TEST TEST OMIT_TABLE USBDM_DN1/PRT_DIS_M1 1 USBHUB_DN1_N BI 9 5% 5% 5% 5% 5% 5%
1 2 BLUETOOTH FOR D1/D2 & J3X 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
1 1 5%
26 USBDP_DN1/PRT_DIS_P1 2 USBHUB_DN1_P BI 9 MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
R2702 R2703 5% 1/16W USB_HUB_RESET_L RESET* 2 402 2 402 2 402 2 402 2 402 2 402
C 10K
5%
10K
5%
1/16W
MF-LF
402
MF-LF
402
26
USB_HUB_XTAL1 33 XTALIN/CLKIN
USBDM_DN2/PRT_DIS_M2 3 USBHUB_DN2_N 9 26
TRACKPAD/KEYBOARD FOR D1/D2, IR FOR J3X
C
1/16W 1/16W CRITICAL 32 USBDP_DN2/PRT_DIS_P2 4 USBHUB_DN2_P 9 26
MF-LF MF-LF USB_HUB_XTAL2 XTALOUT 26 9 USBHUB_DN3_N
402 2 2 402
28 USBDM_DN3/PRT_DIS_M3 6 USBHUB_DN3_N BI 9 26 26 9 USBHUB_DN3_P
USB_HUB_NONREM0 SUSP_IND/LOCAL_PWR/NON_REM0 SMC DEBUG PORT FOR D1/D2, TPAD/KBD FOR J3X
USBDP_DN3/PRT_DIS_P3 7 USBHUB_DN3_P BI 9 26
USB_HUB_NONREM1 22 SDA/SMBDATA/NON_REM1 26 9 USBHUB_DN4_N

NC 8 USBHUB_DN4_N BI 9 26
24 NC FOR D1/D2, SMC DEBUG PORT FOR J3X 26 9 USBHUB_DN4_P
HUB_NONREM1_0 HUB_NONREM0_0 USB_HUB_CFG_SEL0 SCL/SMBCLK/CFG_SEL0 NC 9 USBHUB_DN4_P BI 9 26
R27041 1
R2705 USB_HUB_CFG_SEL1 25 HS_IND/CFG_SEL1 PRTPWR1/BC_EN1* 12
16
TP_USB_HUB_PRTPWR1 26 9 USBHUB_DN2_N
10K 10K PRTPWR2/BC_EN2* TP_USB_HUB_PRTPWR2
5% 5% 18 =PP3V3_S3_USB_HUB 26 9 USBHUB_DN2_P
1/16W 1/16W 1 PRTPWR3/BC_EN3* TP_USB_HUB_PRTPWR3 8 26
MF-LF
402 2
MF-LF
2 402
R2706 1R2707 NC 20 TP_USB_HUB_PRTPWR4
10K 10K
5% 5% 13
1/16W 1/16W IPU OCS1* TP_USB_HUB_OCS1 1
MF-LF
2 402
MF-LF
2 402 IPU OCS2* 17 TP_USB_HUB_OCS2 R2708
19 10K
IPU OSC3* TP_USB_HUB_OCS3 5%
21 1/16W
IPU NC TP_USB_HUB_OCS4 MF-LF
2 402
RBIAS 35 USB_HUB_RBIAS
J5 USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION
VBUS_DET 27 USB_HUB_VBUS_DET
J3X USE 197S0284 FOR Y2700 TO SAVE COST CKPLUS_WAIVE=ndifpr_badterm CRITICAL
USBDM_UP 30 USB_HUB_UP_N BI 19 74
1
R2709
USBDP_UP 31 USB_HUB_UP_P BI 19 74 12K TO CONNECT TP/KB TO PCH XHCI
1%
THRM_PAD 1/16W NOSTUFF R5701 & R5702, STUFF R2720 & R2721
8 =PP3V3_S3_USB_RESET
PCH PORT 7 (EHCI1) MF
2 402 NOSTUFF
37
R2720
27
74 19 BI USB_EXTD_XHCI_N 1 2 USB_TPAD_R_N BI 47 78
B 1 TO PCH XHCI
NOSTUFF
R2721
5%
1/16W TO TP/KB B
R2712 27
MF-LF
402
10K 74 19 BI USB_EXTD_XHCI_P 1 2 USB_TPAD_R_P BI 47 78
5%
1/16W 5%
MF-LF 1/16W
2 402 MF-LF
402
USB_HUB_RESET_L 26
C2715 1
0.1UF
10%
16V
X7R-CERM 2
0402
BYPASS=U2700.26::2MM
USB XHCI/EHCI2 PORT MUX FOR EXT B
8 =PP3V3_S3_USBMUX
C2760 1
9
0.1UF
20%
10V VCC
CERM 2
19
402
USB_EXTB_EHCI_P 5 M+ Y+ 1 USB_EXTB_P 7 36 74
BI BI
PCH PORT 9 (EHCI2) 74
USB_EXTB_EHCI_N 4 M- Y- 2 USB_EXTB_N TO CONNECTOR
74 19 BI U2760 BI 7 36 74
A 19 BI USB_EXTB_XHCI_P 7 D+
PI3USB102ZLE
TQFN SYNC_MASTER=J5_AMD SYNC_DATE=08/17/2011 A
PCH PORT 1 (XHCI) 74
USB_EXTB_XHCI_N 6 D- CRITICAL PAGE TITLE
74 19 BI
PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE USB HUB & MUX
8 OE* SEL 10 USB_EXTB_SEL_XHCIIN 17 DRAWING NUMBER SIZE
PCH GPIO60 <SCH_NUM> D
GND SEL=0 CHOOSE USB EHCI2 PORT Apple Inc. REVISION
SEL=1 CHOOSE USB XHCI PORT
3
R
<E4LABEL>
<BRANCH>
27 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well
as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.
ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.
WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated. D
D WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.
P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L
MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L
1V35 S0 "PGOOD" for CPU
MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L 8 =PP3V3_S5_CPU_VCCDDR
66 39 38 36 27 18 7 IN PM_SLP_S4_L PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

1 =PP1V5R1V35_S3_CPU_VCCDDR PM_MEM_PWRGD
R2805 16 13 11 8 OUT 11 18 72
10K 1
R2822
5%
1/16W 10K
MF-LF 5%
2 402 1/16W CRITICAL 6
MF-LF
P1V5CPU_EN 2 402 D Q2820
CRITICAL OUT 27 65
R28201
27.4K DMB53D0UV
27 8 =PP3V3_S3_MEMRESET CPUMEM:S0 1% SOT-563
1/16W
CPUMEM:S0 Q2805 D 6 MF-LF
402 2
PM_MEM_PWRGD_L 2 G
R28011 SSM6N37FEAPE
SOT563
100K
5% 3 CRITICAL
1/16W
MF-LF
402 2 2 G S 1 P1V35_S0_DIV 5 Q2820 S
NO STUFF DMB53D0UV 1
1 P1V5CPU_EN_L SOT-563
R2895 CRITICAL CRITICAL 4
20K
5%
1/16W
CPUMEM:S0
D 3 3 D
CPUMEM:S0 R28211 C2820 1
MF-LF Q2800 Q2805 33.2K 0.047UF
2 402 SSM6N37FEAPE SSM6N37FEAPE 1% 10%
C SOT563 SOT563
1/16W
MF-LF
402 2
10V
X5R-CERM 2
0402
C
CPUMEM:S0
R2890 5 G S 4 4 S G 5
0
27 24 IN ISOLATE_CPU_MEM_L 2 1 ISOLATE_CPU_MEM_L_R PM_SLP_S3_L IN 7 18 27 36 39 66
5%
1/20W
1
MF
201 R2810 27 8 =PP3V3_S3_MEMRESET
10K
5%
1/16W
MF-LF CPUMEM:SLG
2 402 CPUMEM:SLG
C2800 1
10
MEMVTT_EN OUT 9 27
0.1UF
10%
=PP5V_S3_MEMRESET
27 8
CPUMEM:S0 CPUMEM:S0
CRITICAL
CPUMEM:S0
Q2810 D 6
6.3V
X5R
201
2
U2800
VDD
SLG4AP022
MEMVTT Clamp
1 1 SSM6N37FEAPE TQFN Ensures CKE signals are held low in S3
R2815 R2802 SOT563 27 25 19 IN PLT_RESET_L 1 S0_READY
100K 100K VTT_EN 2 MEMVTT_EN OUT 9 27
5% 5%
1/16W 1/16W 27 24 IN ISOLATE_CPU_MEM_L 9 ISOL*
MF-LF MF-LF
402 2 402 2 2 G S 1 VDDIO_EN 4 P1V5CPU_EN OUT 27 65 8 =PPVTT_S0_VTTCLAMP
66 39 36 27 18 7 IN PM_SLP_S3_L 3 S0_EN
CRITICAL MEMVTT_EN_L
CRITICAL CRITICAL 66 39 38 36 27 18 7 IN PM_SLP_S4_L 6 S3_EN RST_OUT* 8 MEM_RESET_LOUT 27 28 29 R28501
CPUMEM:S0 CPUMEM:S0 10 75mA max load @ 0.75V
CPUMEM:S0 D 6 3 D =MEM_RESET_L 7 RST_IN* 5%
Q2815 Q2800 Q2810 27 11 IN
THRM
1/10W
MF-LF
60mW max power
NOSTUFF SSM6N37FEAPE SSM6N37FEAPE GND PAD 603 2
SSM6N37FEAPE SOT563 SOT563
C2817 1
11
VTTCLAMP_L
G 2
0.047UF SOT563 CRITICAL

10%
6.3V 2 2 G =PP5V_S3_MEMRESET
X5R S 1 4 S G 5 27 8
Q2850 D 6
B 201
B
6 D
1 S
PLT_RESET_L IN 19 25 27
SSM6N37FEAPE
R28511 SOT563
100K
5%
1/16W
MF-LF
402 2 2 G S 1
CRITICAL =PP1V5_S3_MEMRESET 8
CPUMEM:S0 CRITICAL VTTCLAMP_EN
Q2815 1 CPUMEM:S0
SSM6N37FEAPE R2816 1 C2816 NO STUFF
MEMRESET_ISOL_LS5V_L
1K 0.1UF Q2850 D 3
C2851 1
5
31 SOT563 5% 10% SSM6N37FEAPE

1/16W
G
MF-LF 16V
2 X7R-CERM SOT563 0.047UF
10%
2 402 0402 10V
CERM 2
S
3 D
27 11 =MEM_RESET_L CPU_MEM_RESET_L MEM_RESET_L 27 28 29

402
IN OUT
MAKE_BASE=TRUE 5 G S 4
4
60 9 IN =DDRVTT_EN
CPUMEM:S3
R2817
1
0 2
5%
1/16W
MF-LF
402
Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

S0 0 1 1 1 1 1 CPU_MEM_RESET_L 1 1
1 0 1 1 1 1 1 1 1
to 2 0 0 1 1 1 1 0 1
3 0 0 0 1 X 1 0 0
A S3 4 0 0 1 1 X 1 0 1
PAGE TITLE
to 5
6
0
0
1
1
1
1
1
1
0 (*)
1
1
1
1
1
1
1
CPU Memory S3 Support
DRAWING NUMBER SIZE
S0 7 1 1 1 1 1 CPU_MEM_RESET_L 1 1
REVISION
(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO. R
<E4LABEL>
NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 28 OF 132
must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
72 31 28 PP0V75_S3_MEM_VREFDQ_A 72 31 28 PP0V75_S3_MEM_VREFDQ_A 72 31 28 PP0V75_S3_MEM_VREFDQ_A 72 31 28 PP0V75_S3_MEM_VREFDQ_A
72 31 28 PP0V75_S3_MEM_VREFCA_A 72 31 28 PP0V75_S3_MEM_VREFCA_A 72 31 28 PP0V75_S3_MEM_VREFCA_A 72 31 28 PP0V75_S3_MEM_VREFCA_A
=PP1V5R1V35_S3_MEM_A 8 28 =PP1V5R1V35_S3_MEM_A 8 28 =PP1V5R1V35_S3_MEM_A 8 28 =PP1V5R1V35_S3_MEM_A 8 28
C2907 1
C2917 1 C2927 1 C2937 1
0.47UF C2908 1 1 C2909 C2918 1 1 C2919 C2928 1 1 C2929 C2938 1 1 C2939
20% 0.47UF 0.47UF 0.47UF
4V 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF
CERM-X5R-1 2 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
201 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 4V
CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 2 CERM-X5R-1
201 201 201 201 201 201 201 201
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
VDD VDDQ VDD VDDQ VDD VDDQ VDD VDDQ
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE

28 12 MEM_A_A<0> K3 A0 73 30 28 12 MEM_A_A<0> K3 A0 73 30 28 12 MEM_A_A<0> K3 A0 73 30 28 12 MEM_A_A<0> K3 A0
D
73 30
28
73
12
30
MEM_A_A<1> L7 A1 U2900
RESET* N2 MEM_RESET_L 73 30 28 12
27 28 29
MEM_A_A<1> L7 A1 U2910
27 28 29
MEM_A_A<1> L7 A1 U2920
27 28 29
MEM_A_A<1> L7 A1 U2930
RESET* N2 MEM_RESET_L 27 28 29
D
28 12 MEM_A_A<2> L3 A2 FBGA-10.1X12.6-J4 73 30 28 12 MEM_A_A<2> L3 A2 FBGA-10.1X12.6-J4 73 30 28 12 MEM_A_A<2> L3 A2 FBGA-10.1X12.6-J4 73 30 28 12 MEM_A_A<2> L3 A2 FBGA-10.1X12.6-J4
512MX8-4GBIT-DDR3-1600
MT41K1G4
MT41K1G4
MT41K1G4
MT41K1G4
73 30
28
73
12
30
MEM_A_A<3> K2 A3 DQ0 B3 MEM_A_DQ<5> 12 73
7 28 12
73 30
MEM_A_A<3> K2 A3 DQ0 B3 MEM_A_DQ<9> 12 73
7 28 12 MEM_A_A<3> K2 A3 DQ0 B3 MEM_A_DQ<21> 12 73
7 28 12 MEM_A_A<3> K2 A3 DQ0 B3 MEM_A_DQ<28> 7 12 73
73 30 73 30
28 12
73 30
MEM_A_A<4> L8 A4 DQ1 C7 MEM_A_DQ<6> 28 12 MEM_A_A<4> L8 A4 DQ1 C7 MEM_A_DQ<10> 28 12 MEM_A_A<4> L8 A4 DQ1 C7 MEM_A_DQ<23> 28 12 MEM_A_A<4> L8 A4 DQ1 C7 MEM_A_DQ<25> 12 73
73 30 73 30 73 30
28 12 MEM_A_A<5> L2 A5 DQ2 C2 MEM_A_DQ<4> 28 12 MEM_A_A<5> L2 A5 DQ2 C2 MEM_A_DQ<13> 28 12 MEM_A_A<5> L2 A5 DQ2 C2 MEM_A_DQ<20> 28 12 MEM_A_A<5> L2 A5 DQ2 C2 MEM_A_DQ<29> 7 12 73
73 30 73 30 73 30 73 30
28 12
73 30
MEM_A_A<6> M8 A6 DQ3 C8 MEM_A_DQ<7> 28 12
73 30
MEM_A_A<6> M8 A6 DQ3 C8 MEM_A_DQ<15> 28 12 MEM_A_A<6> M8 A6 DQ3 C8 MEM_A_DQ<22> 28 12 MEM_A_A<6> M8 A6 DQ3 C8 MEM_A_DQ<31> 7 12 73
73 30 73 30
28 12 MEM_A_A<7> M2 A7 NF_DQ4 E3 MEM_A_DQ<1> 28 12 MEM_A_A<7> M2 A7 NF_DQ4 E3 MEM_A_DQ<8> 28 12 MEM_A_A<7> M2 A7 NF_DQ4 E3 MEM_A_DQ<16> 28 12 MEM_A_A<7> M2 A7 NF_DQ4 E3 MEM_A_DQ<30> 7 12 73
73 30 73 30 73 30 73 30
28
73
12
30
MEM_A_A<8> N8 A8 NF_DQ5 E8 MEM_A_DQ<3> 28 12 MEM_A_A<8> N8 A8 NF_DQ5 E8 MEM_A_DQ<12> 28 12 MEM_A_A<8> N8 A8 NF_DQ5 E8 MEM_A_DQ<19> 28 12 MEM_A_A<8> N8 A8 NF_DQ5 E8 MEM_A_DQ<26> 7 12 73
73 30 73 30 73 30
28
73
12
30
MEM_A_A<9> M3 A9 NF_DQ6 D2 MEM_A_DQ<0> 28 12 MEM_A_A<9> M3 A9 NF_DQ6 D2 MEM_A_DQ<14> 28 12 MEM_A_A<9> M3 A9 NF_DQ6 D2 MEM_A_DQ<17> 28 12 MEM_A_A<9> M3 A9 NF_DQ6 D2 MEM_A_DQ<24> 7 12 73
73 30 73 30 73 30
28 12 MEM_A_A<10> H7 A10/AP NF_DQ7 E7 MEM_A_DQ<2> 28 12 MEM_A_A<10> H7 A10/AP NF_DQ7 E7 MEM_A_DQ<11> 28 12 MEM_A_A<10> H7 A10/AP NF_DQ7 E7 MEM_A_DQ<18> 28 12 MEM_A_A<10> H7 A10/AP NF_DQ7 E7 MEM_A_DQ<27> 7 12 73
73 30 73 30 73 30 73 30
28 12 MEM_A_A<11> M7 A11 28 12 MEM_A_A<11> M7 A11 28 12 MEM_A_A<11> M7 A11 28 12 MEM_A_A<11> M7 A11
73 30 DQS C3 MEM_A_DQS_P<0> 73 30 C3
DQS MEM_A_DQS_P<1> 73 30 DQS C3 MEM_A_DQS_P<2> 73 30 DQS C3 MEM_A_DQS_P<3> 12 73
28 12 MEM_A_A<12> K7 A12/BC* 28 12 MEM_A_A<12> K7 A12/BC* 28 12 MEM_A_A<12> K7 A12/BC* 28 12 MEM_A_A<12> K7 A12/BC*
73 30 DQS* D3 MEM_A_DQS_N<0> 73 30 DQS* D3 MEM_A_DQS_N<1> 73 30 DQS* D3 MEM_A_DQS_N<2> 73 30 DQS* D3 MEM_A_DQS_N<3> 12 73
28 12 MEM_A_A<13> N3 A13 73 30 28 12 MEM_A_A<13> N3 A13 73 30 28 12 MEM_A_A<13> N3 A13 73 30 28 12 MEM_A_A<13> N3 A13
73 30
28 12
73 30
MEM_A_A<14> N7 A14 DM/TDQS B7 73 30 28 12 MEM_A_A<14> N7 A14 DM/TDQS B7 73 30 28 12 MEM_A_A<14> N7 A14 DM/TDQS B7 73 30 28 12 MEM_A_A<14> N7 A14 DM/TDQS B7
28 12 MEM_A_A<15> J7 A15 NF_TDQS* A7 NC 73 30 28 12 MEM_A_A<15> J7 A15 NF_TDQS* A7 NC 73 30 28 12 MEM_A_A<15> J7 A15 NF_TDQS* A7 NC 73 30 28 12 MEM_A_A<15> J7 A15 NF_TDQS* A7 NC
73 30
28 12 MEM_A_BA<0> J2 BA0 H1MEM_A_CS_L<1>

73
30 28 12 MEM_A_BA<0> J2 BA0 H1MEM_A_CS_L<1> 30 28 12 MEM_A_BA<0> J2 BA0 H1MEM_A_CS_L<1> 30 28 12 MEM_A_BA<0> J2 BA0 H1MEM_A_CS_L<1>
73 30 CS1* 12 28 30 CS1* 73 CS1* 73 CS1* 12 28 30 73
28 12 MEM_A_BA<1> K8 BA1 H2MEM_A_CS_L<0>
73 12 MEM_A_BA<1> K8 BA1 H2MEM_A_CS_L<0> 30 28 12 MEM_A_BA<1> K8 BA1 H2MEM_A_CS_L<0> 30 28 12 MEM_A_BA<1> K8 BA1 H2MEM_A_CS_L<0>
73 30 CS0* 73 30 28 CS0* 73 CS0* 73 CS0* 12 28 30 73
28 12 MEM_A_BA<2> J3 BA2 73 30 28 12 MEM_A_BA<2> J3 BA2 73 30 28 12 MEM_A_BA<2> J3 BA2 73 30 28 12 MEM_A_BA<2> J3 BA2
73 30
CKE0 G9 MEM_A_CKE<0> CKE0 G9 MEM_A_CKE<0> CKE0 G9 MEM_A_CKE<0> CKE0 G9 MEM_A_CKE<0>
73
12 28 30 12 28 30 12 28 30 12 28 30 73
28 12 MEM_A_RAS_L F3 RAS* 73 12 MEM_A_RAS_L F3 RAS* 73 MEM_A_RAS_L F3 RAS* 30 28 12 MEM_A_RAS_L F3 RAS*
73 30 CKE1 F9 MEM_A_CKE<1> 73 30 28 CKE1 F9 MEM_A_CKE<1> 12 28 30 CKE1 F9 MEM_A_CKE<1> 12 73 CKE1 F9 MEM_A_CKE<1> 12 28 30 73
28 12
73 30
MEM_A_CAS_L G3 CAS* 73 30 28 12 MEM_A_CAS_L G3 CAS* 73 12
30 28
MEM_A_CAS_L G3 CAS* 73 30 28 12 28 30 73 MEM_A_CAS_L G3 CAS*
28 12
73 30
MEM_A_WE_L H3 WE* CK F7 MEM_A_CLK_P<0> 28 12 MEM_A_WE_L H3 WE* CK F7 MEM_A_CLK_P<0> 12
73 MEM_A_WE_L H3 WE* CK F7 MEM_A_CLK_P<0> 28 12 MEM_A_WE_L H3 WE* CK F7 MEM_A_CLK_P<0> 12 28 30 73
73 30 28 30 73 73 30
28 12
73 30
MEM_A_ODT<0> G1 ODT0 CK* G7 MEM_A_CLK_N<0> 28 12 MEM_A_ODT<0> G1 ODT0 CK* G7 MEM_A_CLK_N<0> 28 12 MEM_A_ODT<0> G1 ODT0 CK* G7 MEM_A_CLK_N<0> 28 12 MEM_A_ODT<0> G1 ODT0 CK* G7 MEM_A_CLK_N<0> 12 28 30 73
73 30 73 30 73 30
28 12 MEM_A_ODT<1> F1 ODT1 A3 73 30 28 12 MEM_A_ODT<1> F1 ODT1 A3 73 30 28 12 MEM_A_ODT<1> F1 ODT1 A3 NC 73 30 28 12 MEM_A_ODT<1> F1 ODT1 A3
73 30
NC NC NC
MEM_A_ZQ<0> H8 ZQ0 79 MEM_A_ZQ<1> H8 ZQ0 79 MEM_A_ZQ<2> H8 ZQ0 79 NC MEM_A_ZQ<3> H8 ZQ0 79
NC NC NC
MEM_A_ZQ<4> H9 ZQ1 80 MEM_A_ZQ<5> H9 ZQ1 80 MEM_A_ZQ<6> H9 ZQ1 80 NC MEM_A_ZQ<7> H9 ZQ1 80
NC NC NC
C NC 81
NC
NC 81
NC
NC 81 NC NC 81
NC C
2
1
82 82 82 NC 82
2 NC 2 NC 2 2 NC
R2900 R2901 VSS VSSQ R2910 R2911 VSS VSSQ R2920 R2921 VSS VSSQ R2930 R2931 VSS VSSQ
240 240 240 240 240 240 240 240
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
1% 1% 1% 1% 1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
MF MF MF MF MF MF MF MF
201 1 201 201 1 201 201 1 201 201 1 201
1
2
72 31 28 PP0V75_S3_MEM_VREFDQ_A 72 31 28 PP0V75_S3_MEM_VREFDQ_A 72 31 28 PP0V75_S3_MEM_VREFDQ_A 72 31 28 PP0V75_S3_MEM_VREFDQ_A
72 31 28 PP0V75_S3_MEM_VREFCA_A 72 31 28 PP0V75_S3_MEM_VREFCA_A 72 31 28 PP0V75_S3_MEM_VREFCA_A 72 31 28 PP0V75_S3_MEM_VREFCA_A
=PP1V5R1V35_S3_MEM_A 8 28 =PP1V5R1V35_S3_MEM_A 8 28 =PP1V5R1V35_S3_MEM_A 8 28 =PP1V5R1V35_S3_MEM_A 8 28
C2947 1
C2948 1 1 C2949 C2957 1
C2958 1 1 C2959 C2967 1 C2968 1 1 C2969 C2977 1 C2978 1 1 C2979
0.47UF 0.47UF 0.47UF 0.47UF
20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF 20% 0.47UF 0.47UF
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V
201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1
201 201 201 201 201 201 201 201
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
28 12 MEM_A_A<0> K3 A0 73 30 28 12 MEM_A_A<0> K3 A0 73 30 28 12 MEM_A_A<0> K3 A0 73 30 28 12 MEM_A_A<0> K3 A0
73 30
28 12 MEM_A_A<1> L7 A1 U2940 MEM_RESET_L 73 30 28 12 MEM_A_A<1> L7 A1 U2950 MEM_RESET_L 73 30 28 12 MEM_A_A<1> L7 A1 U2960 MEM_RESET_L 73 30 28 12 MEM_A_A<1> L7 A1 U2970 MEM_RESET_L
73 30 RESET* N2 27 28 29 RESET* N2 27 28 29 RESET* N2 27 28 29 RESET* N2 27 28 29
28 12 MEM_A_A<2> L3 A2 FBGA-10.1X12.6-J4 73 30 28 12 MEM_A_A<2> L3 A2 FBGA-10.1X12.6-J4 73 30 28 12 MEM_A_A<2> L3 A2 FBGA-10.1X12.6-J4 73 30 28 12 MEM_A_A<2> L3 A2 FBGA-10.1X12.6-J4
MT41K1G4
MT41K1G4
MT41K1G4
MT41K1G4
73 30
28 12 MEM_A_A<3> K2 A3 DQ0 B3 MEM_A_DQ<32> 12 73
7 28 12 MEM_A_A<3> K2 A3 DQ0 B3 MEM_A_DQ<56> 7 12 73
73 30 73 30 73 30 73 30
28 12
73 30
MEM_A_A<4> L8 A4 DQ1 C7 MEM_A_DQ<39> 28 12
73 30
73 30
MEM_A_A<4> L8 A4 DQ1 C7 MEM_A_DQ<55> 28 12 MEM_A_A<4> L8 A4 DQ1 C7 MEM_A_DQ<62> 7 12 73
73 30
28 12
73 30
73 30
73 30
73 30
MEM_A_A<5> L2 A5 DQ2 C2 MEM_A_DQ<60> 7 12 73
28 12
73 30
MEM_A_A<6> M8 A6 DQ3 C8 MEM_A_DQ<35> 28 12
73 30
MEM_A_A<6> M8 A6 C8 DQ3 MEM_A_DQ<46> 28 12
73 30
MEM_A_A<6> M8 A6 C8DQ3 MEM_A_DQ<54> 28 12 MEM_A_A<6> M8 A6 DQ3 C8 MEM_A_DQ<59> 7 12 73
73 30
28 12
73 30
MEM_A_A<7> M2 A7 NF_DQ4 E3 MEM_A_DQ<36> 28
73
12
30
MEM_A_A<7> M2 A7 NF_DQ4 E3 MEM_A_DQ<45> 28 12
73 30
MEM_A_A<7> M2 A7 NF_DQ4 E3 MEM_A_DQ<53> 28 12
73 30
MEM_A_A<7> M2 A7 NF_DQ4 E3 MEM_A_DQ<61> 7 12 73
28 12 MEM_A_A<8> N8 A8 NF_DQ5 E8 MEM_A_DQ<38> 28 12 MEM_A_A<8> N8 A8 NF_DQ5 E8 MEM_A_DQ<42> 28 12 MEM_A_A<8> N8 A8 NF_DQ5 E8 MEM_A_DQ<51> 28 12 MEM_A_A<8> N8 A8 NF_DQ5 E8 MEM_A_DQ<63> 7 12 73
73 30 73 30 73 30 73 30
B 28
73
28 12
12
30
MEM_A_A<9>
MEM_A_A<10>
M3
H7
A9
A10/AP
NF_DQ6 D2
NF_DQ7 E7
MEM_A_DQ<37>
MEM_A_DQ<34>
28
73
28 12
12
30
MEM_A_A<9>
MEM_A_A<10>
M3
H7
A9
A10/AP
NF_DQ6 D2
NF_DQ7 E7
MEM_A_DQ<40>
MEM_A_DQ<47>
7 12 73
12 73
7 28 12
MEM_A_A<9>
MEM_A_A<10>
M3
H7
A9
A10/AP
NF_DQ6 D2
NF_DQ7 E7
MEM_A_DQ<49>
MEM_A_DQ<50>
28
73
28 12
12
30
MEM_A_A<9>
MEM_A_A<10>
M3
H7
A9
A10/AP
NF_DQ6 D2
NF_DQ7 E7
MEM_A_DQ<57>
MEM_A_DQ<58>
12 73
7 12 73
B
73 30 73 30 73 30 73 30
28 12 MEM_A_A<11> M7 A11 28 12 MEM_A_A<11> M7 A11 28 12 MEM_A_A<11> M7 A11 28 12 MEM_A_A<11> M7 A11
73 30 DQS C3 MEM_A_DQS_P<4> 73 30 DQS C3 MEM_A_DQS_P<5> 73 30 DQS C3 MEM_A_DQS_P<6> 73 30 DQS C3 MEM_A_DQS_P<7> 12 73
28 12 MEM_A_A<12> K7 A12/BC* 28 12 MEM_A_A<12> K7 A12/BC* 28 12 MEM_A_A<12> K7 A12/BC* 28 12 MEM_A_A<12> K7 A12/BC*
73 30 DQS* D3 MEM_A_DQS_N<4> 73 30 DQS* D3 MEM_A_DQS_N<5> 73 30 DQS* D3 MEM_A_DQS_N<6> 73 30 DQS* D3 MEM_A_DQS_N<7> 12 73
28 12
73 30
MEM_A_A<13> N3 A13 73 30 28 12 MEM_A_A<13> N3 A13 73 30 28 12 MEM_A_A<13> N3 A13 73 30 28 12 MEM_A_A<13> N3 A13
28 12 MEM_A_A<14> N7 A14 DM/TDQS B7 73 30 28 12 MEM_A_A<14> N7 A14 DM/TDQS B7 73 30 28 12 MEM_A_A<14> N7 A14 DM/TDQS B7 73 30 28 12 MEM_A_A<14> N7 A14 DM/TDQS B7
73 30
28 12
73 30
MEM_A_A<15> J7 A15 NF_TDQS* A7 NC 73 30 28 12 MEM_A_A<15> J7 A15 NF_TDQS* A7 NC 73 30 28 12 MEM_A_A<15> J7 A15 NF_TDQS* A7 NC 73 30 28 12 MEM_A_A<15> J7 A15 NF_TDQS* A7 NC
28 12 MEM_A_BA<0> J2 BA0 H1MEM_A_CS_L<1> 30 28 12 MEM_A_BA<0> J2 BA0 H1MEM_A_CS_L<1> 30 28 12 MEM_A_BA<0> J2 BA0 H1MEM_A_CS_L<1> 30 28 12 MEM_A_BA<0> J2 BA0 H1MEM_A_CS_L<1>
73 30 CS1* 73 CS1* 73 CS1* 73 CS1* 12 28 30 73
28 12 MEM_A_BA<1> K8 BA1 H2MEM_A_CS_L<0> 30 28 12 MEM_A_BA<1> K8 BA1 H2MEM_A_CS_L<0> 30 28 12 MEM_A_BA<1> K8 BA1 H2MEM_A_CS_L<0> 30 28 12 MEM_A_BA<1> K8 BA1 H2MEM_A_CS_L<0>
73 30 CS0* 73 CS0* 73 CS0* 73 CS0* 12 28 30 73
28 12
73 30
MEM_A_BA<2> J3 BA2 73 30 28 12 MEM_A_BA<2> J3 BA2 73 30 28 12 MEM_A_BA<2> J3 BA2 73 30 28 12 MEM_A_BA<2> J3 BA2
CKE0 G9 MEM_A_CKE<0> 73
12 28 30 CKE0 G9 MEM_A_CKE<0> 73
12 28 30 CKE0 G9 MEM_A_CKE<0> 73
12 28 30 CKE0 G9 MEM_A_CKE<0> 12 28 30 73
28 12 MEM_A_RAS_L F3 RAS* 30 28 12 MEM_A_RAS_L F3 RAS* 30 28 12 MEM_A_RAS_L F3 RAS* 30 28 12 MEM_A_RAS_L F3 RAS*
73 30 CKE1 F9 MEM_A_CKE<1> 73 CKE1 F9 MEM_A_CKE<1> 73 CKE1 F9 MEM_A_CKE<1> 73 CKE1 F9 MEM_A_CKE<1> 12 28 30 73
28 12
73 30
MEM_A_CAS_L G3 CAS* 73 30 28 12 MEM_A_CAS_L G3 CAS* 73 30 28 12 MEM_A_CAS_L G3 CAS* 73 30 28 12 MEM_A_CAS_L G3 CAS*
28 12 MEM_A_WE_L H3 WE* CK F7 MEM_A_CLK_P<0> 28 12 MEM_A_WE_L H3 WE* CK F7 MEM_A_CLK_P<0> 28 12 MEM_A_WE_L H3 WE* CK F7 MEM_A_CLK_P<0> 28 12 MEM_A_WE_L H3 WE* CK F7 MEM_A_CLK_P<0> 12 28 30
73 30 73 30 73 30 73 30 73
28 12
73 30
MEM_A_ODT<0> G1 ODT0 CK* G7 MEM_A_CLK_N<0> 28 12
73 30
73 30
73 30
MEM_A_ODT<0> G1 ODT0 CK* G7 MEM_A_CLK_N<0> 12 28 30 73
28 12
73 30
MEM_A_ODT<1> F1 ODT1 A3 73 30 28 12 MEM_A_ODT<1> F1 ODT1 A3 73 30 28 12 MEM_A_ODT<1> F1 ODT1 A3 73 30 28 12 MEM_A_ODT<1> F1 ODT1 A3
NC NC NC NC
MEM_A_ZQ<8> H8 ZQ0 79 MEM_A_ZQ<9> H8 ZQ0 79 MEM_A_ZQ<10> H8 ZQ0 79 MEM_A_ZQ<11> H8 ZQ0 79
NC NC NC NC
MEM_A_ZQ<12> H9 ZQ1 80
NC MEM_A_ZQ<13> H9 ZQ1 80
NC
NC 81 NC 81 NC 81 NC 81
NC NC NC NC
1
1
82 82 82 82
2 NC 2 NC 2 NC 2 NC
R2940 R2941 VSS VSSQ R2950 R2951 VSS VSSQ R2960 R2961 VSS VSSQ R2970 R2971 VSS VSSQ
240 240 240 240 240 240 240 240
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
1% 1% 1% 1% 1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
201 1 201 201 1 201 201 1 201 201 1 201
2
2
=PP1V5R1V35_S3_MEM_A 8 28
SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)
PAGE TITLE
C2900 1 C2901 1 C2910 1 C2911 1 C2920 1 C2921 1 C2930 1 C2931 1 1 C2903 1 C2904 1 C2905 1 C2913 1 C2914 1 C2915 1 C2923 1 C2924 1 C2925 1 C2933 1 C2934 1 C2935 DDR3 SDRAM Bank A (Rank 0)
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% DRAWING NUMBER SIZE
10V 10V 10V 10V 10V 10V 10V 10V 2 6.3V 6.3V 6.3V 2 6.3V 6.3V 2 6.3V 6.3V 6.3V 2 6.3V 6.3V 6.3V 2 6.3V
X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R 2 X5R 2 X5R X5R 2 X5R X5R 2 X5R 2 X5R X5R 2 X5R 2 X5R X5R <SCH_NUM> D
402 402 402 402 402 402 402 402 201 201 201 201 201 201 201 201 201 201 201 201
Apple Inc. REVISION
R
<E4LABEL>
C2940 1 C2941 1 C2950 1 C2951 1 C2960 1 C2961 1 C2970 1 C2971 1 1 C2943 1 C2944 1 C2945 1 C2953 1 C2954 1 C2955 1 C2963 1 C2964 1 C2965 1 C2973 1 C2974 1 C2975 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
20% 20% 20% 20% 20% 20% 20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2 2 6.3V
X5R
6.3V
2 X5R 6.3V
2 X5R 2 6.3V
X5R
6.3V
2 X5R 2 6.3V
X5R
6.3V
2 X5R 6.3V
2 X5R 2 6.3V
X5R
6.3V
2 X5R 6.3V
2 X5R 2 6.3V
X5R
29 OF 132
402 402 402 402 402 402 402 402 201 201 201 201 201 201 201 201 201 201 201 201
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
72 31 29 PP0V75_S3_MEM_VREFDQ_B 72 31 29 PP0V75_S3_MEM_VREFDQ_B 72 31 29 PP0V75_S3_MEM_VREFDQ_B 72 31 29 PP0V75_S3_MEM_VREFDQ_B
72 31 29 PP0V75_S3_MEM_VREFCA_B 72 31 29 PP0V75_S3_MEM_VREFCA_B 72 31 29 PP0V75_S3_MEM_VREFCA_B 72 31 29 PP0V75_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B 8 29 =PP1V5R1V35_S3_MEM_B 8 29 =PP1V5R1V35_S3_MEM_B 8 29 =PP1V5R1V35_S3_MEM_B 8 29
C3107 1
C3108 1 1 C3109 C3117 1
C3118 1 1 C3119 C3127 1 C3128 1 1 C3129 C3137 1 C3138 1 1 C3139
0.47UF 0.47UF 0.47UF 0.47UF
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 4V
201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 2 CERM-X5R-1
201 201 201 201 201 201 201 201
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA

29 12 MEM_B_A<0> K3 A0 73 30 29 12 MEM_B_A<0> K3 A0 73 30 29 12 MEM_B_A<0> K3 A0 73 30 29 12 MEM_B_A<0> K3 A0
D
73 30
29 12
73 30
MEM_B_A<1> L7 A1 U3100
27 28 29
MEM_B_A<1> L7 A1 U3110
27 28 29
MEM_B_A<1> L7 A1 U3120
27 28 29
MEM_B_A<1> L7 A1 U3130
RESET* N2 MEM_RESET_L 27 28 29
D
29 12 MEM_B_A<2> L3 A2 FBGA-10.1X12.6-J4 73 30 29 12 MEM_B_A<2> L3 A2 FBGA-10.1X12.6-J4 73 30 29 12 MEM_B_A<2> L3 A2 FBGA-10.1X12.6-J4 73 30 29 12 MEM_B_A<2> L3 A2 FBGA-10.1X12.6-J4
MT41K1G4
MT41K1G4
MT41K1G4
MT41K1G4
73 30
29 12 MEM_B_A<3> K2 A3 DQ0 B3 MEM_B_DQ<1> 7 12 73 MEM_B_A<3> K2 A3 DQ0 B3 MEM_B_DQ<8> 7 12 73 MEM_B_A<3> K2 A3 DQ0 B3 MEM_B_DQ<21> 7 12 73 MEM_B_A<3> K2 A3 DQ0 B3 MEM_B_DQ<25> 7 12 73
73 30
29 12 MEM_B_A<4> L8 A4 DQ1 C7 MEM_B_DQ<6> 7 12 73 MEM_B_A<4> L8 A4 DQ1 C7 MEM_B_DQ<15> 7 12 73 MEM_B_A<4> L8 A4 DQ1 C7 MEM_B_DQ<23> 7 12 73 MEM_B_A<4> L8 A4 DQ1 C7 MEM_B_DQ<30> 7 12 73
73 30
73 30
29 12 MEM_B_A<6> M8 A6 DQ3 C8 MEM_B_DQ<7> 7 12 73 MEM_B_A<6> M8 A6 DQ3 C8 MEM_B_DQ<10> 7 12 73 MEM_B_A<6> M8 A6 DQ3 C8 MEM_B_DQ<18> 7 12 73 MEM_B_A<6> M8 A6 DQ3 C8 MEM_B_DQ<27> 7 12 73
73 30
29 12 MEM_B_A<7> M2 A7 NF_DQ4 E3 MEM_B_DQ<4> 7 12 73 MEM_B_A<7> M2 A7 NF_DQ4 E3 MEM_B_DQ<13> 7 12 73 MEM_B_A<7> M2 A7 NF_DQ4 E3 MEM_B_DQ<20> 12 73 MEM_B_A<7> M2 A7 NF_DQ4 E3 MEM_B_DQ<28> 7 12 73
73 30
29 12 MEM_B_A<8> N8 A8 NF_DQ5 E8 MEM_B_DQ<3> 12 73 MEM_B_A<8> N8 A8 NF_DQ5 E8 MEM_B_DQ<11> 7 12 73 MEM_B_A<8> N8 A8 NF_DQ5 E8 MEM_B_DQ<22> 7 12 73 MEM_B_A<8> N8 A8 NF_DQ5 E8 MEM_B_DQ<31> 7 12 73
73 30
29 12 MEM_B_A<9> M3 A9 NF_DQ6 D2 MEM_B_DQ<5> 7 12 73 MEM_B_A<9> M3 A9 NF_DQ6 D2 MEM_B_DQ<9> 7 12 73 MEM_B_A<9> M3 A9 NF_DQ6 D2 MEM_B_DQ<16> 7 12 73 MEM_B_A<9> M3 A9 NF_DQ6 D2 MEM_B_DQ<29> 7 12 73
73 30
MEM_B_A<10> NF_DQ7 E7 MEM_B_DQ<2> MEM_B_A<10> NF_DQ7 E7 MEM_B_DQ<14> MEM_B_A<10> NF_DQ7 E7 MEM_B_DQ<19> MEM_B_A<10> NF_DQ7 E7 MEM_B_DQ<26>
12 73
29 12 H7 A10/AP 7 29 12 H7 A10/AP 12 73 H7 A10/AP 7 12 73 H7 A10/AP 12 73
73 30 73 30
29 12 MEM_B_A<11> M7 A11 MEM_B_A<11> M7 A11
73 30
29 12 MEM_B_A<11> M7 A11
73 30
29 12 MEM_B_A<11> M7 A11
73 30 DQS C3 MEM_B_DQS_P<0> 12 73 C3
DQS MEM_B_DQS_P<1> 12 73 DQS C3 MEM_B_DQS_P<2> 12 73 DQS C3 MEM_B_DQS_P<3> 12 73
29 12 MEM_B_A<12> K7 A12/BC* MEM_B_A<12> K7 A12/BC* MEM_B_A<12> K7 A12/BC* MEM_B_A<12> K7 A12/BC*
73 30 DQS* D3 MEM_B_DQS_N<0> 12 73 DQS* D3 MEM_B_DQS_N<1> 12 73 DQS* D3 MEM_B_DQS_N<2> 12 73 DQS* D3 MEM_B_DQS_N<3> 12 73
29 12 MEM_B_A<13> N3 A13 73 30 29 12 MEM_B_A<13> N3 A13 73 30 29 12 MEM_B_A<13> N3 A13 73 30 29 12 MEM_B_A<13> N3 A13
73 30
29 12 MEM_B_A<14> N7 A14 DM/TDQS B7 73 30 29 12 MEM_B_A<14> N7 A14 DM/TDQS B7 73 30 29 12 MEM_B_A<14> N7 A14 DM/TDQS B7 73 30 29 12 MEM_B_A<14> N7 A14 DM/TDQS B7
73 30
29 12 MEM_B_A<15> J7 A15 NF_TDQS* A7 NC 73 30 29 12 MEM_B_A<15> J7 A15 NF_TDQS* A7 NC 73 30 29 12 MEM_B_A<15> J7 A15 NF_TDQS* A7 NC 73 30 29 12 MEM_B_A<15> J7 A15 NF_TDQS* A7 NC
73 30
29 12 MEM_B_BA<0> J2 BA0 H1MEM_B_CS_L<1>

73
30 29 12 MEM_B_BA<0> J2 BA0 H1MEM_B_CS_L<1>
73
30 29 12 MEM_B_BA<0> J2 BA0 H1MEM_B_CS_L<1> 30 29 12 MEM_B_BA<0> J2 BA0 H1MEM_B_CS_L<1>
73 30 CS1* 12 29 30 CS1* 12 29 30 CS1* 73 CS1* 12 29 30 73
29 12 MEM_B_BA<1> K8 BA1 H2MEM_B_CS_L<0>
73 MEM_B_BA<1> K8 BA1 H2MEM_B_CS_L<0>
73 MEM_B_BA<1> K8 BA1 H2MEM_B_CS_L<0> 30 29 12 MEM_B_BA<1> K8 BA1 H2MEM_B_CS_L<0>
73 30 CS0* 12 29 30 CS0* 1229 30 CS0* 73 CS0* 12 29 30 73
29 12 MEM_B_BA<2> J3 BA2 73 12 MEM_B_BA<2> J3 BA2 73 12 MEM_B_BA<2> J3 BA2 73 30 29 12 MEM_B_BA<2> J3 BA2
73 30 73 30 29 73 30 29
CKE0 G9 MEM_B_CKE<0> 12 29 30 CKE0 G9 MEM_B_CKE<0> 12 29 30 CKE0 G9 MEM_B_CKE<0> 12 29 30 CKE0 G9 MEM_B_CKE<0> 12 29 30 73
29 12 MEM_B_RAS_L F3 RAS* 73 MEM_B_RAS_L F3 RAS* 73 MEM_B_RAS_L F3 RAS* 73 MEM_B_RAS_L F3 RAS*
73 30 CKE1 F9 MEM_B_CKE<1> 73
12 29 30 CKE1 F9 MEM_B_CKE<1> 12 29 30 CKE1 F9 MEM_B_CKE<1> 12 29 30 CKE1 F9 MEM_B_CKE<1> 12 29 30 73
29 12 MEM_B_CAS_L G3 CAS* 73 30 29 12 MEM_B_CAS_L G3 CAS* 73 MEM_B_CAS_L G3 CAS* 73 MEM_B_CAS_L G3 CAS*
73 30
29
73
12
30
MEM_B_WE_L H3 WE* CK F7 MEM_B_CLK_P<0> 12 29
30 73
MEM_B_WE_L H3 WE* CK F7 MEM_B_CLK_P<0> 12
30
29
73
MEM_B_WE_L H3 WE* CK F7 MEM_B_CLK_P<0> 12
30
29
73
MEM_B_WE_L H3 WE* CK F7 MEM_B_CLK_P<0> 12 29 30 73
29 12 MEM_B_ODT<0> G1 ODT0 CK* G7 MEM_B_CLK_N<0> 73

12 29 MEM_B_ODT<0> G1 ODT0 CK* G7 MEM_B_CLK_N<0> 12 29 30 73
73 30 30 73 73
29 12 MEM_B_ODT<1> F1 ODT1 A3 73 30 29 12 MEM_B_ODT<1> F1 ODT1 A3 73 30 29 12 MEM_B_ODT<1> F1 ODT1 A3 73 30 29 12 MEM_B_ODT<1> F1 ODT1 A3
73 30
NC NC NC NC
MEM_B_ZQ<0> H8 ZQ0 79
NC MEM_B_ZQ<1> H8 ZQ0 79
NC
NC
C NC 81
82
NC
NC 81
82
NC
NC 81
82
NC
NC 81
82
NC C
NC NC NC NC
VSS VSSQ VSS VSSQ VSS VSSQ VSS VSSQ
R31002 1
R3101 R31102 1
R3111 R31202 1
R3121 R31302 1
R3131
240 240 240 240 240 240 240 240
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
1% 1% 1% 1% 1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
201 1 2 201 201 1 2 201 201 1 2 201 201 1 2 201
72 31 29 PP0V75_S3_MEM_VREFDQ_B 72 31 29 PP0V75_S3_MEM_VREFDQ_B 72 31 29 PP0V75_S3_MEM_VREFDQ_B 72 31 29 PP0V75_S3_MEM_VREFDQ_B
72 31 29 PP0V75_S3_MEM_VREFCA_B 72 31 29 PP0V75_S3_MEM_VREFCA_B 72 31 29 PP0V75_S3_MEM_VREFCA_B 72 31 29 PP0V75_S3_MEM_VREFCA_B
=PP1V5R1V35_S3_MEM_B 8 29 =PP1V5R1V35_S3_MEM_B 8 29 =PP1V5R1V35_S3_MEM_B 8 29 =PP1V5R1V35_S3_MEM_B 8 29
C3147 1
C3148 1 1 C3149 C3157 1
C3158 1 1 C3159 C3167 1 C3168 1 1 C3169 C3177 1 C3178 1 1 C3179
0.47UF 0.47UF 0.47UF 0.47UF
4V 20% 20% 4V 20% 20% 4V 20% 20% 4V 20% 20%
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
A2
A9
D7
G2
G8
K1
K9
M1
M9
B9
C1
E2
E9
E1
J8
CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V CERM-X5R-1 2 4V 2 4V
201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1 201 CERM-X5R-1 2 CERM-X5R-1
201 201 201 201 201 201 201 201
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
29 12 MEM_B_A<0> K3 A0 73 30 29 12 MEM_B_A<0> K3 A0 73 30 29 12 MEM_B_A<0> K3 A0 73 30 29 12 MEM_B_A<0> K3 A0
73 30
29 12 MEM_B_A<1> L7 A1 U3140 MEM_RESET_L 73 30 29 12 MEM_B_A<1> L7 A1 U3150 MEM_RESET_L 73 30 29 12 MEM_B_A<1> L7 A1 U3160 MEM_RESET_L 73 30 29 12 MEM_B_A<1> L7 A1 U3170 MEM_RESET_L
73 30 RESET* N2 27 28 29 RESET* N2 27 28 29 RESET* N2 27 28 29 RESET* N2 27 28 29
29 12 MEM_B_A<2> L3 A2 FBGA-10.1X12.6-J4 73 30 29 12 MEM_B_A<2> L3 A2 FBGA-10.1X12.6-J4 73 30 29 12 MEM_B_A<2> L3 A2 FBGA-10.1X12.6-J4 73 30 29 12 MEM_B_A<2> L3 A2 FBGA-10.1X12.6-J4
MT41K1G4
MT41K1G4
MT41K1G4
MT41K1G4
73 30
29 12 MEM_B_A<3> K2 A3 DQ0 B3 MEM_B_DQ<32> 7 12 73 MEM_B_A<3> K2 A3 DQ0 B3 MEM_B_DQ<41> 12 73 MEM_B_A<3> K2 A3 DQ0 B3 MEM_B_DQ<52> 7 12 73 MEM_B_A<3> K2 A3 DQ0 B3 MEM_B_DQ<56> 7 12 73
73 30
29 12
73 30
MEM_B_A<4> L8 A4 DQ1 C7 MEM_B_DQ<39> 7 12 73 MEM_B_A<4> L8 A4 DQ1 C7 MEM_B_DQ<46> 7 12 73 MEM_B_A<4> L8 A4 DQ1 C7 MEM_B_DQ<50> 7 12 73 MEM_B_A<4> L8 A4 DQ1 C7 MEM_B_DQ<62> 7 12 73
73 30
29 12 MEM_B_A<6> M8 A6 DQ3 C8 MEM_B_DQ<34> 7 12 73 MEM_B_A<6> M8 A6 C8 DQ3 MEM_B_DQ<47> 7 12 73 MEM_B_A<6> M8 A6 C8DQ3 MEM_B_DQ<51> 7 12 73 MEM_B_A<6> M8 A6 DQ3 C8 MEM_B_DQ<59> 7 12 73
73 30
29 12 MEM_B_A<7> M2 A7 NF_DQ4 E3 MEM_B_DQ<36> 12 73 MEM_B_A<7> M2 A7 NF_DQ4 E3 MEM_B_DQ<45> 7 12 73 MEM_B_A<7> M2 A7 NF_DQ4 E3 MEM_B_DQ<48> 12 73 MEM_B_A<7> M2 A7 NF_DQ4 E3 MEM_B_DQ<60> 7 12 73
73 30
MEM_B_A<8> NF_DQ5 E8 MEM_B_DQ<38> MEM_B_A<8> NF_DQ5 E8 MEM_B_DQ<43> MEM_B_A<8> NF_DQ5 E8 MEM_B_DQ<54> MEM_B_A<8> NF_DQ5 E8 MEM_B_DQ<58>
N8 12 73
29 12 A8 7 12 73 N8 A8 7 12 73 N8 A8 7 29 12 N8 A8 12 73
73 30 73 30
B 29 12
73 30
29 12
MEM_B_A<9>
MEM_B_A<10>
M3
H7
A9
A10/AP
NF_DQ6 D2
NF_DQ7 E7
MEM_B_DQ<33>
MEM_B_DQ<35>
7 12 73
7 12 73
MEM_B_A<9>
MEM_B_A<10>
M3
H7
A9
A10/AP
NF_DQ6 D2
NF_DQ7 E7
MEM_B_DQ<40>
MEM_B_DQ<42>
7 12 73
7 12 73
MEM_B_A<9>
MEM_B_A<10>
M3
H7
A9
A10/AP
NF_DQ6 D2
NF_DQ7 E7
MEM_B_DQ<49>
MEM_B_DQ<55>
7 12 73
7 12 73
MEM_B_A<9>
MEM_B_A<10>
M3
H7
A9
A10/AP
NF_DQ6 D2
NF_DQ7 E7
MEM_B_DQ<57>
MEM_B_DQ<63>
7 12 73
7 12 73
B
73 30
29 12 MEM_B_A<11> M7 A11
73 30
29 12 MEM_B_A<11> M7 A11
73 30
29 12 MEM_B_A<11> M7 A11
73 30
29 12 MEM_B_A<11> M7 A11
73 30 DQS C3 MEM_B_DQS_P<4> 12 73 DQS C3 MEM_B_DQS_P<5> 12 73 DQS C3 MEM_B_DQS_P<6> 12 73 DQS C3 MEM_B_DQS_P<7> 12 73
29 12 MEM_B_A<12> K7 A12/BC* MEM_B_A<12> K7 A12/BC* MEM_B_A<12> K7 A12/BC* MEM_B_A<12> K7 A12/BC*
73 30 DQS* D3 MEM_B_DQS_N<4> 12 73 DQS* D3 MEM_B_DQS_N<5> 12 73 DQS* D3 MEM_B_DQS_N<6> 12 73 DQS* D3 MEM_B_DQS_N<7> 12 73
29 12 MEM_B_A<13> N3 A13 73 30 29 12 MEM_B_A<13> N3 A13 73 30 29 12 MEM_B_A<13> N3 A13 73 30 29 12 MEM_B_A<13> N3 A13
73 30
29 12 MEM_B_A<14> N7 A14 DM/TDQS B7 73 30 29 12 MEM_B_A<14> N7 A14 DM/TDQS B7 73 30 29 12 MEM_B_A<14> N7 A14 DM/TDQS B7 73 30 29 12 MEM_B_A<14> N7 A14 DM/TDQS B7
73 30
29 12
73 30
MEM_B_A<15> J7 A15 NF_TDQS* A7 NC 73 30 29 12 MEM_B_A<15> J7 A15 NF_TDQS* A7 NC 73 30 29 12 MEM_B_A<15> J7 A15 NF_TDQS* A7 NC 73 30 29 12 MEM_B_A<15> J7 A15 NF_TDQS* A7 NC
29 12 MEM_B_BA<0> J2 BA0 H1MEM_B_CS_L<1>
MEM_B_BA<0> J2
73
30 29 12 BA0 H1MEM_B_CS_L<1>
73
73
73 30 CS1* 12 29 30 CS1* 12 29 30 CS1* 12 29 30 CS1* 12 29 30 73
29 12 MEM_B_BA<1> K8 BA1 H2MEM_B_CS_L<0> 12 29 30
73 30 CS0* CS0* 1229 30 CS0* 12 29 30 CS0* 12 29 30 73
29 12
73 30
MEM_B_BA<2> J3 BA2 73 12
73 30 29
MEM_B_BA<2> J3 BA2 73 12 MEM_B_BA<2> J3 BA2 73 12 MEM_B_BA<2> J3 BA2
73 30 29 73 30 29
CKE0 G9 MEM_B_CKE<0> 12 29 30 CKE0 G9 MEM_B_CKE<0> 12 29 30 CKE0 G9 MEM_B_CKE<0> 12 29 30 CKE0 G9 MEM_B_CKE<0> 12 29 30 73
29 12 MEM_B_RAS_L F3 RAS* F9 MEM_B_CKE<1>
73 MEM_B_RAS_L F3 RAS* MEM_B_RAS_L F3
73 RAS* 73 MEM_B_RAS_L F3 RAS*
73 30 CKE1 12 29 30 CKE1 F9 MEM_B_CKE<1> 12 29 30 CKE1 F9 MEM_B_CKE<1> 12 29 30 CKE1 F9 MEM_B_CKE<1> 12 29 30 73
29 12
73 30
MEM_B_CAS_L G3 CAS* 73 MEM_B_CAS_L G3 CAS* 73 MEM_B_CAS_L G3 CAS* 73 MEM_B_CAS_L G3 CAS*
29 12 MEM_B_WE_L H3 WE* CK F7 MEM_B_CLK_P<0> 12 29 MEM_B_WE_L H3 WE* CK F7 MEM_B_CLK_P<0> 12 29 MEM_B_WE_L H3 WE* CK F7 MEM_B_CLK_P<0> 12 29 MEM_B_WE_L H3 WE* CK F7 MEM_B_CLK_P<0> 12 29 30
73 30 30 73 30 73 30 73 73
29 12 MEM_B_ODT<0> G1 ODT0 CK* G7 MEM_B_CLK_N<0> 12 29 MEM_B_ODT<0> G1 ODT0 CK* G7 MEM_B_CLK_N<0> 12 29 MEM_B_ODT<0> G1 ODT0 CK* G7 MEM_B_CLK_N<0> 12 29 MEM_B_ODT<0> G1 ODT0 CK* G7 MEM_B_CLK_N<0> 12 29 30 73
73 30 30 73 30 73 30 73
29 12 MEM_B_ODT<1> F1 ODT1 A3 73 30 29 12 MEM_B_ODT<1> F1 ODT1 A3 73 30 29 12 MEM_B_ODT<1> F1 ODT1 A3 73 30 29 12 MEM_B_ODT<1> F1 ODT1 A3
73 30
NC NC NC NC
NC
NC
NC 81 NC 81 NC 81 NC 81
NC NC NC NC
R31402 1
R3141 VSS VSSQ
82
NC
VSS VSSQ
82
NC
VSS VSSQ
82
NC
VSS VSSQ
82
NC
240
1%
240
1% R31502 1
R3151 R31602 1
R3161 R31702 1
R3171
240 240 240 240 240 240
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
A1
A8
B1
D8
F2
F8
J1
J9
L1
L9
N1
N9
B2
B8
C9
D1
D9
1/20W 1/20W
MF MF 1% 1% 1% 1% 1% 1%
201 1 2 201 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W
MF MF MF MF MF MF
201 1 2 201 201 1 2 201 201 1 2 201
=PP1V5R1V35_S3_MEM_B 8 29 SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)
PAGE TITLE
C3100 1 C3101 1 C3110 1 C3111 1 C3120 1 C3121 1 C3130 1 C3131 1 1 C3103 1 C3104 1 C3105 1 C3113 1 C3114 1 C3115 1 C3123 1 C3124 1 C3125 1 C3133 1 C3134 1 C3135 DDR3 SDRAM Bank B (Rank 0)
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
20% 20% 20% 20% 20% 20% 20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% DRAWING NUMBER SIZE
10V 10V 10V 10V 10V 10V 10V 10V 2 6.3V 6.3V 6.3V 2 6.3V 6.3V 2 6.3V 6.3V 6.3V 2 6.3V 6.3V 6.3V 2 6.3V
X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R 2 X5R 2 X5R X5R 2 X5R X5R 2 X5R 2 X5R X5R 2 X5R 2 X5R X5R <SCH_NUM> D
402 402 402 402 402 402 402 402 201 201 201 201 201 201 201 201 201 201 201 201
Apple Inc. REVISION
R
<E4LABEL>
C3140 1 C3141 1 C3150 1 C3151 1 C3160 1 C3161 1 C3170 1 C3171 1 1 C3143 1 C3144 1 C3145 1 C3153 1 C3154 1 C3155 1 C3163 1 C3164 1 C3165 1 C3173 1 C3174 1 C3175 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
20% 20% 20% 20% 20% 20% 20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2
10V
X5R-CERM 2 2 6.3V
X5R
6.3V
2 X5R 6.3V
2 X5R 2 6.3V
X5R
6.3V
2 X5R 2 6.3V
X5R
6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R 2 6.3V
X5R
31 OF 132
402 402 402 402 402 402 402 402 201 201 201 201 201 201 201 201 201 201 201 201
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE
8 =PP0V75_S0_MEM_VTT_A
73 28 12 MEM_A_A<3> RP3305 36 1 8
IN
73 28 12 MEM_A_CKE<1> RP3301 36 4 5 5% 1/32W 4X0201
IN
73 28 12 MEM_A_BA<2> RP3302 36 2 7 5% 1/32W 4X0201 1 C3300
IN
73 28 12 MEM_A_A<14> RP3306 36 2 7 5% 1/32W 4X0201 0.47UF
IN 20%
73 28 12 MEM_A_A<2> RP3303 36 1 8 5% 1/32W 4X0201 4V
2 CERM-X5R-1
IN
73 28 12 MEM_A_A<12> RP3302 36 1 8 5% 1/32W 4X0201 201
IN
73 28 12 MEM_A_ODT<0> RP3301 36 2 7 5% 1/32W 4X0201
IN
73 28 12 MEM_A_BA<0> RP3305 36 2 7 5% 1/32W 4X0201
D 73 28 12
IN
IN MEM_A_A<1> RP3303 36 2 7
5% 1/32W 4X0201 1 C3302
0.47UF
1 C3303
0.47UF
D
73 28 12 MEM_A_A<7> RP3307 36 3 6 5% 1/32W 4X0201 20% 20%
IN 4V 4V
73 28 12 MEM_A_A<8> RP3306 36 1 8 5% 1/32W 4X0201 2 CERM-X5R-1 2 CERM-X5R-1
IN 201 201
5% 1/32W 4X0201
73 28 12 MEM_A_CS_L<1> RP3305 36 3 6
IN
73 28 12 MEM_A_A<11> RP3306 36 4 5 5% 1/32W 4X0201 1 C3304 1 C3305
IN
73 28 12 MEM_A_BA<1> RP3302 36 3 6 5% 1/32W 4X0201 0.47UF 0.47UF
IN 20% 20%
73 28 12 MEM_A_CKE<0> RP3304 36 3 6 5% 1/32W 4X0201
2 4V 2 4V
IN CERM-X5R-1 CERM-X5R-1
73 28 12 MEM_A_A<0> RP3303 36 4 5 5% 1/32W 4X0201 201 201
IN
73 28 12 MEM_A_A<10> RP3304 36 1 8 5% 1/32W 4X0201
IN
73 28 12 MEM_A_A<9> RP3307 36 2 7 5% 1/32W 4X0201
IN
73 28 12 MEM_A_WE_L RP3302 36 4 5 5% 1/32W 4X0201 1 C3306 1 C3307
IN
73 28 12 MEM_A_A<4> RP3303 36 3 6 5% 1/32W 4X0201 0.47UF 0.47UF
IN 20% 20%
73 28 12 MEM_A_A<5> RP3307 36 1 8 5% 1/32W 4X0201
2 4V 2 4V
73 28 12 MEM_A_A<15> RP3305 36 4 5 5% 1/32W 4X0201 201 201
IN
5% 1/32W 4X0201
RP3307
1 C3308
73 28 12 IN MEM_A_A<13> 36 4 5 0.47UF
20%
73 28 12 MEM_A_CAS_L RP3304 36 2 7 5% 1/32W 4X0201 4V
2 CERM-X5R-1
IN
73 28 12 MEM_A_CS_L<0> RP3304 36 4 5 5% 1/32W 4X0201 201
IN
73 28 12 MEM_A_RAS_L RP3301 36 3 6 5% 1/32W 4X0201
IN
73 28 12 MEM_A_ODT<1> RP3301 36 1 8 5% 1/32W 4X0201
IN
73 28 12 MEM_A_A<6> RP3306 36 3 6 5% 1/32W 4X0201 1 C3310
IN
5% 1/32W 4X0201 0.47UF
20%
4V
2 CERM-X5R-1
C 201
C
8 =PP0V75_S0_MEM_VTT_B
73 29 12 MEM_B_WE_L RP3322 36 2 7
IN
73 29 12 MEM_B_A<13> RP3325 36 1 8 5% 1/32W 4X0201 1 C3320
IN
5% 1/32W 4X0201 0.47UF
73 29 12 MEM_B_CKE<1> RP3328 36 1 8 20%
IN 4V
73 29 12 MEM_B_A<12> RP3325 36 2 7 5% 1/32W 4X0201 2 CERM-X5R-1
IN 201
5% 1/32W 4X0201
73 29 12 MEM_B_ODT<1> RP3328 36 2 7
IN
73 29 12 MEM_B_A<0> RP3325 36 3 6 5% 1/32W 4X0201
IN
5% 1/32W 4X0201
MEM Clock Termination 73 29 12 MEM_B_CS_L<1> RP3320 36 2 7 1 C3322 1 C3323
IN
Place RC end termination after last DRAM 73 29 12 MEM_B_BA<0> RP3326 36 4 5 5% 1/32W 4X0201 0.47UF 0.47UF
IN 20% 20%
Place Source Cterm at neckdown at first DRAM 73 29 12 MEM_B_A<6> RP3330 36 2 7 5% 1/32W 4X0201 4V
2 CERM-X5R-1
4V
2 CERM-X5R-1
IN
73 29 12 MEM_B_ODT<0> RP3320 36 3 6 5% 1/32W 4X0201 201 201
IN
MEM_B_A<4> RP3330 36 1 8 5% 1/32W 4X0201
R3350 C3351 73 29 12 IN
RP3330 36 3 6 5% 1/32W 4X0201
0.1UF 73 29 12 IN MEM_B_A<5>
30 RP3324 5% 1/32W 4X0201
73 28 12 IN MEM_A_CLK_N<0> 1 2 MEM_A_CLK0_TERM_R 1 2 73 29 12 IN MEM_B_BA<1>
RP3326
36 4 5
5% 1/32W 4X0201
1 C3324 1 C3325
5% 73 29 12 IN MEM_B_A<9> 36 2 7 0.47UF 0.47UF
10% 20% 20%
C3350 1
1/20W
MF 6.3V 73 29 12 MEM_B_A<8> RP3324 36 1 8 5% 1/32W 4X0201 4V
2 CERM-X5R-1
4V
2 CERM-X5R-1
X5R IN
3.3PF 201
201 73 29 12 MEM_B_A<3> RP3326 36 3 6 5% 1/32W 4X0201 201 201
5% IN
PLACE_NEAR=U2900.F7:3.2mm 25V
MEM_B_A<10> RP3322 36 3 6 5% 1/32W 4X0201
CERM 2 73 29 12 IN
201 R3351 73 29 12 IN MEM_B_A<7> RP3326 36 1 8 5% 1/32W 4X0201
30 RP3330 36 5% 1/32W 4X0201
B 73 28 12 IN MEM_A_CLK_P<0> 1 2 73 29 12 IN MEM_B_A<1>
RP3324
4 5
5% 1/32W 4X0201
1 C3326 1 C3327 B
5% 73 29 12 IN MEM_B_A<14> 36 3 6 0.47UF 0.47UF
20% 20%
1/20W
MF 73 29 12 MEM_B_A<11> RP3324 36 2 7 5% 1/32W 4X0201
2 4V 2 4V
201
73 29 12 MEM_B_A<2> RP3325 36 4 5 5% 1/32W 4X0201 201 201
IN
5% 1/32W 4X0201
MEM_B_BA<2> RP3320 36 4 5
73 29 12 IN
MEM_B_CS_L<0> RP3320 36 1 8 5% 1/32W 4X0201 1 C3328
73 29 12 IN
RP3322 5% 1/32W 4X0201
0.47UF
73 29 12 IN MEM_B_RAS_L 36 1 8 20%
5% 1/32W 4X0201 2 4V
CERM-X5R-1
201
73 29 12 MEM_B_CAS_L RP3328 36 4 5
IN
MEM_B_CKE<0> RP3328 36 3 6 5% 1/32W 4X0201 1 C3330
73 29 12 IN
RP3322 5% 1/32W 4X0201
0.47UF
73 29 12 IN MEM_B_A<15> 36 4 5 20%
4V
5% 1/32W 4X0201 2 CERM-X5R-1
201
R3360 C3361
0.1UF
30
73 29 12 IN MEM_B_CLK_N<0> 1 2 MEM_B_CLK0_TERM_R 1 2
5%
1/20W 10%
C3360 1 MF
201
6.3V
X5R
PLACE_NEAR=U3170.F7:3.2mm3.3PF
5%
201
25V
CERM 2
201
R3361
30
73 29 12 IN MEM_B_CLK_P<0> 1 2
5%
1/20W
MF
201
PAGE TITLE
DDR3 Termination
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
33 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Must not enable more than two SO-DIMM margining
8 =PP3V3_S3_VREFMRGN
buffers at once or VRef source may be overloaded.
VREFDQ:LDO_DAC
OMIT
=PPVTT_S3_DDR_BUF R3403
R3418 60 8
200 PLACE_NEAR=R3404.2:2.54mm
1
SHORT
2 PP3V3_S3_VREFMRGN_DAC
10mA max load 1 2
MIN_LINE_WIDTH=0.3 mm CRITICAL 1%
NONE MIN_NECK_WIDTH=0.2 mm DDRVREF_DAC DDRVREF_DAC 1/16W
NONE VOLTAGE=3.3V MF-LF
NONE C3400 1 1 C3401 DDRVREF_DAC 402
PP0V75_S3_MEM_VREFDQ_A
402
2.2UF 0.1UF DDRVREF_DAC 28 31 72
20% 20%
CRITICAL C3403 1
B1 U3402 MIN_LINE_WIDTH=0.3 mm
VREFDQ:LDO_DAC MIN_NECK_WIDTH=0.2 mm
D
6.3V
CERM
402-LF
2 2
10V
CERM
402
DDRVREF_DAC
U3400
0.1UF
20%
10V
CERM 2
A2
V+
MAX4253
UCSP
A1
R3404
133
VOLTAGE=0.75V
D
8
402
VREFMRGN_DQ_SODIMMA_BUF 1 2
VDD
A3 A4 1% PLACE_NEAR=R3403.2:1mm
42 IN =I2C_VREFDACS_SCL 6 SCL
MSOP VOUTA 1 VREFMRGN_SODIMMA_DQ V- 1/16W
MF-LF
B4
DAC5574
402
42 BI =I2C_VREFDACS_SDA 7 SDA VOUTB 2 VREFMRGN_SODIMMB_DQ
9 A0 VOUTC 4 VREFMRGN_SODIMMS_CA
Addr=0x98(WR)/0x99(RD) 10 A1 VOUTD 5 VREFMRGN_MEMVREG_FBVREF VREFDQ:LDO_DAC
NOTE: MEMVREG and FRAMEBUF share R3405

GND 200 PLACE_NEAR=R3406.2:2.54mm
a DAC output, cannot enable DDRVREF_DAC 1 2
3
both at the same time! 1 CRITICAL 1%
R3401 1/16W
100K MF-LF
OMIT 5% NC DDRVREF_DAC 402
1/16W PP0V75_S3_MEM_VREFDQ_B 29 31 72
R3419 MF-LF VREFDQ:LDO_DAC MIN_LINE_WIDTH=0.3 mm
2 402 C2
B1 U3402 MIN_NECK_WIDTH=0.2 mm
SHORT MAX4253 R3406 VOLTAGE=0.75V
1 2 PP3V3_S3_VREFMRGN_CTRL V+ UCSP
C1
133
NONE VREFMRGN_DQ_SODIMMB_BUF 1 2
Page Notes NONE

NONE
402
VOLTAGE=3.3V
DDRVREF_DAC
CRITICAL
DDRVREF_DAC C3 C4
1%
1/16W
PLACE_NEAR=R3405.2:1mm
16
C3402 1 V- MF-LF
Power aliases required by this page: 0.1UF VCC
B4 402
- =PP3V3_S3_VREFMRGN 20%
10V
CERM 2 U3401 NC
- =PPVTT_S3_DDR_BUF 402 PCA9557 VREFCA:LDO_DAC
- =PPDDR_S3_MEMVREF QFN
6
DDRVREF_DAC R3409
(OD) P0 NC 1
R3402 200 PLACE_NEAR=R3410.2:2.54mm
3 A0 P1 7 VREFMRGN_DQ_SODIMMA_EN 1 2
Signal aliases required by this page: 100K CRITICAL
Addr=0x30(WR)/0x31(RD) 4 A1 P2 9 VREFMRGN_DQ_SODIMMB_EN 5% 1%
- =I2C_VREFDACS_SCL 5 10 VREFMRGN_CA_SODIMMA_EN
1/16W 1/16W
A2 P3 MF-LF MF-LF
- =I2C_VREFDACS_SDA 11 VREFMRGN_CA_SODIMMB_EN 2
402 DDRVREF_DAC 402
PP0V75_S3_MEM_VREFCA_A
P4 DDRVREF_DAC 28 72
- =I2C_PCA9557D_SCL C3404
C - =I2C_PCA9557D_SDA =I2C_PCA9557D_SCL 1
P5
P6
12
13
VREFMRGN_MEMVREG_EN
VREFMRGN_FRAMEBUF_EN
0.1UF
20%
1
A2
B1
V+
U3403
MAX4253
VREFCA:LDO_DAC
R3410
VOLTAGE=0.75V
C
42 IN SCL 10V UCSP
CERM 2
A1
133
BOM options provided by this page: =I2C_PCA9557D_SDA 2
SDA P7 14 VREFMRGN_CA_SODIMMA_BUF 1 2
42 BI NC 402
DDRVREF_DAC - Stuffs Apple margining circuit.
15 A3 A4 1% PLACE_NEAR=R3409.2:1mm
THRM RESET* V- 1/16W
VREFDQ:LDO - LDO outputs sent to DQ inputs. MF-LF
PAD GND B4 402
VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.
17
8
VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.
VREFCA:LDO_DAC
VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.
VREFCA:LDO - LDO outputs sent to CA inputs. R3411
200 PLACE_NEAR=R3412.2:2.54mm
VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs. 1 2
1%
25 IN PCA9557D_RESET_L DDRVREF_DAC CRITICAL 1/16W
MF-LF
1
RST* on ’platform reset’ so that system R3407 NC DDRVREF_DAC 402
PP0V75_S3_MEM_VREFCA_B 29 72
100K VREFCA:LDO_DAC MIN_LINE_WIDTH=0.3 mm
watchdog will disable margining. 5%
C2
B1 U3403 MIN_NECK_WIDTH=0.2 mm
1/16W MAX4253 R3412 VOLTAGE=0.75V
MF-LF V+ UCSP
NOTE: Margining will be disabled across all 2 402 C1 VREFMRGN_CA_SODIMMB_BUF 1
133
2
soft-resets and sleep/wake cycles.
C3 C4 1% PLACE_NEAR=R3411.2:1mm
31 8 =PPDDR_S3_MEMVREF V- 1/16W
MF-LF
B4 402
CRITICAL PLACE_NEAR=Q3420.6:1mm
PLACE_NEAR=Q3420.6:2mm
VREFDQ:M1_M3 VREFDQ:M1_M3 NC
VREFDQ:M1_M3 1
Q3420 R3421 DDRVREF_DAC
1
C3420 1
SSM6N15FEAPE 0.1UF 1K R3408
1% DDRVREF_DAC
2
MEMRESET_ISOL_LS5V_L 10% 100K

31 27 SOT563 16V 1/16W CRITICAL
C3405 1
G
2 X7R-CERM MF-LF 5%
0402 2
402 1/16W
0.1UF DDRVREF_DAC
MF-LF DDRVREF_DAC
2 402
20%
10V C2
B1 U3404
2 MAX4253 R3414
S
PPCPU_MEM_VREFDQ_A PP0V75_S3_MEM_VREFDQ_A CERM

72 10 28 31 72 V+ UCSP
B 402
33.2K
B
6
1
C1 VREFMRGN_MEMVREG_BUF 1 2 DDRREG_FB OUT 60

VREFDQ:M1_M3
C4 1%
1 C3
R3422 V- PLACE_NEAR=R7320.2:1mm 1/16W
MF-LF
1K B4 402
PLACE_NEAR=R3421.2:1mm 1%
1/16W
MF-LF
2 402
NOTE: CPU DAC output step sizes:

DDR3 (1.5V) 7.70mV per step CRITICAL
=PPDDR_S3_MEMVREF
DDR3L (1.35V) 6.99mV per step VREFMRGN_FRAMEBUF_BUF
31 8 DDRVREF_DAC
DDRVREF_DAC 1 NC DDRVREF_DAC
CRITICAL PLACE_NEAR=Q3420.3:1mm R3413
VREFDQ:M1_M3 PLACE_NEAR=Q3420.3:2mm VREFDQ:M1_M3 R3416 1 100K B1 U3404 DDRVREF_DAC Required zero ohm resistors when no VREF margining circuit stuffed
0 A2
5% MAX4253
Q3420 VREFDQ:M1_M3 1
R3441 5% 1/16W V+ UCSP
1
R3417
1/16W MF-LF PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
SSM6N15FEAPE 1 C3440 1K MF-LF
2
402 A1 0
1% 402 5%
0.1UF
5
31 27 MEMRESET_ISOL_LS5V_L SOT563 1/16W 2 1/16W 116S0004 2 RES,MTL FILM,0,5%,0402,SM,LF R3403,R3405 VREFDQ:LDO

10% A3 A4
G
16V MF-LF V- MF-LF

2 X7R-CERM 402 402
2 B4 2
0402 116S0004 2 RES,MTL FILM,0,5%,0402,SM,LF R3409,R3411 VREFCA:LDO
VREFMRGN_MEMVREG_FBVREF_R
VREFMRGN_FRAMEBUF_BUF_R
S
72 10 PPCPU_MEM_VREFDQ_B PP0V75_S3_MEM_VREFDQ_B 29 31 72
NC
3
4
VREFDQ:M1_M3 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
1
R3442 DDRVREF_DAC
1
114S0218 4 RES,MTL FILM,1K,1%,0402,SM,LF R3421,R3422,R3441,R3442 VREFDQ:M1_DAC
1K R3415
1%
PLACE_NEAR=R3441.2:1mm 1/16W 100K 114S0171 2 RES,MTL FILM,332,1%,0402,SM,LF R3404,R3406 VREFDQ:M1_DAC
MF-LF 5%
402 1/16W
2
MF-LF
402
2
A MEM A VREF DQ MEM B VREF DQ MEM A VREF CA MEM B VREF CA MEM VREG GPU Frame Buffer (1.8V, 70% VRef)
PAGE TITLE
DAC Channel: A B C C D D
DDR3/FRAMEBUF VREF MARGINING
DRAWING NUMBER SIZE
PCA9557D Pin: 1 2 3 4 5 6
REVISION
Nominal value 0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A) 1.267V (DAC: 0x8B) R
<E4LABEL>
Margined target: 0.300V - 1.200V (+/- 450mV) 1.000V - 2.000V (+/- 500mV) 1.056V - 1.442V (+/- 180mV) NOTICE OF PROPRIETARY PROPERTY: BRANCH
DAC range: 0.000V - 1.501V (0x00 - 0x74) 0.000V - 3.000V (0x00 - 0x74) 0.000V - 3.300V (0x00 - 0xFF)
<BRANCH>
VRef current: +3.4mA - -3.4mA (- = sourced) +61uA - -61uA (- = sourced) +6.0mA - -5.0mA (- = sourced) I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
34 OF 132
DAC step size: 7.69mV / step @ output 8.59mV / step @ output 1.51mV / step @ output
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
518S0767
CRITICAL
J3502
819Q-3506-K281
F-RT-SM
8
ALS PLACE_NEAR=J3502.4:2.54MM
6 =I2C_ALS_SDA BI 42 L3508
5 =I2C_ALS_SCL 42
FERR-120-OHM-1.5A
IN
4 275 mA peak 2 1
PP5V_S3_ALSCAMERA_F =PP5V_S3_ALSCAMERA
C 3
7
74 7 USB_CAMERA_CONN_N MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5V
206 mA nominal max 0402-LF
8
C
2 74 7 USB_CAMERA_CONN_P
1
1 C3552
0.1uF
7
CAMERA CRITICAL
20%
10V
2 CERM
402
L3507
90-OHM
DLP0NS
SYM_VER-1
1 2 USB_CAMERA_N BI 19 74
4 3 USB_CAMERA_P BI 19 74
PLACE_NEAR=J3502.2:2.54MM
B B
PAGE TITLE
ALS/CAMERA CONNECTOR
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
35 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
NO_TEST=TRUE
NO_TEST=TRUE
75 9 7 IN PCIE_TBT_R2D_C_P<0> C3600 1 2
PCIE_TBT_R2D_P<0> AB9 OMIT_TABLE AD5 PCIE_TBT_D2R_C_P<0>
C3640 1 2 PCIE_TBT_D2R_P<0> OUT 7 9 75
10% 16V X5R-CERM
0201 PERP_0 PETP_0 75 10% 16V X5R-CERM
0201
0.1UF AA10 U3600 AD7 0.1UF
75 7 PCIE_TBT_R2D_N<0> PERN_0 PETN_0 75 PCIE_TBT_D2R_C_N<0> NOTE: The following pins require testpoints:
75 9 7 IN PCIE_TBT_R2D_C_N<0> C3601 1 2
10% 16V X5R-CERM
0201 NO_TEST=TRUE CACTUSRIDGE4C C3641 1 2 PCIE_TBT_D2R_N<0> OUT
10% 16V X5R-CERM
0201
7 9 75
0 - GPIO_13 8 - GPIO_15
0.1UF FCBGA NO_TEST=TRUE 0.1UF
NO_TEST=TRUE NO_TEST=TRUE 1 - GPIO_1 9 - GPIO_11
(SYM 1 OF 2)
75 9 7 IN PCIE_TBT_R2D_C_P<1> C3602 1 2
AA12 AD9 75 C3642 1 2 PCIE_TBT_D2R_P<1> OUT 7 9 75 2 - GPIO_2 10 - GPIO_14
PCIE GEN2
10% 16V X5R-CERM
0201 PCIE_TBT_R2D_P<1> PERP_1 PETP_1 7 PCIE_TBT_D2R_C_P<1> 10% 16V X5R-CERM
0201
0.1UF AB13 AD11 0.1UF 3 - GPIO_3 11 - GPIO_0
75 7 PCIE_TBT_R2D_N<1> PERN_1 PETN_1 PCIE_TBT_D2R_C_N<1>
C3603 C3643
RECEIVE
TRANSMIT
75 9 7 PCIE_TBT_R2D_C_N<1> 1 2 1 2 PCIE_TBT_D2R_N<1> OUT 7 9 75 4 - GPIO_5 12 - GPIO_12
IN
10% 16V X5R-CERM
0201 NO_TEST=TRUE 10% 16V X5R-CERM
0201
0.1UF NO_TEST=TRUE 0.1UF 5 - PCIE_RST_1_N 13 - GPIO_10
NO_TEST=TRUE
NO_TEST=TRUE 6 - PCIE_RST_2_N 14 - PB_LSTX
75 9 7 PCIE_TBT_R2D_C_P<2> C3604 1 2 C3644 1 2 PCIE_TBT_D2R_P<2> OUT 7 9 75
D
IN
0.1UF 10% 16V X5R-CERM
0201 PCIE_TBT_R2D_P<2>
PCIE_TBT_R2D_N<2>
AB15
AA16
PERP_2
PERN_2
PETP_2
PETN_2
AD13
AD15
PCIE_TBT_D2R_C_P<2>
PCIE_TBT_D2R_C_N<2>
0.1UF 10% 16V X5R-CERM
0201 7 - PCIE_RST_3_N 15 - PB_LSRX
D
75 9 7 IN PCIE_TBT_R2D_C_N<2> C3605 1 2
75 7
C3645 1 2 PCIE_TBT_D2R_N<2> OUT 7 9 75
10% 16V X5R-CERM
0201 10% 16V X5R-CERM
0201
0.1UF NO_TEST=TRUE NO_TEST=TRUE 0.1UF
35 34 33 8 =PP3V3_S4_TBT
NO_TEST=TRUE NO_TEST=TRUE
75 9 7 IN PCIE_TBT_R2D_C_P<3> C3606 1 2
10% 16V X5R-CERM
0201 PCIE_TBT_R2D_P<3> AA18 PERP_3 PETP_3 AD17 PCIE_TBT_D2R_C_P<3>
C3646 1 2 PCIE_TBT_D2R_P<3> OUT
10% 16V X5R-CERM
0201
7 9 75
R36101 0.1UF
PCIE_TBT_R2D_N<3> AB19 PERN_3 PETN_3 AD19 PCIE_TBT_D2R_C_N<3>
0.1UF
47K
5%
75 9 7 IN PCIE_TBT_R2D_C_N<3> C3607 1 2
10% 16V X5R-CERM
0201
75 7
NO_TEST=TRUE
C3647 1 2 PCIE_TBT_D2R_N<3> OUT
10% 16V X5R-CERM
0201
7 9 75
1/20W 0.1UF NO_TEST=TRUE 0.1UF

MF R6 U20
201 2 35 IN TBT_PCIE_RESET_L PERST_N RSENSE TBT_RSENSE
35 TBT_PWR_ON_POC_RST_L J2 PWR_ON_POC_RSTN
IN W20 TBT_RBIAS 1
NO STUFF
RBIAS R3655
1K
=PP3V3_TBTLC_RTR 8 33 34 35 C3610 1 7 TP_TBT_MONDC0 AD23 MONDC0
NC U4 1%
1/20W
0.1UF OMIT 7 TP_TBT_MONDC1 AC24 MONDC1 NC MF
10%
16V 1 2 201
X5R-CERM 2 R3615 DEBUG: For monitoring current/voltage
C3690 1 R36921 1
R3693 0201 NOSTUFF TBT_MONOBSP W18 MONOBS_P
R36901 1
R3691 1UF
10% 3.3K 3.3K NONE
NONE TBT_MONOBSN W16 MONOBS_N
3.3K 3.3K 6.3V 2 5% 5% NONE Not used in host mode.
PCIE RESET
5% 5% 1/20W 1/20W 0201 2
MISC
DEBUG: For monitoring clock
1/20W 1/20W CERM CRITICAL MF MF PCIE_RST_0_N N6 TP_TBT_PCIE_RESET0_L 7
MF MF 402 201 2 TP_TBT_THERM_DP Y7
201 2 OMIT_TABLE 2 201 45 THERMDA T1 TP_TBT_PCIE_RESET1_L
2 201 8 Use AA8 GND ball for THERM_DN PCIE_RST_1_N 7
VCC PCIE_RST_2_N Y5 TP_TBT_PCIE_RESET2_L 7

76 TBT_SPI_MOSI R4 EE_DI U2 TP_TBT_PCIE_RESET3_L
EEPROM
P5 PCIE_RST_3_N 7
(TBT_SPI_MOSI) 5 D U3690 Q 2 (TBT_SPI_MISO) 76 TBT_SPI_MISO EE_DO
M95256-RMC6XG 76 TBT_SPI_CS_L AD3 EE_CS_N
(TBT_SPI_CLK) 6 C MLP PCIE_CLKREQ_OD_N W6 =TBT_CLKREQ_L 35
76 TBT_SPI_CLK W4 EE_CLK OUT =PP3V3_TBTLC_RTR 8 33 34 35
(TBT_SPI_CS_L) 1 S*
K5 TBT_EN_LC_PWR
JTAG/TEST PORT
V1 EN_LC_PWR OUT 35
1
20 IN JTAG_TBT_TDI TDI R3698
TBTROM_WP_L 3 W*
AB3
20 IN JTAG_TBT_TMS TMS 10K
AA6 REFCLK_100_IN_P AB21 PCIE_CLK100M_TBT_P IN 7 17 75 5%
TBTROM_HOLD_L 7 HOLD* JTAG_TBT_TCK
C VSS THM
PAD
20
20
IN
OUT JTAG_TBT_TDO R2
TCK
TDO
REFCLK_100_IN_N AD21 PCIE_CLK100M_TBT_N IN 7 17 75
1/20W
MF
2 201 R3695
C
TBT_TEST_EN N4 806
CLOCKS
TEST_EN AA24
4 9
AB5 XTAL_25_IN 74 SYSCLK_CLK25M_TBT_R 1 2 SYSCLK_CLK25M_TBT IN 25 74
TBT_TEST_PWR_GOOD TEST_PWR_GOOD AB23
XTAL_25_OUT TP_TBT_XTAL25OUT 7 1% Divides 3.3V to 1.8V
1/20W
MF
R36251 1
R3629 79 33 DP_TBTSNK0_ML_P<3> E14 DPSNK0_3_P TMU_CLK_OUT AA4 TBT_TMU_CLK_OUT
201
0 0 DP_TBTSNK0_ML_N<3> D13 Y3 TBT_TMU_CLK_IN =PP3V3_TBTLC_RTR
5% 5% 79 33 DPSNK0_3_N TMU_CLK_IN 35 34 33 8
1/20W 1/20W
MF MF
DP_TBTSNK0_ML_P<2> E16 NO STUFF
201 2 2 201 79 33 DPSNK0_2_P 1 1 1
79 33 DP_TBTSNK0_ML_N<2> D15 DPSNK0_2_N DPSRC_3_P A14 TP_DP_TBTSRC_ML_CP<3> 7
R3697 R3699 R3696 R36801
DISPLAYPORT
100K 10K 1K 10K
SINK PORT 0
DPSRC_3_N B15 TP_DP_TBTSRC_ML_CN<3> 5% 5% 5% 5%
79 33 DP_TBTSNK0_ML_P<1> E18 DPSNK0_1_P
7
1/20W 1/20W 1/20W 1/20W
D17 A12 MF MF MF MF
79 33 DP_TBTSNK0_ML_N<1> DPSNK0_1_N DPSRC_2_P TP_DP_TBTSRC_ML_CP<2> 7
2 201 201 2 2 201 201 2
DPSRC_2_N B13 TP_DP_TBTSRC_ML_CN<2> 7
DP_TBTSNK0_ML_P<0> E20 TBT_DDC_XBAR_EN_L
SOURCE PORT 0
79 33 DPSNK0_0_P 68 33
79 33 DP_TBTSNK0_ML_N<0> D19 DPSNK0_0_N DPSRC_1_P A10 TP_DP_TBTSRC_ML_CP<1> 7 33 20 TBT_GO2SX_BIDIR

DPSRC_1_N B11 TP_DP_TBTSRC_ML_CN<1>
79 33 DP_TBTSNK0_AUXCH_P A6 DPSNK0_AUX_P
7
B5 A8 R3681 for CYA,

79 33 DP_TBTSNK0_AUXCH_N DPSNK0_AUX_N DPSRC_0_P TP_DP_TBTSRC_ML_CP<0> 7
SNK0 AC Coupling B9 allows separation
U6 DPSRC_0_N TP_DP_TBTSRC_ML_CN<0> 7
1
DP_TBTSNK0_HPD DPSNK0_HPD of GPIO_2/GPIO_9 R3681
79 9 IN DP_TBTSNK0_ML_C_P<0> C3620 1 2
10% 16V
DP_TBTSNK0_ML_P<0> 33 79
9 OUT
DPSRC_AUX_P C2 TP_DP_TBTSRC_AUXCH_CP 7 if necessary. 0
0.1UF X5R-CERM
0201 E6 D3 5%
79 9 IN DP_TBTSNK0_ML_C_N<0> C3621 1 2 DP_TBTSNK0_ML_N<0> 33 79
R36301 79 33 DP_TBTSNK1_ML_P<3>
D5
DPSNK1_3_P DPSRC_AUX_N TP_DP_TBTSRC_AUXCH_CN 7 Stuff one of R3861/2. 1/20W
MF
10% 16V 100K 79 33 DP_TBTSNK1_ML_N<3> DPSNK1_3_N V3 2 201
0.1UF X5R-CERM
0201 5% DPSRC_HPD_OD DP_TBTSRC_HPD
1/20W E8
MF DP_TBTSNK1_ML_P<2> DPSNK1_2_P TBT_GPIO_9
79 9 IN DP_TBTSNK0_ML_C_P<1> C3622 1 2 DP_TBTSNK0_ML_P<1> 33 79 201 2
79 33
D7
33
0.1UF 10% 16V 79 33 DP_TBTSNK1_ML_N<2> DPSNK1_2_N Y1 TBT_GO2SX_BIDIR R36321 33 TBT_GPIO_14
SINK PORT 1
X5R-CERM
0201 GPIO_2/GO2SX BI 20 33 NO STUFF
C3623 1 2 E10 W2 100K
79 9 IN DP_TBTSNK0_ML_C_N<1>
10% 16V
DP_TBTSNK0_ML_N<1> 33 79 79 33 DP_TBTSNK1_ML_P<1>
D9
DPSNK1_1_P (FORCE_PWR) GPIO_3
J4
TBT_PWR_EN IN 25 5%
1/20W R36831 1
R3682
0.1UF X5R-CERM
0201 79 33 DP_TBTSNK1_ML_N<1> DPSNK1_1_N GPIO_4/WAKE_N_OD =TBT_WAKE_L 40 MF 10K 10K
B 79 9 IN DP_TBTSNK0_ML_C_P<2> C3624 1 2 DP_TBTSNK0_ML_P<2> 33 79
9 OUT
79 33 DP_TBTSNK1_ML_P<0> E12 DPSNK1_0_P
GPIO_5/CIO_PLUG_EVENT AA2
AB1
TBT_CIO_PLUG_EVENT
OUT
OUT 20
201 2 5%
1/20W
MF
5%
1/20W
MF
B
10% 16V 1 D11 GPIO_6/CIO_SDA_OD =I2C_TBTRTR_SDA BI 42 201 2 2 201
0.1UF X5R-CERM
0201 R3631 79 33 DP_TBTSNK1_ML_N<0> DPSNK1_0_N AC2
GPIO_7/CIO_SCL_OD =I2C_TBTRTR_SCL
79 9 IN DP_TBTSNK0_ML_C_N<2> C3625 1 2
10% 16V
DP_TBTSNK0_ML_N<2> 33 79 100K
5% 79 33 DP_TBTSNK1_AUXCH_P A4 DPSNK1_AUX_P GPIO_8/EN_CIO_PWR_OD* P3 (TBT_EN_CIO_PWR_L)
IN 42
TBT_PWR_REQ_L 19
0.1UF X5R-CERM
0201 1/20W B3 M5
MF 79 33 DP_TBTSNK1_AUXCH_N DPSNK1_AUX_N GPIO_9/OK2GO2SX_OD* TBT_GPIO_9 33
201 2 TBT_EN_CIO_PWR_L
10% 16V
DP_TBTSNK1_HPD T5 DPSNK1_HPD
GPIO_14 T3 TBT_GPIO_14 33 MAKE_BASE=TRUE OUT 35
35 34 33 8 =PP3V3_S4_TBT
0.1UF X5R-CERM
0201 GPIO_15 V5 TBT_DDC_XBAR_EN_L 33 68 WF: Verify logic level!
OUT
10% 16V
DP_TBTSNK0_ML_N<3> 33 79
0.1UF X5R-CERM
0201 76 69 7 TBT_A_R2D_C_P<0> G24 PA_CIO0_TX_P/DP_SRC_0_P PB_CIO2_TX_P/DP_SRC_0_P R24 TBT_B_R2D_C_P<0> 7 70 76
OUT OUT
76 69 7 OUT TBT_A_R2D_C_N<0> E24 PA_CIO0_TX_N/DP_SRC_0_N PB_CIO2_TX_N/DP_SRC_0_N N24 TBT_B_R2D_C_N<0> OUT 7 70 76
R36851 1
R3686
10K 10K
DP_TBTSNK0_AUXCH_C_P C3628 1 2 DP_TBTSNK0_AUXCH_P 5% 5%
PORT0
PORT2
79 9 BI 33 79 G22 R22
10% 16V 76 69 7 IN TBT_A_D2R_P<0> PA_CIO0_RX_P PB_CIO2_RX_P TBT_B_D2R_P<0> IN 7 70 76 1/20W 1/20W
0.1UF X5R-CERM
0201 E22 N22 MF MF
TBT_A_D2R_N<0> PA_CIO0_RX_N PB_CIO2_RX_N TBT_B_D2R_N<0> 201 2 2 201
79 9 BI DP_TBTSNK0_AUXCH_C_N C3629 1 2
10% 16V
DP_TBTSNK0_AUXCH_N 33 79
76 69 7 IN IN 7 70 76
0.1UF X5R-CERM
0201 69 TBT_A_CONFIG1_BUF K1 PA_CONFIG1/CIO_0_LSEO PB_CONFIG1/CIO_2_LSEO P1 TBT_B_CONFIG1_BUF 70 69 33 TBT_A_DP_PWRDN
OUT OUT
69 TBT_A_CONFIG2_RC G4 PA_CONFIG2/CIO_0_LSOE PB_CONFIG2/CIO_2_LSOE H5 TBT_B_CONFIG2_RC 70 70 33 TBT_B_DP_PWRDN
IN IN
SNK1 AC Coupling 35 33 TBT_A_HV_EN
TBT_A_R2D_C_P<1> L24 PA_CIO1_TX_P/DP_SRC_2_P PB_CIO3_TX_P/DP_SRC_2_P W24 TBT_B_R2D_C_P<1> TBT_B_HV_EN
10% 16V
76 69 7
76 69 7
OUT
TBT_A_R2D_C_N<1> J24 PA_CIO1_TX_N/DP_SRC_2_N PB_CIO3_TX_N/DP_SRC_2_N U24 TBT_B_R2D_C_N<1>
OUT 7 70 76
7 70 76
35 33
0.1UF OUT OUT

X5R-CERM
0201
C3631 R36881 1
R3687
PORT1
PORT3
79 9 DP_TBTSNK1_ML_C_N<0> 1 2 DP_TBTSNK1_ML_N<0> 33 79 76 69 7 TBT_A_D2R_P<1> L22 PA_CIO1_RX_P PB_CIO3_RX_P W22 TBT_B_D2R_P<1> 7 70 76
IN IN IN
10% 16V J22 U22 10K 10K
0.1UF X5R-CERM
0201 76 69 7 IN TBT_A_D2R_N<1> PA_CIO1_RX_N PB_CIO3_RX_N TBT_B_D2R_N<1> IN 7 70 76 5% 5%
1/20W 1/20W
MF MF
10% 16V
DP_TBTSNK1_ML_P<1> 33 79 69 OUT TBT_A_LSTX N2 PA_LSTX/CIO_1_LSEO PB_LSTX/CIO_3_LSEO L6 TBT_B_LSTX OUT 70 201 2 2 201
0.1UF X5R-CERM
0201 69 TBT_A_LSRX J6 PA_LSRX/CIO_1_LSOE PB_LSRX/CIO_3_LSOE G6 TBT_B_LSRX 70
IN IN
10% 16V
DP_TBTSNK1_ML_N<1> 33 79
0.1UF DP_TBTPA_ML_C_P<1> A16 A20 DP_TBTPB_ML_C_P<1>

PORTS
X5R-CERM
0201 76 69 OUT PA_DPSRC_1_P PB_DPSRC_1_P OUT 70 76
DP_TBTPA_ML_C_N<1> B17 B21 DP_TBTPB_ML_C_N<1>

A 79 9 IN DP_TBTSNK1_ML_C_P<2> C3634
0.1UF
1 2
10% 16V
X5R-CERM
0201
76 69
76 69
OUT
DP_TBTPA_ML_C_P<3> A18
PA_DPSRC_1_N
PA_DPSRC_3_P
PB_DPSRC_1_N
PB_DPSRC_3_P A22 DP_TBTPB_ML_C_P<3>

OUT 70 76
70 76
SYNC_MASTER=J5_MLB_KEPLER SYNC_DATE=11/14/2011 A
OUT OUT PAGE TITLE
10% 16V
DP_TBTSNK1_ML_N<2> 33 79 76 69 OUT DP_TBTPA_ML_C_N<3> B19 PA_DPSRC_3_N PB_DPSRC_3_N B23 DP_TBTPB_ML_C_N<3> OUT 70 76
Thunderbolt Host (1 of 2)
0.1UF X5R-CERM
0201
F3 D1 DRAWING NUMBER SIZE
DP_TBTPA_AUXCH_C_P PA_AUX_P PB_AUX_P DP_TBTPB_AUXCH_C_P
10% 16V
76 69
76 69
BI
DP_TBTPA_AUXCH_C_N F1 PA_AUX_N PB_AUX_N E2 DP_TBTPB_AUXCH_C_N
BI 70 76
70 76 Apple Inc. <SCH_NUM> D

0.1UF BI BI
X5R-CERM
0201 REVISION
10% 16V
DP_TBTSNK1_ML_N<3> 33 79 69 IN DP_TBTPA_HPD H1 PA_DPSRC_HPD PB_DPSRC_HPD K3 DP_TBTPB_HPD IN 70
R
<E4LABEL>
0.1UF X5R-CERM
0201 G2 M1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
TBT_A_HV_EN GPIO_0/PA_HV_EN/BYP0 GPIO_1/PB_HV_EN/BYP0 TBT_B_HV_EN
35 33 OUT
TBT_A_CIO_SEL M3 GPIO_10/PA_CIO_SEL/BYP1 GPIO_11/PB_CIO_SEL/BYP1 L2 TBT_B_CIO_SEL
OUT 33 35
<BRANCH>
79 9 BI DP_TBTSNK1_AUXCH_C_P C3638 1 2
10% 16V
DP_TBTSNK1_AUXCH_P 33 79
69 OUT
TBT_A_DP_PWRDN H3 GPIO_12/PA_DP_PWRDN/BYP2 GPIO_13/PB_DP_PWRDN/BYP2 L4 TBT_B_DP_PWRDN
OUT 70
0.1UF X5R-CERM
0201
69 33 OUT OUT 33 70
79 9 BI DP_TBTSNK1_AUXCH_C_N C3639 1 2
10% 16V
DP_TBTSNK1_AUXCH_N 33 79
For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.
0.1UF X5R-CERM
0201 IV ALL RIGHTS RESERVED 33 OF 80
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 =PP1V05_TBTLC_RTR
???? mW (Single Port)
250 mW (Dual Port) =PP1V05_TBTCIO_RTR 8

CRITICAL
EDP: 1000 mA C3700 1 1 C3710 1 C3711 1 C3712 1 C3713 1 C3714 ???? mW (Single-Port)
D
D 10UF
20%
6.3V
1.0UF
20%
10V
1.0UF
20%
10V
1.0UF
20%
1.0UF
20%
1.0UF
20% J10 VCC1P0_ON
OMIT_TABLE
VCC1P0 K11 2700 mW (Dual-Port)
CERM-X5R 2 2 X5R-CERM 2 X5R-CERM 2 10V

X5R-CERM 2 10V
X5R-CERM
10V
2 X5R-CERM J12 U3600 K15 EDP: 3000 mA
0402-1 0201-1 0201-1 0201-1 0201-1 0201-1 VCC1P0_ON VCC1P0
J14 VCC1P0_ON CACTUSRIDGE4C VCC1P0 L10 C3740 1 C3741 1 C3742 1 C3743 1 C3744 1 C3745 1 1 C3705
J16 FCBGA L14 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 10UF
VCC1P0_ON (SYM 2 OF 2) VCC1P0 20% 20% 20% 20% 20% 20% 20%
J8 VCC1P0_ON VCC1P0 M11 10V 10V 10V 10V 10V 10V 2 6.3V
X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 CERM-X5R
K17 VCC1P0_ON VCC1P0 M15 0201-1 0201-1 0201-1 0201-1 0201-1 0201-1 0402-1
C3701 1 1 C3715 1 C3716 1 C3717 T15 VCC1P0_ON VCC1P0 N10
10UF 1.0UF 1.0UF 1.0UF
20% 20% 20% 20% U14 VCC1P0_ON VCC1P0 N14
6.3V 10V 10V 2 10V
CERM-X5R 2 2 X5R-CERM 2 X5R-CERM X5R-CERM V7 VCC1P0_ON VCC1P0 P11
0402-1 0201-1 0201-1 0201-1
W8 VCC1P0_ON VCC1P0 P15
VCC1P0 R10
G10 VCC1P0_PE
VCC
VCC1P0 R14
G12 VCC1P0_PE
VCC1P0 T11
G14 VCC1P0_PE
VCC1P0 U10
G16 VCC1P0_PE
VCC1P0 V11
G18 VCC1P0_PE =PP3V3_TBTLC_RTR 8
VCC1P0 W10 33 35
H19 VCC1P0_PE ??? mW (Single-Port)
K19 VCC1P0_PE 250 mW (Dual-Port)
VCC3P3 M7
M19 VCC1P0_PE EDP: 240 mA
VCC3P3 P7
P19 VCC1P0_PE
T19 VCC1P0_PE
VCC3P3 T7 C3770 1 C3771 1 C3772 1 C3773 1 C3774 1 1 C3760
1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 10UF
V15 VCC1P0_PE VCC3P3_CIO L18 20% 20% 20% 20% 20% 20%
10V 10V 10V 10V 10V 2 6.3V
V19 VCC1P0_PE VCC3P3_CIO N18 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 CERM-X5R
0201-1 0201-1 0201-1 0201-1 0201-1 0402-1
W12 VCC1P0_PE VCC3P3_CIO R18
W14 VCC1P0_PE
VCC3P3_DP H11
H13
C G8
H9
VCC1P0_DPAUX
VCC1P0_DPAUX
VCC3P3_DP
VCC3P3_DP H15 C
VCC3P3_DP H17
AD1 VSS VCC3P3_DPAUX H7

K13 VSS
K9 VSS
L12 VSS =PP3V3_S4_TBT 8 33 35
L16 VSS VCC3P3_POC K7 EDP: 10 mA
L8 VSS
M13 VSS VSSPE C22 C3790 1
M17 VSS VSSPE C24 1.0UF
20%
M9 VSS VSSPE C4 10V
X5R-CERM 2
N12 VSS VSSPE C6 0201-1
N16 VSS VSSPE C8
N8 VSS VSSPE D21
P13 VSS VSSPE D23
P17 VSS VSSPE E4
P9 VSS VSSPE F11
R12 VSS VSSPE F13
R16 VSS VSSPE F15
R8 VSS VSSPE F17
T13 VSS VSSPE F19
T17 VSS VSSPE F21
T9 VSS VSSPE F23
U12 VSS VSSPE F5
GND
U16 VSS VSSPE F7
U8 F9
B V9
VSS
VSS
VSSPE
VSSPE G20 B
VSSPE H21
A2 VSSPE VSSPE H23
A24 VSSPE VSSPE J18
AA14 VSSPE VSSPE J20
AA20 VSSPE VSSPE K21
AA22 VSSPE VSSPE K23
AA8 VSSPE VSSPE L20
AB11 VSSPE VSSPE M21
AB17 VSSPE VSSPE M23
AB7 VSSPE VSSPE N20
AC10 VSSPE VSSPE P21
AC12 VSSPE VSSPE P23
AC14 VSSPE VSSPE R20
AC16 VSSPE VSSPE T21
AC18 VSSPE VSSPE T23
AC20 VSSPE VSSPE U18
AC22 VSSPE VSSPE V13
AC4 VSSPE VSSPE V17
AC6 VSSPE VSSPE V21
AC8 VSSPE VSSPE V23
B1 VSSPE VSSPE Y11
B7 VSSPE VSSPE Y13
C10 VSSPE VSSPE Y15
C12 VSSPE VSSPE Y17
A C14
C16
VSSPE
VSSPE
VSSPE
VSSPE
Y19
Y21 SYNC_MASTER=J5_MLB_KEPLER SYNC_DATE=11/14/2011 A
PAGE TITLE
C18 VSSPE VSSPE Y23
C20 Y9 Thunderbolt Host (2 of 2)
VSSPE VSSPE
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
37 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
SI8409DB:
Power aliases required by this page:
- =PPVIN_SW_TBTBST (8-13V Boost Input) CRITICAL

Vds(max): -30V Thunderbolt 15V Boost Regulator
Vgs(max): +/-12V
- =PP15V_TBT_REG (15V Boost Output) TBTBST:Y CRITICAL
Vgs(th): -1.4V
- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)
Q3880 TBTBST:Y
Rds(on): 46mOhm @ 4.5V Vgs
- =PP3V3_TBTLC_FET (3.3V FET Output)
=PPVIN_SW_TBTBST SI8409DB
BGA Id(max): 3.7A @ 70C
L3895
- =PP3V3_S0_TBTPWRCTL
8 3.3UH-6.5A
8-13V Input
2 3
- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input) 8 PPVIN_SW_TBTBST 1 2 TBTBST_BOOST
Changes required MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
D
4
- =PP1V05_TBTLC_FET (1.05V FET Output) MIN_NECK_WIDTH=0.25 mm TBTBST:Y TBTBST:Y IHLP MIN_NECK_WIDTH=0.25 mm
for 2S. SWITCH_NODE=TRUE
TBTBST:Y TBTBST:Y Voltage not specified here, C3860 1 C3861 1 DIDT=TRUE
Signal aliases required by this page: add property on another page. 10UF 10UF
R38801 C3880 TBTBST_SNS1
D
G
- =TBT_CLKREQ_L
1 TBTBST:Y 20% 20%
D - =TBT_RESET_L
470K
5% 10%
0.1UF
R3891 1
25V
X5R-CERM2
0603
25V
X5R-CERM2
0603
TBTBST:Y
R38891 1 2
1
1/16W
2 25V 200K CRITICAL
27
8
9
20
21
38
MF-LF X5R
BOM options provided by this page: 402 2 402 1% 0
1/16W VIN 5% TBTBST:Y =PP15V_TBT_REG
TBTBST:Y - Stuffs 15V boost circuitry. MF-LF SW 1/20W
TBTBST_PWREN_DIV_L 402 2 CRITICAL MF
201 2
D3895 8
TBTBST:Y <R1> 25 EN/UVLO TBTBST:Y PDS540XF Vout = 15.47V

TBTBST_EN_UVLO SNS1 6 PWRDI5
R38811 U3890 3
TBTBST_SNS2 3 Max Current = 2A?
330K LT3957 SNS2 Freq = 500KHz
5%
1/16W TBTBST_INTVCC 28 INTVCC QFN
XW3895
SM
MF-LF 2 1
402 2 PLACE_NEAR=C3895.1:2 mm
30 VC
1 TBTBST_VSNS
TBTBST_PWREN_L TBTBST_VC 2 TBTBST:Y
TBTBST:Y
TBTBST:Y TBTBST:Y TBTBST:Y TBTBST:Y TBTBST:Y TBTBST:Y NC 10
NC TBTBST:Y R38951
Q3805 D 6 Q3805 D 3 C3890 1 C3891 1 C3892 1 1 C3887 R38931 TBTBST_RT 33 RT 35 1 C3888 137K
SSM6N37FEAPE SSM6N37FEAPE 2.2UF 2.2UF 2.2UF 68PF 49.9K 36 10PF 1%
20% 20% 20% 5% 1% 5% 1/16W
SOT563 SOT563 10V 10V 10V 1/16W MF-LF
X5R-CERM2 X5R-CERM2 X5R-CERM2 2 50V
CERM MF-LF 32 SS
50V
2 CERM 402 2 OMIT_TABLE
402 402 402 402-1 402 2 TBTBST_SS 402 OMIT_TABLE OMIT_TABLE OMIT_TABLE
<Ra>
2 G S 1 5 G S 4 TBTBST_VC_RC FBX 31 TBTBST_FBX
1 C3895 1C3897 1C3898 1C389A
4.7UF 4.7UF 4.7UF 4.7UF
TBTBST:Y TBTBST:Y 34 SYNC TBTBST:Y 10% 10% 10% 10%
1 1 TBTBST:Y NO STUFF 1 2 35V
X5R-CERM
35V
2 X5R-CERM 2 35V
X5R-CERM 2 35V
X5R-CERM
R3892 1 C3893 R3894 1 C3894 1 C3889 R3896 0603 0603 0603 0603
35 33 IN TBT_A_HV_EN 73.2K 0.0033UF 26.7K 0.33UF 100PF 15.8K TBTBST:Y
1% 10% 1% 10% SGND GND 5% 1% TBTBST:Y
TBT_B_HV_EN 1/16W
MF-LF 50V
2 CERM
1/16W
MF-LF 6.3V
2 CERM-X5R 2 50V
1/16W
MF-LF C3896 1 C3899 1
23
24
37
12
13
14
15
16
17
35 33 IN CERM 20%
4
2 402 402 402 2 402 402 402 2
25V 0.001UF
<R2> <Rb> 10%
GND_TBTBST_SGND POLY-TANT 2 50V 2
MIN_LINE_WIDTH=0.5 mm X7R
UVLO(falling) = 1.22 * (R1 + R2) / R2 MIN_NECK_WIDTH=0.25 mm CASE-D3L 402
VOLTAGE=0V
UVLO(rising) = UVLO(falling) + (2uA * R1) 33UF-0.06OHM
SGND shorted to
Vout = 1.6V * (1 + Ra / Rb)
C UVLO = 4.55V (falling), 4.95 (rising)
GND inside package,
no XW necessary.
C
Supervisor & CLKREQ# Isolation
8 =PP3V3_S0_TBTPWRCTL
TBTBST:Y
6 D
C3800 1 =PP3V3_TBTLC_RTR Q3888 TBTBST:Y
0.1UF
8 33 34 35
SSM6N37FEAPE 1
R3888 R3850
10%
SOT563 0
16V 1 330K 35 33 TBT_A_HV_EN 2 1 TBT_A_HV_EN_RC OUT 69
CRITICAL R3807
1
X5R-CERM 2 5%
1/16W 5%
0201 100K MF-LF 1/20W
1 VDD
Q3840 R3840 U3800
5%
1/20W 1 S G 2 Max Vgs: 10V 2 402 MF
201 C3850 1 NO STUFF
G 1
SSM3K15FV 10K MF 1.0UF

5% SLG4AP016V 2 201 TBTBST_SHDN_DIV NO STUFF 10%
SOD-VESM-HF 1/20W
MF TDFN =PP1V05_TBTLC 8 TBTBST:Y D3850 6.3V
X5R-CERM 2
2 201 2 1 TBTBST:Y 1N4448HLP-7 0201
+ SENSE R3887 3 D Q3888
3 D
2 S
33 IN TBT_EN_LC_PWR - 0.7V
K A
330K SSM6N37FEAPE
5% SOT563
1/16W DFN1006
MF-LF
64 OUT TBT_EN_LC_ISOL DLY
2 402
RESET* 4 TBT_PCIE_RESET_L OUT 33
25 IN =TBT_RESET_L 3 MR*
4 S G 5
Platform (PCIe) Reset DLY = 60 ms +/- 20%
6 EN
SMC_DELAYED_PWRGD IN 39 40 66
=TBT_CLKREQ_L IN 33
17 OUT TBT_CLKREQ_L 8 OUT
R3860
(OD) IN 7 TBT_CLKREQ_ISOL_L
MAKE_BASE=TRUE
TBT_B_HV_EN 0 TBT_B_HV_EN_RC
Pull-ups provided by SB page. NO STUFF GND
THRM
PAD
35 33 2 1 OUT 70
R38161 5%
5
1/20W
0 MF
5%
1/20W
201 C3865 1 NO STUFF
MF NO STUFF 1.0UF
201 2 TBT "POC" Power-up Reset D3860 10%
6.3V
X5R-CERM 2
B TBT_EN_LC_ISOL_R
Intel investigating whether RC is sufficient. 1N4448HLP-7
K A
0201 B
34 33 8 =PP3V3_S4_TBT
3.3V TBT "LC" Switch DFN1006
U3810 CRITICAL
1
TPS22924 =PP3V3_TBTLC_FET 8 Pull-up: R3610
CSP VDD
8 =PP3V3_S0_P3V3TBTFET A2 A1 Max Current = 2A (85C) =PP3V3_S0_PCH_GPIO 8 17 18 19 20 25
B2 VIN VOUT B1 2 SENSE RESET* 6 TBT_PWR_ON_POC_RST_L
R3811 U3830 OUT 33
1
0
CRITICAL U3810 TPS3808 R3830
C2 ON TBTPOCRST_CT 3 CT QFN MR* 4 TBTPOCRST_MR_L 100K
2 1
Part TPS22924C THRM
Q3825 5%
C3810 1 GND
G 5
5% GND SSM6N37FEAPE 1/20W
1/20W PAD MF
1UF 1 C3811 1 C3831 C3830 1
C1
MF Type Load Switch SOT563 2 201

R38101 20%
7
201
6.3V 2
X5R
1UF 0.0047UF 0.1UF TPS3808G25
10K 20% R(on) 18.3 mOhm Typ 10% 10%
3 D
4 S
5% 0201 2 6.3V 25V
2 CERM 25V 2 Vt = 2.33V +/- 2% TBT_SW_RESET_L 20
1/20W NO STUFF X5R @ 2.5V 24 mOhm Max
X5R IN
MF 0201 402 402 Delay = 27.3ms
201 2 1 C3825
330PF
10%
16V
2 X7R-CERM
0201
R3812 1.05V TBT "CIO" Switch
0 TBT_EN_LC_RC
2 1 80 8 =PP1V05_S0_P1V05TBTREG
5% =PP3V3_TBTLC_RTR PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
1/20W
MF
35 34 33 8
U3820
201 TPS22920 =PP1V05_TBTCIO_FET 8 138S0811 4 CAP,CER,4.7UF,10%,25V,X6S,0603 C3895,C3897,C3898,C389A CRITICAL TBTBST:Y
1
R3820 A2
CSP
A1 Max Current = 4A (85C)
100K B2 B1
5% VIN VOUT
1/20W
P1V05TBTS0_PGOOD MF C2 C1 U3820
A IN 64
2 201
TBT_EN_CIO_PWR D2 ON
CRITICAL
Part TPS22920 SYNC_MASTER=J5_MLB_KEPLER SYNC_DATE=11/14/2011 A
PAGE TITLE
GND Type Load Switch
Thunderbolt Power Support
1 C3820
D1
Q3825 D 6 R(on) 8 mOhm Typ DRAWING NUMBER SIZE

1UF
SSM6N37FEAPE
SOT563
20%
2 6.3V
@ 1.05V 11.5 mOhm Max
X5R REVISION
0201 R
<E4LABEL>
2 G S 1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
<BRANCH>
33 TBT_EN_CIO_PWR_L
38 OF 132
IN
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
OMIT_TABLE PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
L4470 PLACE_NEAR=J4400.28:2.54MM
117S0002 4 RES, 0OHM, 0201 L4470,L4471,L4473,L4474
1 2 75 7 PCIE_AP_R2D_PI_P C4433
12 3V S3 WLAN FET
0.1UF PCIE_AP_R2D_C_P IN 7 17 75
10% 16V
X7R-CERM
0402
0.6NH+/-0.1NH-0.85A
0201
NOSTUFF
NOSTUFF
1 C4470 1 C4471
0.1UF Max Current = 2A (85C)
10% 0.1UF DEBUG CURRENT SENSE RD135 connects to PP3V3_WLAN_F U4450
16V
2 X5R-CERM 10%
75 36 7 OUT PCIE_AP_R2D_P 0201
16V
2 X5R-CERM TPS22924
0201 CSP
66 36 8 =PP3V3_S3_WLAN A2 A1 PP3V3_WLAN_R 80
75 36 7 OUT PCIE_AP_R2D_N B2 VIN VOUT B1 MIN_LINE_WIDTH=0.6 mm
L4471 AIRPORT VOLTAGE=3.3V
D 1 2 75 7 PCIE_AP_R2D_PI_N 1 2 0.1UF PCIE_AP_R2D_C_N IN 7 17 75 66 IN PM_WLAN_EN C2 ON
CRITICAL U4450 D
GND Part TPS22924C
10% 16V
X7R-CERM
0402
0.6NH+/-0.1NH-0.85A
C4432 BTPWR:S4
C1
0201 Type Load Switch
NOSTUFF OMIT_TABLE NOSTUFF PLACE_NEAR=J4400.29:2.54MM L4415
PP3V3_S3RS4_BT_F
1 C4472 1 C4473
36
2 1 =PP3V3_S4_BT 8 R(on) 18.3 mOhm Typ
0.1UF MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V 1 C4417
10%
16V
0.1UF FERR-120-OHM-1.5A
@ 2.5V 24 mOhm Max
2 X5R-CERM 10% 0.01UF
0201 2 16V
X5R-CERM
10%
16V
0402-LF
0201 2 X7R-CERM
0402
BTPWR:S3
OMIT_TABLE L4416
L4473 PP3V3_S3RS4_BT_F 36
1 2
2 1 =PP3V3_S3_BT 8
PCIE_AP_D2R_P OUT 7 17 75
FERR-120-OHM-1.5A =BT_WAKE_L
0.6NH+/-0.1NH-0.85A NOSTUFF 0402-LF
BTPWR:S4 OUT 40
1 C4474 0201 1 C4475 78 USB_BT_CONN_P PLACE_NEAR=J3501.27:2.54MM
Q4410
0.1UF 0.1UF USB_BT_CONN_N
NOSTUFFSSM3K15FV D 3
78
10% NOSTUFF 10% NOSTUFF BTPWR:S3
16V
2 X5R-CERM 2 16V SOD-VESM-HF
75 36 7 IN PCIE_AP_D2R_PI_P 0201
X5R-CERM
0201
1
R4417 R44181 1 C4415 1
R4414
PCIE_AP_D2R_PI_N 15K 0 0.1UF 15K
75 36 7 IN L4474 10%
9
1 2
1%
1/20W
MF
5%
1/20W
MF VCC
2 6.3V
X5R
201
1%
1/20W
MF
RIO POWER CONNECTOR
PCIE_AP_D2R_N OUT 7 17 75
2 201 201 2 2 201 1 G S 2 CRITICAL
NOSTUFF 1 Y+ M+ 5 USB_BT_WAKE_P
1
0.6NH+/-0.1NH-0.85A
C4476 1 C4477 2 Y-
78
J4400
0201
U4410 M- 4 78 USB_BT_WAKE_N 504050-0691
0.1UF OMIT_TABLE 0.1UF NOSTUFF NOSTUFF BTPWR:S4 NOSTUFF M-RT-SM
10% NOSTUFF 10% 1 PI3USB102ZLE
16V
2 X5R-CERM 2 16V
X5R-CERM
R4415 1R4416 TQFN D+ 7 USB_BT_P BI 7 9 36
1
R4412 1R4413 7
0201 0201 15K 15K CRITICAL 74 15K 15K

1% 1% D- 6 USB_BT_N BI 7 9 36 1% 1%
1/20W 1/20W 74 1/20W 1/20W 1
MF MF MF MF
CRITICAL 2 201 2 201 10 SEL 2 201 2 201
2
C L4401
90-OHM-100MA
DLP11S BTPWR:S4 GND
OE* 8
8 =PP1V5_S0_RDRVR
8 =PP5V_S4_RIO
3
4
C
SYM_VER-1
8 =PP3V3_S3_RIO
3
78 36 7 OUT PCIE_CLK100M_AP_CONN_P 1 2 PCIE_CLK100M_AP_P IN 7 17 75
R4411 5
0 80 40 36 7 PP3V3_WLAN_F 6
66 39 38 36 27 18 7 IN PM_SLP_S4_L
1 2 BTMUX_SEL
5% SIGNAL_MODEL=MOJO_MUX
78 36 7 OUT PCIE_CLK100M_AP_CONN_N 4 3 PCIE_CLK100M_AP_N IN 7 17 75 1/20W NOSTUFF 8
MF
PLACE_NEAR=J4410.42:2.54MM 201 C4416 1
0.01UF
10%
R4420 PLACE_NEAR=J4440.4:2.54MM
16V 1
0 2
GND_VOID=TRUE PLACE_NEAR=J4440.2:2.54MM
SEL OUTPUT CERM 2
402 5%
1 C4493 1 C4490 1 C4491 1 C4492 518s0862
0.1UF 0.1UF 0.1UF 0.1UF
RIO FLEX
CRITICAL
CONNECTOR L
H
USB_BT_WAKE
USB_BT
1/20W
MF
201
10%
2 16V
X5R-CERM
10%
2 16V
X5R-CERM
10%
2 16V
X5R-CERM 2 16V
10%
X5R-CERM
0201 0201 0201 0201
C4420 GND_VOID=TRUE
J4410 15PF PLACE_NEAR=J4440.1:2.54MM PLACE_NEAR=J4440.4:2.54MM
DF40CG3.0-70DS-0.4V NOSTUFF 1 2
F-ST-SM
72 71 5% USB3_EXTB_RX_N 7 19 74
25V OUT
NPO
201
66 39 27 18 7 PM_SLP_S3_L 2 1 USB3_EXTB_RX_RC_N GND_VOID=TRUE USB3_EXTB_RX_P 7 19 74
IN OUT
66 39 38 36 27 18 7 IN PM_SLP_S4_L 4 3 USB3_EXTB_RX_RC_P GND_VOID=TRUE C4421 GND_VOID=TRUE
USB_EXTB_OC_L 6 5 GND_VOID=TRUE 15PF
24 7 OUT USB3_EXTB_TX_C_N C4402 0.1UF 2 1 USB3_EXTB_TX_N NOSTUFF 1 2
IN 19 74
74 26 7 USB_EXTB_P 8 7 GND_VOID=TRUE
BI 10% 16V 0201
10 9 X5R-CERM GND_VOID=TRUE 5%
74 26 7 BI USB_EXTB_N C4401 0.1UF 1
2 USB3_EXTB_TX_P 25V
12 11 USB3_EXTB_TX_C_P GND_VOID=TRUE IN 19 74
NPO 40 25 8 =PP3V3_S4_SMC
GND_VOID=TRUE 10% 16V 0201 201
X5R-CERM
16 15 GND_VOID=TRUE R4421 GND_VOID=TRUE 8 =PP3V3_S0_HDMI
42 IN =I2C_HDMIRDRV_SCL HDMI_IG_CLK_C_N IN 7 9 78 0
1 2 PLACE_NEAR=U4430.5:4mm
=I2C_HDMIRDRV_SDA 18 17 HDMI_IG_CLK_C_P 5%
B
42 BI
SDCONN_STATE_CHANGE_RIO 20 19
IN 7 9 78
1/20W
1 C4430 B
25 OUT MF 0.1UF 1
R4430
9 7 HDMI_IG_DDC_CLK 22 21 HDMI_IG_DATA_C_N<2> 7 9 78 201 10%
IN IN
24 23 GND_VOID=TRUE 2 16V
X5R-CERM 100K
9 7 BI HDMI_IG_DDC_DATA HDMI_IG_DATA_C_P<2> IN 7 9 78 0201 5%
26 25 GND_VOID=TRUE 1/20W
MF
74LVC1G00GF 2 201
6
PCIE_CLK100M_ENET_P 30 29 HDMI_IG_DATA_C_N<1> SOT891 2 HDMI_HPD_L
75 17 7 IN IN 7 9 78 A IN 7 36 40
32 31 GND_VOID=TRUE
75 17 7 IN PCIE_CLK100M_ENET_N HDMI_IG_DATA_C_P<1> IN 7 9 78 9 OUT HDMI_HPD 4
U4430
34 33 GND_VOID=TRUE HPD sink High: 2.0V-5.3V
42 IN =I2C_X29THMSNS_SCL B 1
=I2C_X29THMSNS_SDA 36 35 HDMI_IG_DATA_C_P<0> Supervisor & CLKFREG # Isolation NC HPD sink Low: 0.0V-0.8V
42 BI IN 7 9 78
GND_VOID=TRUE 3 5
25 =ENET_RESET_L 38 37 HDMI_IG_DATA_C_N<0> 7 9 78
IN IN
PCIE_CLK100M_AP_CONN_P 40 39 GND_VOID=TRUE Delay = 130 ms +/- 20%
NC
78 36 7 IN
78 36 7 PCIE_CLK100M_AP_CONN_N 42 41 HDMI_HPD_L 7 36 40
IN OUT
44 43 PP3V3_WLAN_F 7 36 40 80 =PP3V3_S3_WLAN 8 36 66
APN:311S0302
PCIE_WAKE_L 48 47 PCIE_ENET_D2R_P CRITICAL
1
18 7 IN OUT 7 17 75
1 1
AP_CLKREQ_Q_L 50 49 PCIE_ENET_D2R_N R4453 R4454 VDD
36 7 IN
AP_RESET_CONN_L 52 51
OUT 7 17 75
100K 232K 1 C4440
36 7 OUT
USB_BT_CONN_P 54 53 PCIE_ENET_R2D_C_P
1%
1/16W
1%
1/16W U4440 0.1uF
20%
74 36 9 7 7 17 75 MF-LF MF-LF SLG4AP041V 2 10V
BI IN
74 36 9 7 USB_BT_CONN_N 56 55 PCIE_ENET_R2D_C_N 7 17 75
2 402 2 402 TDFN CERM
BI IN P3V3WLAN_VMON 402
58 57 2 SENSE +
VREF -
40 39 7 WIFI_EVENT_L 62 61 PCIE_AP_R2D_N 7 36 75
OUT IN
17 7 ENET_CLKREQ_L 64 63 PCIE_AP_R2D_P 7 36 75 DLY
OUT IN
9 7 SD_PWR_EN 66 65 36 7 AP_RESET_CONN_L 4 RESET*
IN OUT MR* 3 AP_RESET_L IN 25
8 =PP3V3_S4_RIO 68 67 PCIE_AP_D2R_PI_P 7 36 75
OUT
70 69 PCIE_AP_D2R_PI_N
A 1
C4410
OUT 7 36 75
EN 6
OUT 8
AP_PWR_EN
AP_CLKREQ_L
IN 19 24 66
17
AP_CLKREQ_Q_L 7 IN (OD)
OUT PAGE TITLE
0.1UF 74 73 36 7 IN
10%
2 16V
X5R-CERM 1
THRM
PAD GND
RIO CONNECTORS
0201 R4455 DRAWING NUMBER SIZE
9
5
100K
1% Apple Inc. <SCH_NUM> D
1/16W REVISION
MF-LF R
2 402 <E4LABEL>
516S1058 NOTICE OF PROPRIETARY PROPERTY: BRANCH
*NOTE: This connector is shielded 70P Hirose Receptacle. THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
44 OF 132
Note: This receptacle mates with the plug with APN 998-4708. III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C4518 & C4517 Placement Note:

It is critical that these two should be near
to U1800 pin AM1 and AM3.
D2R Passive DeEmphasis

VALUE: 0.0 DB
R45061 2 GND_VOID=TRUE
0 5%1/20WMF201 PLACE_NEAR=U1800.AM1:5MM
GND_VOID=TRUE
NOSTUFF
74 37 7 SATA_SSDRHDD_D2R_P C4515 1 2 GND_VOID=TRUE 74 7 SATA_HDD_D2R_RC_P 1 2 C4518 SATA_HDD_D2R_P 7 17 74
D 5.0PF 0201 +/-0.1PF C0G 25V

NOSTUFF
0.01UF 10%16V X7R-CERM 0402
OUT
D
74 37 7 SATA_SSDRHDD_D2R_N C4519 1 2 GND_VOID=TRUE 74 7 SATA_HDD_D2R_RC_N 1 2 C4517 SATA_HDD_D2R_N OUT 7 17 74
5.0PF 0201 +/-0.1PF C0G 25V 0.01UF 10% 16V X7R-CERM 0402
PLACE_NEAR=U1800.AM3:5MM
R45071 2 GND_VOID=TRUE GND_VOID=TRUE
0 5%1/20WMF201
0 5%1/20WMF201
NOSTUFF
74 37 7 SATA_SSDRHDD_R2D_N C4521 1 2 GND_VOID=TRUE
74 7 SATA_HDD_R2D_RC_N C4522 1 2 GND_VOID=TRUE SATA_HDD_R2D_C_N IN 7 17 74
15PF 5% 25V NPO201 0.01UF 10% 16V X7R-CERM 0402
NOSTUFF
74 37 7 SATA_SSDRHDD_R2D_P C4524 1 2 GND_VOID=TRUE
74 7 SATA_HDD_R2D_RC_P C4525 1 2 GND_VOID=TRUE SATA_HDD_R2D_C_P IN 7 17 74
15PF 5%25V NPO201 0.01UF 10% 16V X7R-CERM 0402
0 5%1/20WMF201
R2D Passive DeEmphasis

VALUE: 0.0 DB
C 7 PP3V3_S0_SSD_FLT
MIN_LINE_WIDTH=0.6mm
C
MIN_NECK_WIDTH=0.2mm PLACE_NEAR=J4500.9:3mm
VOLTAGE=3.3V
CRITICAL CRITICAL
L4500 R4530
FERR-70-OHM-4A 0.001
1%
1 2 1W
516S1035 (recpt) 0603
MF
0612
PP3V3_S0_SSD_R 2 1 =PP3V3_S0_SSD 8
MIN_LINE_WIDTH=0.6mm
1 C4501 MIN_NECK_WIDTH=0.4mm
VOLTAGE=3.3V
4 3
0.1UF
CRITICAL PLACE_NEAR=L4500.1:2MM 20% ISNS_SSD_P
10V
2 CERM 1 C4502 ISNS_SSD_N
OUT 43 78
J4500 402
20%
0.1UF OUT 43 78
DF40CG1.5-48DS-0.4V 10V
F-ST-SM 2 CERM
49 50 402
PLACE_NEAR=L4500.2:2MM
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
19 20 GND_VOID=TRUE
SATA_SSDRHDD_D2R_P 7 37 74
21 22 GND_VOID=TRUE
SATA_SSDRHDD_D2R_N 7 37 74
B 40 39 7 IN SMC_OOB1_TX_L
23
25
24
26 B
40 39 7 SMC_OOB1_RX_L 27 28
OUT
29 30
31 32
35 36 GND_VOID=TRUE
SATA_SSDRHDD_R2D_P 7 37 74
37 38 GND_VOID=TRUE
SATA_SSDRHDD_R2D_N 7 37 74
39 40
41 42
43 44
45 46
47 48
51 52
SATA GUMSTICK2 CONNECTOR

L4510
7 PP5V_S0_HDD_FLT FERR-70-OHM-4A
A MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V
1
0603
2 =PP5V_S0_HDD 8
CRITICAL PAGE TITLE
PLACE_NEAR=J4500.39:3MM
SSD/HDD Connectors
DRAWING NUMBER SIZE
2
C4510 2
C4511 <SCH_NUM> D
0.1UF 0.1UF Apple Inc.
20% 20% REVISION
10V 10V R
1
CERM
402
1
CERM
402 <E4LABEL>
PLACE_NEAR=L4510.1:2MM PLACE_NEAR=L4510.2:2MM NOTICE OF PROPRIETARY PROPERTY: BRANCH
<BRANCH>
45 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
USB Port Power Switch
Left USB Port A
8 =PP5V_S3_LTUSB
CRITICAL
PM_SLP_S4_L CRITICAL
66 39 36 27 18 7
U4600 L4605
TPS2557DRB FERR-120-OHM-3A CRITICAL
1
R4690 2 IN_0
SON
5.1K OUT1 6 PP5V_S3_LTUSB_A_ILIM 1 2 PP5V_S3_LTUSB_A_F
5%
1/16W 3 IN_1 OUT2 7
MIN_NECK_WIDTH=0.25 mm 0603 MIN_LINE_WIDTH=0.5 mm
7
514-0835
MF-LF VOLTAGE=5V VOLTAGE=5V
402 2
USB_EXTA_OC_L 8 FAULT* ILIM 5 USB_ILIM C4605 1 J4600
24 OUT
NO_TEST=TRUE
0.1UF USB3.0-LEFT-D1
20% CRITICAL F-RT-TH
USB_PWR_EN 4 EN 10V
CERM 2 L4600
THRM
R46011 402 90-OHM-50MA 1
VBUS
22.1K TCM0605-1 2
GND PAD 1% SYM_VER-1 79 7 USB3_EXTA_TX_C_P SSTX+
1/20W CRITICAL USB_EXTA_MUXED_N 1 4 USB3_EXTA_TX_C_N 3
CRITICAL
9
MF 74 79 7
CRITICAL
C4690 1 1 C4691 201 2 C4695 1 4
SSTX-
C4692 1
C4696 1 10UF GND
10UF 0.1UF 20% 74 7 USB_LT1_N 5
0.47UF 220UF-35MOHM 20% 20% USB_ILIM_R 6.3V 2 74 USB_EXTA_MUXED_P 2 3 D-
10% 20% 6.3V 2 10V
2 CERM X5R 74 7 USB_LT1_P 6
10V 2 6.3V X5R NO_TEST=TRUE 603 D+
X5R POLY-TANT 2 603 402 7
0402 CASE-B2-SM1 GND
USB3_EXTA_RX_F_P 8
R46001 2 5 3 4
79 7
9
SXRX+
22.1K USB3_EXTA_RX_F_N
NC
IO
NC
IO
79 7
1%
SSRX-
1/20W 6 VBUS 10
MF GND
201 2 1 GND
11
C 12 C
13
D4600
CURRENT LIMIT (R4600): 2.19A MIN / 2.76A MAX RCLAMP0582N 14
SLP1210N6 15
CRITICAL 16
17
SIGNAL_MODEL=MOJO_MUX 18
8 =PP3V42_G3H_SMCUSBMUX R4620
SMC_DEBUG_YES 0 GND_VOID=TRUE 19
1 2
SMC_DEBUG_YES 1 20
R4650 5%
C4650 1 10K 1/20W
MF
21
9
0.1UF 5% 22
1/16W 201
20% VCC MF-LF
10V 23
CERM 2
402 5 M+
2 402 C4620 GND_VOID=TRUE
40 39 IN SMC_DEBUGPRT_RX_L Y+ 1 15PF
SMC_DEBUGPRT_TX_L 4 M- Y- 2 1 2
40 39 OUT U4650
PI3USB102ZLE 5%
74 19 USB_EXTA_P 7 D+ TQFN 25V
BI NPO
USB_EXTA_N 6 D- CRITICAL 201
74 19 BI
SMC_DEBUG_YES NOSTUFF
74 19 7 OUT USB3_EXTA_RX_N
8 OE* SEL 10 SMC_DEBUGPRT_EN_L IN 39
GND SEL=0 Choose SMC

SEL=1 Choose USB 74 19 7 OUT USB3_EXTA_RX_P
3
NOSTUFF
NO_XNET_CONNECTION=TRUE C4621 GND_VOID=TRUE
15PF
SMC_DEBUG_NO 2
CRITICAL 1 2
R4651 D4620
ESD0P2RF-02LS
B 1
0 2
NO_XNET_CONNECTION=TRUE
TSSLP-2-1
5%
25V
NPO
201
B
5%
1/16W
SMC_DEBUG_NO 2
MF-LF R4652
1 GND_VOID=TRUE
D4621 CRITICAL R4621 GND_VOID=TRUE
402
ESD0P2RF-02LS 0
1
0 2
1 2
TSSLP-2-1
5%
5% 1/20W
1/16W 1 GND_VOID=TRUE MF
MF-LF 201
402
USB/SMC Debug Mux
GND_VOID=TRUE
USB3_EXTA_TX_N C4610 0.1UF 1 2

74 19 7 IN
10% 16V 0201
X5R-CERM
USB3_EXTA_TX_P C4611 0.1UF 1 2
74 19 IN
10% 16V 0201
X5R-CERM
GND_VOID=TRUE
A CRITICAL CRITICAL SYNC_MASTER=J5_AMD SYNC_DATE=08/24/2011 A

2 2 PAGE TITLE
D4610 D4611 USB 3.0 CONNECTORS
ESD0P2RF-02LS ESD0P2RF-02LS
TSSLP-2-1 TSSLP-2-1 DRAWING NUMBER SIZE
1
GND_VOID=TRUE
1
GND_VOID=TRUE
REVISION
R
<E4LABEL>
<BRANCH>
46 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.
L4901
40 8 =PP3V3_S5_SMC 30-OHM-1.7A
1 2 PP3V3_S5_SMC_VDDA
0402 MIN_LINE_WIDTH=0.25 MM
C4902 1 1 C4903 1 C4904 1 C4905 C4906
1 VOLTAGE=3.3V C4901
0.1UF
1UF 0.1UF 0.1UF 0.1UF 0.1UF 1
R4902 20%
10V
20% 20% 20% 20% 20%
U4900 2 CERM
D
10V
X5R-CERM 2
0603-1
2 10V
CERM
402
2 10V
CERM
402
10V
2 CERM
402
2 10V
CERM
402
1M
5%
1/20W LM4FSXAH5BB
402 D
MF BGA
2 201 (2 OF 2)
57 41 40 7 SMC_RESET_L G10 RST* SWCLK/TCK C10 SMC_TCK 7 40
IN
OMIT_TABLE A10 41
SMC_TMS 7 40
SWDIO/TMS
1 C4907 1 C4908 1 C4909 WIFI_EVENT_L
(OD) B11 PK4/RTCCLK SWO/TDO A11 41
SMC_TDO 41
0.1UF 0.1UF 0.1UF 40 36 7 BI 7 40
U4900 20%
2 10V
20%
2 10V
20%
10V
2 CERM
SMC_WAKE_L
N13 WAKE* TDI B10 SMC_TDI 41
7 40
LM4FSXAH5BB CERM CERM NC_SMC_HIB_L M12 HIB*

402 402 402
NO_TEST=TRUE A2
BGA NC NC
75 41 17 7 BI LPC_AD<0> B13 LPC0AD0 (1 OF 2) AIN00 E2 SMC_ADC0 IN 40
M10
40 IN SMC_CLK32K XOSC0
75 41 17 7 BI LPC_AD<1> A13 LPC0AD1 AIN01 E1 SMC_ADC1 IN 40
NC_SMC_XOSC1 N10 XOSC1
75 41 17 7 BI LPC_AD<2> C12 LPC0AD2 OMIT_TABLE AIN02 F2 SMC_ADC2 IN 40 NO_TEST=TRUE D3
VDDA
75 41 17 7 BI LPC_AD<3> D11 LPC0AD3 AIN03 F1 SMC_ADC3 IN 40
40 SMC_EXTAL G12 OSC0
75 25 7 IN LPC_CLK33M_SMC H12 LPC0CLK AIN04 B3 SMC_ADC4 IN 40 G13
40 SMC_XTAL OSC1 VREFA+ D2 PP3V3_S5_AVREF_SMC 7 40
75 41 17 7 IN LPC_FRAME_L D12 LPC0FRAME* AIN05 A3 SMC_ADC5 IN 40
D1
VREFA-
25 IN SMC_LRESET_L C13 LPC0RESET* AIN06 B4 SMC_ADC6 IN 40
K12 VBAT
XW4900
SM
41 17 7 BI LPC_SERIRQ (OD) H13 LPC0SERIRQ AIN07 A4 SMC_ADC7 IN 40
80 44 43 40 C3 GND_SMC_AVSS 2 1
41 18 7 OUT PM_CLKRUN_L (OD) G11 LPC0CLKRUN* AIN08 B5 SMC_ADC8 IN 40
D7 GNDA E3
41 25 18 7 IN LPC_PWRDWN_L F13 LPC0PD* AIN09 A5 SMC_ADC9 IN 40
E6
PLACE_NEAR=U4900.A1:4MM
20 OUT SMC_RUNTIME_SCI_L F12 LPC0SCI* AIN10 B6 NC FOR STACK BOARD SMC_ADC10 IN 40

E8 A1
20 OUT SMC_WAKE_SCI_L B12 PK5 AIN11 A6 NC FOR STACK BOARD SMC_ADC11 IN 40
E9 C7
AIN12 C1 SMC_ADC12 IN 40 F10 D9
VDD
77 42 BI SMBUS_SMC_0_S0_SCL (OD) E10 I2C0SCL AIN13 C2 SMC_ADC13 IN 40
J7 E5
77 42 BI SMBUS_SMC_0_S0_SDA (OD) D13 I2C0SDA AIN14 B1 SMC_ADC14 IN 40
J9 F9
1 C4920 1 C4921
77 42 7 SMBUS_SMC_1_S0_SCL (OD) M4 I2C1SCL AIN15 B2 SMC_ADC15 40
0.01UF 1UF
BI IN J10 H5 10% 10%
77 42 7 BI SMBUS_SMC_1_S0_SDA (OD) N2 I2C1SDA AIN16 G2 NC FOR STACK BOARD SMC_ADC16 IN 40
H9 2 10V 6.3V
X5R-CERM 2 X5R
77 42 7 SMBUS_SMC_2_S3_SCL (OD) N8 I2C2SCL AIN17 G1 NC FOR STACK BOARD SMC_ADC17 40
GND 0201 402
BI IN PP1V2_S5_SMC_VDDCJ1 J5
C 77 42 7 BI SMBUS_SMC_2_S3_SDA
SMBUS_SMC_3_SCL
(OD)
(OD)
M8
L8
I2C2SDA
I2C3SCL
AIN18
AIN19
H1
H2
NC FOR STACK BOARD SMC_ADC18
SMC_ADC19
IN 40 MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 MM J6 J8 C
77 42 BI
SMBUS_SMC_3_SDA (OD) K8 I2C3SDA AIN20 B7
NC FOR STACK BOARD
SMC_ADC20
IN 40
1 C4910 1 C4911 1 C49121 C49131 C4914 1 C4915 1 C4916 1 C4917VOLTAGE=1.2V K13 VDDC J11
77 42 BI NC FOR STACK BOARD IN 40
1UF 1UF 1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF D6 K11
40 SMBUS_SMC_4_ASF_SCL NC FOR ENG PACKAGE N7 I2C4SCL AIN21 A7 NC FOR STACK BOARD SMC_ADC21 40
10% 10% 10% 20% 20% 20% 20% 20%
2 25V 2 25V 2 25V 2 10V 2 10V 2 10V 10V 10V
BI IN
X5R X5R X5R CERM CERM CERM 2 CERM 2 CERM
40 BI SMBUS_SMC_4_ASF_SDA NC FOR ENG PACKAGE
M7 I2C4SDA AIN22 B8 NC FOR STACK BOARD SMC_ADC22 IN 40
402 402 402 402 402 402 402 402
42 7 BI SMBUS_SMC_5_G3_SCL (OD) N4 I2C5SCL AIN23 A8 1.2V FOR ENG PACKAGE SMC_ADC23 IN 40
42 7 BI SMBUS_SMC_5_G3_SDA (OD) N3 I2C5SDA

C0- K2 CPU_PROCHOT_L IN 11 40 61 72
46 OUT SMC_FAN_0_CTL H11 PM6/FAN0PWM0 C0+ K1 SMC_VCCIO_CPU_DIV2 40
46 IN SMC_FAN_0_TACH L13 PM7/FAN0TACH0 C1- L2 SMC_S5_PWRGD_VIN 40
46 OUT SMC_FAN_1_CTL C11 PK6/FAN0PWM1 PC5/C1+ L1 SPI_DESCRIPTOR_OVERRIDE_L OUT 25 40
46 SMC_FAN_1_TACH A12 PK7/FAN0TACH1 T3CCP1/PJ5/C2- C5 CPU_CATERR_L 11 72

IN IN
7 TP_SMC_MPM5_LED_PWR NC FOR STACK BOARD
G3 PN2/FAN0PWM2 T3CCP0/PJ4/C2+ D5 CPU_THRMTRIP_3V3 40
IN
7 TP_SMC_MPM5_LED_CHG NC FOR STACK BOARD
D10 PN3/FAN0TACH2
SSI0CLK/PA2 M2 SMC_PM_G2_EN OUT 40 66
48 OUT SMC_SYS_KBDLED L11 PN4/FAN0PWM3 SSI0FSS/PA3 M3 PM_DSW_PWRGD OUT 18
40 SMC_T25_EN_L N12 PN5/FAN0TACH3 SSI0RX/PA4 L4 SMC_DELAYED_PWRGD 35 40 66

OUT OUT
40 SYS_TDM_ONEWIRE N11 PN6/FAN0PWM4 SSI0TX/PA5 N1 SMC_PROCHOT 40
BI OUT
56 SYS_ONEWIRE M11 PN7/FAN0TACH4
BI
40 IN HISIDE_ISENSE_OC J4 PH2/FAN0PWM5 U1RX/B0 F11 SMC_DEBUGPRT_RX_L IN 38 40
40 IN SMC_ODD_DETECT J2 PH3/FAN0TACH5 U1TX/PB1 E11 SMC_DEBUGPRT_TX_L OUT 38 40
T0CCP0/PB6 F4 SMC_SYS_LED OUT 40
40 BI CPU_PECI_R C4 PECI0RX T0CCP1/PB7 F3 SMC_GFX_THROTTLE_L BI 40
40 OUT SMC_PECI_L C6 PECI0TX

SSI1RX/PF0 M9 NC FOR STACK BOARD SPI_SMC_MISO IN 40
40 IN SMC_BIL_BUTTON_L M13 PP0/IRQ116 SSI1TX/PF1 N9 NC FOR STACK BOARD SPI_SMC_MOSI OUT 40

L12
B 40
40
IN
IN
SMC_DP_HPD_L
SMC_PME_S4_WAKE_L M5
PP1/IRQ117
PP2/IRQ118
SSI1CLK/PF2
SSI1FSS/PF3
L10
K10
NC FOR STACK BOARD
NC FOR
SPI_SMC_CLK
SPI_SMC_CS_L
STACK BOARD
OUT
OUT
40
40
B
40 SMC_PME_S4_DARK_L J12 PP3/IRQ119 PF4 L9 S5_PWRGD 66
IN IN
66 40 OUT SMC_S4_WAKESRC_EN J13 PP4/IRQ120 PF5 K9 PM_PCH_SYS_PWROK IN 18 24 66
L5 PP5/IRQ121
NC
NC FOR ENG PACKAGE
NC
D8 PP6/IRQ122 WT0CCP0/PG4 K7 SMC_DEBUGPRT_EN_L OUT 38
47 40 IN SMC_LID K6 PP7/IRQ123 WT0CCP1/PG5 L7 SMC_GFX_OVERTEMP IN 40
40 OUT ENET_ASF_GPIO (OD) D4 PQ0/IRQ124 WT2CCP0/PH0 K3 ALL_SYS_PWRGD IN 24 66
49 40 IN SMS_INT_L E4 PQ1/IRQ125 WT2CCP1/PH1 K4 SMC_THRMTRIP OUT 40
56 40 IN SMC_BC_ACOK F5 PQ2/IRQ126
40 IN G3_POWERON_L N5 PQ3/IRQ127 WT3CCP0/PH4 J3 PM_PWRBTN_L OUT 18 24
66 36 27 18 7 PM_SLP_S3_L N6 PQ4/IRQ128 WT3CCP1/PH5 H4 PM_SYSRST_L 7 18 25

IN OUT
66 38 36 27 18 7 PM_SLP_S4_L K5 PQ5/IRQ129 WT4CCP0/PH6 H3 (OD) MEM_EVENT_L 40
IN BI
66 18 PM_SLP_S5_L M6 PQ6/IRQ130 WT4CCP1/PH7 G4 SMC_ADAPTER_EN 18 40 66
IN OUT
47 40 7 SMC_ONOFF_L L6 PQ7/IRQ131
IN
T1CCP0/PJ0 C9 SMC_OOB1_RX_L
NC FOR ENG PACKAGE IN 7 37 40
41 40 7 SMC_RX_L L3 U0RX T1CCP1/PJ1 B9 SMC_OOB1_TX_L 7 37 40

IN OUT
41 40 7 SMC_TX_L M1 U0TX T2CCP0/PJ2 A9 NC FOR ENG PACKAGE IR_RX_OUT_RC 40
OUT IN
PACKAGE BDV_BKL_PWM
T2CCP1/PJ3 C8 NC FOR ENG 40
OUT
74 9 BI USB_SMC_N E13 USB0DM
74 9 BI USB_SMC_P E12 USB0DP WT5CCP1/PM3 H10 SMC_BATLOW_L OUT 40 66
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
A If SMS interrupt is not used, pull up to SMC rail.

SYNC_MASTER=D1_SENSORS SYNC_DATE=02/20/2012 A
PAGE TITLE
SMC
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
49 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ENET_ASF_GPIO NC_ENET_ASF_GPIO
SMC Reset "Button", Supervisor & AVREF Supply 39
=PP3V3_S5_SMC
39 SMC_SYS_LED NC_SMC_SYS_LED
SMC12 PECI SUPPORT
40 39 8
39 MEM_EVENT_L NC_MEM_EVENT_L 7
1 SMC_ODD_DETECT NC_SMC_ODD_DETECT =PPVCCIO_S0_SMC
R5027 R5000 39
8 40
100K CRITICAL
47 5% 57 44 =CHGR_ACOK SMC_BC_ACOK 39 40 56 39 IR_RX_OUT_RC NC_IR_RX_OUT_RC
1 2 PP3V42_G3H_SMC_SPVSR 1/20W MAKE_BASE=TRUE MAKE_BASE=TRUE NO_TEST=TRUE Q5030
MIN_LINE_WIDTH=0.4 mm MF
5% MIN_NECK_WIDTH=0.1 mm 2 201 HISIDE_ISENSE_OC NC_HISIDE_ISENSE_OC SMC_GFX_THROTTLE_L NC_SMC_GFX_THROTTLE_L SSM3K15AMFVAPE
1/20W
MF
1 C5027 VOLTAGE=3.42V
39
39
MAKE_BASE=TRUE NO_TEST=TRUE VESM
D 3
201 4.7UF 39 SMC_ADC0 SMC_CPU_VSENSE 43 40 39 SMC_GFX_OVERTEMP NC_SMC_GFX_OVERTEMP 40
20% MAKE_BASE=TRUE MAKE_BASE=TRUE
6.3V NO_TEST=TRUE
2 X5R
Mac Mini: 5V 8 =PPVIN_S5_SMCVREF 39 SMC_ADC1 SMC_CPU_ISENSE 43 39 SMC_T25_EN_L NC_T25_EN_L
D Mobiles: 3.42V
402
R5028 39 SMC_ADC2
MAKE_BASE=TRUE
NC_SMC_GPU_HI_ISENSE 40 39 SMC_GFX_OVERTEMP
NC_SMC_GFX_OVERTEMP 40 1 G S 2
D
1
0 2 SMC_RESET_LOUT MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE R5032
7 39 41 57
SMC_ADC3 SMC_DCIN_VSENSE SYS_TDM_ONEWIRE NC_SYS_TDM_ONEWIRE 0
3
GND_SMC_AVSS C5020 1 V+ VIN
5%
1/20W NOSTUFF
39
MAKE_BASE=TRUE
44 39
MAKE_BASE=TRUE NO_TEST=TRUE IN SMC_PECI_L1 2 SMC_PECI_L_R
80 44 43 40 39
0.47UF MF SMC_ADC4 SMC_DCIN_ISENSE 5%
10%
6.3V U5010 201 C5028 1 39
MAKE_BASE=TRUE
44
CPU_PROCHOT_L
1/20W
MF
OMIT
CERM-X5R 2 1000PF SMC_ADC5 SMC_PBUS_VSENSE 72 61 39 11 BI 1 1
402 VREF-3.3V-VDET-3.0V 10%
16V 2
39
MAKE_BASE=TRUE
44 201 R5033 R5031
6 MR1* (IPU)
DFN
X7R NOSTUFF 330
47 IN SMC_TPAD_RST_L SN0903048 RESET* 5 SMC_RESET_R_L 201 39 SMC_ADC6 SMC_SSD_ISENSE 43 CRITICAL NONE 5%
7 MR2* (IPU) MAKE_BASE=TRUE NONE 1/20W
47 40 39 7 SMC_ONOFF_L D NONE MF
IN PP3V3_S5_AVREF_SMC
7 39 39 SMC_ADC7 SMC_BMON_ISENSE
MAKE_BASE=TRUE
44
6
Q5059 2 402 2 201
SMC_MANUAL_RST_L 4 DELAY CRITICAL REFOUT 8 MIN_NECK_WIDTH=0.1 mm SSM6N15AFE
THRM VOLTAGE=3.3V 39 SMC_ADC8 SMC_CPU_HI_ISENSE 44 SOT563
OMIT GND PAD MAKE_BASE=TRUE
1 SMC_ADC9 SMC_OTHER_HI_ISENSE
R5001 C5001 1 NOSTUFF 39 44
R5034
2
9
MAKE_BASE=TRUE
0
5% 0.01UF C5025 1 1 C5026 SMC_ADC10 SMC_MEM_ISENSE 1 S G 2 CPU_PECI_R 1 43 2 CPU_PECI
1/10W 10% 10UF 0.1UF 39
MAKE_BASE=TRUE
43 39 OUT BI 11 20 72
MF-LF 10V 20% 10% SMC_PROCHOT 5%

X5R-CERM 2
ADC10 AND ADC11 ARE SHARED WITH COMPARATORS ON STACK BOARD 39 From/To CPU/PCH
603 6.3V 2 10V SMC_ADC11 SMC_VCCIO_ISENSE IN 1/20W
2 0201 CERM-X5R 2 X5R-CERM 39
MAKE_BASE=TRUE
43 To SMC
MF
SILK_PART=SMC_RST 0402-1 0201 201
39 SMC_ADC12 SMC_AXG_VSENSE 43
MAKE_BASE=TRUE 20 OUT PM_THRMTRIP_L_R
PLACE_SIDE=BOTTOM GND_SMC_AVSS 39 40 43 44 80
MIN_LINE_WIDTH=0.4 mm 39 SMC_ADC13 SMC_CPU_SA_ISENSE 80 CRITICAL
MIN_NECK_WIDTH=0.1 mm MAKE_BASE=TRUE
MR1* and MR2* must both be low to cause manual reset. VOLTAGE=0V
Used on mobiles to support SMC reset via keyboard.
39 SMC_ADC14 SMC_CPU_SA_VSENSE
MAKE_BASE=TRUE
80
3 D Q5059
SSM6N15AFE
39 SMC_ADC15 SMC_LCD_PANEL_ISENSE 80 SOT563
NOTE: Internal pull-ups are to VIN, not V+. 40 8 =PPVCCIO_S0_SMC MAKE_BASE=TRUE
SMC_ADC16 SMC_LCDBKLT_VSENSE
Debug Power "Buttons"
39
SMC_ADC17
MAKE_BASE=TRUE
SMC_LCDBKLT_ISENSE
80
4 S G 5
SMC12 SPI SUPPORT
SERIES RESISTORS ARE NO STUFFED UNTIL THE TOPOLOGY OF 2 SPI MASTERS IS VERIFIED
39 80
1 MAKE_BASE=TRUE
SMC_ONOFF_L OUT 7 39 40 47
R5097 39 SMC_ADC18 SMC_AXG_ISENSE 43 SMC_THRMTRIP IN 39 40
100K MAKE_BASE=TRUE R5021
OMIT OMIT 1%
SMC_ADC19 NC_SMC_GPU_P1V35_ISENSE 24
C R5016
PLACE_SIDE=BOTTOM 0
1 1
R5015
0 PLACE_SIDE=TOP
1/20W
MF
2 201
39
39 SMC_ADC20
MAKE_BASE=TRUE
NC_SMC_T25_ISENSE
NO_TEST=TRUE 39 IN SPI_SMC_MISO 1
5%
2 SPI_MLB_MISO
PLACE_NEAR=U6100.2:1MM
OUT 41 50 C
5% 5% MAKE_BASE=TRUE NO_TEST=TRUE R5022 1/20W
1/10W 1/10W 39 SMC_VCCIO_CPU_DIV2 MF
MF-LF MF-LF 39 SMC_ADC21 NC_SMC_PCH_CORE_ISENSE 43 201
603 2 2 603 MAKE_BASE=TRUE NO_TEST=TRUE 39 IN SPI_SMC_MOSI 1 2 SPI_MLB_MOSI OUT 41 50
1 PLACE_NEAR=U6100.5:1MM
SILK_PART=PWR_BTN SILK_PART=PWR_BTN R5096 39 SMC_ADC22 SMC_X29_ISENSE 80 5%
R5023
MAKE_BASE=TRUE 1/20W
100K MF 15
1% 39 SMC_ADC23 SMC_TBT_ISENSE IN 80 39 IN SPI_SMC_CLK 201 1 2 SPI_MLB_CLK OUT 41 50
1/20W MAKE_BASE=TRUE PLACE_NEAR=U6100.6:1MM
MF 5%
2 201 39 SMBUS_SMC_4_ASF_SCL NC_SMBUS_SMC_4_ASF_SCL R5024 1/20W
MAKE_BASE=TRUE NO_TEST=TRUE MF
15 201
SMC Crystal Circuit 39 SMBUS_SMC_4_ASF_SDA NC_SMBUS_SMC_4_ASF_SDA
39 IN SPI_SMC_CS_L 1 2 SPI_MLB_CS_L
OUT 41 50
5%
39 BDV_BKL_PWM NC_BDV_BKL_PWM 1/20W
MAKE_BASE=TRUE NO_TEST=TRUE R5058 MF 40 39 8 =PP3V3_S5_SMC
R5010 201
40 39 SMC_PME_S4_DARK_L SDCONN_STATE_CHANGE_SMC 7 25 3.3K 2 40 36 25 8 =PP3V3_S4_SMC
2.49K2 MAKE_BASE=TRUE PM_THRMTRIP_B_L 1 PM_THRMTRIP_L IN 11 20 72
39 SMC_XTAL 1 SMC_XTAL_R
=TBT_WAKE_L 33 5%
1%
1/20W
CRITICAL 1/16W
MF-LF
MF
201 Y5010 OMIT_TABLE 40 39 OUT CPU_THRMTRIP_3V3 402 SMC_OOB1_RX_L
39 37 7 R5067 100K 1 2 NO STUFF
SM-3.2X2.5MM R5012 SMC_OOB1_TX_L
39 37 7 R5068 100K 1 2 5% 1/20W MF
NO STUFF
201
12.000MHZ-30PPM-10PF 22 R5069 100K 5% 1/20W MF 201
18 IN PM_CLK32K_SUSCLK_R 1 2 SMC_CLK32K OUT 39 40 39 SMC_PME_S4_DARK_L 1 2
39 SMC_EXTAL 1 3 PLACE_NEAR=U1800.N14:5.1mm
R5070 10K 5% 1/20W MF 201
5% 47 40 39 7 SMC_ONOFF_L 1 2
1/20W 5% 1/20W MF 201
2 4 MF
201
39 G3_POWERON_L R5072 10K 1 2
NCNC CRITICAL SMC_LID R5071 100K 1 2
5% 1/20W MF 201
1 C5010 1 C5011 3
47 40 39
SMC_TX_L R5073 10K 1 2 5% 1/20W MF 201

5%
12PF
5%
12PF Q5058 1
41 39 7
SMC_RX_L R5074 100K 1 2 5% 1/20W MF 201

25V 2 25V MMBT3904LP-7 41 39 7
2 NP0-C0G
0201
NP0-C0G
0201 HDMI HPD ESD PROTECTION DFN1006-3
2
39 38 SMC_DEBUGPRT_TX_L
SMC_DEBUGPRT_RX_L
R5075
R5076
10K
100K
1
1
2
2
5% 1/20W
5% 1/20W
MF
MF
201
201
39 38
5% 1/20W MF 201
41 39 7 SMC_TMS R5077 10K 1 2
R5078 10K 5% 1/20W MF 201
R5057 41 39 7 SMC_TDO 1 2
B 36 7 IN HDMI_HPD_L 1
1K 2 SMC_DP_HPD_L OUT 39
41 39 7 SMC_TDI R5079
R5080
10K
10K
1 2
5% 1/20W
5% 1/20W
MF
MF
201
201
B
MAKE_BASE=TRUE 41 39 7 SMC_TCK 1 2
5% 5% 1/20W MF 201
SMC USB CLOCK REQUIRE THESE CRYSTAL VALUES:5,6,8,10,12,16,18,20,24,25 MHZ 1/20W
MF =PP3V3_S4_SMC 39 SMC_BIL_BUTTON_L R5081 10K 1 2
5% 1/20W MF 201
201
8 25 36 40
56 40 39 SMC_BC_ACOK R5087 100K 1 2
1 39 SMC_S5_PWRGD_VIN R5092 100K 1 2 5% 1/20W MF 201
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION R5082 SMS_INT_L NOSTUFF R5093 10K 1 2 5% 1/20W MF 201
49 39
197S0486 1 XTAL,12MHZ,30PPM,10PF,3.2X2.5X0.7MM,90C Y5010 CRITICAL S4 SMC WAKE SOURCES 100K

5%
1/20W
40 39 CPU_THRMTRIP_3V3
SPI_DESCRIPTOR_OVERRIDE_L NOSTUFF
R5094
R5095
100K
10K
1
1
2
2
5% 1/20W
5% 1/20W
MF
MF
201
201
MF 39 25
2 201 41 7 SMC_ROMBOOT 5% 1/20W MF 201
=PSOC_WAKE_L SMC_PME_S4_WAKE_L 1
47 IN
MAKE_BASE=TRUE OUT 39
R5088
1K
5%
36 IN =BT_WAKE_L 1/20W
MF
SMC_THRMTRIP R5086 10K 1 2 201 2
Hall Effect pads 40 39
5% 1/20W MF 201
66 39 18 SMC_ADAPTER_EN R5085 10K 1 2
5% 1/20W MF 201
66 39 SMC_S4_WAKESRC_EN R5090 100K 1 2
APN: 998-4692 =PP3V42_S3_HALL 5% 1/20W MF 201
OMIT_TABLE
8
66 39 35 SMC_DELAYED_PWRGD R5091 100K 1 2
5% 1/20W MF 201
J5050 66 39 SMC_PM_G2_EN R5098 100K 1 2
HALL-EFFECT-SENSOR-MLB-D1
SM BATLOW# ISOLATION 5% 1/20W MF 201
NC
1 8
NC
R5050
2 7 0 80 36 7 PP3V3_WLAN_F
SMC_LID_R 1 2 SMC_LID 39 40 47 8 =PP3V3_S5_SMCBATLOW =PP3V3_SUS_SMC 8
3 6 5% CRITICAL
1/16W WIFI_EVENT_L R5089 10K 1 2
NC
4 5
NC MF-LF
402
1 C5050 Q5040
39 36 7
5% 1/20W MF 201
A 0.001UF
10%
2 50V
R50401
100K
SSM3K15AMFVAPE
VESM
X7R-CERM 5% PAGE TITLE
0402 1/20W G 1
MF
201 2 Internal 20K pull-up on PM_BATLOW_L in PCH.
SMC Support
DRAWING NUMBER SIZE
<SCH_NUM> D
D
66 39 IN SMC_BATLOW_L PM_BATLOW_L OUT 18 Apple Inc. REVISION

3
R
<E4LABEL>
R5041 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1
0 2 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
607-9320 1 SUBASSY,PCBA HALL EFFECT,J4 J5050 CRITICAL THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5% NOSTUFF
1/16W
MF-LF
50 OF 132
639-3261 (J4 Hall effect board) reports to 607-9320 402
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
LPC+SPI Connector
D D
LPCPLUS_CONN:YES
CRITICAL
J5100
DF40C-30DP-0.4V
M-ST-SM
8 =PP3V3_S5_LPCPLUS 31 32
8 =PP5V_S0_LPCPLUS
1 2 SPI_ALT_MISO 7 41
IN
75 25 7 LPC_CLK33M_LPCPLUS 3 4 LPC_FRAME_L 7 17 39 75
BI BI
75 39 17 7 LPC_AD<0> 5 6 SPIROM_USE_MLB 7 20 50
BI BI
7 8
75 39 17 7 LPC_AD<2> 9 10 PM_CLKRUN_L 7 18 39
IN OUT
75 39 17 7 LPC_AD<1> 11 12 SPI_ALT_CLK 7 41
OUT IN
75 39 17 7 LPC_AD<3> 13 14 SPI_ALT_CS_L 7 41
IN IN
41 7 SPI_ALT_MOSI 15 16 LPC_SERIRQ 7 17 39
OUT BI
20 7 LPCPLUS_GPIO 17 18 LPC_PWRDWN_L 7 18 25 39
OUT IN
25 7 LPCPLUS_RESET_L 19 20 SMC_TDI 7 39 40
IN OUT
40 39 7 SMC_TDO 21 22 SMC_TCK 7 39 40
OUT OUT
7 TP_SMC_TRST_L 23 24 SMC_RESET_L 7 39 40 57
OUT
7 TP_SMC_MD1 25 26 SMC_ROMBOOT 7 40
OUT
40 39 7 SMC_TX_L 27 28 SMC_RX_L 7 39 40
IN OUT
29 30 SMC_TMS 7 39 40
OUT
33 34
C 998-4235
C
SPI Bus Series Termination

SPI_ALT_MISO 7 41
SPI_ALT_MOSI 7 41
SPI_ALT_CLK 7 41
SPI_ALT_CS_L 7 41
LPCPLUS_R:YES LPCPLUS_R:YES
1 1 1 1
R5128 R5127 R5126 R5125 PLACE_NEAR=J5100.14:5mm
24 43 43 43 PLACE_NEAR=J5100.12:5mm
5% 5% 5% 5% PLACE_NEAR=J5100.9:5mm
1/16W 1/16W 1/16W 1/16W PLACE_NEAR=J5100.11:5mm
MF-LF MF-LF MF-LF MF-LF
2 402 2 402 2 402 2 402
LPCPLUS_R:YES LPCPLUS_R:YES
PLACE_NEAR=U1800.AV3:5mm R5110 R5120
15 43
75 17 IN SPI_CS0_R_L 1 2 75 SPI_CS0_L 1 2 SPI_MLB_CS_L OUT 40 50
5% 5% PLACE_NEAR=R5125.2:5mm
1/16W 1/16W
B PLACE_NEAR=U1800.BA2:5mm R5111
15
MF-LF
402 R5121
43
MF-LF
402 B
75 17 IN SPI_CLK_R 1 2 75 SPI_CLK 1 2 SPI_MLB_CLK OUT 40 50
1/16W 1/16W
PLACE_NEAR=U1800.AY1:5mm R5112 MF-LF R5122 MF-LF
402 402
SPI_MOSI_R 1
15 2 75 SPI_MOSI 1
43 2 SPI_MLB_MOSI
75 17 IN OUT 40 50
1/16W 1/16W
MF-LF R5123 MF-LF
402 402
24
75 17 OUT SPI_MISO 1 2 SPI_MLB_MISO IN 40 50
5% PLACE_NEAR=U6100.2:5mm
1/16W
MF-LF
402
A SYNC_MASTER=D1_SENSORS SYNC_DATE=02/20/2012 A
PAGE TITLE
LPC+SPI Debug Connector

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
51 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PCH SMBus "0" Connections SMC "0" SMBus Connections SMC "5" SMBUS CONNECTIONS
42 8 =PP3V3_S0_SMBUS_PCH 8 =PP3V3_S0_SMBUS_SMC_0_S0 8 =PP3V42_G3H_SMBUS_SMC_5
Panther Point R52001 1

R5201 SMC R52501 1
R5251 GPU Temp (Ext) SMC R52801 1
R5281 Battery Charger
1K
5%
1K
5%
TBT 4.7K
5%
4.7K
5%
2.0K
5%
2.0K
5%
U1800 1/20W 1/20W U3600 U4900 1/20W 1/20W EMC1414-A: U5550 U4900 1/20W 1/20W ISL6258 - U7000
MF MF MF MF MF MF
(MASTER) 201 2 2 201 (WRITE: 0XXX READ: 0XXX) (MASTER) 201 2 2 201 (Write: 0x98 Read: 0x99) (MASTER) 201 2 2 201 (Write: 0x12 Read: 0x13)
77
75 17 7 SMBUS_PCH_CLK =I2C_TBTRTR_SCL 33 SMB_0_S0_CLK 39 SMBUS_SMC_0_S0_SCL =SMBUS_GPUTHMSNS_SCL 45 SMB_5_CLK SMBUS_SMC_5_G3_SCL =SMBUS_CHGR_SCL 57
D 75 17 7
MAKE_BASE=TRUE
SMBUS_PCH_DATA =I2C_TBTRTR_SDA 33 SMB_0_S0_DATA 77
39
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SDA =SMBUS_GPUTHMSNS_SDA 45 SMB_5_DATA
MAKE_BASE=TRUE
SMBUS_SMC_5_G3_SDA =SMBUS_CHGR_SDA 57
D
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
VRef DACs Battery

U3300
AUDIO J6955
U6411 Battery
(Write: 0x98 Read: 0x99) (See Table)
(WRITE: 0X34 READ: 0X35)
Battery Manager - (Write: 0x16 Read: 0x17)
31 =I2C_VREFDACS_SCL =SMBUS_BATT_SCL 56
31 =I2C_VREFDACS_SDA =SMBUS_BATT_SDA 56
Margin Control SMC "2" SMBUS CONNECTIONS

NOTE: SMC RMT bus remains powered and may be active in S3 state
U3301 AUDIO SMC "3" SMBUS CONNECTIONS
(Write: 0x30 Read: 0x31) 8 =PP3V3_S3_SMBUS_SMC_2_S3
U6410
31 =I2C_PCA9557D_SCL (WRITE: 0X32 READ: 0X33) 8 =PP3V3_S3_SMBUS_SMC_3
31 =I2C_PCA9557D_SDA
SMC R52701 1
R5271 Trackpad DEBUG_ADC DEBUG_ADC
1K 1K
U4900
5%
1/20W
5%
1/20W J5800 SMC R52901 1
R5291 DEBUG SENSOR ADC A
MF MF 4.7K 4.7K
(MASTER) 201 2 2 201 (Write: 0x90 Read: 0x91) 5% 5%
U4900 1/20W 1/20W UD000
MIKEY SMB_2_S3_CLK SMBUS_SMC_2_S3_SCL =I2C_TPAD_SCL MF MF
47 (MASTER) 201 2 2 201 (Write: 0x10 Read: 0x11)
MAKE_BASE=TRUE
U6751 77
SMB_2_S3_DATA SMBUS_SMC_2_S3_SDA =I2C_TPAD_SDA 47 SMB_3_CLK 39 SMBUS_SMC_3_SCL =I2C_SMC_ADCS_SCL
C 54
=I2C_MIKEY_SCL AUDIO
MAKE_BASE=TRUE
SMB_3_DATA
MAKE_BASE=TRUE
77
39 SMBUS_SMC_3_SDA
MAKE_BASE=TRUE
=I2C_SMC_ADCS_SDA C
54 =I2C_MIKEY_SDA U6400 ALS
(WRITE: 0XE0 READ: 0XE1) J3502
(Write: 0x72 Read: 0x73)
XDP Connectors =I2C_ALS_SCL

J2500 & J2550
32
PCH "SMLink 0" Connections
=I2C_ALS_SDA 32
(MASTER)
42 8 =PP3V3_S0_SMBUS_PCH
24 =SMBUS_XDP_SCL
SMS
24 =SMBUS_XDP_SDA AUDIO U5920
U6750 (WRITE: 0X30/31 READ: 0X32/33)
Panther Point R52101 1
R5211
(WRITE: 0X76 READ: 0X77) GYRO 8.2K 8.2K
5% 5%
49 =I2C_SMC_SMS_SCL U1800 1/20W 1/20W
U5940 MF MF
(MASTER) 201 2 2 201
(WRITE: 0XD0 READ: 0XD1)
49 =I2C_SMC_SMS_SDA
75 17 SML_PCH_0_CLK
=I2C_SMC_GYRO_SCL 49 MAKE_BASE=TRUE
75 17 SML_PCH_0_DATA
=I2C_SMC_GYRO_SDA 49 MAKE_BASE=TRUE
HDMI Redriver (on RIO)

J4410
(WRITE: 0xCC READ: 0xCD)
B =I2C_HDMIRDRV_SCL 36
SMC "1" SMBUS CONNECTIONS B
=I2C_HDMIRDRV_SDA 36
8 =PP3V3_S0_SMBUS_SMC_1_S0
SMC R52601 1
R5261 CPU/DDR3/PCH/AIRFLOW TEMP
1K 1K
LED BACKLIGHT 5% 5%
U4900 1/20W 1/20W EMC1414-A: U5570
U9700 MF MF
(MASTER) 201 2 2 201 (Write: 0x98 Read: 0x99)
SMB_1_S0_CLK SMBUS_SMC_1_S0_SCL =I2C_CPUTHMSNS_SCL 45
MAKE_BASE=TRUE
=I2C_BKL_1_SCL 71
SMB_1_S0_DATA SMBUS_SMC_1_S0_SDA =I2C_CPUTHMSNS_SDA 45
MAKE_BASE=TRUE
=I2C_BKL_1_SDA 71
PCH "SMLink 1" Connections
X29 TEMP
Panther Point
TMP105: U5523
U1800
(Write: 0x88 Read: 0x89)
=I2C_X29THMSNS_SCL 36
75 17 SML_PCH_1_CLK
=I2C_X29THMSNS_SDA 36
75 17 SML_PCH_1_DATA
PAGE TITLE
SMLink 1 is slave port to

SMBus Connections
SPKR TEMP DRAWING NUMBER SIZE
U6420
access PCH & CPU via PECI.
(WRITE: 0XD8 READ: 0XD9) Apple Inc. <SCH_NUM> D
REVISION
U6421 R

<E4LABEL>
=I2C_SPKRTHMSNS_SCL THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
=I2C_SPKRTHMSNS_SDA I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
52 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU/PCH VCCIO & TBT 1.05V Load Side Current Sense (IC1C)
Gain: 200x, EDP: 20 A
Rsense: 0.001 (R7640)
V across Rsense: 15 mV
SMC ADC: 11 CPU Core Load Side Current Sense (IC0C)
Gain: 161.7x, EDP: 53 A
Rsense: 2x of 0.00075 (R7510, R7520), Rsum: 0.000375
80 8 =PP3V3_S0_ISNS V across Rsense: 19.8 mV
1 C5360 SMC ADC: 01
0.1uF
D
3
D V+
20%
10V
2 CERM
402 NO_XNET_CONNECTION=TRUE
U5360 LOADISNS:YES R5369 R5345 =PP3V3_S0_IMVPISNS
LOADISNS:YES
INA210 4.53K2 4.42K2 43 8
CPUVCCIOS0_CS_N 5 IN- SC70 OUT 6 CPUVCCIO_IOUT 1 SMC_VCCIO_ISENSE CPUIMVP_ISNS1_P 1

78 63 IN
PLACE_NEAR=R7640.3:5MM
1%
OUT 40 78 62 61 IN
PLACE_NEAR=R7510.4:5MM 0.1% LOADISNS:YES
1 C5340
1/20W 1/16W CRITICAL 0.1UF
78 63 IN CPUVCCIOS0_CS_P
4 IN+ REF 1 MF
201
1 C5369 LOADISNS:YES LOADISNS:YES
MFNO_XNET_CONNECTION=TRUE
0402
20%
10V
2 CERM
LOADISNS:YES
0.22UF
20% R5346 R5342 U5340 402
5
GND 2 6.3V 4.42K2 78 CPUIMVP_ISNS_P 2.21K2 ISL28133
PLACE_NEAR=U4900.A6:5MM X5R
0201 78 62 61 IN CPUIMVP_ISNS2_P 1 1 78 CPUIMVP_ISUM_R_P 1 SC70-5 R5349
2
LOADISNS:YES V+ 4 4.53K2
LOADISNS:YES PLACE_NEAR=R7520.3:5MM 0.1% 0.1% CPUIMVP_ISUM_IOUT 1 SMC_CPU_ISENSE OUT 40
PLACE_NEAR=U4900.A6:5MM 1/16W 1/16W
CRITICAL LOADISNS:YES MFNO_XNET_CONNECTION=TRUE MF 3 V- 1%
0402 0402 1/20W
GND_SMC_AVSS R5347 R5343 MF 1 C5349
2
39 40 43 44 80 201 0.22UF
4.42K2 2.21K2 78 CPUIMVP_ISUM_R_N 20%
78 62 CPUIMVP_ISNS1_N 1 78 CPUIMVP_ISNS_N 1 LOADISNS:YES
IN
PLACE_NEAR=U4900.E1:5MM 2 6.3V
X5R
0.1% 0.1%
DDR 1.35V S3 (Memory) Current Sense (IM0C) PLACE_NEAR=R7510.3:5MM
LOADISNS:YES 1/16W
0402
1/16W
MF
0402
0201
LOADISNS:YES
Gain: 364.9x, EDP: 9 A PLACE_NEAR=U4900.E1:5MM
Rsense: 0.001 (R5370) R5348 LOADISNS:YES R5341
V across Rsense: 9 mV 78 62 IN CPUIMVP_ISNS2_N 14.42K2 715K 2 GND_SMC_AVSS 39 40 43 44 80
1
SMC ADC: 10 =PP3V3_S3_ISNS PLACE_NEAR=R7520.4:5MM 0.1% 1 LOADISNS:YES
43 8 PLACE_NEAR=U5370.8:3MM
LOADISNS:YES 1/16W
MF R5344 0.1%
1/16W
0402 715K MF
CRITICAL
1 C5370 0.1%
1/16W
402
0.1UF MF
20%
=PPVIN_S3_MEM_ISNS_R 2 10V 2 402
8 IN
R5371 U5370 CERM
402 LOADISNS:YES
OPA2330
1 3 ISNS_1V35_S3_MEM_P 12.74K2 8 DFN R5379
R5370 78 ISNS_1V35_S3_MEM_R_P 3
V+ 4.53K2
0.001 1% 1 ISNS_1V35_S3_MEM_IOUT 1 SMC_MEM_ISENSE OUT 40
1% 1/16W
1W
C MF-1
0612 2 4
MF-LF
402
R5372
2
THRM
V-
4
1%
1/20W
MF
201
1 C5379 C
2.74K2 78 9
PLACE_NEAR=U4900.B6:5MM
0.22UF
8 =PPVIN_S3_MEM_ISNS 78 ISNS_1V35_S3_MEM_N 1 ISNS_1V35_S3_MEM_R_N 20%
OUT 6.3V
2 X5R
1% 1 0201
1/16W
MF-LF R5373
402 1M PLACE_NEAR=U4900.B6:5MM
1%
1/16W
MF-LF R5374
2 402 1
1M 2
GND_SMC_AVSS 39 40 43 44 80
1%
1/16W
MF-LF
402
AXG Core Load Side Current Sense (IN0C)
SSD Current Sense (ISDC) Gain: 190.6x, EDP: 46 A
Rsense: 2x of 0.00075 (R7550, R7560), Rsum: 0.000375
Gain: 649.35x, EDP: 5 A (16.5 W)
V across Rsense: 17.25 mV
Rsense: 0.001 (R5370)
SMC ADC: 18
V across Rsense: 5 mV
SMC ADC: 06 43 8 =PP3V3_S3_ISNS
CRITICAL R5355 LOADISNS:YES
43 8 =PP3V3_S0_IMVPISNS PLACE_NEAR=U5350.5:3MM
4.42K2
CPUIMVP_ISNS1G_P 1
R5381 U5370 78 62 IN
0.1%
1 C5350
OPA2330 PLACE_NEAR=R7550.3:5MM LOADISNS:YES 0.1UF
ISNS_SSD_P
1.54K2
1 ISNS_3V3_S0_SSD_R_P 5 8 DFN R5389 LOADISNS:YES
1/16W
LOADISNS:YES
CRITICAL 20%
78 37 78
IN 4.53K2 SMC_SSD_ISENSE 0402 10V
1% V+ 7 ISNS_3V3_S0_SSD_IOUT 1 U5350 2 CERM
1/20W OUT 40
R5356 R5352 402
5
MF 6 1% 4.42K2 1.54K2 ISL28133
201 V- 1/20W CPUIMVP_ISNS2G_P 1 78 CPUIMVP_ISNSG_P 1 78 CPUIMVP_ISUMG_R_P 1 SC70-5 R5359
R5382 THRM 4 MF
201
1 C5389 78 62 IN
PLACE_NEAR=R7560.3:5MM 0.1% 1% V+ 4 CPUIMVP_ISUMG_IOUT 14.53K2 SMC_AXG_ISENSE
1.54K2 9 0.22UF 1/16W 1/16W OUT 40
B 78 37 IN ISNS_SSD_N 1
1%
78 ISNS_3V3_S0_SSD_R_N
1
20%
6.3V
2 X5R
0201
LOADISNS:YES MFNO_XNET_CONNECTION=TRUE
0402
R5357
MF-LF
R5353
402
3 V- 1%
1/20W
MF 1 C5359 B
2
1/20W
MF R5383 4.42K2 1.54K2 78 CPUIMVP_ISUMG_R_N
201 0.22UF
20%
201 1M PLACE_NEAR=U4900.B4:5MM 78 62 CPUIMVP_ISNS1G_N 1 78 CPUIMVP_ISNSG_N 1 LOADISNS:YES
1% IN
PLACE_NEAR=U4900.H1:5MM 2 6.3V
X5R
1/16W R5384 PLACE_NEAR=R7550.4:5MM 0.1% 1% 0201
MF-LF LOADISNS:YES 1/16W 1/16W
2 402 1M GND_SMC_AVSS 39 40 43 44 80 MFNO_XNET_CONNECTION=TRUE MF-LF LOADISNS:YES
1 2 0402 402 PLACE_NEAR=U4900.H1:5MM
1% R5358 LOADISNS:YES R5351
1/16W 4.42K2
MF-LF 78 62 IN CPUIMVP_ISNS2G_N 1 715K 2 GND_SMC_AVSS 39 40 43 44 80
402 1
NO_XNET_CONNECTION=TRUE PLACE_NEAR=R7560.4:5MM 0.1% 1 LOADISNS:YES
LOADISNS:YES 1/16W
MF R5354 0.1%
1/16W NO_XNET_CONNECTION=TRUE
0402 715K MF
0.1% 402
MF
2 402
CPU Core Voltage Sense (VC0C) LOADISNS:YES
Gain: 1x
SMC ADC: 00 PLACE_NEAR=R7510.2:5 MM PLACE_NEAR=U4900.E2:5MM
XW5320
SM R5329
4.53K2
15 13 10 8 =PPVCORE_S0_CPU 1 2 CPUVSENSE_IN 1 SMC_CPU_VSENSE OUT 40 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
1% PLACE_NEAR=U4900.E2:5MM
1/20W 117S0008 3 RES,MTL FLIM,100K,1/16W,0201,SMD,LF C5349,C5359,C5369 LOADISNS:NO
MF
201
1 C5329
0.22UF
20%
6.3V
2 X5R
0201
GND_SMC_AVSS 39 40 43 44 80
AXG Core Voltage Sense (VN0C)

A Gain: 1x
SMC ADC: 12
PLACE_NEAR=R7550.2:5 MM PAGE TITLE
PLACE_NEAR=U4900.C1:5MM
XW5330
SM R5339 Power Sensor: Load Side
4.53K2 DRAWING NUMBER SIZE
=PPVCORE_S0_CPU_VCCAXG 1 2 AXGVSENSE_IN 1 SMC_AXG_VSENSE
16 13 10 8
1% PLACE_NEAR=U4900.C1:5MM
OUT 40

1/20W REVISION
MF
201
1 C5339 R
<E4LABEL>
0.22UF
20% NOTICE OF PROPRIETARY PROPERTY: BRANCH
6.3V
2 X5R
0201 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
GND_SMC_AVSS 39 40 43 44 80
53 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CPU High Side Current Sense (IC0R) PBUS Voltage Sense & Enable (VP0R)
Gain: 50x, EDP: 17.4 A Gain: 0.167x
Rsense: 0.003 (R5400) SMC ADC: 05
V across Rsense: 52.2 mV CRITICAL
SMC ADC: 08 =PP3V3_S0_HS_COMPUTING_ISNS
8
Q5480
1 C5401 NTUD3169CZ
SOT-963
0.1UF N-CHANNEL
D
3
D V+
20%
2 10V
CERM
402
Enables PBUS VSense
6 PBUSVSENS_EN_L
=PPVIN_S5_HS_COMPUTING_ISNS
PLACE_NEAR=U5400.4:10MM divider when in S0. D
8 OUT
U5400 R5409 R5482 1
CRITICAL
0612 2 4 INA214 4.53K2 100K
MF 78 ISNS_HS_COMPUTING_N
5 IN- SC70 OUT 6 HS_COMPUTING_IOUT 1 SMC_CPU_HI_ISENSE OUT 40 66 IN =PBUSVSENS_EN 2 G 1%
1W S 1/16W
1% CRITICAL 1%
1/20W
MF-LF
0.003 402 2
R5400 1 78 ISNS_HS_COMPUTING_P
4 IN+ REF 1 MF
201
1 C5409 1
3 0.22UF 3 PBUS_S0_VSENSE
20%
PLACE_NEAR=U5400.5:10MM GND PLACE_NEAR=U4900.B5:5MM 6.3V
2 X5R
8 IN =PPVIN_S5_HS_COMPUTING_ISNS_R 0201
D
R54881
2
PLACE_NEAR=U4900.B5:5MM 27.4K
PBUS_S0_VSENSE_IN 5 G 1%
S 1/16W
MF-LF
GND_SMC_AVSS 39 40 43 44 80 402 2 Rthevenin = 4573 Ohms
4
P-CHANNEL SMC_PBUS_VSENSE 40
OUT
OTHER High Side Current Sense (IO0R) R54811 1 PLACE_NEAR=U4900.A3:5MM

100K R5489
Gain: 100x, EDP: 8.8 A 1%
1/16W 5.49K
1 C5489
Rsense: 0.003 (R5410) XW5480 MF-LF 1% 0.22UF
SM 402 2 1/16W 20%
MF-LF 6.3V
2 X5R
V across Rsense: 26.4 mV 8 =PPBUS_S0_VSENSE 1 2 402 2 0201
SMC ADC: 09 8 =PP3V3_S0_HS_OTHER_ISNS PLACE_NEAR=R5400.1:10 MM
PBUSVSENS_EN_L_DIV GND_SMC_AVSS 39 40 43 44 80
1 C5411 PLACE_NEAR=U4900.A3:5MM
0.1UF
3
20%
V+ 2 10V
CERM
=PPVIN_S5_HS_OTHER_ISNS PLACE_NEAR=U5410.4:10MM 402
8 OUT
U5410 R5419
0612 2 4 78 ISNS_HS_OTHER_N
CRITICAL INA214 4.53K2
MF HS_OTHER_IOUT SMC_OTHER_HI_ISENSE
1W 5 IN- SC70 OUT 6 1 OUT 40
C 1%
0.003
R5410 1 78 ISNS_HS_OTHER_P 4 IN+ REF 1
1%
1/20W
MF 1 C5419
C
3 201 0.22UF
PLACE_NEAR=U5410.5:10MM 20%
GND PLACE_NEAR=U4900.A5:5MM 6.3V
2 X5R
8 IN =PPVIN_S5_HS_OTHER_ISNS_R 0201
2
CRITICAL
GND_SMC_AVSS 39 40 43 44 80
DC In Voltage Sense & Enable (VD0R)

Gain: 0.167x
SMC ADC: 03
Charger (BMON Production) Current Sense (IPBR) CRITICAL
Charger Gain: 36x, EDP: 6.6 A
Rsense: 0.010 (R7050) Enables DC-In VSense Q5490
SMC ADC: 07 divider when AC present. NTUD3169CZ
SOT-963
R5493 N-CHANNEL 6 DCINVSENS_EN_L
=CHGR_ACOK 1
0 2 NOSTUFF
PLACE_NEAR=U4900.A4:5MM 57 40 IN D
R5429
5%
1/20W R54921
MF 100K
300K 2 201 DCIN_VSENSE_EN 2 G 1%
57 IN CHGR_BMON 1 SMC_BMON_ISENSE OUT 40 S 1/16W
1% R5494 MF-LF
402 2
1/20W 0 1
MF PM_SUS_EN 1 2 PLACE_NEAR=U4900.F1:5MM
201 1 C5429 66 IN
5%
3 DCIN_S5_VSENSE
3300PF 1/20W
10% MF D
2 10V
X7R-CERM 201 R54981
B 0201
8 =PPDCIN_S5_VSENSE 5 G
27.4K
1%
B
PLACE_NEAR=U4900.A4:5MM S 1/16W
MF-LF
4 402 2 Rthevenin = 4573 Ohms
GND_SMC_AVSS 39 40 43 44 80
P-CHANNEL SMC_DCIN_VSENSE OUT 40
1
R5491 1 PLACE_NEAR=U4900.F1:5MM
100K R5499
1%
1/16W 5.49K
1 C5499
0.22UF
DC-In (AMON) Current Sense (ID0R) MF-LF
402 2
1%
1/16W
MF-LF
20%
6.3V
2 X5R
Charger Gain: 20x, EDP: 4.6 A 402 2 0201
Rsense: 0.020 (R7020) PDCINVSENS_EN_L_DIV GND_SMC_AVSS 39 40 43 44 80
SMC ADC: 04 PLACE_NEAR=U4900.F1:5MM
R5439
45.3K2
57 IN CHGR_AMON 1 SMC_DCIN_ISENSE OUT 40
1%
1/20W
MF
201 1 C5439
2200PF
10%
2 10V
X7R-CERM
0201
GND_SMC_AVSS
A 39 40 43 44 80
PAGE TITLE
Power Sensor: High Side

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
54 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Thermal Sensor A:
PCH Proximity, Left Fin Pipe, Right Fin Stack
I2C Write: 0x98, I2C Read: 0x99
R5550
47
8 =PP3V3_S0_GPUTHMSNS 1 2 PP3V3_S0_GPUTHMSNS_R
5% MIN_NECK_WIDTH=0.2 mm
1/16W VOLTAGE=3.3V 1 C5550
D
MF-LF
402 0.1uF
20%
10V R55511 1
R5552
D
2 CERM
78 GPU_TDIODE_P 402 10K 10K
Thermal Diode: None PLACE_NEAR=U5550.2:5mm 1 5%
1/16W
5%
1/16W
VDD MF-LF MF-LF
Placement Note: 402 2 2 402
None.
C5551 1 U5550
0.0022uF EMC1414-A-AIA
NO_XNET_CONNECTION=TRUE 10%
50V DFN
CERM 2 2 DP1 THERM*/ADDR 7 GPUTHMSNS_THM_L
402
78 GPU_TDIODE_N PLACE_NEAR=U5550.3:5mm 3 DN1 ALERT* 8 GPUTHMSNS_ALERT_L
78 GPUTHMSNS_D_P 4 DP2/DN3 SMDATA 9 =SMBUS_GPUTHMSNS_SDA 42
BI
PLACE_NEAR=U5550.4:5mm
5 DN2/DP3 10 =SMBUS_GPUTHMSNS_SCL
Q5501 3 SMCLK BI 42
BC846BLP
DFN1006H4-3
2
CRITICAL Q5503 1 C5552 1 GND THRM_PAD
0.0022uF 6 11
1 BC846BLP NO_XNET_CONNECTION=TRUE 10%
50V
DFN1006H4-3 CERM 2
2 CRITICAL 402 Thermal Sensor: PCH Proximity (TP0P)
3 GPUTHMSNS_D_N PLACE_NEAR=U5550.5:5mm
78 Placement Note:
Place U5550 on top side on top
Thermal Diode: Left Fin Stack (Th1H) Thermal Diode: Right Heat Pipe (Th2H) of PCH.
Placement Note: Placement Note:
Place Q5501 on the top side on the corner Place Q5503 under the top side on the corner
close to the Left Fin Stack. close to the Right Fin Stack.
C C
Thermal Sensor B:
CPU Proximity, Memory Proximity, Airflow
I2C Write: 0x98, I2C Read: 0x99
R5570
=PP3V3_S0_CPUTHMSNS 1
47 2 PP3V3_S0_CPUTHMSNS_R
8
5% MIN_NECK_WIDTH=0.2 mm
1/16W
MF-LF
VOLTAGE=3.3V 1 C5570
402 0.1uF
20%
2 10V
CERM
R55711 1
R5572
78 DDR3THMSNS_D1_P 402 10K 10K
Thermal Diode: Memory Proximity (TM0P) PLACE_NEAR=U5570.2:5mm 1 5%
1/16W
5%
1/16W
3 VDD MF-LF MF-LF
Placement Note: 402 2 2 402
Place Q5506 on the bottom side, below the Q5506 1 C5571 1 U5570
0.0022uF EMC1414-A-AIA
row of Memory device, between 2nd/3rd device. BC846BLP NO_XNET_CONNECTION=TRUE 10%
50V DFN
DFN1006H4-3 CERM 2 2 DP1 7
2 CRITICAL 402 THERM*/ADDR CPUTHMSNS_THM_L
78 DDR3THMSNS_D1_N PLACE_NEAR=U5570.3:5mm 3 DN1 ALERT* 8 CPUTHMSNS_ALERT_L
78 CPUTHMSNS_D2_P 4 DP2/DN3 SMDATA 9 =I2C_CPUTHMSNS_SDA 42
BI
Q5502 3
5 DN2/DP3 SMCLK 10 =I2C_CPUTHMSNS_SCL BI 42
BC846BLP 2
DFN1006H4-3 CRITICAL
Q5504 1 C5590 1 GND THRM_PAD
1 0.0022uF 6 11
BC846BLP NO_XNET_CONNECTION=TRUE 10%
50V
DFN1006H4-3 CERM 2
B 3
2 CRITICAL 402 Thermal Sensor: CPU Proximity (Tc0P) B
78 CPUTHMSNS_D2_N PLACE_NEAR=U5570.5:5mm
Placement Note:
Place U5570 on top side, on top of
Thermal Diode: Airflow (TA0P) Thermal Diode: Airflow (TA1P) the CPU.
Placement Note: Placement Note:
Place Q5502 on the bottom side, below left Place Q5504 on the either side,
underneath the left fan well in the neck. near LCD connector and DCIN connector.
Thermal Sensor: T29 Die

33 BI TP_TBT_THERM_DP 78 TBT_THERMD_P
MAKE_BASE=TRUE
1
R5520
10K
5%
1/16W
MF-LF
A 1 2 78 TBT_THERMD_N
2 402
NOSTUFF
PAGE TITLE
XW5520
SM PLACE_NEAR=U3600.B1:2mm
PLACE_SIDE=TOP
Thermal Sensors
DRAWING NUMBER SIZE
Note: Use GND pin B1 on U3600 for N leg. Apple Inc. <SCH_NUM> D
REVISION
R
<E4LABEL>
<BRANCH>
55 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C Left Fan Right Fan C

8 =PP5V_S0_FAN_LT 8 =PP5V_S0_FAN_RT
8 =PP3V3_S0_FAN_LT 8 =PP3V3_S0_FAN_RT
CRITICAL CRITICAL
R5650 1 J5650 R5660 1 J5660
47K FF14A-5C-R11DL-B-3H 47K FF14A-5C-R11DL-B-3H
5% F-RT-SM 5% F-RT-SM
1/16W 1/16W
MF-LF 6 MF-LF 6
NC NC
R5655 402 2
R5665 402 2
47K 1 47K 1
39 OUT SMC_FAN_0_TACH 1 2 7 FAN_LT_TACH 39 OUT SMC_FAN_1_TACH 1 2 7 FAN_RT_TACH
5% 2 5% 2
1/16W 1/16W
MF-LF 3 MF-LF 3
402 402
4 4
1 1
R5651 5 R5661 5
100K NC 100K NC
5% 5 5% 2
1/16W Q5660 7 1/16W Q5660 7
MF-LF MF-LF
402 2
G 2N7002DW-X-G NC 402 2
G 2N7002DW-X-G NC
SOT-363 SOT-363
39 SMC_FAN_0_CTL 4 S D 3 7 FAN_LT_PWM
518S0769 39 SMC_FAN_1_CTL 1 S D 6 7 FAN_RT_PWM
518S0769
IN IN
B B
PAGE TITLE
Fan Connectors
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
56 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
IPD Flex Connector
PSOC USB CONTROLLER J5700
FF14-18C-R11DL
F-RT-SM
20
Keyboard Connector
- USB INTERFACES TO MLB
- SPI HOST TO Z2 R5708 518S0848
0 32
- TRACKPAD PICK BUTTONS 47 8 =PP3V3_S4_TPAD 1 2 PP3V3_TPAD_CONN 1 47 8 =PP3V3_S4_TPAD
VOLTAGE=3.3V
- KEYBOARD SCANNER 5% NOSTUFF MIN_NECK_WIDTH=0.20MM 47 7 Z2_CLKIN 2 47 8 =PP3V42_G3H_TPAD
1/20W MIN_LINE_WIDTH=0.50MM
PLACE_SIDE=BOTTOM MF
201
1 C5708 42 =I2C_TPAD_SCL 3 30
0.1UF PP5V_S4_CUMULUS 4 29
47 8 =PP3V3_S4_TPAD R5704 BYPASS=U5701.49:50:11 mm
BYPASS=U5701.49:50:8 mm 10%
6.3V
7
VOLTAGE=5V 28
1.5 BYPASS=U5701.49:50:5 mm 2 X5R MIN_NECK_WIDTH=0.20MM 42 =I2C_TPAD_SDA 5 47 7 WS_KBD1
2 1 PP3V3_S3_PSOC 201 MIN_LINE_WIDTH=0.50MM 27
MIN_LINE_WIDTH=0.50MM 6 47 7 WS_KBD2
D
5%
1/16W
MF-LF
VOLTAGE=3.3V 1 C5704 1 C5705 1 C5706 TPAD_5V:S4
47 7 PSOC_SCLK 7 47 7 WS_KBD3 26
25
D
402 100PF 0.1UF 4.7UF 47 7 PSOC_MOSI 8 47 7 WS_KBD4
1 5% 10% 20% PLACE_NEAR=J5700.18:3MM 24
R5703 25V 47 7 Z2_SCLK 9 47 7 WS_KBD5
2 NP0-CERM 2 6.3V 6.3V
2 X5R
220K
5% 0201
X5R
201 402 L5700 47 7 PSOC_MISO 10 47 7 WS_KBD6 23
1/20W FERR-120-OHM-1.5A 47 7 Z2_MISO 11 47 7 WS_KBD7 22
MF 1 2 21
201 2 8 =PP5V_S4_TPAD 12 47 7 WS_KBD8
0402-LF 47 7 Z2_MOSI 13 47 7 WS_KBD9 20
40 OUT =PSOC_WAKE_L WS_KBD23 7 47 TPAD_5V:S4 19
47 7 PSOC_F_CS_L 14 47 7 WS_KBD10
47 7 PICKB_L WS_KBD22 7 47
BUTTON_DISABLE WS_KBD21
1 C5700 47 7 Z2_CS_L 15 CAPS:INT 47 7 WS_KBD11 18
47 7 47
0.1UF Z2_KEY_ACT_L 16 WS_KBD12 17
47 7 Z2_HOST_INTN WS_KBD20 7 47
10%
10V PLACE_NEAR=J5700.18:3MM
47 7
R5714 47 7
16
2 X5R-CERM 47 7 PICKB_L 17 113 47 7 WS_KBD13
47 WS_LEFT_SHIFT_KEY WS_KBD19 7 47 0201 47 WS_KBD15_C 1 2
15
47 7 Z2_HOST_INTN 18 47 7 WS_KBD14
47 WS_LEFT_OPTION_KEY WS_KBD18 7 47 1% 14
1/16W 47 7 WS_KBD15_CAP
R57001 19
MF-LF
402 7 WS_KBD16_NUM 13
56
55
54
53
52
51
50
49
48
47
46
45
44
43
TPAD_5V:S5 220K WS_KBD17 12
P2_5 PLACE_NEAR=J5700.18:3MM 5% R5715 47 7
P2_7
P0_1
P0_3
P0_5
P0_7
VSS
VDD
P0_6
P0_4
P0_2
P0_0
P2_6
P2_4
1/20W
L5707 MF
WS_KBD16N 1
0 2 47 7 WS_KBD18 11
FERR-120-OHM-1.5A 201 2 47
47 7 WS_KBD19 10
47 WS_CONTROL_KEY 1 P2_3 P2_2 42 WS_KBD17 7 47 5%
47 PP5V_S5RS4_CUMULUS 1 2 1/16W 47 7 WS_KBD20 9
47 7 Z2_KEY_ACT_L 2 P2_1 CRITICAL P2_0 41 WS_KBD16N 47 MF-LF
0402-LF 402 47 7 WS_KBD21 8
3 P4_7 OMIT P4_6 40 WS_KBD15_C 47 TPAD_5V:S5
NC WS_KBD22 7
66 IN TPAD_VBUS_EN 4 P4_5 U5701 P4_4 39 WS_KBD14 7 47
1 C5707 R5710
47 7
WS_KBD23 6
5 P4_3 P4_2 38 WS_KBD13 0.1UF 1K
47 7
NC CY8C24794 7 47
10% PLACE_NEAR=J5700.18:3MM 40 39 7 OUT SMC_ONOFF_L 1 2 7 WS_KBD_ONOFF_L 5
6 P4_1 MLF P4_0 37 WS_KBD12 7 47 2 10V
NC X5R-CERM
0201 47 8 =PP3V42_G3H_TPAD 5% 4
PSOC_MISO 7 P3_7 (SYM-VER2) P3_6 36 WS_KBD11 1/16W
47 7
PSOC_F_CS_L 8 P3_5 P3_4 35 WS_KBD10

7 47
C5710 1 MF-LF
402
47 7 WS_LEFT_SHIFT_KBD 3
47 7
337S2983 7 47
0.1UF WS_LEFT_OPTION_KBD 2
47 7 PSOC_MOSI 9 P3_3 P3_2 34 WS_KBD9 7 47
1 C5750 20%
10V
47 7
WS_CONTROL_KBD 1
PSOC_SCLK 10 33 WS_KBD8 0.1UF CERM 2 47 7
47 7 P3_1 P3_0 7 47
10% 402
C C
10
47 7 Z2_MISO 11 P5_7 P5_6 32 WS_KBD7 7 47
16V
2 X7R-CERM PLACEMENT_NOTE=NEAR J5713
31
47 7 Z2_CS_L 12
13
P5_5 P5_4 31
30
WS_KBD1 7 47 www.qdzbwx.com VDD
0402
47 7 Z2_MOSI P5_3 P5_2 WS_KBD2 7 47
47 7 Z2_SCLK 14 P5_1 P5_0 29 WS_KBD3 7 47

U5750 F-RT-SM
23 P7_7
24 P7_0
25 P1_0
26 P1_2
27 P1_4
28 P1_6
15 P1_7
16 P1_5
17 P1_3
18 P1_1
SLG4AP021 FF14A-30C-R11DL-B-3H
19 VSS
22 VDD
THRML TQFN
20 D+
21 D-
PAD 57
47 8 =PP3V3_S4_TPAD 4 OE J5713
(IPD) CRITICAL
47 7 WS_LEFT_SHIFT_KBD 1 IN_1
OUT_1 9 WS_LEFT_SHIFT_KEY 47 518S0752
TP_PSOC_SCL WS_KBD4 (IPD)
TP_PSOC_SDA WS_KBD5
7 47
7 47 47 7 WS_LEFT_OPTION_KBD 2 IN_2
OUT_2 8 WS_LEFT_OPTION_KEY 47 SMC Manual Reset & Isolation
(IPD)
TP_PSOC_P1_3 WS_KBD6 7 47 OUT_3 7 WS_CONTROL_KEY 47 Left shift, option & control keys combined with power button cause SMC RESET# assertion.
47 7 WS_CONTROL_KBD 3 IN_3
TP_ISSP_SCLK_P1_1 TP_ISSP_SDATA_P1_0 (IPD) Keys ANDed with MSP power to isolate when MSP is not powered.
Pull-up in U5010.
ISSP SCLK/I2C SCL ISSP SDATA/I2C SDA OUT_ALL# 6 SMC_TPAD_RST_L No IPD on OE input pin PP3V3_S4 (symbol error).
OUT 40
R5701 Z2_CLKIN 7 47
24 78
74 9 USB_TPAD_P 1 2 26 USB_TPAD_R_P TP_P7_7 THRM CAPS:EXT CAPS:EXT CAPS:EXT
GND PAD
5% R57401 R57381 R57361
11
1/20W (PP3V3_S3_PSOC) 10K 10K 10K
MF
201
1 CAPS:EXT
5% 5% 5%
R5702 1 C5702 1 C5703 1 C5701 1/20W
MF
1/20W
MF
1/20W
MF S Q5736
100PF 0.1UF 4.7UF 201 2 201 2 201 2 NTZD3152P
24 78 5% 10% 20% 2 SOT-563-HF
74 9 USB_TPAD_N 1 2 26 USB_TPAD_R_N 25V
2 NP0-CERM 2 6.3V
X5R 2 6.3V
X5R G
5% 0201 201 402
1/20W 47 8 =PP3V3_S4_TPAD
MF
201
BYPASS=U5701.22:19:5 mm CAPS:EXT CAPS:EXT CAPS:EXT D
BYPASS=U5701.22:19:8 mm 1 1 1
BYPASS=U5701.22:19:11 mm R5730 R5732 R5734 CAPS:EXT8
6
10K 10K 20K CAP_SOURCE
5% 5% 5% V+ CAPS:EXT MIN_LINE_WIDTH=0.2MM
1/20W 1/20W 1/20W MIN_NECK_WIDTH=0.1MM
B IC PIN NAME CURRENT R_SNS V_SNS POWER
TPAD Buttons Disable
MF
2 201
MF
2 201
MF
2 201
U5730
LM393ADGKR
R5737
113
1
B
47 BUTTON_DISABLE 6 MSOP 1%
CAP_VREF_L 7 1/20W
TMP102 V+ 10UA 2.55 KOHM 0.0255 V 0.255E-6 W PLACE THESE COMPONENTS CLOSE TO J5800
WS_KBD15_C 5 MF
47 201 2
80UA 0.204 V 16.32E-6 W D 6 THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB
Q5701 CAPS:EXT
WS_KBD15_CAP
7 47
3V3 LDO VDD 60MA (MAX) 10 OHM 0.6 V 36E-3 W SSM6N37FEAPE 2

1 MIN_NECK_WIDTH=0.1MM
VOUT 60MA (MAX) 0.2 OHM 0.012 V 0.72E-3 W
SOT563
CAP_VREF_H 3 CAP_COMP_H R57391
113
THE TPAD BUTTONS WILL BE DISABLE CAPS:EXT CAPS:EXT CAPS:EXT 1%
PSOC VDD 8MA (TYP) 1.5 OHM 0.012 V 96E-6 W 1 1 1 GND 1/20W
14MA (MAX) 0.021 V 294E-6 W
2 G S 1 WHEN THE LID IS CLOSED R5731 R5733 R5735 4
MF
201 2
LID OPEN => SMC_LID_LC ~ 3.42V 10K 20K 10K
40 39 IN SMC_LID 5% 5% 5% CAP_SINK
18V BOOSTER VIN 4MA (MAX) 4.7 OHM 0.0188 V 75.2E-6 W LID CLOSE => SMC_LID_LC < 0.50V 1/20W 1/20W 1/20W MIN_LINE_WIDTH=0.2MM
MF MF MF MIN_NECK_WIDTH=0.1MM
2 201 2 201 2 201 3
D CAPS:EXT
BOM Options available to CSA 5 TPAD_5V_FET:NO CAPS:EXT Q5738
TPAD_5V:S4 Original implementation off PP5V_S4 CAP_COMP_L_INV 1 G DMN3730UFB4
TPAD_5V:LDO_S4 PP5V_S5 LDO power in S4 only R5720 5V TPAD FET
Caps Lock LED Drive CRITICAL S DFN1006H4-3
0 Q5734 SYM_VER_1
TPAD_5V:LDO_S5 PP5V_S5 LDO power 1 2
5%
SSM3K15AMFVAPE D 3
MOSFET SiA413
VESM 2
All RC values are TBD 1/16W
MF-LF
402 CHANNEL P-TYPE 12V
WS_KBD15_C CAP_COMP_H CAP_COMP_L Q5736 Q5738 LED Current
Z 1 1 off off none

5V TRACKPAD S4 FET TPAD_5V_FET:YES
CRITICAL
RDS(ON) 29 mOhm @4.5V
1 0 1 on off source
Q5720 1 G S 2
LOADING 16 mA (EDP) 0 1 0 off on sink CAP_COMP_L
SIA413DJ
SC70-6L
8 =PP5V_S5_TPAD
7
PP5V_S5RS4_CUMULUS
4
A TPAD_5V_FET:YES
Q5721 TPAD_5V_FET:YES
TPAD_5V_FET:YES
C5722 1
VOLTAGE=5V
47
SYNC_MASTER=D2_MLB_KEPLER SYNC_DATE=12/08/2011 A
1 PAGE TITLE
SSM3K15FV D 3 R5721 0.033UF
G
SOD-VESM-HF 220K 10%

16V
KEYBOARD/TRACKPAD (1 OF 2)
5% X5R
2
1/20W TPAD_5V_FET:YES DRAWING NUMBER SIZE
3
402
MF TPAD_5V_FET:YES
201 2 C5723 Apple Inc. <SCH_NUM> D
R5722 0.01UF TABLE_BOMGROUP_HEAD
REVISION
1 G S 3.3K 2 BOM GROUP BOM OPTIONS R
2 P5VCUMULUS_EN_L 1 P5VCUMULUS_SS 1 2
TABLE_BOMGROUP_ITEM
<E4LABEL>
66 59 IN =P5VS4_EN 5%
10% TPAD_5V_LDO:S4 TPAD_5V_FET:YES,TPAD_5V:S5 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1/20W
MF 10V TABLE_BOMGROUP_ITEM

201 X5R TPAD_5V_LDO:S5 TPAD_5V_FET:NO,TPAD_5V:S5 PROPRIETARY PROPERTY OF APPLE INC.
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 =PP3V3_S0_TPAD
1
R5858
470K
5%
1/16W
MF-LF
2 402
48 39 OUT SMC_SYS_KBDLED CRITICAL
D 1
R5859
J5815
AA07A-S010-VA1
D
4.7K F-ST-SM
5% 12
1/16W 11
MF-LF
2 402
48 7 KBDLED_CATHODE2 2 1 KBDLED_CATHODE1 7 48
48 7 PP_KBD_BOOST_VOUT 4 3 PP_KBD_BOOST_VOUT 7 48
7 SMC_KBDLED_PRESENT_L 6 5 J5815 PIN 5 IS GROUNDED ON KEYBOARD BACKLIGHT FLEX

8 7
10 9
13
14
Keyboard Backlight Driver & Detection
To detect Keyboard backlight, SMC will
tristate and read SMC_SYS_KBDLED: 516S0899

If LOW, keyboard backlight present Keyboard Backlight Connector
If HIGH, keyboard backlight not present
C PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION C

138S0811 2 CAP,CER,4.7UF,10%,25V,X6S,0603 C5810,C5811 CRITICAL
152S1701 COMBO 371S0490

CRITICAL
CRITICAL
XW5810 L5850 D5850
SM
10UH-20%-1.4A-0.17OHM SOD-323
8 =PP5V_S0_KBDLED 1 2 PPVIN_S0_KBDLED_L 1 2 KBDLED_SW1 A K PP_KBD_BOOST_VOUT 7 48
MIN_LINE_WIDTH=0.5 MM PST041H-CDH46D14-SM MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM 1 MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V 1 C5812 R5810 SWITCH_NODE=TRUE PMEG4010BEA 1 C5860 1 C5861 1 C5862 1 C5863 1 C5864 VOLTAGE=30V
0.1UF 0 2 1.0UF 1.0UF 1.0UF 1.0UF 220PF
5%
C5810 1 1 C5811 10%
25V
2 X5R
1/16W
MF-LF
XW5850 10%
50V
2 X5R
10%
50V
2 X5R
10%
50V
2 X5R
10%
50V
2 X5R
10%
50V
2 X7R-CERM
4.7UF 4.7UF SM
10% 10% 402 2 402 0603 0603 0603 0603 0402
35V 35V
X5R-CERM 2 2 X5R-CERM 1
0603 0603
PP_KBDBOOST_XW
1 NOSTUFF MIN_NECK_WIDTH=0.2 MM
R5870 1 C5870 VOLTAGE=30V
PPVIN_S0_KBDLED_C 237K 33PF
MIN_LINE_WIDTH=0.5 MM 1% 5%
MIN_NECK_WIDTH=0.25 MM 1/16W
VOLTAGE=5V 1 C5850 1 C5851 MF-LF
50V
2 CERM
1UF 0.01UF 2 402 402
10% 10% PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
R5802
B 1
0 2
25V
2 X5R
603-1
16V
2 X7R-CERM
0402
116S0004 2 RES,MTL FILM,1/16W,0,5,0402,SMD,LF R5852,R5853 CRITICAL KBDBKLT:PROD
B
48 GND_KBDLED_AGND
5%
PVDC_KBDLED 1 NOSTUFF
1/16W
MF-LF R5871 1 C5871
402 10K 33PF
C5852
11
1 1%
7
1/16W 5%
1UF MF-LF 2 50V
10% CERM
25V VDC VIN 2 402 402
2 X5R
R58501 603-1
GND_KBDLED_AGND 48
48 GND_KBDLED_AGND U5850
100K
5% TQFN
ISL97682
1/16W 6 EN
MF-LF KBDLED_EN LX 9
402 2
SMC_SYS_KBDLED_FILTER 5 PWMI OVP 12 KBDLED_OVP
KBDLED_RSET 3 RSET KBDBKLT:ENG
R5851
0 8 FPW/DIRECTPWM R5852
48 39 SMC_SYS_KBDLED 1 2 KBDLED_FPW
10.2 2
5%
4 FSW CH1 13 KBDLED_CATHODE1_R 1 KBDLED_CATHODE1 7 48
1/16W KBDLED_FSW MIN_LINE_WIDTH=0.3 MM MIN_LINE_WIDTH=0.3 MM
MF-LF MIN_NECK_WIDTH=0.2 MM 0.1% KBDBKLT:ENG MIN_NECK_WIDTH=0.2 MM
402
2 COMP CH2 15 VOLTAGE=35V 1/16W
R5853 VOLTAGE=35V
KBDLED_COMP TF
I_LED= 804/RSET 14
402 10.2 2
CRITICAL NC KBDLED_CATHODE2_R 1 KBDLED_CATHODE2 7 48
MIN_LINE_WIDTH=0.3 MM MIN_LINE_WIDTH=0.3 MM
NOSTUFF 1 1
1 C5853 1
R5854 NOSTUFF
NC 16
NC MIN_NECK_WIDTH=0.2 MM 0.1% MIN_NECK_WIDTH=0.2 MM
R5855 R5856 VOLTAGE=35V 1/16W VOLTAGE=35V
1 AGND
10 PGND
1 C5854 33PF 10K TF

33PF 40.2K 137K 5%
50V 5% 1
R5857 THRM 402
1% 1% 2 CERM 1/16W PAD
5% 1/16W 1/16W MF-LF 100K
50V 402
17
2 CERM MF-LF MF-LF 2 402 5%

402 2 402 2 402 KBDLEDCOMP_RC 1/16W
MF-LF
2 402
FSW =1 MHZ 1 C5855
SEE SPEC FOR OTHERS 0.0082UF
10%
A 25V
2 X7R
402
XW5800
SM SYNC_MASTER=D2_MLB_KEPLER SYNC_DATE=12/08/2011 A
48 GND_KBDLED_AGND 1 2 PAGE TITLE
MIN_NECK_WIDTH=0.2 MM KEYBOARD/TRACKPAD (2 OF 2)
VOLTAGE=0V
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
58 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 =PP3V3_S3_SMS
BYPASS=U5920.14:13:8 mm
D SMS SMS
PLACE_SIDE=TOP
D
14
C5926 1 1
C5922 SMS SMS NOSTUFF
1
10UF 0.1UF 1 1
20% 10% VDD VDD_IO R5920 R5925
6.3V 6.3V
X5R 2 2 X5R NC 2 10K 10K
603 201 SMS NC U5920 5% 5%
3 1/20W 1/20W SMS
BYPASS=U5920.14:13:8 mm 1 NC
R5924 LIS331DLH MF MF
10K LGA
201
2
201
2 R5923
5% 10 CS 8 SMS_I2C_SEL 0
1/20W RESERVED 1 2 =I2C_SMC_SMS_SDA BI 42
MF 15
201 CRITICAL 5%
2
SDO 7 SMS_ADDR_SELECT 1/20W
MF
40 39 OUT SMS_INT_L 11 INT1 SDA/SDI/SDO 6 I2C_SMC_SMS_SDA_R 201
7 TP_SMS_INT2 9 INT2 SCL/SPC 4 I2C_SMC_SMS_SCL_R SMS

GND SMS R5922
1 0
R5921
12
13
16
1 2 =I2C_SMC_SMS_SCL IN 42
10K
338S0687 5% 5%
1/20W
1/20W
MF MF
PLACEMENT_NOTE=See schematic for orientation. 201
2
201
SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd)

Desired orientation when placed on top-side (view top): SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)
NOTE: SDA and SCL have internal pull-ups to VDD_IO.

+Y
+X
Front of system
+Z (up)
C C
Circle indicates pin 1 location when placed
in correct orientation
8 =PP3V3_S3_GYRO
GYRO GYRO GYRO

1 C5940 1 C5941 1 C5943
GYRO
0.1UF
10%
6.3V
2 X5R
201
10%
6.3V
2 X5R
201
0.1UF 10UF
20%
6.3V
2 CERM-X5R
0402-1
GYRO
1 (WRITE: 0XD0 READ: 0XD1)
R5944
10K
GYRO
15
VDD 16
5%
1
1/20W
MF GYRO
2 201 RES/VDD VDD_IO
R5946
CS PU = I2C U5940 338S0927 = 8KHZ 1
0
2 =I2C_SMC_GYRO_SCL IN 42
INT ARE PUSH-PULL

AP3GDL8B 5%
LGA 1/20W
MF
GYRO_CS 5 CS SCL_SPC 2 I2C_SMC_GYRO_SCL_R 201
6 SDA_SDI_SDO 3
B TP_IRQ_GYRO_INT2_L
TP_GYRO_SYNC 8
DRDY/
INT2
DEN SDO_SA0 4
I2C_SMC_GYRO_SDA_R GYRO
R5947
B
CRITICAL 0
7 INT1 9 1 2 =I2C_SMC_GYRO_SDA BI 42
TP_IRQ_GYRO_INT1_L RES0
5%
14 PLLFILT RES1 10 1/20W
MF
RES2 11 201
RES3 12
GND
13
PLLFILT_GYRO
GYRO
1 C5942
0.47UF
10%
2 6.3V
CERM-X5R
402 GYRO
PLLFILT_GYRO1 GYRO 1 C5945
1 0.01UF
R5945 10%
10V
10K 2 X5R
5% 201
1/20W
MF
2 201
PAGE TITLE
DIGITAL ACCELEROMETER & GYRO

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
59 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
DUAL I/O MODE (MODE 0 & 3) SUPPORTED
High Speed CLK Frequency - 50MHz for fast read dual I/O
8 =PP3V3_SUS_ROM
8
R6101 C6100 1 CRITICAL
3.3K 0.1UF VDD
5%
1/20W
10%
16V U6100
MF X5R-CERM 2 64MBIT
2 201 0201
WSON
41 40 IN SPI_MLB_CLK 6 SCK SI/SIO0 5 SPI_MLB_MOSI IN 40 41
SST25VF064C
OMIT_TABLE
41 40 IN SPI_MLB_CS_L 1 CE*
SO/SOI1 2 SPI_MLB_MISO OUT 40 41
SPI_WP_L 3 WP*
41 20 7 IN SPIROM_USE_MLB 7 RST*/HOLD*
NOTE: If HOLD* is asserted VSS THRM_PAD
9
ROM will ignore SPI cycles.
B B
PAGE TITLE
SPI ROM
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
61 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
www.qdzbwx.com
AUDIO CODEC
APPLE P/N 353S2355
L6201 U6201 CONSUMES 40MA MAX. FROM 1.5V RAIL
FERR-22-OHM-1A-0.065-OHM PP5V_AUDIO_HPAMP 51
=PP1V5_S0_AUDIO 1 2 PP1V5_S0_AUDIO_DIG
8 IN
0201 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
C6210 1 1
C6211
D 4.7UF
20%
4V
0.1UF
10%
6.3V
PP4V5_AUDIO_ANALOG IN 51 54 55
D
X5R-1 2 2 X5R
402 201 CRITICAL CRITICAL
1
C6214 1 1 C6213
C6219 0.1UF 10UF
10UF C6218 1 1 10% 20%
20%
C6217 16V 10V
GND_AUDIO_CODEC 16V 0.1UF 10UF X5R-CERM 2 2 X5R-CERM
55 54 52 51 2 0201 0402-1
TANT-POLY 10% 20%
24
46
25
16V
CRITICAL CRITICAL 0805-LLP-1 2 2 16V
9
=PP3V3_S0_AUDIO PP4V5_AUDIO_ANALOG X7R-CERM TANT-POLY GND_AUDIO_CODEC
55 8 55 54 51 IN
C6221 1 1 C6220 MIN_LINE_WIDTH=0.20MM VD VA_REF VA_HP VA
0402 0805-LLP-1
GND_AUDIO_CODEC
51 52 54 55
15UF 15UF MIN_NECK_WIDTH=0.15MM

51 52 54 55
1 20% 20% VBIAS_DAC 29 VBIAS_DAC
R6250 1 4V 4V
10K R6210 X5R 2 2 X5R MIN_LINE_WIDTH=0.20MM
38 AUD_HP_PORT_L
R6252 1 0402 0402 MIN_NECK_WIDTH=0.15MM HPOUT_L MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM OUT 52 54
5% R6251 2.67K CS4206_FP 44 VHP_FILT+
0 HPOUT_R 40 AUD_HP_PORT_R
55 7 IN
SPKRCONN_L_ID1 2
1/16W
MF-LF
402
10K
5%
1%
1/20W
MF
CS4206_FN
41 VHP_FILT- U6201 MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM OUT 52 54
MERRY = LOW 5% 2
1/16W
2
201 MIN_NECK_WIDTH=0.15MM CS4206B HPREF 39 MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM AUD_HP_PORT_REF IN 54
1/16W MF-LF QFN
FG = HIGH MF-LF
2 402
402 55 7 IN AUD_DMIC_SDA1 2 GPIO0/DMIC_SDA1 LINEOUT_L1+ 35 AUD_LO1_L_P OUT 53 78
R6253 SPKRCONN_L_ID_R 12 GPIO1/DMIC_SDA2 LINEOUT_L1- 34 AUD_LO1_L_N OUT 53 78 LFT SUBWOOFER AMP. SIG. SOURCE
0 /SPDIF_OUT2
55 7 SPKRCONN_R_ID 1 2 SPKRCONN_R_ID_R 14 GPIO2 LINEOUT_R1+ 36 AUD_LO1_R_P 53 78
IN OUT
RT. SUBWOOFER AMP. SIG. SOURCE
5%
1/16W
53 OUT AUD_GPIO_3 15 GPIO3 LINEOUT_R1- 37 AUD_LO1_R_N OUT 53 78
MF-LF
402 55 IN AUD_SENSE_A 13 SENSE_A LINEOUT_L2+ 31 AUD_LO2_L_P OUT 53 78
MIN_LINE_WIDTH=0.20MM LFT. SPKR AMP. SIG. SOURCE
MIN_NECK_WIDTH=0.15MM CS4206_FLYP LINEOUT_L2- 30 AUD_LO2_L_N OUT 53 78
GPIO3 = SPKR AMP SHDN CONTROL MIN_LINE_WIDTH=0.20MM
54 51 8 IN =PP3V3_S0_AUDIO_DIG MIN_NECK_WIDTH=0.15MM CS4206_FLYC LINEOUT_R2+ 32 AUD_LO2_R_P OUT 53 78
45 FLYP RT. SPKR AMP. SIG. SOURCE
CRITICAL CRITICAL LINEOUT_R2- 33 AUD_LO2_R_N OUT 53 78
C6222 1 1
C6223 43 FLYC
C6216 1 1 C6226 15UF 15UF 42 FLYN
20% 20%
1UF 0.1UF 4V
2 2
4V
MICBIAS 16 TP_AUD_CODEC_MICBIAS 7
10% 10% X5R X5R
10V 6.3V 0402 0402 MIN_LINE_WIDTH=0.20MM
2 2 MIN_NECK_WIDTH=0.15MM
X5R
402-1
X5R
201 CS4206_FLYN
3 VL_HD CRITICAL MIN_LINE_WIDTH=0.20MM
C MIN_LINE_WIDTH=0.20MM
1 VL_IF
VCOM 28 CS4206_VCOM
C
LINEIN_L+ 21 NO_TEST=TRUE NC_AUD_LI_P_L NC
75 17 IN HDA_BIT_CLK 6 BITCLK
LINEIN_C- 22 NO_TEST=TRUE NC_AUD_LI_REF NC
75 17 IN HDA_SYNC LINEIN_R+ 23 NO_TEST=TRUE NC_AUD_LI_P_R NC
R6211 10 SYNC
22
75 17 IN HDA_SDIN0 1 2 75 AUD_SDI_R 8 SDI MICIN_L+ 18 AUD_MIC_INL_P IN 54 78
EXT MIC CODEC INPUT
5% 5 SDO MICIN_L- 17 AUD_MIC_INL_N IN 54 78
1/16W
MF-LF MICIN_R+ 19
402 11 RESET*
75 17 OUT HDA_SDOUT MICIN_R- 20
75 17 IN HDA_RST_L TP_AUD_MIC_INRP 7
7 AUD_SPDIF_IN 47 SPDIF_IN
VREF+_ADC 27 CS4206_VREF_ADC NC
AUD_SPDIF_OUT 48 SPDIF_OUT MIN_LINE_WIDTH=0.20MM TP_AUD_MIC_INRN 7
DMIC_SCL 4 AUD_DMIC_CLK_R R6241

1 0
R6254 1 2 AUD_DMIC_CLK 55
OUT
0
5% 5%
1/20W DGND THRM_PAD AGND 1/20W
MF MF
201 201
49
26
2
1 1
C6224 C6225
1UF 10UF
20% 20%
16V 2 2 16V
TANT TANT-POLY
0603-SM 0805-LLP-1
R6220
B 54 7 OUT AUD_SPDIF_OUT_JACK 1
33 2
B
5% 55 54 52 51 GND_AUDIO_CODEC MIN_NECK_WIDTH=0.15MM
1/16W VOLTAGE=0V
MF-LF
402
4.5V POWER SUPPLY FOR CODEC NOTES ON CODEC I/O

DIFF FSINPUT= 2.45VRMS
APPLE P/N 353S2456 SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
L6202 MIN_LINE_WIDTH=0.20MM
FERR-22-OHM-1A-0.065-OHM MIN_NECK_WIDTH=0.15MM DAC2/3 FSOUTPUTSE= 1.34VRMS
VOLTAGE=5V
D1: PLACE XW6201 NEAR 5V SOURCE 1 2 PP5V_AUDIO_HPAMP 51
0201
L6200 MIN_LINE_WIDTH=0.20MM MIN_LINE_WIDTH=0.20MM

XW6201 FERR-22-OHM-1A-0.065-OHM MIN_NECK_WIDTH=0.15MM U6200 MIN_NECK_WIDTH=0.15MM
SM VOLTAGE=5V VOLTAGE=4.5V
TPS71745
=PP5V_S0_AUDIO 1 2 PP5V_S0_AUDIO_XW 1 2 4V5_REG_IN 6 SON 1 PP4V5_AUDIO_ANALOG
8 IN IN OUT OUT 51 54 55
MIN_NECK_WIDTH=0.20MM 0201 CRITICAL
VOLTAGE=5V R6200 4V5_REG_EN 4 EN NR/FB 3 4V5_NR
2.2K
54 51 8 IN =PP3V3_S0_AUDIO_DIG 1 2
A 5%
1/20W
MF 1
C6200
GND
2
NC 5
CRITICAL
C6202 1 1
CRITICAL
C6203 SYNC_MASTER=D1_AUDIO SYNC_DATE=06/06/2012 A
201 PAGE TITLE
1UF XW6200 0.1UF 1.0UF
2
10%
10V
X5R
1
C6201
1UF
10%
SM
10%
16V
X5R-CERM 2
20%
10V
2 X5R-CERM
AUDIO: CODEC/REGULATOR
402
2
10V 0201 0201-1
X5R
402
GND_AUDIO_CODEC 51 52 54 55 REVISION
R
<E4LABEL>
PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5 NOTICE OF PROPRIETARY PROPERTY: BRANCH
<BRANCH>
62 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER
54 51 IN AUD_HP_PORT_L OUT
CRITICAL
C6300 1
B 0.1UF
10%
6.3V 1
B
X5R 2
201
R6302
10K
NC AUD_HP_ZOBEL_L 1%
1/20W
MF
R63001 2 201
39
5%
1/20W
MF
201 2
55 54 51 IN GND_AUDIO_CODEC
R63101
39
5%
1/20W 1
MF
201 2 R6312
10K
1%
NC AUD_HP_ZOBEL_R 1/20W
MIN_LINE_WIDTH=0.30MM MF
CRITICAL 2 201
C6310 1
0.1UF
10%
6.3V 2
X5R
201
54 51 IN AUD_HP_PORT_R OUT
A SYNC_MASTER=D1_AUDIO SYNC_DATE=06/06/2012 A
PAGE TITLE
AUDIO: HEADPHONE FILTER

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
63 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
53 9 PP5V_S0_AUDIO_AMP_L
CRITICAL
1
C6612
CRITICAL CRITICAL
47UF
L6610 C6613
20%
PLACE_NEAR=U6610.A1:5.1MM
6.3V 2
FERR-1000-OHM 1
0.01UF TANT-POLY C6611
NO_TEST=TRUE CASE-A4
1 2 1 2 0.1UF
78 51 IN AUD_LO2_L_N 78 AUD_SPKRAMP_LIN_P
A1
10%
0402 16V
CRITICAL 10%
2
X7R-CERM
L6611 50V
PVDD 0402
4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375) C6614 X7R-CERM

FERR-1000-OHM
0.01UF 0402
U6610
APN: 353S2888 & 353S2958 1 2
NO_TEST=TRUE 1 2 MAX98300
78 51 AUD_LO2_L_P 78 AUD_SPKRAMP_LIN_N SPKRCONN_L_OUT_N 7 55 78
D GAIN = +3 DB
1ST ORDER FC (L&R) = NOM 569 HZ
IN
CRITICAL
0402
10%
50V
78
NO_TEST=TRUE
SPKRAMP_LIN_P
A3
B3
IN+
WLP
OUT+ B1
C1
CKPLUS_WAIVE=ndifpr_badterm
CKPLUS_WAIVE=pdifpr_badterm
OUT
D
X7R-CERM
78 SPKRAMP_LIN_N IN- OUT-
1ST ORDER FC (SUB) = NOM 9 HZ NO_TEST=TRUE
0402
C2 C3
53 AUD_SPKRAMP_SHUTDOWN_L SHDN* GAIN SPKR_L_GAIN
SPKRCONN_L_OUT_P OUT 7 55 78
B2
L6601 NC MIN_NECK_WIDTH=0.10 MM
FERR-1000-OHM 1 1
R6600 R6610
AUD_GPIO_3 1 2 100K 100K
51 IN
5%
PGND 5%
0402 1/16W 1/16W
A2
CRITICAL MF-LF MF-LF
402 402
2 2
53 9 PP5V_S0_AUDIO_AMP_R
CRITICAL
1
CRITICAL C6622 PLACE_NEAR=U6620.A1:5.1MM
L6620 C6623 1
47UF C6621
A1
FERR-1000-OHM 20%
0.01UF 0.1UF
6.3V 2
1 2 1 2 POLY-TANT 10%
78 51 IN AUD_LO2_R_P 78 AUD_SPKRAMP_RIN_P
0805-LLP
PVDD 16V
2
0402 X7R-CERM
CRITICAL SPKRCONN_R_OUT_P OUT 7 55 78
CRITICAL 10% U6620 0402
C L6621
FERR-1000-OHM
C6624
0.01UF
X7R-CERM
50V
0402
78
NO_TEST=TRUE
SPKRAMP_RIN_P
A3
IN+
MAX98300
WLP
OUT+ B1
SPKRCONN_R_OUT_N
OUT 7 55 78
C
1 2 1 2
78 51 IN AUD_LO2_R_N 78 AUD_SPKRAMP_RIN_N B3 MIN_NECK_WIDTH=0.10 MM
C1
0402
78 SPKRAMP_RIN_N IN- OUT-
10%
NO_TEST=TRUE
CRITICAL
50V
X7R-CERM C2 C3
0402
53 AUD_SPKRAMP_SHUTDOWN_L SHDN* GAIN SPKR_R_GAIN
B2
NC
1
NOSTUFF R6620
1
R6601 100K
100K PGND 5%
53 9 PP5V_S0_AUDIO_AMP_R 5% 1/16W
A2
1/20W MF-LF
MF 402
2
201
2
PLACE_NEAR=U6630.C2:5.1MM
1
CRITICAL 1
CRITICAL 1
C6635 C6632 C6631
CRITICAL
CRITICAL 47UF 47UF 0.1UF
10%
L6630 C6633
20% 20%
16V
C2
2 6.3V 2 6.3V 2
FERR-1000-OHM POLY-TANT POLY-TANT X7R-CERM
0.22UF CRITICAL 0402
1 2 1 2
NO_TEST=TRUE 0805-LLP 0805-LLP VDD SPKRCONN_SR_OUT_P
OUT 7 55 78
78 51 IN AUD_LO1_R_P 78 AUD_SPKRAMP_RSUBIN_P RSUBIN_P MIN_LINE_WIDTH=0.40 MM
0402
U6630 MIN_NECK_WIDTH=0.10 MM
10% SSM2375
16V
WLCSP
CERM B1 C3
402
IN+ OUT+
A1 B3
CRITICAL IN- OUT-
CRITICAL
L6631 C6634 A2 A3
FERR-1000-OHM 53 AUD_SPKRAMP_SHUTDOWN_L SD* GAIN TP_SWR_GAIN SPKRCONN_SR_OUT_N OUT 7 55 78
0.22UF MIN_LINE_WIDTH=0.40 MM
1 2 1 2 B2
78 51 IN AUD_LO1_R_N 78 AUD_SPKRAMP_RSUBIN_N RSUBIN_N NO_TEST=TRUE EDGE
0402
10%
GND
C1
16V
CERM
402
B B
53 9 PP5V_S0_AUDIO_AMP_L
CRITICAL 1
CRITICAL PLACE_NEAR=U6640.C2:5.1MM
CRITICAL C6645 1
CRITICAL 1
L6640 C6643 C6642 C6641
47UF
FERR-1000-OHM 20% 47UF 0.1UF
0.22UF
6.3V 20% 10%
NO_TEST=TRUE NO_TEST=TRUE 2 16V
1 2 1 2 POLY-TANT SPKRCONN_SL_OUT_N
C2
78 51 IN AUD_LO1_L_N 78 AUD_SPKRAMP_LSUBIN_P LSUBIN_P 2 6.3V 2
X7R-CERM OUT 7 55 78
0805-LLP POLY-TANT
CRITICAL 0402
0402
10%
0805-LLP VDD MIN_LINE_WIDTH=0.40 MM
16V
CERM
U6640
402 SSM2375
WLCSP
CRITICAL B1 C3 CKPLUS_WAIVE=ndifpr_badterm
CRITICAL IN+ OUT+
L6641 C6644 A1 B3
CKPLUS_WAIVE=pdifpr_badterm
FERR-1000-OHM IN- OUT-
0.22UF
NO_TEST=TRUE NO_TEST=TRUE SPKRCONN_SL_OUT_P 7 55 78
1 2 1 2 A2 A3 OUT
78 51 IN AUD_LO1_L_P 78 AUD_SPKRAMP_LSUBIN_N LSUBIN_N 53 AUD_SPKRAMP_SHUTDOWN_L SD* GAIN TP_SWL_GAIN MIN_LINE_WIDTH=0.40 MM
0402
10% B2
16V
EDGE
CERM
402
GND
C1
PAGE TITLE
AUDIO: SPEAKER AMP

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
66 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
55 51 PP4V5_AUDIO_ANALOG
54 51 8 =PP3V3_S0_AUDIO_DIG PORT B LEFT(HEADSET MIC) AUDIO JACK: HP CONNECTOR WITH MIKEY & CHS
CRITICAL
HP=80HZ, LP=10.63KHZ
1 C6755
4.7UF
R67621 20%
6.3V
I2C PULLUPS ON SOUTHBRIDGE PAGE 10K 2 X5R-CERM1
5% 402 MIKEY 1A
1/20W
R6757 MF
201 2
APN:353S2640
33 MIKEY ADDRESS: WRITE=72H, READ=73H
42 IN =I2C_MIKEY_SCL 1 2
5%
L6754 MIN_LINE_WIDTH=0.20MM
A2
FERR-22-OHM-1A-0.065-OHM MIN_NECK_WIDTH=0.15MM
R6758 1/20W
MF
VOLTAGE=3.42V
D 42 BI
33
=I2C_MIKEY_SDA
1 2
201 AVDD
U6751
8 =PP3V42_G3H_AUDIO 1
0201
2 PP3V42_GH3_AUDIO_LC
D
5%
1/20W CD3282A1
MF WCSP
201 1 C6790
54 AUDIO_SCL C3 SCL MICBIAS C1 HS_MIC_BIAS CRITICAL
1UF
AUDIO_SDA B3 SDA DETECT B1 HS_SW_DET
10%
10V 1 C6754
L6701
54 2 X5R FERR-33-OHM-0.8A-0.09-OHM
402 0.1UF 7 AUD_CONN_MIC
19 AUD_I2C_INT_L D3 INT* BYPASS D1 HS_RX_BP 10% US_HS_MIC 1 2
OUT 16V
2 X5R-CERM 0201
25 IN AUD_IPHS_SWITCH_EN A3 ENABLE 1
0201
R6754 CRITICAL
NOSTUFF
HS_HDET A1 HDET 1K 55 54 52 51 GND_AUDIO_CODEC L6700
5% 120-OHM-25%-1.3A
C2 DGND
D2 AGND
1/20W
B2
R6761 CS MF
US_HS_GND 1 2 7 AUD_CONN_SLEEVE_XW
A1
201 2
AUD_PORTA_DET_L47K 1 C6756 54 OUT
MIN_LINE_WIDTH=0.4MM MIN_LINE_WIDTH=0.4MM
55 IN
1 2
R67551 0.01UF
10% VDD
MIN_NECK_WIDTH=0.06MM 0402 MIN_NECK_WIDTH=0.2MM
5% 100K
1/20W 5% 2 10V CRITICAL
MF
201
1/20W
MF
X5R-CERM
0201 U6750 L6702
201 2 TS3A8235YFP 120-OHM-25%-1.3A
WCSP
D4 CRITICAL 54 OUT CH_HS_GND 1 2 7 AUD_CONN_MIC_XW
RAMPI MIN_LINE_WIDTH=0.4MM MIN_LINE_WIDTH=0.4MM
55 54 52 51 GND_AUDIO_CODEC CHS_CLAMPI MIN_NECK_WIDTH=0.06MM 0402 MIN_NECK_WIDTH=0.2MM
NO_XNET_CONNECTION=TRUE D3
R6751 R6752 R6753 C4
RAMPO
2
1K 1 1
2.2K 2 1
2.2K 2 CHS_CLAMPO CLAMPI
CRITICAL 5% 1% 1%
B4
C6752 R6750
1/20W
MF
1/20W
MF
1/20W
MF
CLAMPO
APN:510S0009
0.1UF 201 201 201 54 51 8 =PP3V3_S0_AUDIO_DIG
2.2K 2
78 51 OUT AUD_MIC_INL_P 1 2 78 HS_MIC_HI_RC 1 78 HS_MIC_HI D2 MIC MIC1 B1 CRITICAL
10% CRITICAL
5%
1/20W CRITICAL
78 HS_MIC_LO D1 REF MIC2 C1 51 7 OUT AUD_SPDIF_OUT_JACK J6701
6.3V 1 1 C6751 1 C6791 51138-0274
C X5R
201
R6756
100K
5%
1 C6750
6800PF
MF
201 1 C6758
27PF
10UF
20% 20%
10UF 54 IN AUDIO_SCL
A3 SCL
55
AUD_TIPDET_INV 22
F-ST-SM
C
10V OUT
CRITICAL 1/20W 10%
10V
5%
25V 2 X5R-CERM 2 10V
X5R-CERM 54 BI AUDIO_SDA
A4 SDA 21
C6753 MF
201 2
2 X5R-X7R-CERM
0201 R6759
2 NP0-C0G
0201 54 52
0402-1 0402-1 A2 ADDR
0.1UF 51 GND_AUDIO_CODEC
0 55 CRITICAL 1 2
GND1
GND2
AUD_MIC_INL_N 1 2 78 HS_MIC_LO_RC 1 2
78 51 OUT
5% GND L6704 3 4
10% 1/20W XW6751 120-OHM-25%-1.3A 5 6
6.3V MF SM
X5R 201 AUD_HP_PORT_L
1 2 7 AUD_CONN_HP_LEFT 7 8
C2
B2
B3
C3
52 51 IN
201 NO_XNET_CONNECTION=TRUE 51 AUD_HP_PORT_REF
1 2 MIN_LINE_WIDTH=0.3MM 0402
MIN_LINE_WIDTH=0.3MM 9 10
1 MIN_NECK_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM
R6760 PLACE_NEAR=U6750.D1:5.1MM 11 12
47K NO_XNET_CONNECTION=TRUE 54 IN US_HS_GND 13 14
5% CRITICAL
1/20W CH_HS_GND
R/C6750 FILTER TO ADDRESS OUT-OF-BAND
NOISE ISSUE SEEN ON EARLY HEADSETS
MF
201
54 IN
L6703 15 16
(SEE RADAR # 6210118) 2 55 54 52 51 GND_AUDIO_CODEC FERR-33-OHM-0.8A-0.09-OHM 17 18

NOSTUFF CH_HS_MIC 1 2 7 AUD_CONN_SLEEVE 19 20
0201
23
55 54 52 51 GND_AUDIO_CODEC
24
CRITICAL
L6705
120-OHM-25%-1.3A
B 52 51 IN AUD_HP_PORT_R 1 2 7 AUD_CONN_HP_RIGHT
B
MIN_LINE_WIDTH=0.3MM 0402
MIN_NECK_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM
I2C ADDRESSES CRITICAL

MIKEY U6751 READ 0111 0011 0X73 L6706
MIKEY U6751 WRITE 0111 0010 0X72 FERR-470-OHM
CHS U6750 READ 0111 0111 0X77 55 OUT AUD_TYPEDET 1 2 7 AUD_CONN_TYPEDET
CHS U6750 WRITE 0111 0110 0X76 0201
PAGE TITLE
AUDIO: JACK
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
67 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CODEC OUTPUT SIGNAL PATHS
SPEAKER CONNECTOR HP=80HZ
FUNCTION VOLUME CONVERTER PIN COMPLEX MUTE CONTROL DET ASSIGNMENT

APN: 518S0627
HP/LINE OUT 0X02 (2) 0X02 (2) 0X09 (9,A) N/A 0X09 (B)
TWEETERS 0X04 (4) 0X04 (4) 0X0B (11) GPIO_3 N/A 2-MIC CONNECTOR
SUB 0X03 (3) 0X03 (03) 0X0A (10) GPIO_3 N/A
SPDIF OUT N/A 0X08 (8) 0X10 (16) N/A 0X0C (A)
R6885 MIN_NECK_WIDTH=0.15MM
VOLTAGE=3.3V
CRITICAL
1
0 2
7 CON_DMIC_PWR
J6802
CODEC INPUT SIGNAL PATHS 55 51 8 =PP3V3_S0_AUDIO 5% 78171-6006
1/16W M-RT-SM
MF-LF CRITICAL 7
D FUNCTION
DMIC 1
CONVERTER
0X06 (6)
PIN COMPLEX
0X0E (D,E)
VREF
3V3
DET ASSIGNMENT
N/A
R6884
402
J6801 D
1
0 2
FF14A-6C-R11DL-B-3H 78 53 7 IN SPKRCONN_L_OUT_P 1
DMIC2 0X05 (5) 0X12 (12,C) 3V3 0X0C (12,C) 51 7 OUT AUD_DMIC_SDA1 7 CON_DMIC_SDA1 F-RT-SM
SPKRCONN_L_OUT_N 2
78 53 7 IN
5% 7
SPDIF IN 0X07 (7) 0X0F (15) N/A N/A
1/16W NC 55 51 7 OUT SPKRCONN_L_ID 3
HEADSET MIC 0X06 (6) 0X0D (13,V22,B,LEFT) MIKEY MIKEY MF-LF
402 4
1
2 78 53 7 IN SPKRCONN_SL_OUT_P 5
SYSTEM INT AND GPIO LINES
3 78 53 7 IN SPKRCONN_SL_OUT_N 6
FUNCTION INT GPIO

4
8
MIKEY ENABLE SATA4GP/GPIO 16
5
MIKEY INTERRUPT PIRQ H GPIO 5

6
PERIPHERAL DETECT PIRQ F GPIO 3

R6883
0 8
51 OUT AUD_DMIC_CLK 1 2 7 CON_DMIC_CLK NC CRITICAL
5%
1/16W
MF-LF
J6803
402 78171-6006
M-RT-SM
PORT B DETECT(SPDIF DELEGATE) PORT A DETECT (HEADPHONES) 7
55 51 OUT AUD_SENSE_A 78 53 7 IN SPKRCONN_R_OUT_P 1

78 53 7 IN SPKRCONN_R_OUT_N 2
1 1 SPKRCONN_R_ID 3
R6896 R6895 55 51 7 OUT
20.0K 39.2K 4
1% 1%
1/16W 1/16W 78 53 7 IN SPKRCONN_SR_OUT_P 5
MF-LF MF-LF 55 8 =PP5V_S4_AUDIO
2 402 2 402 78 53 7 IN SPKRCONN_SR_OUT_N 6
AUD_PORTA_DET_L 54 AUD_PORTB_DET_L NC
SPEAKERID SPEAKERID 8
Q6897 D 6 Q6897 D 3 R68101 1
R6811
SSM6N15AFE SSM6N15AFE 100K 100K
C SOT563 SOT563 1%
1/16W
MF-LF
402 2
1%
1/16W
MF-LF
C
2 402
2 G S 1 5 G S 4 55 51 7 IN SPKRCONN_L_ID SPKRCONN_R_ID
IN 7 51 55
AUD_OUTJACK_INSERT_L 1 1
55 IN R6812 R6813
100K 100K
1% 1%
AUD_TYPEDET_OD OUT 55 1/16W 1/16W
R6802 MF-LF
402 2
MF-LF
2 402 PORT C DETECT(SPEAKER MISMATCH)
100K 1 PP4V5_AUDIO_ANALOG
55 54 52 51 GND_AUDIO_CODEC 2 SPEAKERID SPEAKERID
1 AUD_SENSE_A
5%
1/20W R6801 55 51 OUT
MF 150K
3
201 SPEAKERID
DMC2400UV
1%
1/20W
Q6800
MF R6816
D
SPEAKERID
SOT563
2 201 100K 2
P-CHN
1 R68941
5
AUD_TYPEDET IN 54 1% 10K
1/16W 1%
S
MF-LF 1/16W
402 MF-LF
402 2
R6803 =PP5V_S4_AUDIO
4
55 8
100K 1 PP4V5_AUDIO_ANALOG 51 54 55
55 54 51 PP4V5_AUDIO_ANALOG
2 AUD_TYPEDET_OD_INV SPEAKERID
NC AUD_PORTC_DET_L
5%
1/20W 6
1 C6810
MF 0.1UF
201 C6800 1 PLACE_NEAR=Q6800.4:5.1MM 10%
6.3V
2 X5R
0.1UF
D 10% 201 SPEAKERID
6.3V 2
Q6800
N-CHN
X5R Q6896 D 6
DMC2400UV 201
SOT563 G 2
AUD_TYPEDET_OD 55 SSM6N15AFE
B S
IN
SPEAKERID
CRITICAL
SPEAKERID
SOT563
B
U6800 L6802 SPEAKERID
MCP6514_POS 3 5 MCP6541T FERR-1000-OHM R6820 2 G S 1
1 SC70-5
GND_AUDIO_CODEC
55 51 8 =PP3V3_S0_AUDIO 51 52 54 55
1 MCP6514_OUT 1 2 SPKR_MATCH_DRV_R1 33 2 SPKR_MATCH_DRV
R6867 4
0402 5%
0 MCP6514_NEG 1/16W
1 2 AUD_IP_PERIPHERAL_DET OUT 19 2 MF-LF
402
1 5%
R6865 1/16W
MF-LF 55 8 =PP5V_S4_AUDIO
47K 402 EXTRACTION NOTIFICATION
5% SPEAKERID
1/20W
MF
2 201
R68141
1 274K 55 54 52 51 GND_AUDIO_CODEC
R6866 1%
1/16W
475K AUD_OUTJACK_INSERT_L OUT MF-LF
1%
AUD_TIPDET_FET1 55 402 2 SPEAKERID
1/20W
MF R6817
2 201 1
45.3K2
APN:376S0613
1%
Q6803 SPEAKERID
SPEAKERID
1/16W
MF-LF
SSM6N15AFE D 6 Q6803 D 3
SOT563
SSM6N15AFE
R68151 1 C6811
402 AUDIO CONNECTOR DETECT STATES
SOT563
90.9K 4.7UF
1% 20%
1/16W NOTHING SPDIF HEADPHONE
MF-LF 2 10V
X5R-CERM
402 2 0402 AUD_J1_TYPEDET_R 1 1 0
R6892 2 G S 1
CRITICAL
5 G S 4 AUD_J1_TIPDET_R 0 1 1
AUD_TIPDET_INV 1.5K 2 AUD_OUTJACK_INSERT_L 1 0 0
54 IN
1 AUD_TIPDET_INV_R L6801
1% FERR-33-OHM-0.8A-0.09-OHM AUD_SENSE_A 1 20K/2.67K RDIV 39.2K/2.67K RDIV
1/16W 1 2 AUD_TIPDET_FET2
MF-LF
402
A 1
C6860
0201
1 SYNC_MASTER=D1_AUDIO SYNC_DATE=06/06/2012 A
1UF C6891 PAGE TITLE
2 10% 25V
X5R 402 1UF 25V Alternate Parts AUDIO: JACK TRANSLATORS
10%
2 X5R 402 TABLE_ALT_HEAD
DRAWING NUMBER SIZE

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
TABLE_ALT_ITEM
REVISION
353S3452 353S1286 U6800 MAXIM ALT TO MICROCHIP R
NOM R6892-C6860 FC = 106Hz 55 54 52 51 GND_AUDIO_CODEC TABLE_ALT_ITEM
<E4LABEL>
SSM6N15FE Vth = 0.8V to 1.5V 376S0975 376S1081 Q6800 TOSHIBA ALT TO DIODES NOTICE OF PROPRIETARY PROPERTY: BRANCH
SSM6N15FE IGSS = +/-1uA THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
FLEX-SIDE RPULLDOWN = 100k (TB 49.9k in REV 3) THE POSESSOR AGREES TO THE FOLLOWING: PAGE
68 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
MagSafe DC Power Jack
F6905
6AMP-32V-0.0095OHM =PP18V5_DCIN_CONN
1 2 8
0603
CRITICAL =PP3V42_G3H_ONEWIREPROT
J6900 8
53780-8608 1
C6908
F-RT-SM
10 0.1UF
7 PP18V5_DCIN_FUSE CRITICAL 20%
1
MIN_NECK_WIDTH=0.20MM U6901
2
10V
CERM
402
PLACEMENT_NOTE=PLACE NEAR U6900 and U6901
www.qdzbwx.com
NC VOLTAGE=18.5V
D
2
3
TC7SZ08FEAPE
SOT665
4
5
A
2 SMC_BC_ACOK IN 39 40 D
4 Y
1
5 B
6 NO STUFF 3
7
1 C6905 SMC_BC_ACOK_VCC =PP18V5_DCIN_ISOL
0.1UF 8
8 10% BLEEDER
2 50V
X7R
603-1 1 CRITICAL
9 C6900 1
0.1UF R6929 D6920
1
20%
10V 2.0K SBR0330CW
CERM 2 VCC 5% SOT-323
402 1/16W 1
MF-LF
518S0543 U6900 2 402
MAX9940 3 DCIN_ISOL_BLEEDER_PSRC
SC70-5 MIN_LINE_WIDTH=0.6MM
7 ADAPTER_SENSE 5 EXT INT 4 SYS_ONEWIRE BI 39 MIN_NECK_WIDTH=0.20MM
2
CRITICAL 1 C6920
0.1UF
10% 1 Input impedance of 68K meets
NC GND 2 50V
X7R
BLEEDER R6912
1-Wire OverVoltage Protection BLEEDER 603-1 68K sparkitecture requirements
2
1%
The chassis ground will otherwise float and can
1 1/20W for both MPM4 and MPM5.
send transients onto ADAPTER_SENSE when AC is
R6930 MF
2 201
1K 2
Q6910
connected. NC 5%
1/16W S BLEEDER SI5419DU
MF-LF 1
2 402 POWERPAK
G Q6920
DCIN_ISOL_BLEEDER_R AO3407A 5A
MIN_LINE_WIDTH=0.6MM SOT23
BLEEDER 1
R6910
D
3 D 1 When input voltage is 2V the FET will be off
S
5 100K
D 3 5% blocking the leakage path and 22.1K can be
Q6930
G
1/20W
C6912 1 properly detected.
C 2N7002
SOT23-HF1 S G 1 DCIN_ISOL_BLEEDER_NGATE
4 0.047UF
10%
MF
2 201
When input voltage is at 16V+, FET will
C
25V
2
1
BLEEDER X5R 2 R6911 conduct and power charger and 3.42V reg
R6921 0402
10K
DCIN_ISOL_GATE_R 1 2
10K
5% 1%
1/16W 1/20W
MF-LF MF
201
2 402 DCIN_ISOL_GATE
K
PLACE COMPONENTS NEAR BATTERY CONNECTOR AREA D6910
PPVBAT_G3H_CONN 6.8V Zener GDZT2R6.8
7 57 GDZ-0201
A
7 SYSDET_3_4
C6950 1 C6960 1
0.1UF 1UF OMIT
10% 10%
25V 2 25V 998-4777
X5R X5R 2
402 603-1 CRITICAL
J6950 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
R6920 CRITICAL
INTERPOSER-D1-TOP
47
COMBO-SM 1 2 PP18V5_DCIN_CONN_R D6905 138S0811 3 CAP,CER,4.7UF,10%,25V,X6S,0603 C6990,C6991,C6992 CRITICAL
MIN_LINE_WIDTH=0.6 mm SBR0330CW
A1 A1 E2 E2 1% MIN_NECK_WIDTH=0.25 mm SOT-323
1/3W VOLTAGE=18.5V
A2 A2 E3 E3 MF 1 =PP3V42_G3H_REG 8
A3 A3 E8 E8
805 3.425V "G3Hot" Supply
R6905 3 PPVIN_G3H_P3V42G3H
A4 A4 E9 E9 MIN_LINE_WIDTH=0.4 mm Supply needs to guarantee 3.31V delivered to SMC VRef generator
A6 E10 =PPBUS_G3H 1
10 2 PPBUS_G3H_R 2 MIN_NECK_WIDTH=0.2 mm
A6 E10 57 8 VOLTAGE=18.5V
MIN_LINE_WIDTH=0.6 mm P3V42G3H_BOOST
A7 A7 5% MIN_NECK_WIDTH=0.25 mm
B A8 A8
F2
F3
F2
F3
1/8W
MF-LF
805
VOLTAGE=18.5V
OMIT_TABLE OMIT_TABLE OMIT_TABLE
DIDT=TRUE
NO_TEST=TRUE B
3
A9 A9
F8 F8
C6992 1 C6991 1 C6990 1
VIN BOOST
C6994 1
A10 A10 4.7UF 4.7UF 4.7UF 0.22UF CRITICAL
F9 F9 10% 10% 10% 10%
B1 F10 =SMBUS_BATT_SCL
35V
X5R-CERM 2
35V
X5R-CERM 2
35V
X5R-CERM 2 U6990 10V
CERM 2 L6995
B1 F10 BI 42 0603 0603 0603 LT3470AED 40210UH-30%-0.85A-460MOHM
B2 B2 DFN
G1 G1 8 SHDN* SW 4 P3V42G3H_SW 1 2
B3 B3 MIN_LINE_WIDTH=0.5 mm Vout = 3.425V
G2 G2 BIAS 2 MIN_NECK_WIDTH=0.25 mm 2520
B4 B4
G3 7 NC CRITICAL SWITCH_NODE=TRUE
G3 NC DIDT=TRUE 100MA MAX OUTPUT
B6 B6
G7 G7 FB 1
B7 B7 <Ra> (Switcher limit)
G8 G8 THRM
GND PAD 1
B8 B8
G10 G10 =SMBUS_BATT_SDA BI 42
1 C6995 R6995
9
B9 B9 22PF 348K
5% 1%
B10 B10 H1 H1 50V 1/20W
H2
2 CERM MF CRITICAL
H2 201 2
C1 C1
H3 H3
201 1 C6999
C2 C2 P3V42G3H_FB 22UF
H4 H4 20%
C3 C3 CRITICAL <Rb> 6.3V
2 X5R
H6 H6
C4 C4
H7
D6950 R6996 1 0603
1
H7
C6 C6 RCLAMP2402B 200K
1%
C7 C7 J1 J1 SC-75 1/20W
MF
C8 C8 J2 J2 201 2
C9 C9 J3 J3 SH6950
3
C10 C10 J4 J4 4.0OD2.7ID-1.8H

J7 J7 2 Vout = 1.25V * (1 + Ra / Rb)
D1 D1
J6 J6
D2 D2
1
3
D3 D3
A D7
D8
D7
D8
STIFF 63
Pin 63 (SH0962) is Neoconix stiffener, 860-1533 SYNC_MASTER=MASTER SYNC_DATE=MASTER A
TALL 64 PAGE TITLE
D9 D9 Pin 64 (SH0961) is Neoconix tall locator pin. 860-1530
D10 65
DC-In & Battery Connectors
D10 SHRT
Pin 65 (SH0960) is Neoconix short clocking pin. 860-1529 DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
69 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Reverse-Current Protection
PPDCIN_G3H_DRAINS NOSTUFF
VOLTAGE=18.5V C7080 1 R7092 MIN_NECK_WIDTH=0.25 mm For Erp Lot6 spec R7090
4.7UF MIN_LINE_WIDTH=0.5 mm 02 CHGR_DCIN
10% 0 (P5V1_BIAS) 1 57
35V 57 CHGR_DCIN_D_R 1 2 P5V1_VIN P5V1_BOOST
Inrush Limiter X5R-CERM 2
0603
MF-LF
MIN_LINE_WIDTH=0.5 mm5% 402
1/16W
DIDT=TRUE
NO_TEST=TRUE
MF-LF 5% 402
1/16W
NOSTUFF
3
C7090 1 C7094 1
4.7UF
10%
VIN BOOST 0.22UF
10% CRITICAL R7091
NCNCNC U7090 0 2 PP5V1_CHGR_VDDP
FROM ADAPTER 35V
X5R-CERM 2
LT3470A
10V
CERM 2 L7095
33UH-20%-0.39A-0.435OHM
1 57
10
0603 402 MF-LF5% 402
1
2
8
9
4
5
DFN MIN_NECK_WIDTH=0.25 mm
8 =PPDCIN_S5_CHGR OMIT_TABLE
1 2 MIN_LINE_WIDTH=0.5 mm 1/16W
8 SHDN* SW 4 P5V1_SW
D
PPDCIN_G3H_INRUSH
MIN_NECK_WIDTH=0.1 mm CRITICAL
BIAS 2
MIN_LINE_WIDTH=0.5 mm DP418C-SM
SWITCH_NODE=TRUE
CRITICAL CRITICAL D
Q7080 VOLTAGE=18.5V NC 7 NC DIDT=TRUE 1 1 C7098 C7099
S
1 P5V1_BIAS
1 C7085 R7085 IRF9395TRPBF 1
R7080 FB 1
<Ra> 1
R7095 10UF
20%
10UF
20%
0.1UF 470K
10% 1% DIRECTFET-MC 100K GND
THRM 1 C7095 681K 2 25V 25V
X5R-CERM 2 X5R-CERM
2 25V
1/16W 5% PAD
22PF 1% 0603 0603Vout = 5.50V
G
X5R MF-LF 1/16W 1/20W
9
5% 100MA MAX OUTPUT
402 2 402 MF-LF 50V MF
CRITICAL 2 402 2 CERM 201 2
(Switcher limit)
6
CHGR_AGATE_DIV CHGR_SGATE_DIV 201
MIN_LINE_WIDTH=0.3 mm MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm P5V1_FB
1 1
8 =PPDCIN_S5_CHGR_ISOL R7086 R7081 <Rb>
332K
1%
62K
5% R70961
CRITICAL 1/16W 1/16W 200K
MF-LF MF-LF 1%
D7005 402 2 2 402 1/20W
MF
SBR0330CW Vout = 1.25V * (1 + Ra / Rb) 201 2
SOT-323 (CHGR_AGATE)
1 (CHGR_SGATE)
R7005
20 R7021
3 57 CHGR_DCIN_D_R 1 2 (CHGR_DCIN)
1
10 2
5%
2 1/16W CRITICAL
ACIN pin threshold is 3.2V, +/- 50mV MF-LF 5%
CHGR_CSI_R_P 3 1 PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
402 1 C7020 1/16W
MF-LF
78
R7020
Divider sets ACIN threshold at 13.55V 0.047UF 402 0.02 138S0811 1 CAP,CER,4.7UF,10%,25V,X6S,0603 C7090 CRITICAL
0.5%
10% 1W
Input impedance of ~90K meets 2 10V
X5R-CERM R7022 78 CHGR_CSI_R_N MF
RL1632W NOTE: C7080 is the same APN, but NOSTUFFed per <rdar://problem/11815538>.
30mA max load 0402 4 2
sparkitecture requirements 1
10 2
PP5V1_CHGR_VDD R7001 PPDCIN_G3H_CHGR
=PP3V42_G3H_CHGR MIN_LINE_WIDTH=0.2 mm 1
4.7 2 PP5V1_CHGR_VDDP
5% MIN_LINE_WIDTH=0.6 mm
66 8 MIN_NECK_WIDTH=0.2 mm 57 1/16W
MF-LF
MIN_NECK_WIDTH=0.2 mm CRITICAL CRITICAL CRITICAL
VOLTAGE=5.1V MIN_LINE_WIDTH=0.2 mm VOLTAGE=18.5V
5%
1/16W
VOLTAGE=5.1V
NO_XNET_CONNECTION=TRUE 402 1
C7030 1
C7031 1
C7032 1 C7035 1 C7036 1 C7037
MF-LF 22UF 22UF 22UF 1.0UF 1.0UF 0.001UF
402 C7001 1 C7022 1 1 C7021 20% 20% 20% 10%
2 50V
10%
2 50V
20%
50V
C C7002 1 1
NO STUFF 1UF
10%
10V 2
0.1UF
10%
25V 2
0.1UF
10%
2 25V
2 25V
POLY-TANT
CASE-D2-SM
2 25V
POLY-TANT
CASE-D2-SM
2 25V
POLY-TANT
CASE-D2-SM
X5R
0603
X5R
0603
2 CERM
0402 C
R70121 1UF
10%
R7002 X5R
402
X5R
402
X5R
402
PLACE_NEAR=C7036.1:3mm
10V 2 100K PLACE_NEAR=Q7030.5:1mm

1K 5% NO_XNET_CONNECTION=TRUE
19
20
1% X5R 1/16W
1/16W 402 57 MF-LF
MF-LF 2 402
402 2 GND_CHGR_AGND VDD VDDP CHGR_BOOT_R
R7000 12 VHST CRITICAL DCIN 2 57 CHGR_DCIN MIN_LINE_WIDTH=0.2 mm
1 SMC_RESET_L 1
0 2 CHGR_RST_L 13 1 1 C7025 Max Current = 8.5A
R7010 IN SMB_RST_N
SGATE 26 CHGR_SGATE R7025 0.22UF
68.1K
1%
5%
1/16W
42 IN =SMBUS_CHGR_SCL 11 SCL U7000
AGATE 1 CHGR_AGATE 5%
0 10% 2 CRITICAL (L7030 limit)
1/16W MF-LF =SMBUS_CHGR_SDA 10 SDA TQFN 1/16W 2 10V
MF-LF 402
42 BI
CHGR_VFRQ 4 CSIP
ISL6259
28 77 CHGR_CSI_P MF-LF CERM
402 Q7030 f = 400 kHz
2 402 66 IN VFRQ
CSIN 27 77 CHGR_CSI_N 402 2 PLACE_NEAR=U7000.25:2mm RJK03P0DPA
CHGR_CELL 6 CELL MIN_LINE_WIDTH=0.2 mm CRITICAL CRITICAL
Float CELL for 1S 25 CHGR_BOOT MIN_NECK_WIDTH=0.2 mm 1 WPAK
L7030 TO SYSTEM
CHGR_ACIN 3 ACIN
BOOT SWITCH_NODE=TRUE
DIDT=TRUE MIN_LINE_WIDTH=0.6 mm 4.7UH-20%-8.5A-18.3MOHM F7040
UGATE 24 CHGR_UGATE MIN_NECK_WIDTH=0.2 mm 7 12AMP-32V
GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm CHGR_PHASE 1 2 1 2
1 CHGR_ICOMP 5 ICOMP PHASE 23 DIDT=TRUE MIN_NECK_WIDTH=0.2 mm =PPBUS_G3H 8 56
R7011 CHGR_VCOMP 7 VCOMP
SWITCH_NODE=TRUE
MIN_NECK_WIDTH=0.2 mm DIDT=TRUE PIME103T-4R7MS
21.5K LGATE 21 CHGR_LGATE MIN_LINE_WIDTH=0.6 mm 1206
1% CHGR_VNEG 8 VNEG GATE_NODE=TRUE
6
1/16W 1 DIDT=TRUE
MF-LF R7015 77 CHGR_CSO_P 18 CSOP BGATE 16 CHGR_BGATE
2 402 100K 77 CHGR_CSO_N 17 CSON 20V/V AMON 9 CHGR_AMON 44
OUT
1%
29 THRM_PAD
1/16W 36V/V BMON 15 CHGR_BMON 44

(AGND)
OUT PPVBAT_G3H_CHGR_REG
MF-LF 3 4 5
2 402
1 C7050 (OD) ACOK 14 =CHGR_ACOK OUT 40 44 MIN_LINE_WIDTH=0.6 mm
CRITICAL
22 PGND
1UF MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
CHGR_VCOMP_R 10%
2 16V
1
C7040 1 C7045
X5R 68UF 0.001UF
1 C7015 402 353S2929 20%
2 16V
10%
2 50V
330PF CRITICAL POLY-TANT X7R-CERM
5% CASE-D2E-SM 0402
2 50V
COG CRITICAL
402 R7050 Q7055
B 1
R7042
0
0.01
0.5%
SI7137DP
SO-8
B
5%
1/16W
1W
MF
SYM-VER-2
TO/FROM BATTERY
1 0612-3
MF-LF
2 402
R7016 XW7000 1 2 PPVBAT_G3H_CHGR_R 3 S
3.01K SM MIN_LINE_WIDTH=0.6 mm
1% 3 4 MIN_NECK_WIDTH=0.2 mm 2 D 5 PPVBAT_G3H_CONN 7 56
1/16W 1 2 (GND) VOLTAGE=12.6V MIN_LINE_WIDTH=0.6 mm
MF-LF
402 2 PLACE_NEAR=U7000.29:1mm
C7055 1 C7056 1 C7057 1 1 MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
PLACE_NEAR=U7000.22:1mm 1UF 0.1UF 0.01UF
10% 10% 10% G
CHGR_VNEG_R 25V 2 25V 2 50V
X5R X5R X7R-CERM 2 4
402 402 0402
1 C7016 (CHGR_CSO_P) R7051 2.2 1 2 78 CHGR_CSO_R_P
470PF 5% 1/16W MF-LF 402
10% (CHGR_CSO_N) R7052 0 1 2 78 CHGR_CSO_R_N
2 50V
CERM 5% 1/16W MF-LF 402
0402
(PPVBAT_G3H_CHGR_R) (PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)
CHGR_ICOMP_RC
1 C7042 C7011 1 1 C7000 C7005 1 C7026 1
0.068UF 0.01UF 1UF 0.22UF 0.001UF
10% 10% 10% 10% 10%
2 10V
X5R-CERM
16V
X7R-CERM 2
10V
2 X5R 50V
X5R-CERM 2
50V
X7R-CERM 2
0402 0402 402-1 0603-1 0402
57 GND_CHGR_AGND
VOLTAGE=0V
PAGE TITLE
PBus Supply & Battery Charger

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
70 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
System Agent Power Supply

D D

138S0812 1 CAP,CER,1UF,10%,35V,X6S,0402,MURATA C7121 CRITICAL
8 =PPVIN_S0_VCCSAS0
8 =PP5V_S0_VCCSAS0
VCCSAS0_BOOT_RC OMIT_TABLE
CRITICAL MIN_LINE_WIDTH=0.3 mm CRITICAL
R71011 1 C7101 DIDT=TRUE C7120 1 C7121 1 1 C7122
2.2 10UF 68UF 1.0UF 0.001UF
5% 20% 20% 10% 20%
1/16W 2 10V
X5R
1 C7130 16V 2 35V
CERM-X5R 2 2 50V
CERM
MF-LF
402 2 603 R71301 0.22UF
10%
POLY-TANT
CASE-D2E-SM 0402 0402
0 10V PLACE_NEAR=C7121.1:3mm
5% 2 CERM
PP5V_S0_VCCSAS0_VCC 1/16W 402
PLACE_NEAR=Q7100.2:1mm
MIN_LINE_WIDTH=0.6 mm MF-LF
MIN_NECK_WIDTH=0.2 mm 402 2
VOLTAGE=5V 376S0944
19
20
CRITICAL
VCC PVCC VCCSAS0_VBST
Q7100
U7100 MIN_NECK_WIDTH=0.2 mm
DIDT=TRUE
2 RJK0222DNS
ISL95875 HWSON CRITICAL
UTQFN VCCSAS0_DRVH R7140 C
C R7151 66 IN =PVCCSA_EN 15 EN BOOT 18 MIN_LINE_WIDTH=0.6 mm
CRITICAL
L7100
0.001
CPU_VCCSASENSE 11.62K2 CRITICAL GATE_NODE=TRUE 2%
CPU_VCCSASENSE_DIV 10 FB UGATE 17 1 1W =PPVCCSA_S0_REG
72 13 IN DIDT=TRUE 1.0UH-7A MF
8 80
1% 0612
1/16W VCCSAS0_SREF 7 SREF PHASE 16 VCCSAS0_LL 7 1 2 PPVCCSA_S0_REG_R 2 1
MF-LF NO_TEST=TRUE MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm
402 MIN_NECK_WIDTH=0.2 mm PIMB053T-SM MIN_NECK_WIDTH=0.2 mm 4 3 6A Max Output
VCCSAS0_VO 12 VO LGATE 1 SWITCH_NODE=TRUE VOLTAGE=1.05V
1
R7147 DIDT=TRUE 152S1302 f = 500 kHz
41.2K VCCSAS0_OCSET 11 OCSET 6
1%
1/16W
1 C7160
PVCCSA_PGOOD 14 1000PF
R7153 MF-LF
2 402
66 OUT PGOOD 10%
16V
VCCSAS0_RTN 1
1.62K2 VCCSAS0_RTN_DIV 4 VCCSAS0_DRVL 2 X7R-CERM
RTN 3 4 5 0201
NO_TEST=TRUE MIN_LINE_WIDTH=0.6 mm
1% 13 MIN_NECK_WIDTH=0.2 mm
1/16W VCCSAS0_FSEL FSEL GATE_NODE=TRUE
MF-LF DIDT=TRUE
402 8 SET0
2 VCCSAS0_SET0
C7103 1 NO STUFF
XW7101
SM
0.022UF
10% R71031 VCCSAS0_SET1 9 SET1
16V 0
X5R-X7R-CERM 2 1 6 VID0
PLACE_NEAR=C1761.2:1mm1
0402 R7148 5%
1/16W
52.3K MF-LF 5 VID1 (ENDIAN SWAP)
1% 402 2
1/16W 80 78 VCCSAS0_CS_P
MF-LF
2 402
1 C7102 80 78 VCCSAS0_CS_N
2.2UF 1
VCCSAS0_SET_R
GND PGND
10% R7141
2 16V 1K
2
X5R
R7150 603 NO_XNET_CONNECTION=TRUE
1%
1/16W
82.5K2
1 MF-LF C7140
402 2
1%
1000PF
1/16W 72 13 CPU_VCCSA_VID<1> 2 1
MF-LF IN
1 1
402 72 13 IN CPU_VCCSA_VID<0> 5%
1 C7106 R7154 R7152 1 C7105 25V 1
R7142
B 5%
10PF 4.64K
1%
4.64K
1/16W
1%
1/16W 5%
10PF
NP0-C0G
402 1K
1% OCP = R7141 x 8.5uA / R7140
B
2 50V
CERM MF-LF MF-LF 2 50V
CERM
1
R7149 1/16W
402 2 402 2 402 402 499K (VCCSAS0_OCSET)
MF-LF
OCP = 8.5A
1% 2 402
MF-LF (VCCSAS0_VO)
2 402
XW7100
SM
VCCSAS0_AGND 1 2
VOLTAGE=0V
INTEL TABLE:
VID1 VID0 Voltage
0 0 0.9V
1 0 0.8V
0 1 0.725V
1 1 0.675V
PAGE TITLE
System Agent Supply

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
71 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION

D
138S0812 2 CAP,CER,1UF,10%,35V,X6S,0402,MURATA C7241,C7281 CRITICAL
59 8 =PP5V_S4_REG
8 =PPVIN_S5_P5VP3V3
CRITICAL CRITICAL CRITICAL OMIT_TABLE

=PP5V_S5_LDO CRITICAL CRITICAL CRITICAL OMIT_TABLE
C7243 1 C7240 1 C7242 1 1 C7241 1 C7270 8
C7284 1 C7280 1 C7282 1 1 C7281 1 C7283
68UF 68UF 68UF 1.0UF 0.001UF C7200 1 VOUT = 5V 68UF 68UF 68UF 1.0UF 0.001UF
20% 20% 20% 10% 20% 20% 20% 20% 10% 20%
16V 16V 16V 35V 50V 1UF 100MA MAX OUTPUT 16V 16V 16V 2 35V 2 50V
POLY-TANT 2 POLY-TANT 2 POLY-TANT 2 2 CERM-X5R
0402
2 CERM
0402
10%
25V 2 POLY-TANT 2 POLY-TANT 2 POLY-TANT 2 CERM-X5R
0402
CERM
0402
CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM CRITICAL CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM
X5R
603-1 1 C7205
P5VP3V3_VREG3 10UF
20%
2 6.3V
X5R
P5VP3V3_VREF2 603
59 8 =PP5V_S4_REG SKIP_5V3V3:INAUDIBLE =PP3V3_S5_REG 8
1
23
29
22
13
R7201 C7201 1 C7203
2
VOUT = 5.0V SKIP_5V3V3:AUDIBLE 1 VOUT = 3.3V
0
1
0.22UF 2.2UF
R72001 5%
V5SW
VIN
VREG5
VREG3
VREF2
12A MAX OUTPUT 1 152S0688 MIN_LINE_WIDTH=0.6 MM 1/20W 10% 20% MIN_LINE_WIDTH=0.6 MM 152S0754 10.5A MAX OUTPUT
MIN_NECK_WIDTH=0.2 MM 0 MF 10V 2 10V
CRITICAL 5% 201 2 CERM 2 X5R-CERM MIN_NECK_WIDTH=0.2 MM
C7264 1 CRITICAL
F = 600 KHZ
L7220 CRITICAL
1 C7224 1/20W
MF
402 402
0.1UF L7260 F = 600 KHZ
0.1UF 201 2 6 SKIPSEL1 10% 2 376S0958
CRITICAL 1.0UH-21A-0.006OHM 10% CRITICAL 50V 2 1.0UH-22A
PCMB103T-1R0MS Q7220 2 50V R72441 P5VP3V3_SKIPSEL 19 SKIPSEL2 X7R CRITICAL PCMC063T-SM
1
C7253 1 C7271 CSD58872Q5D
X7R
603-1 1 14 OCSEL U7201 =P5VS5_EN R7263 603-1
Q7260 C7272 1
C 330UF
20%
0.001UF
10%
50V 2
1 VIN SON5X6
TG 3 P5VS4_TG 5%
1/16W
QFN
EN 12 IN 66
1
0 2 P3V3S5_TG FDMS3602S
0.001UF
10%
50V
C
TPS51980
6.3V
2 POLY-TANT 2 X7R-CERM MIN_LINE_WIDTH=0.6 MM MF-LF MIN_LINE_WIDTH=0.6 MM POWER56 X7R-CERM 2
MIN_NECK_WIDTH=0.2 MM 402 2 P5VS4_VBST 31 VBST1 VBST2 26 P3V3S5_VBST 5% MIN_NECK_WIDTH=0.2 MM 1
2
CASE-D3L-SM 0402 P5VS4_VSW 6 VSW DIDT=TRUE DIDT=TRUE 1/16W DIDT=TRUE
0402
CRITICAL CRITICAL MIN_LINE_WIDTH=0.6 MM 7 TGR 4 P5VS4_DRVH 1 DRVH1 P3V3S5_DRVH
MF-LF GATE_NODE=TRUE
PHASE 7 CRITICAL CRITICAL
MIN_NECK_WIDTH=0.2 MM DRVH2 24 402
C7252 1 C7250 1 DIDT=TRUE
8 MIN_LINE_WIDTH=0.6
MIN_NECK_WIDTH=0.2
MM
MM
GATE_NODE=TRUE DIDT=TRUE DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 MM
1 C7290 1
C7292
330UF 10UF P5VS4_LL 32 SW1 SW2 25 P3V3S5_LL 10UF 330UF
20% 20%
20% 25V NO STUFF MIN_LINE_WIDTH=0.6 MM SWITCH_NODE=TRUE DIDT=TRUE DIDT=TRUE SWITCH_NODE=TRUE MIN_LINE_WIDTH=0.6 MM NO STUFF 20%
6.3V
POLY-TANT 2 X5R-CERM 2 1 BG 5 MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM 6 2 25V
X5R-CERM 6.3V
2 POLY-TANT
CASE-D3L-SM 0603 R7299 MIN_LINE_WIDTH=0.6 MM GATE_NODE=TRUE
P5VS4_DRVL
DIDT=TRUE
30 DRVL1 DRVL2 27 P3V3S5_DRVL
DIDT=TRUE GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 MM R72981 0603 CASE-D3L-SM
1 PGND
P5VS4_CSP1 7 CSP1 P3V3S5_CSP2 MIN_NECK_WIDTH=0.2 MM 10
5% CSP2 18 5%
1/10W 1/10W
C7218 P5VS4_CSN1 8 CSN1 CSN2 17 P3V3S5_CSN2 C7288
9
MF-LF MF-LF
2 603 0.1UF 0.1UF
3 4 5 603 2
P3V3S5_RF
11 MODE RF 3
P5VS4_SNUBR 1 2 1 2 P3V3S5_SNUBR
MIN_LINE_WIDTH=0.6 MM P5VS4_VFB1 9 VFB1 VFB2 16 P3V3S5_VFB2 MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM 10% 10% MIN_NECK_WIDTH=0.2 MM
DIDT=TRUE
16V P5VS4_COMP1 10 COMP1 COMP2 15 P3V3S5_COMP2 16V DIDT=TRUE
X7R-CERM
2 NO STUFF 0402 =P5VS4_EN 4 EN1 EN2 21 =P3V3S5_EN R72061 X7R-CERM
0402 NO STUFF 2
XW7222 C7299 1 66 47 IN
P5VS4_PGOOD 5 PGOOD1 PGOOD2 20 P3V3S5_PGOOD
IN 66
165K 1 C7298 XW7262
SM 0.0033UF
10%
R7247 66 OUT OUT 66 1%
1/16W R7246 10%
0.001UF SM
50V 1
1.5K 2 GND THRM_PAD MF-LF
1
806 2 50V
1 CERM 2 402 2 2 X7R 1
402 402
28
1% 1%
33
P5VS4_VFB1_R 1/16W 1/16W P3V3S5_VFB2_R
2 2 R72561 MF-LF
402 1
R7237 R72361 1
R7238 R72391 MF-LF
402
1
R7216 2 2
XW7220 XW7221 3.01K 12.1K 12.1K 10K 5.23K XW7260 XW7261
SM SM 1% 10K 1% 1% 1% 1% SM SM
1 1/16W 1% 1/16W 1/16W 1/16W 1/16W
R7220 1 1
MF-LF
402 2
1/16W
MF-LF
MF-LF
402 2 2
MF-LF
2 402
MF-LF
402 2
MF-LF
2 402 1 1 R72601
40.2K 2 402 23.2K
0.5%
1/16W P5VS4_CSP1_R P5VS4_COMP1_R XW7200
SM
P3V3S5_COMP2_R P3V3S5_CSP2_R 0.5%
1/16W
MF-LF MF-LF
2 0402 PLACE_NEAR=U7200.28:1MM
1
0402 2
C7237 1 1 C7236 C7238 1 1 C7239
150PF 4700PF 4700PF 47PF
B 1
R7221
5%
50V
CERM 2
402
10%
2 100V
CERM
402
10%
100V 2
CERM
402
5%
50V
2 CERM
402 R72611
B
10.0K (P5VP3V3_VREF2) (P5VP3V3_VREF2) 10.0K
0.5% 0.5%
1/16W 1/16W
MF MF
2 402 402 2
GND_5V3V3_AGND
VOLTAGE=0V
PAGE TITLE
5V / 3.3V Power Supply

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

138S0812 2 CAP,CER,1UF,10%,35V,X6S,0402,MURATA C7332,C7335 CRITICAL
D D
DDR3 (1V5R1V35 S3) REGULATOR
8 =PPVIN_S3_DDRREG
CRITICAL CRITICAL OMIT_TABLE OMIT_TABLE

CRITICAL
1
C7336 1
C7331 1
1 C7332 1C7335 1 C7333
68UF 68UF C7334 1.0UF 1.0UF 0.001UF
20% 20% 68UF 10% 10% 20%
2 16V
POLY-TANT
16V
2 POLY-TANT 20% 2 35V
CERM-X5R 2 35V
CERM-X5R
50V
2 CERM
16V
2 POLY-TANT 0402 0402 0402
8 =PPVIN_S0_DDRREG_LDO CASE-D2E-SM CASE-D2E-SM
CASE-D2E-SM
=PP5V_S3_DDRREG CRITICAL PLACE_NEAR=Q7330.5:1mm

PLACE_NEAR=Q7330.5:1mm PLACE_NEAR=C7332.1:3mm
8
C7301 1
CRITICAL 10UF
20%
10V
C7300 1 X5R-CERM 2
0402-1
10UF PLACE_NEAR=U7300.2:1mm
20%
10V
X5R-CERM 2 (DDRREG_DRVH)
0402-1
2
MIN_LINE_WIDTH=0.6 mm 2
R7325 MIN_NECK_WIDTH=0.17 mm CRITICAL
C VLDOIN MIN_NECK_WIDTH=0.17 mm
402
NO_TEST=TRUE 5% 0
MF-LF
1/16W
C7325
0.1UF Q7330 152S0905
CRITICAL
C
12 V5IN VBST 15 DDRREG_VBST 1 2 DDRREG_VBST_RC 1 2 FDMS3602S
DDRREG_FB DRVH 14 DDRREG_DRVH MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm 1 POWER56 L7330
31 IN
U7300 GATE_NODE=TRUE (DDRREG_LL)
10% 0.68UH-18A-3.3MOHM
27 9 =DDRVTT_EN VTT Enable 17 S3 SW 13 DDRREG_LL DIDT=TRUE
25V
IN X5R 7 1 2
=DDRREG_EN 16 S5
TPS51916 SWITCH_NODE=TRUE 402
PHASE
=PPDDR_S3_REG
66 IN VDDQ/VTTREF Enable DIDT=TRUE 8
QFN PCMB103T
DRVL 11 DDRREG_DRVL GATE_NODE=TRUE
DIDT=TRUE MIN_LINE_WIDTH=0.6 mm
DDRREG_1V8_VREF 6 VREF MIN_NECK_WIDTH=0.17 mm
CRITICAL PGOOD 20 DDRREG_PGOOD OUT 9 6 CRITICAL Vout = 1.5V
1 VDDQSNS 9 DDRREG_VDDQSNS 1
C7340 15.5A max output
C7315 1 R7315 8 REFIN
VTT 3 8 =PPVTT_S0_DDR_LDO XW7360 330UF (Q7335 limit)
0.1UF 20.0K SM 20%
10% 1%
1/16W
DDRREG_MODE 19 MODE VTTSNS 1
DDRREG_VTTSNS 1 2 3 4 5 CRITICAL
2 2.0V
POLY-TANT
1 C7346 f = 400 kHz
16V
X7R-CERM 2 MF-LF DDRREG_TRIP 18 TRIP PLACE_NEAR=C7361.1:3mm (DDRREG_DRVL) CASE-B2-SM1 0.001UF
1 10%
0402 2 402 VTTREF 5 =PPVTT_S3_DDR_BUF C7342 CRITICAL 50V
2 X7R-CERM
PLACE_NEAR=U7300.6:1mm PLACE_NEAR=U7300.8:5mm
MIN_LINE_WIDTH=0.6 mm 330UF
10mA max load
CRITICAL CRITICAL MIN_NECK_WIDTH=0.17 mm 20%
2 2.0V
C7341 1 1 C7345 0402
OMIT_TABLE PGND GND
VTT THRM C7360 1 1 C7361 POLY-TANT 330UF 10UF 2
OMIT_TABLE GND PAD CASE-B2-SM1 20% 20%
R7319 1 1
R7316 10UF 10UF 2.0V 2 25V
2 X5R-CERM XW7301
1 C7316 20% 20% POLY-TANT
10
21
150K 100K 25V 25V CASE-B2-SM1 0603 SM
0.01UF 1 X5R-CERM 2 2 X5R-CERM
1%
1/16W
1%
1/16W 10%
16V
R7317 1R7318 0603 0603 1
MF-LF MF-LF 2 X7R-CERM 200K 51.1K PLACE_NEAR=C7361.1:1mm PLACE_NEAR=C7360.1:3mm PLACE_NEAR=C7340.1:1mm
402 2 2 402
0402
1%
1/16W
1%
1/16W
DDRREG_P1V35_L MF-LF MF-LF C7360, C7361 close to memory
2 402 2 402 C7350 1
Q7319 PLACE_NEAR=U7300.19:3mm PLACE_NEAR=U7300.18:3mm
2
0.22UF
(DDRREG_VDDQSNS)
SSM3K15FV D 3 XW7300
SM
10%
10V
SOD-VESM-HF
CERM 2
CRITICAL 1 402
OMIT_TABLE GND_DDRREG_SGND
1 G S 2 MIN_NECK_WIDTH=0.17 mm
VOLTAGE=0V
B B
MEM_VDD_SEL_1V5_L IN 24
114S0411 1 RES,MTL FILM,1/16W,100K,1,0402,SMD,LF R7316 CRITICAL PPDDR:1V5
114S0391 1 RES,MTL FILM,1/16W,60.4K,1,0402,SMD,LF R7316 CRITICAL PPDDR:1V35
376S0612 1 MOSFET,N-CH,30V,100MA,7.0OHM,SOT-723,HF Q7319 CRITICAL PPDDR:1V5
114S0428 1 RES, MTL FILM,1/16W,150k,0402,SMD,LF R7319 CRITICAL PPDDR:1V5
PAGE TITLE
1.5V DDR3 Supply

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
73 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
=PP5V_S0_CPUIMVP 8 62
R7401
10
PP5V_S0_CPUIMVP_VCC 1 2
D MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V
5%
1/16W
MF-LF =PPVIN_S0_CPUIMVP 8 62
D
402
=PPVCCIO_S0_CPUIMVP
8
1 C7402 1 C7403
C7401 1 2.2UF 2.2UF
20% 20%
2.2UF 2 10V 2 10V
20% X5R-CERM X5R-CERM
10V 402 402
X5R-CERM 2
R74791 1
R7480 402
54.9 130
1% 1%
1/16W 1/16W PLACE_NEAR=U7400.29:2mm
MF-LF MF-LF
402 2 2 402 PLACE_NEAR=U7400.19:2mm
VCC 46
29
19
PLACE_NEAR=U7400.23:2mm PLACE_NEAR=U7400.21:2mm
Note: value needs scrubbing
VDDA
VDDB
R7402 R7406
200
182K 2 1 2 CPUIMVP_ISNS1_P
U7400 1
5%
IN 43 62 78
MAX15119GTM 1% 1/20W
QFN 1/20W MFNO_XNET_CONNECTION=TRUE
62 OUT CPUIMVP_AXG_PWN2 13 DRVPWMB TONB 1 CPUIMVP_TONB MF
R7403 201
201
182K 2 R7407
NC
37 DRVPWMA TONA 48 CPUIMVP_TONA 1
200
1% 1 2 CPUIMVP_ISNS2_P IN 43 62 78
45 CSPA3 BSTA1 25
CRITICAL CPUIMVP_BOOT1 OUT 62 1/20W
MF 5%
72 40 39 11 OUT CPU_PROCHOT_L 4 VRHOT* DHA1 27 CPUIMVP_UGATE1 OUT 62 201 1/20W
C7408 MF
LXA1 26 CPUIMVP_PHASE1 OUT 62 201
220PF
1 C7450 66 OUT CPUIMVP_PGOOD 24 POKA DLA1 28 CPUIMVP_LGATE1 OUT 62
1 2 CPUIMVP_ISUM_R
47PF 9 OUT CPUIMVP_AXG_PGOOD 12 POKB CSPA1 42 CPUIMVP_ISUM1P OUT 62
5%
50V
2 CERM 10%
402 66 IN CPUIMVP_VR_ON 47 EN CSPAAVE 41 CPUIMVP_ISUM 25V
X7R-CERM
21 CSNA 43 CPUIMVP_ISUMN IN 62
0201
72 13 IN CPU_VIDSOUT VDIO
FBA 3 CPUIMVP_FBA
C 72 13 IN CPU_VIDSCLK
CPU_VIDALERT_L
23
22
CLK
CSPA2 44 CPUIMVP_ISUM2P
61
C7409
1000PF R7410
1
C
72 13 IN ALERT* 1 2 1 2
BSTA2 34 CPUIMVP_BOOT2 62
CPUIMVP_NTC 39 OUT 5%
THERMA 32 10%
40 DHA2 CPUIMVP_UGATE2 OUT 62 NO_TEST=TRUE 16V 1/20W
CPUIMVP_NTCG THERMB 33 X7R MF
LXA2 CPUIMVP_PHASE2 OUT 62
201
201
CPUIMVP_SLEW 38 DLA2 31 CPUIMVP_LGATE2
SR OUT 62
CPUIMVP_IMAXA 35 BSTB 14 CPUIMVP_BOOT1G

IMAXA OUT 62
CPUIMVP_IMAXB 36 IMAXB DHB 16 CPUIMVP_UGATE1G 62 CPUIMVP_ISUMG2P 62

OUT IN
1 1 OMIT 15 CPUIMVP_PHASE1G OUT 62
R7468 R7466 1
R7464 1
R7462 1
R7460 8
LXB
18
OUT 62
5.76K 5.76K CSPBAVE DLB CPUIMVP_LGATE1G OUT 62

1% 1% NOSTUFF 196K 301K
1/20W 1/20W NONE 1% 1% 11
MF MF NONE 1/20W 1/20W CSPB2
2 201 2 201 NONE MF MF 9 CPUIMVP_ISUMG1P
2 0201 2 201 2 201 CSPB1 IN 62
10 NO_TEST=TRUE
CSNB
FBB 6 CPUIMVP_FBB 61
NO_TEST=TRUE
GNDSA
GNDSB
PGNDA
PGNDB
THRM
PAD
1 1 AGND
CRITICAL CRITICAL
1 1 1
R7469 R7467 R7465 R7463 R7461
5
20
49
30
17
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF CPUIMVP_ISUMGN 62
100KOHM 100KOHM 200K

1% 1%
137K
1%
137K
XW7400
1 C7418 1 C7419 1 C7414 1 C7415 1 C7416 1 C7423 IN
1/20W 1/20W 1/20W SM 100PF 100PF 100PF 100PF 100PF 100PF

0402 0402 MF MF MF 5% 5% 5% 5% 5% 5%
2 1 25V 25V 25V 25V 25V 25V
2 2 2 201 2 201 2 201 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
201 201 201 201 201 201
GND_CPUIMVP_SGND
PLACE_NEAR=Q7510.1:1mm MIN_NECK_WIDTH=0.2 mm
B PLACE_NEAR=Q7550.1:1mm
VOLTAGE=0V 1 C7440
1000PF
NO_XNET_CONNECTION=TRUE C7413
100PF
NO_XNET_CONNECTION=TRUE B
10%
16V
1 2 1 C7412
2 X7R-CERM
0201
R7440 5% 10%
1000PF
10
CPU_AXG_SENSE_R 1 2 CPU_AXG_SENSE_N IN 13 72
50V
CERM 2 16V
X7R-CERM
5% 0402 R7412 0201 R7413
62 IN CPUIMVP_ISUMG_AVEP 1/20W 8.06K2 10
NO_TEST=TRUE MF CPUIMVP_FBA 1 CPUIMVP_FBA_R 1 2 CPU_VCCSENSE_P
C7441 1 201
61
1% 5%
IN 13 72
1000PF 1/16W 1/20W

NO_XNET_CONNECTION=TRUE10%
16V R7441 MF-LF MF
X7R-CERM 2 402 201
0201 10
CPU_VCCSENSE_R 1 2 CPU_VCCSENSE_N
5%
IN 13 72
1 C7422 NO_XNET_CONNECTION=TRUE
NO STUFF NO STUFF1/20W 1000PF
MF 10%
1 C7442 1 C7443 201 2 16V
X7R-CERM
1000PF
10%
1000PF NO_XNET_CONNECTION=TRUE
10%
R7422 0201 R7423
16.9K2 10
2 16V
X7R 2 16V
X7R 61 CPUIMVP_FBB 1 CPUIMVP_FBB_R 1 2 CPU_AXG_SENSE_P IN 13 72
201 201 1% 5%
PLACE HOLDER PLACE HOLDER 1/16W 1/20W
MF-LF MF
402 201
PAGE TITLE
CPU IMVP7 & AXG VCore Regulator

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
74 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
62 61 8 =PPVIN_S0_CPUIMVP
CPUIMVP_BOOT1_RC THESE TWO CAPS ARE FOR EMC
MIN_LINE_WIDTH=0.25 MM CRITICAL CRITICAL CRITICAL OMIT_TABLE CRITICAL CRITICAL
MIN_NECK_WIDTH=0.2 MM 1
C7513 1 C7515 1 C7516 1 C7517 1 C7518 1 C7519 1
C7510 1
C7512
PHASE 1 DIDT=TRUE
20%
68UF 4.7UF
10%
4.7UF
10%
1.0UF
10%
0.001UF
10%
0.001UF
10%
68UF
20% 20%
68UF
R7511 1 2 16V
POLY-TANT 2 35V
X5R-CERM
35V
2 X5R-CERM 35V
2 CERM-X5R 2 50V
X7R-CERM
50V
2 X7R-CERM 16V
2 POLY-TANT 16V
2 POLY-TANT
0 CASE-D2E-SM 0603 0603 0402 0402 0402 CASE-D2E-SM CASE-D2E-SM
1 C7511
7
8
5% 376S1010 CRITICAL
1/16W 0.22UF PLACE_NEAR=Q7510.1:1mm
MF-LF
402 2 10% D
Q7510 PLACE_NEAR=C7517.1:3mm
10V
2 CERM IRF6802SDTRPBF
61 IN CPUIMVP_BOOT1 402 2 G DIRECTFET-SA PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
MIN_LINE_WIDTH=0.25 MM DIDT=TRUE
CRITICAL
S CRITICAL R7510 138S0812 4 CAP,CER,1UF,10%,35V,X6S,0402,MURATA C7517,C7527,C7557,C7565 CRITICAL
0.00075
L7510 1%
3
D 61 IN CPUIMVP_UGATE1
DIDT=TRUE
GATE_NODE=TRUE
0.36UH-20%-36A-0.00108OHM
1 2 PPVCORE_S0_CPU_PH1
1W
MF
0612
=PPVCORE_S0_CPU_REG 8
D
1 2 62
CPUIMVP_PHASE1 PIMS103T-SM MIN_LINE_WIDTH=0.5

MM 3 4
61 IN
MIN_LINE_WIDTH=0.6 MM DIDT=TRUE NCNC VOLTAGE=1.25V CPUIMVP_ISNS1_N
SWITCH_NODE=TRUE 152S1538 OUT 43 78
MIN_NECK_WIDTH=0.2 MM CPUIMVP_ISNS1_P
OUT 43 61 78
1
2
8
7
61 IN CPUIMVP_LGATE1 NOSTUFF
MIN_LINE_WIDTH=0.5 MM DIDT=TRUE CRITICAL 1 1 1
D
GATE_NODE=TRUE
Q7515 R7599 R7513 R7514
200 46.4 10
649135PBF NO_XNET_CONNECTION=TRUE
1%
1/20W
1%
1/20W
1%
1/20W
4 G DIRECTFET_S3C MF MF MF
376S1011 201 2 201 2 2 201
S
CPUIMVP_ISUMN 61 62
IN
3
5
6
1 C7571
2200PF
10%
2 10V
X7R-CERM
=PPVIN_S0_CPUIMVP 0201
62 61 8
NOSTUFF NOSTUFF CPUIMVP_ISUM1P 61
CPUIMVP_BOOT2_RC THESE TWO CAPS ARE FOR EMC IN
MIN_LINE_WIDTH=0.25 CRITICAL CRITICAL CRITICAL CRITICAL OMIT_TABLE CRITICAL
PHASE 2 DIDT=TRUE
MM 1
C7523
68UF
1
C7524
68UF
1 C7525
4.7UF
10%
1 C7526
4.7UF
10%
1 C7527
10%
1.0UF
1 C7528
0.001UF
10%
1 C7529
0.001UF
10%
1
C7522
68UF
20% 20% 35V 35V 35V 50V 20%
R75211 2 16V
POLY-TANT
16V
2 POLY-TANT 2 X5R-CERM 2 X5R-CERM 2 CERM-X5R 2 X7R-CERM 2 50V
X7R-CERM 2 16V
POLY-TANT
5%
0 1 C7521 CASE-D2E-SM CASE-D2E-SM 0603 0603 0402 0402 0402 CASE-D2E-SM PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
0.22UF
5
6
1/16W CRITICAL PLACE_NEAR=Q7510.1:1mm
MF-LF 10% PLACE_NEAR=C7527.1:3mm 138S0811 4 CAP,CER,4.7UF,10%,25V,X6S,0603 C7515,C7516,C7563,C7564 CRITICAL
402 2 10V 376S1010
2 CERM Q7510
61 IN CPUIMVP_BOOT2 402 D
MIN_NECK_WIDTH=0.2 MM DIDT=TRUE
IRF6802SDTRPBF CRITICAL
1 G DIRECTFET-SA
CRITICAL R7520
0.00075
C 61 IN CPUIMVP_UGATE2
S L7520
0.36UH-20%-36A-0.00108OHM
1%
1W
MF
C
4
MIN_LINE_WIDTH=0.5 MM GATE_NODE=TRUE
0612
MIN_NECK_WIDTH=0.2 MM DIDT=TRUE
1 2 PPVCORE_S0_CPU_PH2 1 2 =PPVCORE_S0_CPU_REG 8 62
CPUIMVP_PHASE2 PIMS103T-SM MIN_LINE_WIDTH=0.5

MM 3 4
61 IN
MIN_LINE_WIDTH=0.6 MM DIDT=TRUE NCNC VOLTAGE=1.25V CPUIMVP_ISNS2_N
SWITCH_NODE=TRUE 152S1538 OUT 43 78
MIN_NECK_WIDTH=0.2 MM CPUIMVP_ISNS2_P
OUT 43 61 78
NOSTUFF
1
2
8
7
61 IN CPUIMVP_LGATE2 CRITICAL CRITICAL
MIN_LINE_WIDTH=0.5 MM DIDT=TRUE
D CRITICAL R75981 R75231 1
R7524 1
C7550 1
C7552
GATE_NODE=TRUE
Q7525 Removed snubber with EMC’s comment 1%
200 46.4
1%
10
1% NO_XNET_CONNECTION=TRUE 68UF 68UF
649135PBF 1/20W
MF
1/20W
MF
1/20W
MF
20%
16V
2 POLY-TANT
20%
2 16V
4 G DIRECTFET_S3C NO_XNET_CONNECTION=TRUE 201 2 201 2 POLY-TANT
2 201 CASE-D2E-SM CASE-D2E-SM
S 376S1011 CPUIMVP_ISUMN 61 62
PLACE_NEAR=U7400.43:1mm IN
1 C7572
2200PF
3
5
6
10%
2 10V
X7R-CERM
0201 CPUIMVP_ISUM2P 61
IN
=PPVIN_S0_CPUAXG NOSTUFF OMIT_TABLE OMIT_TABLE OMIT_TABLE

8
NOSTUFF THESE TWO CAPS ARE FOR EMC
CRITICAL CRITICAL CRITICAL CRITICAL THESE TWO CAPS ARE FOR EMC CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL OMIT_TABLE CRITICAL
1
C7553 1
C7554 1 C7555 1 C7556 1 C7557 1 C7558 1 C7559 1
C7560 1
C7561 1
C7562 1 C7563 1 C7564 1 C7565 1 C7566 1 C7567 1
C7580
5
6
376S1010 CRITICAL
68UF 68UF 4.7UF 4.7UF 1.0UF 0.001UF 0.001UF 68UF 68UF 68UF 4.7UF 4.7UF 1.0UF 0.001UF 0.001UF 68UF
Q7550 20% 20% 10% 10% 10% 10% 10% 20% 20% 20% 10% 10% 10% 10% 10% 20%
D 2 16V
POLY-TANT 2
16V
POLY-TANT 2 35V
X5R-CERM 2 35V
X5R-CERM
35V
2 CERM-X5R 50V
2 X7R-CERM 2 50V
X7R-CERM 16V
2 POLY-TANT 2 16V
POLY-TANT 2
16V
POLY-TANT
35V
2 X5R-CERM 35V
2 X5R-CERM 35V
2 CERM-X5R 50V
2 X7R-CERM 50V
2 X7R-CERM 16V
2 POLY-TANT
CPUIMVP_BOOT1G_RC IRF6802SDTRPBF
CASE-D2E-SM CASE-D2E-SM 0603 0603 0402 0402 0402 CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM 0603 0603 0402 0402 0402 CASE-D2E-SM
MIN_LINE_WIDTH=0.25 1 G DIRECTFET-SA PLACE_NEAR=Q7550.1:1mm
MM PLACE_NEAR=C7557.1:3mm PLACE_NEAR=Q7560.1:1mm
AXG PHASE 1 DIDT=TRUE S
CRITICAL
R7550 CRITICAL
0.00075
B B
4
AXG_PHASE2 AXG_PHASE2
R75511 L7550
7
8
1% CRITICAL
1W CRITICAL CRITICAL
0 0.36UH-20%-36A-0.00108OHM MF 376S1010 Q7550
5%
1/16W
C7551 1
1 2 PPVCORE_S0_AXG_R 1
0612
2 =PPVCORE_S0_AXG_REG
D
IRF6802SDTRPBF
L7560 R7560
MF-LF 0.22UF 8 62 0.36UH-20%-36A-0.00108OHM
10% PIMS103T-SM MIN_LINE_WIDTH=0.5
MM 3 4 2 G DIRECTFET-SA 0.00075
402 2 10V NCNC 1 2 PPVCORE_S0_AXG2_L 1%
CPUIMVP_BOOT1G CERM 2 152S1538 VOLTAGE=1.05V 1W
61 IN 402 S PIMS103T-SM MIN_LINE_WIDTH=0.5
MM MF
MIN_LINE_WIDTH=0.25 MM CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N 0612
1
2
8
7
78 62 43 43 78 152S1538 VOLTAGE=1.05V
DIDT=TRUE OUT OUT 1 2 =PPVCORE_S0_AXG_REG 8
3
MIN_NECK_WIDTH=0.2 MM 62
CRITICAL
61 IN CPUIMVP_UGATE1G
D
Q7551 R75531 1
R7554 78 43 OUT
CPUIMVP_ISNS2G_P 3 4
CPUIMVP_ISNS2G_N
OUT 43 78
MIN_NECK_WIDTH=0.2 MM DIDT=TRUE 46.4 10
MIN_LINE_WIDTH=0.5 MM GATE_NODE=TRUE 649135PBF NO_XNET_CONNECTION=TRUE
1%
1/20W
1% NO_XNET_CONNECTION=TRUE
1/20W
AXG_PHASE2 AXG_PHASE2
4 G DIRECTFET_S3C 1 1
61 IN CPUIMVP_PHASE1G 376S1011
MF
201 2
MF
2 201
NCNC R7561 R7562
MIN_LINE_WIDTH=0.6 MM DIDT=TRUE S 46.4 10
MIN_NECK_WIDTH=0.2 MM SWITCH_NODE=TRUE CPUIMVP_ISUMGN 1% 1%
Removed snubber with EMC’s comment
1
2
8
7
IN 61 62 AXG_PHASE2 1/20W 1/20W
61 IN CPUIMVP_LGATE1G MF MF NO_XNET_CONNECTION=TRUE
DIDT=TRUE CRITICAL 201 2 2 201
MIN_LINE_WIDTH=0.5 MM 1 C7574 D
3
5
6
MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE
Q7561 NO_XNET_CONNECTION=TRUE CPUIMVP_ISUMGN
2200PF OUT 61 62
10% 649135PBF PLACE_NEAR=U7400.10:1mm
2 10V
AXG PHASE 2 CPUIMVP_ISUMG1P
X7R-CERM
0201PLACE_NEAR=U7400.10:1mm
4 G
S
DIRECTFET_S3C
376S1011
1 C7573
2200PF
10%
AXG_PHASE2
61 8
=PP5V_S0_CPUIMVP IN 61
2 10V
X7R-CERM
CPUIMVP_BOOT2G_RC 0201
CPUIMVP_ISUMG2P
3
5
6
MIN_LINE_WIDTH=0.25
MM OUT 61
AXG_PHASE2
AXG_PHASE2 1 C7541 AXG_PHASE2
DIDT=TRUE
1UF CPUIMVP_ISNS1G_P 43 62 78
1 10% OUT
R7540 AXG_PHASE2
2 16V R75421 AXG_PHASE2 AXG_PHASE2
5
10K
5% VDD
X5R
402 5%
0 1 C7542 R75631 1
R7564
1/16W 1/16W 0.22UF 200 200 NO_XNET_CONNECTION=TRUE
MF-LF MF-LF 10% 1% 1%
10V
2 402 U7542 402 2 2 CERM 1/20W 1/20W CPUIMVP_ISUMG_AVEP OUT 61
A 61 CPUIMVP_AXG_PWN2 2 PWN
MAX17491
TQFN BST 1
CPUIMVP_BOOT2G
DIDT=TRUE 402 MF
201 2
MF
2 201 SYNC_MASTER=MASTER SYNC_DATE=MASTER A
IN PAGE TITLE
6
CRITICAL
CPUIMVP_SKIP SKIP* DH 8 CPUIMVP_UGATE2G CPU IMVP7 & AXG VCore Output
1
DIDT=TRUE
GATE_NODE=TRUE
R7566 DRAWING NUMBER SIZE
LX 7 0
CPUIMVP_PHASE2G
DIDT=TRUE
5%
1/20W Apple Inc. <SCH_NUM> D
DL 4 MIN_NECK_WIDTH=0.2 MM SWITCH_NODE=TRUE MF REVISION
GND
THRM CPUIMVP_LGATE2G 2 201 R
<E4LABEL>
PAD
MIN_LINE_WIDTH=0.5 MM DIDT=TRUE CPUIMVP_ISUMG_AVE_RP
NO_TEST=TRUE
MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE NOSTUFF NOTICE OF PROPRIETARY PROPERTY: BRANCH
3
C7568 1 1 C7569 THE INFORMATION CONTAINED HEREIN IS THE

<BRANCH>
1000PF 330PF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
10% 10%
16V
X7R-CERM 2 2 16V
X7R
62 61
CPUIMVP_ISUMGN 0201 201 II NOT TO REPRODUCE OR COPY IT
SHEET
OUT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
CPU VCCIO (1.05V S0) Regulator

138S0812 1 CAP,CER,1UF,10%,35V,X6S,0402,MURATA C7624 CRITICAL
8 =PPVIN_S0_CPUVCCIOS0
8 =PP5V_S0_CPUVCCIOS0
CPUVCCIOS0_VBST_RC
DIDT=TRUE CRITICAL CRITICAL CRITICAL OMIT_TABLE
R7601 1 1 C7601 R7630
1 1
C7620 1
C7621 1
C7626 1 C7622 1 C7624
2.2 10UF 0 68UF 68UF 68UF 0.001UF 1.0UF
5% 20% 5% 20% 20% 20% 20% 10%
1/16W 10V
2 X5R-CERM 1/16W 2 16V 2 16V 2 16V
50V
2 CERM 35V
2 CERM-X5R
MF-LF MF-LF POLY-TANT POLY-TANT POLY-TANT
402 2 0402-1 CASE-D2E-SM CASE-D2E-SM CASE-D2E-SM 0402 0402
2 402
PP5V_S0_CPUVCCIOS0_VCC
1 C7630 PLACE_NEAR=Q7630.2:1mm
72 13 CPU_VCCIOSENSE_P MIN_LINE_WIDTH=0.6 mm CPUVCCIOS0_VBST 1UF PLACE_NEAR=C7624.1:3mm

MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.3 mm 10%
VOLTAGE=5V MIN_NECK_WIDTH=0.2 mm 2 16V
13
14
72 13 CPU_VCCIOSENSE_N DIDT=TRUE
X5R
402
C 1 1
VCC PVCC C
R7604 R7644 U7600 2 CRITICAL
3.01K 3.01K
1%
1/16W
1%
1/16W
ISL95874 Q7630 152S1538 CRITICAL
MF-LF
402 2
MF-LF
=CPUVCCIOS0_EN 3 UTQFN
BOOT 12 CPUVCCIOS0_DRVH RJK0230DPA CRITICAL
R7640
2 402 66 IN EN
MIN_LINE_WIDTH=0.6 mm 0.001
<Ra> CPUVCCIOS0_FB 6 FB
CRITICAL
UGATE 11
MIN_NECK_WIDTH=0.2 mm 1 WPAK L7630 2%
1W
GATE_NODE=TRUE
DIDT=TRUE
0.36UH-20%-36A-0.00108OHM MF
0612
CPUVCCIOS0_SREF 4 SREF PHASE 10 CPUVCCIOS0_LL 7 1 2 PPCPUVCCIO_S0_REG_R 2 1 =PPCPUVCCIO_S0_REG 8
MIN_LINE_WIDTH=0.6 mm MIN_LINE_WIDTH=0.6 mm 4 3
8 MIN_NECK_WIDTH=0.2 mm PIMS103T-SM MIN_NECK_WIDTH=0.2 mm Vout = 1.05V
CPUVCCIOS0_VO VO LGATE 15 SWITCH_NODE=TRUE VOLTAGE=1.05V
DIDT=TRUE
CPUVCCIOS0_OCSET 7 OCSET CPUVCCIOS0_DRVL 6
R7631 C7627 1 C7623 1 20.5A Max Output
MIN_LINE_WIDTH=0.6 mm 270UF 0.001UF
9 MIN_NECK_WIDTH=0.2 mm 2.2 CPUVCCIOS0_SNUB 20%
20% f = 500 kHz
66 OUT CPUVCCIOS0_PGOOD PGOOD GATE_NODE=TRUE 2 1 2V 2
50V
TANT
DIDT=TRUE
5% DIDT=TRUE MIN_LINE_WIDTH=0.6 MM CASE-B2-SM CERM 2
CPUVCCIOS0_RTN 2 RTN 3 4 5 1/10W MIN_NECK_WIDTH=0.2 MM 0402
MF-LF
5 603 NO_TEST=TRUE
1 1
CPUVCCIOS0_FSEL FSEL NOSTUFF C7625 1
R7605 R7645 NOSTUFF
GND PGND NOSTUFF 270UF
2.74K 2.74K 20%
1
R7603 1 C7631
16
1% 1% 2V 2
1/16W
MF-LF
1/16W
MF-LF
C7602 1 0 0.001UF TANT
CASE-B2-SM
402 2 2.2UF 10%
2 402 10% 5%
1/16W 2 50V
<Rb> 16V 2 MF-LF CERM
X5R 402
603 2 402
C7604 1 1 C7605 1 C7603

47PF 47PF 0.047UF
5% 5% 10%
50V
CERM 2
50V
2 CERM 2 16V
X7R-CERM XW7600
SM
402 402 0402
CPUVCCIOS0_AGND 1 2 78 43 CPUVCCIOS0_CS_P
B MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V
R76411
78 43 CPUVCCIOS0_CS_N B
3.48K
1%
1/16W
MF-LF
402 2 C7640
1000PF
2 1
5%
25V 1
NP0-C0G
402
R7642
3.48K
1%
1/16W
MF-LF
(CPUVCCIOS0_OCSET) 2 402
(CPUVCCIOS0_VO)
OCP = R7641 x 8.5uA / R7640

OCP = 26.265A
Vout = 0.5V * (1 + Ra / Rb)
PAGE TITLE
CPUVCCIO (1.05V) Power Supply

DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
76 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1.5V S0 Switcher 1.05V SUS LDO

8 =PP3V3_S0_P1V5S0 Cougar Point requires JTAG pull-ups to be powered at 1.05V in SUS.
D Pull-ups (3) must be 51 ohms to support XDP (not required in production). D
CRITICAL 70mA is required to support pull-ups. Alternative is strong voltage
1
1 C7770 152S1051 dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.
VIN 22UF
20% CRITICAL
U7770 2 6.3V
X5R CRITICAL
ISL8009B 0603 L7770 XDP_PCH
DFN 2.2UH-2A-0.155-OHM =PP1V5_S0_REG
2 EN
8
U7740
66 IN =P1V5S0_EN CRITICAL LX 8 P1V5_S0_SW 1 2 TPS720105
MIN_NECK_WIDTH=0.2 mm 2512 Vout = 1.508V 8 =PP3V3_SUS_P1V05SUSLDO SON =PP1V05_SUS_LDO
66 P1V5S0_PGOOD 3 POR VFB 6 SWITCH_NODE=TRUE
4 BIAS 8
OUT
DIDT=TRUE
C7776 1
1
R7780 Max Current = 1.5A Vout = 1.05V
4 SKIP RSI 5 100K 6 IN OUT 1
47PF 1% Freq = 1.6MHZ
GND THRM_PAD
5%
50V 1/16W 3 EN NC 2
Max Current = 0.35A
CERM 2 MF-LF
CRITICAL NC
7 9 402 2 402 XDP_PCH XDP_PCH
353S2535 P1V5_S0_FB <Ra> 1 C7773 C7740 1 GND
THRM
PAD 1 C7741
22UF
20% 1UF 5 7 2.2UF
2 6.3V
X5R
10%
6.3V 2
10%
1
R7781 0603 CERM 2 6.3V
X5R
113K 402 402
1%
1/16W
MF-LF
2 402
<Rb>
Vout = 0.8V * (1 + Ra / Rb)
Vout = 1.8V
C 1.8V S0 Switcher MAX CURRENT = 2A C
8 =PP3V3_S0_P1V8S0 F = 1MHZ
1 C7760 1 C7761 1 C7768
22UF 0.1UF 1UF
20% 10% 10%
2 6.3V 2 25V 6.3V
2 X5R
X5R
0603
X5R
402 402 U7760 152S1415
PLACE_NEAR=U7760.A3:1mm
MAX15053EWL CRITICAL
WLP
B2 SKIP CRITICAL IN A3
L7760
1.0UH-20%-4.5A-24MOHM
66 =P1V8S0_EN B3 EN LX A2 P1V8S0_SW 1 2 =PP1V8_S0_REG 8
IN
MIN_LINE_WIDTH=0.4 mm PIMB042T-SM
P1V8S0_SS C2 SS/REFIN PGOOD C3 SWITCH_NODE=TRUE 1 1
DIDT=TRUE R7767 R7760 1 C7766
1 C7764 R7765 C1 FB 10K
1% NOSTUFF
20.0K
1% 100PF
0.022UF 3.24K2 P1V8S0_COMP 1/16W 1/16W 5%
50V
1 C7762 1 C7772 1 C7763
10% P1V8_S0_COMP_RC
1 B1 COMP P1V8S0_PGOOD MF-LF MF-LF 2 CERM
16V
2 X5R-X7R-CERM
OUT 66
22UF 22UF 0.1UF
1% NO_TEST=TRUE GND 2 402 2 402 0402 20% 20% 10%
0402 1/16W 2 6.3V 6.3V
2 X5R 2 25V
MF-LF X5R X5R
A1
402 P1V8_S0_RC 0603 0603 402

P1V8SO_FB
1 C7765
1 C7767 1
R7761
100PF 10K
0.0015UF 5%
50V NOSTUFF 1%
10% 2 1/16W
2 50V
X7R-CERM
CERM
402 MF-LF
0402-1 2 402
B B
8 =PP5V_S4_P1V05TBTS0
1.05V TBT S0 Regulator
CRITICAL
C7724 1
C7720 1
1
1000PF 22UF 152S1415

VIN
VDD
10% 20%
16V 6.3V
X7R-CERM 2 X5R 2
0201 0603
L7720
1.0UH-20%-4.5A-24MOHM
U7720 PIMB042T-SM
ISL8014A =PP1V05_S0_P1V05TBTREG_R 8 80
35 IN TBT_EN_LC_ISOL 5 EN
QFN
LX 14 P1V05TBTS0_SW 1 2
15
SWITCH_NODE=TRUE
CRITICAL
Vout = 1.05V
LX DIDT=TRUE
CRITICAL CRITICAL
35 OUT P1V05TBTS0_PGOOD 7 PG Max Current = 3A
8 P1V05TBTS0_FB
1
C7723 1
C7721
VFB 47PF 22UF
4 5% 20%
Freq = 1 MHz
SYNCH
THRM_PAD
16 1 25V 6.3V
NC R7720 2 NP0-C0G-CERM 2 X5R
0201 0603
NC
6
NC 28K
PGND
SGND
1%
13 1/20W
NC MF
201
2
9
10
11
12
17
<Ra>
A CRITICAL
PAGE TITLE
R7721 1 C7722
90.9K
1%
22UF
20%
1
Misc Power Supplies
1/16W 6.3V DRAWING NUMBER SIZE
MF-LF 2
402
2
X5R
0603
<Rb> REVISION
R
<E4LABEL>
Vout = 0.8V * (1 + Ra / Rb) THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
77 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NOSTUFF
R7803
0
1 2
5%
3.3V SUS FET CRITICAL
376S0945 1/16W
Q7820
MF-LF
3.3V S4 FET CRITICAL 402
SIA427DJ
SC70-6L
Q7800
7
SIA427DJ 8 =PP3V3_S5_P3V3SUSFET
D
4
1
SC70-6L =PP3V3_SUS_FET 8
7
8 =PP3V3_S4_P3V3S4FET
D
4
1
1 1
=PP3V3_S4_FET 8 R7822 C7821
G
Q7802 D 3
100K 0.033UF 3.3V SUS FET
10%
5%
16V
1
C7809 1 SSM6N37FEAPE
3
R7802 1/16W
X5R
2
G
SOT563
D Q7802
SSM6N37FEAPE
D 6
220K
5%
0.033UF
10%
16V
3.3V S4 FET
MF-LF
402
2
R7820
402
C7820
0.01UF
MOSFET SiA427
D
3
1/16W 2
X5R
SOT563
MF-LF
402
12K CHANNEL P-TYPE 8V/5V
1 2
402
2 C7800 MOSFET SiA427 5 G S 4
P3V3SUS_EN_L 1 2 P3V3SUS_SS
R7800 0.01UF 66 =P3V3SUS_EN 5% RDS(ON) 26 mOhm @1.8V
IN 10%
5.1K
1 2
CHANNEL P-TYPE 8V/5V 1/16W
16V
2 G S 1
P3V3S4_EN_L 1 2 P3V3S3_S4 MF-LF
X7R-CERM
402
0402
LOADING 100? mA (EDP)
66 =P3V3S4_EN 5% RDS(ON) 26 mOhm @1.8V
IN 1/16W 10%
MF-LF 16V
X7R-CERM
402
0402
LOADING 0.7? A (EDP)
CRITICAL
5V_SUS FET INPUT FILTER 5V SUS FET CRITICAL
Q7840
3.3V S3 FET Q7810 SIA413DJ
SIA427DJ R7843 SC70-6L
SC70-6L 0
7
8 =PP5V_S5_P5VSUSFET 1 2 PP5V_S5_P5VSUSFET_R
7
=PP3V3_S3_P3V3S3FET MIN_LINE_WIDTH=0.5 MM
S
8
D
4
1
NO STUFF MIN_NECK_WIDTH=0.1 MM =PP5V_SUS_FET
S
5% 8
D
1
1
=PP3V3_S3_FET 8 1/16W C7843 VOLTAGE=5V
MF-LF
2.2UF
402
20% Q7842 1
C7841 1
10V R7842
G
1 1
R7812 C7811 PLACE_NEAR=Q7840.4:5mm 2 SSM3K15FV D 3 0.033UF 5V SUS FET
G
X5R-CERM
220K
Q7812 D 6
100K 0.033UF
3.3V S3 FET 402 SOD-VESM-HF 5%
10%
10% 16V
3
5% 1/16W 2
SSM6N37FEAPE 16V X5R
3
1/16W 2 MF-LF
X5R 402
SOT563 MF-LF 402 MOSFET SiA413
402
402
MOSFET SiA427 2 C7840
2 C7810 R7840 0.01UF
R7810 0.01UF 3.3K CHANNEL P-TYPE 12V
1 2
P3V3S3_EN_L
47K
P3V3S3_SS 1 2
CHANNEL P-TYPE 8V/5V 1 G S 2
P5VSUS_EN_L 1 2 P5VSUS_SS
2 G S 1
1 2
=P5VSUS_EN
66 IN 5% RDS(ON) 29 mOhm @4.5V
=P3V3S3_EN 10%
66 IN 5%
10%
RDS(ON) 26 mOhm @1.8V 1/16W
16V
1/16W MF-LF
16V X7R-CERM
MF-LF 402 LOADING 2 mA (EDP)
X7R-CERM 0402
402
0402
LOADING 3 A (EDP)
CRITICAL
5V S3 FET Q7850 3.3V S0 FET CRITICAL

SIA427DJ Q7830
C SC70-6L SI7615DN
PWRPK-1212-8 C
7
8 =PP5V_S4_P5VS3FET
D
4
1
=PP5V_S3_FET 8 =PP3V3_S0_FET 8
S
8 =PP3V3_S0_P3V3S0FET
D
Q7852
2
1 1
5
R7852 C7851
3.3V S0 FET
G
SSM3K15FV D 3 0.033UF
5V S3 FET
1
100K
SOD-VESM-HF 10% 1
C7831 1
R7832
G
5%
16V
3
1/16W 2
X5R 0.033UF
MF-LF
402 D 3
47K MOSFET SI7615DN
MOSFET SiA427 Q7812 10%
4
402 5%
2 C7850 1/16W
16V
2
R7850 0.01UF SSM6N37FEAPE MF-LF
X5R
CHANNEL P-TYPE 20V/12V
402
47K CHANNEL P-TYPE 8V/5V SOT563
402
1 G S P5VS3_EN_L 1 2 P5VS3_SS 1 2 2 C7830
2 R7830 0.01UF RDS(ON) 5.5 mOhm @4.5V
66 =P5VS3_EN 5% RDS(ON) 26 mOhm @1.8V 33K
IN 1/16W 10% P3V3S0_EN_L 1 2 P3V3S0_SS 1 2
16V
MF-LF
X7R-CERM
5 G S 4
LOADING 5.6 A (EDP)
402 LOADING 3 A (EDP) 66 =P3V3S0_EN 5%
0402 IN 1/16W 10%
MF-LF 16V
X7R-CERM
402
0402
1.5V S3/S0 FET

8 =PPVIN_S3_P1V5S3RS0_FET
8 =PP5V_S5_P1V5S3RS0FET
1
C7801 1.5V S3/S0 FET
0.1UF
1
20%
10V
CERM
2 VCC MOSFET SI7108DN
402
5 APN 376S0651
U7801 CHANNEL N-TYPE
SLG5AP020 D
CRITICAL
TDFN RDS(ON) 6 mOhm @4.5V
P1V5CPU_EN 2 ON D 5
Q7801
27 IN
CRITICAL R7801
0 SI7108DN LOADING 5 A (EDP)
B 3 SHDN* G
6
7 P1V5S3RS0FET_GATE 1
5%
2
P1V5S3RS0FET_GATE_R
4 G
S
PWRPK-1212-8-HF
B
NO STUFF S 1/16W
C7802 1 MF-LF
402
1UF 8 1 2 3
10%
PG
10V
2 THRM
X5R
402
GND PAD
4
=PP1V5_S3RS0_FET 8
P1V5S3RS0_RAMP_DONE 9
OUT CRITICAL
Q7860
5.0V S0 FET SI7615DN
PWRPK-1212-8
=PP5V_S0_FET 8
S
3
D
8 =PP5V_S4_P5VS0FET
5.0V S0 FET
5
1
1
R7862
G
C7861 1
MOSFET SI7615DN
220K
0.033UF
4
5%
10%
1/16W
16V
CHANNEL P-TYPE 20V/12V
MF-LF 2
X5R
402
2 402 C7860 RDS(ON) 5.5 MOHM @4.5V
R7860 0.01UF
10K
P5V0S0_EN_L 1 2
1 2 P5V0S0_SS LOADING 5 A (EDP)
5%
1/16W 10%
MF-LF 16V
X7R-CERM
402
Q7865 0402
SSM3K15FV D 3
A SOD-VESM-HF
PAGE TITLE
Power FETs
1 G S 2
DRAWING NUMBER SIZE
66 IN =P5VS0_EN
REVISION
R
<E4LABEL>
<BRANCH>
78 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1.2V, 5V, 3.3V, DDR S3 ENABLE
S5 Rail Enables & PGOOD Mobile System Power State Table
State SMC_ADAPTER_EN SMC_PM_G2_ENABLE SMC_S4_WAKESRC_EN PM_SUS_EN PM_SLP_S5_L PM_SLP_S4_L PM_SLP_S3_L 39 38 36 27 18 7 IN PM_SLP_S4_L
Run (S0) X 1 1 1 1 1 1
Sleep (S3AC) 1 1 1 1 1 1 0 PM_SLP_S4_L:100K pull down in PCH page
2 R7911 2 R7912 2 R7913 2 R7914 2 R7916
5.1K 0
0 0
3.3K
Sleep (S3) 0 1 1 1 1 1 0 5% 5% 5% 5% 5%
59 OUT =P5VS5_EN R7940 1/16W 1/16W 1/16W 1/16W 1/16W
Deep Sleep (S4AC) 1 1 1 0 0 0 0 1 MF-LF 1 MF-LF 1 MF-LF 1 MF-LF 1 MF-LF
SMC_PM_G2_EN 100 402 402 402 402 402
40 39 IN 1 2 P3V3S5_EN =P3V3S5_ENOUT 59 Deep Sleep (S4) 0 1 1 0 0 0 0
MAKE_BASE=TRUE MAKE_BASE=TRUE PLACE_NEAR=Q7812.2:6mm PLACE_NEAR=U4900.K5:6MM
PLACE_NEAR=U4900.K5:6MM
5% Deep Sleep (S5AC) 1 1 0 0 0 0 0
1/16W PLACE_NEAR=U7300.16:6mm PLACE_NEAR=Q7842.2:6MM
MF-LF Deep Sleep (S5) 0 1 0 0 0 0 0 TPAD_VBUS_ENOUT 47
402 1 C7942 toggle 3Hz 0 0 0 0 0 0 P1V2S3_EN
D
0.0033UF
10%
Battery Off (G3HotAC)
Battery Off (G3Hot) 1 0 0 0 0 0 0 P5VS3_EN =P5VS3_EN OUT 65

D
2 50V
CERM MAKE_BASE=TRUE
8 =PP3V42_G3H_PWRCTL 402 P3V3S3_EN =P3V3S3_EN 65
OUT
NO STUFF MAKE_BASE=TRUE
3.3V S4 ENABLE
R79411 DDRREG_EN
MAKE_BASE=TRUE
=DDRREG_EN OUT 60
100K 66 8 =PP3V3_S5_PWRCTL =TBTAPWRSW_EN OUT 69

5%
1/16W PLACE_NEAR=U7940.1:2.3mm
=TBTBPWRSW_EN NO STUFF NO STUFF NO STUFF NO STUFF
MF-LF
402 2 C7970 1 PM_SLP_S5_L:100K pull down on PCH page U7970 OUT 70
1 C7910 1 C7912 1 C7913 1 C7914 1 C7916
0.1uF 6 0.47UF 0.47UF 0.47UF 0.47UF 0.47UF
S5_PWRGD (old name RSMRST_PWRGD)-->SMC 20% PM_SLP_S5_L
2 74LVC1G32 10% 10% 10% 10% 10%
10V 39 18 IN SOT891
59 P3V3S5_PGOOD S5_PWRGD OUT 39 SMC-->PM_DSW_PWRGD CERM 2 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
MAKE_BASE=TRUE 402 4 P5V3V3_S4_EN =P3V3S4_EN OUT 65 402 402 402 402 402
MAKE_BASE=TRUE
1
NC
5 3
NC =P5VS4_EN OUT 47 59
(PM_SLP_S3_R_L) PM_SLP_S3_R_L
SMC_S4_WAKESRC_EN NOSTUFF
40 39 IN MAKE_BASE=TRUE
MAKE_BASE=TRUE R7915 =P5VS0_EN OUT 65
0
1 2 S0 ENABLE =P3V3S0_EN OUT 65
R7987 R7981 R7985 R7988 R7986
2
2
5% R7978 2 2
1/16W
33K 20K 20K 10K 5.1K =PBUSVSENS_ENOUT 44
CPUVCORE ENABLE 3.3V/5.0V Sus ENABLE MF-LF PM_SLP_S3_L 1 100
402 66 39 36 27 18 7 IN
2 5% 5% 5% 5% 5%
1
1/16W
1
1/16W 1/16W 1/16W 1/16W =TBT_S0_EN OUT 69 70
66 8 =PP3V3_S5_PWRCTL 5% MF-LF MF-LF MF-LF MF-LF 1 MF-LF
1
1/16W 402 402 402 402 402
R7974 PLACE_NEAR=U7940.1:2.3mm PM_SLP_S3_L:100K pull down in PCH page MF-LF
402 PLACE_NEAR=U7100.15:6mm PLACE_NEAR=U7600.3:6mm PLACE_NEAR=U7760.B3:6mm
ALL_SYS_PWRGD 1
0 2 CPUIMVP_VR_ON C7940 1 P1V8S0_EN =P1V8S0_EN
66 39 24 OUT 61
0.1uF 5 MAKE_BASE=TRUE
OUT 64
5% PLACE_NEAR=U7400.7:5mm
20%
1/16W 10V CHGR VFRQ Generation
MF-LF CERM 2 VCC
402
402 U7940 8 =PP3V42_G3H_CHGR P1V5S0_EN =P1V5S0_EN OUT 64
74AUP1G3208 57 MAKE_BASE=TRUE
C SMC_BATLOW_L:100K pull up on SMC page
40 39 IN SMC_BATLOW_L 1 A
SOT891
P1V05S0_EN (Replaced by TBT_EN_LC_ISOL) C
R7931
2
CPUVCCIOS0_EN =CPUVCCIOS0_EN
OUT 63
3 B 100K MAKE_BASE=TRUE
5% PVCCSA_EN =PVCCSA_EN OUT 58
PM_SLP_SUS_L:100K pull down on PCH page Y 4 44 PM_SUS_EN =P5VSUS_ENOUT 65 1/16W MAKE_BASE=TRUE
MAKE_BASE=TRUE MF-LF
1
18 IN
PM_SLP_SUS_L 6 402
C =P3V3SUS_EN
OUT 65
GND CHGR_VFRQ 57 PLACE_NEAR=U7100.15:6mm PLACE_NEAR=U7600.3:6mm PLACE_NEAR=U7770.3:6mm PLACE_NEAR=U7760.B3:6mm
2
OUT
1 C7987 1 C7981
1 C7984 1 C7988 1 C7986
=PP3V3_S5_VMON S0 Rail PGOOD (BJT Version) 0.47UF
8
0.47UF 0.47UF 10% 0.47UF 0.47UF
=PP3V3_S0_VMON 10%
6.3V
10%
6.3V 2 6.3V
CERM-X5R
10%
6.3V
10%
6.3V
66 8
1 2 CERM-X5R 2 CERM-X5R 402 2 CERM-X5R 2 CERM-X5R
R7956 NO STUFF Q7931 402 402 402 402
1 150K R7917 SSM3K15FV D 3
R7951 1%
1/16W 0 SOD-VESM-HF
15.0K MF-LF ALL_SYS_PWRGD 24 39 66 1 2
1% 402 2
1/16W 5%
MF-LF S0PGD_C 1/16W
MF-LF
2 402 R7953 402
VMON_3V3_DIV
1
1K 2 VMON_Q2_BASE 1 G S 2
6
5% 3.3V SUS Detect VFRQ Low: Fix Frequency

1
1/16W Q7950
R7952 MF-LF
402 Q1
VFRQ High: Variable Frequency
7.15K 5 ASMCC0179 =PP3V3_S5_PWRCTL
1% Q2
1/16W DFN2015H4-8 66 8
MF-LF R7954 8 =PP3V3_S5_PCHPWRGD
2 402 1K NC
8 PLACE_NEAR=U7930.6:2.3mm =PP3V3_SUS_CNTRL 8 66
=PP3V3_S0_SB_PM PCH S0 PWRGD
66 8 =PP1V5_S3RS0_VMON
1 2 VMON_Q3_BASE
7
Q3
No stuff C7931, 12ms
Min delay time
C7930 1 25 8
0.1uF 1
PP1V5_S3RS0 5%
1/16W 2 CRITICAL U7930 Sense input 20%
10V
R7933 R79501 1 C7950
MF-LF
NC threhold is 3.07V
CERM 2 100K 0.1UF
402 402 5% 1K 20%
1 1/16W 5%
Q4 CRITICAL 6 MF-LF 1/16W 2 10V
CERM
402 2 MF-LF 402
B R7955
VDD 402 2
B
NC
1K 66 8 =PP3V3_SUS_CNTRL 5 SENSE
U7930RESET* 1 PM_RSMRST_L OUT 18
66 8 =PP1V05_S0_VMON
1 2 VMON_Q4_BASE
TPS3808G33DBVRG4 74LVC2G08GT
3
353S2809 8
5% SOT23-6 PM_RSMRST_L goes to U1800.C21 SOT833
1/16W S0PGD_BJT_GND_R Sus_PGOOD_CT
4 CT MR* 3
NC 66 39 24 IN ALL_SYS_PWRGD 1
A 8 74LVC2G08GT
MF-LF SOT833 R7949
402 Worst-Case Thresholds: 1 GND U7950Y 7 PM_S0_PGOOD 5
A
R7957 CPUIMVP_PGOOD 2 08 U7950Y 3 SYS_PWROK_R1 1K 2 PM_PCH_SYS_PWROK
2
Q2: 0.XXXV 100

5%
1 C7931 61 IN B
6 08 5%
OUT 18 24 39
Q3: 0.640V 1/16W 0.001UF 4 B 1/16W

MF-LF 20% MF-LF
3.3V w/Divider: 2.345V 402 2 9 8
=PP3V3_S0_PWRCTL 2 50V
PLACE_NEAR=U1800.P12:7mm
4 402
CERM
Q4: 0.660V 402
R79671 NO STUFF PM_PCH_APWROK OUT 18
NC
10K
5%
S0 Rail PGOOD Circuitry 1/16W
MF-LF R7948
402 2
SMC_DELAYED_PWRGD 1
0 2 PM_PCH_PWROK
(ISL Version in development) R7968 40 39 35
MAKE_BASE=TRUE OUT 18 25
1
100
P1V5S0_PGOOD 2
5%
1/16W
64 IN MF-LF
5% 402
1/16W
Thresholds:
MF-LF R7966 PM_WLAN_EN_L
VDD: 2.734V-3.010V 402 100 2
64 IN P1V8S0_PGOOD 1
V2MON: 2.815V-3.099V =PP3V3_S3_WLAN 8 36
NO STUFF 1/16W
5% "WLAN" = ("S3" && "AP_PWR_EN")
V3MON: 0.572V-0.630V R7965 MF-LF
6 D Q7925
100 402 NOTE: S3 term is guaranteed by S3 pull-up SSM6N15AFE
2
V4MON: 0.572V-0.630V
59 IN P5VS4_PGOOD
1 2 on open-drain AP_PWR_EN signal. SOT563 R7926
66 8 =PP3V3_S0_VMON 5% 10K
1/16W 5%
8 =PP5V_S0_VMON MF-LF 1/16W
S0PGOOD_ISL 402 S G 2 MF-LF
1
=PP1V5_S3RS0_VMON 1 402
S0PGOOD_ISL
66 8
=PP1V05_S0_VMON
C7960 1 PM_WLAN_EN
1 66 8
0.1uF AC_EN_L OUT 36
R7960
S0PGOOD_ISL 20%
R7969
A 6.04K R7970 1 10V 2 S0PGOOD_ISL A
2
7
S0PGOOD_ISL CERM 100 2 R7925
2
1% 1 402 SYNC_MASTER=MASTER SYNC_DATE=MASTER
10K1/16W R7972 VDD 63 CPUVCCIOS0_PGOOD
1 D 3
MF-LF
402 2
1%
1/16W 6.04K
IN
5% Q7920 D 6 NO STUFF
Q7920 D 3 10K Q7925 PAGE TITLE
MF-LF
402 2
1%
1/16W
U7960 1/16W
MF-LF R7963 SSM6N37FEAPE R7929 1
SSM6N37FEAPE
5%
1/16W
SSM6N15AFE
SOT563
Power Control 1/ENABLE
MF-LF ISL88042IRTEZ 402 100 SOT563 0 SOT563 MF-LF DRAWING NUMBER SIZE
1
402 2 TDFN PVCCSA_PGOOD 1 2 5% 402
P5V_DIV_VMON 3 V2MON
(IPU)
MR* 1
58 IN
5%
1/16W
MF-LF Apple Inc. <SCH_NUM> D
CRITICAL NC 1/16W 402 2 5 G S 4 REVISION
S0PGOOD_ISL P1V5_DIV_VMON 5 V3MON MF-LF 24 39 66 2 G S 1 5 G S 4 R
R7961 1
S0PGOOD_ISL P1V05_VID_VMON
6 V4MON RST* 8 S0PGOOD_ISL
402 OUT
<E4LABEL>
15.0K R7971 1 40 39 18 SMC_ADAPTER_EN 66 39 36 27 18 7 PM_SLP_S3_L NOTICE OF PROPRIETARY PROPERTY: BRANCH
IN IN
1% S0PGOOD_ISL R7962
12.4K
1/16W
MF-LF
1
1%
GND THRM_PAD
R7973 330
<BRANCH>
4
402 2 1/16W 15.0K 353S2310 1 2 ALL_SYS_PWRGD THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MF-LF 1%
402 2 1/16W
MF-LF
ALL_SYS_PWRGD_R
5%
1/16W AP_PWR_EN 19 24 36
79 OF 132
MF-LF IN
402 2 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
402
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
LCD PANEL INTERFACE (eDP) CRITICAL

J9000
20525-130E-01
F-RT-SM
31
80 71 7 PPVOUT_S0_LCDBKLT 1
2
NC
71 7 LED_RETURN_6 3
71 7 LED_RETURN_5 4
71 7 LED_RETURN_4 5
71 7 LED_RETURN_3 6
71 7 LED_RETURN_2 7
0 71 7 LED_RETURN_1 8
10 OUT LCD_HPD R9000 1 2 67 7 LCD_HPD_CONN 9
5% 1/20W MF 201 10
9 OUT LCD_FSS
79 9 BI DP_INT_AUX_C_P C9028 1 2
10% 16V
79 67 7 DP_INT_AUX_P 11
0.1UF X5R-CERM
0201 79 67 7 DP_INT_AUX_N 12
79 9 BI DP_INT_AUX_C_N C9029 1 2
10% 16V
13
0.1UF X5R-CERM
0201 14
15
BEAD_PROBE=TRUE 16
DP_INT_ML_C_P<0> C9020 1 2 DP_INT_ML_P<0>
C 79 9 IN
0.1UF 10% 16V
X5R-CERM
0201
79 67
BEAD_PROBE=TRUE
17
18
C
79 9 IN DP_INT_ML_C_N<0> C9021 1 2
10% 16V
79 67 DP_INT_ML_N<0> 19
0.1UF X5R-CERM
0201 20
BEAD_PROBE=TRUE 21
79 9 IN DP_INT_ML_C_P<1> C9022 1 2
10% 16V
79 67 DP_INT_ML_P<1> 22
0.1UF X5R-CERM
0201 23
BEAD_PROBE=TRUE
LCD_PWR_EN
9 IN
79 9 IN DP_INT_ML_C_N<1> C9023 1 2
10% 16V
79 67 DP_INT_ML_N<1> 24
0.1UF X5R-CERM
0201 25
BEAD_PROBE=TRUE
R90101 79 9 IN DP_INT_ML_C_P<2> C9024 1 2 79 67 DP_INT_ML_P<2>
26
27
1K 10% 16V
5% 0.1UF X5R-CERM
0201 28
1/16W BEAD_PROBE=TRUE
MF-LF
402 2 79 9 IN DP_INT_ML_C_N<2> C9025 1 2
10% 16V
79 67 DP_INT_ML_N<2> 29
0.1UF X5R-CERM
0201 30
BEAD_PROBE=TRUE
79 9 IN DP_INT_ML_C_P<3> C9026 1 2
10% 16V
79 67 DP_INT_ML_P<3> 33
0.1UF X5R-CERM
0201 34
BEAD_PROBE=TRUE 35
79 9 IN DP_INT_ML_C_N<3> C9027 1 2
10% 16V
79 67 DP_INT_ML_N<3> 36
CRITICAL 0.1UF X5R-CERM
0201 37
U9000 LCD Panel Current XW Short CRITICAL 38
FPF1009
1 ONMFET-2X2-8IN
EDP: 1 A, Refdes: XW9020
XW9020 L9000 39
SM
FERR-220-OHM 40
8 =PP5V_S0_LCD 2 VIN_1 VOUT_1 4 PP5VR3V3_SW_LCD_ISNS 1 2 PP5VR3V3_SW_LCD_UF 1 2 7 PP5VR3V3_SW_LCD 41
MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm 0805 MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm
3 VIN_2 VOUT_2 5 VOLTAGE=5V VOLTAGE=5V VOLTAGE=5V
32
B GND THRM
PAD 1 C9011 1 C9012 C9001 1 C9002 1 B
C9009 1 0.1UF 0.1UF 518S0829
6 7 0.1UF 10UF 10% 10% C9003 1 C9000 1
0.1UF 10% 20% 16V 16V
10% 2 16V 6.3V
2 X5R X5R-CERM 2 X5R-CERM 2 1000PF 1000PF
16V X7R-CERM 0201 0201 10% 10%
X7R-CERM 2 0402 603 100V 100V
0402 X7R-CERM 2 X7R-CERM 2
0603 0603
NC_ISNS_LCD_PANELN
OUT 7 80
NC_ISNS_LCD_PANELP
OUT 7 80
SM
BP9000 NO_XNET_CONNECTION=TRUE
BEAD-PROBE R9011
1M
1
79 67 DP_INT_ML_P<0> 1 2
SM
8 =PP3V3_S0_LCD NO_XNET_CONNECTION=TRUE BP9001 5%
1/20W
BEAD-PROBE MF R9012
201
LCD Panel HPD & AUX strapping 1M
1
79 67 DP_INT_ML_N<0> 1 2
1
R9003 NO_XNET_CONNECTION=TRUE BP9002 5%
1/20W
1M BEAD-PROBE R9013 MF
201
5% SM
1M 2
1
1/20W
MF 79 67 DP_INT_ML_P<1> 1
2 201 NO_XNET_CONNECTION=TRUE BP9003 5%
1/20W
BEAD-PROBE MF R9014
SM 201
1M
1
79 67 7 DP_INT_AUX_N 79 67 DP_INT_ML_N<1> 1 2
5%
67 7 LCD_HPD_CONN 67 7 DP_INT_AUX_P NO_XNET_CONNECTION=TRUE BP9004 1/20W
79 MF
BEAD-PROBE R9015 201
SM
1M
1
NO_XNET_CONNECTION=TRUE 79 67 DP_INT_ML_P<2> 1 2
5%
A 1
R9001
1M
1
R9002
1M
NO_XNET_CONNECTION=TRUE BP9005 1/20W NO_XNET_CONNECTION=TRUE
MF
201
5% 5%
BEAD-PROBE
SM R9016 PAGE TITLE
1M
1
1/20W 1/20W
MF MF 79 67 DP_INT_ML_N<2> 1 2 eDP Display Connector
2 201 2 201 5% DRAWING NUMBER SIZE
NO_XNET_CONNECTION=TRUE BP9006 1/20W
MF <SCH_NUM> D
BEAD-PROBE
SM R9017 201 Apple Inc. REVISION
1 1M R
79 67 DP_INT_ML_P<3> 1 2 <E4LABEL>
NO_XNET_CONNECTION=TRUE BP9007 5%
1/20W TRUE
BEAD-PROBE
SM
MF
201 R9018 THE INFORMATION CONTAINED HEREIN IS THE
<BRANCH>
1M
1

DP_INT_ML_N<3> 1 2
79 67
5%
90 OF 132
1/20W
NO_XNET_CONNECTION=TRUE SHEET
MF III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
201 IV ALL RIGHTS RESERVED 67 OF 80
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
8 =PP3V3_S0_DDCMUX
R9251 R9252 R9253 R9254

DDC Crossbar 1
2.2K
1
2.2K
1
2.2K
1
2.2K
Only necessary on dual-port hosts. 1% 1% 1% 1%
1/20W 1/20W 1/20W 1/20W
On single-port hosts alias TBTPA_DDC to TBTSNK0_DDC. MF MF MF MF
NEVER SEND AUXCH THROUGH CROSSBAR! 2 201 2 201 2 201 2 201
VCC 13
1 C9280
0.1UF
20%
10V
2 CERM
402
U9200
16
TS3DS10224
ENA QFN
CRITICAL
C 69
69
OUT DP_TBTPA_DDC_CLK
DP_TBTPA_DDC_DATA
1
2
INA+
INA-
OUTA1+ 20
OUTA1- 19
C
BI
OUTA0+ 18 DP_TBTSNK0_DDC_CLK IN 9
OUTA0- 17 DP_TBTSNK0_DDC_DATA BI 9
14 SAI SAO 15
10 ENB
70 DP_TBTPB_DDC_CLK 3 INB+ OUTB1+ 6

OUT
70 DP_TBTPB_DDC_DATA 4 INB- OUTB1- 7
BI
OUTB0+ 8 DP_TBTSNK1_DDC_CLK IN 9
OUTB0- 9 DP_TBTSNK1_DDC_DATA BI 9
33 TBT_DDC_XBAR_EN_L 12 SBI SBO 11

IN
THRM
PAD
5GND
21
SAI/SBI = 1: INA == OUTA0, INB == OUTB0
SAI/SBI = 0: INA == OUTB0, INB == OUTA0
B B
PAGE TITLE
DDC Crossbar
DRAWING NUMBER SIZE

REVISION
R
<E4LABEL>
<BRANCH>
92 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PP3V3_SW_TBTAPWR
69
138S0811 1 CAP,CER,4.7UF,10%,25V,X5R,0603,MURATA C9415 CRITICAL
C9420 1 C9421 1 1
R9427 R94291
3.3V/HV Power MUX 0.1UF
10%
16V
0.1UF
10%
16V
10K
5%
100K
5%
X5R-CERM 2 X5R-CERM 2 1/20W 1/20W
15
0201 0201 MF MF
3
V3P3 must be S4 to support
2 201 201 2
wake from Thunderbolt devices. VDD TBT_A_BIAS 69
=PP3V3_S4_TBTAPWRSW CRITICAL VOLTAGE=3.3V

8
U9420
D IV3P3
Nominal
1100mA
Min
1030mA
Max
1200mA SIGNAL_MODEL=TBT_MUX
CBTL05023
HVQFN
1 C9425
0.1UF
D
CRITICAL CRITICAL TBT_A_CIO_SEL 1 BIASIN 24 10%
IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum) BIASOUT
C9487 1 C9480 1 1 C9481 33 IN
2 16V
X5R-CERM
100UF 22UF 0.1UF IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
70 25 IN DP_AUXIO_EN 2 AUXIO_EN 0201
20% 20% 10%
6.3V
POLY-TANT 2
6.3V
X5R-CERM-1 2
16V
2 X5R-CERM
PP3V3_SW_TBTAPWR DP_TBTPA_AUXCH_C_N
C9430 1 2
DP_TBTPA_AUXCH_N 7 AUX-
603 0201 69 76 33 BI 10% 16V 76
CASE-B2-SM MIN_LINE_WIDTH=0.38 MM 0.1UF X5R-CERM
0201 8 AUX+ 23
19 V3P3OUT 18 MIN_NECK_WIDTH=0.20 MM DP_TBTPA_AUXCH_C_P 76 DP_TBTPA_AUXCH_P AUXIO- DP_A_AUXCH_DDC_N
20 V3P3 VOLTAGE=3.3V
76 33 BI C9431 1 2
10% 16V AUXIO+ 22 DP_A_AUXCH_DDC_P
69 76
69 76
8 =PPHV_SW_TBTAPWRSW 12 PPHV_SW_TBTAPWR 0.1UF X5R-CERM
0201 68 DP_TBTPA_DDC_DATA 4 DDC_DAT
BI
OUT MIN_LINE_WIDTH=0.38 MM 5 DDC_CLK TBT: RX_1 Bias Sink
18.9V Max 6 14 MIN_NECK_WIDTH=0.20 MM 68 IN DP_TBTPA_DDC_CLK
7 VHV VOLTAGE=15V
OMIT_TABLE 1 C9415 C9410 1 CRITICAL
C9485 1 1 C9486 1C9411 33 OUT TBT_A_CONFIG1_BUF 16 CA_DETOUT CA_DET 18 TBT_A_CONFIG1_RC 69
4.7UF 0.1UF
0.1UF 10UF 0.1UF C9432 1 2
10% 10% U9410 10%
16V
20%
2 6.3V
10%
2 25V
76 33 IN DP_TBTPA_ML_C_P<1>
0.22UF 20% 6.3V 76 DP_TBTPA_ML_P<1> 11 DP+
2 25V 25V 2 CD3210A0RGP X5R-CERM 2 CERM-X5R X5R DP_TBTPA_ML_C_N<1> X5R 0201
76 DP_TBTPA_ML_N<1> 10 DP- DPMLO+ 19 DP_A_LSX_ML_P<1>
X5R-CERM
0603
X5R
402 QFN 0201 0402 402 76 33 IN C9433 1 2
20% 6.3V DPMLO- 20 DP_A_LSX_ML_N<1>
69 76
69 76
16 RSVD RSVD 15 0.22UF X5R 0201 33 TBT_A_LSTX 14 LSTX
IN
13 LSRX TBT: LSX_A_R2P/P2R (P/N)
69 PP3V3_SW_TBTAPWR TBT_A_LSRX_UNBUF
66 IN =TBTAPWRSW_EN 5 EN ISET_V3P3 8 7 TBTAPWRSW_ISET_V3P3
CRITICAL TBT_A_DP_PWRDN 6 DP_PD
33 IN
35 IN TBT_A_HV_EN_RC 11 HV_EN ISET_S0 10 7 TBTAPWRSW_ISET_S0 U9460
74AUP1T97 33 DP_TBTPA_HPD 12 HPDOUT HPD 17 TBT_A_HPD 69
=TBT_S0_EN 17 S0 TBTAPWRSW_ISET_S3 SOT891 5 OUT
70 66 IN ISET_S3 9 7
VCC
TBTHV:P15V TBTHV:P15V TBT_A_LSRX 4 Y 1 GND THMPAD 1
GND THRM 33 OUT A 3 R9426 R9428
PAD R94101 1
R9411 1
R9412
9
21
25
12V: See Y = B 1M 100K
1
2
3
4
13
21
22.6K 22.6K 36.5K B 1 5% 5%
below 1%
1/20W
1%
1/20W
1%
1/20W
1 C9460 1/20W
MF
1/20W
MF
MF MF MF 0.1UF C 6 201 2
201 2 10% 2 201
2 201 2 201 2 16V GND
TBTAPWRSW_ISET_S3_R
7 <RV3P3> X5R-CERM
0201 2
TBTAPWRSW_ISET_S0_R
TBTHV:P15V TBTHV:P15V
C R94131 1
R9414 Single-fault protection
C
22.6K 22.6K requires two R’s per HV
1% 1% ISET_Sx with CD3210.
1/20W 1/20W Single R on ISET_V3P3 OK.
MF MF
201 2 2 201 L9400 Thunderbolt Connector A
<RHVS3> <RHVS0> ILIM = 40000 / RISET FERR-120-OHM-3A
For 12V systems: TBTACONN_1_C
1 2 MIN_LINE_WIDTH=0.38 MM
PP3V3RHV_SW_TBTAPWR MIN_NECK_WIDTH=0.20 MM
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 0603 MIN_LINE_WIDTH=0.38 MM VOLTAGE=18.9V
VOLTAGE=15V
118S0145 2 RES,MTL FILM,1/16W,17.8K,1,0201,SMD,LF R9410,R9413 TBTHV:P12V C9400 1 R9401
0.01UF 12 GND_VOID=TRUE
118S0145 2 RES,MTL FILM,1/16W,17.8K,1,0201,SMD,LF R9411,R9414 TBTHV:P12V 10% TBTACONN_20_RC 1 2
50V
X7R-CERM 2 MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM 5%
C9405 1
0402 VOLTAGE=18V 1/20W 0.01UF
Nominal Min Max
1 C9401 MF
201
10%
25V
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)
0.01UF For J9400 TBT SMT pads
(3, 5, 17 & 19):
X5R-CERM 2 GND_VOID=TRUE
10% 0201 (Both C’s)

GND_VOID=TRUE 50V
2 X7R-CERM
(Both C’s) 0402
(0-18.9V)
C9470 1 2
TBT_A_R2D_C_P<0>
C9474 2 1 TBT Dir DP Dir DP Dir TBT Dir
76 7 TBT_A_R2D_P<0> 0.22UF 20%
X5R
6.3V
0201
IN 7 33 76
TBT_A_D2R_P<0> 0.47UF 20% 4V TBT_A_D2R_C_P<0> TBT_A_R2D_C_N<0>

76 33 7 OUT 76 7
TBT_A_R2D_N<0> C9471 1 2 IN 7 33 76
S16
S15
S14
S13
S12
CERM-X5R-1
201 76 7
76 33 7 OUT TBT_A_D2R_N<0> C9475 1 2
76 7 TBT_A_D2R_C_N<0> CRITICAL 20% 6.3V
TBT: TX_0 TBTACONN_7_C 0.22UF X5R 0201
0.47UF 20% 4V GND_VOID=TRUE GND_VOID=TRUE MIN_LINE_WIDTH=0.38 MM GND_VOID=TRUE
CERM-X5R-1
201 SHIELD PINS MIN_NECK_WIDTH=0.20 MM
GND_VOID=TRUE
R94941 1
R9495 J9400
VOLTAGE=18.9V GND_VOID=TRUE
1
GND_VOID=TRUE
1
1K 1K GND_VOID=TRUE
R9470 R9471
5% 5% MDP-D1
1/20W
MF
1/20W
MF B2 F-RT-TH GND0 B1 C9406 1 470K
5%
470K
5%
201 2 HPD 0.01UF
2 201 B4 ML_LANE0P B3 10% 1/20W
MF
1/20W
MF
CONFIG1 25V
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE
B6 ML_LANE0N B5 X5R-CERM 2 2 201 2 201
R9478 470K 1 2
B8
CONFIG2
B7
0201
5% 1/20W GND1
DP_TBTPA_ML_C_P<3>
C9478 1 2
20% 6.3V DP_TBTPA_ML_P<3> MF 201 B10
GND2
B9 (0-18.9V)
DP_A_LSX_ML_P<1>
ML_LANE3P ML_LANE1P
76 33 76 69 76
IN 0.22UF X5R 0201
B 76 33 IN DP_TBTPA_ML_C_N<3>
C9479 1 2
20% 6.3V
76 DP_TBTPA_ML_N<3> B12
B14
ML_LANE3N ML_LANE1N
GND3
B11
B13
DP_A_LSX_ML_N<1> 69 76
B
0.22UF X5R 0201
TBT: Unused
R9479 470K 1 2
B16
GND4
B15 TBT: LSX_R2P/P2R (P/N)
5% 1/20W AUX_CHP ML_LANE2P
MF 201
69 TBT_A_BIAS B18
AUX_CHN ML_LANE2N B17
B20 RETURN B19
DP_PWR
R94981 1
R9499 PORT B GND_VOID=TRUE
2.2K 2.2K CRITICAL SHIELD PINS (Both C’s)

5% 5%
GND_VOID=TRUE 1/20W
MF
1/20W
MF
SIGNAL_MODEL=TBTPIN
GND_VOID=TRUE C9472 1 2
20% 6.3V TBT_A_R2D_C_P<1> 7 33 76
IN
S24
S22
S21
S20
S19
S18
S17
(Both C’s) 201 2 2 201 (Both D’s) 0.22UF X5R 0201
C9476 D9498 TBT_A_R2D_P<1> TBT_A_R2D_C_N<1>
TBT_A_D2R_P<1> 0.47UF
2 1 GND_VOID=TRUE GND_VOID=TRUE
TBT_A_D2R_C_P<1>
A K
TBT_A_D2R1_AUXDDC_P
76 7
TBT_A_R2D_N<1>
C9473 1 2 IN 7 33 76
76 33 7 OUT 20%
CERM-X5R-1
4V
201
BAR90-02LRH TSLP-2-7 76 76 7
0.22UF 20% 6.3V
X5R 0201
76 33 7 OUT TBT_A_D2R_N<1> C9477 1 2 TBT_A_D2R_C_N<1> D9499 A K 76 TBT_A_D2R1_AUXDDC_N GND_VOID=TRUE
TBT: TX_1
0.47UF 20% 4V BAR90-02LRH TSLP-2-7 GND_VOID=TRUE GND_VOID=TRUE
CERM-X5R-1
201 1 1
CRITICAL
514-0836 R9472 R9473
470K 470K
GND_VOID=TRUE
L9498 5%
1/20W
5%
1/20W
650NH-5%-0.430MA-0.52OHM MF MF
76 69 DP_A_AUXCH_DDC_P 2 1 GND_VOID=TRUE
2 201 2 201
76 69 DP_A_AUXCH_DDC_N 0603
CRITICAL 470k R’s for ESD protection

C9498 1 1 C9499 L9499 on AC-coupled signals.
30PF 30PF 650NH-5%-0.430MA-0.52OHM
5% 5%
25V 25V
C0G-CERM 2 2 C0G-CERM 2 1
0201 0201 GND_VOID=TRUE
0603
A 69 TBT_A_HPD
TBT_A_CONFIG1_RC DP Source must pull
PAGE TITLE
69
C9402 1 Thunderbolt Connector A
33 OUT TBT_A_CONFIG2_RC 0.01UF down HPD input with
10% greater than or equal DRAWING NUMBER SIZE
16V
X5R-CERM 2 to 100K (DPv1.1a). <SCH_NUM> D
R9452 1 1
R9451 C9494 1 1 C9495
1
R9441 0201 Apple Inc. REVISION
1M 1M 330PF 330PF 100K R
5%
1/20W
5%
1/20W 10% 10% 5%
1/20W
Sink HPD range: <E4LABEL>
MF MF 16V 2 16V NOTICE OF PROPRIETARY PROPERTY:
201 2 X7R-CERM 2 X7R-CERM MF High: 2.0 - 5.0V BRANCH
2 201 0201 0201 2 201 Low: 0 - 0.8V THE INFORMATION CONTAINED HEREIN IS THE <BRANCH>
94 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION PP3V3_SW_TBTBPWR
70
138S0811 1 CAP,CER,4.7UF,10%,25V,X5R,0603,MURATA C9615 CRITICAL
C9620 1 C9621 1 1
R9627 R96291
3.3V/HV Power MUX 0.1UF
10%
0.1UF
10% 10K
5%
100K
5%
16V 16V
X5R-CERM 2 X5R-CERM 2 1/20W 1/20W
15
0201 0201 MF MF
3
V3P3 must be S4 to support
2 201 201 2
wake from Thunderbolt devices. VDD TBT_B_BIAS 70
=PP3V3_S4_TBTBPWRSW CRITICAL VOLTAGE=3.3V

8
U9620
D IV3P3
Nominal
1100mA
Min
1030mA
Max
1200mA
SIGNAL_MODEL=TBT_MUX CBTL05023
HVQFN
1 C9625
0.1UF
D
CRITICAL CRITICAL TBT_B_CIO_SEL 1 BIASIN 24 10%
IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum) BIASOUT
C9687 1 C9680 1 1 C9681 33 IN
2 16V
X5R-CERM
100UF 22UF 0.1UF IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)
69 25 IN DP_AUXIO_EN 2 AUXIO_EN 0201
20% 20% 10%
6.3V
POLY-TANT 2
6.3V
X5R-CERM-1 2
16V
2 X5R-CERM
PP3V3_SW_TBTBPWR DP_TBTPB_AUXCH_C_N
C9630 1 2
DP_TBTPB_AUXCH_N 7 AUX-
603 0201 70 76 33 BI 10% 16V 76
CASE-B2-SM MIN_LINE_WIDTH=0.38 MM 0.1UF X5R-CERM
0201 8 AUX+ 23
19 V3P3OUT 18 MIN_NECK_WIDTH=0.20 MM DP_TBTPB_AUXCH_C_P 76 DP_TBTPB_AUXCH_P AUXIO- DP_B_AUXCH_DDC_N
20 V3P3 VOLTAGE=3.3V
76 33 BI C9631 1 2
10% 16V AUXIO+ 22 DP_B_AUXCH_DDC_P
70 76
70 76
8 =PPHV_SW_TBTBPWRSW 12 PPHV_SW_TBTBPWR 0.1UF X5R-CERM
0201 68 DP_TBTPB_DDC_DATA 4 DDC_DAT
BI
OUT MIN_LINE_WIDTH=0.38 MM 5 DDC_CLK TBT: RX_1 Bias Sink
18V Max 6 14 MIN_NECK_WIDTH=0.20 MM 68 IN DP_TBTPB_DDC_CLK
7 VHV VOLTAGE=15V
OMIT_TABLE 1 C9615 C9610 1 CRITICAL
C9685 1 1 C9686 1C9611 33 OUT TBT_B_CONFIG1_BUF 16 CA_DETOUT CA_DET 18 TBT_B_CONFIG1_RC 70
4.7UF 0.1UF
0.1UF 10UF 0.1UF C9632 1 2
10% 10% U9610 10%
16V
20%
2 6.3V
10%
2 25V
76 33 IN DP_TBTPB_ML_C_P<1>
0.22UF 20% 6.3V 76 DP_TBTPB_ML_P<1> 11 DP+
2 25V 25V 2 CD3210A0RGP X5R-CERM 2 CERM-X5R X5R DP_TBTPB_ML_C_N<1> X5R 0201
76 DP_TBTPB_ML_N<1> 10 DP- DPMLO+ 19 DP_B_LSX_ML_P<1>
X5R-CERM
0603
X5R
402 QFN 0201 0402 402 76 33 IN C9633 1 2
20% 6.3V DPMLO- 20 DP_B_LSX_ML_N<1>
70 76
70 76
16 RSVD RSVD 15 0.22UF X5R 0201 33 TBT_B_LSTX 14 LSTX
IN
13 LSRX TBT: LSX_A_R2P/P2R (P/N)
70 PP3V3_SW_TBTBPWR TBT_B_LSRX_UNBUF
66 IN =TBTBPWRSW_EN 5 EN ISET_V3P3 8 7 TBTBPWRSW_ISET_V3P3
CRITICAL TBT_B_DP_PWRDN 6 DP_PD
33 IN
35 IN TBT_B_HV_EN_RC 11 HV_EN ISET_S0 10 TBTBPWRSW_ISET_S0 U9660
74AUP1T97 33 DP_TBTPB_HPD 12 HPDOUT HPD 17 TBT_B_HPD 70
=TBT_S0_EN 17 S0 TBTBPWRSW_ISET_S3 SOT891 5 OUT
69 66 IN ISET_S3 9 7
VCC
TBTHV:P15V TBTHV:P15V TBT_B_LSRX 4 Y 1 GND THMPAD 1
GND THRM 33 OUT A 3 R9626 R9628
PAD R96101 1
R9611 1
R9612
9
21
25
12V: See Y = B 1M 100K
1
2
3
4
13
21
22.6K 22.6K 36.5K B 1 5% 5%
below 1%
1/20W
1%
1/20W
1%
1/20W
1 C9660 1/20W
MF
1/20W
MF
MF MF MF 0.1UF C 6 201 2
201 2 10% 2 201
2 201 2 201 2 16V GND
TBTBPWRSW_ISET_S3_R <RV3P3> X5R-CERM
0201 2
TBTBPWRSW_ISET_S0_R
7
TBTHV:P15V TBTHV:P15V
C R96131 1
R9614 Single-fault protection
C
22.6K 22.6K requires two R’s per HV
1% 1% ISET_Sx with CD3210.
1/20W 1/20W Single R on ISET_V3P3 OK.
MF MF
201 2 2 201 L9600 Thunderbolt Connector B TBTBCONN_1_C
<RHVS3> <RHVS0> ILIM = 40000 / RISET FERR-120-OHM-3A MIN_LINE_WIDTH=0.38 MM
For 12V systems: MIN_NECK_WIDTH=0.20 MM
1 2 VOLTAGE=18.9V
PP3V3RHV_SW_TBTBPWR GND_VOID=TRUE
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 0603 MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V
C9605 1
C9600 1 0.01UF
118S0145 2 RES,MTL FILM,1/16W,17.8K,1,0201,SMD,LF R9610,R9613 TBTHV:P12V 0.01UF
R9601 10%
25V
10% 12 X5R-CERM 2
50V TBTBCONN_20_RC 1 2
0201
118S0145 2 RES,MTL FILM,1/16W,17.8K,1,0201,SMD,LF R9611,R9614 TBTHV:P12V X7R-CERM 2 MIN_LINE_WIDTH=0.38 MM
5%
0402 MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V 1/20W
Nominal Min Max
1 C9601 MF
201
IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)
0.01UF For J9600 TBT SMT pads
(3, 5, 17 & 19):
GND_VOID=TRUE
10% (Both C’s)

GND_VOID=TRUE 50V
2 X7R-CERM
(Both C’s) 0402
(0-18.9V)
C9670 1 2
TBT_B_R2D_C_P<0>
C9674 2 1 TBT Dir DP Dir DP Dir TBT Dir
76 7 TBT_B_R2D_P<0> 0.22UF 20%
X5R
6.3V
0201
IN 7 33 76
TBT_B_D2R_P<0> 0.47UF 20% 4V TBT_B_D2R_C_P<0> TBT_B_R2D_C_N<0>

76 33 7 OUT
TBT_B_D2R_N<0> CERM-X5R-1
201
76 7
TBT_B_D2R_C_N<0>
76 7 TBT_B_R2D_N<0> C9671 1 2 IN 7 33 76
S5
S4
S3
S2
S1
76 33 7 OUT C9675 1 2
76 7
CRITICAL TBT: TX_0 TBTBCONN_7_C 0.22UF 20%
X5R
6.3V
0201
0.47UF 20% 4V GND_VOID=TRUE GND_VOID=TRUE MIN_LINE_WIDTH=0.38 MM GND_VOID=TRUE
CERM-X5R-1
201 SHIELD PINS MIN_NECK_WIDTH=0.20 MM
GND_VOID=TRUE R96941 1
R9695 J9400
VOLTAGE=18.9V
GND_VOID=TRUE
GND_VOID=TRUE
1
GND_VOID=TRUE
1
1K 1K R9670 R9671
5%
1/20W
5%
1/20W MDP-D1 C9606 1
470K 470K
MF MF A2 F-RT-TH GND0 A1 0.01UF 5% 5%
201 2 HPD 10%
2 201 A4 ML_LANE0P A3 25V 1/20W 1/20W
CONFIG1 X5R-CERM 2 MF MF
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE
A6 ML_LANE0N A5 0201 2 201 2 201
R9678 470K 1 2
A8
CONFIG2
A7
5% 1/20W GND1
DP_TBTPB_ML_C_P<3>
C9678 1 2
20% 6.3V DP_TBTPB_ML_P<3> MF 201 A10
GND2
A9 (0-18.9V)
DP_B_LSX_ML_P<1>
76 33 IN 0.22UF X5R 0201
76
ML_LANE3P ML_LANE1P 70 76
B 76 33 IN DP_TBTPB_ML_C_N<3>
C9679 1 2
20% 6.3V
76 DP_TBTPB_ML_N<3> A12
A14
ML_LANE3N ML_LANE1N
GND3
A11
A13
DP_B_LSX_ML_N<1> 70 76
B
0.22UF X5R 0201
TBT: Unused
R9679 470K 1 2
A16
GND4
A15 TBT: LSX_R2P/P2R (P/N)
5% 1/20W AUX_CHP ML_LANE2P
MF 201
70 TBT_B_BIAS A18
AUX_CHN ML_LANE2N A17
A20 RETURN A19
DP_PWR
R96981 1
R9699 PORT A GND_VOID=TRUE
2.2K 2.2K CRITICAL SHIELD PINS (Both C’s)

5% 5%
GND_VOID=TRUE
1/20W
MF
1/20W
MF
SIGNAL_MODEL=TBTPIN
GND_VOID=TRUE C9672 1 2
20% 6.3V TBT_B_R2D_C_P<1> 7 33 76
IN
S23
S11
S10
S9
S8
S7
S6
(Both C’s) 201 2 2 201 (Both D’s) 0.22UF X5R 0201
C9676 D9698 TBT_B_R2D_P<1> TBT_B_R2D_C_N<1>
TBT_B_D2R_P<1> 0.47UF
2 1 GND_VOID=TRUE GND_VOID=TRUE
TBT_B_D2R_C_P<1>
A K
TBT_B_D2R1_AUXDDC_P
76 7
TBT_B_R2D_N<1>
C9673 1 2 IN 7 33 76
76 33 7 OUT 20% 4V
201
CERM-X5R-1
BAR90-02LRH TSLP-2-7 76
514-0836
76 7
0.22UF 20% 6.3V
X5R 0201
76 33 7 OUT TBT_B_D2R_N<1> C9677 1 2 TBT_B_D2R_C_N<1> D9699 A K 76 TBT_B_D2R1_AUXDDC_N GND_VOID=TRUE
TBT: TX_1
0.47UF 20% 4V BAR90-02LRH TSLP-2-7 GND_VOID=TRUE GND_VOID=TRUE
CERM-X5R-1
201 GND_VOID=TRUE
1 1
GND_VOID=TRUE
CRITICAL R9672 R9673
470K 470K
L9698 5%
1/20W
5%
1/20W
650NH-5%-0.430MA-0.52OHM MF MF
76 70 DP_B_AUXCH_DDC_P 2 1 GND_VOID=TRUE
2 201 2 201
76 70 DP_B_AUXCH_DDC_N 0603
CRITICAL 470k R’s for ESD protection

C9698 1 1 C9699 L9699 on AC-coupled signals.
30PF 30PF 650NH-5%-0.430MA-0.52OHM
5% 5%
25V 25V
C0G-CERM 2 2 C0G-CERM 2 1
0201 0201 GND_VOID=TRUE
0603
A 70 TBT_B_HPD
TBT_B_CONFIG1_RC DP Source must pull
PAGE TITLE
70
C9602 1 Thunderbolt Connector B
33 OUT TBT_B_CONFIG2_RC 0.01UF down HPD input with
10% greater than or equal DRAWING NUMBER SIZE
16V
X5R-CERM 2 to 100K (DPv1.1a). <SCH_NUM> D
R9652 1 1
R9651 C9694 1 1 C9695
1
R9641 0201 Apple Inc. REVISION
1M 1M 330PF 330PF 100K R
5%
1/20W
5%
1/20W 10% 10% 5%
1/20W
Sink HPD range: <E4LABEL>
MF MF 16V 2 16V NOTICE OF PROPRIETARY PROPERTY:
201 2 X7R-CERM 2 X7R-CERM MF High: 2.0 - 5.0V BRANCH
2 201 0201 0201 2 201 Low: 0 - 0.8V THE INFORMATION CONTAINED HEREIN IS THE <BRANCH>
96 OF 132
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PPBUS S0 LCDBkLT FET
MOSFET FDC638APZ
CHANNEL P-TYPE
RDS(ON) 43 mOhm @4.5V

CRITICAL
Q9706 LOADING 0.715 A (EDP)
FDC638APZ_SBMS001
SSOT6-HF PPBUS_SW_LCDBKLT_PWR 80
F9700 MIN_LINE_WIDTH=0.4 mm
1 2 5 6
MIN_NECK_WIDTH=0.25 THERE
mm IS A SENSE RESISTOR BETWEEN
3AMP-32V-467 VOLTAGE=12.6V
PPBUS_SW_LCDBKLT_PWR NEED VALUE CHANGES FOR 55V AND 96 LEDS !!!
D
4
=PPBUS_S0_LCDBKLT 1 2 PPBUS_S0_LCDBKLT_FUSED
D 8
603-HF
VOLTAGE=12.6V
AND PPBUS_SW_BKL
ON THE SENSOR PAGE
BOTTOM 1
R9788 C9782 1
301K 0.1UF
10%
3
1% 16V
1/16W X7R-CERM 2
MF-LF 0402
2 402
8 =PP5V_S0_BKL *L9710, Q9701, D9701, C9715-C9719 SHOULD ALL BE PLACED NEAR EACH OTHER.
LCDBKLT_EN_DIV
1
R9789 CRITICAL CRITICAL C9715, C9716 SHOULD BE PLACED IN T-BONE. SAME FOR C9718,C9719
147K
1%
1/16W
L9710 NEED TO BE CHANGED TO 371S0704
D9701 C9715, C9716 SHOULD BE PLACED ON TOP SIDE. PLACE C9718,C9719 ON BOTTOM SIDE
MF-LF 22UH-20%-2.4A-0.105OHM POWERDI-123
2 402 71 8 PPBUS_S0_LCDBKLT_PWR PLACE_NEAR=L9710.1:5MM PLACE_NEAR=L9710.1:3MM VOLTAGE=12.6V 1 2 PPBUS_S0_LCDBKLT_PWR_SW A K PLACE_NEAR=D9701.2:5MM PLACE_NEAR=D9701.2:5MM
PPVOUT_S0_LCDBKLT 7 67 80
MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.6 MM MIN_LINE_WIDTH=0.5 MM
LCDBKLT_EN_L CRITICAL DEM8030C-SM
MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
1 C9712
1 C9713 152S1527 VOLTAGE=50V DFLS260 CRITICAL CRITICAL CRITICAL CRITICAL VOLTAGE=55V
0.1UF SWITCH_NODE=TRUE
1 C9715 1 C9716 1 C9718 1 C9719 1 C9717
10UF 10%
Q9707 D 3 10% 2 25V 2.2UF 2.2UF 2.2UF 2.2UF 1000PF
SSM6N15AFE 2 25V
X5R
X5R
402
10% 10% 10% 10% 10%
SOT563 805 PPBUS_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE 2 100V
X7R-CERM 2 100V
X7R-CERM 2 100V
X7R-CERM 2 100V
X7R-CERM 2 100V
X7R-CERM
1210 1210 1210 1210 0603
5 G S 4
PLACE_NEAR=D9701.2:3MM
9 IN LCD_BKLT_EN
LCDBKLT_DISABLE PLACE_NEAR=D9701.2:3MM
8 =PP3V3_S0_BKL_VDDIO
Q9707 D 6
SSM6N15AFE PLACE_NEAR=U9701.22:5MM PLACE_NEAR=U9701.8:3MM
SOT563
PLACE_NEAR=L9710.2:3MM R97081
1 C9714 1 C9710 1 C9711 63.4K
C
C 2 G S 1
0.01UF
10%
1UF
10%
0.1UF
10%
5 1%
1/16W
MF-LF
16V
2 X7R-CERM 25V
2 X5R 2 16V 402 2
25 BKLT_PLT_RST_L X7R-CERM CRITICAL
IN 0402 603-1 0402
Q9701
4 SI7308DN
BKL_FET_CNTL PWRPK-1212-8
MIN_NECK_WIDTH=0.25 MM R97091
59.0K
1 2 3 1%
1/16W
22
23
MF-LF
8
402 2
VDDIO VLDO VIN
U9701
LLP
LP8545SQX-EXTJ
LCDBKLT:ENG
6 GD 24 MIN_NECK_WIDTH=0.25 mm PLACE_NEAR=U9701.12:10MM
SW BKL_SW
5 FSET 21
R9717 R9717-R9722 CAN BE 0OHM IN PRODUCTION, ADD BOM OPTION
BKL_FSET FB BKL_FB 10.2 2
1 LED_RETURN_1 OUT 7 67
20 FILTER 12 MIN_LINE_WIDTH=0.5 mm
BKL_FLT OUT1 BKL_ISEN1 0.1% MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm 1/16W
MIN_NECK_WIDTH=0.20 mm TF
R9753 AND R9757 NEED TO BE 402 PACK FOR LAB ACCESS BKL_ISET 3 ISET OUT2 13 BKL_ISEN2 402
LCDBKLT:ENG
42 =I2C_BKL_1_SCL R9753 0 1 2 BKL_SCL 10 SCLK OUT3 14 BKL_ISEN3 PLACE_NEAR=U9701.13:10MM
R9718
5% 1/16W MF-LF 402
BKL_SDA 11 SDA 16 BKL_ISEN4 1
10.2 2 LED_RETURN_2
OUT4 OUT 7 67
MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm 0.1% MIN_NECK_WIDTH=0.20 mm
42 =I2C_BKL_1_SDA R9757 0 1 2 LVDS_BKL_PWM_RC 2 PWM OUT5 17 BKL_ISEN5 1/16W
TF
5% 1/16W MF-LF 402
7 FAULT 18 402
7 TP_BKL_FAULT OUT6 BKL_ISEN6 LCDBKLT:ENG
R9731 PLACE_NEAR=U9701.14:10MM
R9719
B 71 8 PPBUS_S0_LCDBKLT_PWR
1
301K 2
7 BKLT_EN 4 EN
CRITICAL
VSYNC 19 BKL_VSYNC_R
1
10.2 2
LED_RETURN_3 OUT 7 67
B
1% R9715 1
R9765
0.1%
2
MIN_NECK_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm
1 GND_SW
1/16W 1
R9755 1/16W
9 GND_S
15 GND_L
MF-LF 100K 10K TF
402 1% 5% 10K 402
1/16W (EEPROM should set EN_I_RES=1) THRM
MF-LF 1/16W
MF-LF PAD 5%
1/16W
PLACE_NEAR=U9701.16:10MM LCDBKLT:ENG
402 1
R9714 2 402 MF-LF R9720
1
25
16.2K I_LED=22.7MA (APN: 353S3376) 2 402 10.2 2
1% 1 LED_RETURN_4

Apple Macbook Pro A1425 - 051 9216

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Apple Macbook Pro A1425 - 051 9216

Uploaded by

Copyright:

Available Formats

8 7 6 5 4 3 2 1

820-3462 1 PCBF,MLB(NEW),D1 PCB CRITICAL

INTEL CPU DDR3-1333/1600MHZ

SYSTEM CLK PG 19 U5340,U5350,U5360,U5370,U5400,U5410,Q5480

FAN CONN AND CONTROL

PANTHER POINT-MPCH SMC SPI LPC+SPI Conn

PG 66 EHCI USB RIO CONN

EXTMIC LINEIN HPOUT SPDIF MICIN LINEOUT

System Block Diagram

Apple Inc. <SCH_NUM> D

VDD SYS_RERST# PM_SYSRST_L

SMC Q5720 MEMVTT_EN

P5VS3_EN PG64 PP3V3_S5 PP3V3_S5

Apple Inc. <SCH_NUM> D

Alternate Parts TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

D 639-3694 PCBA,2.5G,SS 8GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F16P,RAM_4G_SAMSUNG_35NM_1600_S

C 639-3877 PCBA,2.6G,ELPIDA 6GB,MLB,D1 DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33Q,RAM_6G_ELPIDA_CH0_1600_S

Module Parts D1 BOM GROUPS

337S4181 1 IVB,QBP0,ES2,K0,2.3,35W,2+2,1.0,3M,BGA U1000 CRITICAL CPU_IVB_2C_2.3G_ES2 D1_COMMON ALTERNATE,COMMON,D1_COMMON1,D1_COMMON2,D1_PROGPARTS,D1_PVB

337S4182 1 IVB,QBP0,ES2,K0,2.6,35W,2+2,1.05,4M,BGA U1000 CRITICAL CPU_IVB_2C_2.6G_ES2 D1_COMMON1 CPUMEM:S0,SMC_DEBUG_YES,TBTBST:Y,TBTRTR:B1,TBTHV:P15V,HUB_2NONREM,USBHUB:2512B,AXG_PHASE2,TBTISNS:YES

337S4292 1 IVB,Q4CT,QS,L1,2.5,35W,2+2,1.1,3M,BGA U1000 CRITICAL CPU_IVB_2C_2.5G_QS D1_COMMON2 EDP:YES,PPDDR:1V35,LPCPLUS_CONN:YES,LPCPLUS_R:YES,CAPS:INT,BTPWR:S4,SKIP_5V3V3:AUDIBLE,TPAD_5V_LDO:S5,SMS

337S4300 1 IVB,QC96,QS,L1,2.6,35W,2+2,1.2,3M,BGA U1000 CRITICAL CPU_IVB_2C_2.6G_QS D1_PVB LOADISNS:NO,LCDBKLT:PROD,KBDBKLT:PROD

337S4302 1 IVB,QC94,QS,L1,2.8,35W,2+2,1.2,3M,BGA U1000 CRITICAL CPU_IVB_2C_2.8G_QS D1_PROGPARTS SMC_PROG:PVB,TBTROM:PROG,BOOTROM_PROG:PVB,TPAD_PSOC:PROG

B 337S4294 1 IVB,QC4M,QS,L1,2.9,35W,2+2,1.25,4M,BGA U1000 CRITICAL CPU_IVB_2C_2.9G_QS D1_BLANK

337S4338 1 IVB,S R0MY,PRQ,L1,2.6,35W,2+2,1.2,3M,BGA U1000 CRITICAL CPU_IVB_2C_2.6G D1_DEVEL:PVB ALTERNATE,IVB_PPT_XDP,VREFDQ:M1_M3,VREFCA:LDO

337S4339 1 IVB,S R0MU,PRQ,L1,2.8,35W,2+2,1.2,3M,BGA U1000 CRITICAL CPU_IVB_2C_2.8G IVB_PPT_XDP XDP,XDP_CONN,XDP_CPU:BPM,XDP_PCH

337S4265 1 IVB,S R0MU,PRQ,L1,2.9,35W,2+2,1.25,4M,BGA U1000 CRITICAL CPU_IVB_2C_2.9G DDR3 SPD STRAPPINGS

337S4235 1 IC,PCH,PPT-MB SFF,P-QS,C0 U1800 CRITICAL PCH_C0 RAM_4G_HYNIX_1600_S 4G_HYNIX_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

337S4283 1 IC,PCH,PPT-MB SFF,PRQ,C1 U1800 CRITICAL PCH_C1 RAM_2G_ELPIDA_1600_S 2G_ELPIDA_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

338S1113 1 IC,TBT,CR-4C,B1,PRQ,288FCBGA,12X12MM U3600 CRITICAL TBTRTR:B1 RAM_4G_SAMSUNG_28NM_1600_S 4G_SAMSUNG_28NM_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

333S0623 16 IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA CRITICAL

333S0622 16 IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA CRITICAL

333S0628 16 IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA CRITICAL

333S0649 16 IC,SDRAM,DDR3-1600,256MX8,78FBGA,MICRON CRITICAL

333S0625 16 IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX CRITICAL

333S0629 16 IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA CRITICAL

333S0624 16 IC,SDRAM,DDR3-1600,512MX8,78FBGA,D35,SAMSUNG CRITICAL

333S0623 8 IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170 CRITICAL 6G_SAMSUNG_35NM_CH0_1600_S RAM_6G_SAMSUNG_28NM_CH0_1600_S 6G_SAMSUNG_28NM_CH0_1600_S,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

333S0625 8 IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970 CRITICAL 6G_HYNIX_CH0_1600_S RAM_2G_HYNIX_1600_S 2G_HYNIX_1600_S,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L BOM Configuration

333S0660 16 IC,SDRAM,DDR3-1600,512MX8,78FBGA,MICRON CRITICAL

860-1530 1 STDOFF-1.9D2.93H-TH-0.85-1.2 J6950_64 CRITICAL

860-1529 1 STDOFF-1.80D1.53H-SM J6950_65 CRITICAL

825-7841 1 LBL,PART CONFIG,BOARDS,D2 CONFIG_LABEL CRITICAL

946-4350 1 D1 MLB LOCTITE UV GLUE 190024/S 0.24G EDGE_BOND CRITICAL

607-9189 1 D1 MLB BASE BOM BASE CRITICAL BASE_BOM

341S3404 1 IC,SMC,DEVELOPMENT-PIB,D1 U4900 CRITICAL SMC_PROG:PIB

341S3405 1 IC,SMC,DEVELOPMENT-FSB,D1 U4900 CRITICAL SMC_PROG:FSB

341S3406 1 IC,SMC,DEVELOPMENT-PVB,D1 U4900 CRITICAL SMC_PROG:PVB

341S3603 1 IC,EFI,ROM,PIB, D1 U6100 CRITICAL BOOTROM_PROG:PIB

341S3636 1 IC,EFI,ROM,PIB2, D1 U6100 CRITICAL BOOTROM_PROG:PIB2

341S3650 1 IC,EFI,ROM,FSB, D1 U6100 CRITICAL BOOTROM_PROG:FSB

341SXXXX 1 IC,EFI,ROM,FSB2, D1 U6100 CRITICAL BOOTROM_PROG:FSB2

341S3667 1 IC,EFI,ROM,PVB, D1 U6100 CRITICAL BOOTROM_PROG:PVB

Programmables - All builds

337S2983 1 IC,TP PSOC,QFN,BLANK U5701 CRITICAL TPAD_PSOC:BLANK BOM Configuration

Apple Inc. <SCH_NUM> D

338S1098 1 IC,SMC12-A3,LX4FS1AH5BBCIGA3 U4900 CRITICAL SMC_BLANK

TP_DP_TBTSRC_ML_CP<3> TRUE NC_DP_TBTSRC_ML_CP<3>

I1654 TRUE SPKRCONN_R_OUT_N

12 29 73 18 TP_SDVO_TVCLKINN TRUE NC_SDVO_TVCLKINN

I1656 TRUE GND I1846

56 =PP3V42_G3H_REG PP3V42_G3H 7 =PP3V3_S3_ISNS 43