820-1810 - 051-6839 - F000 (Project Q41C)

8 7 6 5 4 3 2 1
CK ENG
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD APPD
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. REV ZONE ECN DESCRIPTION OF CHANGE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. DATE DATE
F 412044 PRODUCTION RELEASED
MLB,Q41C
11/29/05 ?
D D
PDF
TABLE_TABLEOFCONTENTS_HEAD
CSA CONTENTS SYNC MASTER DATE PDF
TABLE_TABLEOFCONTENTS_HEAD
CSA CONTENTS SYNC MASTER DATE
1 1 Table Of Contents N/A N/A 41 52 DDR2 SO-DIMM Slot B MARIAS-MDIFF N/A
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
2 2 Board Information N/A N/A 42 55 M11 Frame Buffer Constraints MARIAS 08/24/2005
3 3 System Block Diagram MARIAS 08/24/2005 43 56 I2 AGP Interface MARIAS 08/24/2005

4 4 Power Block Diagram MARIAS 08/24/2005 44 57 GPU (M11) AGP Interface MARIAS 08/24/2005
5 5 Revision History N/A N/A 45 58 GPU VCore Supply MARIAS 08/24/2005

6 6 Q41C Pin Swaps N/A N/A 46 59 GPU (M11) Core Power MARIAS 08/24/2005
7 7 Functional Test Points MARIAS 08/24/2005 47 60 GPU (M11) I/O Power MARIAS 08/24/2005
8 8 I2C Connections MARIAS 08/24/2005 48 61 GPU (M11) Frame Buffer I/F MARIAS 08/24/2005
9 9 JTAG Connections MARIAS 08/24/2005 49 62 GPU Frame Buffer A MARIAS 08/24/2005

10 10 Power Synonyms MARIAS 08/24/2005 50 63 GPU Frame Buffer B MARIAS 08/24/2005

11 11 Signal Synonyms MARIAS 08/24/2005 51 64 GPU (M11) GPIOs/Straps MARIAS 08/24/2005

12 12 Power Inputs MARIAS 08/24/2005 52 65 GPU (M11) Clocks/Misc MARIAS 08/24/2005

13 13 Battery Charger MARIAS 08/24/2005 53 66 GPU (M11) DVI/DAC Outputs MARIAS 08/24/2005
14 14 12.8V PBUS/PMU Supplies MARIAS 08/24/2005 54 67 Lower TMDS Transmitter MARIAS 08/24/2005
C
TABLE_TABLEOFCONTENTS_ITEM
15
15 5V/3.3V Supplies MARIAS 08/24/2005
55
68 Upper TMDS Transmitter MARIAS 08/24/2005 C
16 16 1.8V/1.5V Supplies MARIAS 08/24/2005 56 69 Internal Display Conns MARIAS 08/24/2005
17 17 2.5V Supply MARIAS 08/24/2005 57 70 External Display Conns MARIAS-PDIFF 06/02/2005

18 19 Vesta Power & Misc MARIAS 08/24/2005 58 71 BootROM MARIAS 08/24/2005

19 21 I2 Power MARIAS 08/24/2005 59 72 I2 PCI Interface MARIAS 08/24/2005

20 22 I2 Power Supplies MARIAS 08/24/2005 60 73 Q85 AIRPORT/BT CONN MARIAS-MDIFF N/A

21 23 I2 Supplemental MARIAS 08/24/2005 61 74 Cardbus MARIAS 08/24/2005

22 24 I2 Miscellaneous MARIAS 08/24/2005 62 75 NEC USB2 MARIAS 08/24/2005

23 25 PCI Clock Buffer MARIAS 08/24/2005 63 81 I2 UATA Interface MARIAS 08/24/2005

24 26 LEDs/Reset/Debug MARIAS 08/24/2005 64 82 HDD/ODD Connectors MARIAS-PDIFF 06/02/2005

25 27 Power Management Unit (PMU05) MARIAS 08/24/2005 65 84 I2 Ethernet Interface MARIAS 08/24/2005
26 29 Power Sequencing MARIAS 08/24/2005 66 85 Vesta Ethernet PHY MARIAS 08/24/2005

27 30 Fan Controller MARIAS 08/24/2005 67 86 Ethernet Connector N/A N/A

28 31 ALS Support MARIAS 08/24/2005 68 88 I2 FireWire Interface MARIAS 08/24/2005

29 32 Sudden Motion Sensor MARIAS 08/24/2005 69 89 Vesta FireWire PHY MARIAS 08/24/2005
30 33 Q41C Internal I/O I N/A N/A 70 90 FireWire Ports MARIAS-PDIFF 06/02/2005

31 34 Q41C Internal I/O II N/A N/A 71 91 FireWire Series Term MARIAS 08/24/2005
32 35 I2 Processor Interface MARIAS 08/24/2005 72 92 I2 USB Interface MARIAS 08/24/2005

B TABLE_TABLEOFCONTENTS_ITEM
33 36 A8 MaxBus (CPU0) MARIAS 08/24/2005

73 93 NEC USB2 Interface MARIAS 08/24/2005

B
34 37 A8 Configuration Straps MARIAS 08/24/2005 74 100 Audio Board Connector N/A N/A
35 38 A8 Power (CPU0) MARIAS 08/24/2005 75 110 Spacing & Physical Constraints MARIAS 08/24/2005
36 39 CPU VCore Supply MARIAS 08/24/2005 76 111 Spacing & Physical Constraints 2 MARIAS 08/24/2005
37 46 CPU AVDD Supply MARIAS 08/24/2005 77 112 Cross Reference Page

38 47 I2 Memory Interface MARIAS 08/24/2005 78 113 Cross Reference Page

39 48 Memory Series Termination MARIAS-NDIFF N/A 79 114 Cross Reference Page

40 50 DDR2 SO-DIMM Slot A MARIAS-MDIFF N/A 80 115 Cross Reference Page

DIMENSIONS ARE IN MILLIMETERS
METRIC Apple Computer Inc.

XX
A X.XX
DRAFTER DESIGN CK NOTICE OF PROPRIETARY PROPERTY A
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
TABLE_5_HEAD
X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION AGREES TO THE FOLLOWING
ENG APPD MFG APPD
TABLE_5_ITEM
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

051-6839 1 SCHEM,BOZEMAN,Q41C SCH1 ANGLES II NOT TO REPRODUCE OR COPY IT
TABLE_5_ITEM
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
820-1810 1 PCBF,BOZEMAN,Q41C PCB1 CRITICAL QA APPD DESIGNER TITLE
TABLE_5_ITEM
DO NOT SCALE DRAWING

826-4393 1 LBL,P/N LABEL,PCB,28MM X 6MM [EEE:SYV] CRITICAL EEE_SYV
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6MM [EEE:TML] CRITICAL EEE_TML

TABLE_5_ITEM
RELEASE SCALE SCHEM,MLB,Q41C

SCHEM,MLB,PB17"
TABLE_5_ITEM
NONE
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6MM [EEE:USH] CRITICAL EEE_USH
SIZE DRAWING NUMBER REV.
826-4393 1 LBL,P/N LABEL,PCB,28MM X 6MM [EEE:USJ] CRITICAL EEE_USJ
TABLE_5_ITEM
MATERIAL/FINISH
NOTED AS D 051-6839 F
THIRD ANGLE PROJECTION APPLICABLE SHT 1 OF 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Design-Specific Rules
TABLE_SPACING_RULE
CHASSIS GND CONNECTIONS BOARD HOLES
TABLE_SPACING_RULE
STANDARD =DEFAULT * =DEFAULT =DEFAULT =DEFAULT =DEFAULT =DEFAULT GND_CHASSIS_UPPER_DVI
=GND_CHASSIS_DVI_HOLE
CHASSIS MOUNTS
TABLE_SPACING_RULE
BGA_P1MM 10 * 0.10 MM 1.25 MM 0.1 MM 12.5 MM 15.0 MM
MAKE_BASE=TRUE
VOLTAGE=0V =GND_CHASSIS_DVI2
2
HEATSINK MOUNTS INVERTER
TABLE_SPACING_RULE MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm =GND_CHASSIS_DVI3
57
57
MECH. HOLES
BGA_P2MM 20 * 0.20 MM 1.25 MM 0.1 MM 12.5 MM 15.0 MM ZT0210
TABLE_SPACING_RULE GND_CHASSIS_FW_LOWER_DVI
=GND_CHASSIS_FW_HOLE 255R158
DEFAULT * 0.1 MM 2.5 MM 0.15 MM 10.0 MM 15.0 MM MAKE_BASE=TRUE
=GND_CHASSIS_DVI1
2
1
ZT0230 1
TABLE_SPACING_ASSIGNMENT
VOLTAGE=0V
MIN_LINE_WIDTH=0.6 mm
57 MCO HOLE B 146R126 SH0200
MIN_NECK_WIDTH=0.25 mm =GND_CHASSIS_DVI4 57 1 2 OG-503040
SHLD-SM-LF
TABLE_SPACING_ASSIGNMENT "1MM" area defined around BGAs to =GND_CHASSIS_TV 57
D *
* 1MM BGA_P1MM reduce DRCs caused by fan-out. =GND_CHASSIS_ENET 67 ZT0204
255R158
3
D
=GND_CHASSIS_FW_PORT1 70 =GND_CHASSIS_DVI_HOLE 2
AGP_STB * 1MM BGA_P2MM 1 MCO HOLE F
TABLE_SPACING_ASSIGNMENT "BGA_P2MM" rule ensures these critical =GND_CHASSIS_FW_PORT2 70
CLOCK * 1MM BGA_P2MM signals do not fan-out routed next =GND_CHASSIS_FW_EMI 70 =GND_CHASSIS_INV_GND_CLIP
to any other signals. =GND_CHASSIS_SVIDEO_HOLE 2 ZT0205
RAM_DIFF * 1MM BGA_P2MM
GND_CHASSIS_LCD
235R126 MCO HOLE G
=GND_CHASSIS_LCD1 56 1
TABLE_PHYSICAL_RULE MAKE_BASE=TRUE
VOLTAGE=0V =GND_CHASSIS_LCD2
BS0200 ZT0220
56
STDOFF-217ODX150IDX35H-TH-LF 146R126
MIN_NECK_WIDTH=0.25 mm =GND_CHASSIS_LCD3
TABLE_PHYSICAL_RULE
=GND_CHASSIS_LCD4
56
ZT0203 1 1
STANDARD
TABLE_PHYSICAL_RULE
* =DEFAULT =DEFAULT =DEFAULT =DEFAULT 56 235R126 MCO HOLE K
GND_CHASSIS_INVERTER 1
DEFAULT * Y 0.100 MM 0.100 mm 1.25 MM =GND_CHASSIS_INV_GND_CLIP 2
MAKE_BASE=TRUE =GND_CHASSIS_SVIDEO_HOLE 2 =GND_CHASSIS_FW_HOLE 2
VOLTAGE=0V =GND_CHASSIS_INVERTER1 56
Layer-specific rules for 90-ohm differential impedance MIN_NECK_WIDTH=0.25 mm =GND_CHASSIS_INVERTER2 56
TABLE_SPACING_RULE
TABLE_SPACING_RULE
SPEAKER CLIPS
90_OHM_DIFF
TABLE_SPACING_RULE
TOP,BOTTOM 2.5 MM 0.200 MM 2.5 MM 1.0 MM PCB MOUNTS SP0201 SP0202 SP0203
90_OHM_DIFF * 2.5 MM 0.200 MM 2.5 MM 1.0 MM SPKR_CLIP_P84-LF SPKR_CLIP_P84-LF SPKR_CLIP_P84-LF
ZT0201
TABLE_PHYSICAL_RULE 235R126 MCO HOLE E 1 1 1
1
TABLE_PHYSICAL_RULE
90_OHM_DIFF TOP,BOTTOM Y 0.118 MM 0.1 MM 5 MM
TABLE_PHYSICAL_RULE
ZT0202
90_OHM_DIFF * Y 0.125 MM 0.1 MM 5 MM 235R126 MCO HOLE H SP0204 SP0205 SP0206
1 SPKR_CLIP_P84-LF SPKR_CLIP_P84-LF SPKR_CLIP_P84-LF
Layer-specific rules for 100-ohm differential impedance Layer-specific rules for 60-ohm single-ended impedance
TABLE_SPACING_RULE TABLE_PHYSICAL_RULE 1 1 1
C TABLE_SPACING_RULE
100_OHM_DIFF
TABLE_SPACING_RULE
TOP,BOTTOM 2.5 MM 0.200 MM 2.5 MM 1.0 MM
TABLE_PHYSICAL_RULE
60_OHM_SE * Y 0.076 MM =50_OHM_SE =50_OHM_SE
C
100_OHM_DIFF * 2.5 MM 0.200 MM 2.5 MM 1.0 MM
Layer-specific rules for 50-ohm single-ended impedance
TABLE_SPACING_RULE
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
TABLE_SPACING_RULE
50_OHM_SE * 2.5 MM 0.125 MM 2.5 MM 1.0 MM
BOARD STACK-UP AND CONSTRUCTION
100_OHM_DIFF TOP,BOTTOM Y 0.092 MM 0.1 MM 5 MM
TABLE_PHYSICAL_RULE TABLE_PHYSICAL_RULE SEE BOARD FILE FOR DETAILED INFORMATION
100_OHM_DIFF * Y 0.100 MM 0.1 MM 5 MM CONVENTIONAL CONSTRUCTION WITH Pxx TH VIA
TABLE_PHYSICAL_RULE
50_OHM_SE * Y 0.100 MM 0.100 MM 1.25 MM
Layer-specific rules for 110-ohm differential impedance SIGNAL (1/2 OZ + COPPER PLATING)
TABLE_SPACING_RULE
1
TABLE_SPACING_RULE PREPREG GROUND (1/2 OZ)
110_OHM_DIFF
TABLE_SPACING_RULE
TOP,BOTTOM 2.5 MM 0.330 MM 2.5 MM 1.0 MM 2 CORE
110_OHM_DIFF * 2.5 MM 0.300 MM 2.5 MM 1.0 MM SIGNAL (1/2 OZ)
TABLE_PHYSICAL_RULE
TMDS RETURN CURRENT VIAS 3
PREPREG SIGNAL (1/2 OZ)
TABLE_PHYSICAL_RULE ZT0250
HOLE-VIA-P5RP25
ZT0254
HOLE-VIA-P5RP25
4
110_OHM_DIFF
TABLE_PHYSICAL_RULE
TOP,BOTTOM Y 0.080 MM 0.1 MM 5 MM 1 1
CORE GROUND (1/2 OZ)
110_OHM_DIFF * Y 0.085 MM 0.1 MM 5 MM 5
ZT0251 ZT0255 PREPREG CUT POWER PLANE (1 OZ)
Portable-specific Override Rules
TABLE_SPACING_RULE
HOLE-VIA-P5RP25
1
HOLE-VIA-P5RP25
1
6
CORE CUT POWER PLANE (1 OZ)
TABLE_SPACING_RULE
AGP 201 * 0.2 MM
ZT0252
HOLE-VIA-P5RP25
ZT0256
HOLE-VIA-P5RP25
7
PREPREG GROUND (1/2 OZ)
B
TABLE_SPACING_RULE
AGP_STB 251 * 0.25 MM
1 1
8 B
TABLE_SPACING_RULE ZT0253 ZT0257 CORE SIGNAL (1/2 OZ)
VGA 151 * 0.15 MM =DEFAULT =DEFAULT =DEFAULT =DEFAULT HOLE-VIA-P5RP25
1
HOLE-VIA-P5RP25
1
9
TABLE_SPACING_RULE PREPREG SIGNAL (1/2 OZ)
TV 151 * 0.15 MM =DEFAULT =DEFAULT =DEFAULT =DEFAULT 10
CORE GROUND (1/2 OZ)
TABLE_PHYSICAL_RULE
SI_TMDS_DP<2> 54
11
TABLE_PHYSICAL_RULE
I224
NO_TEST=YES PREPREG SIGNAL (1/2 OZ + COPPER PLATING)
VGA * =60_OHM_SE =60_OHM_SE =60_OHM_SE =60_OHM_SE 12
TABLE_PHYSICAL_RULE TABLE_BOARD_INFO
TV * =60_OHM_SE =60_OHM_SE =60_OHM_SE =60_OHM_SE
BOM OPTIONS Module Components TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,1MM MM
TABLE_BOMGROUP_HEAD
PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION

BOM NUMBER BOM NAME BOM OPTIONS
TABLE_BOMGROUP_ITEM
343S0383 1 IC,ASIC,I2,REV1.2,NB/SB,974 BGA U2100 CRITICAL

630-7017 PCBA,MLB,BESTMHZ,BOZEMAN,VRAM_S,Q41C COMMON,ALTERNATE,EEE_SYV,GPU_LF,VRAM_SAMSUNG,gQ41C,gCommon
TABLE_BOMGROUP_ITEM
337S3135 1 IC,PMU05,BLANK,QFP U2700 CRITICAL PMU_BLANK

630-7186 PCBA,MLB,BESTMHZ,BOZEMAN,VRAM_H,Q41C COMMON,ALTERNATE,EEE_TML,GPU_LF,VRAM_HYNIX,gQ41C,gCommon
TABLE_BOMGROUP_ITEM
341S1772 1 IC,PMU05,Vxxx,QFP U2700 CRITICAL PMU_PROG

630-7443 PCBA,MLB,BESTMHZ,GPU_EUT,VRAM_S,PB17 COMMON,ALTERNATE,EEE_USH,GPU_EUTECTIC,VRAM_SAMSUNG,gQ41C,gCommon
TABLE_BOMGROUP_ITEM
337S3277 1 IC,A7PM,R1.6,1.67GHZ,LGA,1.28V,25W,85C U3600 CRITICAL A7PM_1P67_LGA

630-7444 PCBA,MLB,BESTMHZ,GPU_EUT,VRAM_H,PB17 COMMON,ALTERNATE,EEE_USJ,GPU_EUTECTIC,VRAM_HYNIX,gQ41C,gCommon
337S3077 1 IC,A8,xxxGHZ U3600 CRITICAL CPU_A8
BOM GROUP BOM OPTIONS
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
338S0252 1 IC,GPU,M11P U5700 CRITICAL GPU_LF Board Information
gCommon 5V_HD_LOGIC,BACKUP_BATT,CPU_A7PM,I2_FW_BETA,I2_MAXBUS_50OHM,MAXBUS_1V8,gCommon1 338S0299 1 IC,GPU,M11P,EUTECTIC U5700 CRITICAL GPU_EUTECTIC
A gCommon1 MMM_ACCEL_KIONIX,GPU_PWRPLAY,GPU_SS,GPU_LVDDR_2V8,GPU_MEMIO_1V8,gCommon2
TABLE_BOMGROUP_ITEM
335S0088 1 BOOTROM,BLANK U7100 CRITICAL BOOTROM_BLANK

SYNC_MASTER=N/A
NOTICE OF PROPRIETARY PROPERTY

SYNC_DATE=N/A
A
TABLE_BOMGROUP_ITEM
gCommon2 I2_REV1_NOT,I2_MAXBUS_FBCLK_MATCHED,I2_AGP_FBCLK_MATCHED,I2_PCI_FBCLK_MATCHED,gCommon3 341S1739 1 IC,BOOTROM,B,Q41C U7100 CRITICAL BOOTROM_PROG THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
TABLE_BOMGROUP_ITEM
AGREES TO THE FOLLOWING

gCommon3 CPU_VCORE_2STATES,I2_MAXBUS_166MHZ,CPU0_BUSRATIO_10.0X,I2VCORE_1V5,I2VCORE_BURST,gCommon4 343S0356 1 IC,ASIC,VESTA,V1.3,LF U8500 CRITICAL
TABLE_BOMGROUP_ITEM
gCommon4 VESTA_PORT2_DISABLE,DVO_1V8,TMDS_DUAL,VCORE_OFFSET,VCORE_OFFSET_SW,gUSB 333S0317 4 IC,GDDR SDRAM,2MX32X4,300MHZ, LF FBGA144 U6200,U6250,U6300,U6350 CRITICAL VRAM_SAMSUNG II NOT TO REPRODUCE OR COPY IT
TABLE_BOMGROUP_ITEM

gUSB USB2_NEC,USB1P1_NEC,TPAD_SEQ_PMU 333S0314 4 IC,GDDR SDRAM,2MX32X4,300MHZ, LF FBGA144 U6200,U6250,U6300,U6350 CRITICAL VRAM_HYNIX
TABLE_BOMGROUP_ITEM
IS TABLE_ALT_HEAD

gQ41C Q41C_PARTS,A7PM_1P67_LGA,BOOTROM_PROG,PMU_PROG,MAXBUS_TBEN_SYNC,gQ41CVcore PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
gQ41CVcore CPU0_VCORE_1V30,Q41,CPU0_AVDD_1V30
TABLE_BOMGROUP_ITEM
343S0388
PART NUMBER
343S0356 ? U8500 v1.4 is alt to v1.3

TABLE_ALT_ITEM
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
2 115
TABLE_ALT_ITEM
337S3181 337S3277 A7PM_1P67_LGA U3600 v1.5 is alt to v1.6 NONE
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J8600 J9020 J9010
Ethernet FW - A FW - B
Connector Connector Connector
P.70
J3320 JA000 J1250 J3400
P.67 P.70 SW MODEM Audio Battery Power Supply DC-In
Connector Connector Connector & Charger Connector
4 DATA PAIRS
2 DATA PAIRS
@ 200MHz
2 DATA PAIRS
@ 400MHZ P.30 P.74 P.12 P.13-17 P.31
D D
U8500
Vesta U1250
Ethernet Combo FireWire
BATTERY
P.66 PHY P.69 CURRENT
G/MII J8200/J8250 SENSOR
3.3V HDD/ODD P.12 ALS Sensors
10/100/1000 1394 OHCI Connectors U3000
8BIT TX
8BIT RX
3.3V
8BIT TX/RX
P.64 I2S Fan SLEEP SMBUS
125MHZ 100MHZ I2C Circuit LED 3.3V J7400
UATA P.27 P.24 CARDBUS
U2700
Connector
ETHERNET
10/100/1000
FIREWIRE
800 Mb/S
UATA 100
I2S I2C
x2 x2 PMU P.61
P.65 P.68
P.63 P.21 P.21 J2690 P.25 33MHZ
C USB2.0 SCCA
Serial Debug
U3220 16/32 BITS C
Connector 3.3V/5V
UNUSABLE PORTS A-F P.21 SMS Sensor
P.73 P.24 U7400
P.29
VIA/PMU TI PCI1510
U2100 P.21 U7100 J7300 CardBus
BOOTROM BOOT ROM AIRPORT Controller
I2 P.21 1M X 8
P.58
Connector
P.60
P.61
PCI
32BITS PCI BUS
33MHZ 32BITS
P.59 33MHZ
AGP BUS MEMORY BUS 3.3V
1.5V/3.3V U5700 1.8V
32BITS 240MHZ
MAXBUS U7500
B P.32
DDR2 MEMORY
4X AGP
P.43
66MHZ
ATI 64BITS
NEC USB2.0 B
(x2 Channels) EHCI HC
P.47
MEMORY BUS
M11P P.62
MAXBUS
1.8V 1.8V
167MHZ
P.44-53 MEMORY CH A LEFT USB2
167MHZ BlueTooth (1.1)
32BIT ADDR 64BITS U6200/U6250
64BIT DATA J5000/J5200
P.49
CONN P.60
DDR2 SDRAM DIMM 0
U3600
DDR2 SDRAM DIMM 1 RIGHT USB2
Trackpad (1.1)
A7PM SO-DIMM Connector MEMORY CH B
U6300/U6350
CONN
P.30
(VIA SIL1178)
CPU P.40/41 P.50
COMPOSITE
EDID (I2C)
S-VIDEO
TMDS
(MPC7448) 128MB System Block Diagram
RGB
DDC
LVDS
A P.33-35 SYNC_MASTER=MARIAS SYNC_DATE=08/24/2005

A
J6950 J6900 J7060 J7000 AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
CPU PLL Inverter LCD Panel S-Video DVI-I III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
Config Connector Connector Connector Connector SIZE DRAWING NUMBER REV.
P.7 P.56 P.56 P.57 P.57 APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 3 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
POWER SYSTEM ARCHITECTURE

5V_PWRON MAXBUS
1V20_REF -
>~13.44V TURNS-ON BACKLIGHT VCC VRAM CORE

<~13.44V SHUTS-OFF
+
INVERTER VRAM I/O

MAIN 1.8V/1.5V DDR2 POWER
D AC RUN/SS D
+PBUS
DC/DC 1V8_PWRON
ADAPTER INRUSH BUCK
LIMITER +24V_PBUS REGULATOR (MAX1715)
IN
VCC
(LTC1625)
+PBUS PGOOD 1V8_1V5_OK
SHUTDOWN: STOPPED
14V_PBUS SLEEP: RUNNING 1V5_PWRON
AC: 12.8V RUN: RUNNING
NO AC: BATTERY VOLTAGE
1625 NOT RUNNING TURNS ON OUTPUT @ 2.4V
AGP I/O
ON1/ON2 5V_PWRON
SHUTDOWN: RUNNING
SLEEP: RUNNING VCC
RUN: RUNNING
5V_PWRON DC/DC
RC AT 1M*0.047UF @ 24V (MAX1717)
3V3_ALL 5V_PWRON
+BATT PMU
LDO 3V3_ALL SHUTDOWN: STOPPED
4V6_ALL
RUN/SS - 5V
TURNS ON AT >1V 5V_PWRON +PBUS VCC
EXT_VCC SLEEP: STOPPED
RUN: RUNNING C
C <100UA ALLOWED
INTERNAL ZENER CLAMP TO 6V DC/DC
MAIN 3V/5V PGOOD 3V_5V_OK (LTC1778) GPU_VCORE
DC/DC SHUTDOWN: STOPPED +1.3V
(LTC3707) HOLDS BOTH RUN/SS AT GND
SLEEP: STOPPED CPU_VCORE
VCC STBYMD
WHEN IT’S CONNECTED TO GND
TURNS CONTROL TO RUN/SS
RUN: RUNNING (+1.3V)
14V_PBUS WHEN IT’S OPEN
TURNS ON AS LOW AS 0.8V/TYP 1.5V
INTERNAL 1.2UA CURRENT SOURCE
SHUTDOWN: STOPPED
SLEEP: RUNNING RUN/SS
RUN: RUNNING
BACKUP 14V CHARGES BACKUP BATTERY
INTERNAL ZENER CLAMP TO 6V
3V3_PWRON
<100UA ALLOWED
TURNS ON AT >1V
BATTERY RUN/SS - 3V
POWER SEQUENCE
24V IS OUTPUT ONLY FROM
BACKUP BATTERY (CONTROLLED BY PMU)
RC AT 1M*0.1UF @ 24V
CHARGER INPUT SHUT-DOWN RUN SLEEP RUN SHUT-DOWN
& BOOST OUTPUT NO INRUSH PROTECTION DC/DC
WHEN ONLY BATTERY IS CONNECTED (LTC3412) SLEEP
B +24V_PBUS SHUTDOWN: STOPPED 2V5_PWRON
B
SLEEP: RUNNING
BACKUP BATTERY CIRCUIT CHARGES OFF +PBUS RUN: RUNNING
AND PREVENTS +PBUS AND +24V_PBUS FROM DROPPING BELOW 6V
(UNTIL DRAINED) 5V_PWRON ~2.23MS
BATTERY DC/DC
5V_RUN
~7.36MS
(LTC3412) 3V3_PWRON
CHARGER I2 CORE
SHUTDOWN: STOPPED +1.5V 3V3_RUN
(MAX1772)
+BATT
SLEEP: RUNNING
RUN: RUNNING
3V_5V_OK
2V5_PWRON
2V5_RUN
1V8_PWRON
INCORRECT 2.4V - ??? MS
??? MS
??? MS
NO INRUSH PROTECTION 1V8_RUN

3S 2P 18650 CELLS WHEN ONLY BATTERY IS CONNECTED
1V5_PWRON
1V5_RUN
Power Block Diagram
BATTERY VOLTAGE
A +PBUS SYNC_MASTER=MARIAS

SYNC_DATE=08/24/2005
A
CPU_VCORE ~8.2MS
FEED-IN PATH THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
GPU_VCORE AGREES TO THE FOLLOWING
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 4 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
REVISION HISTORY
PROTO
04/05/2005 - Beginning revision history
- Sync’d FB pin swaps from 051-5838
- Pinned out audio connector per flex cable
- Pinned out left USB/ALS connector per flex cable
04/07/2005 - Moved modem connector to non-shared page
- Updated chassis ground connections
- Pin swapped DDR2 according to layout
04/11/2005 - Changed audio caps to X5R (CA033, CA050, CA051)
04/12/2005 - Updated wireless connector pinout according to flex
- Implemented more DDR2 pin swaps
- Implemented pin swaps on FW data lines
D -
-
04/14/2005 -
Added RAM_DQS_N pulldowns
Corrected most line and neck width properties
Switched GPU to M11
D
04/15/2005 - Added CPU Vcore mux circuit
04/19/2005 - Added NO_TEST property to buses between JTAG enabled devices
- Pinswapped FB I/F for M11
04/20/2005 - Corrected ENET power rail to PWRON instead of RUN (Wake-on-LAN)
- Corrected Vesta reset and Ethernet LOWPWR circuits
- Changed R5880 to 6.34K to take GPU Vcore to 1.3V/!.05V
- Added page 6 and modified pages 11,35,81 for design specific pin swaps
- Separated GPU MVREF into two dividers
04/26/2005 - Added 8 vias for TMDS return current
- Added LVDS electrical constraint set properties
04/27/2005 - Added NO_TEST property to SI_TMDS_DP<2> (no room for TP)
- Changed MIN_NECK_WIDTH property on TMDS power rails to 0.2 mm
- Changed gender of debug connector
- Removed C6367 due to MCO violation
04/29/2005 - SChematic released as REV 01 for PROTO
EVT
05/04/2005 - Added SYNONYMS to allow DVO and USB pulldown pinswaps
05/09/2005 - Added missing pullup to SYS_LID_OPEN
- Added missing pulldown to Vesta LPWR_1394
05/09/2005 - Lead-free resistor replacement on page 86
05/16/2005 - Various lead-free replacements
- Added Hynix VRAM option and PCBA
05/17/2005 - Added 2 0.1uF caps to VGA sync buffers
05/25/2005 - Added NEC USB2 controller and PCI clock buffer
- Various lead-free replacements
- Added pullup to BATT0_DET
05/26/2005 - Removed SMS PIC microcontroller
05/31/2005 - Added 2 0.1uF caps to GPU Vcore output
- Corrected USB diff pair and spacing/physical rules on ports
06/01/2005 - Corrected caps on FireWire VP rail to 50V
- Various lead-free replacements
DVT
06/28/2005 - Added 10K pullup to VIA_REQ_L
- Changed Q2941 to level shift/pass FET to correct GPU VCore and CPU Vcore power sequencing
- Moved R2943 to SYS_PWRSEQ_1_L to correct trackpad power state in sleep
- Moved =PP3V3_I2C_SB to RUN rail to correct pumpup problem in sleep
- Changed to USB1P1_NEC BOMOPTION
07/06/2005 - Various Pb-free replacements
- Changed TMDS drive strength resistors to 301 ohm, which was built at EVT
- Added FET to allow PMU control of trackpad power sequencing
07/08/2005 - Added resistor mux for I2’s MAXBUS I/O rail (PWRON vs RUN)
07/09/2005 - Changed CPU Vcore to 2-states only (no MUX)
C -
-
-
07/14/2005 -
Removed I2’s connection to TBEN (leakage path)
Changed 32.768kHz crystal to new APN specifing 1uW drive parts
Added line width constraints to LTC1625 and CPU Vcore gate nodes
Added external 1K pullups in parallel with all I2 internal pullups
C
07/18/2005 - Changed NEC USB2 series R value to 39.2 ohm
- Added 150 ohm pulldowns to FW_CTL lines at Vesta
- Changed TMDS transmitter ferrites to part with higher current rating (1.5A)
- Added BOMOPTIONs for and stuffed CPU Vcore at 1.28V and 1.30V
07/19/2005 - Added audio mute sequencing FETs
- Moved UATA_DSTROBE cap to other side of series resistor
- Released as REV 06 for DVT
07/22/2005 - Changed all external I2 GPIO pullups to 10K
- Stuffed R2452, R2462, R2463 to correct I2 2.5V pullup problem
07/25/2005 - Replaced 371S0299 with 371S0300
- Swapped I2_MAXBUS_33OHM and I2_MAXBUS_50OHM BOMOPTIONs
- Changed to Vesta v1.4 as primary U8500, Vesta v1.3 as alternate
07/26/2005 - Changed PCI ADB output series term to 22 ohms
- Swapped locations (i.e. values) of C2500 and C2501
07/29/2005 - Released as REV 05 for DVT
08/03/2005 - Added R3772 on CPU0_EXT_QUAL 10K pulldown.
- Added R0985 on CPU0_JTAG_TCK 10K pull down (no stuff).
- Changed C1721 and C2205 to 2200pF.
08/03/2005 - Changed C1730 to 5.6pF.
- Changed C1700 and C1701 and C2215 and C2216 to 47uF.
- Changed R1720 and R2205 to 7.5K.
Pre-PVT
08/16/2005 - Replaced C3940-C3947 with ceramic caps
08/17/2005 - Changed power supply solder jumpers to shorts
- Added five ceramic caps to Vcore supply input
- Changed D1460,D1461 to 60V schottky to reduce reverse leakage
08/18/2005 - Changed R2958 to 10K to improve power sequencing timing
08/22/2005 - Added FETs to control leakage on Vesta rails
08/24/2005 - Changed C8600-C8603 to 1uF due to FET isolation
- Changed R5822 to 100K for power sequencing improvements
- NO STUFFed R2969 for power sequencing improvements
- Released as REV 07 for Pre-PVT
PVT
08/29/2005 - Released as REV A for PVT/Production
09/02/2005 - Stuffed R8420 with 10K, 5% to ensure MDIO logic levels
- Stuffed R2464 to correct unused GPIO logic level
B B
F
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 5 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D I2S Series Rs Lower DVO Series Rs D

MAKE_BASE=TRUE 22 I2S0_SB_TO_DEV_DTO_R =RP1150P1 11 11 =RP1150P8 I2S0_SB_TO_DEV_DTO 7 74 MAKE_BASE=TRUE MAKE_BASE=TRUE 53 GPU_DVOD_R<0> =RP6720P1 54 54 =RP6720P8 GPU_DVOD<0> 54 MAKE_BASE=TRUE
MAKE_BASE=TRUE 22 I2S0_BITCLK_R =RP1150P2 11 11 =RP1150P7 I2S0_BITCLK 7 74 MAKE_BASE=TRUE MAKE_BASE=TRUE 53 GPU_DVOD_R<1> =RP6720P2 54 54 =RP6720P7 GPU_DVOD<1> 54 MAKE_BASE=TRUE
MAKE_BASE=TRUE 22 I2S0_MCLK_R =RP1150P3 11 11 =RP1150P6 I2S0_MCLK 7 74 MAKE_BASE=TRUE MAKE_BASE=TRUE 53 GPU_DVOD_R<2> =RP6720P3 54 54 =RP6720P6 GPU_DVOD<2> 54 MAKE_BASE=TRUE
MAKE_BASE=TRUE 22 I2S0_SYNC_R =RP1150P4 11 11 =RP1150P5 I2S0_SYNC 7 74 MAKE_BASE=TRUE MAKE_BASE=TRUE 53 GPU_DVOD_R<3> =RP6720P4 54 54 =RP6720P5 GPU_DVOD<3> 54 MAKE_BASE=TRUE
MAKE_BASE=TRUE 22 I2S1_SB_TO_DEV_DTO_R =RP1151P1 11 11 =RP1151P8 I2S1_SB_TO_DEV_DTO 30 MAKE_BASE=TRUE MAKE_BASE=TRUE 53 GPU_DVOD_R<11> =RP6721P1 54 54 =RP6721P8 GPU_DVOD<11> 54 MAKE_BASE=TRUE
MAKE_BASE=TRUE 22 I2S1_SYNC_R =RP1151P2 11 11 =RP1151P7 I2S1_SYNC 30 MAKE_BASE=TRUE MAKE_BASE=TRUE 53 GPU_DVOD_R<10> =RP6721P2 54 54 =RP6721P7 GPU_DVOD<10> 54 MAKE_BASE=TRUE
MAKE_BASE=TRUE 22 I2S1_MCLK_R =RP1151P3 11 11 =RP1151P6 I2S1_MCLK 30 MAKE_BASE=TRUE MAKE_BASE=TRUE 53 GPU_DVOD_R<9> =RP6721P3 54 54 =RP6721P6 GPU_DVOD<9> 54 MAKE_BASE=TRUE
MAKE_BASE=TRUE 22 I2S1_BITCLK_R =RP1151P4 11 11 =RP1151P5 I2S1_BITCLK 30 MAKE_BASE=TRUE MAKE_BASE=TRUE 53 GPU_DVOD_R<8> =RP6721P4 54 54 =RP6721P5 GPU_DVOD<8> 54 MAKE_BASE=TRUE
MAKE_BASE=TRUE 53 GPU_DVOD_R<6> =RP6722P1 54 54 =RP6722P8 GPU_DVOD<6> 54 MAKE_BASE=TRUE

UATA Series Rs MAKE_BASE=TRUE 53 GPU_DVOD_R<5>
GPU_DVO_HSYNC_R
=RP6722P4
=RP6723P1
54 54 =RP6722P5
=RP6723P8
GPU_DVOD<5>
GPU_DVO_HSYNC
54 MAKE_BASE=TRUE
MAKE_BASE=TRUE 53 54 54 54 55 MAKE_BASE=TRUE
MAKE_BASE=TRUE 53 GPU_DVO_VSYNC_R =RP6723P2 54 54 =RP6723P7 GPU_DVO_VSYNC 54 55 MAKE_BASE=TRUE
MAKE_BASE=TRUE 63 UATA_DD_R<12> =RP8150P1 63 63 =RP8150P8 UATA_DD<12> 7 63 64 MAKE_BASE=TRUE
MAKE_BASE=TRUE 53 GPU_DVO_DE_R =RP6723P3 54 54 =RP6723P6 GPU_DVO_DE 54 55 MAKE_BASE=TRUE
MAKE_BASE=TRUE 63 UATA_CS0_L_R =RP8150P2 63 63 =RP8150P7 UATA_CS0_L 7 63 64 MAKE_BASE=TRUE (IDE_CS1FX_L)
MAKE_BASE=TRUE 53 GPU_DVO_CLKP_R =RP6723P4 54 54 =RP6723P5 GPU_DVO_CLKP 54 55 MAKE_BASE=TRUE

MAKE_BASE=TRUE 63 UATA_DD_R<3>
UATA_DD_R<15>
=RP8151P3
=RP8151P4
63 63 =RP8151P6
=RP8151P5
UATA_DD<3>
UATA_DD<15>
7 63 64 MAKE_BASE=TRUE Upper DVO Series Rs
MAKE_BASE=TRUE 63 63 63 7 63 64 MAKE_BASE=TRUE
C MAKE_BASE=TRUE
MAKE_BASE=TRUE
63
63
UATA_DD_R<9>
UATA_DD_R<4>
=RP8152P1
=RP8152P2
63
63
63
63
=RP8152P8
=RP8152P7
UATA_DD<9>
UATA_DD<4>
7 63 64
7 63 64
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
53
53
GPU_DVOD_R<13>
GPU_DVOD_R<12>
=RP6821P1
=RP6821P2
55
55
55
55
=RP6821P8
=RP6821P7
GPU_DVOD<13>
GPU_DVOD<12>
55
55
MAKE_BASE=TRUE
MAKE_BASE=TRUE
C
MAKE_BASE=TRUE 63 UATA_DD_R<6> =RP8152P3 63 63 =RP8152P6 UATA_DD<6> 7 63 64 MAKE_BASE=TRUE MAKE_BASE=TRUE 53 GPU_DVOD_R<14> =RP6821P3 55 55 =RP6821P6 GPU_DVOD<14> 55 MAKE_BASE=TRUE
MAKE_BASE=TRUE 63 UATA_DA_R<2> =RP8153P1 63 63 =RP8153P8 UATA_DA<2> 7 63 64 MAKE_BASE=TRUE MAKE_BASE=TRUE 53 GPU_DVOD_R<18> =RP6822P1 55 55 =RP6822P8 GPU_DVOD<18> 55 MAKE_BASE=TRUE
MAXBUS Pullups AGP Pullups USB Pulldowns

MAKE_BASE=TRUE 33 32 MAXBUS_TS_L =RP3510P1 32 MAKE_BASE=TRUE 44 43 AGP_TRDY_L =RP5610P1 43 72 =RP9210P8 USB2_I2_LEFT_PORT_P 11 MAKE_BASE=TRUE
MAKE_BASE=TRUE 32 MAXBUS_CPU1_BG_L =RP3510P2 32 MAKE_BASE=TRUE 44 43 AGP_IRDY_L =RP5610P2 43 72 =RP9210P7 USB2_I2_LEFT_PORT_N 11 MAKE_BASE=TRUE
MAKE_BASE=TRUE 33 32 MAXBUS_CPU0_DBG_L =RP3510P3 32 MAKE_BASE=TRUE 44 43 AGP_REQ_L =RP5610P3 43 72 =RP9210P6 USB2_I2_P<1> 72 MAKE_BASE=TRUE
MAKE_BASE=TRUE NC_MAXBUS_TBEN_I2 =RP3510P4 32 MAKE_BASE=TRUE 44 43 AGP_RBF_L =RP5610P4 43 72 =RP9210P5 USB2_I2_N<1> 72 MAKE_BASE=TRUE
NO_TEST=YES
MAKE_BASE=TRUE 33 32 MAXBUS_CPU0_BG_L =RP3511P1 32 MAKE_BASE=TRUE 44 43 AGP_FRAME_L =RP5611P1 43 72 =RP9211P8 USB2_I2_RIGHT_PORT_P 11 MAKE_BASE=TRUE
MAKE_BASE=TRUE 32 MAXBUS_CPU1_HIT_L =RP3511P2 32 MAKE_BASE=TRUE 44 43 AGP_DEVSEL_L =RP5611P2 43 72 =RP9211P7 USB2_I2_RIGHT_PORT_N 11 MAKE_BASE=TRUE
MAKE_BASE=TRUE 33 32 MAXBUS_CPU0_HIT_L =RP3511P3 32 MAKE_BASE=TRUE 44 43 AGP_STOP_L =RP5611P3 43 72 =RP9211P6 USB2_I2_P<3> 72 MAKE_BASE=TRUE
B MAKE_BASE=TRUE 33 32 MAXBUS_CPU0_BR_L =RP3511P4 32 MAKE_BASE=TRUE 44 43 AGP_GNT_L =RP5611P4 43 72 =RP9211P5 USB2_I2_N<3> 72 MAKE_BASE=TRUE

B
MAKE_BASE=TRUE 32 MAXBUS_CPU1_BR_L =RP3512P1 32 72 =RP9212P8 USB_I2_BT_P 11 MAKE_BASE=TRUE
MAKE_BASE=TRUE 33
MAKE_BASE=TRUE 34
32
32
MAXBUS_TA_L
MAXBUS_CPU0_INT_L
=RP3512P2
=RP3512P3
32
32
PCI Pullups 72
72
=RP9212P7
=RP9212P6
USB_I2_BT_N
USB_I2_TPAD_P
11
11
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE 32 MAXBUS_CPU1_INT_L =RP3512P4 32 72 =RP9212P5 USB_I2_TPAD_N 11 MAKE_BASE=TRUE
MAKE_BASE=TRUE 11 PCI_AIRPORT_GNT_L =RP7250P1 59
MAKE_BASE=TRUE 60 59 PCI_TRDY_L =RP7250P2 59 73 =RP9300P8 USB2_NEC_LEFT_PORT_P 11 MAKE_BASE=TRUE

62 61
MAKE_BASE=TRUE 33 32 MAXBUS_CPU0_DRDY_L =RP3513P2 32 MAKE_BASE=TRUE 60 59 PCI_IRDY_L =RP7250P3 59 73 =RP9300P7 USB2_NEC_LEFT_PORT_N 11 MAKE_BASE=TRUE
62 61
MAKE_BASE=TRUE 32 MAXBUS_CPU1_DRDY_L =RP3513P3 32 MAKE_BASE=TRUE 60 59 PCI_STOP_L =RP7250P4 59 73 =RP9300P6 USB2_NEC_RIGHT_PORT_N 11 MAKE_BASE=TRUE
62 61
MAKE_BASE=TRUE 33 32 MAXBUS_AACK_L =RP3513P4 32 73 =RP9300P5 USB2_NEC_RIGHT_PORT_P 11 MAKE_BASE=TRUE
MAKE_BASE=TRUE 11 PCI_CBUS_REQ_L =RP7251P1 59
MAKE_BASE=TRUE 33 32 MAXBUS_ARTRY_L =RP3514P1 32 MAKE_BASE=TRUE 11 PCI_AIRPORT_REQ_L =RP7251P2 59 73 =RP9301P8 USB_NEC_BT_P 11 MAKE_BASE=TRUE

MAKE_BASE=TRUE 32 MAXBUS_CPU1_DBG_L =RP3514P2 32 MAKE_BASE=TRUE 11 PCI_CBUS_GNT_L =RP7251P3 59 73 =RP9301P7 USB_NEC_BT_N 11 MAKE_BASE=TRUE
MAKE_BASE=TRUE 33 32 MAXBUS_TEA_L =RP3514P3 32 MAKE_BASE=TRUE 60 59 PCI_FRAME_L =RP7251P4 59 73 =RP9301P6 USB_NEC_TPAD_N 11 MAKE_BASE=TRUE
62 61
73 =RP9301P5 USB_NEC_TPAD_P 11 MAKE_BASE=TRUE
FW Series Rs
MAKE_BASE=TRUE 68 9 FW_D_R<3> =RP9100P1 71 71 =RP9100P8 FW_D<3> 9 69 MAKE_BASE=TRUE
MAKE_BASE=TRUE 68 9 FW_D_R<7> =RP9101P1 71 71 =RP9101P8 FW_D<7> 9 69 MAKE_BASE=TRUE Q41C Pin Swaps

A MAKE_BASE=TRUE
MAKE_BASE=TRUE
68 9
68 9
FW_D_R<6>
FW_D_R<4>
=RP9101P3
=RP9101P4
71
71
71
71
=RP9101P6
=RP9101P5
FW_D<6>
FW_D<4>
9 69
9 69
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 6 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Enhanced MAC-1 Test Coverage

D Functional test points use a P6 pad placed on bottom side.
D
I121 PP24V_ADAPTER 10 FUNC_TEST=YES Place 2 TPs @ connector I76

PP5V_TPAD_F 30 FUNC_TEST=YES
I1
PP24V_ALL_PBUSA 10 FUNC_TEST=YES I77
USB_TPAD_P 11 30 FUNC_TEST=YES
I2
PP12V8_ALL_PBUSB 10 FUNC_TEST=YES I78
USB_TPAD_N 11 30 FUNC_TEST=YES
I4 PPVCORE_RUN_GPU 10 FUNC_TEST=YES I88
PP3V3_PWRON_DS1775_R 30 FUNC_TEST=YES
I3 PPVCORE_RUN_CPU 10 FUNC_TEST=YES I89
SYS_OVERTEMP_L 11 25 30 FUNC_TEST=YES
POWER
I6
PP1V8_PWRON 10 FUNC_TEST=YES Place within 50 mm I43
PP3V3_ALL_HALL_EFFECT_R 30 FUNC_TEST=YES
SYSTEM
I5
PP2V5_PWRON 10 FUNC_TEST=YES of power supply. I45 SYS_LID_OPEN_F 30 FUNC_TEST=YES
I7 PP5V_PWRON 10 FUNC_TEST=YES I30 SYS_POWER_BUTTON_L_F 30 FUNC_TEST=YES Place within 25 mm
I8
PP3V3_PWRON 10 FUNC_TEST=YES I29
=FTP_SLEEP_LED 74 FUNC_TEST=YES of TPAD connector.
I9
PP5V_RUN 10 FUNC_TEST=YES I31 SYS_CHARGE_LED_L 24 31 FUNC_TEST=YES
I10
PP3V3_ALL 10 FUNC_TEST=YES I87
SYS_ADAPTER_ANALOG_AC_DET 12 31 FUNC_TEST=YES
I62 =FTP_GND 7 10 FUNC_TEST=YES Place 5-10 GND TPs. I90 KBDLED_ANODE 28 30 FUNC_TEST=YES
I91
KBDLED_RETURN 28 30 FUNC_TEST=YES
I105
=I2C_DS1775_SDA 8 30 FUNC_TEST=YES
I79
LVDS_U0_P 53 56 FUNC_TEST=YES I106 =I2C_DS1775_SCL 8 30 FUNC_TEST=YES
I80
LVDS_U0_N 53 56 FUNC_TEST=YES
I81
LVDS_U1_P 53 56 FUNC_TEST=YES
CPU FAN
I82
LVDS_U1_N 53 56 FUNC_TEST=YES
I100
=PP5V_FAN1_PWR 10 31 FUNC_TEST=YES
I83
LVDS_U2_P 53 56 FUNC_TEST=YES
I98
FAN1_TACH 27 31 FUNC_TEST=YES Place within 25 mm
C I84
I85
LVDS_U2_N
CLKLVDS_U_P
53 56
53 56
FUNC_TEST=YES
FUNC_TEST=YES I97
FAN1_PWM
=FTP_GND
27 31
7 10
FUNC_TEST=YES
FUNC_TEST=YES
of fan connector. C
I119
I86
CLKLVDS_U_N 53 56 FUNC_TEST=YES
LVDS_L0_P FUNC_TEST=YES
LVDS
I11 53 56
I12
LVDS_L0_N 53 56 FUNC_TEST=YES Place within 25 mm
GPU FAN
I13
LVDS_L1_P 53 56 FUNC_TEST=YES of LVDS connector. I102
=PP5V_FAN2_PWR 10 31 FUNC_TEST=YES
I14
LVDS_L1_N 53 56 FUNC_TEST=YES I101
FAN2_TACH 27 31 FUNC_TEST=YES Place within 25 mm
I16
LVDS_L2_P 53 56 FUNC_TEST=YES I104
FAN2_PWM 27 31 FUNC_TEST=YES of fan connector.
I15
LVDS_L2_N 53 56 FUNC_TEST=YES I120
=FTP_GND 7 10 FUNC_TEST=YES
I17
CLKLVDS_L_P 53 56 FUNC_TEST=YES
I18
CLKLVDS_L_N 53 56 FUNC_TEST=YES
LVDS_DDC_CLK 51 56 FUNC_TEST=YES =PP3V3_PWRON_LEFT_ALS 10 31 FUNC_TEST=YES
ALS
I19 I70
LVDS_DDC_DATA ALS_0_OUT
Place within 25 mm
I20 51 56 FUNC_TEST=YES I68 25 31 FUNC_TEST=YES
=PP3V3_DDC_LCD ALS_GAIN_BOOST
of ALS connector.
I21 10 56 FUNC_TEST=YES I69 25 28 31 FUNC_TEST=YES
I63
PP3V3_LCD_CONN 56 FUNC_TEST=YES
SCCA
I72
SCCA_RXD 22 24 FUNC_TEST=YES Place within 25 mm
PPBUS_INVERTER 56 FUNC_TEST=YES SCCA_TXD_L 22 24 FUNC_TEST=YES of debug connector.
INVERTER
I22 I71
I23
PP5V_INV_SW 56 FUNC_TEST=YES Place within 25 mm
I25
BRIGHT_PWM 56 FUNC_TEST=YES of inverter connector.
BATT
BACKUP
I24
GND_INVERTER 56 FUNC_TEST=YES I73
=PPVIO_BU_BATT 10 31 FUNC_TEST=YES Place within 25 mm
I74
=PPVOUT_BU_BATT 10 31 FUNC_TEST=YES of battery connector.
I96
=PP5V_RUN_ODD 10 64 FUNC_TEST=YES
=PP5V_RUN_HDD FUNC_TEST=YES =PP5V_PWRON_RIGHT_USB FUNC_TEST=YES
RT USB
I117 10 64 I64 10 31
PP3V3R5V_RUN_HDD_LOGIC USB2_RIGHT_PORT_P
Place within 25 mm
I118 64 FUNC_TEST=YES I65 11 31 FUNC_TEST=YES
UATA_DD<15..0> USB2_RIGHT_PORT_N
of right USB connector.
6 63 64 FUNC_TEST=YES 11 31 FUNC_TEST=YES
B I32
I33
UATA_DMARQ 63 64 FUNC_TEST=YES
I66
B
I35
UATA_DSTROBE 63 64 FUNC_TEST=YES
UATA_DMACK_L FUNC_TEST=YES Place within 50 mm =PP5V_PWRON_LEFT_USB FUNC_TEST=YES
LT USB
I34 63 64 I114 10 31
Place within 25 mm
UATA
I36
UATA_DA<2..0> 6 63 64 FUNC_TEST=YES of ODD/HDD connector. I116
USB2_LEFT_PORT_P 11 31 FUNC_TEST=YES
UATA_CS0_L USB2_LEFT_PORT_N
of left USB connector.
I38 6 63 64 FUNC_TEST=YES I115 11 31 FUNC_TEST=YES
I37
UATA_CS1_L 63 64 FUNC_TEST=YES
I40
UATA_RESET_L 63 64 FUNC_TEST=YES
I39
UATA_HSTROBE 63 64 FUNC_TEST=YES
I41 UATA_STOP 63 64 FUNC_TEST=YES
I42 UATA_INTRQ 63 64 FUNC_TEST=YES
I75
PP5V_PWRON_AUDIO_PVDD 74 FUNC_TEST=YES
I60
PP5V_PWRON_AUDIO_AVDD 74 FUNC_TEST=YES
I59
PP3V3_PWRON_AUDIO_AVDD 74 FUNC_TEST=YES
I61 =PP3V3_RUN_AUDIO 10 74 FUNC_TEST=YES
I44
=I2C_AUDIO_SCL 8 74 FUNC_TEST=YES
I46 =I2C_AUDIO_SDA 8 74 FUNC_TEST=YES
I48 I2S0_MCLK 6 74 FUNC_TEST=YES
I47 I2S0_BITCLK 6 74 FUNC_TEST=YES
I50
I2S0_SYNC 6 74 FUNC_TEST=YES
I49 I2S0_SB_TO_DEV_DTO 6 74 FUNC_TEST=YES
AUDIO
I51 I2S0_DEV_TO_SB_DTI 22 74 FUNC_TEST=YES

I53
AUDIO_LO_MUTE_L 22 74 FUNC_TEST=YES Place within 25 mm
I52
AUDIO_SPKR_MUTE_L 22 74 FUNC_TEST=YES of audio connector. Functional Test Points
I56
AUDIO_CODEC_RESET_L 22 74 FUNC_TEST=YES
A I55
AUDIO_SPDIFRX_RESET_L
AUDIO_LO_DET_L
22 74
22 74
FUNC_TEST=YES
FUNC_TEST=YES
SYNC_MASTER=MARIAS

A
I57
I58
AUDIO_LI_DET_L 22 74 FUNC_TEST=YES
I107 AUDIO_LO_OPTICAL_PLUG_L 22 74 FUNC_TEST=YES PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
I108 AUDIO_LI_OPTICAL_PLUG_L 22 74 FUNC_TEST=YES
I109 AUDIO_I2S_DTIB_SEL 22 74 FUNC_TEST=YES
I110 AUDIO_EXT_MCLK_SEL 22 74 FUNC_TEST=YES
I111 AUDIO_GPIO_11 22 74 FUNC_TEST=YES
I112
GND_AUDIO_AGND 74 FUNC_TEST=YES SIZE DRAWING NUMBER REV.
I113
GND_AUDIO_PGND 74 FUNC_TEST=YES
APPLE COMPUTER INC.
D 051-6839 F
SCALE SHT OF
NONE 7 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL DIFFERENTIAL_PAIR
I2C I2C I2C_PMU_SMB_SCL 8

SouthBridge I2C Bus
I2C I2C I2C_PMU_SMB_SDA 8
I2C I2C I2C_PMU_SCL 8
I2C I2C I2C_PMU_SDA 8 10 =PPI2C_I2_SB
I2C_NB I2C I2C I2C_I2_NB_SCL 8
I2C_NB I2C I2C I2C_I2_NB_SDA 8
I2 R08401 1
R0841 Audio Board
I2C I2C I2C_I2_SB_SCL 8 1K 1K
U2100 5% 5% JA000
I2C I2C I2C_I2_SB_SDA 8 1/16W 1/16W
D I2C I2C I2C_GPU_TMDS_SCL 8

(MASTER) MF-LF
402 2
MF-LF Codec
2 402 SPDIF
(Write: 0x8C Read: 0x8D)
(Write: 0x22 Read: 0x23)
D
I2C I2C I2C_GPU_TMDS_SDA 8 22 =I2C_I2_SB_SCL 8 I2C_I2_SB_SCL =I2C_AUDIO_SCL 7 74
MAKE_BASE=TRUE
22 =I2C_I2_SB_SDA 8 I2C_I2_SB_SDA =I2C_AUDIO_SDA 7 74
MAKE_BASE=TRUE
Page Notes
Power aliases required by this page:
(NONE)
Signal aliases required by this page:
(NONE)
BOM options provided by this page:
- GOV_I2C / GOV_I2C_BYPASS
Allows bypassing Governator I2C bus.
Most devices are connected directly to
PMU unstead. One ADT7467 connects to NB
PMU I2C Bus NorthBridge I2C Bus
I2C bus 1 to resolve address conflict.
- MMM_PWR_ALL / MMM_PWR_PWRON
Selects whether MMM MCU is powered all 10 =PPI2C_SYS1 10 =PPI2C_I2_NB
the time or only when the system is on.
ALL moves the MCU to the PMU I2C bus so
it can be monitored by in shutdown.
PMU R08201 1
R0821 I2 R08301 1
R0831 DIMMs
NOTE: Neither option is necessary when 1K 1K 2.0K 2.0K
U1300 5% 5% U2100 5% 5% J5000A / J5000B
C MMM_MCU_PMU BOM option is selected.
(MASTER)
1/16W
MF-LF
402 2
1/16W
MF-LF
2 402
(MASTER)
1/16W
MF-LF
402 2
1/16W
MF-LF
2 402
(Write: 0xA0 / 0xA2,
Read: 0xA1 / 0xA3)
C
25 =I2C_PMU_SCL 8 I2C_PMU_SCL 22 =I2C_I2_NB_SCL 8 I2C_I2_NB_SCL =I2C_SODIMM_SCL 40 41
MAKE_BASE=TRUE MAKE_BASE=TRUE
25 =I2C_PMU_SDA 8 I2C_PMU_SDA 22 =I2C_I2_NB_SDA 8 I2C_I2_NB_SDA =I2C_SODIMM_SDA 40 41
ADT7467
U3000
PMU SMBus (Write: 0x5C Read: 0x5D)
=I2C_ADT7467_SCL 27
10 =PPI2C_SYS0
=I2C_ADT7467_SDA 27
1 1
PMU R0850
7.15K
R0851
7.15K
Battery Conn
U1300
(MASTER)
1%
1/16W
MF-LF
1%
1/16W
MF-LF
J790
DS1775
402 2 2 402 On Trackpad Flex
25 =I2C_PMU_SMB_SCL 8 I2C_PMU_SMB_SCL =I2C_BATT_SCL 12
MAKE_BASE=TRUE
25 =I2C_PMU_SMB_SDA 8 I2C_PMU_SMB_SDA =I2C_BATT_SDA 12 =I2C_DS1775_SCL 7 30
MAKE_BASE=TRUE
=I2C_DS1775_SDA 7 30
B GPU I2C Bus B
10 =PPI2C_GPU
GPU R08421 1
R0843 EXT TMDS/M
1K 1K
U5700 5% 5% U6700
1/16W 1/16W
(MASTER) MF-LF MF-LF (Write: 0x70 Read: 0x71)
402 2 2 402
51 =I2C_GPU_TMDS_SCL 8 I2C_GPU_TMDS_SCL =I2C_SI_M_SCL 54

MAKE_BASE=TRUE
51 =I2C_GPU_TMDS_SDA 8 I2C_GPU_TMDS_SDA =I2C_SI_M_SDA 54
MAKE_BASE=TRUE
EXT TMDS/S
U6800
=I2C_SI_S_SCL 55
=I2C_SI_S_SDA 55
I2C Connections
A SYNC_MASTER=MARIAS

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 8 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
10 =PPJTAG_CPU
NO STUFF
R09801 R09811
10K 10K
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 2 402 2
CPU0
D
JTAG_CPU_TDI
MAKE_BASE=TRUE
=JTAG_CPU0_TDI 34 34 =JTAG_CPU0_TDO TP_JTAG_CPU_TDO
MAKE_BASE=TRUE D
1 1
R0982 R0983 =JTAG_CPU0_TMS 34
10K 10K
5% 5% =JTAG_CPU0_TRST_L 34
PMU (BOOTBANGER) 1/16W
MF-LF
1/16W
MF-LF =JTAG_CPU0_TCK 34
=JTAG_BBANGER_TDI 2 402 2 402

25
25 =JTAG_BBANGER_TMS JTAG_CPU_TMS
MAKE_BASE=TRUE
Nets not requiring TPs due to JTAG
25 =JTAG_BBANGER_TRST_L JTAG_CPU_TRST_L
MAKE_BASE=TRUE
25 =JTAG_BBANGER_TCK JTAG_CPU_TCK
MAKE_BASE=TRUE
NO STUFF
R09841 1
R0985
200 10K
5% 5%
1/16W 1/16W I76
MAXBUS_DATA<63..0> 21 32 33 NO_TEST=YES
MF-LF MF-LF
402 2 2 402 I77
MAXBUS_ADDR<31..0> 32 33 NO_TEST=YES
MAXBUS_CI_L NO_TEST=YES
MAXBUS
I78 32 33
I79
MAXBUS_GBL_L 32 33 NO_TEST=YES
I80 MAXBUS_TBST_L 32 33 NO_TEST=YES
I81 MAXBUS_TSIZ<2..0> 32 33 NO_TEST=YES
I82
MAXBUS_TT<4..0> 32 33 NO_TEST=YES
I83
MAXBUS_WT_L 32 33 NO_TEST=YES
I85 MAXBUS_DTI<2..0> 32 33 NO_TEST=YES
C 10 =PP3V3_PWRON_JTAG_ASIC C
6
RP0990
10K
5%
1/16W
SM-LF
3
I2
JTAG_I2_TDI =JTAG_I2_TDI 22 22 =JTAG_I2_TDO TP_JTAG_I2_TDO
8 MAKE_BASE=TRUE MAKE_BASE=TRUE
RP0990 =JTAG_I2_TMS
10K 22
5% =JTAG_I2_TRST_L 22
1/16W
SM-LF =JTAG_I2_TCK 22
1
JTAG_ASIC_TMS
MAKE_BASE=TRUE
JTAG_ASIC_TRST_L
MAKE_BASE=TRUE
JTAG_ASIC_TCK
MAKE_BASE=TRUE
R09901 2
ENET_MDC NO_TEST=YES
1K
5%
RP0990 I86
ENET_MDIO
11 65
NO_TEST=YES
1/16W 10K I87 11 65
MF-LF 5% ENET_TXD<7..0> 11 NO_TEST=YES

1/16W I88
402 2
SM-LF I89 ENET_TX_EN 11 NO_TEST=YES
ENET
7
ENET_TX_ER 11 NO_TEST=YES
B I90
I92 ENET_RXD<7..0> 11 65 NO_TEST=YES B

I91 ENET_RX_DV 11 65 NO_TEST=YES
I93 ENET_RX_ER 11 65 NO_TEST=YES
I94
ENET_COL 11 65 NO_TEST=YES
I95 ENET_CRS 11 65 NO_TEST=YES
I96 FW_D_R<7..0> 6 68 NO_TEST=YES
FIREWIRE
I97 FW_D<7..0> 6 69 NO_TEST=YES
I98
FW_CTL_R<1..0> 68 71 NO_TEST=YES
I99
FW_CTL<1..0> 69 71 NO_TEST=YES
I100
FW_LPS_R 68 71 NO_TEST=YES
I101 FW_LPS 69 71 NO_TEST=YES
I103 FW_LREQ_R 68 71 NO_TEST=YES
I102 FW_LREQ 69 71 NO_TEST=YES
VESTA
TP_JTAG_VESTA_TDI =JTAG_VESTA_TDI 18 18 =JTAG_VESTA_TDO TP_JTAG_VESTA_TDO
=JTAG_VESTA_TMS 18
=JTAG_VESTA_TRST_L 18
=JTAG_VESTA_TCK 18
TP_JTAG_VESTA_TMS
MAKE_BASE=TRUE
JTAG_VESTA_TRST_L
MAKE_BASE=TRUE
JTAG Connections
TP_JTAG_VESTA_TCK
A MAKE_BASE=TRUE
SYNC_MASTER=MARIAS

A
1
R0950
10K THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
5% PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1/16W AGREES TO THE FOLLOWING
MF-LF
402 2 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 9 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GND =FTP_GND 7
MAKE_BASE=TRUE
VOLTAGE=0V
7 MIN_NECK_WIDTH=0.2 mm
13 =PP14VR24V_ALL_PBUS_A PP24V_ALL_PBUSA =PPVIN_ALL_LTC1625 14 18 =PP3V3_VESTA_REG PP3V3_VESTA =PP3V3_VESTA_1V2REG 18
13 =PPVBATT_BATT_PBUSA VOLTAGE=24V =PPVIN_ALL_BATT_CHGR 13 VOLTAGE=3.3V =PP3V3_VESTA_2V5REG 18
MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
31 7 =PPVOUT_BU_BATT MIN_NECK_WIDTH=0.25 mm =PPVIN_ALL_LTC3707 15 MIN_NECK_WIDTH=0.25 mm =PP3V3_VESTA 18 65 66 67
=PP24V_PBUSA_HOLDUP_CAPS 31 =PP3V3_FW 69 70
=PP3V3_ENETFW 69
14 =PP12V8_LTC1625_VREG 7 PP12V8_ALL_PBUSB =PP12V8_PBUS_PMU_SUPPLY 14

MAKE_BASE=TRUE
13 =PPVBATT_BATT_PBUSB VOLTAGE=12.8V =PPVIN_ALL_MAX1715 16
MIN_LINE_WIDTH=0.5 mm 18 =PP2V5_VESTA_LDO PP2V5_VESTA =PP2V5_VESTA 18
D 31 7 =PPVIO_BU_BATT MIN_NECK_WIDTH=0.25 mm =PP12V8_PBUSB_HOLDUP_CAPS

=PPVIN_LTC1778_GPU 45
31 MAKE_BASE=TRUE
VOLTAGE=2.5V
=PP2V5_ENETFW 66 69 D
MIN_NECK_WIDTH=0.25 mm
=PPBUS_FWPWRSW 18
18 =PP1V2_VESTA_REG PP1V2_VESTA =PP1V2_VESTA 18
=PPVIN_CPUVCORE_MAX1717 36 MAKE_BASE=TRUE
VOLTAGE=1.2V =PP1V2_ENETFW 66 69
=PPBUS_INVERTER 56 MIN_LINE_WIDTH=0.5 mm
18 =PPBUS_FW_FET PPFW_CABLE_POWER =PPFW_PHY_CPS 69
MAKE_BASE=TRUE
VOLTAGE=33V =PPFW_PORT1
XW1019
SM
MIN_NECK_WIDTH=0.25 mm =PPFW_PORT2
70
70
1 2 PPBUS_DVI_PWRSW =PPFW_P3V3VESTA 18
MAKE_BASE=TRUE
VOLTAGE=12.8V
MIN_LINE_WIDTH=0.25 mm 20 =PP1V5_PWRON_I2PLL_LDO PP1V5_PWRON_I2PLL =PP1V5_PWRON_I2_PLL 19
MIN_NECK_WIDTH=0.15 mm MAKE_BASE=TRUE
VOLTAGE=1.5V =PP1V5_PWRON_I2_USBPLL 72
=PPBUS_DVI_PWRSW 57 36 =PPVCORE_CPU_REG PPVCORE_RUN_CPU =PPVCORE_CPU0 35 MIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.3V
12 =PPVBATT_ISNS_N PPVBATT_BATT =PPVBATT_BATT 13 MIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
=PPVBATT_BATTERY_PMU_SUPPLY 14 XW1013
SM 37 =PPVOUT_CPU0_AVDD PPAVDD_CPU0 =PPAVDD_CPU0 35
MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE
7 1 2 PPVCORE_CPU_ADT7467 VOLTAGE=1.22V
31 =PP24V_ADAPTER_CONN PP24V_ADAPTER =PP24V_ADAPTER_RAW 12 MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE VOLTAGE=1.3V MIN_NECK_WIDTH=0.25 mm
VOLTAGE=24V =PP24V_ADAPTER_PMU_SUPPLY 14 MIN_LINE_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.15 mm
=PPVCORE_CPU_ADT7467 27
12 =PPVBATT_BATT_VSNS PPVBATT_BATT_CHRG_VSNS =PPVIN_BATT_CHRG_VSNS 13

MAKE_BASE=TRUE
VOLTAGE=12.8V =PP5V_RUN_HDDFET PP5V_RUN_HDD =PP5V_RUN_HDD
XW1050
SM
15
MAKE_BASE=TRUE
VOLTAGE=5V
7 64
14 =PP4V85_ALL_VREG PP4V85_ALL =PP4V85_ALL_A29_DET 12 15 =PP5V_PWRON_REG 1 2 7 PP5V_PWRON =PP5V_PWRON_LTC1625_EXTVCC 14 MIN_NECK_WIDTH=0.25 mm
MAKE_BASE=TRUE MAKE_BASE=TRUE 7
VOLTAGE=4.85V PP5V_PWRON_REG VOLTAGE=5V =PP5V_PWRON_PMU_SUPPLY 14 15 =PP5V_RUN_RUNFET PP5V_RUN =PP5V_RUN_ODD 7 64
MIN_LINE_WIDTH=0.38 mm MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V MIN_NECK_WIDTH=0.25 mm =PP5V_PWRON_LTC3707_EXTVCC 15 VOLTAGE=5V =PPBU_RUN_FW 18
MIN_NECK_WIDTH=0.25 mm =PP5V_PWRON_RUNFET 15 MIN_NECK_WIDTH=0.25 mm =PP5V_RUN_FANPWM 27
C =PP5V_PWRON_PWRSEQ 26
=PP5V_PWRON_MAX1715_VDD 16
=PP5V_RUN_KEYBRD_LED
=PP5V_RUN_DVI_DDC
28
57
C
=PP5V_PWRON_TPS2211 61 =PP5V_FAN1_PWR 7 31
7
14 =PP3V3_ALL_VREG PP3V3_ALL =PP3V3_ALL_AC_DETECT 12 =PP5V_PWRON_LTC1778_GPU_EXTVCC 45 =PP5V_FAN2_PWR 7 31
MAKE_BASE=TRUE
VOLTAGE=3.3V =PP3V3_ALL_A29_DET 12 =PP5V_PWRON_GPUVCORE_PWRPLAY 45 =PP5V_RUN_PWRSEQ 26
MIN_NECK_WIDTH=0.25 mm =PP3V3_ALL_BATT_CHGR 13 =PP5V_PWRON_CPUVCORE_PWRSEQ 36
=PP3V3_ALL_LTC1625_SW 14 =PP5V_PWRON_CPUVCORE_VDD 36
=PPI2C_SYS0 8 =PP5V_PWRON_LEFT_USB 7 31 15 =PP5V_TPAD_FET PP5V_TPAD =PP5V_TPAD 30
MAKE_BASE=TRUE
=PP3V3_ALL_PBUS_ILIM 13 =PP5V_PWRON_AUDIO_AVDD 74 VOLTAGE=5V
=PP3V3_ALL_HALL_EFFECT 30 =PP5V_PWRON_AUDIO_PVDD 74 MIN_NECK_WIDTH=0.15 mm
=PP3V3_ALL_PMU 24 25 =PP5V_PWRON_RIGHT_USB 7 31
=PP3V3_ALL_PWRSEQ 26 =PP5V_PWRON_SLEEPLED 24
=PP3V3_ALL_BATT0_DET 12 =PP5V_PWRON_TRACKPAD 15
=PP3V3_ALL_DEBUG 24 =PP5V_PWRON_INVERTER 56
XW1033
SM
25 PP3V3_ALL_PMU_AVCC =PPVREF_PMU 25 15 =PP3V3_PWRON_REG 1 2 7 PP3V3_PWRON =PP3V3_PWRON_MMM 29 15 =PP3V3_RUN_RUNFET PP3V3_RUN =PP3V3_RUN_SI 54 55
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
=PP3V3_BATT_IMON 12 PP3V3_PWRON_REG VOLTAGE=3.3V =PP3V3_PWRON_RUNFET 15 VOLTAGE=3.3V =PP3V3_RUN_KEYBRD_LED 28
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm
VOLTAGE=3.3V MIN_NECK_WIDTH=0.25 mm =PP3V3_PWRON_LTC3412 17 MIN_NECK_WIDTH=0.25 mm =PP3V3_PCI_AIRPORT 60
MIN_NECK_WIDTH=0.25 mm =PP3V3_PWRON_TPS2211 61 =PP3V3_RUN_PCI1510_R 61
22 =PP3V3_AUDIO_MUTESEQ
R1033 =PP3V3_ADT7467 27 =PP3V3_RUN_HDD 64
8 =PPI2C_I2_NB 37 =PPVIN_CPU0_AVDD
=PP3V3_GPU 1
0 2 PP3V3_GPU =PP3V3_AGP =PPI2C_SYS1
=PP3V3_PWRON_CPUVCORE_VID 36
=PP3V3_RUN_PWRSEQ
=PP3V3_GPU_CLOCKS 52
10 43 44 8 26
MAKE_BASE=TRUE =PP3V3_PWRON_CPUVCORE_OFFSET 36 =PP3V3_RUN_FWPORTPWRSW 18
5% VOLTAGE=3.3V =PP3V3_GPU_VDDR3 47 9 =PP3V3_PWRON_JTAG_ASIC 61 =TPS2211_SHDN_L
B 1/8W
MF-LF
805
MIN_NECK_WIDTH=0.25 mm =PP3V3_GPU_GPIOS 51 53 22 =PP3V3_PWRON_I2_MISC
=PP3V3_PWRON_BT 60
=PP3V3_PWRON_AUDIO_AVDD 74
74 7 =PP3V3_RUN_AUDIO
=PP3V3_RUN_FANTACH
=PP3V3_GPU
27
10
B
=PP3V3_GPU_PWRSEQ 52 28 =PP3V3_PWRON_RT_ALS 62 =PPVIO_PCI_USB2
=PP3V3_PWRON_PMU 25 =PPI2C_GPU 8
=PPVIN_GPU_LVDDR_LDO 52 41 40 =PP3V3_PWRON_VDDSPD 62 =PP3V3_PCI_USB2
=PP3V3_PWRON_MODEM 30 =PP3V3_DDC_DVI 57
58 =PP3V3_PCI_ROM 23 =PP3V3_PCI_ZDB
=PP3V3_PWRON_LEFT_ALS 7 31 =PP3V3_DDC_LCD 7 56
52 =PP2V8_GPU_LVDDR_LDO PP2V8_GPU_LVDDR =PP2V8_GPU_LVDS_IO 47 65 =PP2V5R3V3_PWRON_I2_ENET 8 =PPI2C_I2_SB
MAKE_BASE=TRUE =PP3V3_PWRON_DS1775 30 =PP3V3_PCI 59
VOLTAGE=2.8V 22 =PP3V3_I2_PCISLOTEGPIOS
MIN_LINE_WIDTH=0.38 mm =PP3V3_PWRON_VGASYNC 57
=PP3V3_PWRON_I2_AGPPCI
R1025 MIN_NECK_WIDTH=0.25 mm 19
=PP3V3_PWRON_LCD 56 17 =PP2V5_RUN_RUNFET PP2V5_RUN =PP2V5_RUN_PCI1510 61
0 19 =PP3V3_PWRON_I2_IO1 MAKE_BASE=TRUE
10 =PP2V5_GPU 1 2 PP2V5_GPU =PP2V5_GPU_LVDS_IO 47 =PP3V3_PWRON_INVERTER 56 VOLTAGE=2.5V =PP2V5_GPU 10
MAKE_BASE=TRUE 19 =PP3V3_PWRON_I2_IO2 MIN_LINE_WIDTH=0.5 mm
5% VOLTAGE=2.5V =PP2V5_GPU_PVDD 51 =PP2V7R5V5_PWRON_I2VCORE 20 MIN_NECK_WIDTH=0.25 mm
1/8W MIN_LINE_WIDTH=0.5 mm 26 =PP3V3_PWRON_PWRSEQ
MF-LF MIN_NECK_WIDTH=0.25 mm =PP2V5_GPU_PWRSEQ 52 =PP3V3_PWRON_I2_MAXBUS 19
805 66 =PP3V3_ENET
=PP2V5_GPU_A2VDD =PP3V3_PWRON_USB2
R1015
53
XW1025
SM
73
16 =PP1V8_RUN_RUNFET PP1V8_RUN
MAKE_BASE=TRUE
=PP1V8_GPU 10
1
0 2 1 2
VOLTAGE=1.8V =PP1V5R1V8_MAXBUS 21 32 33 34
10 =PP1V5_GPU PP1V5_GPU =PP1V5_AGP 43 44 47 17 =PP2V5_PWRON_REG 7 PP2V5_PWRON =PP2V5_PWRON_RUNFET 17 MIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE MAKE_BASE=TRUE MIN_NECK_WIDTH=0.25 mm =PP1V5R1V8_RUN_I2_MAXBUS 32
5% VOLTAGE=1.5V =PP1V5_GPU_VDD15 46 PP2V5_PWRON_REG VOLTAGE=2.5V =PP2V5_ENET 67
1/8W MIN_LINE_WIDTH=0.38 mm MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm =PPJTAG_CPU 9
MF-LF MIN_NECK_WIDTH=0.25 mm =PP1V5_GPU_PWRSEQ 52 VOLTAGE=2.5V MIN_NECK_WIDTH=0.25 mm =PPVIN_PWRON_I2PLLVDD 20
805 MIN_LINE_WIDTH=0.5 mm =PP1V8_RAM_I2_VREF 38
=PP1V5_GPU_DVO 47 MIN_NECK_WIDTH=0.25 mm
R1018 =PP1V8_RUN_TBEN_SYNC 21
0
XW1018
SM
10 =PP1V8_GPU 1 2 PP1V8_GPU =PP1V8_GPU_PANEL_IO 47
MAKE_BASE=TRUE 16 =PP1V8_PWRON_REG 1 2 7 PP1V8_PWRON =PP1V8_PWRON_RUNFET 16
5% VOLTAGE=1.8V =PP1V8_GPU_DVO 47 MAKE_BASE=TRUE 16 =PP1V5_RUN_RUNFET PP1V5_RUN =PP1V5_GPU 10
1/8W MIN_LINE_WIDTH=0.5 mm PP1V8_PWRON_REG VOLTAGE=1.8V =PP1V8_PWRON_DDR2 40 41 MAKE_BASE=TRUE
MF-LF MIN_NECK_WIDTH=0.25 mm =PP1V8R2V5_GPU_FB_VIO 47 48 MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm VOLTAGE=1.5V
805 VOLTAGE=1.8V MIN_NECK_WIDTH=0.25 mm =PP1V8_PWRON_I2_RAM 38 MIN_LINE_WIDTH=0.5 mm
=PP1V8_FB_VDD 49 50 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm
53 =PP1V8_GPU_AVDD MIN_NECK_WIDTH=0.25 mm =PP1V5R1V8_PWRON_I2_MAXBUS 32
=PP1V8_FB_VDDQ
53 =PP1V8_GPU_TPVDD
=PP1V8_GPU_PWRSEQ
49 50
52
XW1015
SM
XW1012 =PP1V8_GPU_MEMVMODE 48 16 =PP1V5_PWRON_REG 1 2 PP1V5_PWRON

MAKE_BASE=TRUE
=PP1V5_PWRON_RUNFET 16 Power Synonyms
SM PP1V5_PWRON_REG VOLTAGE=1.5V =PP1V5_I2_AGP 43
A 45 =PPVCORE_GPU_REG
PPVCORE_GPU_REG
1 2 7 PPVCORE_RUN_GPU
MAKE_BASE=TRUE
VOLTAGE=1.3V
=PP1V05R1V3_GPU_VCORE 46
MAKE_BASE=TRUE
VOLTAGE=1.5V
SYNC_MASTER=MARIAS

A
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.5 mm
VOLTAGE=1.3V MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
MIN_NECK_WIDTH=0.25 mm PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
XW1017
SM
20 =PPVCORE_PWRON_I2_REG 1 2 PPVCORE_PWRON_I2 =PPVCORE_PWRON_I2 19
MAKE_BASE=TRUE III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
PPVCORE_PWRON_I2_REG VOLTAGE=1.5V
VOLTAGE=1.5V MIN_NECK_WIDTH=0.25 mm SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6839 F
SCALE SHT OF
NONE 10 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I2S0 Series Rs CPU Clocks PCI
RP1150 R1110 R1120
33 10
32 MAXBUS_CLK_CPU0_R 1 2 MAXBUS_CLK_CPU0 =MAXBUS_CPU0_CLK 33 22
5% MAKE_BASE=TRUE 59 TP_PCI_CLK33M_SLOTA_R PCI_CLK33M_ZDB_R 1 2 PCI_CLK33M_ZDB =PCI_CLK33M_ZDB_IN 23
5% MAKE_BASE=TRUE MAKE_BASE=TRUE
6 =RP1150P1 1 8 =RP1150P8 6 1/16W 5%
MF-LF 1/16W
6 =RP1150P2 2 7 =RP1150P7 6 402 MF-LF
402
6 =RP1150P3 3 6 =RP1150P6 6 MAXBUS_TBEN_SYNC
6 =RP1150P4 4 5 =RP1150P5 6
R1111 MAXBUS_TBEN_SYNC
10 R1130
1/16W 32 TP_MAXBUS_CLK_CPU1_R MAXBUS_CLK_CPU1_R 1 2 MAXBUS_CLK_TBEN_SYNC =SYSCLK_TBEN_SYNC 21
SM-LF MAKE_BASE=TRUE MAKE_BASE=TRUE
1
22 2
5% 59 TP_PCI_CLK33M_SLOTD_R PCI_CLK33M_TBEN_SYNC_R PCI_CLK33M_TBEN_SYNC =CLK33M_TBEN_SYNC 21
One resistor for each of: 1/16W MAKE_BASE=TRUE MAKE_BASE=TRUE
D - I2S0_SB_TO_DEV_DTO(_R)
MF-LF
402
5%
1/16W
MF-LF
D
- I2S0_MCLK(_R) 402
- I2S0_BITCLK(_R)
- I2S0_SYNC(_R) R1135
USB Controller Mux 23 =PCI_CLK33M_ZDBOUT_R<0> PCI_CLK33M_AIRPORT_R 1
22 2 PCI_CLK33M_AIRPORT =PCI_CLK33M_AIRPORT 60
5%
I2S1 Series Rs 1/16W
MF-LF
402
RP1151 R1160 USB2_NEC R1170 USB1P1_NEC 59 PCI_SLOTA_REQ_L 6
PCI_AIRPORT_REQ_L =PCI_AIRPORT_REQ_L 60
33 1
0 2 1
0 2
MAKE_BASE=TRUE
31 7 USB2_LEFT_PORT_P USB2_NEC_LEFT_PORT_P 6 11 60 USB_BT_P USB_NEC_BT_P 6 11 6
5% 59 PCI_SLOTA_GNT_L PCI_AIRPORT_GNT_L =PCI_AIRPORT_GNT_L 60
5% 5% MAKE_BASE=TRUE
=RP1151P1 1 8 =RP1151P8
6
2 7
6 1/16W
MF-LF R1161 USB2_I2
1/16W
MF-LF R1171 USB1P1_I2 59 22 PCI_SLOTA_INT_L PCI_AIRPORT_INT_L =PCI_AIRPORT_INT_L 60
6 =RP1151P2 =RP1151P7 6
1
402 0 2 USB2_I2_LEFT_PORT_P
402
1
0 2 USB_I2_BT_P
MAKE_BASE=TRUE
3 6 NET_SPACING_TYPE=USB2 6 11 NET_SPACING_TYPE=USB2 6 11
6 =RP1151P3 =RP1151P6 6 NET_PHYSICAL_TYPE=USB2 NET_PHYSICAL_TYPE=USB2 62 61 60 59 58 PCI_AD<17> =PCI_AIRPORT_IDSEL 60
DIFFERENTIAL_PAIR=USB2_LT_PORT 5% DIFFERENTIAL_PAIR=USB_BT 5% MAKE_BASE=TRUE
6 =RP1151P4 4 5 =RP1151P5 6 1/16W 1/16W
MF-LF MF-LF 25 11 PCI_RESET_L =PCI_AIRPORT_RESET_L 60
1/16W 402 402 MAKE_BASE=TRUE
SM-LF R1162 USB2_NEC R1172 USB1P1_NEC
One resistor for each of:
USB2_LEFT_PORT_N
0 0
31 7 1 2 USB2_NEC_LEFT_PORT_N 6 11 60 USB_BT_N 1 2 USB_NEC_BT_N 6 11
R1136
- I2S1_SB_TO_DEV_DTO(_R)
5% 5% 22
- I2S1_MCLK(_R) 1/16W
R1163 1/16W
R1173 23 =PCI_CLK33M_ZDBOUT_R<1> PCI_CLK33M_CBUS_R 1 2 PCI_CLK33M_CBUS =PCI_CLK33M_CBUS 61
MF-LF USB2_I2 MF-LF USB1P1_I2 MAKE_BASE=TRUE MAKE_BASE=TRUE
- I2S1_BITCLK(_R) 402 0 402 0 5%
NET_SPACING_TYPE=USB2 1 2 USB2_I2_LEFT_PORT_N 6 11 NET_SPACING_TYPE=USB2 1 2 USB_I2_BT_N 6 11 1/16W
- I2S1_SYNC(_R) NET_PHYSICAL_TYPE=USB2 NET_PHYSICAL_TYPE=USB2 MF-LF
DIFFERENTIAL_PAIR=USB2_LT_PORT 5% DIFFERENTIAL_PAIR=USB_BT 5% 402
1/16W 1/16W 6
MF-LF MF-LF 59 PCI_SLOTD_REQ_L PCI_CBUS_REQ_L =PCI_CBUS_REQ_L 61
402 402 MAKE_BASE=TRUE
GPU R1164 USB2_NEC R1174 USB1P1_NEC 59 PCI_SLOTD_GNT_L
6
PCI_CBUS_GNT_L =PCI_CBUS_GNT_L 61
0 0 MAKE_BASE=TRUE
USB2_RIGHT_PORT_P USB2_NEC_RIGHT_PORT_P USB_TPAD_P USB_NEC_TPAD_P
R1140 31 7 1 2 6 11 30 7 1 2 6 11
59 22 PCI_SLOTD_INT_L PCI_CBUS_INT_L =PCI_CBUS_INT_L 61
AGP_CLK66M_GPU_R
22 AGP_CLK66M_GPU
5% 5% MAKE_BASE=TRUE
43 1 2 44 1/16W
R1165 1/16W
R1175
C 5%
1/16W
MF-LF
NET_SPACING_TYPE=USB2
NET_PHYSICAL_TYPE=USB2
1
MF-LF
402 0 2
USB2_I2
USB2_I2_RIGHT_PORT_P 6 11 NET_SPACING_TYPE=USB2
NET_PHYSICAL_TYPE=USB2
MF-LF
402
1
0 2
USB1P1_I2
USB_I2_TPAD_P 6 11
62 61 60 59 58
25 11
PCI_AD<20>
MAKE_BASE=TRUE
PCI_RESET_L
=PCI_CBUS_IDSEL
=PCI_CBUS_RESET_L
61
61
C
402 DIFFERENTIAL_PAIR=USB2_RT_PORT 5% DIFFERENTIAL_PAIR=USB_TPAD 5% MAKE_BASE=TRUE
1/16W 1/16W
25 11 PCI_RESET_L =AGP_GPU_RESET_L 44 MF-LF MF-LF
MAKE_BASE=TRUE 402 402
R1166 USB2_NEC R1176 USB1P1_NEC R1137
AGP_VREF =I2_AGP_VREF 43
1
0 2 1
0 2 1
22 2
MAKE_BASE=TRUE 31 7 USB2_RIGHT_PORT_N USB2_NEC_RIGHT_PORT_N 6 11 30 7 USB_TPAD_N USB_NEC_TPAD_N 6 11 23 =PCI_CLK33M_ZDBOUT_R<2> PCI_CLK33M_USB2_R PCI_CLK33M_USB2 =PCI_CLK33M_USB2 62
VOLTAGE=0.75V =AGP_VREF 44 MAKE_BASE=TRUE MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.25 mm 5% 5% 5%
MIN_NECK_WIDTH=0.15 mm =GPU_AGP_VREF 44 1/16W
R1167 1/16W
R1177 1/16W
MF-LF USB2_I2 MF-LF USB1P1_I2 MF-LF
1
402 0 2
402
1
0 2
402
NET_SPACING_TYPE=USB2 USB2_I2_RIGHT_PORT_N 6 11 NET_SPACING_TYPE=USB2 USB_I2_TPAD_N 6 11
NET_PHYSICAL_TYPE=USB2 NET_PHYSICAL_TYPE=USB2 22 PCI_SLOTE_REQ_L PCI_USB2_REQ_L =PCI_USB2_REQ_L 62
51 TP_EXTTMDS_RESET_L SI_TMDS_RESET_L =SI_TMDS_RESET_L 54 55 DIFFERENTIAL_PAIR=USB2_RT_PORT 5% DIFFERENTIAL_PAIR=USB_TPAD 5% MAKE_BASE=TRUE
MAKE_BASE=TRUE 1/16W 1/16W
MF-LF MF-LF 22 PCI_SLOTE_GNT_L PCI_USB2_GNT_L =PCI_USB2_GNT_L 62
402 402 MAKE_BASE=TRUE
22 PCI_SLOTE_INT_L PCI_USB2_INT_L =PCI_USB2_INT_L 62
MAKE_BASE=TRUE
62 61 60 59 PCI_AD<21> =PCI_USB2_IDSEL 62
MAKE_BASE=TRUE
25 11 PCI_RESET_L =PCI_USB2_RESET_L 62
MAKE_BASE=TRUE
23 =PCI_CLK33M_ZDBOUT_R<3> TP_PCI_CLK33M_ZDBOUT3
MAKE_BASE=TRUE
USB Port Assignments
USB2_I2_LEFT_PORT_P USB2_I2_P<0> USB2_NEC_LEFT_PORT_P USB2_NEC_P<0>
11 6
MAKE_BASE=TRUE
72 11 6
MAKE_BASE=TRUE
73
PMU Connections
11 6 USB2_I2_LEFT_PORT_N USB2_I2_N<0> 72 11 6 USB2_NEC_LEFT_PORT_N USB2_NEC_N<0> 73
B 11 6 USB2_I2_RIGHT_PORT_P
MAKE_BASE=TRUE
USB2_I2_P<2> 72 11 6 USB2_NEC_RIGHT_PORT_P
MAKE_BASE=TRUE
USB2_NEC_P<1> 73 30 25 7 SYS_OVERTEMP_L
MAKE_BASE=TRUE
=ADT7467_THERM_L 27 26 SYS_PWRSEQ_TPAD_L
MAKE_BASE=TRUE
TP_PMU_AN_P0_0 25
B
11 6 USB2_I2_RIGHT_PORT_N USB2_I2_N<2> 72 11 6 USB2_NEC_RIGHT_PORT_N USB2_NEC_N<1> 73 13 PMU_CHARGE_V TP_PMU_P7_5 25 26 SYS_PWRSEQ_1 TP_PMU_AN_P0_1 25
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
25 PMU_CPU_HRESET_L =CPU_HRESET_L 34 26 SYS_PWRSEQ_2 TP_PMU_AN_P0_2 25
11 6 USB_I2_BT_P USB2_I2_P<4> 72 11 6 USB_NEC_BT_P USB2_NEC_P<2> 73 MAKE_BASE=TRUE MAKE_BASE=TRUE
12 SYS_PMU_ANALOG_AC_DET TP_PMU_AN_P10_6 25 26 SYS_PWRSEQ_3_L TP_PMU_AN_P0_3 25
11 6 USB_I2_BT_N USB2_I2_N<4> 72 11 6 USB_NEC_BT_N USB2_NEC_N<2> 73 MAKE_BASE=TRUE MAKE_BASE=TRUE
25 GOV_RESET_L TP_GOV_RESET_L 26 SYS_PWRSEQ_4 TP_PMU_AN_P0_4 25
11 6 USB_I2_TPAD_P USB2_I2_P<5> 72 11 6 USB_NEC_TPAD_P USB2_NEC_P<3> 73
MAKE_BASE=TRUE MAKE_BASE=TRUE 25 PMU_CPU_CLK_EN =I2_STOPCPU_L 22 26 SYS_PWRSEQ_5 TP_PMU_AN_P0_5 25
11 6 USB_I2_TPAD_N USB2_I2_N<5> 72 11 6 USB_NEC_TPAD_N USB2_NEC_N<3> 73
MAKE_BASE=TRUE MAKE_BASE=TRUE 25 PMU_SYS_CLK_EN =I2_STOPXTAL_L 22 26 SYS_PWRSEQ_6_L TP_PMU_P7_4 25
26 SYS_PWRSEQ_FINAL TP_PMU_AN_P10_5 25
MAKE_BASE=TRUE
I105 TP_PMU_P3_0 25
MAKE_BASE=TRUE
Vesta Ethernet I106
TP_PMU_P3_1
MAKE_BASE=TRUE
25
I107
TP_PMU_P3_2 25
MAKE_BASE=TRUE
9
65 ENET_TX_EN_R ENET_TX_EN =ENET_TX_EN 66 I108
TP_PMU_P3_3 25
9
65 ENET_TX_ER_R ENET_TX_ER =ENET_TX_ER 66
MAKE_BASE=TRUE
9
65 ENET_TXD_R<7..0> ENET_TXD<7..0> =ENET_TXD<7..0> 66
MAKE_BASE=TRUE
65 ENET_RESET_L 65 9 ENET_RXD<7..0> =ENET_RXD_R<7..0> 66
MAKE_BASE=TRUE
65 9 ENET_RX_DV
MAKE_BASE=TRUE
=ENET_RX_DV_R 66 MISC
R11851
100K
5%
65 9 ENET_RX_ER
MAKE_BASE=TRUE
=ENET_RX_ER_R 66
25 11 PCI_RESET_L =ROM_PWD_L 58
Signal Synonyms
1/16W 65 9 ENET_COL =ENET_COL_R 66 MAKE_BASE=TRUE
A MF-LF
402 2
65 9
MAKE_BASE=TRUE
ENET_CRS
MAKE_BASE=TRUE
=ENET_CRS_R 66
32 TP_MAXBUS_CPU1_QACK_L NC_MAXBUS_CPU1_QACK_L
MAKE_BASE=TRUE
NO_TEST=YES
SYNC_MASTER=MARIAS

A
65 ENET_CLK125M_GBE_REF =VESTA_CLK125M_GBE_REF 66
MAKE_BASE=TRUE THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
65 ENET_CLK125M_RX =VESTA_CLK125M_RX 66 AGREES TO THE FOLLOWING
MAKE_BASE=TRUE 22 I2_GPIO_EXT_02 CPU0_VID_AB_SEL =CPU0_VID_AB_SEL 36
MAKE_BASE=TRUE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
65 ENET_CLK25M_TX =VESTA_CLK25M_TX 66
MAKE_BASE=TRUE 22 =SPI_I2_REQ CPU0_MAX1717_AB_SEL =CPU0_MAX1717_AB_SEL 36 II NOT TO REPRODUCE OR COPY IT
MAKE_BASE=TRUE
65 9 ENET_MDC =VESTA_MDC 66 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
MAKE_BASE=TRUE
24 =SLEEP_LED_IOUT SLEEP_LED_IOUT =SLEEP_LED_CONN 74
65 9 ENET_MDIO =VESTA_MDIO 66 MAKE_BASE=TRUE SIZE DRAWING NUMBER REV.
TP_ENET_ENERGYDET
MAKE_BASE=TRUE
=VESTA_ENERGYDET 66
APPLE COMPUTER INC.
D 051-6839 F
SCALE SHT OF
NONE 11 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
I317 THERM THERM BATTERY_ISNS PPVBATT_ISNS_VINP 12
I318 THERM THERM BATTERY_ISNS PPVBATT_ISNS_VINN 12
ADAPTER INPUT/INRUSH LIMITER

A29 ADAPTER DETECTION
D D
Adapter Connector Side Q1210 =PP4V85_ALL_A29_DET =PP3V3_ALL_A29_DET
(Connector is on separate page
to facilitate design reuse)
IRF7416BF System Side 10 10
SOI
8 PP24V_ADAPTER_SW 2
10 =PP24V_ADAPTER_RAW 3 S3 D4 VOLTAGE=24V
13 R1221
2 S2 D3 7 MIN_LINE_WIDTH=0.5 mm 100K
6 MIN_NECK_WIDTH=0.25 mm 1%
D2 1/16W
R12102 2 C1210 1
S1 5 MF-LF 1
R1228
330K 0.1uF D1 1 402 100K
5%
1
20%
50V
GATE
SYS_ADAPTER_ANALOG_AC_DET
1
R1225 1 C1220 5%
1/16W
1/16W
MF-LF
CERM
4
31 7
52.3K 0.1uF MF-LF
805
1% 20%
402
1 1/16W 2 10V 2 402
1 CERM
2
AC_ENABLE_GATE R1222 MF-LF
402 402 A29_DETECT 13
R1201 10 =PP3V3_ALL_AC_DETECT 100K 2
1%
20.0K 2 1/16W 3
1%
1/16W
R1209 MF-LF
2 402 2 U1220
MF-LF 470K 4
D
Q1220
1 402 5%
1/16W
ANALOG_AC_DET LMC7211 2N7002
MF-LF V+ SM-LF SOT23-LF
1 1 1 1 1
C1200 1 R1208 R1215 R1216 1 402 R1224 A29_DET_L G S
R1202 2
R1204 1
0.01uF 10K 10K 10K 1
10K 2 SYS_PMU_ANALOG_AC_DET 3
5% 5% 5% 11 V- 2
97.6K 100K 20%
16V 1/16W 1/16W 1/16W AC_ENABLE_L
1%
1/16W
1%
1/16W CERM 2
402
MF-LF
2 402
MF-LF
2 402
MF-LF
402 2
5%
1/16W
5 R1227
MF-LF MF-LF MF-LF
402 A29_DET_REF 1
4.7M 2
402 1 402 2 3
SYS_AC_DET_L 24
4
2 U1200 D
Q1215 1
R1223 1
R1226
5%
1/16W
14 1V20_REF LMC7211 SYS_AC_DET 25 25 18 13 SYS_ACIN 2N7002DW-X-F 402K 127K
MF-LF
402
V+ SM-LF SOT-363 1% 1%
1 5 G S 1/16W 1/16W
MF-LF MF-LF
AC_DET_DIV 3 V- 4 2 402 2 402
3
5 R1206 SYS_ACIN_L 13
C R12032
10K
R12052
57.6K
1
1M 2
D
Q1208
2N7002DW-X-F
SOT-363
C
1% 1% 5% 5 G S 6
1/16W 1/16W 1/16W
MF-LF D
MF-LF
402 1
MF-LF
402 1 402 6 4 Q1215
2N7002DW-X-F
R12072 D
Q1208 2 G S
SOT-363 ADAPTER IDs
470K 2N7002DW-X-F
5% 2 G S
SOT-363 ADAPTER ID RANGE PIN VOLTAGE
1/16W 1
MF-LF
402 1 Q11 (65W) 1.65-2.31V 2.007-2.066V
1
A29 (45W) 2.31-2.97V 2.558-2.661V
SYS_AC_DET indicates adapter presence. SYS_ACIN is code-controlled AIRLINE 0.33-0.99V 0.589-0.663V
GREATER THAN 13.1V DETECT signal to enable use of AC in system. Q1208 ensures SYS_ACIN
goes low as soon as SYS_AC_DET goes low. Therefore, hardware
immediately disables the AC upon removal but only software can
enable AC after detection by the PMU.
BATTERY INPUT/CURRENT SENSE

=PPVBATT_BATT_VSNS 10
10 =PP3V3_ALL_BATT0_DET
2
B 1
R1256
470K L1252 B
5% FERR-EMI-100-OHM
1/16W
MF-LF SM
2 402
1
L1250
FERR-50-OHM R1250
CRITICAL
1 2 0.0062
J1250 SM-LF
PPVBATT_BATT_RAW
VOLTAGE=12.8V
1 =PPVBATT_ISNS_N 10
87438-0832 MIN_LINE_WIDTH=0.5 mm
1%
1W
M-RT-SM
1 L1253
FERR-EMI-100-OHM
MF-LF
2512
2
2 PPVBATT_BATTPOS_CONN
1 2 =I2C_BATT_SCL
3 VOLTAGE=10.8V
(BATT_IN_PD) MIN_LINE_WIDTH=0.5 mm SM
8
XW1251 XW1252
4 MIN_NECK_WIDTH=0.25 mm SM SM
BATT_CLK
1
5 BATT_DATA
6 BATT0_DET_L L1254
FERR-EMI-100-OHM
12 PPVBATT_ISNS_VINP
VOLTAGE=12.8V
PPVBATT_ISNS_VINN
VOLTAGE=12.8V
12
7 GND_BATT_CONN MIN_LINE_WIDTH=0.25 mm MIN_LINE_WIDTH=0.25 mm
VOLTAGE=0V 1 2 MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm
8 MIN_LINE_WIDTH=0.5 mm =I2C_BATT_SDA 8
MIN_NECK_WIDTH=0.25 mm SM
3 4
VIN+ VIN-
R1255
1K U1250
1 2 SYS_BATT0_DET_L 24 25
INA138 R1252
5%
5 V+ 49.9K2
OUT 1
SOT23-5-LF 1
1/16W 10 =PP3V3_BATT_IMON BATT_ISNS_R BATT_ISNS 25
MF-LF CRITICAL MAKE_BASE=TRUE
402 1%
1/16W
MF-LF
Power Inputs
1
R1251 402 1 C1252
A L1251
FERR-50-OHM
C1250
0.1UF
1 GND
2 1%
249K 10UF
20%
SYNC_MASTER=MARIAS SYNC_DATE=08/24/2005
A
20% 1/16W 2 4V
X5R NOTICE OF PROPRIETARY PROPERTY
1 2 10V MF-LF 603
CERM 2 2 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
SM-LF 402
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 12 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BACKFEED +PBUS CURRENT LIMIT BATTERY SWITCH-OVER CIRCUIT
10 =PPVBATT_BATT
PROTECTION PLACE U1370 NEXT TO R1300 R1386
1K
C1386
0.1uF
1 2 1 1
2 1 IAC_RC_COMP
Q1360 F1390 F1395
IRF7416BF
SOI
1 C1370
0.01uF
1%
1/16W
MF-LF
20%
10V
CERM 10 =PPVBATT_BATT_PBUSA
5AMP-125V
SM-LF
5AMP-125V
SM-LF
402
20% 10 =PP3V3_ALL_PBUS_ILIM 402
13 12 PP24V_ADAPTER_SW 8
D4 3 8 2 50V
CERM
13
7
S3 PP24V_ADAPTER_ILIM_P CRITICAL 603 2 10 =PPVBATT_BATT_PBUSB 2
D3 2 VOLTAGE=24V
S2 MIN_LINE_WIDTH=0.5 mm
6
D2 MIN_NECK_WIDTH=0.25 mm V+ C1380 1
5
D1
S1 1
U1370
MAX4172 =PP14VR24V_ALL_PBUS_A 10
0.1uF
CRITICAL PLACE R383 CLOSE TO LTC1625 13 PPVBATT_BATT_PBUSA_FUSE PPVBATT_BATT_PBUSB_FUSE
D GATE
1
1
RS+
TSSOP-LF
RS-
2
1
R1380
20%
10V
CERM 2
402
ROUTE LTC1625_ITH CAREFULLY
VOLTAGE=14V
VOLTAGE=14V
D
4 R1360 Place close to RS- 42.2K
0.1% CRITICAL CRITICAL
47K 1 C1371
7 NC LTC1625_ITH
5% NC 3 NC1 PG R1385
1/16W
MF-LF Q1390 Q1395
1/16W
MF-LF NC 4 6 0.1UF 10K 2 603 2
U1380
LMC7111
DP1390 IRF7416BF
SUD45P03
402 2 NC2 OUT 10% 2 1 IAC_FB 4 BAS16TW-X-F
SOT23-5-LF R1387 SOI
TO-252-LF
GND 2 50V
X7R SOT-363
603-1 1%
1 6 1 150 3 D4
8
D 4
BKFD_PROT_GATE 1/16W 2 1 1625_COMP 14 S3
MF-LF 7
CRITICAL D3
S
5 402 1% 2 S2
C1361 1R13611 R13701 3 1/16W D2 6
G
MF-LF 1
S1
1
0.01UF 68K 2.21k MAX4172_OUT 5 402 D1 5
5% 0.1%
20% 1/16W ADAPTER_I_REG GATE
50V
CERM
603
2
1/16W
MF-LF
402
2
MF-LF
603 2 R1390 1 4
R1395
47K
1
BKFD_PROT_EN_L CRITICAL
CURRENT_THRESHOLD
CRITICAL CRITICAL
47K 5%
5%
1/16W
1/16W MF-LF
6
R13811 1
R1382 1
R1383 MF-LF
402 2
402 2
42.2K 82.5K =PP3V3_ALL_PBUS_ILIM 10 13 51.1K BATT_14V_GATE
0.1% 0.1% 0.1%
D 1/16W 1/16W 1/16W BATT_24V_GATE
MF-LF MF-LF FF-LF
SYS_ACIN 2 G S A29_CURRENT_ADJ
603 2 2 603 1
R1384 OVER_18V_ADJ
2 603
R1391 1 R1396
10K
1
25 18 12
100K 10K 5%
Q1392 6 5% 3 5%
1/16W
1/16W
2N7002DW-X-F
1
D
Q1330
1/16W
MF-LF
2 402
D SYS_ACIN_L MF-LF
402 2
DP1390 MF-LF
BAS16TW-X-F
402 2
SOT-363
2N7002DW-X-F Q1384 12
SOT-363
SOT-363 2N7002DW-X-F
A29_DETECT 2 5 SOT-363
DP1390 1R1392
4
13 12 G S AC_GTR_18V G S BATT_24PBUS_EN 5 2 BATT_14PBUS_EN
BAS16TW-X-F 158K SOT-363
1 6 4 1% 3
1/16W
3
CRITICAL
R1300
D
Q1384 C1384
1uF
1 MF-LF
2 402
D
Q1392
0.0252
2N7002DW-X-F
SOT-363 20%
2N7002DW-X-F
SOT-363
1772_ACOK_L 2 10V 5
C 13 12 PP24V_ADAPTER_SW
1
1%
1W
13 G S
1
CERM 2
603
SYS_ACIN_L_RC
1 C1392
G S
4
C
R1301
TABLE_5_HEAD
1 1
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
R13211
MF
2512-1 R1302 10uF
114S0343 1 RES,20K,1%,1/16W,MF-LF,402 R1345 Q16C_PARTS
TABLE_5_ITEM
100K
1%
1
D13034.71/16W
5%
4.7
5%
1/16W
20%
6.3V
2 X5R
TABLE_5_ITEM
1/16W MMBD914XXG
MF-LF 1772_CSSP MF-LF 603 WHEN AC IS IN, P-CHANNEL FETS ARE QUICKLY (DIODE) TURNED OFF
MF-LF SOT23 402 2
114S0382 1 RES,48.7K,1%,1/16W,MF-LF,402 R1345 Q41C_PARTS
402 2 3 1772_CSSN 2 402 WHEN AC IS NOT PLUGGED, P-CHANNEL FETS ARE ON
R1319 D1319
MMBD914XXG
RC TIME IS 480K*10UF @ +3V_PMU
=PP3V3_ALL_BATT_CHGR SWITCHER VOLTAGE CONTROL SWITCHER CURRENT CONTROL C1301 1 1 C1302 1772_LDO
33 1 2 1 3 1772_BST_ESR
10
13
PMU SELECTS BETWEEN TWO VOLTAGES CHARGE DISABLED BY PMU OR INPUT VOLTAGE <18V R13221 1 C1303
1uF 0.47UF 10%
0.47UF
10%
5%
12.7K 1/4W SOT23 =PPVIN_ALL_BATT_CHGR
CHARGE THROTTLED BY LOW BATTERY VOLTAGE 1%
1/16W
20%
50V
2 CERM
50V
CERM 2
1206
50V
2 CERM
1206
R1317
100K
1 MF-LF
1206
1
R1320
4.7
10
MF-LF 1210
R1341 R1344 1 1 1
R1346
402 2
27 26
5%
1/16W
MF-LF
C1319
0.1uF
1 5%
1/10W
MF-LF
402 2 2 603
27.4K 10K 1% 1%
10K
1% CSSP CSSN
20%
25V
1772_DCIN 1 DCIN 16 1772_CELLS CERM 2
1/16W
MF-LF
402 2
1/16W
MF-LF
402 2
1/16W
MF-LF
2 402 11 ACIN
CRITICAL CELLS
U1300 LDO 2
603 C1320
0.1uF
1
5 6 7 8
1 C1312 1 C1313 1 C1314 1 C1315 1 C1316
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
1772_ACIN 20% 10% 10% 10% 10% 10%
OD OUTPUT LOW - WHEN AC GREATER THAN 18V
13 1772_ACOK_L 12 ACOK MAX1772 DLOV 22 1772_DLOV 50V
CERM 2 CRITICAL 2 50V 2 50V 2 50V 2 50V 2 50V
QSOP-LF X7R X7R X7R X7R X7R
(+3V_PMU) 13 RFIN BST 25 1772_BST 805

Q1300 1206 1206 1206 1206 1206
15 VCTL 24 4
RLA130N03
1772_VCTL DHI 1772_DHI SO8 PPVOUT_BATT_CHRG_R
1772_ICTL 14 ICTL CRITICAL VOLTAGE=14V
LX 23 1772_LX MIN_LINE_WIDTH=0.5 mm
R1342
4.12K
1 OMIT
1772_ICHG 10 ICHG DLO 21 1772_DLO 1 2 3 L1300 MIN_NECK_WIDTH=0.25 mm PPVBATT_BATT_PBUSA_FUSE
MAKE_BASE=TRUE
13
1%
1/16W
R1345
20.0K
1
R1348
1K
1
1772_IINP 28 IINP PGND 20 (GND)
10uH R1303
0.05 2
=PPVOUT_BATT_CHRG
MF-LF
402 2
1%
1/16W
MF-LF
1%
1/16W
MF-LF
R1323
1K
1
1772_CCV 7 CCV CSIP 19 1772_CSIP
1
SM1-LF
2 1
1%
402 2 402 2 1% CSIN 18 1772_CSIN 1W
B R1340 1
BATTV_HIGH
BATT_LOW_L
1/16W
MF-LF
1772_CCI
1772_CCS
6 CCI
5 CCS BATT 17
5 6 7 8 2
D1300
MF-LF
2512 1 C1305 1 C1307 1 C1309 CRITICAL B
100K 5% 6
402 2
1 C1322
C13170.1uF
1 1 C1323
0.1uF
CRITICAL SMB
4.7uF
20%
4.7uF
20% 4.7uF
1
C1311
1/16W
MF-LF D
Q1340 R1343
5.23K
1
6 3 R1325
1KC1325
1
1 1 C1326 REF CLS
4 3
GND
8 9
1uF 20%
25V
20% Q1301 MBRS140XXG 25V
2 CERM
25V
2 CERM 20%
25V
2 CERM
33uF
20%
402 2 0.01uF 0.01uF 20%
10V CERM 2 2 25V
CERM
1 1206 1206 2 25V
2N7002DW-X-F 1% D Q1348 D Q1348 1% 2 CERM 603 603 4 IRF7811W 1206 ELEC
BATTV_LOW2 G S
SOT-363 1/16W
MF-LF 2N7002DW-X-F 2N7002DW-X-F 1/16W
MF-LF
20%
16V
CERM 2
20%
16V
2 CERM 603 NO STUFF
SO-8-LF R13041 R13051 C1306 1 C1308 1 C1310 1
SM1-LF
2 402 2 G S
SOT-363
5 G S
SOT-363 402 2 402 402 1 C1321 5%
1 5%
1 4.7uF 4.7uF 4.7uF
1 1/10W 1/10W 20% 20% 20%
3 1772_CCV_RC 1772_REF R1328 1
XW1300
0.0022UF 1 2 3
10% MF-LF MF-LF 25V
CERM 2
25V
CERM 2
25V
CERM 2
D
Q1340
2N7002DW-X-F
1 4
R1324
1
1K C1324 C1327 1
10K
1 1%
1/16W
R1318
100K
1 SM
1 2
50V
2 CERM
402
603 2 603 2 1206 1206 1206
5 SOT-363 1% 0.1uF 1uF MF-LF 5%

11 PMU_CHARGE_V G S 1/16W 20% 20% 402 2 1/16W
MF-LF 10V 10V 1772_CLS
MF-LF
4 2 402 2 CERM CERM 2 402 2
402 603
13 10 =PP3V3_ALL_BATT_CHGR R1329
4.12K
1
PART NUMBER
IS
ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
1% PART NUMBER
R1347
100K
1
=PP3V3_ALL_BATT_CHGR
VOLTAGE=0V
1/16W
MF-LF TABLE_ALT_ITEM
6 10
13
MIN_NECK_WIDTH=0.25 mm 402 2 126S0084 126S0079 C1311 Primary is 260C/Alt is 250C part
5%
1/16W 1772_GND
MF-LF
402 2
D
Q1347
2N7002DW-X-F =PPVIN_BATT_CHRG_VSNS 10
SOT-363
CHARGE_DISABLE 2 G S
1 C1350
0.1uF R1353 1 1
R1351 R1330 1
3 1 20% 100K
1% 1%
499K 6.34K
10V
2 CERM 1/16W 1/16W 1%
D
Q1347
2N7002DW-X-F
402 MF-LF
402 2
MF-LF
2 402
1/16W
MF-LF
U1350 2 402 2
25 PMU_BATT0_CHARGE 5 G S
SOT-363
LMC7211
SM-LF V+
4
A29_CLS_ADJ
Battery Charger
1 BATT_DIV
BATT_LOW
A 4
3
1V65_REF 3 SYNC_MASTER=MARIAS SYNC_DATE=08/24/2005
A
V- D
Q1330 NOTICE OF PROPRIETARY PROPERTY
5 1 1 2N7002DW-X-F
R1354 R1352 1 C1352 A29_DETECT 5 G S
SOT-363 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
V = CELLS X (4.096 + (0.4096 * V / V ))
100K
1% 1%
100K 0.047uF AGREES TO THE FOLLOWING
BATT VCTL REFIN 1/16W 1/16W 10% 4 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MF-LF MF-LF 16V
2 CERM
For 4.15V cells, VCTL = 0.123 REFIN 402 2 2 402 402 II NOT TO REPRODUCE OR COPY IT
For 4.20V cells, VCTL = 0.245 REFIN III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I = (0.2048/R ) * (V / V ) SIZE DRAWING NUMBER REV.

CHG _62 ICTL REFIN
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 13 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL
Q1430
FDG6324L
SC70-6-LF
3
=PP5V_PWRON_LTC1625_EXTVCC 4 S2 D2 2 PP5V_LTC1625_EXTVCC_SW
10
VOLTAGE=5V
R1430 G2
470K 6
5%
1/16W
MF-LF
402 2
D 1625_ENABLE_L
D
6
1625_ENABLE 5 G1
D1
S1
CRITICAL
Q1430
FDG6324L
SC70-6-LF
1 C1400
0.1uF
20%
12.8V PBUS SUPPLY
1 2 10V
CERM
402
10 =PPVIN_ALL_LTC1625
CONNECT LTC1625 TK PIN AT TOP-SIDE FET
KEEP VIN/TK LOOP SHORT
=PP3V3_ALL_LTC1625_SW 1625_INTVCC
5 6 7 8 1 C1403 1 C1405 1 C1407
10
2 VOLTAGE=5V 2.2UF
10%
2.2UF
10%
2.2UF
10%
R1427 NO STUFF MIN_LINE_WIDTH=0.5 mm
CRITICAL
2 50V 2 50V 2 50V
5%
1 1
R1415 MIN_LINE_WIDTH=0.5 mm
Q1400 X7R
1206
X7R
1206
X7R
1206
C1420 1 1/10W 0 1 1625_TG

RLA130N03
R14201 MF-LF
603 1
5%
1/16W
4
SO8 1 C1404 1 C1406 1 C1408
97.6K 0.1uF MF-LF EXTVCC D1410 2.2UF 2.2UF 2.2UF
1%
1/16W
20%
10V
CERM 2
2 402 U1400
LTC1625
SOD-123 10% 10% 10%
MF-LF 16 10
1 2 1625_BST_ESR 1 2 3 2 50V 2 50V 2 50V
402 2
402 1625_VIN VINSSOP-LF BG X7R
1206
X7R
1206
X7R
1206
4
2 U1420 15 TK CRITICAL TG 13 1
R14101 C1410
1V20_REF LMC7211 MBR0540XXG
12
V+ SM-LF D1420 2 SYNC VOSENSE 7 2.2
5%
0.22uF CRITICAL
1 1625_RUNSS 3 11 20%
3 1
13 1625_COMP 5
RUN/SS INTVCC
ITH
1/10W
MF-LF
603
2
25V
CERM
L1400
3
1625_DIV 3
V- MMBD914XXG 2 805
SOT23 1625_FCB 4 FCB BOOST 12 1625_BST 10 =PP12V8_LTC1625_VREG
C 5 R1422 NC 8 14 C
1
VPROG SW 1625_VSW
R1421 1 1M
10K
1 2
R1425 2 C1421 1 SGND PGND
8.0uH-6.8A
SM1
1%
1/16W
1%
1/16W C1427 1 4.99K
1%
4700pF
5% 6 9 5 6 7 8
1 C1401
4.7uF
1
R1401
MF-LF
402 2
MF-LF
402 0.1uF 1/16W
MF-LF
25V
CERM 2 20%
158K
1%
20% 402 1 603 CRITICAL 2 25V 1/16W
50V 1 CERM
CERM 2 R1416 MIN_LINE_WIDTH=0.5 mm Q1401 1206 MF-LF
2 402
805 0
5%
IRF7811W
COMP_RC
1 C1425 1/16W 1625_BG 4
SO-8-LF 2
470pF
10%
2 50V
MF-LF
2 402
NO STUFF
D1400
SMB
CERM MBRS140XXG
WHEN +24V_PBUS IS BELOW ~13.1V,
1625 IS SHUT-OFF C1426 1
603 1 C1411
4.7uF
1 C1412
0.0047uF
1 2 3
1 C1402 1
1
R1402
4700pF 20% 10% 4.7uF 16.2K
1%
5% 10V
2 CERM 2 25V 20% 1/16W
25V CERM 25V
CERM 2 XW1400 1206 402 CERM 2 MF-LF
603
SM 1206 2 402
1625_SGND 1 2
VOLTAGE=0V
1625_VFB
B PMU SUPPLY B
BACKUP_BATT
=PP5V_PWRON_PMU_SUPPLY
10
D1460
SOD-123
PP4V6_ALL_RAW
MAKE_BASE=TRUE
3V_PMU_VTAP
NC 1 2 VOLTAGE=4.6V
IF SUPERCAP BOM OPTION IS CHOSEN: MIN_NECK_WIDTH=0.25 mm
BOOTSTRAP SYSTEM FROM ADAPTER, 6 6
OUTPUT AT U23.1 IS 5.65V
MAIN BATTERY OR BACKUP BATTERY PLUS5VTAP OUTPUT AT U22.8 IS 5.4V RB160M-60 VTAP
R1450 D1450 U1450 D1461 U1460
SOD-123 LP2951 =PP4V85_ALL_VREG 10 SOD-123 LP2951
=PP24V_ADAPTER_PMU_SUPPLY 1
390 2 PP24V_ADAPT_PMU_ILIM 1 2 PPVIN_ALL_ADAPT_OR_BATT 8 SOI-LF 1 1 2 8 SOI-3.3V-LF1 1 =PP3V3_ALL_VREG
10
VOLTAGE=24V VOLTAGE=18V IN OUT IN OUT 10
5% MIN_LINE_WIDTH=0.38 mm MIN_LINE_WIDTH=0.38 mm NC 2 5 NC BACKUP_BATT BACKUP_BATT 2 5 NC

1/4W MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm SENSE ERR SENSE ERR
MBR0540XXG 3 7 1 1 3 7 1
MF-LF
1206
NC SHUT FDBK R1451 R1453 RB160M-60 NC SHUT FDBK R1461
GND 294K 1 C1452 1 GND 1
D1451 1%
1/16W 470pF
10%
5%
1/10W
31 =PP5V_SUPERCAP 5%
1/10W
MMBD914XXG 4 MF-LF
402 2
50V
2 CERM
MF-LF
SUPERCAP HOOKS IN HERE
4 MF-LF
=PPVBATT_BATTERY_PMU_SUPPLY 1 3 2 603 2 603
10
1 C1450 C1451 1 FB_4_85V_BU
603
PP4V85_ALL_ESR
SOT23 0.1uF 0.1uF VOLTAGE=4.6V PP3V3_ALL_ESR
20%
50V
2 CERM
20%
10V MIN_LINE_WIDTH=0.38 mm
1 C1460 VOLTAGE=3.3V
CERM 2 1 0.1uF
805 402 R1452 BACKUP_BATT 20% MIN_NECK_WIDTH=0.25 mm
D1452
SOD-123
100K
1% 1 C1453
10V
2 CERM 1 C1461
1/16W 402 10UF
10 =PP12V8_PBUS_PMU_SUPPLY 1 2 MF-LF 2.2uF 20%
6.3V
402 2 20% 2 X5R
10V
2 CERM 603
MBR0540XXG 805
12.8V PBUS/PMU Supplies

A
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM
114S0465 1 RES,MF-LF,1/16W,357K OHM,1%,0402,SMD R1451 ? SUPERCAP III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 14 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3.3V/5V SWITCHER
10 =PPVIN_ALL_LTC3707
1 C1520 1 C1521 1 C1522 1 C1523 8 7 6 5 5 6 7 8

1 C1570 1 C1571 1 C1572 1 C1573
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
10% 10% 10% 10% CRITICAL CRITICAL 10% 10% 10% 10%
2 50V
X7R 2 50V
X7R 2 50V
X7R
50V
2 X7R 3707_INTVCC 2 50V
X7R 2 50V
X7R 2 50V
X7R 2 50V
X7R
VOLTAGE=5V
1206 1206 1206 1206
Q1501 MIN_LINE_WIDTH=0.5 mm
Q1551 1206 1206 1206 1206
RLA130N03 RLA130N03
4
R15321 1
R1530 1 C1530 3V_TG 4
D 5V_RSNS CRITICAL
SO8
5%
0
1%
100K 20%
4.7uF
SO8
CRITICAL
3V_RSNS D
CRITICAL 1
R15101 1/16W 1/16W 2 10V 1
R1560 1 CRITICAL =PP3V3_PWRON_REG
L1501 3 2 1 D1511 1M
MF-LF MF-LF
CERM
1206 1M
D1561 1 2 3 L1551 10
10 =PP5V_PWRON_REG R1501 4.7uH SOD-123

MBR0540XXG 5%
402 2 2 402 5%
SOD-123
MBR0540XXG
4.7uH R1551
0.0052
1 2 1 1/16W 1/16W 1 2
0.0052
1
2 MF-LF MF-LF 2
402 2 2 402
1% IHLP-5050 10 =PP5V_PWRON_LTC3707_EXTVCC IHLP-5050 1%
1/4W NC 1/4W CRITICAL
C1501 1 MF-LF 2 8 7 6 5
5V_BOOST_ESR 3V_BOOST_ESR 5 6 7 8 2 MF-LF
1 C1551 1
CRITICAL 22uF 1206
D1501 D1551
1206
22uF
C1553
1
20%
10V SMB 1
22 21 24 10
1 SMB 20%
330uF
C1503 CERM 2 MBRS140XXG
CRITICAL
C1511 1 R1511 EXT INT VIN 3.3
VCC VCC VOUT
R1561 1 C1561 CRITICAL MBRS140XXG 10V
2 CERM
20%
2 6.3V
330uF 1210
1 Q1502 0.22uF 2.2 2.2 0.22uF Q1552 1 1210
TANT
20% CASE-D4-LF
6.3V 2
1 C1502 1 1
IRF7811W 4
20%
25V
5%
1/10W U1500 5%
1/10W 20%
25V 4
IRF7811W
TANT
CASE-D4-LF
22uF
R1502 R1503 SO-8-LF CERM 2
805
MF-LF
2 603
LTC3707
27 TG1 SSOP-LF TG2 16
MF-LF
603 2
2 CERM
805
SO-8-LF R15531 R15521 C1552 1
20%
10 10 NO STUFF 5V_TG NO STUFF 10 10 22uF
5% 5% 5% 5%
10V
2 CERM 1/16W
MF-LF
1/16W
MF-LF 3 2 1
C1515 1 5V_BOOST 25 BOOST1 BOOST2 18 3V_BOOST 1 C1565 1/16W 1/16W 20%
10V
1210 0.0022UF 5V_SW 26 SW1 SW2 17 3V_SW 0.0022UF 1 2 3 MF-LF MF-LF CERM 2
2 402 2 402 10% 10% 402 2 402 2 1210
50V 5V_BG 23 BG1 BG2 19 3V_BG 50V
CERM 2 2 CERM
402 CRITICAL 402
2 SNS1+ SNS2+ 14
5V_SNSP 3V_SNSP
5V_SNSM 3 SNS1- SNS2- 13 3V_SNSM
C1514 5V_VOSNS 4 VOSNS1 VOSNS2 12 3V_VOSNS C1564
0.001uF 8 ITH1 0.001uF
1 2
5V_ITH ITH2 11 3V_ITH 1 2
NO STUFF 5V_RUNSS 1 RUN/ RUN/ 15
SS1 SS2 NO STUFF
R15041 1 C1504
20%
50V 7 FCB
3V_RUNSS
1 C1562
20%
50V C1554 1
1
R1554
113K
1% 180pF
CERM
402 C1512 1 C1510 1
3707_FSET 5 FREQSET PGOOD 28 0.0022uF
CERM
402 180pF 1%
63.4K
1/16W 5% 0.0022uF 0.047uF 1 C1560 10% 5% 1/16W
50V 10% 10% 6 STBYMD 50V 50V
MF-LF 2 CERM 50V 16V 0.1uF 2 CERM CERM 2 MF-LF
402 2 402 CERM 2 CERM 2 20% 402 402 2 402
402 402 3707_FCB 10V
SGND PGND 2 CERM
C 5V_ITH_RC
3707_STBYMD 9 20 402
3V_ITH_RC
C
R15051 R15121 1 C1513 C1531 1
1
R1531 C1563 1
1
R1562 1
R1555
21.5K 15.0K 100pF 0.01uF 100K 100pF 12.7K 20.0K
1% 1% 5% 20% 1% 5% 1% 1%
1/16W 1/16W 50V 16V 1/16W 50V 1/16W 1/16W
MF-LF MF-LF 2 CERM CERM 2 MF-LF CERM 2 MF-LF MF-LF
402 2 402 2 402 402 2 402 402 2 402 2 402
3707_SGND
VOLTAGE=0V
MIN_NECK_WIDTH=0.25 mm 3
=5V3VPWRON_PGOOD 26
R1533
D
Q1533 2
2N7002 XW1500
=5V3V3PWRON_EN_L 1
1M 2 5V3VPWRON_EN_L_RC 1 G S
SOT23-LF SM
1 C1532
26
220pF
5% 1 5%
1/16W 25V
2 2 CERM
MF-LF
402
1 C1533 402
0.01uF
20%
D1533 16V
2 CERM
3 1 402
MMBD914XXG
SOT23
5V START TO TURN ON ~12.5MS =5V3V3PWRON_EN_L goes low
3V START TO TURN ON ~25MS AFTER =5V3V3PWRON_EN_L goes low
DIODE WILL ENSURE REGULATOR TURNS ON QUICKLY
POWERDOWN DELAY IS AROUND 4MS-15.6MS, VIA RC NETWORK
10 =PP3V3_PWRON_RUNFET
B 26 3V3RUN_EN_L
4
3 6
=PP3V3_RUN_RUNFET 10
B
5
=PP5V_PWRON_RUNFET
10
C1585 2
0.01uF C1592 1
10 =PP5V_PWRON_TRACKPAD 1 2 10UF TSOP-LF

SI3443DV
1 1
C1591
20%
6.3V
100UF
20%
TPAD_SEQ_PMU
1
20%
16V
X5R 2
603
Q1590 2 6.3V
R1535 CERM
402
POLY
B2
100K 4 C1590
5% =PP5V_RUN_HDDFET 10
1/16W
5VRUNHD_EN_L
0.0022uF
MF-LF 26
3 6 2 1
402 2
5
4 =PP5V_TPAD_FET 10 C1586 1 2 C1587 10%
50V
26 =5VPWRONTPAD_EN_L 10UF 100UF CERM
3 6 20% TSOP-LF 1 20% 402
6.3V 6.3V
5 X5R 2 SI3443DV POLY
603 B2
2 1 C1536 Q1585
TSOP-LF 1 10UF
20%
SI3443DV 6.3V
2 X5R C1580
Q1535 603 0.1uF
1 2
20%
10V
CERM
402
4 =PP5V_RUN_RUNFET 10
26 5VRUN_EN_L
3 6
5 5V/3.3V Supplies
1 C1581 2
1
C1582
A 10UF
20%
6.3V
2 X5R
TSOP-LF 1
100UF
20%
2 6.3V
SYNC_MASTER=MARIAS

A
SI3443DV POLY
603 B2
Q1580 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 15 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1.5V/1.8V SWITCHER
10 =PP5V_PWRON_MAX1715_VDD 16 10 =PPVIN_ALL_MAX1715
D D
R1641 1 R1630 1 C1631
20 2.2uF
2
100K 2 1 PP5V_MAX1715_VCC 20%
5% VOLTAGE=5V
1/16W DP1620 5% MIN_LINE_WIDTH=0.38 mm 2 10V
CERM
MF-LF 1/16W MIN_NECK_WIDTH=0.25 mm 805
402 2 BAS16TW-X-F MF-LF
5
DP1620 SOT-363 NO STUFF 402 1 C1630
1 2.2uF
BAS16TW-X-F MAX1715_ON R1631 20%
10V
SOT-363 0 2 CERM
6 1 5% 805 NO STUFF
1/16W
3 MF-LF
2 402
1
R1633
0
R1640
D
Q1640 5%
2N7002 1/16W
=1V8_1V5PWRON_EN_L 1
330K 2 MAX1715_EN_L_RC 1 G S
SOT23-LF MAX1715_TON MF-LF
2 402
3
26
5%
MF-LF
1/16W
1 C1640 2 DP1620
402
0.01uF 1_8V_ILIM 1_5V_ILIM BAS16TW-X-F
4
DIODE PROVIDE PROVIDE QUICK TURN-ON 20% SOT-363
POWER DOWN DELAY 1.5MS TO 3.5MS 16V
2 CERM
402
R16211 1
R1671
158K 158K
1% 1% 16 10 =PPVIN_ALL_MAX1715
1/16W 1/16W
MF-LF MF-LF
402 2 21 20
2 402
VCC VDD
MAX1715_SKIP
MAX1715_GND 16
U1600
MAX1715 CRITICAL CRITICAL
QSOP-LF
16 10 =PPVIN_ALL_MAX1715
3 ILIM1 V+ 4
1 C1601 1 C1602
4.7uF 4.7uF
12 ILIM2 NC_15 15 NC 20% 20%
25V 25V
10 23 2 CERM 2 CERM
CRITICAL CRITICAL ON1 NC_23 NC 1206 1206
C C1651
4.7uF
1 C1652 1
4.7uF
R1670
4.7
11 ON2 NC_28 28 NC R1620
4.7
C
20% 20% 1_5V_BOOST 1 2 1_5V_BST 25 BST2 18 1_8V_BST 1 2 1_8V_BOOST
25V 25V BST1
CERM 2 CERM 2 5% CRITICAL 5%
1206 1206 26 DH2 17
8 7 6 5
1/10W
MF-LF
DH1 1/10W
MF-LF
1 C1670 603
27 LX1 LX2 16
603
1 C1620
5 6 7 8
CRITICAL 0.1uF
20% 0.1uF CRITICAL
Q1651 25V
2 CERM 24 DL1 DL2 19 20%
25V
2 CERM Q1601
RLA130N03 603
4 1_5V_DH 5 PGND 22 603 RLA130N03
SO8 TON MAX1715_GND
1_8V_DH 4
SO8
1 OUT1 OUT2 14
CRITICAL 10 =PP1V8_PWRON_REG
=PP1V5_PWRON_REG L1651 3 2 1 26 =1V8_1V5PWRON_PGOOD 7 PGOOD CRITICAL
1 2 3
10
4.7uH 9 REF SKIP 6 L1601
4.7uH
1 2 1_5V_LX 2 FB1 FB2 13 R16011
SM4-LF
8.06K 1_8V_LX 1 2
NO STUFF AGND THRML 1%
1 1 1/16W Ra SM4-LF
R1651 8 7 6 5 R1632 8 29 MF-LF
402 2 5 6 7 8
5.11K 0
Ra 1%
1/16W
5%
1/16W
MF-LF CRITICAL MF-LF CRITICAL
1_8V_FB
2 402 Q1652 2 402 Q1602 C1603
1 C1655 C1653 1 1_5V_FB 2
1
10UF
1
C1604 1
C1605
10UF IRF7805ZPBF
2 MAX1715_REF IRF7805ZPBF D1601 150uF 330UF
330UF SO-8
4 1_5V_DL 1_8V_DL 4
SO-8 SMB
20%
6.3V
20% 20%
20%
6.3V
2 X5R
20%
2.5V-ESR9V 2
1
R1652 D1651 NO STUFF
1
R1634 R1602 1
NO STUFF B130LBT01XF
2 X5R 2 6.3V
POLY
2 2.5V-ESR9V
POLY
603
POLY
CASE-D2E-LF Rb 1%
10K
B130LBT01XF
SMB
C1671 1
1 C1632 5%
0 10K
1% 1 C1621 1
603 CASE-D2-LF CASE-D2E-LF
1/16W 1uF 1/16W 1/16W Rb
MF-LF 1 3 2 1 0.0022UF 20% MF-LF MF-LF 0.0022UF 1 2 3
2 402
10%
50V XW1600 10V
2 CERM 2 402 402 2 10%
50V
CERM 2 SM 603 2 CERM
402 1 2 16 MAX1715_GND 402
VOLTAGE=0V
B MIN_NECK_WIDTH=0.25 mm
B
Vout = 1.0V * (1 + Ra/Rb)
10 =PP1V8_PWRON_RUNFET
=PP1V8_RUN_RUNFET 10
C1680 1 1
R1680
10UF 100K
20% 5% 2 3 6 7
6.3V
X5R 2 1/16W
MF-LF CRITICAL
603
2 402
Q1685
Q1680
4
SI6467BDQ-E3
10 =PP1V5_PWRON_RUNFET SI3446DV =PP1V5_RUN_RUNFET 10 26 1V8RUN_EN_L TSSOP
1 TSOP-LF
2
5 1 5 8
6 3 1V5RUN_EN 26
C1686 1 1 C1685 1.8V/1.5V Supplies

10UF 1000pF C1681
A 20%
6.3V 2
X5R
10%
2 25V
X7R
2200pF
1 2
SYNC_MASTER=MARIAS

A
603 402
NO STUFF 5% THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

50V PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
C1682 1 CERM
603 AGREES TO THE FOLLOWING
1000PF I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
10%
25V 2 II NOT TO REPRODUCE OR COPY IT
X7R
402
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 16 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
2.5V SWITCHER
10 =PP3V3_PWRON_LTC3412
CONTINUOUS MODE 1 C1710 1 C1711

R17221 1
R1723 22UF 22UF 1
R1730
4.7M 0 20% 20% C1730 1
16
6.3V 6.3V 402K
5% 5% 2 CERM 2 CERM
9
1/16W 1/16W 5.6pF 1%
1206 1206 +/-0.25pF
MF-LF MF-LF SVIN PVIN 50V 1/16W
402 2 2 402 CERM 2 MF-LF
U1700 402 2 402
LTC3412
=PP2V5_PWRON_REG
RT TSSOP-LF
10
LTC3412_RT 5 CRITICAL
PGOOD 2 =2V5PWRON_PGOOD
LTC3412_RUNSS 7 RUN/SS
26
L1700
CRITICAL 1.0uH-3.48A
LTC3412_ITH 3 ITH 10 LTC3412_SW 1 2
3
LTC3412_SYNC 6 SYNC/MODE 11 SM-LF
D
Q1740 BURST MODE SW 14
2N7002DW-X-F 1
R1720 NO STUFF 4 15
C 26 =2V5PWRON_EN_L 5 G S
SOT-363
1%
7.5K 1
R1724
0 1
LTC3412_VFB VFB
THERM 1 C1700 C
4
1/16W
MF-LF C1722 1 5%
R1731 SGND PGND PAD 47uF
110K 20%
12
13
17
C1720 1 2 402 470PF 1/16W
MF-LF 1% 6.3V
2 X5R
10%
100PF 50V 2 402 1/16W 1206-1
5% CERM 2 MF-LF 1
50V
CERM 2
402 2 402 R1733
402 LTC3412_ITH_RC 309K
LTC3412_VFB_DIV 1%
1/16W
MF-LF
C1701 1
1 47uF
C1721 1 R1732 2 402 20%
6.3V
2200pF 75K X5R 2
5% 1% 1206-1
1/16W
50V
CERM 2 MF-LF XW1700
603 2 402 SM
LTC3412_GND 1 2
VOLTAGE=0V
B B
Q1780
TSSOP
10 =PP2V5_PWRON_RUNFET SI6467BDQ-E3 =PP2V5_RUN_RUNFET 10
6 7
8
1 5
3
2
C1781 1
4
10UF
20%
6.3V 2
X5R
603
C1780
1000pF
26 2V5RUN_EN_L 1 2
10%
25V
X7R
402
2.5V Supply

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 17 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes 3.3V Regulator
=PPFW_P3V3VESTA
D1975 CRITICAL
- =PPBUS_FW (system supply for bus power) 10 SC-59
CRITICAL
- =PPBU_RUN_FW (backup PHY power) 1 U1970
LM2594 L1970
- =PP3V3_RUN_FWPORTPWRSW
10 =PPBU_RUN_FW
3 PPVIN_VESTA3V3
VOLTAGE=33V
7
VIN FB
SM-LF 4
8 1
100uH-0.8A
2
=PP3V3_VESTA_REG 10 2.5V LDO
Signal aliases required by this page: 2 MIN_LINE_WIDTH=0.38 mm
VOUT
(NONE) GND ON/OFF
PLC Vout = 3.3V @ 500mA CRITICAL
SMD20E40C-X-F
VESTA3V3_SW U1980
BOM options provided by this page: 6 5 MIN_LINE_WIDTH=0.5 mm MM1572FN
MIN_NECK_WIDTH=0.25 mm CRITICAL
- VESTA1V2_BURST / VESTA1V2_PULSE SOT-25A-LF
1 1
C1971 10 =PP3V3_VESTA_2V5REG =PP2V5_VESTA_LDO 10
D Controls operating mode of Vesta 1.2V

regulator. If both options are off the
C1970
10uF
N20P20%
1
D1970
SMD
100UF
20%
1 VIN VOUT 5 D
50V MMBRM140XXG 2 6.3V
POLY 3 CONT NOISE 4 VESTA2V5_NOISE
Vout = 2.5V @ 150 mA
regulator will be in continuous mode. CERM 2
2 B2
2320 MIN_LINE_WIDTH=0.2 mm
Port Power Switch C1980

1uF
1
GND
2 C1981
0.01uF
1 1
C1982
10UF
10% 20% 20%
CRITICAL 6.3V 16V 6.3V
CERM 2 CERM 2 2 X5R
Q1965 CRITICAL 402 402 603
NDS9407
F1965 SOI-LF
D1965
SMB =PPBUS_FW_FET 10
10 =PPBUS_FWPWRSW 1.5A-24V 8 PPBUS_FW_FET_D 1 2
1 2 PPBUS_FWPWRSW_F 3
VOLTAGE=25V
VOLTAGE=25V 7 MIN_LINE_WIDTH=0.5 mm
2
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm B340XF
MINISMDC MIN_NECK_WIDTH=0.25 mm 6
1
5
1
R1965 C1965 1
4
0.01uF
5%
470K
1/16W
20%
16V
CERM 2
10 =PP3V3_VESTA_1V2REG 1.2V Regulator
MF-LF 402
2 402
R1990
FWPWR_EN_L_DIV
1
10
2 PPVOUT_VESTA1V2
1 C1990
MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V 10UF
5% MIN_LINE_WIDTH=0.5 mm 20%
1 1/16W 6.3V
R1966 MF-LF
MIN_NECK_WIDTH=0.25 mm 2 X5R
603
330K Burst Mode 402
5%
1/16W VESTA1V2_BURST 7 6
=PP3V3_RUN_FWPORTPWRSW
MF-LF 1 1 C1991 1
SVIN PVIN
10
2 402 R1992 R1991 1uF CRITICAL
10K 1M 10% U1990 L1990
FWPWR_EN_L 6.3V
5% 5% CERM 2 LTC3411 MIN_LINE_WIDTH=0.5 mm 2.2uH
R1960 1 MIN_LINE_WIDTH=0.2 mm
1/16W
MF-LF
1/16W
MF-LF
402 MSOP-LF MIN_NECK_WIDTH=0.25 mm =PP1V2_VESTA_REG 10
C 100K
5%
1/16W DP1960
3
402 2 402 2 VESTA1V2_RT 1 SHDN/RT SW 4 VESTA1V2_SW 1
SM1-LF
2
<R2> C
MF-LF
BAS16TW-X-F
D
Q1960 Pulse Mode VESTA1V2_MODE 2 SYNC/MODE VFB 9 VESTA1V2_VFB 1 Vout = 0.8V * (1 + (R2 / R1))
402 2
SOT-363 2N7002 VESTA1V2_PULSE C1992 1 R1997
10
3 4 1
SOT23-LF 8
PGOOD ITH VESTA1V2_ITH
22pF 4.99K Vout = 1.199V @ 1.2 A
FWPWR_RUN FWPWR_EN G S R1993 1 5%
1%
1/16W
10K PGND SGND 1
50V
CERM 2 MF-LF
DP1960
2 5%
1/16W
5 3
CRITICAL R1996 402 2
402
MF-LF 4.99K
BAS16TW-X-F 402 1%
SOT-363 2 1/16W
=FWPWR_PWRON 5 2
MF-LF <R1>
26 402 2 1 1
Continuous C1993 R1998
100pF
1
C1995
If =FWPWR_PWRON is NC: Mode VESTA1V2_ITH_RC 5%
10K 22uF
DP1960 50V 1%
BAS16TW-X-F Enables port power when machine is R1994 1 1
R1995 2 CERM 1/16W 20%
6.3V
R1961 SOT-363 1M 324K 1
C1994 402 MF-LF 2 X5R
10K 2 402 805
1 6 running or on AC. 5% 1% 0.0033uF
25 13 12 SYS_ACIN 1 2 FWPWR_ACIN 1/16W 1/16W
10%
MF-LF MF-LF
5% If =FWPWR_PWRON is low when off: 402 2
2 402
2
50V
CERM
XW1990
1/16W SM
MF-LF 1 402
402 R1963 Enables port power when machine is VESTA1V2_SGND 1 2
470K VOLTAGE=0V
5% running or on AC and not shut down. MIN_LINE_WIDTH=0.38 mm
1/16W MIN_NECK_WIDTH=0.25 mm
MF-LF
402
2
=PP2V5_VESTA 10
L1900
FERR-EMI-600-OHM
10 =PP1V2_VESTA C1920 1
C1921 1
C1922 1
C1923 1
C1924 1
C1925 1
B 1
SM
2 PP1V2_VESTA_AVDDL
VOLTAGE=1.2V
0.1uF
20%
10V
0.1uF
20%
10V
0.1uF
20%
10V
0.1uF
20%
10V
0.1uF
20%
10V
0.1uF
20%
10V
B
MIN_LINE_WIDTH=0.5 mm CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2
MIN_NECK_WIDTH=0.25 mm 402 402 402 402 402 402
1
C1908 C1900 1
C1901 1
C1902 1
C1903 1
10UF 0.1uF 0.1uF 0.1uF 0.1uF
20% 20% 20% 20% 20%
6.3V 10V 10V 10V 10V
2 X5R CERM 2 CERM 2 CERM 2 CERM 2
603 402 402 402 402
L6/M6 L9/M9 N5/N6 N9/N10 C1930 1
C1931 1
0.1uF 0.1uF
20% 20%
10V 10V
CERM 2 CERM 2
402 402
B15
C15
N10
P10
P11
R12
A15
B1
J1
L6
L9
M6
M9
N5
N6
N9
P4
P5
R3
N4
C1910 1 C1911 1 C1912 1 C1913 1
=PP3V3_VESTA 10 18 65 66 67
0.1uF 0.1uF 0.1uF 0.1uF
20%
10V
20%
10V
20%
10V
20%
10V
DVDD AVDDL AVDD PVDD
CERM 2 CERM 2 CERM 2 CERM 2
402 402 402 402
A1
C1940 1
C1941 1
C1942 1
C1943 1
Reset circuit per Vesta design guide 0.1uF 0.1uF 0.1uF 0.1uF
OVDD
A7 20% 20% 20% 20%
10V 10V 10V 10V
(Int PU) F15 CERM 2 CERM 2 CERM 2 CERM 2
67 66 65 18 10 =PP3V3_VESTA VESTA_RESET_L
Schmitt trigger
H4 RESET* VESTA MISC K1
402 402 402 402
65 18 10 =PP3V3_VESTA
R1950 1 R1951 1 67 66 9 =JTAG_VESTA_TDI D7 TDI
OMIT
20K 10K 9 =JTAG_VESTA_TDO E10 TDO
3
5%
1/16W
5%
1/16W
R1952 1 9 =JTAG_VESTA_TCK E7 TCK U8500 2.5V_EN M3 TP_VESTA_2_5V_EN
MF-LF
402 2
MF-LF
402 2 VESTA_RESET 66
D Q1950 10K
5% 9 =JTAG_VESTA_TMS E8 TMS BCM5462
2N7002DW-X-F 1/16W FBGA-200
VESTA_RESET_L_RC 5 G
SOT-363 MF-LF 9 =JTAG_VESTA_TRST_L D8 TRST* 1 OF 3
TP_VESTA_REGSUP1
S 402
2
REGSUP1 E1
4
REGSEN1 F1 TP_VESTA_REGSEN1 Vesta Power & Misc
C1950 1 6 TP_VESTA_DNC_B9 B9 DNC REGCTL1 G5 NC? TP_VESTA_REGCTL1
A 1uF
10%
6.3V
2
D Q1950
2N7002DW-X-F
TP_VESTA_DNC_C9
TP_VESTA_DNC_E9
C9
E9
DNC
DNC
SYNC_MASTER=MARIAS

A
CERM SOT-363
402 2 TP_VESTA_REGSUP2
G S R1952 to enable wirespeed feature REGSUP2 E2
NC C3 NC REGSEN2 F2 TP_VESTA_REGSEN2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
NC M13 NC REGCTL2 G4 NC? TP_VESTA_REGCTL2
AGND GND III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

H11
H12
J11
J12
L7
L8
M7
M8
N7
N8
P6
P7
P8
P9
A2
B2
B7
C14
F14
J2
K2
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 19 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes 10 =PPVCORE_PWRON_I2
VCore Bypassing (25 Balls on I2) 4 X 10uF (0603)
25 X 1uF (0402)
- =PPVCORE_PWRON_I2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
- =PP1V5_PWRON_I2_PLL C2146 C2147 C2120 C2121 C2122 C2123 C2124 C2125 C2126 C2127 C2128 C2129 C2130 C2131 C2132
- =PP3V3_PWRON_I2_IO1 10UF 10UF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
20% 20% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
- =PP3V3_PWRON_I2_IO2 X5R 2 X5R 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
603 603 402 402 402 402 402 402 402 402 402 402 402 402 402
- =PP3V3_PWRON_I2_AGPPCI
- =PP3V3_PWRON_I2_MAXBUS
NOTE: The four 3.3V rails are meant to be
aliased together. They are called
C2148 1
C2149 1 1
C2133 1
C2134 1
C2135 1
C2136 1
C2137 1
C2138 1
C2139 1
C2140 1
C2141 1
C2142 1
C2143 1
C2144
out separately for test purposes.
D NOTE: When these four rails are not
10UF
20%
6.3V
X5R 2
10UF
20%
6.3V
X5R 2 2
1uF
10%
6.3V
CERM 2
1uF
10%
6.3V
CERM 2
1uF
10%
6.3V
CERM 2
1uF
10%
6.3V
CERM 2
1uF
10%
6.3V
CERM 2
1uF
10%
6.3V
CERM 2
1uF
10%
6.3V
CERM 2
1uF
10%
6.3V
CERM 2
1uF
10%
6.3V
CERM 2
1uF
10%
6.3V
CERM 2
1uF
10%
6.3V
CERM 2
1uF
10%
6.3V
CERM
D
aliased together, make sure there 603 603 402 402 402 402 402 402 402 402 402 402 402 402
is at least one 10uF cap per rail.
AA22
AB21
AC16
AC19
(NONE)
N17
P16
P20
R16
R18
R21
T15
T19
T22
U15
U18
U20
U22
V17
V19
V22
W18
W20
W22
Y15
Y17
VDD15_0
VDD15_1
VDD15_2
VDD15_3
VDD15_4
VDD15_5
VDD15_6
VDD15_7
VDD15_8
VDD15_9
VDD15_10
VDD15_11
VDD15_12
VDD15_13
VDD15_14
VDD15_15
VDD15_16
VDD15_17
VDD15_18
VDD15_19
VDD15_20
VDD15_21
VDD15_22
VDD15_23
VDD15_24
(NONE)
OMIT OMIT
U2100 U2100
I2 I2
BGA BGA
CORE POWER & GND
PLL POWER
10 =PP1V5_PWRON_I2_PLL R2101 (3 of 14) (1 of 14)
4.7 AA20
1 2 PP1V5_PWRON_I2_PLL1AVDD PLL1_AVDD
VOLTAGE=1.5V AA13 AJ29 E32 P17
5% MIN_LINE_WIDTH=0.25 mm VSS_0 VSS_50 VSS_100 VSS_150
1/16W MIN_NECK_WIDTH=0.2 mm AA15 AJ32 E35 P2
1
C2101 MF-LF
402
VSS_1 VSS_51 VSS_101 VSS_151
1uF PLL1 AA17
VSS_2 VSS_52 AJ35 E5
VSS_102 VSS_152 P21
10%
2
6.3V 32/48 MHZ AA21
VSS_3 VSS_53 AJ5 E8
VSS_103 VSS_153 P24
CERM
402 AA25 AJ8 H11 P27
VSS_4 VSS_54 VSS_104 VSS_154
AA29 AM11 H12 P29
Y20 VSS_5 VSS_55 VSS_105 VSS_155
PLL1_VSSA AB12 AM14 H14 P32
R2102 VSS_6 VSS_56 VSS_106 VSS_156
C 3.3V I/O DECOUPLING 1
4.7
2 PP1V5_PWRON_I2_PLL2AVDD
VOLTAGE=1.5V
AA19
PLL2_AVDD
AB15
AB16
VSS_7
VSS_8
VSS_57
VSS_58
AM17
AM2
H15
H17
VSS_107
VSS_108
VSS_157
VSS_158
P35
P5
C
(48 Balls on I2) 1 X 10uF (0603) =PP3V3_PWRON_I2_IO1
5% MIN_LINE_WIDTH=0.25 mm AB22 AM20 H18 P8
10 1/16W MIN_NECK_WIDTH=0.2 mm VSS_9 VSS_59 VSS_109 VSS_159
48 X 1uF (0402) 1
C2102 MF-LF
AB24 AM23 H2 R13
1uF
402 VSS_10 VSS_60 VSS_110 VSS_160
10%
PLL2 AC2 AM26 H20 R15
6.3V 45.16 MHZ VSS_11 VSS_61 VSS_111 VSS_161
2 CERM AC20 AM29 H23 R17
C2150 1
C2151 1
C2152 1
C2153 1
C2154 1
C2155 1
402 VSS_12 VSS_62 VSS_112 VSS_162
1uF 1uF 1uF 1uF 1uF 1uF AC25
VSS_13 VSS_63 AM32 H24
VSS_113 VSS_163 R19
10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V Y19 AC26 AM35 H26 R20
CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 PLL2_VSSA VSS_14 VSS_64 VSS_114 VSS_164
402 402 402 402 402 402 R2103 AC29
VSS_15 VSS_65 AM5 H27
VSS_115 VSS_165 R22
OMIT 4.7 AK19 AC32 AM7 H29 R25
1 2 PP1V5_PWRON_I2_PLL3AVDD PLL3_AVDD VSS_16 VSS_66 VSS_116 VSS_166
VOLTAGE=1.5V AC35 AM8 H32 R29
U2100 5%
1/16W
MIN_LINE_WIDTH=0.25 mm VSS_17 VSS_67 VSS_117 VSS_167
MIN_NECK_WIDTH=0.2 mm AC5 AR11 H35 T16
I2 1
C2103 MF-LF VSS_18 VSS_68 VSS_118 VSS_168
C2156 1
C2157 1
C2158 1
C2159 1
C2160 1
C2161 1
1uF
402
AD16 AR14 H5 T18
BGA
1uF 1uF 1uF 1uF 1uF 1uF 10%
PLL3 VSS_19 VSS_69 VSS_119 VSS_169
3.3V I/O POWER 10% 10% 10% 10% 10% 10%
2
6.3V 49.15 MHZ AD21
VSS_20 VSS_70 AR17 H8
VSS_120 VSS_170 T20
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V CERM
CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 402 AD29 AR2 K10 U13
(2 of 14) 402 402 402 402 402 402 VSS_21 VSS_71 VSS_121 VSS_171
AH17 AE14 AR20 K11 U16
VDD33_AGP VDD33_0 AJ19 VSS_22 VSS_72 VSS_122 VSS_172
E3 PLL3_VSSA AE15 AR23 K14 U2
VDD33_1 R2104 VSS_23 VSS_73 VSS_123 VSS_173
F5 AE17 AR26 K17 U21
VDD33_2 4.7 H9 VSS_24 VSS_74 VSS_124 VSS_174
H3
1 2 PP1V5_PWRON_I2_PLL4AVDD PLL4_AVDD AE19 AR29 K20 U25
VDD33_3 C2162 1
C2163 1
5%
VOLTAGE=1.5V VSS_25 VSS_75 VSS_125 VSS_175
H6 1uF 1uF MIN_LINE_WIDTH=0.25 mm AE20 AR32 K23 U28
VDD33_IO_1 (14)
VDD33_4 1/16W MIN_NECK_WIDTH=0.2 mm VSS_26 VSS_76 VSS_126 VSS_176

I2S and some GPIOs
J8
10%
6.3V
10%
6.3V
1
C2104 MF-LF
PLL4 AE25 AR35 K25 U32
VDD33_5 CERM 2 CERM 2
1uF
402 VSS_27 VSS_77 VSS_127 VSS_177
L10 402 402 10%
SYSCLK AF10 AR5 K26 U35
VDD33_6 VSS_28 VSS_78 VSS_128 VSS_178
For USB, FireWire,
=PP3V3_PWRON_I2_IO2 10 2
6.3V PCI(SS)
L3 CERM AF18 AR8 K29 U5
VDD33_7 402 AGP(SS) VSS_29 VSS_79 VSS_129 VSS_179
L6 AF2 B11 L2 U8
N13 H10 AF27 B14 L20 V12
VDD33_9 PLL4_VSSA VSS_31 VSS_81 VSS_131 VSS_181
P12 C2164 1
C2165 1
C2166 1
C2167 1
C2168 1
C2169 1
R2105 AF29 B17 L27 V16
VDD33_10 1uF 1uF 1uF 1uF 1uF 1uF VSS_32 VSS_82 VSS_132 VSS_182
4.7
B VDD33_11
VDD33_12
P3
P6
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2
10%
6.3V
CERM
402
2
1
5%
2 PP1V5_PWRON_I2_PLL5AVDD
VOLTAGE=1.5V
AD9
PLL5_AVDD AF32
AF35
VSS_33
VSS_34
VSS_83
VSS_84
B2
B20
L29
L32
VSS_133
VSS_134
VSS_183
VSS_184
V20
V28
B
1/16W
VDD33_13 R14 1
C2105 MF-LF
PLL5 AF5
VSS_35 VSS_85 B23 L35
VSS_135 VSS_185 W15
T13 1uF
402 INT REF AF8 B26 L5 W19
VDD33_14 10% PCI VSS_36 VSS_86 VSS_136 VSS_186
AB13 6.3V AG11 B29 L8 W21
VDD33_15 2 CERM AGP VSS_37 VSS_87 VSS_137 VSS_187
VDD33_16 AC15
C2170 1
C2171 1
C2172 1
C2173 1
C2174 1
C2175 1 402 ATA AG14
VSS_38 VSS_88 B32 M13
VSS_138 VSS_188 W25
AC3 1uF 1uF 1uF 1uF 1uF 1uF AG29 B35 M15 W26
VDD33_IO_2 (12)
VDD33_17 10% 10% 10% 10% 10% 10% AE9 VSS_39 VSS_89 VSS_139 VSS_189
AC6 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V PLL5_VSSA AH14 B5 M17 Y11
For GPIOs, Pwr Mgt
CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 R2106

AF11 402 402 402 402 402 402 AJ11 B8 M19 Y16
VDD33_19 4.7 M24 VSS_41 VSS_91 VSS_141 VSS_191
AF3
1 2 PP1V5_PWRON_I2_PLL6AVDD PLL6_AVDD AJ14 E11 M21 Y18
VDD33_20 VOLTAGE=1.5V VSS_42 VSS_92 VSS_142 VSS_192
AF6
=PP3V3_PWRON_I2_MAXBUS 10 5% MIN_LINE_WIDTH=0.25 mm AJ17 E14 M23 Y2
VDD33_21 1/16W MIN_NECK_WIDTH=0.2 mm VSS_43 VSS_93 VSS_143 VSS_193
AF9
=PP3V3_PWRON_I2_AGPPCI 10
1
C2106 MF-LF
AJ2 E17 M26 Y22
VDD33_22 1uF
402 VSS_44 VSS_94 VSS_144 VSS_194
AJ3 10%
PLL6 AJ20 E2 N14 Y29
VDD33_23 6.3V SYS TRACK VSS_45 VSS_95 VSS_145 VSS_195
AJ6 2 CERM AJ23 E20 N16 Y32
VDD33_24 402 VSS_46 VSS_96 VSS_146 VSS_196
AM3 C2176 1
C2177 1
C2178 1
C2179 1 1
C2199 AJ24 E23 N18 Y35
VDD33_25 1uF 1uF 1uF 1uF 10UF VSS_47 VSS_97 VSS_147 VSS_197
Y13 10% 10% 10% 10% 20% N24 AJ26 E26 N23 Y5
VDD33_26 6.3V 6.3V 6.3V 6.3V 6.3V PLL6_VSSA VSS_48 VSS_98 VSS_148 VSS_198
VDD33_27 M16 CERM 2 CERM 2 CERM 2 CERM 2 2 X5R R2107 AJ27
VSS_49 VSS_99 E29 N25
VSS_149 VSS_199 Y8
402 402 402 402 603 4.7
VDD33_ M18 AH22
VDD33_28 1 2 PP1V5_PWRON_I2_PLL7AVDD PLL7_AVDD
MAXBUS M22 VOLTAGE=1.5V
VDD33_29 5% MIN_LINE_WIDTH=0.25 mm
AC21
VDD33_30 1
C2107 MF-LF
402
VDD33_31 AD20
C2180 1 C2181 1 C2182 1 C2183 1 C2184 1 C2185 1 1uF PLL7
10%
VDD33_32 AD22 1uF 1uF 1uF 1uF 1uF 1uF 2
6.3V PCI TRACK
10% 10% 10% 10% 10% 10% CERM
AH20 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 402
VDD33_33 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2
AH23 402 402 402 402 402 402
VDD33_34 AH21
PLL7_VSSA
VDD33_35 AH24
R2109 I2 Power
VDD33_PCI (18)
AH26
VDD33_36 4.7 AK10
PP1V5_PWRON_I2_PLL9AVDD
A VDD33_37
VDD33_38
AH27
AL23 C2186 1 C2187 1 C2188 1 C2189 1 C2190 1 C2191 1

1
5%
1/16W
2
VOLTAGE=1.5V
PLL9_AVDD SYNC_MASTER=MARIAS

A
1uF 1uF 1uF 1uF 1uF 1uF 1
C2109 MF-LF
AL24 10% 10% 10% 10% 10% 10%
VDD33_39 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 1uF
402
AL26 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 10%
PLL9 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
VDD33_40 402 402 402 402 402 402 6.3V AGP TRACK PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AL27 2 CERM AGREES TO THE FOLLOWING
VDD33_41 402
AL29 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
VDD33_42
AL30 AL10 II NOT TO REPRODUCE OR COPY IT
VDD33_43 PLL9_VSSA
AP23 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
VDD33_44 C2192 1
C2193 1
C2194 1
C2195 1
C2196 1
C2197 1
VDD33_45 AP26 1uF 1uF 1uF 1uF 1uF 1uF SIZE DRAWING NUMBER REV.
10% 10% 10% 10% 10% 10%
051-6839 F
AP29 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
VDD33_46
VDD33_47 AP32
CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2
APPLE COMPUTER INC.

D
SCALE SHT OF
NONE 21 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PP2V7R5V5_PWRON_I2VCORE
- =PPVCORE_PWRON_I2_REG
- =PPVIN_PWRON_I2PLLVDD
- =PP1V5_PWRON_I2PLLVDD_LDO

- =I2VCORE_PGOOD
BOM options provided by this page: I2 VCore Regulator

- I2VCORE_CONT / I2VCORE_BURST
D Selects between forced continuous and D
burst mode for LTC3412 regulator. 10 =PP2V7R5V5_PWRON_I2VCORE
One for each PVIN pin
- I2VCORE_xVx
Selects appropriate resistor for the Vout = 0.8V * (1 + (Ra / (Rb1 + Rb2)))
indicated LTC3412 output voltage. 1
C2200 1
C2201
22uF 22uF PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION
I2VCORE_CONT 20% 20%
1 1 6.3V 6.3V
R2207 R2208 2 CERM 2 CERM 114S0437 1 RES,185K,1%,MF-LF,0402 R2210 I2VCORE_1V6
1206 1206
4.7M 0
5% 5% 114S0442 1 RES,210K,1%,MF-LF,0402 R2210 I2VCORE_1V7
1/16W 1/16W
16
MF-LF MF-LF
9
402
2
402
2
114S0446 1 RES,232K,1%,MF-LF,0402 R2210 I2VCORE_1V8
SVIN PVIN
U2200 =I2VCORE_PGOOD 26
I2VCORE_RT LTC3412
MIN_LINE_WIDTH=0.20 mm TSSOP-LF Open-Collector
MIN_NECK_WIDTH=0.15 mm 5 RT CRITICAL
PGOOD 2
I2VCORE_RUNSS 7 RUN/SS L2200
MIN_LINE_WIDTH=0.20 mm 1.0uH-3.48A
MIN_NECK_WIDTH=0.15 mm CRITICAL =PPVCORE_PWRON_I2_REG 10
I2VCORE_ITH I2VCORE_SW 1 2
3 ITH 10
MIN_NECK_WIDTH=0.15 mm 6 SYNC/MODE 11 MIN_NECK_WIDTH=0.25 mm SM-LF
SW SWITCH_NODE=TRUE
1
R2205 R2204
1 I2VCORE_MODE 14 I2VCORE_1V5 1
C2215
MIN_LINE_WIDTH=0.20 mm 47uF
7.5K
1%
309K
1%
MIN_NECK_WIDTH=0.15 mm 4 VFB 15
R2210 1 1
C2210 20%
I2VCORE_VFB 6.3V
1/16W 1/16W THERM 162K 22pF 2 X5R
MF-LF MF-LF MIN_LINE_WIDTH=0.20 mm 1%
C2207 1
402 402 MIN_NECK_WIDTH=0.15 mm SGND PGND PAD 1/16W
5%
50V
1206-1
2 2
12
13
17
MF-LF 2
470pF 402
CERM
C2216 1
10% I2VCORE_ITH_RC 2 402
50V
2 MIN_LINE_WIDTH=0.20 mm <Ra> 47uF
CERM 20%
402 MIN_NECK_WIDTH=0.15 mm 6.3V
X5R 2
1
C2206 C2205 1
1206-1
100pF 2200pF
5% 5%
XW2200
C 2
50V
CERM
402
50V
CERM
603
2
GND_I2VCORE 1
SM
2
C
VOLTAGE=0V
I2VCORE_BURST MIN_LINE_WIDTH=0.75 mm
R2209 1 R2211 1
0 110K
5% 1%
1/16W 1/16W
MF-LF MF-LF
402 402
2 2
<Rb1>
I2VCORE_MODE_VDIV
If I2VCORE_BURST is selected: 1
R2212
Iburst = (Vburst - 0.2V) * (3.75A / 0.8V) 75K
1%
1/16W
Vburst = 0.8V * (Rb2 / (Rb1 + Rb2)) MF-LF
402
2
<Rb2>
B B
I2 PLL LDO
=PP1V5_PWRON_I2PLL_LDO 10
CRITICAL
Vout = 1.22V * (1 + Ra/Rb) + (Iadj * Ra)
U2250 1
R2255
=PPVIN_PWRON_I2PLLVDD LT1962-ADJ C2254 1
15.8K
Iadj = 30nA at 25 C
10
MSOP-LF 0.01uF 1%
8
IN OUT 1 10%
16V 1/16W
CERM 2 MF-LF
402
NC 7
NC 402 2 1
C2259
C2250 1
<Ra> 10uF
1uF ADJ 2 I2PLLVDD_ADJ 20%
20%
NC 6
NC 2
6.3V
10V X5R
CERM 2 603
603 BYP 3 I2PLLVDD_BYP 1
R2256
5
SHDN GND 4 68.1K
1%
1/16W
MF-LF
402
2
<Rb>
I2 Power Supplies

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 22 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
I2_MAXBUS_FBCLK_IN
MaxBus Feedback Clock Network
I2_FBCLK I2_FBCLK 21
I2_FBCLK I2_FBCLK I2_MAXBUS_FBCLK_MATCHED 21
I2_FBCLK I2_FBCLK I2_AGP_FBCLK_IN 21

21 I2_MAXBUS_FBCLK_MATCHED
I2_FBCLK I2_FBCLK I2_AGP_FBCLK_MATCHED 21
I105 I2_FBCLK I2_FBCLK I2_PCI_FBCLK_IN 21
I104 I2_FBCLK I2_FBCLK I2_PCI_FBCLK_MATCHED 21

I2_MAXBUS_FBCLK_MATCHED I2_MAXBUS_FBCLK_MATCHED
I119 CLOCK CLOCK =CLK33M_TBEN_SYNC 11 21 R2350 1 1
R2352
D I120 CLOCK CLOCK =SYSCLK_TBEN_SYNC 11 21 0
5%
1/16W I2_MAXBUS_FBCLK_SHORTEST
0
5%
1/16W
D
MF-LF MF-LF
402
2 R2340 2
402
Keep short 0 Keep short

32 IN I2_MAXBUS_FBCLK_OUT 1 2 21 I2_MAXBUS_FBCLK_IN =I2_MAXBUS_FBCLK_IN OUT 32
MAKE_BASE=TRUE
5%
1/16W
MF-LF
402
AGP Feedback Clock Ladder

I2_AGP_FBCLK_MATCHED
R2365
0
43 IN I2_AGP_FBCLK_OUT 1 2 21 I2_AGP_FBCLK_MATCHED
I2_AGP_FBCLK_SHORTEST 5%
1/16W
1 MF-LF
R2360 402
0
5%
1/16W I2_AGP_FBCLK_MATCHED
MF-LF
402
2 R2367
0
43 OUT =I2_AGP_FBCLK_IN 21 I2_AGP_FBCLK_IN 1 2
MAKE_BASE=TRUE
5%
1/16W
C MF-LF
402 C
I2 Configuration Straps
=PP1V5R1V8_MAXBUS
PCI Feedback Clock Ladder
34 33 32 10
I2_PCI_FBCLK_MATCHED
I2_MAXBUS_33OHM MAXBUS_D43_PU MAXBUS_D41_PU R2385
1 1 1 0
R2302 R2306 R2310 59 I2_PCI_FBCLK_OUT 1 2 21 I2_PCI_FBCLK_MATCHED
10K 10K 10K IN
5% 5% 5% I2_PCI_FBCLK_SHORTEST 5%
1/16W 1/16W 1/16W 1/16W
1 MF-LF
MF-LF MF-LF MF-LF R2380 402
2 402 2 402 2 402 0
5%
I2_FW_BETA MAXBUS_D44_PU MAXBUS_D42_PU 1/16W I2_PCI_FBCLK_MATCHED
MF-LF
1 1 1
R2300 R2304 R2308 402
2 R2387
10K 10K 10K 0
OUT =I2_PCI_FBCLK_IN I2_PCI_FBCLK_IN
5% 5% 5% 59 21 1 2
1/16W 1/16W 1/16W MAKE_BASE=TRUE
MF-LF MF-LF MF-LF 5%
402 2 402 2 402 2 1/16W
MF-LF
402
33 32 9 MAXBUS_DATA<62>
MAXBUS_TBEN_SYNC MAXBUS_TBEN_SYNC MAXBUS_TBEN_SYNC
33 32 9 MAXBUS_DATA<42> 1 C2390 1 C2391 1 C2392
33 32 9 MAXBUS_DATA<41> 0.1uF 0.1uF 0.1uF
20% 20% 20%
I2_MAXBUS_50OHM MAXBUS_D43_PD MAXBUS_D41_PD 10V
2 CERM 2 10V 2 10V
CERM CERM
B 1
R2303
10K
1
R2307
10K
1
R2311
10K
402 402 402
B
5% 5% 5%
1/16W 1/16W 1/16W 10 =PP1V8_RUN_TBEN_SYNC
MF-LF MF-LF MF-LF
2 402 2 402 2 402
MAXBUS_TBEN_SYNC MAXBUS_TBEN_SYNC MAXBUS_TBEN_SYNC
A2 CRITICAL A2 CRITICAL A2 CRITICAL
I2_FW_LEGACY MAXBUS_D44_PD MAXBUS_D42_PD
VCC 74AUC1G74 VCC 74AUC1G74 VCC 74AUC1G74
R2301 1 R2305 1 R2309 1 MAXBUS_TBEN_SYNC
10K
5%
10K
5%
10K
5%
U2390 U2391 U2392 R2392
BGA-YZP BGA-YZP BGA-YZP 0
1/16W 1/16W 1/16W B2 B2 B2
MF-LF MF-LF MF-LF D2 D2 D2 MAXBUS_TBEN_SYNC 1 2 MAXBUS_TBEN 33
402 2 402 2 402 2 B1
PRE Q B1
PRE Q B1
PRE Q
TBEN_SYNC_F1 TBEN_SYNC_F2 5%
C2
D C1 C2
D C1 C2
D C1
1/16W
NC NC MF-LF
CLR Q* CLR Q* CLR Q* 402
21 11 =CLK33M_TBEN_SYNC A1 A1 A1
CLK CLK CLK
GND GND GND
D1 D1 D1
Signal Tied Description
HIGH 1394b Support (Beta Mode)

MAXBUS_DATA<62>
LOW 1394a Support (Legacy Mode)
HIGH 50-Ohm MaxBus Drivers

MAXBUS_DATA<54>
TBEN_SYNC_CLR_L
LOW 33-Ohm MaxBus Drivers
MAXBUS_DATA<44:41> See Table Below 21 11 =SYSCLK_TBEN_SYNC
TABLE_BOMGROUP_HEAD
BOM GROUP Tied Description BOM OPTIONS I2 Supplemental

TABLE_BOMGROUP_ITEM
A I2_MAXBUS_133MHZ
I2_MAXBUS_150MHZ
0000
1000
133.12MHz CPU / 266.24MHz DDR
149.76MHz CPU / 299.52MHz DDR

MAXBUS_D44_PD,MAXBUS_D43_PD,MAXBUS_D42_PD,MAXBUS_D41_PD
TABLE_BOMGROUP_ITEM
MAXBUS_D44_PU,MAXBUS_D43_PD,MAXBUS_D42_PD,MAXBUS_D41_PD
SYNC_MASTER=MARIAS

A
TABLE_BOMGROUP_ITEM
I2_MAXBUS_166MHZ 0100 166.40MHz CPU / 332.80MHz DDR MAXBUS_D44_PD,MAXBUS_D43_PU,MAXBUS_D42_PD,MAXBUS_D41_PD THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
TABLE_BOMGROUP_ITEM

I2_MAXBUS_172MHZ 1100 171.95MHz CPU / 342.90MHz DDR MAXBUS_D44_PU,MAXBUS_D43_PU,MAXBUS_D42_PD,MAXBUS_D41_PD
TABLE_BOMGROUP_ITEM
I2_MAXBUS_177MHZ 0010 177.49MHz CPU / 354.98MHz DDR MAXBUS_D44_PD,MAXBUS_D43_PD,MAXBUS_D42_PU,MAXBUS_D41_PD II NOT TO REPRODUCE OR COPY IT
TABLE_BOMGROUP_ITEM

I2_MAXBUS_183MHZ 1010 183.04MHz CPU / 366.08MHz DDR MAXBUS_D44_PU,MAXBUS_D43_PD,MAXBUS_D42_PU,MAXBUS_D41_PD
TABLE_BOMGROUP_ITEM

I2_MAXBUS_189MHZ 0110 188.59MHz CPU / 377.18MHz DDR MAXBUS_D44_PD,MAXBUS_D43_PU,MAXBUS_D42_PU,MAXBUS_D41_PD
I2_MAXBUS_194MHZ 1110 194.13MHz CPU / 388.26MHz DDR

TABLE_BOMGROUP_ITEM
MAXBUS_D44_PU,MAXBUS_D43_PU,MAXBUS_D42_PU,MAXBUS_D41_PD APPLE COMPUTER INC.

D 051-6839 F
TABLE_BOMGROUP_ITEM
SCALE SHT OF
I2_MAXBUS_200MHZ 0001 199.68MHz CPU / 399.36MHz DDR MAXBUS_D44_PD,MAXBUS_D43_PD,MAXBUS_D42_PD,MAXBUS_D41_PU
NONE 23 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
I2S0_DTI I2S I2S I2S0_DEV_TO_SB_DTI 7 22 74
I2S0_DTO I2S I2S I2S0_SB_TO_DEV_DTO_R 6 22
I2S0_MCLK I2S I2S I2S0_MCLK_R 6 22
Signal Direction
OMIT
I2S0_BITCLK I2S I2S I2S0_BITCLK_R 6 22
I2S0_SYNC_R U2100
Pin Direction
I2S0_SYNC I2S I2S 6 22
I2
I2S1_DTI I2S I2S I2S1_DEV_TO_SB_DTI 22 30
BGA
I2S1_DTO I2S I2S I2S1_SB_TO_DEV_DTO_R 6 22
I2S1_MCLK_R
MISCELLANEOUS
I2S1_MCLK I2S I2S 6 22
(4 OF 14)
D I2S1_BITCLK
I2S1_SYNC
I2S
I2S
I2S
I2S
I2S1_BITCLK_R
I2S1_SYNC_R
6 22
6 22 GPIO INTERFACE
Pin Address MPIC Int Int PU? Alt Func D
MODEM_RING2SYS_L AH1
30 25 22 EXT_00_H (Int PU) EXT_00 0x0_0058 46 (0x2E) Yes PCI_REQ_2_L (When PCI1_Slot2En = 10)
I2_XTAL XTAL XTAL I2_CLK18M_XOUT_R 22 AK4
25 22 PMU_INT_L EXT_01_H (Int PU) EXT_01 0x0_0059 47 (0x2F) Yes
(I2_XTAL) XTAL XTAL I2_CLK18M_XOUT 22 AT19
44 43 AGP_INT_L EXT_02_H EXT_02 0x0_005A 48 (0x30) No
(I2_XTAL) XTAL XTAL I2_CLK18M_XIN 22
AH2
74 7 AUDIO_LI_OPTICAL_PLUG_L EXT_03_H EXT_03 0x0_005B 49 (0x31) No
AUDIO_LI_DET_L J2
74 7 EXT_04_H EXT_04 0x0_005C 50 (0x32) No
Page Notes Audio Mute Sequencing 59 11 PCI_SLOTA_INT_L AR33

EXT_05_H - See Ethernet Sym
EXT_06_H
EXT_05
EXT_06
0x0_005D
0x0_005E
51
52
(0x33)
(0x34)
No
No
Prevents mute glitch from reaching audio circuit AN33
Power aliases required by this page: 59 11 PCI_SLOTD_INT_L EXT_07_H EXT_07 0x0_005F 53 (0x35) No
=PP3V3_AUDIO_MUTESEQ I2_EXT_08 AG4
- =PP3V3_PWRON_I2_GPIO 22 10 EXT_08_H (Int PU - rev 1) EXT_08 0x0_0060 54 (0x36) Yes
PMU_SB_NMI_L AK1
- =PP3V3_I2_PCISLOTEGPIOS (PWRON or PCI) 25 22 EXT_09_H (Int PU) EXT_09 0x0_0061 55 (0x37) Yes
1 1 AG1
Should be same as =PP3V3_PCI if slot E R2470 R2471 74 7 AUDIO_LO_OPTICAL_PLUG_L EXT_10_H EXT_10 0x0_0062 56 (0x38) No
is used, or else =PP3V3_PWRON_I2_GPIO. 100K 10K 25 22 MMM_FFIRQ_L AG3
EXT_11_H (Int PU) EXT_11 0x0_0063 57 (0x39) Yes
5% 5% AG2
1/16W 1/16W 25 22 MMM_SIRQ_L EXT_12_H (Int PU) EXT_12 0x0_0064 58 (0x3A) Yes
Signal aliases required by this page: MF-LF MF-LF AF1
2 402 2 402
I2_EXT_13 EXT_13_H EXT_13 0x0_0065 59 (0x3B) No PCI_GNT_2_L (When PCI1_Slot2En = 11)
(NONE) AE4
I2_EXT_14 EXT_14_H EXT_14 0x0_0066 60 (0x3C) No PCI_REQ_2_L (When PCI1_Slot2En = 11)
AUDIO_LO_MUTE_L 7 74 H1
BOM options provided by this page: 74 7 AUDIO_LO_DET_L EXT_15_H EXT_15 0x0_0067 61 (0x3D) No
AUDIO_GPIO_11 G4
- I2_REV1_NOT 3 74 7 EXT_16_H (Int PU - rev 1) EXT_16 0x0_0068 62 (0x3F) Yes
Use for I2 revisions > 1.0
D
Q2470 74 7 AUDIO_CODEC_RESET_L AK2
GPIO_EXT_00_H GPIO_00 0x0_006A 14 (0x0E) No
AUDIO_LO_MUTE 2N7002DW-X-F AJ1
SOT-363 22 11 =SPI_I2_REQ GPIO_EXT_01_H GPIO_01 0x0_006B 15 (0x0F) No SPIREQ (When SPISReqEn = 1)
5 G S
I2_GPIO_EXT_02 AH4
22 11 GPIO_EXT_02_H (Int PU) GPIO_02 0x0_006C 16 (0x10) Yes PCI_GNT_2_L (When PCI1_Slot2En = 10)
MODEM_RESET_L AH3
6 4 30 GPIO_EXT_03_H (Int PU) GPIO_03 0x0_006D 17 (0x11) Yes
FW_POWERDOWN M1
22 GPIO_04_H GPIO_04 0x0_006E N/A No
D
Q2470 22 I2_AUDIO_LO_MUTE_L G3
GPIO_05_H GPIO_05 0x0_006F N/A No
2N7002DW-X-F G1
SOT-363 22 I2_AUDIO_SPKR_MUTE_L GPIO_06_H GPIO_06 0x0_0070 N/A No
I2_AUDIO_LO_MUTE_L 2
C 22 G S
1
74 7
22
AUDIO_I2S_DTIB_SEL
I2_GPIO_11
AG8
G2
GPIO_09_H
GPIO_11_H (Int PU)
GPIO_09
GPIO_11
0x0_0073
0x0_0075
N/A
N/A
No
Yes
C
R24721 74 7 AUDIO_SPDIFRX_RESET_L AG7
GPIO_12_H (Int PU - rev 1) GPIO_12 0x0_0076 N/A Yes
100K AG6
5% MUTE_CONTROL 22 74 7 AUDIO_EXT_MCLK_SEL GPIO_15_H GPIO_15 0x0_0079 N/A No
1/16W
MF-LF GPIO_16_H - See Ethernet Sym GPIO_16 0x0_007A N/A No
402 2
Alternate GPIO Functions
I2C
Use MAKE_BASE to force net name J1
IIC_CLK_0_H =I2C_I2_NB_SCL 8
PCI_SLOTE_INT_L J3 =I2C_I2_NB_SDA
GPIO Pull-ups / Pull-downs 22 11
22 11 PCI_SLOTE_GNT_L
IIC_D_0_H 8
PCI_SLOTE_REQ_L F4 =I2C_I2_SB_SCL
22 11 IIC_CLK_2_H 8
=PP3V3_PWRON_I2_MISC 10 22
F1
IIC_D_2_H =I2C_I2_SB_SDA 8
=PP3V3_I2_PCISLOTEGPIOS 10 NO STUFF
R2460
10K
NO STUFF
R2461 E1
I2S 0 (Master)
C1
(Slave) Audio Mute Sequencing
EXT_00 Internal pull-up to 3.3V PWRON 1 2 MODEM_RING2SYS_L 22 25 30 74 22 7 I2S0_DEV_TO_SB_DTI AUD_DTI_A_H AUD_DTO_A_H I2S0_SB_TO_DEV_DTO_R 6 22
10K F2 Prevents mute glitch from reaching audio circuit
EXT_01 Internal pull-up to 3.3V PWRON 5% 1 2 PMU_INT_L 22 25 AUD_CLKOUT_A_H I2S0_MCLK_R 6 22
1/16W
F3 I2S0_BITCLK_R
EXT_02 10K Pull-up to 3.3V on I2 AGP page. MF-LF 5% AUD_BITCLK_A_H 6 22
402 1/16W
D2 22 10 =PP3V3_AUDIO_MUTESEQ
EXT_03 Pull-up/down to be provided by audio page. MF-LF AUD_SYNC_A_H I2S0_SYNC_R 6 22
402
EXT_04 Pull-up/down to be provided by audio page. 1 1
EXT_05 10K Pull-up to Enet OVdd on I2 Enet page.
22 10 =PP3V3_PWRON_I2_MISC I2S 1 (Master) (Slave) R2480 R2481
30 22 I2S1_DEV_TO_SB_DTI J5
MOD_DTI_B_H MOD_DTO_B_H G5 I2S1_SB_TO_DEV_DTO_R 6 22 100K 10K
EXT_06 10K Pull-up to 3.3V on I2 PCI page. J6 5% 5%
R2490 1 MOD_CLKOUT_B_H I2S1_MCLK_R 6 22 1/16W 1/16W
EXT_07 10K Pull-up to 3.3V on I2 PCI page. J7 MF-LF MF-LF
10K MOD_BITCLK_B_H I2S1_BITCLK_R 6 22
2 402 2 402
5% G6
I2_REV1_NOT 1/16W MOD_SYNC_B_H I2S1_SYNC_R 6 22
AUDIO_SPKR_MUTE_L
R2455 (I2_EXT_08)
MF-LF
402
7 74
1
10K
2 PCI_SLOTE_INT_L
2
SCCA
EXT_08 11 22 AG5 AE5 3
24 7 SCCA_RXD SCC_RXDA_H SCC_TXDA_L SCCA_TXD_L 7 24
5% (*) - Rev 1.0: Internal pull-up to 3.3V PWRON R2462
1/16W
MF-LF 10K SCCB/VIA
D Q2480
B EXT_09
402
Internal pull-up to 3.3V PWRON

1
5%
2 PMU_SB_NMI_L 22 25
25 VIA_PMU_TO_SB AL3
AM1
SCC_RXDB_H SCC_TXDB_L AL2
AL4
VIA_SB_TO_PMU 25
AUDIO_SPKR_MUTE
5 G S
2N7002DW-X-F
SOT-363 B
R2452 1/16W 25 VIA_ACK_L SCC_GPIOB_L SCC_RTSB_L VIA_REQ_L 25
EXT_10 Pull-up/down to be provided by audio page. MF-LF
10K 402 25 VIA_CLK AL1
SCC_TRXCB_H 6 4
EXT_11 1 2 MMM_FFIRQ_L 22 25
EXT_12 Internal pull-up to 3.3V PWRON 5% (*) - Rev 1.0: Missing internal pull-up to 3.3V PWRON
1/16W
TEST/JTAG D Q2480
MF-LF I2_TST_TEI AL6
TST_TEI_H 2N7002DW-X-F
402 SOT-363
RP2450 R2463 I2_TST_PLLEN AL5
TST_PLLEN_H 22 I2_AUDIO_SPKR_MUTE_L 2 G S
(I2_EXT_13) 10K
10K 1 2 MMM_SIRQ_L 22 25 =SPI_I2_MOSI =SPI_I2_MISO
EXT_13 2 7 PCI_SLOTE_GNT_L 11 22 1
5%
5%
1/16W R2400 1
1
R2401 9 =JTAG_I2_TDI AN6
JTG_TDI_H JTG_TDO_H AN4 =JTAG_I2_TDO 9 R24821
1/16W MF-LF 10K 10K 9 =JTAG_I2_TMS AN2
JTG_TMS_H 100K
RP2450 SM-LF 402 5% 5% AN3 5% MUTE_CONTROL 22
(I2_EXT_14) 1/16W 1/16W 9 =JTAG_I2_TCK JTG_TCK_H 1/16W
10K MF-LF MF-LF MF-LF
3 6 PCI_SLOTE_REQ_L =JTAG_I2_TRST_L AP1
EXT_14 11 22 402
2 2
402 9 JTG_TRSTN_L 402 2
5% =SPI_I2_CLK 6
1/16W POWER MGMT/CLOCK
SM-LF
62 25 22 SYS_WARM_RESET_L AK3
REF_PURESET_L PWR_PCI_PME_L AK7 SYS_PME_L 25 62
D Q2481
AH7
2N7002DW-X-F
EXT_15 Pull-up/down to be provided by audio page. 11 =I2_STOPXTAL_L PWR_STPXTL_L 2 SOT-363
62 25 22 SYS_WARM_RESET_L G S
=I2_STOPCPU_L AH6 AL7 SYS_WATCHDOG
EXT_16 Pull-up/down to be provided by audio page. (*) - See above 11 PWR_STPCPU_L PWR_INTRWD_H 25
GPIO_EXT_00 Pull-up/down to be provided by audio page. 1

NB_SUSPENDREQ_L AH5 AK5 NB_SUSPENDACK_L
25 PWR_SPDREQ_L PWR_SPDACK_L 25
RP2450 Put crystal circuit close to I2

10K 22 I2_CLK18M_XOUT_R
AC12
REF_CLK_OUT PWR_PENDINT_H AK6 TP_I2_PENDINT
GPIO_EXT_01 1 8 =SPI_I2_REQ 11 22 AC13
NO STUFF 22 I2_CLK18M_XIN REF_CLK_IN
5% NO STUFF
1/16W
SM-LF
R2451 (*) - Rev 1.0: Missing internal pull-up to 3.3V PWRON R2410
1
10K 2 I2_GPIO_EXT_02 11 22 1
10M
2
GPIO_EXT_02
GPIO_EXT_03 Internal pull-up to 3.3V PWRON
5%
1/16W
5%
1/16W
I2 Miscellaneous
MF-LF
402 R2411 1 MF-LF
A RP2450 5%
1/16W
0
402
CRITICAL
SYNC_MASTER=MARIAS

A
10K MF-LF
GPIO_04 4 5 FW_POWERDOWN 22 402 2 Y2410
18.432M THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
5%
1 2 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
SM-LF
22 I2_CLK18M_XOUT I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
8X4.5MM-SM1
GPIO_05 Pull-up/down to be provided by audio page. II NOT TO REPRODUCE OR COPY IT
GPIO_06 Pull-up/down to be provided by audio page. C2411 1 1
C2410 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
GPIO_09 Pull-up/down to be provided by audio page. R2464 22pF 22pF
10K 5% 5% SIZE DRAWING NUMBER REV.
1 2 I2_GPIO_11 50V 50V
GPIO_11 Internal pull-up to 3.3V PWRON 22 2 2
051-6839 F
CERM CERM
GPIO_12 Pull-up/down to be provided by audio page. (*) - See above 5%
1/16W
402 402
APPLE COMPUTER INC.

D
GPIO_15 Pull-up/down to be provided by audio page. MF-LF
402 SCALE SHT OF
GPIO_16 Pull-up/down to be provided by design.
Crystal load capacitance is 16pF NONE 24 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
I72 CLOCK CLOCK =PCI_CLK33M_ZDB_IN 11 23
I73 PCI_ZDBOUT0 CLOCK CLOCK =PCI_CLK33M_ZDBOUT_R<0> 11 23
Page Notes
D Power aliases required by this page:
- =PP3V3_PWRON_I2_GPIO
D
- =PP3V3_I2_PCISLOTEGPIOS (PWRON or PCI)
Should be same as =PP3V3_PCI if slot E
is used, or else =PP3V3_PWRON_I2_GPIO.

(NONE)

- I2_REV1_NOT
Use for I2 revisions > 1.0
C C
10 =PP3V3_PCI_ZDB
C2500 1 1 C2501
0.1uF 1uF
20% 10%
10V 2 6.3V
CERM 2 CERM
402 402
CRITICAL 6
VDD
CDCVF2505
23 11 =PCI_CLK33M_ZDB_IN 1 CLKIN 1Y0 3 =PCI_CLK33M_ZDBOUT_R<0> 11 23
1Y1 2 =PCI_CLK33M_ZDBOUT_R<1>
U2500 5
11 23
1Y2 =PCI_CLK33M_ZDBOUT_R<2> 11 23
SOIC 7 =PCI_CLK33M_ZDBOUT_R<3>
1Y3 11 23
CLKOUT 8 PCI_CLK_DELAY_ADJ
GND NO STUFF
4 C2502 1
0.001uF
20%
50V
CERM 2
402
B B
PCI Clock Buffer


A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 25 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PMU RESET CIRCUIT

25 24 10 =PP3V3_ALL_PMU
D 1
D
R2680
100K
5%
1/16W
MF-LF
DP2680 2 402
BAS16TW-X-F
12 SYS_AC_DET_L
SOT-363
6 1
PMU_RESET_L 24 25
SERIAL DEBUG INTERFACE
6
DP2680 D Q2680
BAS16TW-X-F
SOT-363 2N7002DW-X-F
SOT-363
25 12 SYS_BATT0_DET_L 5 2 PMU_CUSTOMER_RESET 2 G S
DEVELOPMENT
CRITICAL
1
3 J2690
QT500166-L020
D
Q2680
2N7002DW-X-F 1
M-ST-SM
2 SCCA_TXD_L
(WAS COMM_GPIO_L) NC 7 22
5 SOT-363 3 4
57 36 30 25 24 SYS_POWER_BUTTON_L G S 22 7 SCCA_RXD COMM_RTS_L NO_TEST=TRUE
(WAS COMM_TRXC) NC 5 6
4 7 8
25 24 PMU_RESET_L COMM_DTR_L NO_TEST=TRUE
(WAS PMU_BOOT_CE) NC 9 10 PMU_BOOT_TXD 25
11 12 DEVELOPMENT DEVELOPMENT
25 PMU_BOOT_SCLK PMU_BOOT_RXD 25 1 1
10 =PP3V3_ALL_DEBUG
25 PMU_BOOT_CNVSS 13 14 PMU_BOOT_BUSY 25 R2695 R2696
15 16 PMU_BOOT_RP_L 25
10K 10K
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 2 2 402
C C
SLEEP LED DEBUGGING AIDS

PLACE ON TOP SIDE NEAR FRONT EDGE OF BOARD
OMIT
10 =PP5V_PWRON_SLEEPLED
R2692
470K 2
R26011 R26001 1 SYS_POWER_BUTTON_L 24 25 30 36 57
2.2K 100 5% PLACE "POWER BTN" IN SILK NEAR RESISTOR
5% 5% 1/10W
1/16W 1/16W MF-LF OMIT
MF-LF MF-LF 603
402 2 402 2 R2690
SLEEP_LED_L SLEEP_LED_I 1
470K 2 PMU_RESET_L 24 25
Q2600 MIN_NECK_WIDTH=0.25 mm 5% PLACE "PMU RESET" IN SILK NEAR RESISTOR
2
1/10W
R2602 2N3906 MF-LF
SOT23-LF OMIT 603
4.7K 1
SLEEP_LED_SW_L
R2691
5%
1/16W 1
470K 2 SYS_RESET_BUTTON_L 25 36
MF-LF
402 3 5% PLACE "SYS RESET" IN SILK NEAR RESISTOR
3 1/10W
=SLEEP_LED_IOUT 11 MF-LF
D
Q2601 603
B 1
2N7002
SOT23-LF
B
25 SYS_LED G S
CHARGE LED
25 24 10 =PP3V3_ALL_PMU
1
R2610
470K
5%
1/16W
MF-LF
2 402
25 SYS_ONEWIRE SYS_CHARGE_LED_L 7 31
LEDs/Reset/Debug

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 26 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
PMU_CLK10M_XTAL XTAL XTAL PMU_CLK10M_XIN 25
XTAL XTAL PMU_CLK10M_XOUT 25
XTAL XTAL PMU_CLK10M_XOUT_R 25
PMU_CLK32K_XTAL XTAL XTAL PMU_CLK32K_XIN 25
XTAL XTAL PMU_CLK32K_XOUT 25
XTAL XTAL PMU_CLK32K_XOUT_R 25

Power Management Unit
Page Notes D
D Power aliases required by this page:
25 24 10 =PP3V3_ALL_PMU
1
R2705
4.7
2
PP3V3_ALL_PMU_AVCC
VOLTAGE=3.3V
10
- =PP3V3_ALL_PMU MIN_NECK_WIDTH=0.25 mm
5%
- =PP3V3_PWRON_PMU 1 1 1
1/16W
1
C2702 C2701 C2700 MF-LF C2705
- =PPVREF_PMU (PMU AVCC or 2.5V reference) 10UF 0.1uF 0.1uF 402
1uF
20% 20% 20% 10%
6.3V 10V 10V 6.3V
Signal aliases required by this page: X5R 2 CERM 2 CERM 2 2 CERM
603 402 402 402
- =I2C_PMU_SCL
GND_PMU_AVSS 25 28 29 31
- =I2C_PMU_SDA
- =I2C_PMU_SMB_SCL
- =I2C_PMU_SMB_SDA
- =JTAG_BBANGER_TCK 13 78
- =JTAG_BBANGER_TDI VCC AVCC
- =JTAG_BBANGER_TMS U2700
Spares (Analog capable)
- =JTAG_BBANGER_TRST_L M30280F8-LF
QFP-80 RTS0*/
NOTE: Boot-banger pins can be aliased to 11 TP_PMU_AN_P0_0 67 P0[0] AN00 CTS0* P6[0] 43 GOV_RESET_L 11
TP_ or NC_ if not implemented. 11 TP_PMU_AN_P0_1 66 P0[1] AN01 OMIT CLK0 P6[1] 42 PCI_RESET_L 11 25
11 TP_PMU_AN_P0_2 65 P0[2] AN02 RxD0 P6[2] 41 SYS_WARM_RESET_L 22 25 62

11 TP_PMU_AN_P0_3 64 P0[3] AN03 TxD0 P6[3] 40 SYS_COLD_RESET_L 25
(NONE)
11 TP_PMU_AN_P0_4 63 P0[4] AN04 RTS1*/BUSY P6[4] 31 PMU_BOOT_BUSY 24
NOTE: TP_PMU_Px_x signals are general- 11 TP_PMU_AN_P0_5 62 P0[5] AN05 CLK1 P6[5] 30 PMU_BOOT_SCLK 24
purpose spares. Some pins are 25 TP_PMU_AN_P0_6 61 P0[6] AN06 RxD1 P6[6] 29 PMU_BOOT_RXD 24
reserved for alternate functions. 25 TP_PMU_AN_P0_7 60 P0[7] AN07 TxD1 P6[7] 28 PMU_BOOT_TXD 24
TP_PMU_AN_Px_x signals are general- PMU_BOOT_RP_L 24

SDA/TxD2/
purpose spares that can also be used 25 22 NB_SUSPENDREQ_L 59 P1[0] AN20 TA0out P7[0] 27 TP_PMU_P7_0 25
as analog inputs. 22 NB_SUSPENDACK_L 58 P1[1] AN21 SCL/RxD2/TA0in P7[1] 26 TP_PMU_P7_1 25
11 PMU_CPU_CLK_EN 57 P1[2] AN22 CLK2/TA1out P7[2] 25 TP_PMU_P7_2 25

NOTE: All analog inputs to PMU should have
C a 100pF capacitor to the PMU AVSS
signal (GND_PMU_AVSS). None of
36 25 24
11 PMU_SYS_CLK_EN
SYS_RESET_BUTTON_L
56
55
P1[3]
P1[4]
AN23 TA1in
TA2out
P7[3] 24
P7[4] 23
SYS_ACIN
TP_PMU_P7_4
12 13 18
11 25
C
57 36 30 25 24 SYS_POWER_BUTTON_L 54 P1[5] INT3*/ADtrig TA2in P7[5] 22 TP_PMU_P7_5 11 25
those capacitors are provided on
30 SYS_LID_OPEN 53 P1[6] INT4* TA3out P7[6] 21 SYS_KBDLED 28
this page.
30 22 MODEM_RING2SYS_L 52 P1[7] INT5* TA3in P7[7] 20 SYS_OVERTEMP_L 7 11 25 30
PMU Pull-ups / pull-downs 8 =I2C_PMU_SMB_SDA 51 P2[0] ICOC0/SDAmm TA4out P8[0] 19 SYS_LED 24
8 =I2C_PMU_SMB_SCL 50 P2[1] ICOC1/SCLmm TA4in P8[1] 18 PMU_BATT0_CHARGE 13

=PP3V3_ALL_PMU 10 24 25
8 =I2C_PMU_SDA 49 P2[2] ICOC2 INT0* P8[2] 17 SYS_BATT0_DET_L 12 24
R2760 8 =I2C_PMU_SCL 48 P2[3] ICOC3 INT1* P8[3] 16 SYS_PME_L 22 25 62
10K 9 =JTAG_BBANGER_TRST_L 47 P2[4] ICOC4 INT2* P8[4] 15 SYS_AC_DET 12

1 2 PMU_POWER_UP_L 25 26
9 =JTAG_BBANGER_TMS 46 P2[5] ICOC5 RP/NMI* P8[5] 14 SYS_ONEWIRE 24
5%
R2761 1/16W 9 =JTAG_BBANGER_TDI 45 P2[6] ICOC6 CE*/Xcout P8[6] 8 25 PMU_CLK32K_XOUT_R
MF-LF
10K 402 9 =JTAG_BBANGER_TCK 44 P2[7] ICOC7 Xcin P8[7] 7 25 PMU_CLK32K_XIN
1 2 SYS_POWER_BUTTON_L 24 25 30 36 57
5%
1/16W 25 11 TP_PMU_P3_0 39 P3[0] CLK3 TB0in P9[0] 5 VIA_ACK_L 22 NO STUFF
MF-LF
402 25 11 TP_PMU_P3_1 38 P3[1] Sin3 TB1in P9[1] 4 VIA_REQ_L 22 25
R2750
25 11 TP_PMU_P3_2 37 P3[2] Sout3 TB2in P9[2] 3 PMU_INT_L 22 10M
=PP3V3_PWRON_PMU 10 1 2
25 11 TP_PMU_P3_3 36 P3[3] AN24 P9[3] 2 PMU_SB_NMI_L 22
5%
R2765 22 SYS_WATCHDOG 35 P3[4] CLK4/AN25 P9[5] 1 VIA_CLK 22 1/16W
1
MF-LF
10K 11 PMU_CPU_HRESET_L 34 P3[5] Sout4/AN26 P9[6] 80 VIA_PMU_TO_SB 22 402 R2751
2 1 SYS_PME_L 22 25 62 25 24 10 =PP3V3_ALL_PMU 0
26 25 PMU_POWER_UP_L 33 P3[6] Sin4//AN27 P9[7] 79 VIA_SB_TO_PMU 22 CRITICAL 5%
5% OMIT 1/16W
1/16W SYS_SLEEP 32 P3[7]
R2766 MF-LF
25
Spares (Analog capable) Y2750
MF-LF
100K 402 2 402
1 2 SYS_RESET_BUTTON_L 1 32.768K
24 25 36
3 R2710 AN0 P10[0] 76 TP_PMU_AN_P10_0 25
1 2
5% 150K
1/16W
MF-LF R2767 D2710 5%
=PPVREF_PMU
AN1 P10[1] 74 TP_PMU_AN_P10_1 25
SM1 PMU_CLK32K_XOUT
MMBD914XXG 1/16W 10
TP_PMU_AN_P10_2
25
402 10K SOT23 MF-LF AN2 P10[2] 73 25
B 1
5%
2 SYS_OVERTEMP_L 7 11 25 30 1
2 402
24 PMU_BOOT_CNVSS 6 PCNVSS AN3 P10[3] 72 TP_PMU_AN_P10_3 25
1 C2750 1 C2751
B
R2768 1/16W 24 PMU_RESET_L 9 RESET* KI0*/AN4 P10[4] 71 TP_PMU_AN_P10_4 25
12pF 12pF
MF-LF
PMU_CLK10M_XOUT_R XOUT TP_PMU_AN_P10_5 5% 5%
1
10K
2
402
VIA_REQ_L
25 10 KI1*/AN5 P10[5] 70 11 25 50V 50V
22 25 2 CERM 2 CERM
5%
C2710 1 25 PMU_CLK10M_XIN 12 XIN KI2*/AN6 P10[6] 69 TP_PMU_AN_P10_6 11 25 402 402
1/16W 0.22uF 77 VREF KI3*/AN7 P10[7] 68 TP_PMU_AN_P10_7 25
MF-LF 10%
6.3V
402
CERM-X5R 2 NO STUFF
402 1
R2770 R2740 VSS AVSS R2730
100K 10M 11 75 4.7K
1 2 SYS_COLD_RESET_L 25 1 2
R2715 1 1
C2720
5%
1/16W
TABLE_5_HEAD
5% 5% 4.7K 1uF MF-LF PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
1/16W 1/16W
MF-LF R2771 1 MF-LF
5%
10% 2
402
R2741 1/16W TABLE_5_ITEM
402 100K 402 6.3V

MF-LF 2 197S0163 1 XTAL,32.768KHZ,4.1X1.5X0.9MM,SMD Y2750 CRITICAL ?
1 2 SYS_WARM_RESET_L 22 25 62 0 402 2
CERM
402
XW2700
5% SM
5% 1/16W CRITICAL 1 2
1/16W
R2772 MF-LF
MF-LF
402 Y2740
100K 402 2
1 2 PCI_RESET_L 11 25
10.0000M
1 2 GND_PMU_AVSS 25 28 29 31
5% VOLTAGE=0V
1/16W
R2773 25 PMU_CLK10M_XOUT 8X4.5MM-SM1 MIN_LINE_WIDTH=0.38 mm
MF-LF Keep crystal subcircuit close to PMU. MIN_NECK_WIDTH=0.25 mm
402 100K
1 2 NB_SUSPENDREQ_L 22 25
5%
C2741 1 C2740 1 Y2740’s load capacitance is 12pF
1/16W 18pF 18pF
R2774 MF-LF 5% 5%
100K 402 50V 50V
CERM 2 CERM 2
1 2 SYS_SLEEP 25 402 402
5%
1/16W
MF-LF
402
Power Management Unit (PMU05)
A Additional PMU05 "Modules"

SYNC_MASTER=MARIAS

A
MMM ALS SPI Dual Battery Charger Battery Current Mon PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
25 TP_PMU_AN_P10_0 MMM_X_AXIS 29 25 TP_PMU_AN_P10_3 ALS_0_OUT 7 31 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
25 11 TP_PMU_P3_0 SPI_PMU_CHGR_CLK 25 TP_PMU_AN_P10_7 BATT_ISNS 12
25 TP_PMU_AN_P10_1 MMM_Y_AXIS 29 25 TP_PMU_AN_P10_4 ALS_1_OUT 28 II NOT TO REPRODUCE OR COPY IT
25 11 TP_PMU_P3_1 SPI_CHGR_TO_PMU_MISO
25 TP_PMU_AN_P10_2 MMM_Z_AXIS 29 25 TP_PMU_P7_2 ALS_GAIN_BOOST 7 28 31 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
25 11 TP_PMU_P3_2 SPI_PMU_TO_CHGR_MOSI
25 TP_PMU_P7_0 MMM_FFIRQ_L 22
TP_PMU_P3_3 SPI_PMU_CHGR_CS SIZE DRAWING NUMBER REV.
25 TP_PMU_P7_1 MMM_SIRQ_L 22 CPU T-Diodes 25 11
25
25
TP_PMU_AN_P0_7
TP_PMU_AN_P0_6
MMM_ACC_SELFTEST
MMM_ACC_PWRDOWN
29
29
25 11 TP_PMU_AN_P10_5 CPU0_TEMP
25 11
25 11
TP_PMU_P7_4
TP_PMU_P7_5
PMU_BATT1_DET_L
PMU_BATT1_CHARGE APPLE COMPUTER INC.
D 051-6839 F
25 11 TP_PMU_AN_P10_6 CPU1_TEMP SCALE SHT OF
NONE 27 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R2900 26 10 =PP3V3_ALL_PWRSEQ
ACTIVE-LOW, OUTPUT, OPEN-COLLECTOR
1
0 2
25 PMU_POWER_UP_L SYS_POWER_UP_L 1
100K pull-up to 3.3V_ALL on pg 13
5% R2901
1/16W 100K
MF-LF
402 R2902 5%
1/16W
0 MF-LF
1 2 5V3V3PWRON_EN_L =5V3V3PWRON_EN_L 15
2 402
5%
MAKE_BASE=TRUE R2903
1/16W 0
MF-LF SYS_POWERUP 1 2 FWPWR_PWRON =FWPWR_PWRON 18
402 MAKE_BASE=TRUE
5%
ACTIVE-HIGH, OUTPUT, PUSH-PULL 1/16W
6 MF-LF
11 SYS_PWRSEQ_1 402
D
Q2900 R2911
2N7002DW-X-F 0
R29132 10 =PP5V_PWRON_PWRSEQ SOT-363 1 2 1V8_1V5PWRON_EN_L =1V8_1V5PWRON_EN_L 16
D 100K
5% 1
2 G S 1
R2910
100K
5%
1/16W
MAKE_BASE=TRUE
D
1/16W
MF-LF
R2929 1 5%
1/16W
MF-LF
402
402 1 100K MF-LF
5%
1/16W 2 402 R2912
MF-LF
SYS_PWRSEQ_1_L
0 2V5PWRON_EN_L =2V5PWRON_EN_L
402 2 R2920 1 2
MAKE_BASE=TRUE
17
100K 2 3
5%
SYS_PWRSEQ_2_L 1 5VRUN_EN_L 15 1/16W
MF-LF
5%
1/16W
D
Q2900 402
TPAD_SEQ_HW
6
R2921 MF-LF 2N7002DW-X-F R2943
402 SOT-363
100K 2 5 0
D
Q2910 1 5VRUNHD_EN_L 15
G S
1 2 5VTPAD_EN_L =5VPWRONTPAD_EN_L 15
ACTIVE-HIGH, OUTPUT, PUSH-PULL 2N7002DW-X-F MAKE_BASE=TRUE
SOT-363 5% 4 5%
11 SYS_PWRSEQ_2 2 G S 1/16W 1/16W
MF-LF
402 R2922 MF-LF
402
1
1
100K 2
3V3RUN_EN_L 15
26 10 =PP3V3_PWRON_PWRSEQ
5%
1/16W TPAD_SEQ_PMU
MF-LF
R2930
402
R29481
ACTIVE-LOW, OUTPUT, PUSH-PULL 100K TPAD_SEQ_PMU
0 5% 1
11 SYS_PWRSEQ_3_L 1 2 2V5RUN_EN_L 17 1/16W
MF-LF
Q2948
5% 402 2 G 2N7002
1/16W SOT23-LF
MF-LF
402 11 SYS_PWRSEQ_TPAD_L 2 S D 3
26 10 =PP5V_RUN_PWRSEQ
R29351
100K
5%
1/16W
MF-LF
402 2 R2936
100K 2
C SYS_PWRSEQ_3_LS5 1
5%
1V5RUN_EN 16 C
1/16W
3 MF-LF
402
Q2910 D
2
2N7002DW-X-F
SOT-363
Q2941
S G 5 G 2N7002DW-X-F
SHUT-DOWN
SOT-363
POWER-UP
4 1 S D 6
SLEEP
26 10 =PP3V3_PWRON_PWRSEQ
WAKE
NO STUFF
1
R2941 R2940
0
100K 1 2 VCORE_CPU0_SHDN_L 36
5%
1/16W 5%
MF-LF 1/16W
MF-LF 1V8RUN_EN_L 16
ACTIVE-HIGH, OUTPUT/INPUT, OPEN-COLLECTOR 2 402 402
11 SYS_PWRSEQ_4
6
NO STUFF
R29491
D Q2940
2N7002DW-X-F
0 2 G S
SOT-363
5%
1/16W
MF-LF
402 2 1
10 =PP3V3_RUN_PWRSEQ 26 10 =PP3V3_ALL_PWRSEQ
15 =5V3VPWRON_PGOOD
16 =1V8_1V5PWRON_PGOOD PWRON_REGS_PGOOD
MAKE_BASE=TRUE 1
17 =2V5PWRON_PGOOD R2958
20 =I2VCORE_PGOOD 10K
5% 5
1/16W
MF-LF
Q2941
2N7002DW-X-F
B ACTIVE-HIGH, OUTPUT/INPUT, OPEN-COLLECTOR 2 402
4 S
G
D 3
SOT-363 B
11 SYS_PWRSEQ_5 GPUVCORE_SHDN_L 45
R2951
1
0 2 CPU_AVDD_EN 37
5%
1/16W
MF-LF
402
36 =VCORE_PGOOD TP_VCORE_PGOOD
MAKE_BASE=TRUE
ACTIVE-LOW, OUTPUT, PUSH-PULL

11 SYS_PWRSEQ_6_L
26 10 =PP5V_RUN_PWRSEQ
1
R2965
100K
5%
NO STUFF 1/16W
MF-LF
R2969 2 402
0 R2966
45 =GPUVCORE_PGOOD GPUVCORE_PGOOD 1 2
MAKE_BASE=TRUE 1
100K 2
5% SYS_PWRSEQ_6_LS5 GPUVDD15_EN 46
1/16W MAKE_BASE=TRUE
MF-LF 5%
402 1/16W
3
Q2940 D
R2967
0
MF-LF
402 Power Sequencing
1 2 GPUPVDD_EN 51
2N7002DW-X-F
A SOT-363
S G 5
5%
1/16W
MF-LF
SYNC_MASTER=MARIAS

A
402
4
ANALOG INPUT, SENSE > 1.7V
XW2970
SM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
11 SYS_PWRSEQ_FINAL 1 2 PP1V8_GPU_PVDD 51
Used to see if last rail is up
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 29 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
I528 THERM THERM THERM1_M THERM1_M_P 27
I529 THERM THERM THERM1_M THERM1_M_N 27
I530 THERM THERM THERM2_M THERM2_M_P 27
I531 THERM THERM THERM2_M THERM2_M_N 27
I532 THERM THERM THERM1_A THERM1_A_P 27
I533 THERM THERM THERM1_A THERM1_A_N 27
I534 THERM THERM THERM2_A THERM2_A_P 27
THERM THERM THERM2_A THERM2_A_N 27
D
I535
I536 THERM THERM THERM_D1 THERM_D1_P 27

D
I537
I539
THERM
THERM
THERM
THERM
THERM_D1
THERM_D2
THERM_D1_N
THERM_D2_P
27
27
FAN CONTROLLER
I538 THERM THERM THERM_D2 THERM_D2_N 27
R3000
10
10 =PP3V3_ADT7467 PP3V3_ADT7467
VOLTAGE=3.3V 10 =PP5V_RUN_FANPWM 10 =PP3V3_RUN_FANTACH
5% MIN_LINE_WiDTH=0.25 mm
1/16W
MF-LF
402
C3000 C3001MIN_NECK_WIDTH=0.25 mm 1
R3001
1uF 0.1uF 10K
10% 20%
6.3V
CERM
10V
CERM
5%
1/16W R30021 1
R3003 R30041 1
R3005
603 402 MF-LF 10K 10K 10K 10K
2 402 5%
1/16W
5%
1/16W
5%
1/16W
5%
1/16W
MF-LF MF-LF MF-LF MF-LF
402 2 2 402 402 2 2 402
3
PLACE CLOSE TO CPU VCC
MAIN1 U3000
=PPVCORE_CPU_ADT7467 14
QSOP-LFPWM1/15 FAN1_PWM 7 31
10
VCCP CRITICAL XTO
THERM1_M_P 6 FAN1_TACH
ADT7467 TACH1
27 7 31
8 =I2C_ADT7467_SDA 16 SDA
3 8 =I2C_ADT7467_SCL 1 SCL PWM2/ 5 FAN2_PWM 7 31
27 THERM_D1_P SMBALERT#
1 Q3001 R3010 TACH2 7 FAN2_TACH
2N3904LF THERM1_M_P 1
0 2 THERM_D1_P 27
C3002 13 D1+
7 31
27
1000pF 12
2
SOT23
5% 10%
25V
D1- PWM3 8 ADT7467_ADR_ENABLE_L I2C READ ADDR = 0x5C, WRITE ADDR = 0x5D
1/16W (Device is connected so as to be backward
X7R 11
27 THERM1_M_N MF-LF 402 D2+ TACH3 4 NC
R3011 402 27 THERM_D1_N
10 D2-
compatible with the ADT7460.)
C 27 THERM1_M_N 1
0 2 THERM_D1_N 27
27 THERM_D2_P TACH4/ 9
THERM#/ =ADT7467_THERM_L 11
C
PLACE IN BETWEEN 3/5/1.5/2.5V PWR SUPPLY
5%
1/16W
C3003 SMBALERT#/GPIO
MF-LF 1000pF
402
R3012 10% GND
MAIN2 0
25V
X7R 2
27 THERM2_M_P 1 2 THERM_D2_P 27 27 THERM_D2_N 402
27 THERM2_M_P 5%
1/16W
3 R3013 MF-LF
402
THERM2_M_N 1
0 2 THERM_D2_N 27
1 Q3002 27
5%
2N3904LF 1/16W
SOT23 MF-LF
2 402
27 THERM2_M_N
KEEP STUFFING RESISTORS CLOSE TO ADT7467 CONTROLLER

PLACE UNDERNEATH UPPER RAM
ALTERNATE1
27 THERM1_A_P NO STUFF
3 R3020
THERM1_A_P 1
0 2 THERM_D1_P 27
1 Q3003 27
NO STUFF 5%
2N3904LF 1/16W
2
SOT23
R3021 MF-LF
402
THERM1_A_N THERM1_A_N 1
0 2 THERM_D1_N 27
27 27
5%
B 1/16W
MF-LF
402
NO STUFF
R3022
B
PLACE CLOSE TO BATTERY CHARGER/VCORE 27 THERM2_A_P 1
0 2 THERM_D2_P 27
ALTERNATE2 NO STUFF
5%
1/16W
MF-LF
27 THERM2_A_P R3023 402
THERM2_A_N 1
0 2 THERM_D2_N 27
27
3
5%
1/16W
1 Q3004 MF-LF
402
2N3904LF
SOT23
2
27 THERM2_A_N
Fan Controller

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 30 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
10 =PP3V3_PWRON_RT_ALS
RT ALS SENSOR 1 C3100

0.1UF
20%
10V
2 CERM
D
402
D
4 CRITICAL
V+
6 MAX4236EUTT
SOT23-6-LF R3105
1 1
1K 2
R3101 RT_ALS_OUT_FB ALS_1_OUT
1K
U3100 1%
MAKE_BASE=TRUE
25
RT_ALS_PHOTODIODE 1 2 RT_ALS_OP_IN 3 5 1/16W

V- MF-LF
1%
1/16W
2
SHDN_L
402 1 C3105
MF-LF 0.001uF Place cap at PMU!
402 10%
2 50V
CERM
402
1
1
CRITICAL
PD3100
R3100 1 C3101 R3104 GND_PMU_AVSS 25 29 31
5.1M 0.01UF 120K 2
BS520EOF 5% 20%
RT_ALS_OP_COMP 1
TH 1/16W 16V
MF-LF 2 CERM 5%
1/16W
2 402
2
402
R31021 1
R3103 MF-LF
402
15.0K 1K
1%
1/16W
1%
1/16W C3104
MF-LF MF-LF 0.22uF
402 2 2 402 1 2
GAIN_SETTING2 10%
6.3V
CERM-X5R
6 402
D Q3103
2N7002DW-X-F
SOT-363
31 25 7 ALS_GAIN_BOOST 2 G S
MAKE_BASE=TRUE
1
C C
IS TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
TABLE_ALT_ITEM
353S1191 353S1186 U3100 Primary is unity gain stable/Alt is stable at G=5
B Keyboard LED Driver B

L3130
22UH
10 =PP5V_RUN_KEYBRD_LED 1 2 MM3120_SW
3.8X3.8X1.5MM
10 =PP3V3_RUN_KEYBRD_LED
NO STUFF
R31321 1 7
10K VDD SW
5%
1/16W
MF-LF
402 2
U3130
MM3120
LLP
25 SYS_KBDLED 3 CNTRL VOUT 8 KBDLED_ANODE 7 30
NC 6 NC FB 4 KBDLED_RETURN 7 30
R31301 THRML_PAD 9 NC
10K
C3130 1 1
1
C3131 R3131
5% 1UF PGND AGND 25.5
1/16W 10% 0.22uF 1%
6.3V 5 2 10%
MF-LF CERM 2 50V 1/8W
402 2 603 2 CERM MF-LF
1210 2 805
ALS Support

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 31 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
I57 THERM THERM MMM_X_AXIS 25 29
I58 THERM THERM MMM_Y_AXIS 25 29
I59 THERM THERM MMM_Z_AXIS 25 29
D D
C 10 =PP3V3_PWRON_MMM
MMM_ACCEL_KIONIX
C
MMM_ACCEL_KIONIX
C3220 1
0.1uF
R32201 20%
10V
CERM 2
10K 8
402
5% VDD OMIT
1/16W
MF-LF
402 2 U3220
KXM52
QFN
25 MMM_ACC_SELFTEST 10 SELF OUTPUTX 2 MMM_X_AXIS 25 29
MAKE_BASE=TRUE TEST MAKE_BASE=TRUE
25 MMM_ACC_PWRDOWN 9 PS OUTPUTY 13 MMM_Y_AXIS 25 29
NC 5 PARITY OUTPUTZ 14 MMM_Z_AXIS 25 29
MAKE_BASE=TRUE
4 RSVD
6 RSVD DNC 1 NC OMIT OMIT OMIT
Package Top
7 RSVD 1 C3204 1 C3205 1 C3206
11 RSVD 0.1uF 0.1uF 0.1uF
20% 20% 20%
1 THRML 2 10V
CERM 2 10V
CERM 2 10V
CERM
+Y GND PAD 402 402 402
3 12 15
GND_PMU_AVSS 25 28 31
+X
+Z (up)
TABLE_5_HEAD TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
B 338S0222 1 IC,KIONIX,KXM52-2050,3AXIS ACCELEROMETER,SMD U3220 CRITICAL MMM_ACCEL_KIONIX

TABLE_5_ITEM
132S0131 3 CAP,CER,0.033UF,10%,16V,X5R/X7R,0402,SMD C3204,C3205,C3206 MMM_ACCEL_KIONIX

TABLE_5_ITEM
Sudden Motion Sensor


A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 32 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
USB Trackpad Conn

R3353
22
D 10 =PP3V3_ALL_HALL_EFFECT 1
5%
2 7 PP3V3_ALL_HALL_EFFECT_R
VOLTAGE=3.3V
D
MF-LF
402
L3350
400-OHM-EMI
10 =PP5V_TPAD 2 1 7 PP5V_TPAD_F
VOLTAGE=5V
R33551 SM-1 MIN_LINE_WIDTH=0.25 mm
100K
5%
1/16W
MF-LF R3352 CRITICAL
402 2 22
10 =PP3V3_PWRON_DS1775 1
5%
2 7 PP3V3_PWRON_DS1775_R
VOLTAGE=3.3V
J3350
1/16W
MF-LF
402
MIN_NECK_WIDTH=0.10 mm 54550-1494
F-RT-SM
15
L3355
400-OHM-EMI 1
25 SYS_LID_OPEN 2 1 7 SYS_LID_OPEN_F 2
SM-1 3
11 7 USB_TPAD_N 4
11 7 USB_TPAD_P 5
6
28 7 KBDLED_RETURN 7
28 7 KBDLED_ANODE 8
9
8 7 =I2C_DS1775_SCL 10
8 7 =I2C_DS1775_SDA 11
25 11 7 SYS_OVERTEMP_L 12
C 7 SYS_POWER_BUTTON_L_F
13
14
C
L3354
400-OHM-EMI C3355 1 C3350 1 16
57 36 25 24 SYS_POWER_BUTTON_L 2 1 0.001UF 0.001UF
10% 10%
SM-1 50V 50V
CERM 2 CERM 2
402 402
1 C3354 1 C3352 1 C3353

0.001UF 0.001UF 0.001UF
10% 10% 10%
50V 50V 50V
2 CERM 2 CERM 2 CERM
402 402 402
B B
SOFT MODEM CONN
10 =PP3V3_PWRON_MODEM
PLACE NEAR CONNECTOR PINS 1/3 NO STUFF

1
C3320 R3320 R33211
4.7uF CRITICAL 10K 10K
5% 5%
20%
6.3V J3320 1/16W 1/16W
CERM QT500166-L020 MF-LF MF-LF
603 M-ST-SM 2 402 402 2
1 2 MODEM_RING2SYS_L 22 25
3 4 SOFTMODEM_FC_RGDT
6 I2S1_SYNC 5 6
22 I2S1_DEV_TO_SB_DTI 7 8
9 10
11 12
13 14
6
6
I2S1_SB_TO_DEV_DTO
I2S1_BITCLK 15 16
MODEM_RESET_L
I2S1_MCLK
22
6
Q41C Internal I/O I
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 33 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PBUS HOLD-UP CAPS
ADAPTER CONNECTOR 10 =PP24V_PBUSA_HOLDUP_CAPS 10 =PP12V8_PBUSB_HOLDUP_CAPS
D CRITICAL
1
CRITICAL
1
CRITICAL CRITICAL CRITICAL D
CRITICAL C3451 C3453 C3461 1 C3463 1 C3465 1
J3400 22uF 22uF 33UF 33UF 33UF
20% 20% 20% 20% 20%
87438-0832 35V 2
ELEC
35V 2
ELEC
25V 2
ELEC
25V 2
ELEC
25V 2
ELEC
M-RT-SM SM1-LF SM1-LF SM1-LF SM1-LF SM1-LF
1 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
SYS_CHARGE_LED_L 7 24
2 =PP24V_ADAPTER_CONN 10
1
C3450 1
C3452 1
C3454 1
C3460 1
C3462 1
C3464
3
22uF 22uF 22uF 33uF 33UF 33UF
20% 20% 20% 20% 20% 20%
4
1 C3400 2 35V
ELEC
2 35V
ELEC
2 35V
ELEC
2 25V
ELEC
2 25V
ELEC
2 25V
ELEC
0.1UF SM1-LF SM1-LF SM1-LF SM1-LF SM1-LF SM1-LF
5 20%
50V
6 2 CERM
805
7
8 SYS_ADAPTER_ANALOG_AC_DET 7 12
IS TABLE_ALT_HEAD
IS TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER PART NUMBER
C3450,C3451,C3452,C3453,C3454 C3460,C3461,C3462,C3463,C3464,C3465
TABLE_ALT_ITEM TABLE_ALT_ITEM
126S0085 126S0080 Primary is 260C/Alt is 250C part 126S0084 126S0079 Primary is 260C/Alt is 250C part
LEFT USB/LEFT ALS

CRITICAL
J3430
C 54550-1494
F-RT-SM
C
15
1
NC 2
NC 3
10 7 =PP3V3_PWRON_LEFT_ALS 4
5
25 7 ALS_0_OUT MAKE_BASE=TRUE 6
7
C3430
BACKUP BATTERY / RT USB CONNECTOR Place cap at PMU!
1
0.001uF
10%
2 50V
CERM
11 7
11 7
USB2_LEFT_PORT_N
USB2_LEFT_PORT_P
8
9
10
402
29 28 25 GND_PMU_AVSS MAKE_BASE=TRUE 28 25 7 ALS_GAIN_BOOST 11
10 7 =PP5V_PWRON_LEFT_USB 12
13
14
CRITICAL 16
J3410
54550-1494
10 7 =PP5V_PWRON_RIGHT_USB
F-RT-SM
15
1
2
3
B 4
5 CPU FAN GPU FAN B
6 USB2_RIGHT_PORT_N 7 11
7 CRITICAL CRITICAL
USB2_RIGHT_PORT_P 7 11
8 J3450
SM-2MT-LF
J3460
SM-2MT-LF
9
5 5
10 =PPVIO_BU_BATT 7 10
INPUT TO AND OUTPUT
11 NC FROM BATTERY
BACKUP_BATT 10 7 =PP5V_FAN1_PWR 1 10 7 =PP5V_FAN2_PWR 1
12
FAN1_TACH 2 FAN2_TACH 2
13 NC R3410 27 7
3
27 7
3
14 0 27 7 FAN1_PWM 27 7 FAN2_PWM
PPVOUT_BU_BATT 1 2 =PPVOUT_BU_BATT 7 10
4 4
VOLTAGE=5V OUTPUT FROM BATTERY
MIN_LINE_WIDTH=0.38 mm 5%
MIN_NECK_WIDTH=0.25 mm 1/4W
16 MF-LF
1206 6 6
SUPERCAP
R3411
1
0 2 =PP5V_SUPERCAP 14
OUTPUT FROM BATTERY
5%
1/4W
MF-LF
1206
Q41C Internal I/O II

A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 34 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
OMIT
ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL DIFFERENTIAL_PAIR MaxBus Pull-ups / Pull-downs
MAXBUS_CLK_CPU0_R
U2100
MAXBUS_CLK_CPU0 CLOCK CLOCK 11 32
I2
MAXBUS_CLK_CPU1 CLOCK CLOCK TP_MAXBUS_CLK_CPU1_R 11 32
BGA
I2_MAXBUS_FBCLK I2_FBCLK I2_FBCLK I2_MAXBUS_FBCLK_OUT_R 32 PROCESSOR INTERFACE =PP1V5R1V8_MAXBUS
34 33 21 10
I2_FBCLK I2_FBCLK I2_MAXBUS_FBCLK_OUT 21 32 (5 of 14)
MAXBUS_CPUS_BIDIR MAXBUS MAXBUS MAXBUS_ADDR<0..31> 9 32 33 PROCESSOR 0 RP3510

10K
MAXBUS_DATA<0..40> MAXBUS_CPU0_QREQ_L E25 F18 MAXBUS_CPU0_QACK_L =RP3510P1 1 8
MAXBUS_CPUS_BIDIR MAXBUS MAXBUS 9 32 33 33 32 MAX_QREQ_0_L MAX_QACK_0_L 33 6
MAXBUS_DATA<41> MAXBUS_CPU0_BR_L F21 E22 MAXBUS_CPU0_BG_L

MAXBUS_DATA41 MAXBUS MAXBUS 9 21 32 33 33 32 6 MAX_BR_0_L MAX_BG_0_L 6 32 33 5%
MAXBUS_DATA42 MAXBUS MAXBUS MAXBUS_DATA<42> 9 21 32 33 33 32 6 MAXBUS_CPU0_DRDY_L G25

MAX_DRDY_0_L MAX_DBG_0_L F24 MAXBUS_CPU0_DBG_L 6 32 33
1/16W
SM-LF
RP3510
10K
D MAXBUS_DATA43
MAXBUS_DATA44
MAXBUS
MAXBUS
MAXBUS
MAXBUS
MAXBUS_DATA<43>
MAXBUS_DATA<44>
9 21 32 33
9 21 32 33
33 32 6 MAXBUS_CPU0_HIT_L E21
MAX_HIT_0_L CPU_INT_0_L
MAX_CLK_0_H
J19
H21
MAXBUS_CPU0_INT_L
MAXBUS_CLK_CPU0_R
6 34
11 32
6 =RP3510P2 2
5%
7
D
MAXBUS_CPUS_BIDIR MAXBUS MAXBUS MAXBUS_DATA<45..53> 9 32 33
One resistor for each of: RP3510 1/16W
SM-LF
PROCESSOR 1 - MAXBUS_TS_L 10K
MAXBUS_DATA<54> =RP3510P3 3 6
MAXBUS_DATA54 MAXBUS MAXBUS 9 21 32 33
E27 G18 6
32 MAXBUS_CPU1_QREQ_L MAX_QREQ_1_L MAX_QACK_1_L TP_MAXBUS_CPU1_QACK_L 11 - MAXBUS_TA_L
MAXBUS_CPUS_BIDIR MAXBUS MAXBUS MAXBUS_DATA<55..61> 9 32 33 G21 E24 5%
32 6 MAXBUS_CPU1_BR_L MAX_BR_1_L MAX_BG_1_L MAXBUS_CPU1_BG_L 6 32 - MAXBUS_TEA_L 1/16W RP3510
MAXBUS_DATA62 MAXBUS MAXBUS MAXBUS_DATA<62> 9 21 32 33 SM-LF
32 6 MAXBUS_CPU1_DRDY_L F25
MAX_DRDY_1_L MAX_DBG_1_L G24 MAXBUS_CPU1_DBG_L 6 32 - MAXBUS_ARTRY_L 10K
MAXBUS_CPUS_BIDIR MAXBUS MAXBUS MAXBUS_DATA<63> 9 32 33 =RP3510P4 4 5
C21 6
MAXBUS_CPU1_HIT_L H19 MAXBUS_CPU1_INT_L
32 6 MAX_HIT_1_L CPU_INT_1_L 6 - MAXBUS_AACK_L
J21 5%
MAXBUS_CPUS_BIDIR_R MAXBUS MAXBUS MAXBUS_TS_L 6 32 33 MAX_CLK_1_H TP_MAXBUS_CLK_CPU1_R 11 32 - (Spare) RP3511 1/16W
SM-LF
MAXBUS_NB_TO_CPUS_R MAXBUS MAXBUS MAXBUS_TA_L 6 32 33 10K
MAXBUS_TEA_L
MAXBUS INTERFACE 6 =RP3511P1 1 8
MAXBUS_NB_TO_CPUS_R MAXBUS MAXBUS 6 32 33
B27 A31
33 32 6 MAXBUS_TS_L MAX_TS_L MAX_AACK_L MAXBUS_AACK_L 6 32 33 5%
MAXBUS_NB_TO_CPUS_R MAXBUS MAXBUS MAXBUS_AACK_L 6 32 33 C30 1/16W RP3511
33 32 6 MAXBUS_ARTRY_L MAX_ARTRY_L SM-LF
MAXBUS_CPUS_BIDIR_R MAXBUS MAXBUS MAXBUS_ARTRY_L 6 32 33
10K
D16 MAXBUS_DATA<0> =RP3511P2 2 7
MAX_D_00_H 9 32 33 6
MAXBUS_CPUS_TO_NBIO MAXBUS MAXBUS MAXBUS_CI_L 9 32 33
D18 A10
33 32 9 MAXBUS_ADDR<0> MAX_A_00_H MAX_D_01_H MAXBUS_DATA<1> 9 32 33 5%
MAXBUS_DTI MAXBUS MAXBUS MAXBUS_DTI<0..2> 9 32 33
A28 A9 1/16W
33 32 9 MAXBUS_ADDR<1> MAX_A_01_H MAX_D_02_H MAXBUS_DATA<2> 9 32 33 SM-LF
MAXBUS_GBL_L MAXBUS MAXBUS MAXBUS_GBL_L 9 32 33 A19 D12
33 32 9 MAXBUS_ADDR<2> MAX_A_02_H MAX_D_03_H MAXBUS_DATA<3> 9 32 33
MAXBUS_CPUS_TO_NBIO MAXBUS MAXBUS MAXBUS_TBST_L 9 32 33
A23 A11
MAXBUS_TSIZ<0..2>
33 32 9 MAXBUS_ADDR<3> MAX_A_03_H MAX_D_04_H MAXBUS_DATA<4> 9 32 33 I2 CPU0 Support
MAXBUS_CPUS_TO_NBIO MAXBUS MAXBUS 9 32 33
D21 B10
MAXBUS_CPUS_BIDIR MAXBUS MAXBUS MAXBUS_TT<0..4> 9 32 33 A25 C10
MAXBUS_WT_L MAXBUS MAXBUS MAXBUS_WT_L 9 32 33
A18 G16 RP3511
10K
MAXBUS_CPU0_BG_L MAXBUS_ADDR<7> C28 D9 MAXBUS_DATA<8> =RP3511P3 3 6
MAXBUS_NB_TO_CPU0_R MAXBUS MAXBUS 6 32 33 33 32 9 MAX_A_07_H MAX_D_08_H 9 32 33 6
MAXBUS_CPU0_BR_L MAXBUS_ADDR<8> D25 C9 MAXBUS_DATA<9>

MAXBUS_CPU0_TO_NB_R MAXBUS MAXBUS 6 32 33 33 32 9 MAX_A_08_H MAX_D_09_H 9 32 33 5%
MAXBUS_NB_TO_CPU0_R MAXBUS MAXBUS MAXBUS_CPU0_DBG_L 6 32 33 33 32 9 MAXBUS_ADDR<9> B31
MAX_A_09_H MAX_D_10_H F15 MAXBUS_DATA<10> 9 32 33
1/16W RP3511
SM-LF 10K
MAXBUS_CPU0_DRDY_L MAXBUS_ADDR<10> B24 G15 MAXBUS_DATA<11> =RP3511P4 4 5
MAXBUS_CPU0_DRDY_L MAXBUS MAXBUS 6 32 33 33 32 9 MAX_A_10_H MAX_D_11_H 9 32 33 6
MAXBUS_CPU0_HIT_L MAXBUS_ADDR<11> G28 B9 MAXBUS_DATA<12>

MAXBUS_CPU0_TO_NB_R MAXBUS MAXBUS 6 32 33 33 32 9 MAX_A_11_H MAX_D_12_H 9 32 33 5%
33 32 9 MAXBUS_ADDR<12> C25
MAX_A_12_H MAX_D_13_H D10 MAXBUS_DATA<13> 9 32 33
SM-LF
MAXBUS_NB_TO_CPU1_R MAXBUS MAXBUS MAXBUS_CPU1_BG_L 6 32 - MAXBUS_CPU0_BR_L 10K
MAXBUS_ADDR<13> D31 E15 MAXBUS_DATA<14> =RP3512P1 1 8
33 32 9 MAX_A_13_H MAX_D_14_H 9 32 33 6
C MAXBUS_CPU1_TO_NB_R
MAXBUS_NB_TO_CPU1_R
MAXBUS
MAXBUS
MAXBUS
MAXBUS
MAXBUS_CPU1_BR_L
MAXBUS_CPU1_DBG_L
6 32
6 32
33 32 9
33 32 9
MAXBUS_ADDR<14>
MAXBUS_ADDR<15>
F19
E30
MAX_A_14_H
MAX_A_15_H
MAX_D_15_H
MAX_D_16_H
C7
B7
MAXBUS_DATA<15>
MAXBUS_DATA<16>
9 32 33
9 32 33
- MAXBUS_CPU0_BG_L
- MAXBUS_CPU0_DBG_L
5%
1/16W RP3512
C
SM-LF 10K
MAXBUS_CPU1_DRDY_L MAXBUS MAXBUS MAXBUS_CPU1_DRDY_L 6 32 D27 A8 - MAXBUS_CPU0_DRDY_L 2 7
33 32 9 MAXBUS_ADDR<16> MAX_A_16_H MAX_D_17_H MAXBUS_DATA<17> 9 32 33 6 =RP3512P2
MAXBUS_CPU1_TO_NB_R MAXBUS MAXBUS MAXBUS_CPU1_HIT_L 6 32
A27 F16 - MAXBUS_CPU0_HIT_L
33 32 9 MAXBUS_ADDR<18> B28
MAX_A_18_H MAX_D_19_H G13 MAXBUS_DATA<19> 9 32 33
- MAXBUS_CPU0_INT_L RP3512 1/16W
SM-LF
10K
Page Notes 33 32 9
33 32 9
MAXBUS_ADDR<19>
MAXBUS_ADDR<20>
B25
E19
MAX_A_19_H
MAX_A_20_H
MAX_D_20_H
MAX_D_21_H
E13
E12
MAXBUS_DATA<20>
MAXBUS_DATA<21>
9 32 33
9 32 33
6 =RP3512P3 3
5%
6
Power aliases required by this page: Signal aliases required by this page: 33 32 9 MAXBUS_ADDR<21> G27
MAX_A_21_H MAX_D_22_H D7 MAXBUS_DATA<22> 9 32 33
1/16W
SM-LF
RP3512
10K
MAXBUS_ADDR<22> D30 A7 MAXBUS_DATA<23> =RP3512P4 4 5
- =PP1V5R1V8_RUN_I2_MAXBUS - =PP1V5R1V8_PWRON_I2_MAXBUS - =I2_MAXBUS_FBCLK_IN - MaxBus feedback 33 32 9 MAX_A_22_H MAX_D_23_H 9 32 33 6
MAXBUS_ADDR<23> C31 G12 MAXBUS_DATA<24>

clock input. Length should match that 33 32 9 MAX_A_23_H MAX_D_24_H 9 32 33 5%
of clock(s) from I2 to CPU(s). 33 32 9 MAXBUS_ADDR<24> F28
MAX_A_24_H MAX_D_25_H F12 MAXBUS_DATA<25> 9 32 33
R3513 1/16W
SM-LF
- MAXBUS_1V8 - Provides required voltage
MAXBUS_ADDR<25> F27 F13 1
10K 2
33 32 9 MAX_A_25_H MAX_D_26_H MAXBUS_DATA<26> 9 32 33 33 32 MAXBUS_CPU0_QREQ_L
divider for FBCLK if MaxBus OVdd=1.8V. B30 A6
E28 E10
1/16W
33 32 9 MAXBUS_ADDR<27> MAX_A_27_H MAX_D_28_H MAXBUS_DATA<28> 9 32 33 MF-LF
PP1V5R1V8_I2_MAXBUS B18 B6
402
VOLTAGE=1.5V 33 32 9 MAXBUS_ADDR<28> MAX_A_28_H MAX_D_29_H MAXBUS_DATA<29> 9 32 33
MAXBUS_ADDR<29> C22 C6 MAXBUS_DATA<30> I2 CPU1 Support
OMIT
MaxBus I/O DECOUPLING MIN_NECK_WIDTH=0.25 mm 33 32 9
33 32 9 MAXBUS_ADDR<30> A17
MAX_A_29_H
MAX_A_30_H
MAX_D_30_H
MAX_D_31_H D6 MAXBUS_DATA<31>
9 32 33
9 32 33
1 X 10uF (0603)
(41 Balls on I2) 33 32 9 MAXBUS_ADDR<31> B19
MAX_A_31_H MAX_D_32_H G7 MAXBUS_DATA<32> 9 32 33
U2100 41 X 1uF (0402) A3 MAXBUS_DATA<33> RP3513
MAX_D_33_H 9 32 33
10K
I2 A26 E6 2 7
33 32 9 MAXBUS_CI_L MAX_CI_L MAX_D_34_H MAXBUS_DATA<34> 9 32 33 6 =RP3513P2
BGA A24 F7
C3550 1 C3551 1 C3552 1 C3553 1 C3554 1 C3555 1 1 C3599 33 32 9 MAXBUS_GBL_L MAX_GBL_L MAX_D_35_H MAXBUS_DATA<35> 9 32 33 5%
MAXBUS POWER 1uF 1uF 1uF 1uF 1uF 1uF 10uF MAXBUS_TBST_L E16 C4 MAXBUS_DATA<36>
1/16W RP3513
10% 10% 10% 10% 10% 10% 20%
33 32 9 MAX_TBST_L MAX_D_36_H 9 32 33 SM-LF
10K
(6 of 14) 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V D19 D3 3 6
C11 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 2 X5R 33 32 9 MAXBUS_TSIZ<0> MAX_TSIZ_0_H MAX_D_37_H MAXBUS_DATA<37> 9 32 33 6 =RP3513P3
VDD18_0 402 402 402 402 402 402 603 C18 G9
C14 33 32 9 MAXBUS_TSIZ<1> MAX_TSIZ_1_H MAX_D_38_H MAXBUS_DATA<38> 9 32 33 5%
VDD18_1
MAXBUS_TSIZ<2> B21
MAX_TSIZ_2_H MAX_D_39_H D4 MAXBUS_DATA<39>
33 32 9 9 32 33 SM-LF
VDD18_2 C17
- MAXBUS_CPU1_BR_L 10K
MAXBUS_TT<0> B22 B16 MAXBUS_DATA<40> =RP3513P4 4 5
C20 33 32 9 MAX_TT_0_H MAX_D_40_H 9 32 33 6
VDD18_3 - MAXBUS_CPU1_BG_L
B VDD18_4 C23
C26
C3556
1uF
1
C3557
1uF
1
C3558
1uF
1
C3559
1uF
1
C3560
1uF
1
C3561
1uF
1
33 32 9
33 32 9
MAXBUS_TT<1>
MAXBUS_TT<2>
D22
E18
MAX_TT_1_H
MAX_TT_2_H
MAX_D_41_H
MAX_D_42_H
C16
A13
MAXBUS_DATA<41>
MAXBUS_DATA<42>
9 21 32 33
9 21 32 33
- MAXBUS_CPU1_DBG_L
5%
1/16W
SM-LF
RP3514
10K
B
VDD18_5 10% 10% 10% 10% 10% 10% A21 A16 - MAXBUS_CPU1_DRDY_L 1 8
C29 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 33 32 9 MAXBUS_TT<3> MAX_TT_3_H MAX_D_43_H MAXBUS_DATA<43> 9 21 32 33 6 =RP3514P1
VDD18_6 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 A22 C13 - MAXBUS_CPU1_HIT_L
C3 402 402 402 402 402 402 33 32 9 MAXBUS_TT<4> MAX_TT_4_H MAX_D_44_H MAXBUS_DATA<44> 9 21 32 33 5%
VDD18_7
MAXBUS_WT_L D24
MAX_WT_L MAX_D_45_H B15 MAXBUS_DATA<45>
- MAXBUS_CPU1_INT_L RP3514 1/16W
C32 33 32 9 9 32 33
10K SM-LF
VDD18_8 D15 2 7
C8 MAX_D_46_H MAXBUS_DATA<46> 9 32 33 6 =RP3514P2
VDD18_9 B12
F11 MAX_D_47_H MAXBUS_DATA<47> 9 32 33 5%
VDD18_10
C3562 1
C3563 1
C3564 1
C3565 1
C3566 1
C3567 1 R3550 MAX_D_48_H A14 MAXBUS_DATA<48> 9 32 33
1/16W
SM-LF
RP3514
10K
VDD18_11 F14
1uF 1uF 1uF 1uF 1uF 1uF 0 A12 3 6
F17 10% 10% 10% 10% 10% 10%
1 2 =PP1V5R1V8_RUN_I2_MAXBUS 10 MAX_D_49_H MAXBUS_DATA<49> 9 32 33 6 =RP3514P3
VDD18_12 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V D13
F20 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 5% MAX_D_50_H MAXBUS_DATA<50> 9 32 33 5%
VDD18_13 402 402 402 402 402 402
1/10W
MF-LF MAX_D_51_H B13 MAXBUS_DATA<51> 9 32 33
R3514 1/16W
SM-LF
VDD18_14 F23 603
A15
10K
F26 MAX_D_52_H MAXBUS_DATA<52> 9 32 33 32 MAXBUS_CPU1_QREQ_L 1 2
VDD18_15 NO STUFF C15
F29 MAX_D_53_H MAXBUS_DATA<53> 9 32 33 5%
VDD18_16 R3551 MAX_D_54_H C5 MAXBUS_DATA<54> 9 21 32 33
1/16W
MF-LF
VDD18_17 F8
C3568 1
C3569 1
C3570 1
C3571 1
C3572 1
C3573 1 0 C12
402
J11 1uF 1uF 1uF 1uF 1uF 1uF
1 2 =PP1V5R1V8_PWRON_I2_MAXBUS 10 MAX_D_55_H MAXBUS_DATA<55> 9 32 33
VDD18_18 10% 10% 10% 10% 10% 10% F6
J12 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
5% MAX_D_56_H MAXBUS_DATA<56> 9 32 33
VDD18_19 2 2 2 2 2 2 1/10W
CERM CERM CERM CERM CERM CERM MF-LF A5 MAXBUS_DATA<57>
J14 402 402 402 402 402 402 MAX_D_57_H 9 32 33
VDD18_20 603 F9
J15 K9 MAX_D_58_H MAXBUS_DATA<58> 9 32 33
VDD18_21 I2_ACS_REF ACS_REF_H E9
J17 MAX_D_59_H MAXBUS_DATA<59> 9 32 33
VDD18_22 E7
J18 1 MAX_D_60_H MAXBUS_DATA<60> 9 32 33
VDD18_23 R3500 G10
J20 C3574 1 C3575 1 C3576 1 C3577 1 C3578 1 C3579 1 MAX_D_61_H MAXBUS_DATA<61> 9 32 33
VDD18_24 1uF 1uF 1uF 1uF 1uF 1uF 1K B4
J23 10% 10% 10% 10% 10% 10%
1% MAX_D_62_H MAXBUS_DATA<62> 9 21 32 33
VDD18_25 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 1/16W F10
J24 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 MF-LF MAX_D_63_H MAXBUS_DATA<63> 9 32 33
VDD18_26 402 402 402 402 402 402 2
402
J26
VDD18_27
VDD18_28 J27 MAX_DTI_0_H C27 MAXBUS_DTI<0> 9 32 33 I2 Processor Interface
A30 MAXBUS_DTI<1>
L14 MAX_DTI_1_H 9 32 33
A VDD18_29
VDD18_30 L17
C3580 1 C3581 1 C3582 1 C3583 1 C3584 1 C3585 1 MAX_DTI_2_H A29 MAXBUS_DTI<2> 9 32 33
SYNC_MASTER=MARIAS

A
VDD18_31 L23 1uF 1uF 1uF 1uF 1uF 1uF
10% 10% 10% 10% 10% 10% G19 MAXBUS_TA_L
M20 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V MAX_TA_L 6 32 33
VDD18_32 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 D28 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
N15 402 402 402 402 402 402 MAX_TEA_L MAXBUS_TEA_L 6 32 33 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
VDD18_33 21 =I2_MAXBUS_FBCLK_IN AGREES TO THE FOLLOWING
N19
VDD18_34 MAXBUS_1V8 C24 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
N21 MAX_TBEN_H TP_MAXBUS_TBEN_I2
VDD18_35 R3506 1 1.5V IN R3505 II NOT TO REPRODUCE OR COPY IT
N22 360 10
VDD18_36 H22 J22 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
P14 C3586 1
C3587 1
C3588 1
C3589 1
C3590 1
5% MAX_CLK_FB_IN_H MAX_FBCLK_OUT_H 32 I2_MAXBUS_FBCLK_OUT_R 1 2 I2_MAXBUS_FBCLK_OUT 21 32
VDD18_37 1uF 1uF 1uF 1uF 1uF 1/16W
MF-LF 5% SIZE DRAWING NUMBER REV.
P15 10% 10% 10% 10% 10%
VDD18_38 402 2 1/16W
051-6839 F
6.3V 6.3V 6.3V 6.3V 6.3V
VDD18_39 P18
P22
CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
2 1.5V-1.8V OUT (Matches MaxBus OVdd)
Output impedance is 50 Ohms
MF-LF
402
APPLE COMPUTER INC.
D
VDD18_40
SCALE SHT OF
NONE 35 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL DIFFERENTIAL_PAIR T3

32 9 MAXBUS_DATA<0> R15 D0 DP0 NC
W4
CLOCK CLOCK =MAXBUS_CPU0_CLK 11 33 32 9 MAXBUS_DATA<1> W15
D1 DP1 NC
I1020
U3600 T4
32 9 MAXBUS_DATA<2> T14 D2 DP2 NC
W9
32 9 MAXBUS_DATA<3> V16
D3 BGA DP3 NC
MAXBUS_DATA<4> W16
D4 (2 OF 6) DP4 M6
Page Notes 32 9 NC
XXGHZ-XXV
A8-X.X
V3
32 9 MAXBUS_DATA<5> T15 D5 DP5 NC
N8
Power aliases required by this page: 32 9 MAXBUS_DATA<6> U15
D6 DP6 NC
W6
- =PP1V5R1V8_MAXBUS 32 9 MAXBUS_DATA<7> P14
D7 DP7 NC
PLACE RC GLITCH FILTER
D8 M2 R3600
MAXBUS_DATA<9> W13
DBG* MAXBUS_CPU0_DBG_L 6 32 CLOSE TO CPU PIN
32 9 D9 0
D - =MAXBUS_CPU0_CLK
32 9 MAXBUS_DATA<10> T13 D10
DRDY*
DTI0
R3
G1
MAXBUS_CPU0_DRDY_L_R
MAXBUS_EDTI 33
1
5%
2 MAXBUS_CPU0_DRDY_L 6 32
D
BOM options provided by this page: 32 9 MAXBUS_DATA<11> P13 D11 K1
1/16W
1
MAXBUS_DATA<12> U14
DTI1 MAXBUS_DTI<0> 9 32 MF-LF C3600
(NONE) 32 9 D12 DTI2 P1 MAXBUS_DTI<1> 9 32
402
10PF
MAXBUS_DATA<13> 5%
32 9 W14 D13 N1 50V
MAXBUS_DATA<14>
DTI3 MAXBUS_DTI<2> 9 32 2 CERM
32 9 R12 D14 402
K6
32 9 MAXBUS_DATA<15> T12
D15 OMIT TA* MAXBUS_TA_L 6 32
L1
32 9 MAXBUS_DATA<16> W12 D16 CRITICAL TEA* MAXBUS_TEA_L 6 32
D17 B2
MAXBUS_DATA<18>
HIT* MAXBUS_CPU0_HIT_L 6 32
32 9 N11 D18
32 9 MAXBUS_DATA<19> N10 D19
32 9 MAXBUS_DATA<20> R11
D20 U3600
32 9 MAXBUS_DATA<21> U11 D21 C1
MAXBUS_DATA<22>
32 6 MAXBUS_CPU0_BR_L D2
BR* BGA AP0 NC
32 9 W11 D22 M1 (1 OF 6) E3
MAXBUS_DATA<23> T11
32 6 MAXBUS_CPU0_BG_L BG* AP1 NC
D23
XXGHZ-XXV
A8-X.X
32 9
H6
MAXBUS_DATA<24>
AP2 NC
32 9 R10 D24 F5
MAXBUS_DATA<25>
32 6 MAXBUS_TS_L L4
TS* AP3 NC
32 9 N9 D25 R3601 G7
MAXBUS_DATA<26> P10 470
AP4 NC
32 9 D26 CPU0_PULLDOWN E11
MAXBUS_DATA<27>
1 2 A0
32 9 U10 D27 E5
MAXBUS_DATA<28> R9
5% H1
A1 TT0 MAXBUS_TT<0> 9 32
32 9 D28 1/16W
C11 TT1 E6 MAXBUS_TT<1>
MAXBUS_DATA<29>
MF-LF A2 9 32
32 9 W10 D29 402
F6
34 33 32 21 10 =PP1V5R1V8_MAXBUS
MAXBUS_DATA<30>
G3
32 9 U9 D30 E9
MAXBUS_DATA<31> V9
32 9 MAXBUS_ADDR<0> F10
32 9 D31 MAXBUS_ADDR<1> L2 TT4 C5 MAXBUS_TT<4>
MAXBUS_DATA<32>
32 9 A5 9 32
32 9 W5 D32 F11
MAXBUS_DATA<33>
32 9 MAXBUS_ADDR<2> D11
A6 OMIT TBST* MAXBUS_TBST_L 9 32
32 9 U6 D33 D1 G6
MAXBUS_DATA<34> T5
32 9 MAXBUS_ADDR<3> A7 CRITICAL TSIZ0 MAXBUS_TSIZ<0> 9 32
32 9 D34 MAXBUS_ADDR<4> C10 TSIZ1 F7 MAXBUS_TSIZ<1>
MAXBUS_DATA<35>
32 9 A8 9 32
32 9 U5 D35 E7
B4
U3600
P11 32 9 MAXBUS_ADDR<5> G2
A9 TSIZ2 MAXBUS_TSIZ<2> 9 32
C C2
C12
BGA
R4
R13
32 9
32 9
MAXBUS_DATA<36>
MAXBUS_DATA<37>
W7
R6
D36
D37
32 9 MAXBUS_ADDR<6>
MAXBUS_ADDR<7>
D12
L3
A10 GBL*
WT*
E2
D3
MAXBUS_GBL_L
MAXBUS_WT_L
9 32 C
(5 OF 6) MAXBUS_DATA<38>
32 9 A11 9 32
P7 D38
XXGHZ-XXV
A8-X.X
32 9 J1
D5 R16
MAXBUS_DATA<39> V6
32 9 MAXBUS_ADDR<8> G4
A12 CI* MAXBUS_CI_L 9 32
F2 T6
32 9 D39 MAXBUS_ADDR<9> T2 AACK* R1 MAXBUS_AACK_L
MAXBUS_DATA<40>
32 9 A13 6 32
32 9 P17 D40 N2
H3
OVDD OVDD
T9
MAXBUS_DATA<41>
32 9 MAXBUS_ADDR<10> F4
A14 ARTRY* MAXBUS_ARTRY_L 6 32
32 21 9 R19 D41 E4
J5 U2
MAXBUS_DATA<42> V18
32 9 MAXBUS_ADDR<11> V1
A15 SHD0* MAXBUS_SHD0_L 33
K2 U12 32 21 9 D42 MAXBUS_ADDR<12> J4
SHD1* H5 MAXBUS_SHD1_L
MAXBUS_DATA<43>
32 9 A16 33
L5 U16
32 21 9 R18 D43 MAXBUS_ADDR<13> R2 A10 =MAXBUS_CPU0_CLK
MAXBUS_DATA<44>
32 9 A17 SYSCLK 11 33
M3 V4
32 21 9 V19 D44 MAXBUS_ADDR<14> K5 H2 TP_CPU0_CLKOUT
MAXBUS_DATA<45> T19
32 9 A18 CLK_OUT ADD GND TP NEAR CLKOUT TP
N6 V7
32 9 D45 MAXBUS_ADDR<15> W2 E1 MAXBUS_TBEN
MAXBUS_DATA<46>
32 9 A19 TBEN 21
P2 V10
32 9 U19 D46 MAXBUS_ADDR<16> J2 P4 MAXBUS_CPU0_QREQ_L
MAXBUS_DATA<47>
32 9 A20 QREQ* 32
P8
OMIT V14
32 9 W19 D47 MAXBUS_ADDR<17> K4 G5 MAXBUS_CPU0_QACK_L
MAXBUS_DATA<48> U18
32 9 A21 QACK* 32
CRITICAL 32 9 D48 MAXBUS_ADDR<18> N4 A3
TP_CPU0_OVDDSENSE1 E18 MAXBUS_DATA<49>
32 9 A22 CKSTP_IN*
OVDDSENSE1 32 9 W17 D49 MAXBUS_ADDR<19> J3 B1 CPU_CHKSTP_OUT_L
TP_CPU0_OVDDSENSE2 G18 MAXBUS_DATA<50> W18
32 9 A23 CKSTP_OUT* 34
OVDDSENSE2 32 9 D50 MAXBUS_ADDR<20> M5
MAXBUS_DATA<51>
32 9 A24
(Kelvin sense points) 32 9 T16 D51 MAXBUS_ADDR<21> P5
MAXBUS_DATA<52>
32 9 A25
32 9 T18 D52 MAXBUS_ADDR<22> N3
MAXBUS_DATA<53> T17
32 9 A26
32 9 D53 MAXBUS_ADDR<23> T1
MAXBUS_DATA<54>
32 9 A27
32 21 9 W3 D54 MAXBUS_ADDR<24> V2
MAXBUS_DATA<55>
32 9 A28
32 9 V17 D55 MAXBUS_ADDR<25> U1
MAXBUS_DATA<56> U4
32 9 A29
32 9 D56 MAXBUS_ADDR<26> N5
MAXBUS_DATA<57>
32 9 A30
32 9 U8
D57 MAXBUS_ADDR<27> W1
MAXBUS_DATA<58>
32 9 A31
32 9 U7
D58 MAXBUS_ADDR<28> B12
MAXBUS_DATA<59> R7
32 9 A32
32 9 D59 MAXBUS_ADDR<29> C4
MAXBUS_DATA<60>
32 9 A33
32 9 P6
D60 MAXBUS_ADDR<30> G10
MAXBUS_DATA<61> R8
32 9 A34
32 9 D61 MAXBUS_ADDR<31> B11
MAXBUS_DATA<62>
32 9 A35
32 21 9 W8
D62
B 32 9 MAXBUS_DATA<63> T8 D63 B
=PP1V5R1V8_MAXBUS 10 21 32 33 34
26 X 1UF (0402)
VIO DECOUPLING (28 PINS) 2 X 10UF (0603)
1
C3670 1
C3671 1
C3672 1
C3673 1
C3674 1
C3675 1
C3676 1
C3677 1
C3678 1
C3679
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402
MAXBUS Straps
1 1 1 1 1 1 1 1 1 1
C3680 C3681 C3682 C3683 C3684 C3685 C3686 C3687 C3688 C3689
1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF 34 33 32 21 10 =PP1V5R1V8_MAXBUS
10% 10% 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402 402 402 402 402 402
R3610 A8 MaxBus (CPU0)

10K
33 MAXBUS_SHD0_L 1 2
1
C3690 1
C3691 1
C3692 1
C3693 1
C3694 1
C3695
A 1uF
10%
1uF
10%
1uF
10%
1uF
10%
1uF
10%
1uF
10%
5%
1/16W
MF-LF R3611
SYNC_MASTER=MARIAS

A
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 10K
402 402 402 402 402 402 33 MAXBUS_SHD1_L 1 2
MF-LF
402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1
C3698 1
C3699 II NOT TO REPRODUCE OR COPY IT
10uF 10uF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
20% 20% R3620
4V 4V
2 X5R 2 X5R
1K
603 603 33 MAXBUS_EDTI 1 2 SIZE DRAWING NUMBER REV.
1%
1/16W
MF-LF
402 APPLE COMPUTER INC.
D 051-6839 F
SCALE SHT OF
NONE 36 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
A7PM
CPU0 PLL CONFIG CIRCUITRY
- =PP1V5R1V8_MAXBUS U3600
34 CPU_BVSEL<0> B7 BVSEL0 BVSEL INT* D4 MAXBUS_CPU0_INT_L 6 32
- =PP3V3_PWRON_PLLSEL BGA
SMI* F9 CPU0_SMI_L 34
34 CPU0_PLL_CFG<0> B8 PLL_CFG0 (3 OF 6) 34 33 32 21 10 =PP1V5R1V8_MAXBUS
Signal aliases required by this page: MCP* C9 CPU_MCP_L
A8-X.X
XXGHZ-XXV
34
34 CPU0_PLL_CFG<1> C8 PLL_CFG1 CPU0_PLL0_1 CPU0_PLL1_1 CPU0_PLL2_1 CPU0_PLL3_1 CPU0_PLL4_1 CPU0_PLL5_1
- =CPU0_JTAG_TDI SRESET* A2 CPU0_SRESET_L 34
1 1 1 1 1
34 CPU0_PLL_CFG<2> C7 PLL_CFG2 R3720 R3722 R3724 R3726 R3728
1
R3730
- =CPU0_JTAG_TDO HRESET* D8 =CPU_HRESET_L 11 34
34 CPU0_PLL_CFG<3> D7 PLL_CFG3 10K 10K 10K 10K 10K 10K
- =CPU0_JTAG_TMS 5% 5% 5% 5% 5% 5%
34 CPU0_PLL_CFG<4> A7 PLL_CFG4 CFGEXT PMON_IN* D9 CPU_PMON_IN_L 34 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
- =CPU0_JTAG_TCK MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
A7PM PMON_OUT* A9 TP_CPU0_PMON_OUT_L 2
402
2
402
2
402
2
402
2
402
2
402
- =CPU0_JTAG_TRST_L 9 =JTAG_CPU0_TDI B9 TDI
- =CPU_HRESET_L (Reset given to all processors) 9 =JTAG_CPU0_TDO A4 TDO BMODE0* G9 CPU0_BMODE0_L 34 CPU0_PLL_CFG<0> 34
D BOM options provided by this page:

9 =JTAG_CPU0_TMS F1 TMS OMIT BMODE1* F8 CPU0_BMODE1_L 34 CPU0_PLL_CFG<1> 34 D
9 =JTAG_CPU0_TCK C6 TCK CPU0_PLL_CFG<2> 34
- CPU0_PLL0_0/1 CRITICAL EXT_QUAL A11 CPU0_EXT_QUAL 34
9 =JTAG_CPU0_TRST_L A5 TRST* CPU0_PLL_CFG<3> 34
- CPU0_PLL1_0/1
34 CPU_LSSD_MODE_L E8 LSSD_MODE* CPU0_PLL_CFG<4> 34
- CPU0_PLL2_0/1 TEST0 DFS2* A12 CPU0_DFS2_L 34
34 CPU0_L1TSTCLK G8 L1_TSTCLK CPU0_PLL_CFG<5> 34
- CPU0_PLL3_0/1 TEST2 LVRAM* B10 CPU0_LVRAM_L 34
34 CPU0_L2TSTCLK B3 L2_TSTCLK CPU0_PLL0_0 CPU0_PLL1_0 CPU0_PLL2_0 CPU0_PLL3_0 CPU0_PLL4_0 CPU0_PLL5_0
- CPU0_PLL4_0/1 A7PM TEST3 BVSEL1 E10 CPU_BVSEL<1> 34
1 1 1 1 1 1
- CPU0_PLL5_0/1 TEST1 DFS4* B6 CPU0_DFS4_L 34
R3721 R3723 R3725 R3727 R3729 R3731
10K 10K 10K 10K 10K 10K
These must be selected to set the CPU core to Maxbus TEST4 PLL_CFG5 D10 CPU0_PLL_CFG<5> 34 5% 5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
frequency ratio to attain the desired spec MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
402 402 402 402 402 402
N18 TP_CPU0_TEMP_ANODE 2 2 2 2 2 2
- MAXBUS_1V5 - MAXBUS_1V8 TEMP_ANODE
One of these must be selected to set the Maxbus voltage TEMP_CATHODE N19 TP_CPU0_TEMP_CATHODE
* the MAXBUS_1V5 option does not exist for A7PM HPR_N A6 TP_CPU0_HPR_N
- CPU_A7PM - CPU_A8
One of these must be selected to ensure the the above
strap is interpreted correctly
BUS TYPE SELECT

SIGNAL TIED MODE R3704 MAXBUS VSEL
22
CPU0_BMODE0_L HIGH 60X BUS MODE 34 CPU0_BMODE0_L 2 1 =CPU_HRESET_L 11 34
(PROCESSOR)
CPU_HRESET_L MAX BUS MODE
5%
1/16W
MF-LF
MAXBUS_1V5
R3703 =PP1V5R1V8_MAXBUS 10 21 32 33 34
CPU0 FREQUENCY CONFIGURATION
402 10 () Indicates DFS setting supported by A8 only
34 CPU_BVSEL<0> 2 1
A7PM DFS SUPPORT PLL BITS
TABLE_BOMGROUP_HEAD
5% BOM GROUP BOM OPTIONS

C OVDD BVSEL0 BVSEL1
MAXBUS_1V8
R3702
1
1/16W
MF-LF
402 CPU0_BUSRATIO_1.0X
F/2
-
F/4
-
012345
001100 CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_1,CPU0_PLL4_0,CPU0_PLL5_0
TABLE_BOMGROUP_ITEM
C
10 TABLE_BOMGROUP_ITEM
5% CPU0_BUSRATIO_2.0X - - 010000 CPU0_PLL0_0,CPU0_PLL1_1,CPU0_PLL2_0,CPU0_PLL3_0,CPU0_PLL4_0,CPU0_PLL5_0

1.8V INTERFACE GND OVDD 1/16W
TABLE_BOMGROUP_ITEM
MF-LF
402 2 CPU0_BUSRATIO_3.0X - - 100000 CPU0_PLL0_1,CPU0_PLL1_0,CPU0_PLL2_0,CPU0_PLL3_0,CPU0_PLL4_0,CPU0_PLL5_0
2.5V INTERFACE OVDD OVDD (SPEC request this pull down
TABLE_BOMGROUP_ITEM
resistor should less than 250 ohm)

CPU0_BUSRATIO_4.0X 2.0X - 101000 CPU0_PLL0_1,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_0,CPU0_PLL4_0,CPU0_PLL5_0
2.5V INTERFACE CPU_HRESET_L OVDD TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_5.0X 2.5X - 101100 CPU0_PLL0_1,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_1,CPU0_PLL4_0,CPU0_PLL5_0

RESERVED(1.5V) CPU_HRESET_INV OVDD TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_5.5X (2.75X) - 100100 CPU0_PLL0_1,CPU0_PLL1_0,CPU0_PLL2_0,CPU0_PLL3_1,CPU0_PLL4_0,CPU0_PLL5_0

CPU_A7PM
A8 =PP1V5R1V8_MAXBUS
TABLE_BOMGROUP_ITEM
R3705 10 21 32 33 34 CPU0_BUSRATIO_6.0X 3.0X - 110100 CPU0_PLL0_1,CPU0_PLL1_1,CPU0_PLL2_0,CPU0_PLL3_1,CPU0_PLL4_0,CPU0_PLL5_0

10K TABLE_BOMGROUP_ITEM
34 CPU_BVSEL<1> 1 2 CPU0_BUSRATIO_6.5X (3.25X) - 010100 CPU0_PLL0_0,CPU0_PLL1_1,CPU0_PLL2_0,CPU0_PLL3_1,CPU0_PLL4_0,CPU0_PLL5_0

OVDD BVSEL0 BVSEL1
CPU_A8 5% TABLE_BOMGROUP_ITEM
1/16W CPU0_BUSRATIO_7.0X 3.5X - 001000 CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_0,CPU0_PLL4_0,CPU0_PLL5_0

1.8V INTERFACE GND GND R3706 1 MF-LF
1K CPU0_BUSRATIO_7.5X (3.75X) - 000100 CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_0,CPU0_PLL3_1,CPU0_PLL4_0,CPU0_PLL5_0

1.5V INTERFACE OVDD GND 5%
TABLE_BOMGROUP_ITEM
1/16W
MF-LF CPU0_BUSRATIO_8.0X 4.0X 2.0X 110000 CPU0_PLL0_1,CPU0_PLL1_1,CPU0_PLL2_0,CPU0_PLL3_0,CPU0_PLL4_0,CPU0_PLL5_0
RESERVED CPU_HRESET_L GND 402

RESERVED CPU_HRESET_INV GND TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_9.0X 4.5X (2.25X) 011110 CPU0_PLL0_0,CPU0_PLL1_1,CPU0_PLL2_1,CPU0_PLL3_1,CPU0_PLL4_1,CPU0_PLL5_0

2.5V INTERFACE GND OVDD TABLE_BOMGROUP_ITEM

2.5V INTERFACE OVDD OVDD TABLE_BOMGROUP_ITEM
CPU0_BUSRATIO_10.0X 5.0X 2.5X 101010 CPU0_PLL0_1,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_0,CPU0_PLL4_1,CPU0_PLL5_0

RESERVED CPU_HRESET_L OVDD TABLE_BOMGROUP_ITEM

RESERVED CPU_HRESET_INV OVDD TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM
B CPU PULLUPS
TABLE_BOMGROUP_ITEM
B
TABLE_BOMGROUP_ITEM
34 33 32 21 10 =PP1V5R1V8_MAXBUS CPU0_BUSRATIO_12.5X (6.25X) - 111110 CPU0_PLL0_1,CPU0_PLL1_1,CPU0_PLL2_1,CPU0_PLL3_1,CPU0_PLL4_1,CPU0_PLL5_0

TABLE_BOMGROUP_ITEM

R3752 INTERRUPT PULL-UPS TABLE_BOMGROUP_ITEM
10K CPU0_BUSRATIO_13.5X (6.75X) - 111000 CPU0_PLL0_1,CPU0_PLL1_1,CPU0_PLL2_1,CPU0_PLL3_0,CPU0_PLL4_0,CPU0_PLL5_0

33 CPU_CHKSTP_OUT_L 1 2
TABLE_BOMGROUP_ITEM
5% 34 33 32 21 10 =PP1V5R1V8_MAXBUS CPU0_BUSRATIO_14.0X 7.0X 3.5X 110010 CPU0_PLL0_1,CPU0_PLL1_1,CPU0_PLL2_0,CPU0_PLL3_0,CPU0_PLL4_1,CPU0_PLL5_0

1/16W
MF-LF R3753 TABLE_BOMGROUP_ITEM
402 10K CPU0_BUSRATIO_15.0X 7.5X (3.75X) 000110 CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_0,CPU0_PLL3_1,CPU0_PLL4_1,CPU0_PLL5_0

34 CPU_LSSD_MODE_L 1 2
R3769 TABLE_BOMGROUP_ITEM
5% 10K CPU0_BUSRATIO_16.0X 8.0X 4.0X 110110 CPU0_PLL0_1,CPU0_PLL1_1,CPU0_PLL2_0,CPU0_PLL3_1,CPU0_PLL4_1,CPU0_PLL5_0

R3756 1/16W 34 CPU0_SMI_L 1 2
MF-LF TABLE_BOMGROUP_ITEM
10K 402 5% CPU0_BUSRATIO_17.0X 8.5X (4.25X) 000010 CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_0,CPU0_PLL3_0,CPU0_PLL4_1,CPU0_PLL5_0

CPU_MCP_L 1 2 1/16W
34
R3771 MF-LF TABLE_BOMGROUP_ITEM
5% 10K 402 CPU0_BUSRATIO_18.0X 9.0X 4.5X 001010 CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_0,CPU0_PLL4_1,CPU0_PLL5_0

1/16W 34 CPU0_SRESET_L 1 2
MF-LF
R3765
TABLE_BOMGROUP_ITEM
402 5% CPU0_BUSRATIO_20.0X 10.0X 5.0X 001110 CPU0_PLL0_0,CPU0_PLL1_0,CPU0_PLL2_1,CPU0_PLL3_1,CPU0_PLL4_1,CPU0_PLL5_0

10K 1/16W
34 CPU0_DFS2_L 1 2 MF-LF TABLE_BOMGROUP_ITEM
402 CPU0_BUSRATIO_21.0X 10.5X (5.25X) 010010 CPU0_PLL0_0,CPU0_PLL1_1,CPU0_PLL2_0,CPU0_PLL3_0,CPU0_PLL4_1,CPU0_PLL5_0

5%
1/16W
R3766
TABLE_BOMGROUP_ITEM
MF-LF CPU0_BUSRATIO_24.0X 12.0X 6.0X 011010 CPU0_PLL0_0,CPU0_PLL1_1,CPU0_PLL2_1,CPU0_PLL3_0,CPU0_PLL4_1,CPU0_PLL5_0

10K 402
34 CPU0_LVRAM_L 1 2 TABLE_BOMGROUP_ITEM

5%
1/16W
MF-LF R3767
34 CPU0_DFS4_L
402
1
10K
2
CPU PULLDOWNS
5%
1/16W
R3759 MF-LF R3761 A8 Configuration Straps
10K 402 1K
34 CPU0_L2TSTCLK 1 2 34 CPU0_L1TSTCLK 2 1
A 5%
1/16W
MF-LF R3758
5%
1/16W
MF-LF
SYNC_MASTER=MARIAS

A
402 10K 402
34 CPU_PMON_IN_L 1 2
R3772 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1/16W 1K AGREES TO THE FOLLOWING
R3707 MF-LF 34 CPU0_EXT_QUAL 2 1
402 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1K 5%
34 CPU0_BMODE1_L 2 1 1/16W II NOT TO REPRODUCE OR COPY IT
MF-LF
PID<0> SELECT 5%
1/16W
402 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
MF-LF R3757
402 10K SIZE DRAWING NUMBER REV.
34 11 =CPU_HRESET_L 1 2
5%
1/16W
MF-LF APPLE COMPUTER INC.
D 051-6839 F
402 SCALE SHT OF
NONE 37 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page: VCORE BULK CAPS
- =PPVCORE_CPU0
35 10 =PPVCORE_CPU0 40 X 1 UF (0402)
(NONE)
(NONE)
1
C3830 1
C3831 1
C3832 1
C3833 1
C3834 1
C3835 1
C3836 1
C3837
1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
D
402 402 402 402 402 402 402 402
D
1
C3838 1
C3839 1
C3840 1
C3841 1
C3842 1
C3843 1
C3844 1
C3845
B5 P12 10% 10% 10% 10% 10% 10% 10% 10%
U3600 2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
2
6.3V
C3 R5 CERM CERM CERM CERM CERM CERM CERM CERM
BGA 402 402 402 402 402 402 402 402
D6 (6 OF 6) R14
XXGHZ-XXV
A8-X.X
D13 R17
E17 T7
F3 T10
G17 U3
H4 U13
1
C3846 1
C3847 1
C3848 1
C3849 1
C3850 1
C3851 1
C3852 1
C3853
H7 U17 10% 10% 10% 10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
H9 V5
402 402 402 402 402 402 402 402
H11 V8
H13 V11
J6 V15
J8 A17
=PPVCORE_CPU0
J10
OMIT A19 1
C3854 1
C3855 1
C3856 1
C3857 1
C3858 1
C3859 1
C3860 1
C3861
35 10
J12
GND GND B13 1UF 1UF 1UF 1UF 1UF 1UF 1UF 1UF
10% 10% 10% 10% 10% 10% 10% 10%
CRITICAL 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
K7 B16 2 2 2 2 2 2 2 2
CERM CERM CERM CERM CERM CERM CERM CERM
K3 B18 402 402 402 402 402 402 402 402
K9 E12
C H8
U3600 A18
K11
K13
E19
F13 C
L6 F16
H10 BGA B17
L8 F18
H12 (4 OF 6) B19
XXGHZ-XXV
A8-X.X
L10 G19
J7 C13
L12 H18
J9 E13
M4 J14
J11 E16
M7 L14
J13 F12
M9 M15
K8 F17
M11 M17
K10 F19 =PPVCORE_CPU0
24 X 10 UF (0603)
35 10
M13 M19
K12 G11
VDD VDD N7 N14
K14 G16
P3 N16
L7 H14
P9 P15
1
C3800 1
C3801 1
C3802 1
C3803 1
C3804 1
C3805 1
C3806 1
C3807 1
C3808 1
C3809
L9
OMIT H17 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
P19 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
L11 H19 TP_CPU0_SENSEGND1 N13 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
SENSEGND1 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
CRITICAL 603 603 603 603 603 603 603 603 603 603
L13 M14 TP_CPU0_SENSEGND2 G12 SENSEGND2
M8 M16 (Kelvin sense points) A14 C17
M10 M18 NC N/C_1 N/C_21 NC
B14 N/C_22 D17
NC N/C_2 NC
M12 N15
C14 C18
1
C3810 1
C3811 1
C3812 1
C3813 1
C3814 1
C3815 1
C3816 1
C3817 1
C3818 1
C3819
A13 N17 NC N/C_3 N/C_23 NC 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF 10uF
D14 N/C_24 D18 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
A16 P16 NC N/C_4 NC 4V 4V 4V 4V 4V 4V 4V 4V 4V 4V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
E14 C19
P18 NC N/C_5 N/C_25 NC 603 603 603 603 603 603 603 603 603 603
F14 N/C_26 D19
NC N/C_6 NC
TP_CPU0_SENSEVDD1 N12 SENSEVDD1 AVDD A8 =PPAVDD_CPU0 G14 N/C_27 H16
10 NC N/C_7 NC
TP_CPU0_SENSEVDD2 G13 A15 J16
SENSEVDD2 NC N/C_8 N/C_28 NC
B15 K16
1
C3820 1
C3821 1
C3822 1
C3823
(Kelvin sense points) NC N/C_9 N/C_29 NC 10uF 10uF 10uF 10uF
C15 N/C_30 L16 20% 20% 20% 20%
NC N/C_10 NC
B NC D15
E15
N/C_11 N/C_31 J17
K17
NC
2
4V
X5R
603
2
4V
X5R
603
2
4V
X5R
603
2
4V
X5R
603
B
NC N/C_12 N/C_32 NC
F15 N/C_33 L17
NC N/C_13 NC
G15 N/C_34 J18
NC N/C_14 NC
H15 N/C_35 K18
NC N/C_15 NC
J15 L18
NC N/C_16 N/C_36 NC
K15 N/C_37 J19
NC N/C_17 NC
L15 N/C_38 K19
NC N/C_18 NC
C16 L19
NC N/C_19 N/C_39 NC
D16
NC N/C_20
A8 Power (CPU0)

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 38 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
"Low" and "Mid" States "High" State
36 10 =PP3V3_PWRON_CPUVCORE_VID CPU_VCORE_3STATES
THERM THERM VCORE_SNS NO STUFF Q16BST&Q41 Q16BST&Q41 Q16BST&Q41 NO STUFF NO STUFF NO STUFF NO STUFF
I400 36
1 1 1 1 1 1 1 1
1 C3990
I401 THERM THERM VCORE_GNDSNS 36
R3980 R3982 R3984 R3986 R3970 R3972 R3974 R3976 16 0.1uF
470K 470K 470K 470K 470K 470K 470K 470K CPU_VCORE_3STATES VCC
20%
5% 5% 5% 5% 5% 5% 5% 5% 2 10V
CERM
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W CRITICAL 402
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF U3990
TABLE_5_HEAD 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 74CBTLV3257 4
VCORE_VID_A<1> 2 VCORE_VID<1>
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION (WITH VCORE OFFSET)
VCORE_VID_A<1> 36 VCORE_VID_B<1> 36
36
A1 QSOP Y1
SYM_VER-2
36
TABLE_5_ITEM
1.5GHZ 36 VCORE_VID_B<1> 3
114S0270 1 RES,3.48K,1%,1/16W,MF-LF,402,SMD R3946 CPU0_VCORE_1V22 VCORE_VID_A<2> 36 VCORE_VID_B<2> 36
B1
VCORE_VID_A<2> 5 Y2 7 VCORE_VID<2>
114S0258 1 RES,2.61K,1%,1/16W,MF-LF,402,SMD R3944 CPU0_VCORE_1V22
TABLE_5_ITEM
1.260V -> 0.940V VCORE_VID_A<3> 36 VCORE_VID_B<3> 36

36
36 VCORE_VID_B<2> 6
A2 36
(CPU SPEC: 1.220V -> 0.930V) VCORE_VID_A<4> 36 VCORE_VID_B<4> 36 B2

D 114S0246 1 RES,2.0K,1%,1/16W,MF-LF,402,SMD R3946 CPU0_VCORE_1V28
TABLE_5_ITEM
1.67GHZ
Q16BST&Q41 NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF
36 VCORE_VID_A<3>
VCORE_VID_B<3>
11
10
A3 Y3
9 VCORE_VID<3> 36
D
TABLE_5_ITEM
1.320V -> 0.940V 1

R3981 1R3983 1R3985 1R3987 1
R3971 1R3973 1R3975 1R3977
36
36 VCORE_VID_A<4> 14
B3
12 VCORE_VID<4> 36
(CPU SPEC: 1.280V -> 0.930V) 470K 470K 470K 470K 470K 470K 470K 470K A4 Y4
TABLE_5_ITEM
1.67GHZ 5% 5% 5% 5% 5% 5% 5% 5% 36 VCORE_VID_B<4> 13
114S0276 1 RES,4.02K,1%,1/16W,MF-LF,402,SMD R3946 CPU0_VCORE_1V30 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W B4
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
TABLE_5_ITEM
1.340V -> 0.940V 2 402 2 402 2 402 2 402 2 402 2 402 2 402 2 402 11 =CPU0_VID_AB_SEL 1
SEL 8 7 6 5 CPU_VCORE_2STATES
(CPU SPEC: 1.300V -> 0.930V) VID_MUX_OE_L 15
TABLE_5_ITEM
1.67GHZ <D4> <D3> <D2> <D1> <D4> <D3> <D2> <D1> CPU_VCORE_3STATES OE
114S0246 1 RES,2.0K,1%,1/16W,MF-LF,402,SMD R3946 CPU0_VCORE_1V33 1 GND RP3990
TABLE_5_ITEM
1.370V -> 0.940V Pullup on =CPU0_VID_AB_SEL

will set default mux state R3990 0
5%
114S0294 1 RES,6.04K,1%,1/16W,MF-LF,402,SMD R3944 CPU0_VCORE_1V33 to VID_B. 1K 8
1/16W
(CPU SPEC: 1.330V -> 0.930V) 5% SM-LF
1/16W
MF-LF
Keep trace fat (1.00-2.54 mm) and short!! 2 402 1 2 3 4
10 =PPVIN_CPUVCORE_MAX1717
36 VCORE_VID_A<1>
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL 36 VCORE_VID_A<2>
1 C3937 1 C3938 1 C3939 1 C3940 1 C3941 1 C3942 1 C3943 36 VCORE_VID_A<3>
10 =PP5V_PWRON_CPUVCORE_VDD 10uF 10uF 10uF 10uF 10uF 10uF 10uF 36 VCORE_VID_A<4>
10% 10% 10% 10% 10% 10% 10%
25V 25V 25V 25V 25V 25V 25V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
1206 1206 1206 1206 1206 1206 1206
PLACE CLOSE TO 1
TO PINS 15 & 13 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
10 =PP5V_PWRON_CPUVCORE_PWRSEQ
D3901
SOD-123 1 C3944 1 C3945 1 C3946 1 C3947 1 C3948 1 C3949
C3900 B0530WXF 10uF 10uF 10uF 10uF 10uF 10uF
R39601 1
1UF 2 10%
25V
10%
25V
10%
25V
10%
25V
10%
25V
10%
25V
1
R3965 20 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
VCORE_BOOST
5% 20%
100K 1/16W 2 10V
CERM
1206 1206 1206 1206 1206 1206
1% MF-LF 603
1/16W 402 2
MF-LF
2 402 VCORE_VCC
C VCORE_CPU0_SHDN_L
VOLTAGE=12.8V
MIN_NECK_WIDTH=0.25 mm 5 C
26
R39611 C3960 1
7 15
CRITICAL
XW3900
SM
0 1UF VCC VDD MIN_LINE_WIDTH=0.5 mm 4
CPUVCORE_VSENSE_R
R39621
5%
1/16W 20%
10V U3900 MIN_NECK_WIDTH=0.25 mm Q3900
27.4K
MF-LF
402 2 CERM 2
603
MAX1717 NO STUFF HAT2168H
1% QSOP-LF (VCORE_VPLUS) LFPAK Keep trace fat and short!!
1/16W
2 SKP/SDN V+ 1
1 C3902
MF-LF
402 2 R3951 0.0047uF
10% Keep trace fat and short!! CRITICAL CRITICAL
(VCORE_SNS) 5 FBS 2.2
3
BST 22 VCORE_BST2 1 2 25V
CERM 1 2 3 R3900 =PPVCORE_CPU_REG 10
VCORE_ILIM 10 ILIM DH 24 5% 402 0.0012
1
(VCORE_GNDSNS) 11 GNDS 1/10W 1
MF-LF
36 10 =PP3V3_PWRON_CPUVCORE_VID 36 11 =CPU0_MAX1717_AB_SEL 16 A/B 603
1 C3951 5
L3900
1.0uH-20.5
1%
1W
NO STUFF CRITICAL VCORE_DH MF-LF
0.1UF 5 SM1 2512
1 20%
R3988 VCORE_REF 9 REF 25V
2 CERM CRITICAL
NO STUFF
0 1
Q3903 R3901
603 CRITICAL 4
5% 4
1/16W VCORE_TON 8 TON LX 23 VCORE_LX
Q3902 2.2
MF-LF HAT2160H 5% CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
3
2 402 HAT2160H 1/4W CRITICAL
MAX1717 VID CAN TAKE 3.3V TO 5.5V INPUTS VCORE_CC 6 CC DL 14 VCORE_DL MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm LFPAK
LFPAK MF-LF
1206 2 D3900 C3910 1 C3912 1 C3914 1 C3916 1 C3918 1
<D0> PWRMITE
330uF 330uF 330uF 330uF 330uF
36 VCORE_VID<0> MIN_LINE_WIDTH=0.25 mm 21 D0 GND 13 VCORE_GND SNM540XF 20% 20% 20% 20% 20%
MIN_NECK_WIDTH=0.15 mm VOLTAGE=0V 2.5V-ESR9V 2 2.5V-ESR9V 2 2.5V-ESR9V 2 2.5V-ESR9V 2 2.5V-ESR9V 2
36 VCORE_VID<1> MIN_LINE_WIDTH=0.25
MIN_NECK_WIDTH=0.15
mm
mm
20 D1 MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm SM
XW3910 1 2 3 C3903 1 1 2 3 POLY
CASE-D2E-LF
POLY
CASE-D2E-LF
POLY
CASE-D2E-LF
POLY
CASE-D2E-LF
POLY
CASE-D2E-LF
VCORE_VID<2> MIN_LINE_WIDTH=0.25 mm 19 D2 FB 4 VCORE_FB CPU_VCORE_SNUB
36
0.0022UF
1
MIN_NECK_WIDTH=0.15 mm 18 10%
36 VCORE_VID<3> MIN_LINE_WIDTH=0.25 mm D3 TIME 3 VCORE_TIME 50V CRITICAL CRITICAL CRITICAL CRITICAL
MIN_NECK_WIDTH=0.15 mm R3910 CERM 2 1 1 1 1
36 VCORE_VID<4> MIN_LINE_WIDTH=0.25
MIN_NECK_WIDTH=0.15
mm
mm
17 D4 VGATE 12 =VCORE_PGOOD 26
100 2 402 C3911 C3913 C3915 C3917
Q16BST&Q41 1 330uF 330uF 330uF 330uF
20% 20% 20% 20%
R39891 C3964 1 R39641 R39631 1 C3962 C3963 1 5% NO STUFF 2 2.5V-ESR9V 2 2.5V-ESR9V 2 2.5V-ESR9V 2 2.5V-ESR9V
0 0.01UF 66.5K 12.7K 1UF
20%
220PF
5%
R39501 C3950 1 1/16W
MF-LF C3901 1
POLY
CASE-D2E-LF
POLY
CASE-D2E-LF
POLY POLY
CASE-D2E-LF CASE-D2E-LF
5% 1% 1% 390K 0.001UF 402 0.0022uF
1/16W 20%
16V 1/16W 1/16W 2 10V
CERM
25V
CERM 2 5% 20% 10%
MF-LF CERM 2 MF-LF MF-LF 1/16W
B 402 2 402 402 2 402 2 603 402 MF-LF
402 2
50V
CERM 2 XW3911
SM
50V
CERM 2 B
402 603
VCORE_GNDA
VOLTAGE=0V
VCORE_OFFSET_SW VCORE_OFFSET MIN_LINE_WIDTH=0.5 mm Connect MAX1717 GND pin 13
R3943 1 OMIT 1
R3945
to GND at bottom-side FET Keep trace fat and short!!
100K 2 VCORE_SEL_OFF_PU R3944
=PP3V3_PWRON_CPUVCORE_OFFSET 1 162K
10
5% 1%
6.04K 1%
1/10W
R2 GROUND SENSE VOLTAGE DIVIDER
NO STUFF 1/16W 1/16W MF-LF
MF-LF MF-LF 2 603 This allows for an offset to the ground sense to adjust the output voltage.
R3940 402
2 402 VREF = 2.0V WITH A 0.85 SCALE FACTOR, HENCE VOFFSET = 1.7V * (R1/(R1+R2)) AND VCORE = VDAC + VOFFSET.
0 VCORE_SEL_ON VCORE_GNDDIV 36
OUTPUT VOLTAGE 1
5%
1/16W
MF-LF
2
3 VCORE_OFFSET_SW 1
OMIT
R3946 PLACE THIS SHORT AT
PIN OF 1000uF CAP
Q3940 2.0K
VDAC D3 D2 D1 D0 36 11 =CPU0_MAX1717_AB_SEL
402 D
2N7002DW-X-F
SOT-363
1%
1/16W
MF-LF
R1
NOTE: R3945 (R2) NO STUFFED FOR NO OFFSET CASE
CLOSEST TO CPU
XW3901
D4=0 D4=1 VCORE_OFFSET_SW
R3941
0 AB_SEL_LOW
5 G S
2 402
36 VCORE_GNDSNS 2
SM
1
2.00 1.275 0 0 0 0 1 2
6 VCORE_OFFSET_SW
4
36
VOLTAGE=0V MIN_LINE_WIDTH=0.25 mm
VCORE_SNS
5%
1.95 1.250 0 0 0 1 1/16W
MF-LF
D Q3940 ROUTE AS DIFFERENTIAL PAIR OMIT
VOLTAGE=1.3V MIN_LINE_WIDTH=0.25 mm
402 2N7002DW-X-F
1.90 1.225 0 0 1 0 2 G S
SOT-363
R3998 FMAX CONNECTOR
2.05K2
1.85 1.200 0 0 1 1 NO STUFF
1 1
36 VCORE_GNDDIV 1 CRITICAL
1.80 1.175 0 1 0 0 R3942 1%

1/16W
OMIT
1.75 1.150 0 1 0 1
100K
5%
1/16W
MF-LF
402 J3999
M-ST-SM-52465-1217
MF-LF
1.70 1.125 0 1 1 0
402 2 OMIT
R3999
1
2
12
11
VCORE_VID<0> CPU VCore Supply
VCORE_GNDDIV_TEST VCORE_VID<1>
A 1.65 1.100 0 1 1 1 100 36
SYNC_MASTER=MARIAS SYNC_DATE=08/24/2005
1.60 1.075 1 0 0 0
36 VCORE_GNDSNS 1
1%
2
25 24
VCORE_GNDSNS_TEST
SYS_RESET_BUTTON_L
3
4
10
9
VCORE_VID<2>
VCORE_VID<3>
36
36 NOTICE OF PROPRIETARY PROPERTY

A
1/16W
SYS_POWER_BuTTON_L 5 8 VCORE_VID<4>
1.55 1.050 1 0 0 1
FOR V-STEP:
MF-LF
402
57 30 25 24
NC (RFU) 6 7
36
1.50 1.025 1 0 1 0
When A/B_ is high (fast): D4-D0 read as-is
1.45 1.000 1 0 1 1 A/B_ =
When A/B_ is low (slow): <=1K-ohm -> 0 II NOT TO REPRODUCE OR COPY IT
1.40 0.975 1 1 0 0 D<4..0> Hi/Fast Lo/Slow

>=100K-ohm -> 1
1.35 0.950 1 1 0 1
<= 1K PU 1 0 SIZE DRAWING NUMBER REV.
1.30 0.925 1 1 1 0
>=
>=
100K PU
100K PD
1
0
1
1
If all pull-ups are >=100K and all
APPLE COMPUTER INC.
D 051-6839 F
NO CPU NO CPU
<= 1K PD 0 0 pull-downs are <=1K, V A = V B . SCALE SHT OF
1 1 1 1
NONE 39 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
CPU PLL POWER SUPPLY

R4600
0
C 10 =PPVIN_CPU0_AVDD 1
5%
1/16W
2 PPVIN_CPU0_AVDD
VOLTAGE=3.3V
VOLTAGE=1.22V
MIN_NECK_WIDTH=0.25 mm R4625
10
C
MF-LF PPVOUT_CPU0_AVDD_R 1 2 =PPVOUT_CPU0_AVDD 10
402 CRITICAL
5%
C4600 1 D4610 CRITICAL 1
1/16W
2.2uF
SOT23
3 1 U4600
1 C4620 R4620
24.9K
MF-LF
402
10%
6.3V FAN2558
0.01UF 1%
2 10% 1/16W
CERM1 SOT23-6-LF 2 16V MF-LF
603-1 BAT54E3 1 CERM
VIN VOUT 6 2 402
R4610 4 PG
402 1 C4625 1 C4626 1 C4627
100K 2 1UF 0.1UF 4.7UF
26 CPU_AVDD_EN 1 FAN2558_EN_CPU0 3 EN ADJ 5 FAN2558_ADJ_CPU0 10% 20% 20%
NO STUFF OMIT 2 6.3V
CERM 2 10V
CERM
6.3V
2 CERM
1%
1 GND 1 402 402 805
1/16W
MF-LF C4610 1 R4611 2
R4621
402
0.1UF 357K 23.2K
20% 1% 1%
10V 1/16W 1/16W
CERM 2 MF-LF MF-LF
402 2 402 2 402
AVDD=0.59*(1+R4620/R4621)
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) BOM OPTION
B 114S0349 1 RES,23.2K,1%,1/16W,MF-LF,402,SMD R4621 CPU0_AVDD_1V22

TABLE_5_ITEM
TABLE_5_ITEM
B
114S0346 1 RES,21.5K,1%,1/16W,MF-LF,402,SMD R4621 CPU0_AVDD_1V28
TABLE_5_ITEM

TABLE_5_ITEM
CPU AVDD Supply


A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 46 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL DIFFERENTIAL_PAIR OMIT
RAM_CLK_0 RAM_DIFF RAM_DIFF RAM_CLK_0_R RAM_CLKDDR_0_P_R 38 39 U2100

RAM_CLK_0 RAM_DIFF RAM_DIFF RAM_CLK_0_R RAM_CLKDDR_0_N_R 38 39 I2
RAM_CLK_1 RAM_DIFF RAM_DIFF RAM_CLK_1_R RAM_CLKDDR_1_P_R 38 39

DDR2 I/O DECOUPLING BGA
RAM_CLKDDR_1_N_R
DDR2 POWER
RAM_CLK_1 RAM_DIFF RAM_DIFF RAM_CLK_1_R 38 39 (40 Balls on I2) 1 X 10uF (0603)
10 =PP1V8_PWRON_I2_RAM (8 of 14)
40 X 1uF (0402) AA24
RAM_CLK_2 RAM_DIFF RAM_DIFF RAM_CLK_2_R RAM_CLKDDR_2_P_R 38 39 VTT18_0
RAM_CLKDDR_2_N_R AA26
RAM_CLK_2 RAM_DIFF RAM_DIFF RAM_CLK_2_R 38 39 VTT18_1
AA28
RAM_CLKDDR_3_P_R
C4749 1 1
C4750 1
C4751 1
C4752 1
C4753 1
C4754 VTT18_2
RAM_CLK_3 RAM_DIFF RAM_DIFF RAM_CLK_3_R 38 39
10UF 1uF 1uF 1uF 1uF 1uF AB26
VTT18_3
RAM_CLKDDR_3_N_R 20% 10% 10% 10% 10% 10%
RAM_CLK_3 RAM_DIFF RAM_DIFF RAM_CLK_3_R 38 39
D RAM_CKE_0 RAM RAM RAM_CKE_R<1..0> 38 39

6.3V
X5R
603
2 2
6.3V
CERM
402
2
6.3V
CERM
402
2
6.3V
CERM
402
2
6.3V
CERM
402
2
6.3V
CERM
402
AC24
AC27
VTT18_4
VTT18_5
D
RAM_CKE_R<3..2> AC28
RAM_CKE_1 RAM RAM 38 39 VTT18_6
AC31
OMIT VTT18_7
RAM_CS_0 RAM RAM RAM_CS_L_R<1..0> 38 39 AC34
VTT18_8
RAM_CS_1 RAM RAM RAM_CS_L_R<3..2> 38 39 U2100 1 C4755 1 C4756 1 C4757 1 C4758 1 C4759 AD24
1uF 1uF 1uF 1uF 1uF VTT18_9
I2 10% 10% 10% 10% 10% AD28
RAM_ADDR_CTL RAM RAM RAM_ADDR_R<13..0> 38 39 6.3V 6.3V 6.3V 6.3V 6.3V VTT18_10
BGA 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM AF28
RAM_ADDR_CTL RAM RAM RAM_BA_R<2..0> 38 39 402 402 402 402 402 VTT18_11
RAM_RAS_L_R
MEMORY INTERFACE AF31
RAM_ADDR_CTL RAM RAM 38 39 VTT18_12
(7 of 14) AF34
RAM_ADDR_CTL RAM RAM RAM_CAS_L_R 38 39 39 38 BI RAM_DATA_R<63..0> AK31 R33
RAM_ADDR_R<13..0> OUT 38 39 VTT18_13
0 DDR_D_00_H DDR_A_00_H 0
AJ31
RAM_ADDR_CTL RAM RAM RAM_WE_L_R 38 39 AK32 R34 VTT18_14
AJ34
RAM_ODT0 RAM RAM RAM_ODT_R<0> 38 39 AL33 R35
1
C4760 1
C4761 1
C4762 1
C4763 1
C4764 VTT18_15
1uF 1uF 1uF 1uF 1uF AM34
RAM_ODT1 RAM RAM RAM_ODT_R<1> 38 39 AH31 T32 10% 10% 10% 10% 10% VTT18_16
6.3V 6.3V 6.3V 6.3V 6.3V AP34
AK34 R36 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM VTT18_17
RAM_DQS0 RAM RAM RAM_DQS_P_R<0> 38 39 4 DDR_D_04_H DDR_A_04_H 4
402 402 402 402 402 C34
AK33 T33 VTT18_18
E34
AK35 T34 VTT18_19
H31
AK36 T36 VTT18_20
H34
AF36 T35 1 1 1 1 1 VTT18_21
RAM_DQS4 RAM RAM RAM_DQS_P_R<4> 38 39 8 DDR_D_08_H DDR_A_08_H 8 C4765 C4766 C4767 C4768 C4769 K28
AG36 U36 1uF 1uF 1uF 1uF 1uF VTT18_22
10% 10% 10% 10% 10% L28
AG35 P36 6.3V 6.3V 6.3V 6.3V 6.3V VTT18_23
RAM_DQS6 RAM RAM RAM_DQS_P_R<6> 38 39 10 DDR_D_10_H DDR_A_10_H 10 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM L31
AG34 V32 402 402 402 402 402 VTT18_24
L34
AG33 V33 VTT18_25
12 DDR_D_12_H DDR_A_12_H 12
M25
RAM_DQM0 RAM RAM RAM_DQM_R<0> 38 39 AH36 N32 VTT18_26
13 DDR_D_13_H DDR_A_13_H 13
N26
RAM_DQM1 RAM RAM RAM_DQM_R<1> 38 39 AH35 N36
RAM_BA_R<2..0> OUT 38 39 VTT18_27
14 DDR_D_14_H DDR_BA_0_H 0
1 1 1 1 1 P28
RAM_DQM2 RAM RAM RAM_DQM_R<2> 38 39 AH34 R32 C4770 C4771 C4772 C4773 C4774 VTT18_28
1uF 1uF 1uF 1uF 1uF P31
RAM_DQM3 RAM RAM RAM_DQM_R<3> 38 39 AE33 V34 VTT18_29
10% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V 6.3V P34
RAM_DQM4 RAM RAM RAM_DQM_R<4> 38 39 AE34 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM VTT18_30
C RAM_DQM5
RAM_DQM6
RAM
RAM
RAM
RAM
RAM_DQM_R<5>
RAM_DQM_R<6>
38 39
38 39
17
18
AE35
DDR_D_17_H
DDR_D_18_H DDR_CS_0_L AM36
0
RAM_CS_L_R<3..0> OUT 38 39
402 402 402 402 402 R24
R26
VTT18_31
VTT18_32
C
AD33 AL31
19 DDR_D_19_H DDR_CS_1_L 1
R28
RAM_DQM7 RAM RAM RAM_DQM_R<7> 38 39 AE36 AL35 VTT18_33
20 DDR_D_20_H DDR_CS_2_L 2
T25
AD34 AL32 VTT18_34
RAM_DATA_0 RAM RAM RAM_DATA_R<7..0> 38 39 21 DDR_D_21_H DDR_CS_3_L 3
1
C4775 1
C4776 1
C4777 1
C4778 1
C4779 U24
AD35 1uF 1uF 1uF 1uF 1uF VTT18_35
RAM_DATA_1 RAM RAM RAM_DATA_R<15..8> 38 39 22 DDR_D_22_H 10% 10% 10% 10% 10% U27
AD36 AH30
RAM_DQS_P_R<7..0> BI 38 39 6.3V 6.3V 6.3V 6.3V 6.3V VTT18_36
RAM_DATA_2 RAM RAM RAM_DATA_R<23..16> 38 39 23 DDR_D_23_H DDR_DQS_0_L 0 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM U29
Y36 AG32 402 402 402 402 402 VTT18_37
RAM_DATA_3 RAM RAM RAM_DATA_R<31..24> 38 39 24 DDR_D_24_H DDR_DQS_1_L 1
U31
AA36 AD32 VTT18_38
U34
AA35 AB33 VTT18_39
V25
AA34 M29 VTT18_40
V26
RAM_DATA_R<63..56> AA33 J32
1
C4780 1
C4781 1
C4782 1
C4783 1
C4784 VTT18_41
RAM_DATA_7 RAM RAM 38 39 28 DDR_D_28_H DDR_DQS_5_L 5
1uF 1uF 1uF 1uF 1uF V29
AA32 G35 10% 10% 10% 10% 10%
VTT18_42
29 DDR_D_29_H DDR_DQS_6_L 6
6.3V 6.3V 6.3V 6.3V 6.3V W24
AB36 E31 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM VTT18_43
30 DDR_D_30_H DDR_DQS_7_L 7
Page Notes 31
AB34
M36
DDR_D_31_H
AJ36
RAM_DQM_R<7..0> OUT 38 39
402 402 402 402 402 Y25
Y28
VTT18_44
VTT18_45
32 DDR_D_32_H DDR_DM_0_L 0
Y31
Power aliases required by this page: M35 AH33 VTT18_46
Y34
- =PP1V8_PWRON_I2_RAM M34 AE32 VTT18_47
1
C4785 1
C4786 1
C4787 1
C4788 1
C4789
- =PP1V8_RAM_I2_VREF M33 AB35 1uF 1uF 1uF 1uF 1uF
10% 10% 10% 10% 10%
M32 N28 6.3V 6.3V 6.3V 6.3V 6.3V
Signal aliases required by this page: 36 DDR_D_36_H DDR_DM_4_L 4 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
L36 K35 402 402 402 402 402
(NONE) 37 DDR_D_37_H DDR_DM_5_L 5
M31 F32
BOM options provided by this page: M30 C36

(NONE) K32
40 DDR_D_40_H
H36 N35 RAM_RAS_L_R
1
C4790 1
C4791 1
C4792 1
C4793 1
C4794
41 DDR_D_41_H DDR_RAS_L OUT 38 39
1uF 1uF 1uF 1uF 1uF
J36 N33 RAM_CAS_L_R 10% 10% 10% 10% 10%
42 DDR_D_42_H DDR_CAS_L OUT 38 39 6.3V 6.3V 6.3V 6.3V 6.3V
J33 N34 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
43 DDR_D_43_H DDR_WE_L RAM_WE_L_R 38 39
B 44
J34
J35
DDR_D_44_H
AN35
RAM_CKE_R<3..0>
OUT
OUT 38 39
402 402 402 402 402
B
45 DDR_D_45_H DDR_CKE_0_L 0
K33 AL36
K34 AP36
1 C4795 1 C4796 1 C4797
48
G34
DDR_D_48_H DDR_CKE_3_L AL34 3
1uF 1uF 1uF
10% 10% 10%
F36 6.3V 6.3V 6.3V
49 DDR_D_49_H 2 CERM 2 CERM 2 CERM
F35 J31 RAM_ODT_R<0> 402 402 402
50 DDR_D_50_H ODT0 OUT 38 39
G33 AB30 RAM_ODT_R<1>
51 DDR_D_51_H ODT1 OUT 38 39
F34
52 DDR_D_52_H
G32 W31 RAM_CLKDDR_0_P_R
53 DDR_D_53_H DDR_MCLK_0_P OUT 38 39
E36 W30 RAM_CLKDDR_0_N_R
54 DDR_D_54_H DDR_MCLK_0_N OUT 38 39
F33
55 DDR_D_55_H
A32
56 DDR_D_56_H V36
A34 DDR_MCLK_1_P RAM_CLKDDR_1_P_R OUT 38 39
57 DDR_D_57_H V35
F30 DDR_MCLK_1_N RAM_CLKDDR_1_N_R OUT 38 39
58 DDR_D_58_H
10 =PP1V8_RAM_I2_VREF B33
59 DDR_D_59_H
C33 W29 RAM_CLKDDR_2_P_R
1
60 DDR_D_60_H DDR_MCLK_2_P OUT 38 39
R4700 61
D33
DDR_D_61_H DDR_MCLK_2_N W28 RAM_CLKDDR_2_N_R OUT 38 39
1K D34
1% 62 DDR_D_62_H
1/16W D35
MF-LF 63 DDR_D_63_H W35
402 2 DDR_MCLK_3_P RAM_CLKDDR_3_P_R OUT 38 39
W34 RAM_CLKDDR_3_N_R
AG28 DDR_MCLK_3_N OUT 38 39
I2_MEM_VREF DDR_VREF_0_H
Y21
DDR_VREF_1_H
V21
R4701 1
1 C4705 1 C4706 DDR_VREF_2_H
1K 0.1UF 0.1UF T21
DDR_VREF_3_H
I2 Memory Interface
20% 20%
1% 10V 10V
A 1/16W
MF-LF
402
2
2 CERM
402
U2100.AG28
2 CERM
402
U2100.V21
SYNC_MASTER=MARIAS

A
AC22 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
I2_SD_REF SD_REF_H PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1
R4710 II NOT TO REPRODUCE OR COPY IT
1K
1% III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1/16W
MF-LF
2
402 SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 47 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Main Memory Series Termination
SERIES RESISTORS FOR CONTROL SIGNALS
PINS ARE SWAPPABLE FOR RPAKS RP4800-RP4804 SERIES RESISTORS FOR CLOCKS
RP4800 R4850
22 22
3 6 38 IN RAM_CLKDDR_0_P_R 1 2 RAM_CLKDDR_0_P OUT 39 40
38 RAM_ADDR_R<0> RAM_ADDR<0> 39 40 41
5%
5% RP4803 1/16W
R4851
D 38 RAM_ADDR_R<1>
1/16W
SM-LF 2
22
7 RAM_ADDR<1> 39 40 41 38 IN RAM_CLKDDR_0_N_R
MF-LF
402
1
22 2 RAM_CLKDDR_0_N OUT 39 40
D
RP4803 5% 5%
4
22 5
1/16W
SM-LF R4855 1/16W
MF-LF
38 RAM_ADDR_R<2> RAM_ADDR<2> 39 40 41 22 402
38 IN RAM_CLKDDR_1_P_R 1 2 RAM_CLKDDR_1_P OUT 39 40
5%
1/16W
RP4803 5%
22
38 RAM_ADDR_R<3> SM-LF 1 8 RAM_ADDR<3> 39 40 41
1/16W
MF-LF R4856
402 22
RP4803 5% 38 IN RAM_CLKDDR_1_N_R 1 2 RAM_CLKDDR_1_N OUT 39 40
22 1/16W
SM-LF 5%
RAM_ADDR_R<4> 3 6 RAM_ADDR<4>
38 39 40 41
R4860 1/16W
MF-LF
5%
1/16W
RP4801 RAM_CLKDDR_2_P_R 1
22 2
402
RAM_CLKDDR_2_P
SM-LF 22 38 IN OUT 39 41
38 RAM_ADDR_R<5> 4 5 RAM_ADDR<5> 39 40 41 5%
RP4802 5%
1/16W
MF-LF R4861
22 1/16W 402 22
1 8 SM-LF 38 IN RAM_CLKDDR_2_N_R 1 2 RAM_CLKDDR_2_N OUT 39 41
5%
5%
1/16W
RP4802 R4865 1/16W
MF-LF
SM-LF 4
22 5 22 402
38 RAM_ADDR_R<7> RAM_ADDR<7> 39 40 41 38 IN RAM_CLKDDR_3_P_R 1 2 RAM_CLKDDR_3_P OUT 39 41
RP4802 5% 5%
3
22
6
1/16W
SM-LF
1/16W
MF-LF R4866
38 RAM_ADDR_R<8> RAM_ADDR<8> 39 40 41 402 22
38 IN RAM_CLKDDR_3_N_R 1 2 RAM_CLKDDR_3_N OUT 39 41
5%
1/16W
RP4802 5%
SM-LF 22 1/16W
38 RAM_ADDR_R<9> 2 7 RAM_ADDR<9> 39 40 41 MF-LF
402
RP4800 5%
1/16W
22
38 RAM_ADDR_R<10> 2 7 SM-LF RAM_ADDR<10> 39 40 41 SERIES RESISTORS FOR CS / CKE
5%
1/16W
RP4801 Do not swap with other RPAKs
SM-LF 22
38 RAM_ADDR_R<11> 3 6 RAM_ADDR<11> 39 40 41
C RP4801
22
5%
1/16W
RP4870
C
RAM_ADDR_R<12> 2 7 SM-LF RAM_ADDR<12>
38 39 40 41
22
5% RP4804 38 IN RAM_CS_L_R<0> 1 4 RAM_CS_L<0> OUT 39 40
1/16W 22
SM-LF 4 5 38 IN RAM_CS_L_R<2> 2 3 RAM_CS_L<2> OUT 39 41
5%
5% 1/16W
1/16W SM-LF
SM-LF
RP4871
RP4800 22
22 38 IN RAM_CS_L_R<1> 1 4 RAM_CS_L<1> OUT 39 40
38 RAM_BA_R<0> 1 8 RAM_BA<0> 39 40 41
38 IN RAM_CS_L_R<3> 2 3 RAM_CS_L<3> OUT 39 41
5%
1/16W
RP4800 5%
SM-LF 22 1/16W
38 RAM_BA_R<1> 4 5 RAM_BA<1> 39 40 41 SM-LF
RP4801 5%
1/16W RP4875
1
22 8 SM-LF 22
38 RAM_BA_R<2> RAM_BA<2> 39 40 41
38 IN RAM_CKE_R<0> 1 4 RAM_CKE<0> OUT 39 40
5%
1/16W 38 IN RAM_CKE_R<2> 2 3 RAM_CKE<2> OUT 39 41
SM-LF 5%
1/16W
RP4804 SM-LF
22
38 RAM_RAS_L_R 1 8 RAM_RAS_L 39 40 41 RP4876
RP4804 5% 22
22 1/16W 38 IN RAM_CKE_R<1> 1 4 RAM_CKE<1> OUT 39 40
RAM_CAS_L_R 3 6 SM-LF RAM_CAS_L

38 39 40 41 38 IN RAM_CKE_R<3> 2 3 RAM_CKE<3> OUT 39 41
5%
1/16W
RP4804 5%
1/16W
SM-LF 22 SM-LF
38 RAM_WE_L_R 2 7 RAM_WE_L 39 40 41
5%
1/16W
B SM-LF 38 RAM_DATA_R<63..0> 39
RAM_DATA<63..0>
MAKE_BASE=TRUE
RAM_DATA_A<63..0>
RAM_DATA_B<63..0>
40
41
B
R4810
0
38 RAM_ODT_R<0> 1 2 RAM_ODT<0> 39 40
38 RAM_DQM_R<7..0> 39 RAM_DQM<7..0> RAM_DQM_A<7..0> 40
5% MAKE_BASE=TRUE
1/16W
R4811 RAM_DQM_B<7..0> 41
MF-LF
402 0
38 RAM_ODT_R<1> 1 2 RAM_ODT<1> 39 41
39
5% 38 RAM_DQS_P_R<7..0> RAM_DQS<7..0> RAM_DQS_A_P<7..0> 40
1/16W MAKE_BASE=TRUE
MF-LF RAM_DQS_B_P<7..0> 41
402
1 8 RAM_DQS_A_N<0> 1 8 RAM_DQS_B_N<0>
2
RP4872
10K 7 RAM_DQS_A_N<1>
40
40
2
RP4877
10K 7 RAM_DQS_B_N<1>
41
41
5% 5%
3 1/16W 6 RAM_DQS_A_N<2> 40
3 1/16W 6 RAM_DQS_B_N<2> 41
SM-LF SM-LF
4 5 RAM_DQS_A_N<3> 40
4 5 RAM_DQS_B_N<3> 41
NET_TYPE
1 8 RAM_DQS_A_N<4> 1 8 RAM_DQS_B_N<4>
2
RP4873
10K 7 RAM_DQS_A_N<5>
40
40
2
RP4878
10K 7 RAM_DQS_B_N<5>
41
41
RAM_DIFF RAM_DIFF RAM_CLK_0 RAM_CLKDDR_0_P 39 40 5% 5%
I196 3 1/16W 6 RAM_DQS_A_N<6> 40
3 1/16W 6 RAM_DQS_B_N<6> 41
RAM_DIFF RAM_DIFF RAM_CLK_0 RAM_CLKDDR_0_N 39 40 SM-LF SM-LF
I194 4 5 RAM_DQS_A_N<7> 40
4 5 RAM_DQS_B_N<7> 41
ECSETs provided by
memory controller.
I195 RAM_DIFF RAM_DIFF RAM_CLK_1 RAM_CLKDDR_1_P 39 40
I193 RAM_DIFF RAM_DIFF RAM_CLK_1 RAM_CLKDDR_1_N 39 40
I197 RAM_DIFF RAM_DIFF RAM_CLK_2 RAM_CLKDDR_2_P 39 41
I199 RAM_DIFF RAM_DIFF RAM_CLK_2 RAM_CLKDDR_2_N 39 41
RAM_CLKDDR_3_P
I198
I200
RAM_DIFF
RAM_DIFF
RAM_DIFF
RAM_DIFF
RAM_CLK_3
RAM_CLK_4 RAM_CLKDDR_3_N
39 41
39 41
Memory Series Termination
A I205 RAM
RAM
RAM
RAM
RAM_CKE<3..0>
RAM_CS_L<3..0>
39 40 41
39 40 41
SYNC_MASTER=MARIAS-NDIFF

SYNC_DATE=N/A
A
I204
I203 RAM RAM RAM_ADDR<13..0> 39 40 41
I202 RAM RAM RAM_BA<2..0> 39 40 41 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
I201 RAM RAM RAM_RAS_L 39 40 41
I208 RAM RAM RAM_CAS_L 39 40 41
I207 RAM RAM RAM_WE_L 39 40 41
I259 RAM RAM RAM_ODT<1..0> 39 40 41

I209
I206
RAM
RAM
RAM
RAM
RAM_DQS<7..0>
RAM_DQM<7..0>
39
39
APPLE COMPUTER INC.
D 051-6839 F
I210 RAM RAM RAM_DATA<63..0> 39 SCALE SHT OF
NONE 48 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
41 40 10 =PP1V8_PWRON_DDR2 201 NC =PP1V8_PWRON_DDR2 10 40 41
=RAM_VREF_A 1 2
40 VREF VSS0
3 CRITICAL 4
VSS1 DQ4 RAM_DATA_A<2> 39
39 RAM_DATA_A<3> 5
DQ0
J5000 DQ5
6 RAM_DATA_A<1> 39
RAM_DATA_A<0> 7 F-RT-SM 8
39 DQ1 VSS2
DDR2-SODIMM-STD
9 10 RAM_DQM_A<0>
VSS4 DM0 39
RAM_DQS_A_N<0> 11 12
39 DQS0* VSS5
RAM_DQS_A_P<0> 13 14 RAM_DATA_A<5>
39 DQS0 DQ6 39
15 16 RAM_DATA_A<7>
VSS6 DQ7 39
RAM_DATA_A<4> 17 18
39 DQ2 VSS7
RAM_DATA_A<6> 19 20 RAM_DATA_A<12>
39 DQ3 DQ12 39
21 22 RAM_DATA_A<11>
VSS8 DQ13 39
D 39 RAM_DATA_A<14> 23
25
DQ8 VSS9
24
26
D
RAM_DATA_A<15> RAM_DQM_A<1>
39
RAM_DQS_A_N<1>
27
29
DQ9
VSS10
DQS1*
DM1
VSS11
CK0
28
30 RAM_CLKDDR_0_P
39
DDR2 VREF
39
39 RAM_DQS_A_P<1> 31
DQS1 CK0*
32 RAM_CLKDDR_0_N
39
39
ONE 0.1UF PER SLOT
33 34
VSS12 VSS13
39 DQ10 DQ14 39
=RAM_VREF_A
40
39 DQ11 DQ15 39
39 40
VSS14
KEY
VSS15 1 C5001
41
VSS16 VSS17
42 0.1uF
20%
RAM_DATA_A<20> 43 44 RAM_DATA_A<23> 10V
2 CERM
39 DQ16 DQ20 39
RAM_DATA_A<18> 45 46 RAM_DATA_A<22> 402

39 DQ17 DQ21 39
47 48
VSS18 VSS19
RAM_DQS_A_N<2> 49 50 NC
39 DQS2* NC0
RAM_DQS_A_P<2> 51 52 RAM_DQM_A<2>
39 DQS2 DM2 39
53 54
VSS21 VSS22
39 DQ18 DQ22 39
39 DQ19 DQ23 39
59 60
VSS23 VSS24
39 DQ24 DQ28 39
39 DQ25 DQ29 39
39 RAM_DQM_A<3>
65
67
VSS25
DM3
VSS26
DQS3*
66
68 RAM_DQS_A_N<3> 39
DDR2 BYPASS
NC 69 70 RAM_DQS_A_P<3>
71
NC1
VSS27
DQS3
VSS28
72
39
SLOT "A"
C SLOT "A" 39
39
RAM_DATA_A<26>
RAM_DATA_A<27>
73
75
77
DQ26
DQ27
VSS29
DQ30
DQ31
VSS30
74
76
78
RAM_DATA_A<24>
RAM_DATA_A<28>
39
39 41 40 10 =PP1V8_PWRON_DDR2 C
UPPER/STD SLOT 39 RAM_CKE<0>
NC
79
81
83
CKE0
VDD0
NC2
NC/CKE1
VDD1
NC/A15
80
82
84 NC
RAM_CKE<1> 39
1 C5008
10UF
20%
1 C5009
10UF
20%
FACTORY SLOT 41 39
41 39
RAM_BA<2>
RAM_ADDR<12>
85
87
89
BA2
VDD2
A12
NC/A14
VDD3
A11
86
88
90
NC
RAM_ADDR<11> 39 41
6.3V
2 X5R
603
6.3V
2 X5R
603
RAM_ADDR<9> 91 92 RAM_ADDR<7>
41 39 A9 A7 39 41
41 39
95
A8 A6
96
39 41
1 C5010 1 C5011 1 C5012 1 C5013 1 C5014
VDD4 VDD5 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RAM_ADDR<5> 97 98 RAM_ADDR<4> 20% 20% 20% 20% 20%
41 39 A5 A4 39 41
99 100 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
41 39 RAM_ADDR<3> A3 A2 RAM_ADDR<2> 39 41
402 402 402 402 402
41 39 A1 A0 39 41
103 104
VDD6 VDD7
RAM_ADDR<10> 105 106 RAM_BA<1>
41 39 A10/AP BA1 39 41
41 39 RAM_BA<0> 107
BA0 RAS*
108 RAM_RAS_L 39 41
1 C5015 1 C5016 1 C5017 1 C5018 1 C5019
41 39 RAM_WE_L 109
WE* S0*
110 RAM_CS_L<0> 39
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
20% 20% 20% 20% 20%
2 10V
10V
111
VDD8 VDD9
112
CERM 2 CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
RAM_CAS_L 113 114 RAM_ODT<0> 402 402 402 402 402
41 39 CAS* ODT0 39
RAM_CS_L<1> 115 116 RAM_ADDR<13>

39 NC/S1* NC/A13 39 41
117 118
VDD10 VDD11
(ODT<1>) 119 120 NC
121
NC/ODT1 NC3
122
1 C5020 1 C5021 1 C5022 1 C5023
VSS31 VSS32 0.1uF 0.1uF 0.1uF 0.1uF
RAM_DATA_A<39> 123 124 RAM_DATA_A<36> 20% 20% 20% 20%
39 DQ32 DQ36 39
125 126 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
39 RAM_DATA_A<38> DQ33 DQ37 RAM_DATA_A<35> 39
402 402 402 402
B 39 RAM_DQS_A_N<4>
127
129
VSS33
DQS4*
VSS34
DM4
128
130 RAM_DQM_A<4> 39 Distribute C502x caps along connector
B
RAM_DQS_A_P<4> 131 132
39 DQS4 VSS35
133 134 RAM_DATA_A<32>
VSS36 DQ38 39

39 DQ34 DQ39 39
RAM_DATA_A<33> 137 138

39 DQ35 VSS37
139 140 RAM_DATA_A<43>
VSS38 DQ44 39

39 DQ40 DQ45 39
RAM_DATA_A<46> 143 144

39 DQ41 VSS39
145 146 RAM_DQS_A_N<5>
VSS40 DQS5* 39
41 40 10 =PP1V8_PWRON_DDR2
DDR2 VREF 39 RAM_DQM_A<5> 147
149
DM5
VSS41
DQS5
VSS42
148
150
RAM_DQS_A_P<5> 39
1
R5001 ADD ONE 0.1UF PER SLOT 39 RAM_DATA_A<42> 151
DQ42 DQ46
152 RAM_DATA_A<41> 39
1K 39 RAM_DATA_A<44> 153
DQ43 DQ47
154 RAM_DATA_A<45> 39
1% 155 156
1/16W VSS43 VSS44
MF-LF 157 158
2 402 39 RAM_DATA_A<51> DQ48 DQ52 RAM_DATA_A<50> 39

RAM_VREF =RAM_VREF_A
39 DQ49 DQ53 39
40
VSS45 VSS46
MIN_LINE_WIDTH=0.38 mm 163 164
1 MIN_NECK_WIDTH=0.25 mm =RAM_VREF_B 41 NC NC_TEST CK1 RAM_CLKDDR_1_P 39
R5002 165
VSS47 CK1*
166 RAM_CLKDDR_1_N 39
1K RAM_DQS_A_N<6> 167 168
1% 39 DQS6* VSS48
1/16W 169 170
MF-LF 39 RAM_DQS_A_P<6> DQS6 DM6 RAM_DQM_A<6> 39
2 402 171 172
VSS49 VSS50
39 DQ50 DQ54 39
39 RAM_DATA_A<54> 175
177
DQ51 DQ55
176
178
RAM_DATA_A<53> 39 DDR2 SO-DIMM Slot A
VSS51 VSS52
A 39 RAM_DATA_A<60>
RAM_DATA_A<61>
179
181
DQ56 DQ60
180
182
RAM_DATA_A<63>
RAM_DATA_A<62>
39
SYNC_MASTER=MARIAS-MDIFF

SYNC_DATE=N/A
A
39 DQ57 DQ61 39
183 184
VSS53 VSS54
185 186 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
39 RAM_DQM_A<7> DM7 DQS7* RAM_DQS_A_N<7> 39 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
187 188 AGREES TO THE FOLLOWING
VSS55 DQS7 RAM_DQS_A_P<7> 39
39 RAM_DATA_A<59> DQ58 VSS56
191 192 II NOT TO REPRODUCE OR COPY IT
39 RAM_DATA_A<57> DQ59 DQ62 RAM_DATA_A<58> 39
193 194 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
VSS57 DQ63 RAM_DATA_A<56> 39
=I2C_SODIMM_SDA 195 196 SIZE DRAWING NUMBER REV.

41 8 SDA VSS58
051-6839 F
=I2C_SODIMM_SCL 197 198
41 8
41 10 =PP3V3_PWRON_VDDSPD 199
SCL
VDDSPD
SA0
SA1
200 ADDR=0XA0(WR)/0XA1(RD) APPLE COMPUTER INC.
D
202 SCALE SHT OF
NC
NONE 50 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
41 40 10 =PP1V8_PWRON_DDR2 201 NC =PP1V8_PWRON_DDR2 10 40 41
=RAM_VREF_B 1 2
41 40 VREF VSS0
3 CRITICAL 4
VSS1 DQ4 RAM_DATA_B<2> 39
39 RAM_DATA_B<3> 5
DQ0
J5200 DQ5
6 RAM_DATA_B<1> 39
RAM_DATA_B<0> 7 F-RT-SM 8
39 DQ1 VSS2
DDR2-SODIMM-REV
9 10 RAM_DQM_B<0>
VSS4 DM0 39
RAM_DQS_B_N<0> 11 12
39 DQS0* VSS5
RAM_DQS_B_P<0> 13 14 RAM_DATA_B<5>
39 DQS0 DQ6 39
15 16 RAM_DATA_B<4>
VSS6 DQ7 39
RAM_DATA_B<6> 17 18
39 DQ2 VSS7
RAM_DATA_B<7> 19 20 RAM_DATA_B<12>
39 DQ3 DQ12 39
21 22 RAM_DATA_B<11>
VSS8 DQ13 39
D 39 RAM_DATA_B<15> 23
25
DQ8 VSS9
24
26
D
RAM_DATA_B<14> RAM_DQM_B<1>
39
RAM_DQS_B_N<1>
27
29
DQ9
VSS10
DQS1*
DM1
VSS11
CK0
28
30 RAM_CLKDDR_2_P
39
DDR2 VREF
39
39 RAM_DQS_B_P<1> 31
DQS1 CK0*
32 RAM_CLKDDR_2_N
39
39
ONE 0.1UF PER SLOT
33 34
VSS12 VSS13
39 DQ10 DQ14 39
=RAM_VREF_B
41 40
39 DQ11 DQ15 39
39 40
VSS14
KEY
VSS15 1 C5201
41
VSS16 VSS17
42 0.1uF
20%
RAM_DATA_B<18> 43 44 RAM_DATA_B<22> 10V
2 CERM
39 DQ16 DQ20 39
RAM_DATA_B<20> 45 46 RAM_DATA_B<23> 402

39 DQ17 DQ21 39
47 48
VSS18 VSS19
RAM_DQS_B_N<2> 49 50 NC
39 DQS2* NC0
RAM_DQS_B_P<2> 51 52 RAM_DQM_B<2>
39 DQS2 DM2 39
53 54
VSS21 VSS22
39 DQ18 DQ22 39
39 DQ19 DQ23 39
59 60
VSS23 VSS24
39 DQ24 DQ28 39
39 DQ25 DQ29 39
39 RAM_DQM_B<3>
65
67
VSS25
DM3
VSS26
DQS3*
66
68 RAM_DQS_B_N<3> 39
DDR2 BYPASS
NC 69 70 RAM_DQS_B_P<3>
71
NC1
VSS27
DQS3
VSS28
72
39
SLOT "B"
C SLOT "B" 39
39
RAM_DATA_B<26>
RAM_DATA_B<27>
73
75
77
DQ26
DQ27
VSS29
DQ30
DQ31
VSS30
74
76
78
RAM_DATA_B<24>
RAM_DATA_B<28>
39
39 41 40 10 =PP1V8_PWRON_DDR2 C
LOWER/REV SLOT 39 RAM_CKE<2>
NC
79
81
83
CKE0
VDD0
NC2
NC/CKE1
VDD1
NC/A15
80
82
84 NC
RAM_CKE<3> 39
1 C5208
10UF
20%
1 C5209
10UF
20%
CUSTOMER SLOT 40 39
40 39
RAM_BA<2>
RAM_ADDR<12>
85
87
89
BA2
VDD2
A12
NC/A14
VDD3
A11
86
88
90
NC
RAM_ADDR<11> 39 40
6.3V
2 X5R
603
6.3V
2 X5R
603
40 39 A9 A7 39 40
40 39
95
A8 A6
96
39 40
1 C5210 1 C5211 1 C5212 1 C5213 1 C5214
VDD4 VDD5 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
RAM_ADDR<5> 97 98 RAM_ADDR<4> 20% 20% 20% 20% 20%
40 39 A5 A4 39 40
99 100 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
40 39 RAM_ADDR<3> A3 A2 RAM_ADDR<2> 39 40 402 402 402 402 402
40 39 A1 A0 39 40
103 104
VDD6 VDD7
RAM_ADDR<10> 105 106 RAM_BA<1>
40 39 A10/AP BA1 39 40
40 39 RAM_BA<0> 107
BA0 RAS*
108 RAM_RAS_L 39 40
1 C5215 1 C5216 1 C5217 1 C5218 1 C5219
40 39 RAM_WE_L 109
WE* S0*
110 RAM_CS_L<2> 39
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
20% 20% 20% 20% 20%
111
VDD8 VDD9
112 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
RAM_CAS_L 113 114 RAM_ODT<1> 402 402 402 402 402
40 39 CAS* ODT0 39
RAM_CS_L<3> 115 116 RAM_ADDR<13>

39 NC/S1* NC/A13 39 40
117 118
VDD10 VDD11
(ODT<1>) 119 120 NC
121
NC/ODT1 NC3
122
1 C5220 1 C5221 1 C5222 1 C5223
VSS31 VSS32 0.1uF 0.1uF 0.1uF 0.1uF
RAM_DATA_B<39> 123 124 RAM_DATA_B<36> 20% 20% 20% 20%
39 DQ32 DQ36 39
125 126 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM
39 RAM_DATA_B<38> DQ33 DQ37 RAM_DATA_B<35> 39 402 402 402 402
B 39 RAM_DQS_B_N<4>
127
129
VSS33
DQS4*
VSS34
DM4
128
130 RAM_DQM_B<4> 39 Distribute C522x caps along connector
B
RAM_DQS_B_P<4> 131 132
39 DQS4 VSS35
133 134 RAM_DATA_B<32>
VSS36 DQ38 39

39 DQ34 DQ39 39
RAM_DATA_B<33> 137 138

39 DQ35 VSS37
139 140 RAM_DATA_B<43>
VSS38 DQ44 39

39 DQ40 DQ45 39
RAM_DATA_B<46> 143 144

39 DQ41 VSS39
145 146 RAM_DQS_B_N<5>
VSS40 DQS5* 39
RAM_DQM_B<5> 147 148 RAM_DQS_B_P<5>

39 DM5 DQS5 39
149 150
VSS41 VSS42
39 DQ42 DQ46 39

39 DQ43 DQ47 39
155 156
VSS43 VSS44
39 DQ48 DQ52 39

39 DQ49 DQ53 39
161 162
VSS45 VSS46
NC 163 164 RAM_CLKDDR_3_P
NC_TEST CK1 39
165 166 RAM_CLKDDR_3_N
VSS47 CK1* 39
RAM_DQS_B_N<6> 167 168

39 DQS6* VSS48
RAM_DQS_B_P<6> 169 170 RAM_DQM_B<6>
39 DQS6 DM6 39
171 172
VSS49 VSS50
39 DQ50 DQ54 39
39 RAM_DATA_B<54> 175
177
DQ51 DQ55
176
178
RAM_DATA_B<53> 39 DDR2 SO-DIMM Slot B
VSS51 VSS52
A 39 RAM_DATA_B<60>
RAM_DATA_B<61>
179
181
DQ56 DQ60
180
182
RAM_DATA_B<63>
RAM_DATA_B<62>
39
SYNC_MASTER=MARIAS-MDIFF

SYNC_DATE=N/A
A
39 DQ57 DQ61 39
183 184
VSS53 VSS54
185 186 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
39 RAM_DQM_B<7> DM7 DQS7* RAM_DQS_B_N<7> 39 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
187 188 AGREES TO THE FOLLOWING
VSS55 DQS7 RAM_DQS_B_P<7> 39
39 RAM_DATA_B<59> DQ58 VSS56
191 192 II NOT TO REPRODUCE OR COPY IT
39 RAM_DATA_B<57> DQ59 DQ62 RAM_DATA_B<58> 39
193 194 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
VSS57 DQ63 RAM_DATA_B<56> 39
=I2C_SODIMM_SDA 195 196 SIZE DRAWING NUMBER REV.

40 8 SDA VSS58
051-6839 F
=I2C_SODIMM_SCL 197 198 =PP3V3_PWRON_VDDSPD
40 8
41 40 10 =PP3V3_PWRON_VDDSPD 199
SCL
VDDSPD
SA0
SA1
200 ADDR=0XA2(WR)/0XA3(RD)
10 40 41
APPLE COMPUTER INC.

D
202 SCALE SHT OF
NC
NONE 52 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
I1059 FB_A_CLK_0 RAM_DIFF RAM_DIFF FB_A_CLK_0_R FB_A_CLKDDR_0_P_R 48
I1060 (provided above) RAM_DIFF RAM_DIFF FB_A_CLK_0_R FB_A_CLKDDR_0_N_R 48
I1062 FB_A_CLK_1 RAM_DIFF RAM_DIFF FB_A_CLK_1_R FB_A_CLKDDR_1_P_R 48
I1061 (provided above) RAM_DIFF RAM_DIFF FB_A_CLK_1_R FB_A_CLKDDR_1_N_R 48
I1068 FB_A_ADDR_CTL RAM RAM FB_A_CKE_R 48
I1069 FB_A_ADDR_CTL RAM RAM FB_A_CS_L_R 48
I1071 FB_A_ADDR_CTL RAM RAM FB_A_ADDR_R<12..0> 48
I1072 FB_A_ADDR_CTL RAM RAM FB_A_BA_R<2..0> 48
D I1073
I1074
FB_A_ADDR_CTL
FB_A_ADDR_CTL
RAM
RAM
RAM
RAM
FB_A_RAS_L_R
FB_A_CAS_L_R
48
48
D
I1075 FB_A_ADDR_CTL RAM RAM FB_A_WE_L_R 48
I1076 FB_A_DQS0 RAM RAM FB_A_DQS_R<0> 48
I1085 FB_A_DQM0 RAM RAM FB_A_DQM_R<0> 48
I1093 FB_A_DQ0 RAM RAM FB_A_DQ_R<7..0> 48
C I1099
I1100
FB_A_DQ6
FB_A_DQ7
RAM
RAM
RAM
RAM
FB_A_DQ_R<55..48>
FB_A_DQ_R<63..56>
48
48
C
NET_TYPE
I1104 FB_B_CLK_0 RAM_DIFF RAM_DIFF FB_B_CLK_0_R FB_B_CLKDDR_0_P_R 48
I1103 (provided above) RAM_DIFF RAM_DIFF FB_B_CLK_0_R FB_B_CLKDDR_0_N_R 48
I1102 FB_B_CLK_1 RAM_DIFF RAM_DIFF FB_B_CLK_1_R FB_B_CLKDDR_1_P_R 48
I1101 (provided above) RAM_DIFF RAM_DIFF FB_B_CLK_1_R FB_B_CLKDDR_1_N_R 48
I1105 FB_B_ADDR_CTL RAM RAM FB_B_CKE_R 48
I1109 FB_B_ADDR_CTL RAM RAM FB_B_CS_L_R 48
I1108 FB_B_ADDR_CTL RAM RAM FB_B_ADDR_R<12..0> 48
I1107 FB_B_ADDR_CTL RAM RAM FB_B_BA_R<2..0> 48
I1106 FB_B_ADDR_CTL RAM RAM FB_B_RAS_L_R 48
I1110 FB_B_ADDR_CTL RAM RAM FB_B_CAS_L_R 48
I1114 FB_B_ADDR_CTL RAM RAM FB_B_WE_L_R 48
I1113 FB_B_DQS0 RAM RAM FB_B_DQS_R<0> 48
B I1119 FB_B_DQS7 RAM RAM FB_B_DQS_R<7> 48

B
I1123 FB_B_DQM0 RAM RAM FB_B_DQM_R<0> 48
I1125 FB_B_DQ0 RAM RAM FB_B_DQ_R<7..0> 48
M11 Frame Buffer Constraints


A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 55 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
AGP_CLK CLOCK CLOCK AGP_CLK66M_GPU_R 11 43
I2_AGP_FBCLK I2_FBCLK I2_FBCLK I2_AGP_FBCLK_OUT_R 43
I2_FBCLK I2_FBCLK I2_AGP_FBCLK_OUT 21 43
AGP_AD_0 AGP AGP AGP_AD<15..0> 43 44
AGP_AD_1 AGP AGP AGP_AD<31..16> 43 44 OMIT
AGP_AD_0 AGP AGP AGP_CBE_L<1..0> 43 44 U2100

AGP_AD_1 AGP AGP AGP_CBE_L<3..2> 43 44 I2
BGA
D AGP_AD_STB_0
AGP_AD_STB_0
AGP_STB
AGP_STB
AGP_STB
AGP_STB
AGP_AD_STB0
AGP_AD_STB0
AGP_AD_STB0_P
AGP_AD_STB0_N
43 44
43 44
AGP INTERFACE D
(9 of 14)
AGP_AD_STB_1 AGP_STB AGP_STB AGP_AD_STB1 AGP_AD_STB1_P 43 44
AGP_CLK_H AH19 AGP_CLK66M_GPU_R 11 43
AGP PULL-UPS/PULL DOWNS
AGP_AD_STB_1 AGP_STB AGP_STB AGP_AD_STB1 AGP_AD_STB1_N 43 44
(3.3V SIGNALS)
AGP_SBA<7..0> AGP_BUSY_L AP19 AT21 STOP_AGP_L =PP3V3_AGP
AGP_SBA AGP AGP 43 44 44 43 AGP_BUSY_L AGP_STP_L 43 44 44 10
AGP_SB_STB AGP_STB AGP_STB AGP_SB_STB AGP_SB_STB_P 43 44 (VDDAGP SIGNALS) R5610

AGP_SB_STB_N AGP_REQ_L AR19 AL16 AGP_GNT_L 10K
AGP_SB_STB AGP_STB AGP_STB AGP_SB_STB 43 44 44 43 6 AGP_REQ_L AGP_GNT_L 6 43 44
44 43 AGP_BUSY_L 1 2
AGP_ST AGP AGP AGP_ST<3..0> 43 44 5%

1/16W
44 43 AGP_PAR AT15
AGP_PAR_H AGP_AD_00_H AP6 AGP_AD<0> 43 44
R5611 MF-LF
AGP_CTL AGP AGP AGP_FRAME_L 6 43 44 AK16 AP4
10K 402
44 43 6 AGP_FRAME_L AGP_FRAME_L AGP_AD_01_H AGP_AD<1> 43 44 44 43 STOP_AGP_L 1 2
AGP_CTL AGP AGP AGP_DEVSEL_L 6 43 44
AM16 AR4
44 43 6 AGP_TRDY_L AGP_TRDY_L AGP_AD_02_H AGP_AD<2> 43 44 5%
AGP_CTL AGP AGP AGP_IRDY_L 6 43 44
AR15 AT5
1/16W
R5620
44 43 6 AGP_IRDY_L AGP_IRDY_L AGP_AD_03_H AGP_AD<3> 43 44 MF-LF
AGP_CTL AGP AGP AGP_TRDY_L 6 43 44 AT14 AN7
402 10K
44 43 6 AGP_STOP_L AGP_STOP_L AGP_AD_04_H AGP_AD<4> 43 44 44 22 AGP_INT_L 1 2
AGP_CTL AGP AGP AGP_STOP_L 6 43 44
AP15 AL13
44 43 6 AGP_DEVSEL_L AGP_DEVSEL_L AGP_AD_05_H AGP_AD<5> 43 44 5%
AGP_PAR AGP AGP AGP_PAR 43 44
AN19 AR6
1/16W
43 AGP_PIPE_L AGP_PIPE_L AGP_AD_06_H AGP_AD<6> 43 44 MF-LF
AGP_DEV_CTL AGP AGP AGP_PIPE_L 43 AT18 AT6
402
44 43 AGP_WBF_L AGP_WBF_L AGP_AD_07_H AGP_AD<7> 43 44
AGP_DEV_CTL AGP AGP AGP_WBF_L 43 44 AM19 AT3
44 43 6 AGP_RBF_L AGP_RBF_L AGP_CBE_0_L AGP_CBE_L<0> 43 44
AGP_DEV_CTL AGP AGP AGP_RBF_L 6 43 44
47 44 43 10 =PP1V5_AGP
AGP_REQ_L AGP_SBA<0> AL18 AN9 AGP_AD<8>
AGP AGP 6 43 44 44 43 AGP_SBA_0_H AGP_AD_08_H 43 44
AGP AGP AGP_GNT_L 6 43 44 44 43 AGP_SBA<1> AR18

AGP_SBA_1_H AGP_AD_09_H AP7 AGP_AD<9> 43 44
RP5610
10K
AGP_SBA<2> AP18 AR7 AGP_AD<10> =RP5610P4 4 5
44 43 AGP_SBA_2_H AGP_AD_10_H 43 44 6
AGP_SBA<3> AN18 AT7 AGP_AD<11>

44 43 AGP_SBA_3_H AGP_AD_11_H 43 44 5%
Page Notes 44 43 AGP_SBA<4>

AGP_SBA<5>
AM18
AK18
AGP_SBA_4_H AGP_AD_12_H AN10
AR9
AGP_AD<12>
AGP_AD<13>
43 44
=RP5610P2
1/16W
SM-LF
RP5610
2
10K
7
44 43 AGP_SBA_5_H AGP_AD_13_H 43 44 6
Power aliases required by this page: AT16 AT8
44 43 AGP_SBA<6> AGP_SBA_6_H AGP_AD_14_H AGP_AD<14> 43 44 5%
- =PP3V3_AGP AT17 AT9 RP5610 1/16W
C - =PP1V5_AGP
- =PP1V5_I2_AGP
44 43 AGP_SBA<7> AGP_SBA_7_H AGP_AD_15_H
AGP_CBE_1_L AP9
AGP_AD<15>
AGP_CBE_L<1>
43 44
43 44 6 =RP5610P3 3
10K
6
SM-LF
C
44 43 AGP_SB_STB_P AH16 AGP_SB_STB_P One resistor for each of: 5%
AGP_SB_STB_N AJ16 AH9 AGP_AD_STB0_P
1/16W RP5611
- =I2_AGP_VREF - VRef from graphics
AGP I/O DECOUPLING 44 43 AGP_SB_STB_N AGP_AD_STB0_P
AGP_AD_STB0_N AJ9 AGP_AD_STB0_N
43 44
43 44
- AGP_RBF_L
- AGP_GNT_L 6 =RP5611P2
SM-LF
2
10K
7
1 X 10uF (0603)
card or on-board graphics controller 10 =PP1V5_I2_AGP (25 Balls on I2) - AGP_FRAME_L 5%
25 X 1uF (0402) AD15 AM12 AGP_AD<16> RP5611 1/16W
- =I2_AGP_FBCLK_IN - AGP feedback clock VDDAGP_0 AGP_AD_16_H 43 44 - AGP_REQ_L 10K SM-LF
AD17 AP10 AGP_AD<17> =RP5611P3 3 6
input. Length should match that of VDDAGP_1 AGP_AD_17_H 43 44 - AGP_STOP_L 6
AD19 AN12
clock from I2 to AGP device. C5649 1 1 C5650 1 C5651 1 C5652 1 C5653 1 C5654 1 C5655 1 C5656 VDDAGP_2 AGP_AD_18_H AGP_AD<18> 43 44 - AGP_DEVSEL_L 5%
10UF 1uF 1uF 1uF 1uF 1uF 1uF 1uF AE13
VDDAGP_3 AGP_AD_19_H AT10 AGP_AD<19> 43 44 - AGP_IRDY_L
1/16W
SM-LF
RP5611
BOM options provided by this page: 20% 10% 10% 10% 10% 10% 10% 10% 10K
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V AE16 AK15 AGP_AD<20> =RP5611P4 4 5
X5R 2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM VDDAGP_4 AGP_AD_20_H 43 44 - AGP_TRDY_L 6
(NONE) 603 402 402 402 402 402 402 402 AE18 AM13
VDDAGP_5 AGP_AD_21_H AGP_AD<21> 43 44 5%
NOTE: I2 implements an AGP 4x bridge. AF14

VDDAGP_6 AGP_AD_22_H AP12 AGP_AD<22> RP5611 1/16W
43 44
10K SM-LF
AG13 AT11 AGP_AD<23> =RP5611P1 1 8
AGP 8x signals are not provided VDDAGP_7 AGP_AD_23_H 43 44 6
AG16 AR10 AGP_CBE_L<2>
by this page. VDDAGP_8 AGP_CBE_2_L 43 44 5%
1
C5657 1
C5658 1
C5659 1
C5660 1
C5661 1
C5662 1
C5663 AH11 1/16W RP5610
1uF 1uF 1uF 1uF 1uF 1uF 1uF VDDAGP_9 SM-LF
10K
10% 10% 10% 10% 10% 10% 10% AH13 AL15 AGP_AD<24> =RP5610P1 1 8
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V VDDAGP_10 AGP_AD_24_H 43 44 6
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM AL11 AN13
402 402 402 402 402 402 402 VDDAGP_11 AGP_AD_25_H AGP_AD<25> 43 44 5%
1/16W
AL12
VDDAGP_12 AGP_AD_26_H AR12 AGP_AD<26> 43 44
R5612 SM-LF
AL14 AT12
10K
VDDAGP_13 AGP_AD_27_H AGP_AD<27> 43 44 44 43 AGP_WBF_L 1 2
AL17 AR13 AGP_AD<28>
VDDAGP_14 AGP_AD_28_H 43 44 5%
1/16W
1
C5664 1
C5665 1
C5666 1
C5667 1
C5668 1
C5669 1
C5670 AL20
VDDAGP_15 AGP_AD_29_H AT13 AGP_AD<29> 43 44 MF-LF R5613
1uF 1uF 1uF 1uF 1uF 1uF 1uF AL8 AM15
402 10K
10% 10% 10% 10% 10% 10% 10%
VDDAGP_16 AGP_AD_30_H AGP_AD<30> 43 44 43 AGP_PIPE_L 1 2
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V AL9 AN15 AGP_AD<31>
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM VDDAGP_17 AGP_AD_31_H 43 44 5%
1/16W
402 402 402 402 402 402 402 AP11
VDDAGP_18 AGP_CBE_3_L AP13 AGP_CBE_L<3> 43 44
R5614 MF-LF
AP14
10K 402
VDDAGP_19 44 43 AGP_AD_STB0_P 1 2
AP17 AK13 AGP_AD_STB1_P
VDDAGP_20 AGP_AD_STB1_P 43 44 5%
B 1 C5671 1 C5672 1 C5673 1 C5674

AP20
AP3
VDDAGP_21 AGP_AD_STB1_N AJ13 AGP_AD_STB1_N 43 44
1/16W
MF-LF
402
R5615
10K
B
1uF 1uF 1uF 1uF VDDAGP_22 44 43 AGP_AD_STB1_P 1 2
10% 10% 10% 10% AP5 AR16 AGP_ST<0>
6.3V 6.3V 6.3V 6.3V VDDAGP_23 AGP_ST_0_H 43 44 5%
1/16W
2 CERM
402
2 CERM
402
2 CERM
402
2 CERM
402
AP8
VDDAGP_24 AGP_ST_1_H AN16 AGP_ST<1> 43 44
R5616 MF-LF
AP16
10K 402
AGP_ST_2_H AGP_ST<2> 43 44 44 43 AGP_SB_STB_P 1 2
5%
1/16W
MF-LF
402
=I2_AGP_VREF AD18
11 AGP_VREF_0_H
R5617
10K
44 43 AGP_AD_STB0_N 1 2
47 44 43 10 =PP1V5_AGP
5%
1/16W
R5618 MF-LF
1 10K 402
R5600 44 43 AGP_AD_STB1_N 1 2
60.4
1% 5%
1/16W
1/16W
MF-LF MF-LF R5619
2 402
402 10K
44 43 AGP_SB_STB_N 1 2
I2_AGP_PVTREF AJ18
AGP_PVTREF_H 5%
1/16W
R5605 MF-LF
AM10 AM9
22 402
21 =I2_AGP_FBCLK_IN AGP_FB_CLK_IN_H AGP_FBCLK_OUT_H 43 I2_AGP_FBCLK_OUT_R 1 2 I2_AGP_FBCLK_OUT 21 43
5%
1/16W
1.5V IN 1.5V OUT MF-LF
402
I2 AGP Interface

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 56 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
I798 CLOCK CLOCK AGP_CLK66M_GPU 11 44
Page Notes
- =PP3V3_AGP
- =PP1V5_AGP
D - =AGP_VREF - VRef divider output for

both GPU and NB
D
- =AGP_GPU_RESET_L - Active low reset for GPU

(NONE)
OMIT
NOTE: AGP 8x signals are not provided
by this page.
CRITICAL R5700
=AGP_GPU_RESET_L 1
47 2
U5700 11
BGA 5%
1/16W
43 AGP_AD<0> H29 AD_0 M11P MF-LF
(1 OF 8) 402
43 AGP_AD<1> H28 AD_1
43 AGP_AD<2> J29 AD_2
43 AGP_AD<3> J28 AD_3
43 AGP_AD<4> K29 AD_4 PCICLK AG30 AGP_CLK66M_GPU 11 44
43 AGP_AD<5> K28 AD_5

AGP_AD<6> L29 AG28 AGP_ATI_RESET_L
AGP/PCI INTERFACE
43 AD_6 RST*
43 AGP_AD<7> L28 AD_7
43 AGP_AD<8> N28 AD_8 INTA* AE26 AGP_INT_L 22 43
43 AGP_AD<9> P29 AD_9

43 AGP_AD<10> P28 AD_10 GNT* AD26 AGP_GNT_L 6 43
43 AGP_AD<11> R29 AD_11 REQ* AF28 AGP_REQ_L 6 43
43 AGP_AD<12> R28 AD_12

43 AGP_AD<13> T29 AD_13
43 AGP_AD<14> T28 AD_14
FRAME* W28 AGP_FRAME_L 6 43
43 AGP_AD<15> U29 AD_15
TRDY* V28 AGP_TRDY_L 6 43
43 AGP_AD<16> N25 AD_16
C 43
43
AGP_AD<17>
AGP_AD<18>
R26
P25
AD_17
AD_18
IRDY*
DEVSEL*
W29
V29
AGP_IRDY_L
AGP_DEVSEL_L
6 43
6 43
C
STOP* N26 AGP_STOP_L 6 43
43 AGP_AD<19> R27 AD_19
PAR M25 AGP_PAR 43
43 AGP_AD<20> R25 AD_20
43 AGP_AD<21> T25 AD_21
44 43 10 =PP3V3_AGP 47 44 43 10 =PP1V5_AGP
43 AGP_AD<22> T26 AD_22
43 AGP_AD<23> U25 AD_23
R57201 R57251 1
R5726 43 AGP_AD<24> V27 AD_24 C_BE_0* N29 AGP_CBE_L<0> 43
10K 47K 47K AGP_AD<25> AGP_CBE_L<1>
5% 5% 5% 43 W26 AD_25 C_BE_1* U28 43
1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF 43 AGP_AD<26> W25 AD_26 C_BE_2* P26 AGP_CBE_L<2> 43
402 2 402 2 2 402 43 AGP_AD<27> Y26 AD_27 C_BE_3* U26 AGP_CBE_L<3> 43
43 AGP_AD<28> Y25 AD_28

43 AGP_AD<29> AA26 AD_29
43 AGP_AD<30> AA25 AD_30
43 AGP_AD<31> AA27 AD_31
AGP ONLY RBF* AE29 AGP_RBF_L 6 43
ATI_DBI_HI_PU AB25 DBI_HI WBF* AC26 AGP_WBF_L 43
ATI_DBI_LO_PU AB26 DBI_LO AGP 8X

ST_0 AF29 AGP_ST<0> 43
AGP8X_DET_PU AC25 AGP8X_DET* ST_1 AD27 AGP_ST<1> 43
ST_2 AE28 AGP_ST<2> 43
47 44 43 10 =PP1V5_AGP 43 AGP_SBA<0> AD28 SBA_0

SB_STBF AB29 AGP_SB_STB_P 43
43 AGP_SBA<1> AD29 SBA_1
SB_STBS AB28 AGP_SB_STB_N 43
R57211 43 AGP_SBA<2> AC28 SBA_2 44 43 10 =PP3V3_AGP
47 44 43 10 =PP1V5_AGP
47 43 AGP_SBA<3> AC29 SBA_3
AGP_AD_STB0_P
1% AD_STBF_0 M28 43
1
1/16W 43 AGP_SBA<4> AA28 SBA_4 R5722
B MF-LF
402 2 43 AGP_SBA<5> AA29 SBA_5
AD_STBS_0 M29 AGP_AD_STB0_N 43
20K
5% CONNECT TO GPU AGP REF
1
R5730
1K
B
43 AGP_SBA<6> Y28 SBA_6 1/16W 1%
AD_STBF_1 V25 AGP_AD_STB1_P 43 MF-LF CAN ALSO CONNECT TO NB 1/16W
43 AGP_SBA<7> Y29 SBA_7 2 402 IF CHIPS ARE CO-LOCATED MF-LF
AD_STBS_1 V26 AGP_AD_STB1_N 43
2 402
GPU_AGPTEST M27 AGPTEST AGPREF M26 =GPU_AGP_VREF 11 11 =AGP_VREF
AH30 STOP_AGP_L 1
STP_AGP* 43
C5732 1 1 C5731 R5731
AGP_BUSY* AH29 AGP_BUSY_L 43
0.1uF 0.1uF 1K
10% 10% 1%
16V 2 1/16W
SUS_STAT* AG26 AGP_SUS_STAT_L_PU X5R 2 16V
X5R MF-LF
402 402 2 402
PLACE C5731 AT GPU

PLACE C5732 AT NB
PLACE RESISTORS MIDWAY BETWEEN
GPU (M11) AGP Interface


A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 57 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PPVIN_LTC1778_GPU
- =PP5V_PWRON_LTC1778_GPU_EXTVCC
- =PPVCORE_GPU_REG

- =GPUVCORE_PGOOD - Active high Power Good
signal for power sequencing

- GPU_PWRPLAY
D NOTE: Implements "Power Miser" feature
D
for ATI GPUs
GPU VCORE SUPPLY
10 =PP5V_PWRON_LTC1778_GPU_EXTVCC 10 =PPVIN_LTC1778_GPU
C5810 1 C5811 1
R58221 1
R5820 1
R5821 4.7uF
20%
4.7uF
20%
100K 1 576K 5 25V 25V
5% 5% 1% CERM 2 CERM 2
1/16W 1/10W 1/16W 1206 1206
MF-LF MF-LF MF-LF
402 2 2 603 2 402 CRITICAL
Q5800
PPVOUT_1778_VCC 4 SI7860DP
SO-8-PWRPK-LF
VOLTAGE=5V
MIN_LINE_WIDTH=0.38 mm 10 =PPVCORE_GPU_REG
PPVIN_1778_VIN 1 CRITICAL
NO STUFF
D5823
3
1 VOLTAGE=12.8V 1 2 3
R5828 1R5826 1 C5825 MIN_LINE_WIDTH=0.38SOD-123
MIN_NECK_WIDTH=0.25
mm
mm
2
0 63.4K MBR0540XXG GPU_VCORE_SW
5% 1% 4.7UF
20% 2
1/16W 1/16W
2 10V C5820 1 L5800
1778_BST_RC
MF-LF
2 402
MF-LF
2 402
CERM
1206 0.1uF
R5823 2.1uH-11A
20% 1
2.2 2 SM
25V
CERM 2 5%
CRITICAL
9 11 10
603 1/10W
MF-LF
1
C5802 1 C5804
EXT INT VIN 603 470uF 0.1uF
20% 20%
VCC VCC 10V
2 2.5V 2 CERM
U5800 C5823 1
2 TANT
402
C GPUVCORE_SHDN_L
LTC1778
SSOP-LF
1 RUN/SS ION 7 1778_ION
0.1uF
20%
25V
D5800
SMB
7343-H2.9
C
26
CERM 2
5 ITHCRITICAL
603
5
B340LBXF R58801
1778_ITH B00ST 16 1778_BST 1 6.34K
CRITICAL CRITICAL 1% Ra
TG 15 1778_TG 1/16W
R58301 1778_VRNG 3 VRNG
SW 14
CRITICAL C5801 1 C5803 1 C5805 1 MF-LF
402 2
20.0K Q5801 22uF 470uF 0.1uF
1% 1778_FCB 4 FCB 20% 20% 20%
1/16W SI7892DP 10V 2.5V 2 10V
CERM 2 CERM 2
MF-LF BG 12 1778_BG 4
SO-8-PWRPK-LF 1210
TANT
7343-H2.9 402
402 2 NO STUFF 2 PGOOD
26 =GPUVCORE_PGOOD NO STUFF
1 1 VFB 8
1778_ITH_RC 1 C5831 R5829 R5827 1 C5822 1778_VFB
C5824 1
220pF 0
5%
0
5% 0.1uF SGND PGND
0.0022UF 1 2 3 R58831
C5830 1 5%
2 25V
1/16W 1/16W 20%
2 10V
6 13 10%
50V 20.0K Rb
470pF CERM MF-LF MF-LF CERM CERM 2 1%
10% 402 2 402 2 402 402 402 1/16W
MF-LF
50V
CERM 2 XW5800
SM
402 2
402
1778_GND 1 2
VOLTAGE=0V
GPU_PWRPLAY
1
R5881
18.2K
1%
1/16W
MF-LF
402 2
Rc HIGH_GPU_VCORE_DIV
GPU_PWRPLAY GPU_PWRPLAY
B 10 =PP5V_PWRON_GPUVCORE_PWRPLAY
R5882 1 C5882
0.1uF
1 B
WHEN VCORE_CNTL HIGH => 1.307V GPU_PWRPLAY 1.82K
1% 20%
1 10V
1.307V = 0.8V * (1 + Ra*(Rc+Rb) / (Rc*Rb)) R5884 1/16W
MF-LF
CERM
402
2
100K 402 2
WHEN VCORE_CNTL LOW => 1.054V 5%
1/16W
1.054V = 0.8V * (1 + Ra / Rb) MF-LF HIGH_GPU_VCORE_L
402 2
GPU_VCORE_HI 3 GPU_PWRPLAY
6 GPU_PWRPLAY
D
Q5884
2N7002DW-X-F
GPU_PWRPLAY 5 SOT-363
R5885
D Q5884 G S
2N7002DW-X-F
GPU_VCORE_HI_L 1
10K 2 GPU_VCORE_HI_L_RC 2 G S
SOT-363 4
51
5% NO STUFF
1/16W 1
MF-LF
402
C5885 1
0.1uF
20%
10V
CERM 2
402
GPU VCore Supply


A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 58 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PP1V5_GPU_VDD15
- =PP1VR1V3_GPU_VCORE

(NONE)

(NONE)
H23
H27
D H4
GPU VCORE - 1.3V/1.05V Internal I/O - 1.3V/1.05V D
OMIT H8
CRITICAL H9
K1
L5990
U5700 60-OHM-EMI
K23
M11P 10 =PP1V05R1V3_GPU_VCORE 1 2
BGA K24
SM
K27
(6 OF 8)
K30 AC13
K7 AC15
K8
1 C5900 1 C5901 1 C5902 1 C5903 1 C5904 AC17
OMIT
10UF 10UF 0.22UF 0.22UF 0.22UF CRITICAL
L4 20% 20% 10% 10% 10% AD13
6.3V 6.3V 6.3V 6.3V 6.3V
M16
2 X5R
603
2 X5R
603
2 CERM-X5R
402
2 CERM-X5R
402
2 CERM-X5R
402 AD15 U5700
HOST GROUND
M30 M12 M11P
M7 M13 BGA
M8 1 C5905 1 C5906 1 C5907 1 C5908 1 C5909 M14 (8 OF 8)
M15 PP1VR1V3_GPU_VDDCI
N15 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF M17 VOLTAGE=1.3V
10% 10% 10% 10% 10% R19 MIN_LINE_WIDTH=0.5 mm
N16 6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R M18 VDDCI T12
1 C5990 1 C5991 MIN_NECK_WIDTH=0.25 mm
N23 402 402 402 402 402 M19 10UF 0.01uF
W16 20% 20%
N24 N12 2 6.3V
X5R 2 16V
CERM
N27 N13 603 402
P15
1 C5910 1 C5911 1 C5912 1 C5913 1 C5914 N14
0.22UF 0.22UF 0.22UF 0.22UF 0.22UF
P16 10% 10% 10% 10% 10% N17
P4
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R N18
1 C5992 1 C5993 1 C5994
402 402 402 402 402 0.01uF 0.01uF 0.01uF
R12 N19 VDDC 20% 20% 20%
16V
2 16V
16V
2 CERM CERM 2 CERM
R13 P12 402 402 402
R14 1 C5915 1 C5916 1 C5917 1 C5918 1 C5919 P13
0.22UF 0.22UF 0.22UF 0.22UF 0.22UF
C VSS
R15
R16
10%
6.3V
2 CERM-X5R
10%
6.3V
2 CERM-X5R
10%
6.3V
2 CERM-X5R
10%
6.3V
2 CERM-X5R
10%
6.3V
2 CERM-X5R
P14
P17
C
R17 402 402 402 402 402 P18
R18 P19 AC11
R23 U12 AC20
R24
1 C5920 1 C5921 1 C5922 1 C5923 1 C5924 U13 H11
0.22UF 0.22UF 0.22UF 0.22UF 0.22UF
R30 10% 10% 10% 10% 10% U14 H20
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V VDD15
R7 CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R U17 L23
402 402 402 402 402
R8 U18 P8
T1 U19 Y23
CORE GND T13 V12 Y8
T14 V13
T15 V14
T16 V17
T17 V18
T18 Internal I/O - 1.5V V19
I/O GROUND
T19 W12
T27 W13
U15 10 =PP1V5_GPU_VDD15 W14
U16 W17
U23 W18
1
2
5
6
A10
U4 W19
SI3446DV
A16
Q5950
CRITICAL
U8
TSOP-LF
A2
V15
A22
V16
A29
V30
AA30
W15
B AB1
L5950 B
4
W23
AB23 FERR-220-OHM
W24
AB24 1 2 (500mA)
W27 26 GPUVDD15_EN PP1V5_GPU_VDD15_F PP1V5_GPU_VDD15
AB27 VOLTAGE=1.5V VOLTAGE=1.5V
W7 MIN_LINE_WIDTH=0.5 mm 0805 MIN_LINE_WIDTH=0.5 mm
AB4 MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm
AB7
W8
C5950 1
1 C5951 1 C5952 1 C5953 1 C5954 1 C5955
Y4 0.01uF 0.01uF 0.01uF 0.01uF 10UF
AB8 1000pF 20% 20% 20% 20% 20%
10%
25V 2 2 16V
CERM 2 16V
CERM 2 16V
CERM 2 16V
CERM 2 6.3V
X5R
AC12 X7R 402 402 402 402 603
AC14 402
AC16
AC18
AC4 1 C5956 1 C5957 1 C5958 1 C5959
AD12 0.01uF 0.01uF 0.01uF 0.01uF
20% 20% 20% 20%
AD16 VSS 2 16V
CERM 2 16V
CERM 2 16V
CERM 2 16V
CERM
AD18 402 402 402 402
AD25
AD30
AE27
AG11
AG15
AG18
AG22
AG27
AG5
AG9 GPU (M11) Core Power
AJ1
A AJ30
AK2
SYNC_MASTER=MARIAS

A
AK29
C1 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
C28
C3
C30
VSS III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
D10
D12
D15
D18
D21
D24
D25
D27
D4
D6
D9
E4
F27
G12
G16
G18
G21
G24
G9
H12
H14
H16
H18
H21
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 59 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes 10 =PP3V3_GPU_VDDR3
L6000
- =PP1V8R2V5_GPU_FB_VIO - =PP1V8_GPU_PANEL_IO FERR-10-OHM-500MA
- =PP3V3_GPU_VDDR3 - =PP1V8_GPU_LVDS_PLL 2 1
AC19 51 PP3V3_GPU_VDDR3
- =PP1V5_GPU_DVO - =PP2V5_GPU_LVDS_IO SM
OMIT AC21 VOLTAGE=3.3V
- =PP1V8_GPU_DVO - =PP2V5_GPU_LVDS_IO
CRITICAL AC22
1 C6000 1 C6001 1 C6002 1 C6003 MIN_LINE_WIDTH=0.38 mm
- =PP1V5R3V3_DVO_VREF - =PP1V5_AGP 10UF 0.1uF 0.1uF 0.1uF
AC8 20% 20% 20% 20%
U5700 VDDR3 AD19
2 6.3V
X5R 2 10V
CERM 2 10V
CERM 2 10V
CERM
M11P 603 402 402 402
(NONE) A15 BGA AD21

A21
(7 OF 8)
AD22 GPIO - 3.3V
D - DVO_1V5 - GPU_LVDDR_2V5
A28
A3
AD7 1 C6004
0.1uF
20%
1 C6005
0.1uF
20%
1 C6006
0.1uF
20%
(Max Current varies, depends on usage)
D
- DVO_1V8 - GPU_LVDDR_2V8
2 10V 2 10V
A9 10V
CERM CERM 2 CERM
NOTE: Implements a low-swing DVO bus only AA1 402 402 402
AA4
AA7
AA8
AC10
AD4
AC9
B1
B30 VDDR4 AD10 1 C6010
10UF
1 C6011
0.1uF
1 C6012
0.1uF
1 C6013
0.1uF
DVO I/O (EXT.TMDS) - 1.5V/1.8V
AD9 20% 20% 20% 20%
D11
2 6.3V 2 10V
AG7 10V 10V
X5R CERM 2 CERM 2 CERM
D13 603 402 402 402
D14 10 =PP1V8_GPU_DVO
D17
DVO_1V8
D19
L6010
D20 1 C6014 1 C6015 FERR-10-OHM-500MA
D23 0.1uF 0.1uF
20% 20% 53 PP1V5R3V3_GPU_VDDR4 1 2
D26 2 10V
CERM 2 10V
CERM MAKE_BASE=TRUE
402 402 VOLTAGE=1.8V SM
D5 MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm 10 =PP1V5_GPU_DVO
D8
E27 DVO_1V5
44 43 10 =PP1V5_AGP
F4 L6011
L6050
MEMORY I/O - 1.8V/2.5V G10
G13 VDDR1
L6020
FERR-10-OHM-500MA
1 2
FERR-10-OHM-500MA
FERR-220-OHM G15 (20mA) SM
(1200mA) AA23 PP1V5_GPU_AGP 1 2
48 10 =PP1V8R2V5_GPU_FB_VIO1 2 PP1V8R2V5_GPU_FB_VIO G19 VOLTAGE=1.5V =PP1V5R3V3_DVO_VREF 54
0805 VOLTAGE=1.8V AA24 MIN_LINE_WIDTH=0.5 mmSM
MIN_LINE_WIDTH=0.5 mm G22 MIN_NECK_WIDTH=0.25 mm
AB30 1 C6020 1 C6021 1 C6022 1 C6023 1 C6024 C
C 1 C6050
10UF
1 C6051
10UF
1 C6052
0.1uF
1 C6053
0.1uF
1 C6054
0.1uF
G27
G7
AC23 0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
10UF
20% AGP 4X I/O - 1.5V
20% 20% 20% 20% 20% AC27 10V
2 CERM
10V
2 CERM 10V
2 CERM
10V
2 CERM 6.3V
2 X5R
2 6.3V 2 6.3V
10V 10V
X5R X5R 2 CERM 2 CERM 2 10V
CERM H10 402 402 402 402 603
603 603 402 402 402 AE30
H13
AF27
H15
J30
H17
M23
H19
1 C6055 1 C6056 1 C6057 1 C6058 1 C6059 H22 VDDP M24 1 C6025 1 C6026 1 C6027 1 C6028 1 C6029
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF N30 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
20% 20% 20% 20% 20% J1 20% 20% 20% 20% 20%
10V
2 10V
10V 10V
2 10V 2 16V
16V 16V 16V
2 CERM CERM 2 CERM 2 CERM CERM P23 CERM 2 CERM 2 CERM 2 CERM 2 16V
CERM
402 402 402 402 402 J23 402 402 402 402 402 51 =PP1V8_GPU_LVDS_PLL
P27
J24
T23
J4
T24
(40mA) L6048
J7 FERR-220-OHM
T30
1 C6060 1 C6061 1 C6062 1 C6063 1 C6064 J8
U27
PP1V8_GPU_LVDS_PLL
VOLTAGE=1.8V
1 2
0.1uF 0.1uF 0.01uF 0.01uF 0.01uF L27 MIN_LINE_WIDTH=0.38 mm 0402
20% 20% 20% 20% 20% V23 MIN_NECK_WIDTH=0.25 mm
2 10V
CERM 2 10V
CERM 2 16V
CERM 2 16V
CERM 2 16V
CERM L8
V24
1 C6030 1 C6031 1 C6032 1 C6033 1 C6048 1 C6049
402 402 402 402 402 M4
N4
W30
Y27
0.1uF
20%
2 10V
CERM
0.1uF
20%
2 10V
CERM
0.1uF
20%
2 10V
CERM
0.1uF
20%
2 10V
CERM
10UF
20%
2 6.3V
X5R
0.01uF
20%
2 16V
CERM
LVDS PLL - 1.8V
N7 402 402 402 402 603 402
N8
L6043
1 C6065 1 C6066 1 C6067 1 C6068 1 C6069 FERR-220-OHM
10UF 10UF 0.1uF 0.1uF 0.1uF R1
20% 20% 20% 20% 20% 10 =PP1V8_GPU_PANEL_IO 1 2 PP1V8_GPU_PANEL_IO 53
R4 VOLTAGE=1.8V
2 6.3V
X5R 2 6.3V
X5R 2 10V
CERM 2 10V
CERM 2 10V
CERM
603 603 402 402 402 T4 LPVDD AJ20 MIN_NECK_WIDTH=0.25 mm
T7
T8
LVDDR_18_0 AE15
LVDS I/O - 1.8V (180mA) ALSO TXVDDR
V4
LVDDR_18_1 AF21
B 1 C6070 1 C6071 1 C6072 1 C6073 1 C6074 V7 1 C6043 1 C6044 1 C6045 1 C6046 1 C6047 B
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF V8
20% 20% 20% 20% 20% 10UF 0.1uF 0.1uF 0.01uF 0.01uF
2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM 2 10V
CERM LVDDR_25_0 AE17 20% 20% 20% 20% 20%
402 402 402 402 402 2 6.3V
X5R 2 10V
CERM 2 10V
CERM 2 16V
CERM 2 16V
CERM
LVDDR_25_1 AE20 603 402 402 402 402
10 =PP2V5_GPU_LVDS_IO
GPU_LVDDR_2V5
1 C6075 1 C6076 1 C6077 1 C6078 1 C6079 L6040
0.1uF 0.1uF 0.01uF 0.01uF 0.01uF FERR-10-OHM-500MA
20% 20% 20% 20% 20% (350mA)
10V 10V 16V 16V 16V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 1 2
402 402 402 402 402
PP2V5R2V8_GPU_LVDS_IO
VOLTAGE=2.8V SM
VDDRH1 N6 MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm 10 =PP2V8_GPU_LVDS_IO
VDDRH0 F18 1 C6040 1 C6041 1 C6042
10UF GPU_LVDDR_2V8
1 C6095 1 C6096 1 C6097 20%
0.01uF
20%
0.01uF
20% L6041
1 C6080 1 C6081 1 C6082 1 C6083 1 C6084 10UF 0.01uF 0.01uF 2 6.3V
X5R 2 16V
CERM 2 16V
CERM FERR-10-OHM-500MA
VSSRH0 F19 20% 20% 20%
10UF 10UF 0.1uF 0.1uF 0.1uF 2 6.3V
X5R 2 16V
CERM 2 16V
CERM
603 402 402
20% 20% 20% 20% 20% VSSRH1 M6 1 2
2 6.3V 2 6.3V 2 10V 2 10V 2 10V
603 402 402
X5R X5R CERM CERM CERM SM
603 603 402 402 402
LVDS I/O - 2.5V/2.8V

1 C6085 1 C6086 1 C6087 1 C6088 1 C6089
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
20% 20% 20% 20% 20%
10V 10V 10V 10V 10V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
402 402 402 402 402
GPU (M11) I/O Power

A 1 C6090
0.1uF
1 C6091
0.1uF
1 C6092
0.01uF
1 C6093
0.01uF
1 C6094
0.01uF
SYNC_MASTER=MARIAS

A
20% 20% 20% 20% 20%
2 10V
CERM 2 10V
CERM 2 16V
CERM 2 16V
CERM 2 16V
CERM
402 402 402 402 402 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
L6095 II NOT TO REPRODUCE OR COPY IT
FERR-220-OHM III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
1 2 PP1V8_GPU_VDD_MEM_CLK
0402 VOLTAGE=1.8V SIZE DRAWING NUMBER REV.
APPLE COMPUTER INC.
D 051-6839 F
SCALE SHT OF
NONE 60 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
GPU Frame Buffer Series Term
- =PP1V8R2V5_GPU_FB_VIO
- =PP1V8_GPU_MEMVMODE

(NONE) 48 42 FB_A_ADDR_R<11..0>
NO_TEST=YES
RP6101 FB_A_ADDR<11..0>
NO_TEST=YES
49 48 42 FB_B_ADDR_R<11..0>
NO_TEST=YES
RP6151 FB_B_ADDR<11..0>
NO_TEST=YES
50
0 0
BOM options provided by this page: 0 1 8 0 0 2 7 0
- GPU_MEMIO_1V8 5% 5%
- GPU_MEMIO_2V5
1/16W
SM-LF
RP6102 1/16W
SM-LF
RP6152
0 0
1 2 7 1 1 4 5 1
D OMIT OMIT RP6101 5%

1/16W RP6152 5%
1/16W
D
0 SM-LF 0 SM-LF
48 42 FB_A_DQ_R<63..0> CRITICAL 48 42 FB_B_DQ_R<63..0> CRITICAL
2 3 6 2 2 1 8 2
U5700 FB_A_ADDR_R<11..0> 42 48 FB_B_ADDR_R<11..0> 42 48 5% 5%

L25 DQA_0 MAA_0 E22 0 D7 DQB_0
U5700 MAB_0 N5
1/16W RP6100 1/16W RP6150
0
M11P 0
M11P 0 SM-LF 0 SM-LF 0
1 L26 DQA_1 BGA MAA_1 B22 1 1 F7 DQB_1 MAB_1 M1 1 3 3 6 3 3 3 6 3
BGA
K25 DQA_2 (4 OF 8) MAA_2 B23 2 E7 (5 OF 8) M3
2 2 DQB_2 MAB_2 2 5% 5%
3 K26 DQA_3 MAA_3 B24 3 3 G6 DQB_3 MAB_3 L3 3
RP6101 1/16W
SM-LF
RP6150 1/16W
SM-LF
0 0
MEMORY INTERFACE B
4 J26 DQA_4 MAA_4 C23 4 4 G5 DQB_4 MAB_4 L2 4 4 2 7 4 4 4 5 4
MEMORY INTERFACE A
5 H25 DQA_5 MAA_5 C22 5 5 F5 DQB_5 MAB_5 M2 5 5% 5%
6 H26 DQA_6 MAA_6 F22 6 6 E5 DQB_6 MAB_6 M5 6
1/16W
SM-LF
RP6102 1/16W
SM-LF
RP6152
0 0
7 G26 DQA_7 MAA_7 F21 7 7 C4 DQB_7 MAB_7 P6 7 5 1 8 5 5 2 7 5
8 G30 DQA_8 MAA_8 C21 8 8 B5 DQB_8 MAB_8 N3 8 5% 5%

9 D29 DQA_9 MAA_9 A24 9 9 C5 DQB_9 MAB_9 K2 9
RP6101 1/16W
SM-LF
RP6151 1/16W
SM-LF
4
0 5 3
0 6
10 D28 DQA_10 MAA_10 C24 10 10 A4 DQB_10 MAB_10 K3 10 6 6 6 6
11 E28 DQA_11 MAA_11 A25 11 11 B4 DQB_11 MAB_11 J2 11 5% 5%

12 E29 DQA_12 MAA_12 E21 0
FB_A_BA_R<1..0> 42 48
12 C2 DQB_12 MAB_12 P5 0
FB_B_BA_R<1..0> 42 48 1/16W
SM-LF
RP6102 1/16W
SM-LF
RP6151
0 0
13 G29 DQA_13 MAA_13 B20 1 13 D3 DQB_13 MAB_13 P3 1 7 3 6 7 7 1 8 7
14 G28 DQA_14 MAA_14 C19 NC 14 D1 DQB_14 MAB_14 P2 NC 5% 5%

15 F28 DQA_15 FB_A_DQM_R<7..0> 15 D2 DQB_15 FB_B_DQM_R<7..0> RP6102 1/16W
SM-LF
RP6152 1/16W
SM-LF
42 48 42 48
4
0 5 3
0 6
16 G25 DQA_16 DQMA_0* J25 0 16 G4 DQB_16 DQMB_0* E6 0 8 8 8 8
17 F26 DQA_17 DQMA_1* F29 1 17 H6 DQB_17 DQMB_1* B2 1 5% 5%

18 E26 DQA_18 DQMA_2* E25 2 18 H5 DQB_18 DQMB_2* J5 2
1/16W
SM-LF
RP6100 1/16W
SM-LF
RP6150
4
0 5 2
0 7
19 F25 DQA_19 DQMA_3* A27 3 19 J6 DQB_19 DQMB_3* G3 3 9 9 9 9
20 E24 DQA_20 DQMA_4* F15 4 20 K5 DQB_20 DQMB_4* W6 4 5% 5%

21 F23 DQA_21 DQMA_5* C15 5 21 K4 DQB_21 DQMB_5* W2 5
RP6100 1/16W
SM-LF
RP6151 1/16W
SM-LF
0 0
2 7 4 5
C 22
23
E23
D22
DQA_22
DQA_23
DQMA_6*
DQMA_7*
C11
E11
6
7
22
23
L6
L5
DQB_22
DQB_23
DQMB_6*
DQMB_7*
AC6
AD2
6
7
10
5%
10 10
5%
10
C
24 B29 DQA_24 24 G2 DQB_24
1/16W
SM-LF
RP6100 1/16W
SM-LF
RP6150
FB_A_DQS_R<7..0> 42 48 FB_B_DQS_R<7..0> 42 48 0 0
25 C29 DQA_25 25 F3 DQB_25 11 1 8 11 11 1 8 11
QSA_0 J27 0 QSB_0 F6 0
26 C25 DQA_26 26 H2 DQB_26 5% 5%
QSA_1 F30 1 QSB_1 B3 1 48 42 FB_A_BA_R<1..0> R6103 1/16W FB_A_BA<1..0> 49 48 42 FB_B_BA_R<1..0> R6153 1/16W FB_B_BA<1..0> 50
27 C27 DQA_27 27 E2 DQB_27 NO_TEST=YES SM-LF NO_TEST=YES NO_TEST=YES SM-LF NO_TEST=YES
QSA_2 F24 2 QSB_2 K6 2
1
0 2 1
0 2
28 B28 DQA_28 28 F2 DQB_28 0 0 0 0
QSA_3 B27 3 QSB_3 G1 3
29 B25 DQA_29 29 J3 DQB_29 5% 5%
30 C26 DQA_30
QSA_4 E16 4
30 F1 DQB_30
QSB_4 V5 4 1/16W
MF-LF R6104 1/16W
MF-LF R6154
QSA_5 B16 5 QSB_5 W1 5 402
1
0 2
402
1
0 2
31 B26 DQA_31 31 H3 DQB_31 1 1 1 1
QSA_6 B11 6 QSB_6 AC5 6
32 F17 DQA_32 32 U6 DQB_32 5% 5%
33 E17 DQA_33
QSA_7 F10 7
33 U5 DQB_33
QSB_7 AD1 7
R6105 1/16W
MF-LF R6155 1/16W
MF-LF
0 402 0 402
34 D16 DQA_34 34 U3 DQB_34 48 42 FB_A_CS_L_R 1 2 FB_A_CS_L 49 48 42 FB_B_CS_L_R 1 2 FB_B_CS_L 50
NO_TEST=YES NO_TEST=YES
35 F16 DQA_35 35 V6 DQB_35 5% 5%
1/16W 1/16W
36 E15 DQA_36 36 W5 DQB_36 MF-LF
402 R6106 MF-LF
402 R6156
37 F14 DQA_37 37 W4 DQB_37 0 0
48 42 FB_A_RAS_L_R 1 2 FB_A_RAS_L 49 48 42 FB_B_RAS_L_R 1 2 FB_B_RAS_L 50
38 E14 DQA_38 38 Y6 DQB_38 NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES
5% 5%
39 F13 DQA_39 39 Y5 DQB_39 R6107 1/16W
MF-LF R6157 1/16W
MF-LF
40 C17 DQA_40 40 U2 DQB_40
FB_A_CAS_L_R 1
0 2
402
FB_A_CAS_L FB_B_CAS_L_R 1
0 2
402
FB_B_CAS_L
48 42 49 48 42 50
41 B18 DQA_41 41 V2 DQB_41 NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES
5% 5%
42 B17 DQA_42 42 V1 DQB_42 1/16W
MF-LF R6108 1/16W
MF-LF R6158
43 B15 DQA_43 43 V3 DQB_43 402 0 402 0
48 42 FB_A_WE_L_R 1 2 FB_A_WE_L 49 48 42 FB_B_WE_L_R 1 2 FB_B_WE_L 50
44 C13 DQA_44 44 W3 DQB_44 NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES
CLKA0 B21 FB_A_CLKDDR_0_P_R 42 48 CLKB0 N1 FB_B_CLKDDR_0_P_R 42 48 5% 5%
45 B14 DQA_45
CLKA0* C20 FB_A_CLKDDR_0_N_R 42 48
45 Y2 DQB_45
CLKB0* N2 FB_B_CLKDDR_0_N_R 42 48
R6109 1/16W
MF-LF R6159 1/16W
MF-LF
46 C14 DQA_46 46 Y3 DQB_46 0 402 0 402
48 42 FB_A_CKE_R 1 2 FB_A_CKE 49 48 42 FB_B_CKE_R 1 2 FB_B_CKE 50
47 C16 DQA_47 CLKA1 C18 FB_A_CLKDDR_1_P_R 42 48 47 AA2 DQB_47 CLKB1 T2 FB_B_CLKDDR_1_P_R 42 48 NO_TEST=YES NO_TEST=YES
5% 5%
48 A13 DQA_48 CLKA1* A18 FB_A_CLKDDR_1_N_R 42 48 48 AA6 DQB_48 CLKB1* T3 FB_B_CLKDDR_1_N_R 42 48 1/16W 1/16W
B 49 A12 DQA_49 49 AA5 DQB_49
MF-LF
402
MF-LF
402 B
50 C12 DQA_50 CKEA B19 FB_A_CKE_R 42 48 50 AB6 DQB_50 CKEB R3 FB_B_CKE_R 42 48 RP6108 RP6158
51 B12 DQA_51 51 AB5 DQB_51 2
10 3 2
10 3
48 42 FB_A_CLKDDR_0_P_R FB_A_CLKDDR_0_P 49 48 42 FB_B_CLKDDR_0_P_R FB_B_CLKDDR_0_P 50
52 C10 DQA_52 RASA* A19 FB_A_RAS_L_R 42 48 52 AD6 DQB_52 RASB* R2 FB_B_RAS_L_R 42 48 NO_TEST=YES NO_TEST=YES
5% 5%
53 C9 DQA_53 53 AD5 DQB_53 1/16W
SM-LF
RP6108 1/16W
SM-LF
RP6158
54 B9 DQA_54 CASA* E18 FB_A_CAS_L_R 42 48 54 AE5 DQB_54 CASB* T5 FB_B_CAS_L_R 42 48 10 10
48 42 FB_A_CLKDDR_0_N_R 1 4 FB_A_CLKDDR_0_N 49 48 42 FB_B_CLKDDR_0_N_R 1 4 FB_B_CLKDDR_0_N 50
55 B10 DQA_55 55 AE4 DQB_55 NO_TEST=YES NO_TEST=YES
5% 5%
56 E13 DQA_56 WEA* E19 FB_A_WE_L_R 42 48 56 AB2 DQB_56 WEB* T6 FB_B_WE_L_R 42 48 RP6109 1/16W
SM-LF
RP6159 1/16W
SM-LF
57 E12 DQA_57 57 AB3 DQB_57 10 10
48 42 FB_A_CLKDDR_1_P_R 2 3 FB_A_CLKDDR_1_P 49 48 42 FB_B_CLKDDR_1_P_R 2 3 FB_B_CLKDDR_1_P 50
58 E10 DQA_58 CSA_0* E20 FB_A_CS_L_R 42 48 58 AC2 DQB_58 CSB_0* R5 FB_B_CS_L_R 42 48 NO_TEST=YES NO_TEST=YES
5% 5%
59 F12 DQA_59 CSA_1* F20 NC 59 AC3 DQB_59 CSB_1* R6 NC 1/16W
SM-LF
RP6109 1/16W
SM-LF
RP6159
60 F11 DQA_60 60 AD3 DQB_60 10 10
48 42 FB_A_CLKDDR_1_N_R 1 4 FB_A_CLKDDR_1_N 49 48 42 FB_B_CLKDDR_1_N_R 1 4 FB_B_CLKDDR_1_N 50
61 E9 DQA_61 61 AE1 DQB_61 NO_TEST=YES NO_TEST=YES
5% 5%
62 F9 DQA_62 62 AE2 DQB_62 1/16W 1/16W
TEST_MCLK B6 SM-LF SM-LF
63 F8 DQA_63 63 AE3 DQB_63
TEST_YCLK E8 48 42 FB_A_DQM_R<7..0> FB_A_DQM<7..0> 49 48 42 FB_B_DQM_R<7..0> FB_B_DQM<7..0> 50
NO_TEST=YES MAKE_BASE=TRUE NO_TEST=YES MAKE_BASE=TRUE
MEMTEST C8 GPU_MEMTEST
B7 MVREFD C6 MEMVMODE_0 48 42 FB_A_DQS_R<7..0> FB_A_DQS<7..0> 49 48 42 FB_B_DQS_R<7..0> FB_B_DQS<7..0> 50
NO_TEST=YES MAKE_BASE=TRUE NO_TEST=YES MAKE_BASE=TRUE
B8 MVREFS C7 MEMVMODE_1 1
DIMA_0 D30 NC DIMB_0 E3 NC R6194 48 42 FB_A_DQ_R<63..0>
NO_TEST=YES
FB_A_DQ<63..0>
MAKE_BASE=TRUE
49 48 42 FB_B_DQ_R<63..0>
NO_TEST=YES
FB_B_DQ<63..0>
MAKE_BASE=TRUE
50
DIMA_1 B13 NC DIMB_1 AA3 NC 45.3

1%
1/16W
MF-LF
47 10 =PP1V8R2V5_GPU_FB_VIO 10 =PP1V8_GPU_MEMVMODE 2 402
GPU_MEMIO_1V8 GPU_MEMIO_2V5
1 1
R6190 R6192 R61961 1
R6198 GPU (M11) Frame Buffer I/F
1K 1K 4.7K 4.7K
1% 1% 5% 5%
A VOLTAGE=0.9V
1/16W
MF-LF
2 402
VOLTAGE=0.9V
1/16W
MF-LF
2 402
1/16W
MF-LF
402 2
1/16W
MF-LF
2 402
SYNC_MASTER=MARIAS

A
GPU_MVREFS GPU_MVREFD
GPU_MEMVMODE1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 1
GPU_MEMVMODE0 AGREES TO THE FOLLOWING
C6190 1 1 C6191 R6191
1K C6192 1 1 C6193 R6193
1K GPU_MEMIO_2V5 GPU_MEMIO_1V8 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
10uF 0.1uF 1% 10uF 0.1uF 1% R61971 1
R6199 II NOT TO REPRODUCE OR COPY IT
20% 10% 1/16W 20% 10% 1/16W
6.3V 16V 6.3V 16V 4.7K 4.7K
X5R 2 2 X5R MF-LF X5R 2 2 X5R MF-LF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
603 402 2 402 603 402 2 402 5%
1/16W
5%
1/16W
MF-LF MF-LF SIZE DRAWING NUMBER REV.
402 2 2 402
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 61 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
CRITICAL CRITICAL
OMIT OMIT Power aliases required by this page:
- =PP1V8_FB_VDD
U6200 U6250 - =PP1V8_FB_VDDQ
K4D553235F K4D553235F
SDRAM_GDDR-2MX32X4 SDRAM_GDDR-2MX32X4
300MHZ-BGA-LF 300MHZ-BGA-LF Signal aliases required by this page:
50 49 10 =PP1V8_FB_VDD D7 (2 OF 2) E5 50 49 10 =PP1V8_FB_VDD D7 (2 OF 2) E5 (NONE)
D8 E7 D8 E7
1 C6200 1 C6201 1 C6202 1 C6203 1 C6204 E4 E8
1 C6250 1 C6251 1 C6252 1 C6253 1 C6254 E4 E8
10uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF (NONE)
20% 10% 10% 10% 10% E11 E10 20% 10% 10% 10% 10% E11 E10
2 4V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R VDD 2 4V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R VDD
L4 K6 L4 K6
603 402 402 402 402 VSS 603 402 402 402 402 VSS
L7 K7 L7 K7 NET_TYPE
D L8
L11
K8
K9
L8
L11
K8
K9
ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL DIFFERENTIAL_PAIR D
FB_A_CLKDDR_0_P
ECSETs provided by GPU

I244 RAM_DIFF RAM_DIFF FB_A_CLK_0 48 49
L5 L5
50 49 10 =PP1V8_FB_VDDQ C3 50 49 10 =PP1V8_FB_VDDQ C3 RAM_DIFF RAM_DIFF FB_A_CLK_0 FB_A_CLKDDR_0_N 48 49
L10 L10 I245
C5 C5
1 C6210 1 C6211 1 C6212 1 C6213 C7 F6
1 C6260 1 C6261 1 C6262 1 C6263 C7 F6 I246 RAM_DIFF RAM_DIFF FB_A_CLK_1 FB_A_CLKDDR_1_P 48 49
10uF 10uF 0.1uF 0.1uF 10uF 10uF 0.1uF 0.1uF I247 RAM_DIFF RAM_DIFF FB_A_CLK_1 FB_A_CLKDDR_1_N 48 49
20% 20% 10% 10% C8 F7 20% 20% 10% 10% C8 F7
4V 4V 16V 16V 4V 4V 16V 16V
2 X5R 2 X5R 2 X5R 2 X5R C10 F8 2 X5R 2 X5R 2 X5R 2 X5R C10 F8
603 603 402 402 603 603 402 402 I248 RAM RAM FB_A_CKE 48 49
C12 F9 C12 F9 RAM RAM FB_A_CS_L 48 49
I249
E3 G6 E3 G6 RAM RAM FB_A_ADDR<11..0> 48 49
I250
1 C6214 1 C6215 1 C6216 1 C6217 E12
VDDQ
G7 1 C6264 1 C6265 1 C6266 1 C6267 E12
VDDQ
G7
I251 RAM RAM FB_A_BA<1..0> 48 49
0.1uF 0.1uF 0.1uF 0.1uF F4 G8 0.1uF 0.1uF 0.1uF 0.1uF F4 G8
I253 RAM RAM FB_A_RAS_L 48 49
10% 10% 10% 10% 10% 10% 10% 10%
16V 16V 16V 16V 16V 16V 16V 16V
2 X5R 2 X5R 2 X5R 2 X5R F11 VSS_THERM G9 2 X5R 2 X5R 2 X5R 2 X5R F11 VSS_THERM G9
I252 RAM RAM FB_A_CAS_L 48 49
402 402 402 402 G4 H6 402 402 402 402 G4 H6 FB_A_WE_L
I254 RAM RAM 48 49
G11 H7 G11 H7
I255 RAM RAM FB_A_DQS<7..0> 48 49
J4 H8 J4 H8
1 C6218 1 C6219 1 C6220 1 C6221 J11 H9
1 C6268 1 C6269 1 C6270 1 C6271 J11 H9 I256 RAM RAM FB_A_DQM<7..0> 48 49
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF I257 RAM RAM FB_A_DQ<63..0> 48 49
10% 10% 10% 10% K4 J6 10% 10% 10% 10% K4 J6
16V 16V 16V 16V 16V 16V 16V 16V
2 X5R 2 X5R 2 X5R 2 X5R K11 J7 2 X5R 2 X5R 2 X5R 2 X5R K11 J7
402 402 402 402 402 402 402 402
J8 J8
N13 VREF N13 VREF
J9 J9
1 1
R6240 B4
R6290 B4
1K B11 1K B11
5% 5%
1/16W D4 1/16W D4
MF-LF MF-LF
D5 D5
2 402 2 402
D6 D6
FB_C0_VREF FB_C1_VREF
C 1
D9
D10
1
D9
D10 C
R6241 1 C6241 D11 R6291 1 C6291 D11
1K 0.1uF E6
1K 0.1uF E6
5% 10% 5% 10%
1/16W
MF-LF
16V
2 X5R
VSSQ E9
1/16W
MF-LF
16V
2 X5R
VSSQ E9
2 402 402 F5 2 402 402 F5
F10 F10
G5 G5
G10 G10
H5 H5
H10 H10
J5 J5
J10 J10
K5 K5
K10 K10
CRITICAL CRITICAL
OMIT OMIT
U6200 U6250
K4D553235F K4D553235F
49 48 FB_A_ADDR<0> N5 A0 300MHZ-BGA-LF
(1 OF 2)
49 48 FB_A_ADDR<0> N5 A0 300MHZ-BGA-LF
(1 OF 2)
49 48 FB_A_ADDR<1> N6 A1 DQ0 B7 FB_A_DQ<26> 48 49 49 48 FB_A_ADDR<1> N6 A1 DQ0 B7 FB_A_DQ<54> 48 49
49 48 FB_A_ADDR<2> M6 A2 DQ1 C6 FB_A_DQ<29> 48 49 49 48 FB_A_ADDR<2> M6 A2 DQ1 C6 FB_A_DQ<53> 48 49
B 49 48 FB_A_ADDR<5> M9 A5 DQ4 C2 FB_A_DQ<24> 48 49 49 48 FB_A_ADDR<5> M9 A5 DQ4 C2 FB_A_DQ<49> 48 49 B

49 48 FB_A_ADDR<6> N9 A6 DQ5 D3 FB_A_DQ<25> 48 49 49 48 FB_A_ADDR<6> N9 A6 DQ5 D3 FB_A_DQ<51> 48 49
49 48 FB_A_ADDR<7> N10 A7 DQ6 D2 FB_A_DQ<28> 48 49 49 48 FB_A_ADDR<7> N10 A7 DQ6 D2 FB_A_DQ<50> 48 49
49 48 FB_A_ADDR<8> N11 A8/AP DQ7 E2 FB_A_DQ<27> 48 49 49 48 FB_A_ADDR<8> N11 A8/AP DQ7 E2 FB_A_DQ<48> 48 49
49 48 FB_A_ADDR<9> M8 A9 DQ8 K13 FB_A_DQ<16> 48 49 49 48 FB_A_ADDR<9> M8 A9 DQ8 K13 FB_A_DQ<34> 48 49
49 48 FB_A_ADDR<10> L6 A10 DQ9 K12 FB_A_DQ<17> 48 49 49 48 FB_A_ADDR<10> L6 A10 DQ9 K12 FB_A_DQ<36> 48 49
49 48 FB_A_ADDR<11> M7 A11 DQ10 J13 FB_A_DQ<21> 48 49 49 48 FB_A_ADDR<11> M7 A11 DQ10 J13 FB_A_DQ<35> 48 49
DQ11 J12 FB_A_DQ<19> 48 49 DQ11 J12 FB_A_DQ<38> 48 49

49 48 FB_A_DQS<3> B2 DQS0 49 48 FB_A_DQS<6> B2 DQS0
H13
DQ12 G13 FB_A_DQ<23> 48 49
H13
DQ12 G13 FB_A_DQ<33> 48 49
49 48 FB_A_DQS<2> DQS1 DQ13 G12 FB_A_DQ<22> 48
49 48 FB_A_DQS<4> DQS1 DQ13 G12 FB_A_DQ<39> 48
49 49
49 48 FB_A_DQS<1> H2 DQS2 49 48 FB_A_DQS<7> H2 DQS2
DQ14 F13 FB_A_DQ<18> 48 49 DQ14 F13 FB_A_DQ<32> 48 49
49 48 FB_A_DQS<0> B13 DQS3 DQ15 F12 FB_A_DQ<20> 48
49 48 FB_A_DQS<5> B13 DQS3 DQ15 F12 FB_A_DQ<37> 48
49 49
49 48 FB_A_DQM<3> B3 DM0 DQ16 F3 FB_A_DQ<8> 48 49 49 48 FB_A_DQM<6> B3 DM0 DQ16 F3 FB_A_DQ<60> 48 49
49 48 FB_A_DQM<2> H12 DM1 DQ17 F2 FB_A_DQ<13> 48 49 49 48 FB_A_DQM<4> H12 DM1 DQ17 F2 FB_A_DQ<59> 48 49
49 48 FB_A_DQM<1> H3 DM2 DQ18 G3 FB_A_DQ<12> 48 49 49 48 FB_A_DQM<7> H3 DM2 DQ18 G3 FB_A_DQ<63> 48 49
49 48 FB_A_DQM<0> B12 DM3 DQ19 G2 FB_A_DQ<9> 48 49 49 48 FB_A_DQM<5> B12 DM3 DQ19 G2 FB_A_DQ<62> 48 49
N4
DQ20 J3 FB_A_DQ<15> 48 49
N4
DQ20 J3 FB_A_DQ<56> 48 49
49 48 FB_A_BA<0> BA0 49 48 FB_A_BA<0> BA0
M5
DQ21 J2 FB_A_DQ<10> 48 49
M5
DQ21 J2 FB_A_DQ<61> 48 49
49 48 FB_A_BA<1> BA1 49 48 FB_A_BA<1> BA1
DQ22 K2 FB_A_DQ<11> 48 49 DQ22 K2 FB_A_DQ<58> 48 49
49 48 FB_A_CLKDDR_0_P M11 CLK DQ23 K3 FB_A_DQ<14> 48 49 49 48 FB_A_CLKDDR_1_P M11 CLK DQ23 K3 FB_A_DQ<57> 48 49
49 48 FB_A_CLKDDR_0_N M12 CLK* DQ24 E13 FB_A_DQ<0> 48 49 49 48 FB_A_CLKDDR_1_N M12 CLK* DQ24 E13 FB_A_DQ<41> 48 49
49 48 FB_A_CKE N12 CKE DQ25 D13 FB_A_DQ<1> 48 49 49 48 FB_A_CKE N12 CKE DQ25 D13 FB_A_DQ<40> 48 49
49 48 FB_A_CS_L N2 CS* DQ26 D12 FB_A_DQ<2> 48 49 49 48 FB_A_CS_L N2 CS* DQ26 D12 FB_A_DQ<42> 48 49
DQ27 DQ27
49 48
49 48
FB_A_RAS_L
FB_A_CAS_L
M2
L2
RAS*
CAS* DQ28
C13
B10
FB_A_DQ<3> 48
FB_A_DQ<5> 48
49
49
49 48
49 48
FB_A_RAS_L
FB_A_CAS_L
M2
L2
RAS*
CAS* DQ28
C13
B10
FB_A_DQ<47> 48
FB_A_DQ<43> 48
49
49
GPU Frame Buffer A
FB_A_WE_L L3 WE* DQ29 B9 FB_A_DQ<7> 48 FB_A_WE_L L3 WE* DQ29 B9 FB_A_DQ<45> 48
A 49 48
NC C4
DQ30 C9 FB_A_DQ<4> 48
49
49
49 48
NC C4
DQ30 C9 FB_A_DQ<46> 48
49
49
SYNC_MASTER=MARIAS

A
1 1 DQ31 1 1 DQ31
R6245 R6246 NC C11
B8 FB_A_DQ<6> 48 49 R6295 R6296 NC C11
B8 FB_A_DQ<44> 48 49
56 56 56 56 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

5% 5% NC H4 MCL M13 5% 5% NC H4 MCL M13 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1/16W 1/16W 1/16W 1/16W AGREES TO THE FOLLOWING
MF-LF MF-LF NC H11 MF-LF MF-LF NC H11
402 2 402 2 L12
RFU1 L9 NC 402 2 402 2 L12
RFU1 L9 NC I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NC NC NC NC
FB_A_DDRCLK_0_RC
L13
RFU2 M10 NC FB_A_DDRCLK_1_RC
L13
RFU2 M10 NC II NOT TO REPRODUCE OR COPY IT
NC NC
1 C6245 NC M3 1 C6295 NC M3
470pF NC M4 470pF NC M4 SIZE DRAWING NUMBER REV.
10% 10%
2 50V 2 50V
051-6839 F
N3 N3
CERM
402
NC CERM
402
NC
APPLE COMPUTER INC.
D
SCALE SHT OF
NONE 62 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
CRITICAL CRITICAL
OMIT OMIT Power aliases required by this page:
- =PP1V8_FB_VDD
U6300 U6350 - =PP1V8_FB_VDDQ
K4D553235F K4D553235F
300MHZ-BGA-LF 300MHZ-BGA-LF Signal aliases required by this page:
50 49 10 =PP1V8_FB_VDD D7 (2 OF 2) E5 50 49 10 =PP1V8_FB_VDD D7 (2 OF 2) E5 (NONE)
D8 E7 D8 E7
1 C6300 1 C6301 1 C6302 1 C6303 1 C6304 E4 E8
1 C6350 1 C6351 1 C6352 1 C6353 1 C6354 E4 E8
10uF 0.1uF 0.1uF 0.1uF 0.1uF 10uF 0.1uF 0.1uF 0.1uF 0.1uF (NONE)
20% 10% 10% 10% 10% E11 E10 20% 10% 10% 10% 10% E11 E10
2 4V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R VDD
4V
2 X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R 2 16V
X5R VDD
L4 K6 L4 K6
603 402 402 402 402 VSS 603 402 402 402 402 VSS
L7 K7 L7 K7 NET_TYPE
D L8
L11
K8
K9
L8
L11
K8
K9
ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL DIFFERENTIAL_PAIR D
FB_B_CLKDDR_0_P
ECSETs provided by GPU

I243 RAM_DIFF RAM_DIFF FB_B_CLK_0 48 50
L5 L5
50 49 10 =PP1V8_FB_VDDQ C3 50 49 10 =PP1V8_FB_VDDQ C3 RAM_DIFF RAM_DIFF FB_B_CLK_0 FB_B_CLKDDR_0_N 48 50
L10 L10 I244
C5 C5
1 C6310 1 C6311 1 C6312 1 C6313 C7 F6
1 C6360 1 C6361 1 C6362 1 C6363 C7 F6 I245 RAM_DIFF RAM_DIFF FB_B_CLK_1 FB_B_CLKDDR_1_P 48 50
10uF 10uF 0.1uF 0.1uF 10uF 10uF 0.1uF 0.1uF I247 RAM_DIFF RAM_DIFF FB_B_CLK_1 FB_B_CLKDDR_1_N 48 50
20% 20% 10% 10% C8 F7 20% 20% 10% 10% C8 F7
4V 4V 16V 16V 4V 4V 16V 16V
2 X5R 2 X5R 2 X5R 2 X5R C10 F8 2 X5R 2 X5R 2 X5R 2 X5R C10 F8
603 603 402 402 603 603 402 402 I246 RAM RAM FB_B_CKE 48 50
C12 F9 C12 F9 RAM RAM FB_B_CS_L 48 50
I248
E3 G6 E3 G6 RAM RAM FB_B_ADDR<11..0> 48 50
I252
1 C6314 1 C6315 1 C6316 1 C6317 E12
VDDQ
G7 1 C6364 1 C6365 1 C6366 C6367 removed E12
VDDQ
G7
I251 RAM RAM FB_B_BA<1..0> 48 50
0.1uF 0.1uF 0.1uF 0.1uF F4 G8 0.1uF 0.1uF 0.1uF due to MCO F4 G8
I249 RAM RAM FB_B_RAS_L 48 50
10% 10% 10% 10% 10% 10% 10%
16V 16V 16V 16V 16V 16V 16V
2 X5R 2 X5R 2 X5R 2 X5R F11 VSS_THERM G9 2 X5R 2 X5R 2 X5R violation F11 VSS_THERM G9
I250 RAM RAM FB_B_CAS_L 48 50
402 402 402 402 G4 H6 402 402 402 G4 H6 FB_B_WE_L
I253 RAM RAM 48 50
G11 H7 G11 H7
I254 RAM RAM FB_B_DQS<7..0> 48 50
J4 H8 J4 H8
1 C6318 1 C6319 1 C6320 1 C6321 J11 H9
1 C6368 1 C6369 1 C6370 1 C6371 J11 H9 I255 RAM RAM FB_B_DQM<7..0> 48 50
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF I256 RAM RAM FB_B_DQ<63..0> 48 50
10% 10% 10% 10% K4 J6 10% 10% 10% 10% K4 J6
16V 16V 16V 16V 16V 16V 16V 16V
2 X5R 2 X5R 2 X5R 2 X5R K11 J7 2 X5R 2 X5R 2 X5R 2 X5R K11 J7
402 402 402 402 402 402 402 402
J8 J8
N13 VREF N13 VREF
J9 J9
1 1
R6340 B4
R6390 B4
1K B11 1K B11
5% 5%
1/16W D4 1/16W D4
MF-LF MF-LF
D5 D5
2 402 2 402
D6 D6
FB_D0_VREF FB_D1_VREF
C 1
D9
D10
1
D9
D10 C
R6341 1 C6341 D11 R6391 1 C6391 D11
1K 0.1uF E6
1K 0.1uF E6
5% 10% 5% 10%
1/16W
MF-LF
16V
2 X5R
VSSQ E9
1/16W
MF-LF
16V
2 X5R
VSSQ E9
2 402 402 F5 2 402 402 F5
F10 F10
G5 G5
G10 G10
H5 H5
H10 H10
J5 J5
J10 J10
K5 K5
K10 K10
CRITICAL CRITICAL
OMIT OMIT
U6300 U6350
K4D553235F K4D553235F
50 48 FB_B_ADDR<0> N5 A0 300MHZ-BGA-LF
(1 OF 2)
50 48 FB_B_ADDR<0> N5 A0 300MHZ-BGA-LF
(1 OF 2)
50 48 FB_B_ADDR<1> N6 A1 DQ0 B7 FB_B_DQ<31> 48 50 50 48 FB_B_ADDR<1> N6 A1 DQ0 B7 FB_B_DQ<51> 48 50
50 48 FB_B_ADDR<2> M6 A2 DQ1 C6 FB_B_DQ<24> 48 50 50 48 FB_B_ADDR<2> M6 A2 DQ1 C6 FB_B_DQ<53> 48 50
B 50 48 FB_B_ADDR<5> M9 A5 DQ4 C2 FB_B_DQ<30> 48 50 50 48 FB_B_ADDR<5> M9 A5 DQ4 C2 FB_B_DQ<48> 48 50 B

50 48 FB_B_ADDR<6> N9 A6 DQ5 D3 FB_B_DQ<25> 48 50 50 48 FB_B_ADDR<6> N9 A6 DQ5 D3 FB_B_DQ<52> 48 50
50 48 FB_B_ADDR<7> N10 A7 DQ6 D2 FB_B_DQ<28> 48 50 50 48 FB_B_ADDR<7> N10 A7 DQ6 D2 FB_B_DQ<49> 48 50
50 48 FB_B_ADDR<8> N11 A8/AP DQ7 E2 FB_B_DQ<27> 48 50 50 48 FB_B_ADDR<8> N11 A8/AP DQ7 E2 FB_B_DQ<50> 48 50
50 48 FB_B_ADDR<9> M8 A9 DQ8 K13 FB_B_DQ<1> 48 50 50 48 FB_B_ADDR<9> M8 A9 DQ8 K13 FB_B_DQ<32> 48 50
50 48 FB_B_ADDR<10> L6 A10 DQ9 K12 FB_B_DQ<2> 48 50 50 48 FB_B_ADDR<10> L6 A10 DQ9 K12 FB_B_DQ<35> 48 50
50 48 FB_B_ADDR<11> M7 A11 DQ10 J13 FB_B_DQ<3> 48 50 50 48 FB_B_ADDR<11> M7 A11 DQ10 J13 FB_B_DQ<33> 48 50
DQ11 J12 FB_B_DQ<4> 48 50 DQ11 J12 FB_B_DQ<34> 48 50

50 48 FB_B_DQS<3> B2 DQS0 50 48 FB_B_DQS<6> B2 DQS0
H13
DQ12 G13 FB_B_DQ<5> 48 50
H13
DQ12 G13 FB_B_DQ<36> 48 50
50 48 FB_B_DQS<0> DQS1 DQ13 G12 FB_B_DQ<0> 48
50 48 FB_B_DQS<4> DQS1 DQ13 G12 FB_B_DQ<37> 48
50 50
50 48 FB_B_DQS<1> H2 DQS2 50 48 FB_B_DQS<7> H2 DQS2
DQ14 F13 FB_B_DQ<7> 48 50 DQ14 F13 FB_B_DQ<38> 48 50
50 48 FB_B_DQS<2> B13 DQS3 DQ15 F12 FB_B_DQ<6> 48
50 48 FB_B_DQS<5> B13 DQS3 DQ15 F12 FB_B_DQ<39> 48
50 50
50 48 FB_B_DQM<3> B3 DM0 DQ16 F3 FB_B_DQ<12> 48 50 50 48 FB_B_DQM<6> B3 DM0 DQ16 F3 FB_B_DQ<63> 48 50
50 48 FB_B_DQM<0> H12 DM1 DQ17 F2 FB_B_DQ<10> 48 50 50 48 FB_B_DQM<4> H12 DM1 DQ17 F2 FB_B_DQ<60> 48 50
50 48 FB_B_DQM<1> H3 DM2 DQ18 G3 FB_B_DQ<11> 48 50 50 48 FB_B_DQM<7> H3 DM2 DQ18 G3 FB_B_DQ<62> 48 50
50 48 FB_B_DQM<2> B12 DM3 DQ19 G2 FB_B_DQ<8> 48 50 50 48 FB_B_DQM<5> B12 DM3 DQ19 G2 FB_B_DQ<61> 48 50
N4
DQ20 J3 FB_B_DQ<13> 48 50
N4
DQ20 J3 FB_B_DQ<56> 48 50
50 48 FB_B_BA<0> BA0 50 48 FB_B_BA<0> BA0
M5
DQ21 J2 FB_B_DQ<9> 48 50
M5
DQ21 J2 FB_B_DQ<58> 48 50
50 48 FB_B_BA<1> BA1 50 48 FB_B_BA<1> BA1
DQ22 K2 FB_B_DQ<14> 48 50 DQ22 K2 FB_B_DQ<59> 48 50
50 48 FB_B_CLKDDR_0_P M11 CLK DQ23 K3 FB_B_DQ<15> 48 50 50 48 FB_B_CLKDDR_1_P M11 CLK DQ23 K3 FB_B_DQ<57> 48 50
50 48 FB_B_CLKDDR_0_N M12 CLK* DQ24 E13 FB_B_DQ<23> 48 50 50 48 FB_B_CLKDDR_1_N M12 CLK* DQ24 E13 FB_B_DQ<40> 48 50
50 48 FB_B_CKE N12 CKE DQ25 D13 FB_B_DQ<20> 48 50 50 48 FB_B_CKE N12 CKE DQ25 D13 FB_B_DQ<41> 48 50
50 48 FB_B_CS_L N2 CS* DQ26 D12 FB_B_DQ<21> 48 50 50 48 FB_B_CS_L N2 CS* DQ26 D12 FB_B_DQ<42> 48 50
DQ27 DQ27
50 48
50 48
FB_B_RAS_L
FB_B_CAS_L
M2
L2
RAS*
CAS* DQ28
C13
B10
FB_B_DQ<22> 48
FB_B_DQ<19> 48
50
50
50 48
50 48
FB_B_RAS_L
FB_B_CAS_L
M2
L2
RAS*
CAS* DQ28
C13
B10
FB_B_DQ<43> 48
FB_B_DQ<47> 48
50
50
GPU Frame Buffer B
FB_B_WE_L L3 WE* DQ29 B9 FB_B_DQ<17> 48 FB_B_WE_L L3 WE* DQ29 B9 FB_B_DQ<45> 48
A 50 48
NC C4
DQ30 C9 FB_B_DQ<18> 48
50
50
50 48
NC C4
DQ30 C9 FB_B_DQ<44> 48
50
50
SYNC_MASTER=MARIAS

A
1 1 DQ31 1 1 DQ31
R6345 R6346 NC C11
B8 FB_B_DQ<16> 48 50 R6395 R6396 NC C11
B8 FB_B_DQ<46> 48 50
56 56 56 56 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY

5% 5% NC H4 MCL M13 5% 5% NC H4 MCL M13 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
1/16W 1/16W 1/16W 1/16W AGREES TO THE FOLLOWING
MF-LF MF-LF NC H11 MF-LF MF-LF NC H11
402 2 402 2 L12
RFU1 L9 NC 402 2 402 2 L12
RFU1 L9 NC I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NC NC NC NC
FB_B_DDRCLK_0_RC
L13
RFU2 M10 NC FB_B_DDRCLK_1_RC
L13
RFU2 M10 NC II NOT TO REPRODUCE OR COPY IT
NC NC
1 C6345 NC M3 1 C6395 NC M3
470pF NC M4 470pF NC M4 SIZE DRAWING NUMBER REV.
10% 10%
2 50V
051-6839 F
N3 50V N3
CERM
402
NC 2 CERM
402
NC
APPLE COMPUTER INC.
D
SCALE SHT OF
NONE 63 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PP3V3_GPU_GPIOS
- =PP2V5_PVDD
- =PP1V8_GPU_LVDS_PLL

- =I2C_GPU_TMDS_SDA - I2C data line for
external TMDS transmitters
- =I2C_GPU_TMDS_SCL - I2C clock line for
external TMDS transmitters
D BOM options provided by this page: D

(NONE) CRITICAL
U6400
(150mA MAX)
MM1571J VOLTAGE=1.8V
SOT-25A-LF MIN_LINE_WIDTH=0.38 mm
10 =PP2V5_GPU_PVDD 1 VIN VOUT 5 26 PP1V8_GPU_PVDD =PP1V8_GPU_LVDS_PLL 47
MAKE_BASE=TRUE
GPUPVDD_EN 3 CONT NOISE 4 ATI_PVDD_BYP 1
R6400
C6400 1 26
0
1uF GND 5%
20%
10V 2 C6401 1 1/16W
CERM 2 0.01uF MF-LF
603 20% 2 402
16V
CERM 2 1_8V_PVDD_STD
402
1 C6402
10UF
20%
2 6.3V
X5R
603
OMIT L6403
CRITICAL GPU PLL - 1.8V (21mA)
FERR-220-OHM
PP1V8_GPU_PLL 1 2
U5700 VOLTAGE=1.8V
MIN_LINE_WIDTH=0.38 mm 0402
M11P MIN_NECK_WIDTH=0.25 mm 1
C6403 1 C6404 1 C6405
BGA
(2 OF 8) 10UF 0.1uF 0.01uF
PLLTEST AE25 NC 20% 20% 20%
2 6.3V 2 10V 2 16V
C DPLUS
DMINUS
AF11 NC
AE11 NC
X5R
603
CERM
402
CERM
402 C
PVDD AK28
L6410
PVSS AJ28
MEMORY PLL - 1.8V (20mA)
FERR-220-OHM
MPVDD A7 PP1V8_GPU_MEMPLL 1 2
VOLTAGE=1.8V 0402
MPVSS A6 MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm 1 1
AH28 ATI_CLK27M
C6410 C6411
XTALIN 52
10UF 0.01uF
XTALOUT AJ29 NC 20% 20%
2 6.3V
X5R 2 16V
CERM
53 51 10 =PP3V3_GPU_GPIOS 603 402
HPD1 AF12 GPU_DVI_HPD 57
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF DDC1DATA AF25 GPU_DVI_DDC_DATA 57

1
R6450 1R6452 1R6454 1R6456 1R6458 1R6460 1R6462 AF24 GPU_DVI_DDC_CLK
INTERFACE
DDC1CLK 57
MONITOR
10K 10K 10K 10K 10K 10K 10K
5% 5% 5% 5% 5% 5% 5% DDC2DATA AE14 LVDS_DDC_DATA 7 56
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF DDC2CLK AE13 LVDS_DDC_CLK 7 56
2 402 2 402 2 402 2 402 2 402 2 402 2 402
AG24 =I2C_GPU_TMDS_SDA
MULTI-FUNCTION GENERAL PURPOSE I/O

DDC3DATA 8
ATI_AGP_FBSKEW<0> AJ5 GPIO_0
DDC3CLK AG23 =I2C_GPU_TMDS_SCL 8
ATI_AGP_FBSKEW<1> AH5 GPIO_1 R6499
ATI_X1CLK_SKEW<0> AJ4 GPIO_2 1K
ATI_X1CLK_SKEW<1>
TEST TESTEN AH27 GPU_TESTEN 1 2
AK4 GPIO_3
5%
ATI_BUS_CFG<0> AH4 GPIO_4 1/16W
MF-LF
ATI_BUS_CFG<1> AF4 GPIO_5 ROM ROMCS* AF5 NC 402
ATI_BUS_CFG<2> AJ3 GPIO_6
NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF NO STUFF 11 TP_EXTTMDS_RESET_L AK3 GPIO_7 EXTERNAL R6498
1K
B R64701
10K
1
R6451 1R6453 1R6455 1R6457 1R6459 1R6461 1R6463
10K 10K 10K 10K 10K 10K 10K
TP_ATI_GPIO8
TP_ATI_GPIO9
AH3
AJ2
GPIO_8
GPIO_9
SSC SSIN AK25 GPU_SSIN_PD 1
5%
2
B
5% 5% 5% 5% 5% 5% 5% 5% 1/16W
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W TP_ATI_GPIO10 AH2 GPIO_10 MF-LF
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF BUS POWER 402
R6490
402 2 TP_ATI_GPIO11 AH1 GPIO_11
2 402 2 402 2 402 2 402 2 402 2 402 2 402 MGMT 0
TP_ATI_GPIO12 AG3 GPIO_12 RSTB_MSK AG29 GPU_RSTB_MSK 1 2
51 ATI_MEMTYPE AG1 GPIO_13 5%
1/16W
LVDS PLL
HPD_PWR_SNS_EN AG2 GPIO_14 LPVSS AJ19 MF-LF
AND I/O
57
402
45 GPU_VCORE_HI_L AF3 GPIO_15
GND
LVSSR_0 AE16
52 ATI_CLK27M_SS AF2 GPIO_16
LVSSR_1 AE19
47 PP3V3_GPU_VDDR3 LVSSR_2 AF15
PROPERTIES PROVIDED BY
PAGE INDICATED BY CREF GPU_VREFG AG4 VREFG LVSSR_3 AF20
1
R6420
53 51 10 =PP3V3_GPU_GPIOS 1K
1%
VRAM_HYNIX 1/16W
1 MF-LF
R6422 2 402
10K
5%
1/16W
MF-LF
2 402 1
R6421 1 C6421
ATI_MEMTYPE 51 1K 0.1uF
1% 10%
VRAM_SAMSUNG 1/16W
1 MF-LF 2 16V
X5R
R6423 2 402 402
10K
5%
1/16W
MF-LF
2 402 GPU (M11) GPIOs/Straps

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 64 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PP3V3_GPU_CLOCKS - =PP3V3_GPU_PWRSEQ
- =PPVIN_GPU_LVDDR_LDO - =PP2V5_GPU_PWRSEQ
- =PP2V5_GPU_LVDDR_LDO - =PP1V8_GPU_PWRSEQ
- =PP1V5_GPU_PWRSEQ

(NONE)

M11 Power Shutdown Sequencing
- GPU_SS - GPU_LVDDR_2V8
D D
NET_TYPE 10 =PP3V3_GPU_PWRSEQ
DP6590
I50 ATI_CLK27M CLOCK CLOCK ATI_CLK27M_R 52 10 =PP2V5_GPU_PWRSEQ XW6590
SM
BAS16TW-X-F
SOT-363
XW6593
SM
I54 CLOCK CLOCK ATI_CLK27M 51 52
1 6
1 2 PP2V5_GPU_PSNECK PP3V3_GPU_PSNECK 1 2
I55 CLOCK CLOCK ATI_CLK27M_SSIN 52 VOLTAGE=2.5V VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm
DP6590
I51
I52
ATI_CLK27M_SS CLOCK
CLOCK
CLOCK
CLOCK
ATI_CLK27M_SS_R
ATI_CLK27M_SS
52
51 52
10 =PP1V8_GPU_PWRSEQ XW6591
SM
BAS16TW-X-F
SOT-363
1 2 PP1V8_GPU_PSNECK 2 5
VOLTAGE=1.8V
DP6590
10 =PP1V5_GPU_PWRSEQ XW6592
SM
BAS16TW-X-F
SOT-363
PP1V5_GPU_PSNECK 3 4
27M OSC 1 2
VOLTAGE=1.5V
=PP3V3_GPU_CLOCKS
L6500 VOLTAGE=3.3V
52 10 FERR-EMI-100-OHM MIN_NECK_WIDTH=0.25 mm
1 2 PP3V3_GPU_OSC
SM
NO STUFF C6500 1 1 C6501
R6503 1 CRITICAL 14 0.1uF 4.7uF
20% 20%
100K 10V 6.3V
VCC CERM 2 2 CERM
5% 402 805
1/16W
MF-LF
402 2
G6500 GPU_SS (PLACE R6500 CLOSE TO OSC)
27MHZ R6500
1
OSC
SM 8 0
OE
C ATI_OSC_OE
OUT 52 ATI_CLK27M_R 1
1
5%
2 ATI_CLK27M_SSIN 52
C
GND R6501 1/16W
MF-LF
287 402
7 1%
1/16W
(PLACE THE OSCILLATOR AND R6501/R6502 MF-LF
CLOSE TO M18 IC)
402 2
ATI_CLK27M 51 52
LVDDR 2.8V LDO
GPU_LVDDR_2V8
R65021 CRITICAL
162
1%
1/16W
U6530
MF-LF
MAX8860EUA27+T
402 2 10 =PPVIN_GPU_LVDDR_LDO 2 IN UMAX1OUT1 1 =PP2V8_GPU_LVDDR_LDO 10
OUT2 4 GPU_LVDDR_2V8
7 SHDN* 1
GPU_LVDDR_2V8
FAULT* 8 MAX8860_FAULT_L R6530 GPU_LVDDR_2V8
5 SET 100K
C6530 1 CC 6 MAX8860_CC 5%
1/16W
1 C6532
2.2uF GND GPU_LVDDR_2V8 MF-LF 2.2uF
20% 20%
6.3V 3
C6531 1 2 402 6.3V
CERM1 2 2 CERM1
603 0.033uF 603
20%
10V
X7R 2
402
IS TABLE_ALT_HEAD
SPREAD SPECTRUM SUPPORT PART NUMBER ALTERNATE FOR

PART NUMBER
BOM OPTION REF DES COMMENTS:
B
B S0=1;S1=M => -1.5% DOWN-SPREAD 353S1188 353S1140 GPU_LVDDR_2V8 U6530 Primary is 2.77V/Alt is 2.82V
TABLE_ALT_ITEM
GPU_SS
=PP3V3_GPU_CLOCKS
52 10
L6510 VOLTAGE=3.3V
FERR-EMI-100-OHM MIN_NECK_WIDTH=0.25 mm
1 2 PP3V3_GPU_SS
SM GPU_SS GPU_SS
1 C6510 1 C6511 GPU_SS
10UF 0.1uF
20% 20% 7 CRITICAL
2 6.3V 2 10V
X5R
603
CERM
402
VDD
U6510
CY25811 GPU_SS
SOI-LF
NO STUFF
1 1
GPU_SS
52 ATI_CLK27M_SSIN 1 XIN/CLKIN R6510
R6511 R6513 8 XOUT 33
NC SSCLK 5 52 ATI_CLK27M_SS_R 1 2 ATI_CLK27M_SS 51 52
0 0 5%
5% 5%
1/16W 1/16W 1/16W
MF-LF MF-LF NC 6 FRSEL MF-LF
402 2 402
2 402
CY25811_S1 3 S1
CY25811_S0 4 S0
NO STUFF NO STUFF
1 1
VSS
R6512 R6514 2
0 0
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 2 2 402
GPU (M11) Clocks/Misc

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 65 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes ELECTRICAL_CONSTRAINT_SET
NET_TYPE
SPACING PHYSICAL DIFFERENTIAL_PAIR

I108 DVO DVO GPU_DVOD_R<23..0> 6 53
- =PP2V5_GPU_A2VDD - =PP1V8_GPU_AVDD
I109 DVO DVO GPU_DVO_HSYNC_R 6 53
- =PP1V8_GPU_TPVDD - =PP3V3_GPU_GPIOS ECSETs provided by SI TMDS
I111 DVO DVO GPU_DVO_VSYNC_R 6 53
Signal aliases required by this page: I110 DVO DVO GPU_DVO_DE_R 6 53
(NONE) I112 DVO DVO GPU_DVO_CLKP_R 6 53

I113 LVDS_DATA LVDS LVDS LVDS_U0 LVDS_U0_P 7 53 56
- DVO_1V5 - GPU_VDDR4_3V3
I114 LVDS LVDS LVDS_U0 LVDS_U0_N 7 53 56
- DVO_1V8 - DVO_3V3
LVDS_DATA LVDS LVDS LVDS_U1 LVDS_U1_P 7 53 56
D
I115
I116 LVDS LVDS LVDS_U1 LVDS_U1_N 7 53 56 D

I117 LVDS_DATA LVDS LVDS LVDS_U2 LVDS_U2_P 7 53 56
I118 LVDS LVDS LVDS_U2 LVDS_U2_N 7 53 56
I119 LVDS_CLK_UPPER LVDS LVDS LVDS_UCLK CLKLVDS_U_P 7 53 56
I120 LVDS LVDS LVDS_UCLK CLKLVDS_U_N 7 53 56
I125 LVDS_DATA LVDS LVDS LVDS_L0 LVDS_L0_P 7 53 56
I124 LVDS LVDS LVDS_L0 LVDS_L0_N 7 53 56
I123 LVDS_DATA LVDS LVDS LVDS_L1 LVDS_L1_P 7 53 56
53 47 PP1V5R3V3_GPU_VDDR4 10 =PP1V8_GPU_TPVDD I122 LVDS LVDS LVDS_L1 LVDS_L1_N 7 53 56
DVO_1V5&DVO_1V8 I121 LVDS_DATA LVDS LVDS LVDS_L2 LVDS_L2_P 7 53 56

1
R6640 OMIT
L6600 I127 LVDS LVDS LVDS_L2 LVDS_L2_N 7 53 56
10K CRITICAL FERR-220-OHM I128 LVDS_CLK_LOWER LVDS LVDS LVDS_LCLK CLKLVDS_L_P 7 53 56

5%
DVO_3V3&GPU_VDDR4_3V3 1/16W 1 2 I126 LVDS LVDS LVDS_LCLK CLKLVDS_L_N 7 53 56
MF-LF PP1V8_GPU_TPVDD
R6641 2 402 U5700 VOLTAGE=1.8V
10K M11P MIN_NECK_WIDTH=0.25 mm VGA VGA GPU_VGA_R
2 1 GPU_DVOVMODE AE10 DVOVMODE BGA TXCM AH13 NC 1 C6600 1 C6601 I130
VGA VGA GPU_VGA_G
53 57
5% (3 OF 8) TXCP AK13 NC 1uF 0.01uF I129 53 57
1/16W 10% 20%

VGA VGA GPU_VGA_B
MF-LF 6.3V
2 CERM
16V
2 CERM
I133 53 57
402 TX0M AJ13 NC 402 402 VGA_CONN VGA_CONN VGA_R 57
INTEGRATED TMDS
GPU_DVO_VSYNC_R AJ10 I136
53 6 ZV_LCDCNTL_0
TX0P AH14 NC I135 VGA_CONN VGA_CONN VGA_G 57
53 6 GPU_DVO_HSYNC_R AK10 ZV_LCDCNTL_1
I137 VGA_CONN VGA_CONN VGA_B 57
53 6 GPU_DVO_DE_R AJ11 ZV_LCDCNTL_2 TX1M AJ14 NC
53 6 GPU_DVO_CLKP_R AH11 ZV_LCDCNTL_3 TX1P AH15 NC
I132 TV TV GPU_TV_Y 53 57
53 6 GPU_DVOD_R<0> AH6 ZV_LCDDATA_0 TX2M AJ15 NC I131 TV TV GPU_TV_C 53 57

PP1V8_GPU_PANEL_IO 47
VIP HOST/ EXTERNAL TMDS

53 6 GPU_DVOD_R<1> AJ6 ZV_LCDDATA_1 TX2P AK15 NC PROPERTIES PROVIDED BY I134 TV TV GPU_TV_COMP 53 57
PAGE INDICATED BY CREF
GPU_DVOD_R<2> AK6 ZV_LCDDATA_2 =PP3V3_GPU_GPIOS TV_CONN TV_CONN TV_Y
53 6
53 6 GPU_DVOD_R<3> AH7 ZV_LCDDATA_3

TPVDD AK12 1 C6605 1 C6606 1 C6607 51 10 I138
TV_CONN TV_CONN TV_C
57
57
0.1uF 0.1uF 0.01uF I139
C 53 6
53 6
GPU_DVOD_R<4>
GPU_DVOD_R<5>
AK7 ZV_LCDDATA_4
AJ7 ZV_LCDDATA_5
TPVSS
TXVDDR1
AJ12
AF14
20%
2 10V
CERM
20%
2 10V
CERM
20%
16V
2 CERM R6690
10K
1
I140 TV_CONN TV_CONN TV_COMP 57 C
402 402 402 5%
53 6 GPU_DVOD_R<6> AH8 ZV_LCDDATA_6 TXVDDR0 AF13 1/16W
MF-LF
53 6 GPU_DVOD_R<7> AJ8 ZV_LCDDATA_7 402 2
TXVSSR0 AG13
53 6 GPU_DVOD_R<8> AH9 ZV_LCDDATA_8
TXVSSR1 AG14 53 GPU_AUXWIN_PU
53 6 GPU_DVOD_R<9> AJ9 ZV_LCDDATA_9
TXVSSR2 AH12 10 =PP1V8_GPU_AVDD
53 6 GPU_DVOD_R<10> AK9 ZV_LCDDATA_10
53 6 GPU_DVOD_R<11> AH10 ZV_LCDDATA_11 R AK27 GPU_VGA_R 53 57
53 6 GPU_DVOD_R<12> AE6 ZV_LCDDATA_12 G AJ27 GPU_VGA_G 53 57 L6610

53 6 GPU_DVOD_R<13> AG6 ZV_LCDDATA_13 B AJ26 GPU_VGA_B 53 57
FERR-220-OHM
53 47 PP1V5R3V3_GPU_VDDR4
53 6 GPU_DVOD_R<14> AF6 ZV_LCDDATA_14 PP1V8_GPU_AVDD 1 2
1
53 6 GPU_DVOD_R<15> AE7 ZV_LCDDATA_15
HSYNC AG25 GPU_VGA_HSYNC 57
1
R6650 R6660 1R6661 1R6662 VOLTAGE=1.8V
R6642 1 VSYNC AH25 GPU_VGA_VSYNC 75 75 75 MIN_NECK_WIDTH=0.25 mm
57
C6610 C6611
DAC/CRT
53 6 GPU_DVOD_R<16> AF7 ZV_LCDDATA_16 499 1% 1% 1% 1 1

10K GPU_DVOD_R<17>
1% 1/16W 1/16W 1/16W 10UF 0.01uF
5% 53 6 AE8 ZV_LCDDATA_17 1/16W MF-LF MF-LF MF-LF 20% 20%
1/16W MF-LF 2 402 2 402 2 402
MF-LF 53 6 GPU_DVOD_R<18> AG8 ZV_LCDDATA_18 AUXWIN AF26 GPU_AUXWIN_PU 53
2 402 2 6.3V
X5R 2 16V
CERM
402 2 603 402
53 6 GPU_DVOD_R<19> AF8 ZV_LCDDATA_19 RSET AH26 ATI_RSET
53 6 GPU_DVOD_R<20> AE9 ZV_LCDDATA_20
AVDD AH24 (PP1V8_GPU_AVDD)
53 6 GPU_DVOD_R<21> AF9 ZV_LCDDATA_21
(AVDD+VDDDI=75mA)
53 6 GPU_DVOD_R<22> AG10 ZV_LCDDATA_22
53 6 GPU_DVOD_R<23> AF10 ZV_LCDDATA_23 AVSSQ AD24
AVSSN AH23
L6615
56 INV_ON_PWM AG12 BLON FERR-220-OHM
CONTROL AND VDD1DI AE24 (PP1V8_GPU_VDDDI) PP1V8_GPU_VDDDI 1 2
56 PANEL_PWR_EN AE12 DIGON VOLTAGE=1.8V
EXTERNAL SSC VSS1DI AE23 MIN_LINE_WIDTH=0.38 mm 0402
R6680 1
R6681 1 NC AJ25 SSOUT 1 C6615 1 C6616 1 C6617
10K 10K 10UF 0.01uF 0.01uF
B 5%
1/16W
MF-LF
5%
1/16W
MF-LF
56 53 7
56 53 7
LVDS_U0_P
LVDS_U0_N
AF16
AG16
TXOUT_U0P
TXOUT_U0N
20%
6.3V
2 X5R
603
20%
16V
2 CERM
402
20%
16V
2 CERM
402
B
402 2 402 2
56 53 7 LVDS_U1_P AF17 TXOUT_U1P
H2SYNC AJ24 NC
56 53 7 LVDS_U1_N AG17 TXOUT_U1N
V2SYNC AK24 NC
56 53 7 LVDS_U2_P AE18 TXOUT_U2P 10 =PP2V5_GPU_A2VDD
LVDS_U2_N GPU_TV_Y
(TV/CRT2)
56 53 7 AF18 TXOUT_U2N Y_G AJ22 53 57
NO_TEST=YES TP_LVDS_U3_P AG20 TXOUT_U3P C_R AJ23 GPU_TV_C 53 57

DAC2
L6620
LVDS CHANNEL
NO_TEST=YES TP_LVDS_U3_N AH20 TXOUT_U3N COMP_B AK22 GPU_TV_COMP 53 57

(140mA) FERR-220-OHM
56 53 7 CLKLVDS_U_P AG19 TXCLK_UP R2SET AK21 ATI_R2SET 1 1 1 1 2
56 53 7 CLKLVDS_U_N AF19 TXCLK_UN R6670 R6671 R6672 PP2V5_GPU_A2VDD
VOLTAGE=2.5V 0402
A2VDD0 AG21 (PP2V5_GPU_A2VDD) 1
R6651 75 75 75 MIN_LINE_WIDTH=0.5 mm
1% 1% 1% MIN_NECK_WIDTH=0.25 mm
56 53 7 LVDS_L0_P AH16 TXOUT_L0P A2VDD1 AH21 715
1%
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1 C6620 1 C6621 1 C6622
LVDS_L0_N AK16 TXOUT_L0N 1/16W 10UF 0.01uF 0.01uF
56 53 7
A2VSSN0 AH22 MF-LF 2 402 2 402 2 402 20% 20% 20%
56 53 7 LVDS_L1_P AJ16 TXOUT_L1P 2 402 2 6.3V
X5R 2 16V
CERM 2 16V
CERM
A2VSSN1 AJ21 603 402 402
56 53 7 LVDS_L1_N AH17 TXOUT_L1N
56 53 7 LVDS_L2_P AJ17 TXOUT_L2P A2VDDQ AF22 (PP1V8_GPU_A2VDDQ)
LVDS_L2_N AH18 TXOUT_L2N A2VSSQ AF23
56 53 7
NO_TEST=YES TP_LVDS_L3_P AH19 TXOUT_L3P

L6625
VDD2DI AE22 (PP1V8_GPU_VDDDI) (2mA) FERR-220-OHM
NO_TEST=YES TP_LVDS_L3_N AK19 TXOUT_L3N 1 2
VSS2DI AE21 PP1V8_GPU_A2VDDQ
VOLTAGE=1.8V 0402
56 53 7 CLKLVDS_L_P AJ18 TXCLK_LP MIN_LINE_WIDTH=0.25 mm
56 53 7 CLKLVDS_L_N AK18 TXCLK_LN 1 C6625 1 C6626
10UF 0.01uF
20% 20%
2 6.3V
X5R 2 16V
CERM
603 402
GPU (M11) DVI/DAC Outputs

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 66 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
Power aliases required by this page: SILICON IMAGE TMDS EXTERNAL TMDS TERMINATION
TERMINATION NETWORK SHOULD BE CONNECTED AS SHOWN
- =PP3V3_RUN_SI - =PP1V5R3V3_DVO_VREF
TMDS_EXT&TMDS_DUAL TMDS_EXT&TMDS_DUAL
- =SI_TMDS_RESET_L - =RP67xxPy (pinswappable series R)
RP6707 RP6709
10 10 EXT_TMDS_CLK_CMF
- =SI_I2C_CLK SI_TMDS_CLKN 1 4 TMDS_CLKN SI_TMDS_DN<1> 2 3 TMDS_DN<1>
54 54 57 54 54 57
- =SI_I2C_DATA TMDS_EXT&TMDS_DUAL 5% TMDS_EXT&TMDS_DUAL 5% R6760 R6761
1/16W 1/16W
RP6707 SM-LF RP6709 SM-LF 49.9 49.9
BOM options provided by this page: 57 54 TMDS_CLKP 1 2 1 2 TMDS_CLKN 54 57
10 10
- TMDS_EXT SI_TMDS_CLKP 2 3 TMDS_CLKP SI_TMDS_DP<1> 1 4 TMDS_DP<1> EXT_TMDS_D0_CMF
- DVO_1V5 - DVO_3V3 54 54 57 54 54 57 1% 1%
1/16W 1/16W TMDS_EXT&TMDS_DUAL
- TMDS_DUAL - DVO_1V8 5% TMDS_EXT&TMDS_DUAL 5% TMDS_EXT&TMDS_DUAL MF-LF MF-LF TMDS_EXT&TMDS_DUAL
D 1/16W
SM-LF RP6708
10
1/16W
SM-LF RP6710
10 TMDS_EXT&TMDS_DUAL
402 402
R6762
49.9
R6763
49.9
D
Net Spacing Type: TMDS 1 4 2 3 1
57 54 TMDS_DP<0> 1 2 1 2 TMDS_DN<0> 54 57
54 SI_TMDS_DN<0> TMDS_DN<0> 54 57 54 SI_TMDS_DN<2> TMDS_DN<2> 54 57 C6760 1% 1%
Net Physical Type: TMDS TMDS_EXT&TMDS_DUAL 5% TMDS_EXT&TMDS_DUAL 5%
0.001uF 1/16W 1/16W
10% MF-LF MF-LF
1/16W 1/16W 50V
RP6708 SM-LF RP6710 SM-LF CERM 2 402 402
NOTE: Target differential impedance for 10 10 402

TMDS_EXT&TMDS_DUAL
SI_TMDS_DP<0> 2 3 TMDS_DP<0> SI_TMDS_DP<2> 1 4 TMDS_DP<2>
54 54 57 54 2 54 57
TMDS data pairs is 100 ohms. EXT_TMDS_D1_CMF 1
5% 5% C6762
1/16W 1/16W TMDS_EXT&TMDS_DUAL TMDS_EXT&TMDS_DUAL 0.001uF
NET_TYPE SM-LF SM-LF R6764 R6765 10%
50V
ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL DIFFERENTIAL_PAIR 49.9 49.9 CERM 2
57 54 TMDS_DP<1> 1 2 1 2 TMDS_DN<1> 54 57
402
I306 GPU_DVO_LOWER DVO DVO GPU_DVOD<0..11> 6 54 1% 1%
1/16W 1/16W
I309
GPU_DVO_BOTH DVO DVO GPU_DVO_HSYNC 6 54 55 MF-LF MF-LF
402 402 EXT_TMDS_D2_CMF
I310 GPU_DVO_BOTH DVO DVO GPU_DVO_VSYNC 6 54 55 TMDS_EXT&TMDS_DUAL
GPU_DVO_BOTH DVO DVO GPU_DVO_DE 6 54 55 =PP3V3_RUN_SI 10 54 55 TMDS_EXT&TMDS_DUAL R6766 R6767
I311
L6723
I312
GPU_DVO_CLKP DVO DVO GPU_DVO_CLKP 6 54 55 180-OHM-1.5A C6764 1
TMDS_DP<2> 1
49.9
2 1
49.9
2 TMDS_DN<2>
57 54 54 57
0.001uF
TMDS_CLK TMDS TMDS SI_TMDS_CLK SI_TMDS_CLKP 54
1 2 10% 1% 1%
I316 50V 1/16W 1/16W
CERM 2
I317 TMDS TMDS SI_TMDS_CLK SI_TMDS_CLKN 54 0603
402
MF-LF MF-LF
I319 TMDS_DATA TMDS TMDS SI_TMDS_D0 SI_TMDS_DP<0> 54 TMDS_EXT&TMDS_DUAL MIN_LINE_WIDTH=0.38 mm
VOLTAGE=3.3V TMDS_EXT&TMDS_DUAL
TMDS TMDS SI_TMDS_D0 SI_TMDS_DN<0> 54 L6720 =PP3V3_RUN_SI 10 54 55
I318
SI_TMDS_DP<1> 180-OHM-1.5A PP3V3_SI_M_AVCC C6766 1

I321 TMDS_DATA TMDS TMDS SI_TMDS_D1 54
0.001uF
SI_TMDS_DN<1> 1 2 10%
I320 TMDS TMDS SI_TMDS_D1 54 TMDS_EXT&TMDS_DUAL TMDS_EXT&TMDS_DUAL 50V
CERM 2
I322 TMDS_DATA TMDS TMDS SI_TMDS_D2 SI_TMDS_DP<2> 2 54 0603 1 C6723 1 C6725 402
MIN_NECK_WIDTH=0.2 mm 10UF 100pF
I323 TMDS TMDS SI_TMDS_D2 SI_TMDS_DN<2> 54 MIN_LINE_WIDTH=0.38 mm TMDS_EXT&TMDS_DUAL
10% 5%
VOLTAGE=3.3V
PP3V3_SI_M_VCC
2
6.3V
X5R C6724 1
2
50V
CERM
805 100pF 402
5%
50V
TMDS_EXT&TMDS_DUAL CERM 2
402
C6722
C Lower DVO Termination
Place close to GPU
C6720 1 1
TMDS_EXT&TMDS_DUAL
C6721 100pF
5%
1
TMDS_EXT&TMDS_DUAL
C
10UF 100pF 50V
2 L6726
10% 5% CERM
One each for: GPU_DVOD<0..11>
6.3V
2 2
50V 402 180-OHM-1.5A =PP3V3_RUN_SI
X5R CERM 10 54 55
GPU_DVO_HSYNC 805 402 MIN_NECK_WIDTH=0.2 mm 1 2
GPU_DVO_VSYNC MIN_LINE_WIDTH=0.38 mm
GPU_DVO_DE VOLTAGE=3.3V 0603
GPU_DVO_CLKP TMDS_EXT&TMDS_DUAL
PP3V3_SI_M_PVCC
TMDS_EXT&TMDS_DUAL TMDS_EXT&TMDS_DUAL TMDS_EXT&TMDS_DUAL TMDS_EXT&TMDS_DUAL
TMDS_EXT&TMDS_DUAL 1
C6726 1
C6727 1
C6728 1
C6729
RP6720 10UF 100pF 10UF 100pF
10 10% 5% 10% 5%
=RP6720P1 1 8 =RP6720P8 6.3V 50V 6.3V 50V
6 6 2 X5R 2 CERM 2 X5R 2 CERM
805 402 805 402
5% TMDS_EXT&TMDS_DUAL
1/16W
SM-LF RP6720
10 TMDS_EXT&TMDS_DUAL TMDS_EXT&TMDS_DUAL NO STUFF Place C6726/C6727 at pin 28 Place C6728/C6729 at pin 46
=RP6720P2 2 7 =RP6720P7
6 6
R6734 1 R6752 1
1
TMDS_EXT&TMDS_DUAL 5%
R6754
1/16W 10K 301 4.99K
RP6720 SM-LF 5%
1/16W
1%
1/16W
1%
1/16W
10 MF-LF MF-LF MF-LF
=RP6720P3 3 6 =RP6720P6 402 2 402 2
2 402
6 6
28
PVCC1 46
40
AVCC 34
AVCC 22
1/16W
VCC 3
SM-LF RP6720
PVCC2
VCC
10
6 =RP6720P4 4 5 =RP6720P5 6
1/16W
RP6721 SM-LF 8 =I2C_SI_M_SCL 27 SCL MSEN 48 SI_M_MSEN
10 8 =I2C_SI_M_SDA 26 SDA
6 =RP6721P1 1 8 =RP6721P8 6
SI_M_A1 24 CTL3/A1
1/16W 55 11 =SI_TMDS_RESET_L 25 RST* NET_TYPE
SM-LF RP6721 TMDS_EXT&TMDS_DUAL ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL DIFFERENTIAL_PAIR
B 6 =RP6721P2 2
10
7 =RP6721P7 6
55
55
SI_SYNC
SI_HTPLG
47
44
SYNCO/SYNCI
EHTPLG TXC+ 33 SI_TMDS_CLKP 54 I329 TMDS TMDS TMDS_CLK TMDS_CLKP 54 57
B
TMDS_EXT&TMDS_DUAL 5% CRITICAL
1/16W TXC- 32 SI_TMDS_CLKN 54 TMDS TMDS TMDS_CLK TMDS_CLKN 54 57
RP6721 SM-LF 54 6 GPU_DVOD<0> 18 D0 U6700 I330
TMDS TMDS TMDS_D0 TMDS_DP<0> 54 57

10 54 6 GPU_DVOD<1> 17 D1 SIL1178CS48 TX0+ 36 SI_TMDS_DP<0> 54
I331
=RP6721P3 3 6 =RP6721P6 TMDS_DN<0>

6 6 I332 TMDS TMDS TMDS_D0 54 57
54 6 GPU_DVOD<2> 16 D2 TSSOP TX0- 35 SI_TMDS_DN<0> 54
5% TMDS_EXT&TMDS_DUAL I333
TMDS TMDS TMDS_D1 TMDS_DP<1> 54 57
1/16W 54 6 GPU_DVOD<3> 15 D3
SM-LF RP6721 TX1+ 39 SI_TMDS_DP<1> 54 I334 TMDS TMDS TMDS_D1 TMDS_DN<1> 54 57
54 6 GPU_DVOD<4> 14 D4
10 TX1- 38 SI_TMDS_DN<1> 54 TMDS TMDS TMDS_D2 TMDS_DP<2> 54 57
4 5 I335
6 =RP6721P4 =RP6721P5 6 54 6 GPU_DVOD<5> 13 D5
I336 TMDS TMDS TMDS_D2 TMDS_DN<2> 54 57
TMDS_EXT&TMDS_DUAL 5% 54 6 GPU_DVOD<6> 10 D6 TX2+ 42 SI_TMDS_DP<2> 2 54
1/16W
RP6722 SM-LF 54 6 GPU_DVOD<7> 9 D7 TX2- 41 SI_TMDS_DN<2> 54
10 54 6 GPU_DVOD<8> 8 D8
=RP6722P1 1 8 =RP6722P8
6 6
54 6 GPU_DVOD<9> 7 D9
1/16W 54 6 GPU_DVOD<10> 6 D10
SM-LF RP6722 54 6 GPU_DVOD<11> 5 D11
10
=RP6722P2 2 7 =RP6722P7 GPU_DVO_DE
6 6 55 54 6 19 DE
TMDS_EXT&TMDS_DUAL 5% 55 54 6 GPU_DVO_HSYNC 20 HSYNC
1/16W EXT_SWING 30 SI_M_EXTSWING
RP6722 SM-LF 55 54 6 GPU_DVO_VSYNC 21 VSYNC
10 55 54 6 GPU_DVO_CLKP 12 IDCK+ VREF 2 SI_VREF 54 55
=RP6722P3 3 6 =RP6722P6
6 6
55 54 SI_IDCK_N 11 IDCK- The DVO bus can be run with 3.3V or 1.5V/1.8V
TMDS_EXT&TMDS_DUAL
THRML
5% signaling. The power rail for the reference
1/16W TMDS_EXT&TMDS_DUAL should be connected to the GPU DVO rail.
PGND
PGND
AGND
AGND
AGND
RP6722 NO STUFF
PAD
SM-LF
GND
GND
GND
10
6 =RP6722P4 4 5 =RP6722P5 6
R6730 1 R6732 1 =PP1V5R3V3_DVO_VREF 47
DVO_3V3 10K 100K TMDS_EXT&TMDS_DUAL

29
45
31
43
37
1
23
49
1 5% 5%
1
RP6723
1/16W R6733 1/16W
MF-LF
1/16W
MF-LF
R6740
10
SM-LF
1K
5%
402
2
402
2
1%
1K Lower TMDS Transmitter
=RP6723P1 1 8 =RP6723P8
6 6 1/16W TMDS_EXT&TMDS_DUAL DVO_1V5&DVO_1V8 1/16W
A 5%
1/16W
SM-LF
TMDS_EXT&TMDS_DUAL
RP6723
MF-LF
402 2
1
R6731
10K
R6742
0 55 54 SI_VREF
MF-LF
2 402
SYNC_MASTER=MARIAS

A
5% 55 54 SI_IDCK_N 2 1
10 1/16W MIN_LINE_WIDTH=0.2 mm
=RP6723P2 2 7 =RP6723P7 5%
6 6 MF-LF MIN_NECK_WIDTH=0.2 mm THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1/16W PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
2 402 MF-LF
TMDS_EXT&TMDS_DUAL 5% TMDS_EXT&TMDS_DUAL DVO_1V5&DVO_1V8 AGREES TO THE FOLLOWING
1/16W 402
1 1
RP6723 SM-LF C6740 R6741 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
10 0.1uF 1K II NOT TO REPRODUCE OR COPY IT
=RP6723P3 3 6 =RP6723P6 20%
6 6 10V 1%
CERM 2 1/16W III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
5% TMDS_EXT&TMDS_DUAL 402 MF-LF
1/16W 402
2
SM-LF RP6723 SIZE DRAWING NUMBER REV.
051-6839 F
10
6 =RP6723P4 4 5 =RP6723P5 6
APPLE COMPUTER INC.
D
5%
1/16W SCALE SHT OF
SM-LF
NONE 67 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PP3V3_RUN_SI Upper Channel Series Termination
TMDS_DUAL
- =SI_I2C_CLK - =SI_TMDS_RESET_L
- =SI_I2C_DATA - =RP68xxPy (pinswappable series R)
RP6811
TMDS_DUAL 10
SI_TMDS_DN<3> 1 4 TMDS_DN<3>
55 55 57
BOM options provided by this page: L6836
180-OHM-1.5A TMDS_DUAL 5%
- TMDS_DUAL VOLTAGE=3.3V =PP3V3_RUN_SI 10 54 55 1/16W
MIN_NECK_WIDTH=0.2 mm 1 2 RP6811 SM-LF

10
0603 SI_TMDS_DP<3> 2 3 TMDS_DP<3>
Net Spacing Type: TMDS MIN_LINE_WIDTH=0.38 mm 55 55 57
D Net Physical Type: TMDS

PP3V3_SI_S_PVCC 5%
1/16W
TMDS_DUAL D
TMDS_DUAL TMDS_DUAL TMDS_DUAL TMDS_DUAL SM-LF RP6812
NOTE: Target differential impedance for 1
C6836 1
C6837 1
C6838 1
C6839 10
SI_TMDS_DN<4> 2 3 TMDS_DN<4>
55 55 57
TMDS data pairs is 100 ohms. 10UF 100pF 10UF 100pF
10% 5% 10% 5%
6.3V 50V 6.3V 50V TMDS_DUAL 5%
2 X5R 2 CERM 2 X5R 2 CERM 1/16W
NET_TYPE 805 402 805 402 RP6812 SM-LF
ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL DIFFERENTIAL_PAIR 10
SI_TMDS_DP<4> 1 4 TMDS_DP<4>
TMDS_DUAL 55 55 57
Place C6836/C6837 Place C6838/C6839
I54 GPU_DVO_UPPER DVO DVO GPU_DVOD<12..19> 6 55 L6833 5% TMDS_DUAL
at pin 28. at pin 46. 180-OHM-1.5A 1/16W
I55 GPU_DVOD20 DVO DVO GPU_DVOD<20> 6 55 =PP3V3_RUN_SI 10 54 55 SM-LF RP6813
GPU_DVO_UPPER DVO DVO GPU_DVOD<21..23> 6 55
1 2 10
I56 2 3
55 SI_TMDS_DN<5> TMDS_DN<5> 55 57
I58 PROVIDED BY LOWER TXMR GPU_DVO_VSYNC 6 54 55 0603
TMDS_DUAL 5%
I59 PROVIDED BY LOWER TXMR GPU_DVO_DE 6 54 55 PP3V3_SI_S_AVCC 1/16W
PROVIDED BY LOWER TXMR GPU_DVO_CLKP 6 54 55 MIN_LINE_WIDTH=0.38 mm TMDS_DUAL TMDS_DUAL TMDS_DUAL

RP6813 SM-LF
I60 10
SI_TMDS_DP<3>
MIN_NECK_WIDTH=0.2 mm 1
C6833 1
C6834 1
C6835 55 SI_TMDS_DP<5> 1 4 TMDS_DP<5> 55 57
I74
TMDS_DATA TMDS TMDS SI_TMDS_D3 55
10UF 100pF 100pF
VOLTAGE=3.3V 10% 5% 5%
5%
I75 TMDS TMDS SI_TMDS_D3 SI_TMDS_DN<3> 55 6.3V 50V 50V 1/16W
2 X5R 2 CERM 2 CERM SM-LF
I76 TMDS_DATA TMDS TMDS SI_TMDS_D4 SI_TMDS_DP<4> 55 805 402 402
TMDS_DUAL
TMDS TMDS SI_TMDS_D4 SI_TMDS_DN<4> 55
I77
L6830
I78 TMDS_DATA TMDS TMDS SI_TMDS_D5 SI_TMDS_DP<5> 55 180-OHM-1.5A =PP3V3_RUN_SI 10 54 55
I79
TMDS TMDS SI_TMDS_D5 SI_TMDS_DN<5> 55
1 2
TMDS TMDS TMDS_D3 TMDS_DP<3> 55 57 0603

I80
TMDS TMDS TMDS_D3 TMDS_DN<3> 55 57

Upper Channel Common-mode Termination
I81
PP3V3_SI_S_VCC
I82 TMDS TMDS TMDS_D4 TMDS_DP<4> 55 57
MIN_LINE_WIDTH=0.38 mm TMDS_DUAL TMDS_DUAL TMDS_DUAL TMDS_D3_CMF
TMDS TMDS TMDS_D4 TMDS_DN<4> 55 57
1 1 1
I83
TMDS_DP<5>
MIN_NECK_WIDTH=0.2 mm C6830 C6831 C6832 TMDS_DUAL TMDS_DUAL
I84 TMDS TMDS TMDS_D5 55 57
10UF 100pF 100pF
VOLTAGE=3.3V 10% 5% 5% R6804 R6805
I85 TMDS TMDS TMDS_D5 TMDS_DN<5> 55 57 6.3V 50V 50V
2 X5R 2 CERM 2 CERM
49.9 49.9
C 805 402 402 57 55 TMDS_DP<3> 1
1%
1/16W
2 1
1%
1/16W
2 TMDS_DN<3> 55 57
C
MF-LF MF-LF
402 402
TMDS_DUAL
C6804 1
0.001uF
10%
50V
CERM 2
402
TMDS_DUAL
TMDS_DUAL NO STUFF TMDS_D4_CMF
1
R6880
R6881 1
1
R6882 TMDS_DUAL TMDS_DUAL
10K
5% 301 4.99K R6802 R6803
1/16W 1% 1%
MF-LF 1/16W 1/16W 49.9 49.9
TMDS_DP<4> 1 2 1 2 TMDS_DN<4>
28
46
40
34
22
402 2 MF-LF MF-LF 57 55 55 57
VCC 3
402 2
2 402
Upper DVO series termination
PVCC1
PVCC2
AVCC
AVCC
VCC
1% 1%
1/16W 1/16W
MF-LF MF-LF
Place close to GPU 402 402
TMDS_DUAL
8 =I2C_SI_S_SCL 27 SCL MSEN 48 SI_S_MSEN
One for each of: GPU_DVOD<12..23>
=I2C_SI_S_SDA
C6802 1
8 26 SDA 0.001uF
SI_S_A1 10%
24 CTL3/A1 50V
CERM 2
TMDS_DUAL 54 11 =SI_TMDS_RESET_L 25 RST* 402
RP6821 54 SI_SYNC 47 SYNCO/SYNCI
TMDS_DUAL
10
=RP6821P1 1 8 =RP6821P8 SI_HTPLG TMDS_D5_CMF
6 6 54 44 EHTPLG TXC+ 33 NC
CRITICAL
5% TMDS_DUAL TXC- 32 NC TMDS_DUAL TMDS_DUAL
1/16W 55 6 GPU_DVOD<12> 18 D0 U6800
SM-LF RP6821 55 6 GPU_DVOD<13> 17 D1 SIL1178CS48 TX0+ 36 SI_TMDS_DP<3> 55
R6800 R6801
10 49.9 49.9
=RP6821P2 2 7 =RP6821P7 GPU_DVOD<14> SI_TMDS_DN<3> TMDS_DP<5> TMDS_DN<5>
6 6 55 6 16 D2 TSSOP TX0- 35 55 57 55 1 2 1 2 55 57
TMDS_DUAL 5% 55 6 GPU_DVOD<15> 15 D3 1% 1%
B RP6821
10
1/16W
SM-LF 55 6 GPU_DVOD<16> 14 D4
TX1+ 39
TX1- 38
SI_TMDS_DP<4>
SI_TMDS_DN<4>
55
55
1/16W
MF-LF
402
1/16W
MF-LF
402
B
3 6 55 6 GPU_DVOD<17> 13 D5
6 =RP6821P3 =RP6821P6 6 TMDS_DUAL
55 6 GPU_DVOD<18> 10 D6 TX2+ 42 SI_TMDS_DP<5> 55
5% TMDS_DUAL
GPU_DVOD<19> SI_TMDS_DN<5>
C6800 1
1/16W 55 6 9 D7 TX2- 41 55
0.001uF
SM-LF RP6821 55 6 GPU_DVOD<20> 8 D8 10%
10 50V
2
=RP6821P4 4 5 =RP6821P5 GPU_DVOD<21> CERM
6 6 55 6
7 D9 402
TMDS_DUAL 5% 55 6 GPU_DVOD<22> 6 D10
1/16W
RP6822 SM-LF 55 6 GPU_DVOD<23> 5 D11
10 55 54 6 GPU_DVO_DE 19 DE
6 =RP6822P1 1 8 =RP6822P8 6
54 6 GPU_DVO_HSYNC 20 HSYNC
5% TMDS_DUAL
GPU_DVO_VSYNC
EXT_SWING 30 SI_S_EXTSWING
1/16W 55 54 6
21 VSYNC
SM-LF RP6822 55 54 6 GPU_DVO_CLKP 12 IDCK+ VREF 2 SI_VREF 54
10
6 =RP6822P2 2 7 =RP6822P7 6 54 SI_IDCK_N 11 IDCK-
THRML
TMDS_DUAL 5%
PGND
PGND
AGND
AGND
AGND
1/16W
PAD
GND
GND
GND
RP6822 SM-LF
10
6 =RP6822P3 3 6 =RP6822P6 6
29
45
31
43
37
1
23
4
49
5% TMDS_DUAL
1/16W
SM-LF RP6822
10
=RP6822P4 4 5 =RP6822P5
6 6
TMDS_DUAL 5%
1/16W
RP6823 SM-LF
10
6 =RP6823P1 1 8 =RP6823P8 6
5%
1/16W
TMDS_DUAL Upper TMDS Transmitter
SM-LF RP6823
A 6 =RP6823P2 2
10
7 =RP6823P7 6
SYNC_MASTER=MARIAS

A
TMDS_DUAL 5%
1/16W
RP6823 SM-LF THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
6 =RP6823P3 3 6 =RP6823P6 6
5% TMDS_DUAL
1/16W II NOT TO REPRODUCE OR COPY IT
SM-LF RP6823 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
10
6 =RP6823P4 4 5 =RP6823P5 6
5%
1/16W
SM-LF
APPLE COMPUTER INC.
D 051-6839 F
SCALE SHT OF
NONE 68 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
LCD (LVDS) INTERFACE
10 =PP3V3_PWRON_LCD
C6900
2200pF
R69001 1 2
100K
5% 5%
1/16W
MF-LF 50V L6900 2 =GND_CHASSIS_LCD1
402 2 R6901
100K 2
CERM
603 4 FERR-250-OHM
1 2 CRITICAL
INVERTER INTERFACE
1 LCD_PWREN_L PP3V3_LCD_SW
5%
3 6 VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mm SM C6920 1
J6900
1/16W 5 MIN_NECK_WIDTH=0.25 mm MSC-RB30-5-FA
MF-LF C6901 1 0.001uF F-RT-SM L6952
402 2 20% 34 =PPBUS_INVERTER
LCD_DIGON_L 0.001uF 50V 10 FERR-1K-OHM-EMI
TSOP-LF 1 20% CERM 2
50V 402 2 1 PPBUS_INVERTER
SI3443DV CERM 2 1
7
3 Q6900 402 VOLTAGE=3.3V VOLTAGE=12.8V

C D
Q6901 2 =GND_CHASSIS_LCD2
7 PP3V3_LCD_CONN
2
3 10 =PP5V_PWRON_INVERTER Q6950
FDG6324L
SM MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm C
2N7002
PANEL_PWR_EN 1 G S
SOT23-LF 10 7 =PP3V3_DDC_LCD 4 SC70-6-LF
L6950
56 53
NC 5 3 400-OHM-EMI
2 R69101 1
R6911 6 R69501 4 S2 D2 2 PP5V_INV_SW_F 1 2 CRITICAL
100K pull-ups are for
no-panel case (development) 100K 100K 7 100K
5%
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm SM-1
1 C6952 J6950
SM-2MT-LF
Panel has 2K pull-ups 5% 5% 1/16W MIN_NECK_WIDTH=0.25 1
mm 0.001uF
1/16W
MF-LF
1/16W
MF-LF
53 7 LVDS_L0_N 8 MF-LF
402 2
G2 C6950 20%
50V
2 CERM
5
402 2 C6910 1 LVDS_L0_P 9 6 10UF

2 402 53 7
20% 402
0.001uF 10 FP_PWR_EN_L 6.3V
2 X5R 1
51 7 LVDS_DDC_CLK 20%
50V LVDS_L1_N 11 603 2
LVDS_DDC_DATA CERM 2 53 7
51 7 402 12 6 3
53 7 LVDS_L1_P 7 PP5V_INV_SW
NO STUFF 13 D1 VOLTAGE=5V 4
C6911 1 LVDS_L2_N 14 Q6950 MIN_NECK_WIDTH=0.25 mm
0.001uF 53 7
FDG6324L 1 C6951
20% LVDS_L2_P 15 PANEL_PWR_EN 5 G1 SC70-6-LF 6
50V
CERM 2
53 7 56 53
S1 L6953 0.001uF
16 20%
402 400-OHM-EMI 50V
2 CERM
53 7 CLKLVDS_L_N 17 1
1 2 402 7 BRIGHT_PWM
2 =GND_CHASSIS_LCD3 53 7 CLKLVDS_L_P 18
SM-1 7 GND_INVERTER
19 VOLTAGE=0V
10 =PP3V3_PWRON_INVERTER MIN_LINE_WIDTH=0.5 mm
53 7 LVDS_U0_N 20 MIN_NECK_WIDTH=0.25 mm
LVDS_U0_P 21
53 7
22 C6954 1 1 C6955 1
C6953 1 0.001uF 0.001uF
LVDS_U1_N 23 20% 20%
53 7
0.1uF 50V
CERM 2 2 50V
53 7 LVDS_U1_P 24 20%
10V U6953 402
CERM
402 L6955
25 CERM 2 FERR-250-OHM
26
402
1
5 NC7S32 SM
53 7 LVDS_U2_N 53 INV_ON_PWM A SC70-LF 2 =GND_CHASSIS_INVERTER1
53 7 LVDS_U2_P 27 4 BRIGHT_PWM_F
Y 2
B 53 7 CLKLVDS_U_N
28
29
2
B
3
INVERTER EXPECTS ACTIVE HIGH SIGNAL B
53 7 CLKLVDS_U_P 30
33
C6921
0.001uF
2 1
20%
50V
CERM
402 R6999
1
0 2
2 =GND_CHASSIS_LCD4 5%
1/16W
MF-LF
402
C6999
0.01uF
1 2
20%
=GND_CHASSIS_INVERTER2 2
50V
CERM
603
Internal Display Conns


A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 69 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TMDS FILTERING
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
SPACING PHYSICAL DIFFERENTIAL_PAIR

PLACE CLOSE TO CONNECTOR
CRITICAL
DVI DDC CURRENT LIMIT
(55mA requirement per DVI spec)
DVI INTERFACE
I548 TMDS_CONN TMDS_CONN TMDS_CONN_CLK TMDS_CONN_CLKP 57 L7000 CRITICAL
I549 TMDS_CONN TMDS_CONN TMDS_CONN_CLK TMDS_CONN_CLKN 57
90-OHM-300mA
2012H
SYM_VER-1
TMDS_EXT&TMDS_DUAL F7010 L7010
400-OHM-EMI
PP5V_RUN_DDC
VOLTAGE=5V
57
I550 TMDS_CONN TMDS_CONN TMDS_CONN_D0 TMDS_CONN_DP<0> 57

TMDS_DN<0> 1 4 TMDS_CONN_DN<0>
0.5AMP-13.2V MIN_LINE_WIDTH=0.38 mm
54 57
1 2 1 2 MIN_NECK_WIDTH=0.25 mm
I551 TMDS_CONN TMDS_CONN TMDS_CONN_D0 TMDS_CONN_DN<0> 57 10 =PP5V_RUN_DVI_DDC PP5V_RUN_DDC_FUSE
VOLTAGE=5V SM-1
I552 TMDS_CONN TMDS_CONN TMDS_CONN_D1 TMDS_CONN_DP<1> 57 MIN_LINE_WIDTH=0.38 mm
TMDS_CONN_DN<1> TMDS_DP<0> 2 3 TMDS_CONN_DP<0>
SM-LF MIN_NECK_WIDTH=0.25 mm Isolation required for DVI power switch
I553 TMDS_CONN TMDS_CONN TMDS_CONN_D1 57 54 57
I554 TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN_D2
TMDS_CONN_D2
TMDS_CONN_DP<2>
TMDS_CONN_DN<2>
57 CRITICAL
D7010 3V LEVEL SHIFTERS
I555
57
L7001
90-OHM-300mA
CRITICAL
SOD-123
1 2 PP5V_RUN_DDC_PULLUPS 57 10 =PP3V3_DDC_DVI
D I559 TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN
TMDS_CONN_D3
TMDS_CONN_D3
TMDS_CONN_DP<3>
TMDS_CONN_DN<3>
57
57
2012H
SYM_VER-1
TMDS_EXT&TMDS_DUAL J7000
QH81127-CK1
VOLTAGE=5V
D
I558
54 TMDS_DN<1> 1 4 TMDS_CONN_DN<1> 57 F-RT-TH-LF 36 B0530WXF 1
I560 TMDS_CONN TMDS_CONN TMDS_CONN_D4 TMDS_CONN_DP<4> 57
33 31 R7010 1 R7012 1
I561 TMDS_CONN TMDS_CONN TMDS_CONN_D4 TMDS_CONN_DN<4> 57 =GND_CHASSIS_DVI1 2 4.7K R7020
4.7K 5%
TMDS_CONN TMDS_CONN TMDS_CONN_D5 TMDS_CONN_DP<5> 57 TMDS_DP<1> 2 3 TMDS_CONN_DP<1> 5% 1/16W 10K
I562
TMDS_CONN TMDS_CONN TMDS_CONN_D5 TMDS_CONN_DN<5>
54
CRITICAL
57
1/16W
MF-LF
MF-LF Q7011 5 5%
2 402 1/16W
57
I563
57 TMDS_CONN_DN<0> 17 1 TMDS_CONN_DN<2> 57 402 2 2N7002DW-X-F MF-LF
G
L7002 9 TMDS_CONN_DN<1> 57
R7011 SOT-363
2 402
90-OHM-300mA
18 2
100 2 DVI_DDC_CLK3 D S 4
2012H TMDS_EXT&TMDS_DUAL 57 TMDS_CONN_DP<0> TMDS_CONN_DP<2> 57 1 GPU_DVI_DDC_CLK 51
SYM_VER-1
10 TMDS_CONN_DP<1> 57 5%
54 TMDS_DN<2> 1 4 TMDS_CONN_DN<2> 57 1/16W
19 3 1
11
1 C7011 MF-LF
402 R7021
100pF 10K
TMDS_DP<2> 2 3 TMDS_CONN_DP<2> TMDS_CONN_DN<5> 20 4 TMDS_CONN_DN<4> 57 5% Q7011 2 5%
1/16W
54 57 57 50V
2 CERM 2N7002DW-X-F MF-LF
12 TMDS_CONN_DN<3> 57 G
CRITICAL
21 5
402 R7013 SOT-363
2 402
L7006 57 TMDS_CONN_DP<5> TMDS_CONN_DP<4> 57
1
100 6 D
2 DVI_DDC_DATA S 1 GPU_DVI_DDC_DATA 51
370-OHM 13 TMDS_CONN_DP<3> 57
SM TMDS_EXT&TMDS_DUAL 22 6
5%
SYM_VER-1 57 DVI_DDC_CLK_UF 1/16W
1
54 TMDS_CLKP 1 4 TMDS_CONN_CLKP 57
14 (PP5V_RUN_DDC) 1 C7013 MF-LF
402 R7022
100pF 100K
57 TMDS_CONN_CLKP 23 7 DVI_DDC_DATA_UF
5% Q7014 5 5%
1/16W
15 2 50V 2N7002DW-X-F MF-LF
TMDS_CLKN 2 3 TMDS_CONN_CLKN CERM SOT-363 G
ANALOG FILTERING 54 57
57 TMDS_CONN_CLKN 24 8 VGA_VSYNC 57
402 R7014 2 402
CRITICAL 16 1
100 2 3 D S 4
57 DVI_HPD_UF DVI_HPD GPU_DVI_HPD 51
PLACE CLOSE TO CONNECTOR L7003

90-OHM-300mA VGA_B C3 C1 VGA_R
5%
1/16W
57 53 53 57 NOTE: Pulldown for DVI_HPD provided by DVI power switch interface
2012H TMDS_DUAL C5B C5A
MF-LF
SYM_VER-1 402
FL7040 55 TMDS_DN<3> 1 4 TMDS_CONN_DN<3> 57 57 VGA_HSYNC C4 C2 VGA_G 53 57 VGA SYNC BUFFERS
LCFILTER CRITICAL
SM-220MHZ-LF C7010 1 1 C7014 C7050
1 2 2 3 34 32 0.01uF 100pF 0.1uF
C 53 GPU_VGA_B VGA_B 53 57 55 TMDS_DP<3>
CRITICAL
TMDS_CONN_DP<3> 57
35
20%
50V
CERM 2
5%
50V
2 CERM
57 10 =PP3V3_PWRON_VGASYNC
1 2
C
3 4 1
R7040 L7004
603 402 U7050 20%
1 C7040 75 =GND_CHASSIS_DVI2
5
74AHC1G32 CERM
10V
FL7041 3.3pF 1%
NO STUFF 90-OHM-300mA
2012H TMDS_DUAL
2 PLACE NEAR C5A & C5B
53 GPU_VGA_VSYNC 1 SM-LF 402 R7050
0.25% 1/16W SYM_VER-1
R7030 33
LCFILTER CRITICAL 2 50V
CERM MF-LF 1 4
4 GPU_VSYNC_BUF 1 2 VGA_VSYNC 57
SM-220MHZ-LF 402 2 402 55 TMDS_DN<4> TMDS_CONN_DN<4> 57
2
0 1 2
=GND_CHASSIS_DVI3 2 32 5%
1/16W
53 GPU_VGA_G 1 2 VGA_G 53 57 5% MF-LF
1/16W 3 402
55 TMDS_DP<4> 2 3 TMDS_CONN_DP<4> 57 MF-LF PLACE R7050 & R7051 CLOSE TO DVI CONNECTOR
3 4 402
1
1 C7041 R7041 CRITICAL C7051
3.3pF 75 NO STUFF L7005 R7031 0.1uF
FL7042 0.25% 1%
1/16W 90-OHM-300mA 0 57 10 =PP3V3_PWRON_VGASYNC
1 2
LCFILTER CRITICAL 2 50V
CERM MF-LF 2012H TMDS_DUAL 2 1 =GND_CHASSIS_DVI4 2
SM-220MHZ-LF 402 2 402
TMDS_DN<5> 1
SYM_VER-1
4 TMDS_CONN_DN<5>
5%
1/16W 5
U7051 20%
10V
55 57
GPU_VGA_R 1 2 VGA_R 74AHC1G32 CERM
53 53 57 MF-LF
402 53 GPU_VGA_HSYNC 1 SM-LF 402 R7051
4 GPU_HSYNC_BUF1
33 2 VGA_HSYNC
3 4 1 2 3 PLACE NEAR 3, 11 & 19 57
1 C7042 R7042 55 TMDS_DP<5> TMDS_CONN_DP<5> 57
2 32 5%
3.3pF 75 NO STUFF 1/16W
1% MF-LF
0.25% 1/16W 3 402
2 50V
CERM MF-LF
402 2 402
DVI POWER SWITCH

Power key detect path when
system is shutdown or asleep.. 57 PP5V_RUN_DDC
DDC_CLK is isolated from
GPU during shutdown. When
power key on remote device Q7081 SYS_POWER_BUTTON_L 24 25 30 36
S-VIDEO/COMP OUT INTERFACE is pressed, 5V will be driven

into DDC_CLK. Since host rails
will be low, TP0610 will turn G
1
TP0610
S0T23-3
Place GND shorts at
on, driving SYS_POWER_BUTTON_L low.
As host rails rise, TP0610 R7081 R7083 3
B graphics controller will turn off, as will remote

device path into DDC_CLK. DVI_DDC_CLK_UF 2 S D 3 DVI_TURN_ON 2
680 1 DVI_TURN_ON_ILIM 1
10K 2 DVI_TURN_ON_BASE 5 Q7080 B
Isolation will be disabled as well.
57
MMDT3904XF
5% 5% SOT-363-LF
XW7060 L7060 1/16W
1
1/16W
4
SM
FERR-10-OHM-500MA MF-LF
402 R7082 MF-LF
402
57 10 =PP3V3_DDC_DVI 330
GND_GPU_TV1 GND_TV1 5% Pulldown prevents
VOLTAGE=0V SM
VOLTAGE=0V 1/16W 3904 from turning
MIN_LINE_WIDTH=0.25 mm MIN_LINE_WIDTH=0.25 mm MF-LF on when DVI monitor
MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm 1
1 C7070 402 2 has active, self-
C7060 R7072 0.1uF
20%
powered DDC clock
pullup.
0.01uF Power key detect path 68.1K 10V
20% when system is running. 1% 2 CERM
HPD normally driven to 1/16W
L7062 50V
CERM 3.3V. When power key MF-LF
402
3.3uH 603 on remote device pressed,
HPD will be driven to 5V.
402 2
Comparator output enabled
53 GPU_TV_Y 53 TV_Y by GPU.
0603
HPD_4V_REF
4
2 U7070
CRITICAL LMC7211 R7078 R7080 6
C7062 C7063 J7060
V+ SM-LF
1 HPD_PWR_SW 3 4 HPD_ON 1
330 2 HPD_ON_RC 1
20K 2 HPD_BASE 2
Q7080
560pF
10%
560pF
10% MINIDIN
R7070 D S MMDT3904XF
SOT-363-LF
10K Q7076 5% 5%
50V
CERM L7064 50V
CERM
RT-TH-LF
MH11773-MR8N-7F 57 DVI_HPD_UF 1 2 DVI_HPD_DIV 3 V-
2N7002DW-X-F
1/16W
MF-LF
1/16W
MF-LF 1
402 3.3uH 402 1% 5
G
SOT-363 402 402
1/16W
53 GPU_TV_C 53 TV_C 4 3 MF-LF Q7075 5
C7079 1
1
R7079
0603 2 1 402
R70731 TP0610 47UF 68K
5 R70711 100K S0T23-3
20% 5%
1% 1/16W
C7064 C7065 10K
1%
1/16W
MF-LF
10 =PPBUS_DVI_PWRSW 2
S D
3 COMP_ENABLE 6.3V
CERM 2 MF-LF
560pF 560pF 8 9 1/16W 402 2 1210 2 402
10% 10%
50V
CERM L7066 50V
CERM
10 11 MF-LF
402 2
R70751 G R70771
402 3.3uH 402 100K
5% 100K
1/16W 5%
GPU_TV_COMP TV_COMP
53
0603
53 MF-LF
402 2
1/16W
MF-LF
402 2
External Display Conns
COMP_DISABLE
A C7066
560pF
C7067
560pF
Q16C/514-0265/MH11773-MR8A-7F
Q41C/514-0256/MH11773-MR8N-7F 6
SYNC_MASTER=MARIAS-PDIFF

A
10% 10% NEED PULL-DOWN BECAUSE THIS
XW7061
50V
CERM L7061 50V
CERM SIGNAL IS TRISTATED INITIALLY D
Q7076
SM
402 FERR-10-OHM-500MA 402 2N7002DW-X-F THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
SOT-363 AGREES TO THE FOLLOWING
GND_GPU_TV2 GND_TV2 51 HPD_PWR_SNS_EN 2 G S
VOLTAGE=0V SM VOLTAGE=0V I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MIN_LINE_WIDTH=0.25 mm MIN_LINE_WIDTH=0.25 mm 1
MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm R7076 1 II NOT TO REPRODUCE OR COPY IT
C7061 100K
5%
0.01uF 1/16W
20% MF-LF SIZE DRAWING NUMBER REV.
Place GND shorts at 50V
402 2
051-6839 F
CERM
graphics controller 603
APPLE COMPUTER INC.
D
SCALE SHT OF
=GND_CHASSIS_TV
2
NONE 70 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Page Notes
- =PP3V3_PCI_ROM

- =ROM_PWD_L

(NONE)
NOTE: This page does not specify a

BootROM part number. Must use a
D TABLE_x_ITEM symbol to declare D
U7100 part number.
58 10 =PP3V3_PCI_ROM
C7100 1
C7101 1
C7102 1
2.2uF 0.1uF 0.1uF

10% 20% 20%
6.3V 10V 10V
X5R 2 CERM 2 CERM 2
603 402 402
11 30 31
C VPP VCC
U7100
C
62 61 60 59 11 BI PCI_AD<20:0> 1MX8-3.3V-90.0NS PCI_AD<31:24> BI 59 60 61 62
0 21 25 24
A0 TSOP DQ0
1 20 26 25
A1 OMIT DQ1
2 19 27 26
A2 DQ2
3 18 28 27
A3 DQ3
4 17 32 28
A4 DQ4
5 16 33 29
A5 DQ5
6 15 34 30
A6 DQ6
7 14 35 31
A7 DQ7
8 8
A8
9 7
A9
=PP3V3_PCI_ROM 10 36
58 10
A10
11 6
A11
12 5
1 1
A12
4
R7150 R7151 13
A13
10K 10K 14 3
5% 5% A14
1/16W 1/16W 15 2
MF-LF MF-LF A15
1
402 2 R7152 2 402
16
A16
470 17 40
60 59 IN ROM_CS_L 1 2 A17
18 13
5% A18
Allows ROM override module 1/16W 19 37
MF-LF A19
to intercept ROM chip select 402 20 38
A20
60 ROM_ONBOARD_CS_L 22
IN CE
60 59 ROM_OE_L 24
OE
B 60 59
IN
IN ROM_WE_L 9
WE B
ROM_WP_L 12
WP
11 =ROM_PWD_L 10
IN PWD
GND
23 39
BootROM

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 71 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE

PCI PULL-UPS
10 =PP3V3_PCI
PCI_CLK_SLOTA CLOCK CLOCK TP_PCI_CLK33M_SLOTA_R 11 59
PCI_CLK_SLOTD CLOCK CLOCK TP_PCI_CLK33M_SLOTD_R 11 59 RP7250

10K
I2_PCI_FBCLK I2_FBCLK I2_FBCLK I2_PCI_FBCLK_OUT_R =RP7250P1 1 8
59 6
I2_FBCLK I2_FBCLK I2_PCI_FBCLK_OUT 21 59 5%

1/16W RP7250
SM-LF 10K
PCI_AD16_0 PCI PCI PCI_AD<16..0> 58 59 60 61 62 (BOOTROM ADDR) One resistor for each of: 2 7
6 =RP7250P2
PCI_AD17 PCI PCI PCI_AD<17> 11 58 59 60 61 (BOOTROM ADDR/SLOT A IDSEL) - PCI_FRAME_L
62 5%
PCI_AD19_18 PCI PCI PCI_AD<19..18> 58 59 60 61 62 (BOOTROM ADDR) - PCI_TRDY_L RP7250 1/16W
SM-LF
PCI_AD20 PCI PCI PCI_AD<20> 11 58 59 60 61 (SLOT D IDSEL) - PCI_IRDY_L 10K
62 =RP7250P3 3 6
6
D PCI_AD21
PCI_AD23_22
PCI
PCI
PCI
PCI
PCI_AD<21>
PCI_AD<23..22>
11 59 60 61 62
59 60 61 62
(SLOT E IDSEL)
(PCI ONLY)
- PCI_STOP_L
5%
1/16W RP7250
D
SM-LF
PCI_AD31_24 PCI PCI PCI_AD<31..24> 58 59 60 61 62 (BOOTROM DATA) 10K
6 =RP7250P4 4 5
PCI_CBE PCI PCI PCI_CBE_L<3..0> 59 60 61 62 5%
PCI_CTL PCI PCI PCI_FRAME_L 6 59 60 61 62

R7252 1/16W
SM-LF
10K
PCI_CTL PCI PCI PCI_DEVSEL_L 59 60 61 62 62 61 60 59 PCI_DEVSEL_L 1 2
PCI_CTL PCI PCI PCI_IRDY_L 6 59 60 61 62 5%

1/16W
PCI_CTL PCI PCI PCI_TRDY_L 6 59 60 61 62 MF-LF
402
PCI_CTL PCI PCI PCI_STOP_L 6 59 60 61 62
OMIT
PCI_PAR PCI PCI PCI_PAR 59 60 61 62
U2100 R7253
10K
PCI PCI PCI_SLOTA_REQ_L 11 59 I2 22 11 PCI_SLOTA_INT_L 1 2
PCI PCI PCI_SLOTA_GNT_L 11 59 BGA 5%

1/16W
PCI PCI PCI_SLOTD_REQ_L 11 59 PCI/ROM INTERFACE R7254 MF-LF
10K 402
PCI PCI PCI_SLOTD_GNT_L 11 59 (10 of 14) 22 11 PCI_SLOTD_INT_L 1 2
5%
ROM INTERFACE 1/16W
MF-LF
AP33 ROM_CS_L
ROM_CS_L 58 60 402
Page Notes ROM_OE_L AM31
AN34
ROM_OE_L
ROM_WE_L
58 60

ROM_WE_L 58 60 RP7251
10K
- =PP3V3_PCI PCI DEVICE 0 6 =RP7251P2 2 7
AL25 TP_PCI_CLK33M_SLOTA_R
PCI_CLK_0_H 11 59 5%
Signal aliases required by this page: RP7251 1/16W
SM-LF
- =I2_PCI_FBCLK_IN - PCI feedback clock One resistor for each of: 10K
PCI_SLOTA_REQ_L AR21 AL19 PCI_SLOTA_GNT_L =RP7251P1 1 8
59 11 PCI_REQ_0_L PCI_GNT_0_L 11 59 6
input. Length should match that of - PCI_SLOTA_GNT_L
"Slot A" - AD17 5%
longest clock from I2 to PCI device. PCI DEVICE 1 - PCI_SLOTA_REQ_L 1/16W RP7251
SM-LF
PCI_CLK_1_H AR27 TP_PCI_CLK33M_SLOTD_R 11 59 - PCI_SLOTD_GNT_L 10K
C BOM options provided by this page:
(NONE)
PCI_SLOTD_REQ_L AT20 AN21 PCI_SLOTD_GNT_L
- PCI_SLOTD_REQ_L
6 =RP7251P3 3
5%
6
C
59 11 PCI_REQ_1_L PCI_GNT_1_L 11 59 RP7251 1/16W
SM-LF
"Slot D" - AD20 10K
PCI INTERFACE 6 =RP7251P4 4 5
PCI_PAR AP28 AP31 PCI_AD<0>

62 61 60 59 PCI_PAR_H PCI_AD_00_H 58 59 60 61 62 5%
AT24 AT32 1/16W
62 61 60 59 6 PCI_FRAME_L PCI_FRAME_L PCI_AD_01_H PCI_AD<1> 58 59 60 61 62 SM-LF
PCI_TRDY_L AN24 AT31 PCI_AD<2>
62 61 60 59 6 PCI_TRDY_L PCI_AD_02_H 58 59 60 61 62
AR25 AP30
62 61 60 59 6 PCI_IRDY_L PCI_IRDY_L PCI_AD_03_H PCI_AD<3> 58 59 60 61 62 SLOT E REQ/GNT pull-ups
PCI_STOP_L AP27 AN28 PCI_AD<4>
62 61 60 59 6 PCI_STOP_L PCI_AD_04_H 58 59 60 61 62
PCI_DEVSEL_L AM25 AT34 PCI_AD<5>

not provided by this page.
62 61 60 59 PCI_DEVSEL_L PCI_AD_05_H 58 59 60 61 62
AN30 PCI_AD<6>
PCI_AD_06_H 58 59 60 61 62
AR31 PCI_AD<7>
PCI_AD_07_H 58 59 60 61 62
AR30 PCI_CBE_L<0>
PCI_CBE_0_L 59 60 61 62
AM27 PCI_AD<8>
PCI_AD_08_H 58 59 60 61 62
AM30 PCI_AD<9>
PCI_AD_09_H 58 59 60 61 62
AT28 PCI_AD<10>
PCI_AD_10_H 58 59 60 61 62
AT30 PCI_AD<11>
PCI_AD_11_H 58 59 60 61 62
AN27 PCI_AD<12>
PCI_AD_12_H 58 59 60 61 62
AT27 PCI_AD<13>
PCI_AD_13_H 58 59 60 61 62
AN25 PCI_AD<14>
PCI_AD_14_H 58 59 60 61 62
AR28 PCI_AD<15>
PCI_AD_15_H 58 59 60 61 62
AT29 PCI_CBE_L<1>
PCI_CBE_1_L 59 60 61 62
AP25 PCI_AD<16>
PCI_AD_16_H 58 59 60 61 62
AL22 PCI_AD<17>
PCI_AD_17_H 11 58 59 60 61 62
AT26 PCI_AD<18>
PCI_AD_18_H 58 59 60 61 62
B PCI_AD_19_H AP24
AR24
PCI_AD<19> 58 59 60 61 62 B
PCI_AD_20_H PCI_AD<20> 11 58 59 60 61 62
AT25 PCI_AD<21>
PCI_AD_21_H 11 59 60 61 62
AK22 PCI_AD<22>
PCI_AD_22_H 59 60 61 62
AT23 PCI_AD<23>
PCI_AD_23_H 59 60 61 62
AM24 PCI_CBE_L<2>
PCI_CBE_2_L 59 60 61 62
AM21 PCI_AD<24>
PCI_AD_24_H 58 59 60 61 62
AP22 PCI_AD<25>
PCI_AD_25_H 58 59 60 61 62
AN22 PCI_AD<26>
PCI_AD_26_H 58 59 60 61 62
AR22 PCI_AD<27>
PCI_AD_27_H 58 59 60 61 62
AK21 PCI_AD<28>
PCI_AD_28_H 58 59 60 61 62
AL21 PCI_AD<29>
PCI_AD_29_H 58 59 60 61 62
AT22 PCI_AD<30>
PCI_AD_30_H 58 59 60 61 62
AP21 PCI_AD<31>
PCI_AD_31_H 58 59 60 61 62
AM22 PCI_CBE_L<3>
PCI_CBE_3_L 59 60 61 62
21 =I2_PCI_FBCLK_IN AM28
PCI_FB_CLK_IN_H PCI_FBCLK_OUT_H AE23 R7205
33
59 I2_PCI_FBCLK_OUT_R 1 2 I2_PCI_FBCLK_OUT 21 59
3.3V IN 3.3V OUT 5%

1/16W
Output Impedance is about 20 Ohms MF-LF
402
I2 PCI Interface

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 72 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
I315 CLOCK CLOCK =PCI_CLK33M_AIRPORT 11 60
Page Notes
- =PP3V3_PCI (802.11g Power)
- =PP3V3_PWRON_BT (Bluetooth Power)
- =PCI_CLK33M_AIRPORT (33MHz PCI clock)
D - =PCI_AIRPORT_RESET_L (PCI Reset) D
- =USB_BT_P (Bluetooth USB D+)
- =USB_BT_N (Bluetooth USB D-)
(NONE)
PCI Devices implemented on this page:
AD17 (Slot "A") - AirPort (0x????/0x????)
NOTE: This AirPort implementation does
not support PME#.
CRITICAL
J7300
CPB7280-1210
M-ST-SM-LF
81
10 =PP3V3_PWRON_BT =PP3V3_PCI_AIRPORT 10
1 2 PCI_AD<31> 58 59 61 62
62 61 59 58 PCI_AD<30> 3 4 AIRPORT_CLKRUN_L_PD
5 6 TP_AIRPORT_PME_L
PCI_AD<27> 7 8 =PCI_AIRPORT_GNT_L 1
62 61 59 58 11
R7305
11 =PCI_AIRPORT_REQ_L 9 10 10K
5%
PCI_AD<25>
C 62 61 59 58
62 61 59 58 PCI_AD<29>
11
13
12
14 PCI_AD<24> 58 59 61 62
1/16W
MF-LF
2 402
C
15 16 =PCI_AIRPORT_RESET_L 11
62 61 59 PCI_CBE_L<3> 17 18 PCI_AD<28> 58 59 61 62
62 61 59 58 PCI_AD<26> 19 20
R7300 62 61 59 PCI_AD<22> 21 22 PCI_AD<23> 59 61 62
22
11 =PCI_AIRPORT_IDSEL 1 2 PCI_AIRPORT_IDSEL 23 24
5% 25 26 PCI_AD<20> 11 58 59 61 62
1/16W
MF-LF 62 61 59 58 PCI_AD<19> 27 28 PCI_FRAME_L 6 59 61 62
402
62 61 59 11 PCI_AD<21> 29 30 PCI_AD<17> 11 58 59 61 62
62 61 59 6 PCI_IRDY_L 31 32
62 61 59 58 PCI_AD<18> 33 34 PCI_TRDY_L 6 59 61 62
62 61 59 PCI_DEVSEL_L 35 36
37 38 PCI_CBE_L<2> 59 61 62
60 11 =PCI_CLK33M_AIRPORT 39 40 PCI_AD<16> 58 59 61 62
62 61 59 6 PCI_STOP_L 41 42
62 61 59 58 PCI_AD<12> 43 44 NC
62 61 59 PCI_PAR 45 46
47 48 PCI_AD<14> 58 59 61 62
62 61 59 58 PCI_AD<8> 49 50 PCI_AD<13> 58 59 61 62
62 61 59 58 PCI_AD<9> 51 52
62 61 59 PCI_CBE_L<0> 53 54 PCI_AD<10> 58 59 61 62
55 56 PCI_AD<15> 58 59 61 62
62 61 59 58 PCI_AD<7> 57 58 TP_AIRPORT_ALT_ANTENNA
62 61 59 58 PCI_AD<3> 59 60 PCI_CBE_L<1> 59 61 62
62 61 59 58 PCI_AD<6> 61 62 PCI_AD<4> 58 59 61 62
63 64
B 62 61 59 58 PCI_AD<1> 65 66 PCI_AD<11> 58 59 61 62 B
62 61 59 58 PCI_AD<5> 67 68 ROM_WE_L 58 59
62 61 59 58 PCI_AD<0> 69 70 PCI_AD<2> 58 59 61 62
11 USB_BT_P 71 72
11 USB_BT_N 73 74 =PCI_AIRPORT_INT_L 11
75 76 ROM_OE_L 58 59
77 78 ROM_ONBOARD_CS_L 58
79 80 ROM_CS_L 58 59
82
Q85 Connector
Q16C/516S0361/F-ST-SM
Q41C/516S0352/M-ST-SM-LF
Q85 AIRPORT/BT CONN

A SYNC_MASTER=MARIAS-MDIFF

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 73 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
10 =PP3V3_RUN_PCI1510_R
NET_TYPE
1 ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL DIFFERENTIAL_PAIR
R7400
0 I192 CLOCK CLOCK =PCI_CLK33M_CBUS 11 61
5%
1/10W
MF-LF
2 603
61 PP3V3_RUN_PCI1510
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5 mm 10 =PP5V_PWRON_TPS2211
1 C7400 1 C7401 1 C7402 1 C7403 1 C7404 10 =PP3V3_PWRON_TPS2211
10UF 10UF 0.22UF 0.22UF 0.22UF
20% 20% 10% 10% 10%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R MAKE SURE VCC AND VPP ARE WIDE PLANE/TRACES
D
603 603 402 402 402
U7450 TO MINIMIZE INDUCTANCE! D
10 =TPS2211_SHDN_L TPS2211
NC 9 10 PPVPP_CBUS_SW 61
V_12 SSOI AVPP VOLTAGE=3.3V
1 C7405 1 C7406 1 C7407 1 C7408 6
V_5_1
PPVCC_CBUS_SW 61
0.22UF 0.22UF 0.22UF 0.22UF R74501 V_5_2 AVCC0 VOLTAGE=3.3V
10% 10% 10% 10% 3 12 MIN_LINE_WIDTH=0.5 mm
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 0 V_3_1 AVCC1 MIN_NECK_WIDTH=0.25 mm
5% 4 13
402 402 402 402 1/16W V_3_2 AVCC2
MF-LF
R7410 1 402 2 1
VCCD0 C7450 1 1 C7451
10K 2 0.1uF 0.1uF
5% VCCD1 20%
10V
20%
10V
15
1/16W
MF-LF VPPD0 CERM 2 2 CERM
402 14 402 402
2 VPPD1
TPS2211_SHTDWN_L 16
A7 C13 D5 E1 M1 N7 N11
SHTDWN
10 =PP2V5_RUN_PCI1510 7 8 NC
GND OC
VCC
1 C7410 1 C7411 NC H10
CLK_48_RSVD/NC CRITICAL CLAMP FOR PC-CARDVCCCB B11
0.1UF ARE USED TO INCREASE ESD DISCHARGES OF UP TO 10KV
4.7uF 0.22UF
20% 10% VCCP L3
6.3V
2 CERM
6.3V
2 CERM-X5R PCI1510_VR_EN_L D4 VR_EN* U7400 CLAMP FOR PCI
805 402 L8 VR_PORT PCI1510ZGU VCCD0* N13 CBUS_VCCD0_L
BGA-LF
VCCD1* L12 CBUS_VCCD1_L
62 60 59 58 PCI_AD<0> N8 AD0
PCI_AD<1> M7 AD1 VPPD0 K9 CBUS_VPPD0
62 60 59 58
62 60 59 58 PCI_AD<2> L7 AD2 VPPD1 M11 CBUS_VPPD1

PC CARD/CARDBUS CONNECTOR
62 60 59 58 PCI_AD<3> N6 AD3 L13 CBUS_DET_1_L 61
PCI_AD<4> K4 AD4 CD1*/CCD1*
62 60 59 58 CRITICAL
AD5 CD2*/CCD2* B5 CBUS_DET_2_L 61
62 60 59 58 PCI_AD<5> M6
IORD*/CAD13 F12 CBUS_IORD_L 61 J7490
62 60 59 58 PCI_AD<6> L6 AD6 C11
QT500806-L121-9F
C 62 60 59 58
62 60 59 58
PCI_AD<7>
PCI_AD<8>
N5
N4
AD7
AD8
IOWR*/CAD15
OE*/CAD11 G10
CBUS_IOWR_L 61
CBUS_OE_L 61
M-ST-SM
84 81 C
CE1*/CC/BE0* H13 CBUS_CE1_L 61
62 60 59 58 PCI_AD<9> M2 AD9
VS1*/CVS1 B2 CBUS_VS1 2 1 CBUS_DATA<3>
PCI1510 PULL-UPS 62 60 59 58 PCI_AD<10> M5 AD10 VS2*/CVS2 A9 CBUS_VS2
61
61 61 CBUS_DET_1_L 4 3 CBUS_DATA<4>
61
61
62 60 59 58 PCI_AD<11> L4 AD11 WE*/CGNT* D13 CBUS_WE_L 61 61 CBUS_DATA<11> 6 5 CBUS_DATA<5> 61
62 60 59 58 PCI_AD<12> N3 AD12
PP3V3_RUN_PCI1510 61
PCI_AD<13> K5 RDY/IREQ*/CINT* A6 CBUS_READY 61 61 CBUS_DATA<12> 8 7 CBUS_DATA<6> 61
62 60 59 58 AD13 RESET/CRST* D8 CBUS_RESET_L 61 61 CBUS_DATA<13> 10 9
L5
R7420 62 60 59 58 PCI_AD<14> AD14 REG*/CC/BE3* A8 CBUS_REG_L 61 12 11 CBUS_DATA<7> 61
10K 62 60 59 58 PCI_AD<15> M4 AD15
1 2 PCI_PERR_L 61
PCI_AD<16> J4
BVD1/CSTSCHG/STSCHG*/RI* C6 CBUS_BVD1_L 61 61 CBUS_DATA<14> 14 13 CBUS_CE1_L 61
5%
62 60 59 58 AD16 BVD2/SPKR*/CAUDIO D6 CBUS_BVD2_L 61 61 CBUS_DATA<15> 16 15 CBUS_ADDR<10> 61
H1
R7421 1/16W
MF-LF
62 60 59 58 11 PCI_AD<17> AD17 INTEGRATED PULL-UP WP/IOIS16*/CCLKRUN* A5 CBUS_WP_L 61 61 CBUS_CE2_L 18 17 CBUS_OE_L 61
10K 402 62 60 59 58 PCI_AD<18> H3 AD18 G13
1 2 PCI_SERR_L 61
PCI_AD<19> H2
CE2/CAD10* CBUS_CE2_L 61 61 CBUS_VS1 20 19
5%
62 60 59 58 AD19 INPACK/CREQ* B8 CBUS_INPACK_L 61 22 21 CBUS_ADDR<11> 61
G2
1/16W
MF-LF R7422 62 60 59 58 11 PCI_AD<20> AD20 WAIT/CSERR* B6 CBUS_WAIT_L 61 61 CBUS_IORD_L 24 23 CBUS_ADDR<9> 61
402
1
10K 2 CBUS_SUSPEND_PU
62 60 59 11 PCI_AD<21> G4 AD21 CBUS_IOWR_L 26 25 CBUS_ADDR<8> 61
61 61
62 60 59 PCI_AD<22> F1 AD22 A0/CAD26 C7 CBUS_ADDR<0> 61
5% 61 CBUS_ADDR<17> 28 27 CBUS_ADDR<13> 61
1/16W 62 60 59 PCI_AD<23> C3 AD23 A1/CAD25 D7 CBUS_ADDR<1> 61
MF-LF 61 CBUS_ADDR<18> 30 29
402 62 60 59 58 PCI_AD<24> F3 AD24 A2/CAD24 B7 CBUS_ADDR<2> 61
32 31 CBUS_ADDR<14> 61
62 60 59 58 PCI_AD<25> E2 AD25 A3/CAD23 D10 CBUS_ADDR<3> 61
61 CBUS_ADDR<19> 34 33 CBUS_WE_L 61
62 60 59 58 PCI_AD<26> F4 AD26 A4/CAD22 B12 CBUS_ADDR<4> 61
61 CBUS_ADDR<20> 36 35 CBUS_READY 61
62 60 59 58 PCI_AD<27> B1 AD27 A5/CAD21 C8 CBUS_ADDR<5> 61
61 CBUS_ADDR<21> 38 37 PPVCC_CBUS_SW 61
62 60 59 58 PCI_AD<28> D2 AD28 A6/CAD20 C9 CBUS_ADDR<6> 61 TI REFERENCE SCHEMATIC DID NOT HAVE BULK ON PPVCC_CBUS_SW
61 PPVCC_CBUS_SW 40 39
62 60 59 58 PCI_AD<29> E4 AD29 A7/CAD18 A12 CBUS_ADDR<7> 61
42 41 PPVPP_CBUS_SW 61
62 60 59 58 PCI_AD<30> D3 AD30 A8/CC/BE1* E11 CBUS_ADDR<8> 61
PPVPP_CBUS_SW 44 43 CBUS_ADDR<16>
62 60 59 58 PCI_AD<31> E3 AD31 A9/CAD14 F11 CBUS_ADDR<9> 61 1 C7490 1 C7491 61
CBUS_ADDR<22> 46 45 CBUS_ADDR<15>
61
A10/CAD9 G11 CBUS_ADDR<10> 61 2.2uF 2.2uF 61 61
11 =PCI_CBUS_IDSEL 62 60 59 PCI_CBE_L<0> K6 C/BE0* 10% 10% 61 CBUS_ADDR<23> 48 47 CBUS_ADDR<12> 61
B 62 60 59 PCI_CBE_L<1> M3
J2
C/BE1*
A11/CAD12 G12
A12/CC/BE2* D9
CBUS_ADDR<11> 61
CBUS_ADDR<12> 61
2 6.3V
X5R
603
2 6.3V
X5R
603 61 CBUS_ADDR<24> 50 49 B
62 60 59 PCI_CBE_L<2> C/BE2* 52 51 CBUS_ADDR<7> 61
R74231 62 60 59 PCI_CBE_L<3> A1 C/BE3*
A13/CPAR E12 CBUS_ADDR<13> 61
61 CBUS_ADDR<25> 54 53 CBUS_ADDR<6> 61
22 A14/CPERR* D12 CBUS_ADDR<14> 61
5%
1/16W 62 60 59 PCI_PAR N1 PAR A15/CIRDY* C10 CBUS_ADDR<15> 61 R7430 61 CBUS_VS2 56 55 CBUS_ADDR<5> 61
MF-LF
K1
47 61 CBUS_RESET_L 58 57 CBUS_ADDR<4> 61
402 2 62 60 59 6 PCI_IRDY_L IRDY A16/CCLK B13 CBUS_ADDR_16_R 1 2 CBUS_ADDR<16> 61
CBUS_WAIT_L 60 59
61
61 PCI_SERR_L L2 SERR A17/CAD16 F10 CBUS_ADDR<17> 61 5%
1/16W 62 61 CBUS_ADDR<3> 61
PCI_CBUS_IDSEL F2 IDSEL A18/RSVD E13 CBUS_ADDR<18> 61 MF-LF
402 61 CBUS_INPACK_L 64 63 CBUS_ADDR<2> 61
61 PCI_PERR_L K3 PERR A19/CBLOCK* A13 CBUS_ADDR<19> 61
61 CBUS_REG_L 66 65 CBUS_ADDR<1> 61
62 60 59 6 PCI_FRAME_L J1 FRAME A20/CSTOP* E10 CBUS_ADDR<20> 61
61 CBUS_BVD2_L 68 67 CBUS_ADDR<0> 61
62 60 59 6 PCI_STOP_L L1 STOP A21/CDEVSEL* D11 CBUS_ADDR<21> 61
61 CBUS_BVD1_L 70 69
62 60 59 6 PCI_TRDY_L J3 TRDY A22/CTRDY* C12 CBUS_ADDR<22> 61
R7424 62 60 59 PCI_DEVSEL_L K2 DEVSEL A23/CFRAME* A10 CBUS_ADDR<23> 61
CBUS_DATA<8>
72 71 CBUS_DATA<0>
CBUS_DATA<1>
61
47 61 74 73 61
11 =PCI_CBUS_RESET_L 1 2 G3
PCI_CBUS_RESET_L PRST A24/CAD17 B10 CBUS_ADDR<24> 61
61 CBUS_DATA<9> 76 75 CBUS_DATA<2> 61
5% 11 =PCI_CBUS_REQ_LC2 REQ A25/CAD19 B9 CBUS_ADDR<25> 61
1/16W 61 CBUS_DATA<10> 78 77 CBUS_WP_L 61
MF-LF 11 =PCI_CBUS_GNT_LC1 GNT
402
=PCI_CLK33M_CBUSG1
D0/CAD27 A4 CBUS_DATA<0> 61 61 CBUS_DET_2_L 80 79
61 11 PCLK C4
D1/CAD29 CBUS_DATA<1> 61
D2/RSVD A3 CBUS_DATA<2> 61 83 82
NC M9 SPKROUT D3/CAD0 K11 CBUS_DATA<3> 61

RP7410 NC M8 RI_OUT/PME D4/CAD1 K12 CBUS_DATA<4> 61
10K 61 N10
CBUS_SUSPEND_PU SUSPEND D5/CAD3 J13 CBUS_DATA<5> 61
5% J10
1 8 CBUS_MFUNC5_PD =PCI_CBUS_INT_L K7 MFUNC0 D6/CAD5 CBUS_DATA<6> 61
61 11
D7/CAD7 H12 CBUS_DATA<7> 61
2 7 CBUS_MFUNC6_PD 61 61 CBUS_MFUNC1_PD N9 MFUNC1
3
4
6
5
CBUS_MFUNC3_PD 61 61 CBUS_MFUNC2_PD L9 MFUNC2
D8/CAD28
D9/CAD30
C5
B4
CBUS_DATA<8> 61
CBUS_DATA<9> 61
Cardbus
CBUS_MFUNC1_PD 61 61 CBUS_MFUNC3_PD K10 MFUNC3
D10/CAD31 B3 CBUS_DATA<10> 61
A 1/16W
SM-LF
61
61
CBUS_MFUNC4_PD M10
CBUS_MFUNC5_PD N12
MFUNC4
MFUNC5
D11/CAD2 M12 CBUS_DATA<11> 61
SYNC_MASTER=MARIAS

A
D12/CAD4 J11 CBUS_DATA<12> 61
R7411 61 CBUS_MFUNC6_PD L10 MFUNC6
10K D13/CAD6 K13 CBUS_DATA<13> 61 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1 2 CBUS_MFUNC4_PD 61 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
D14/RSVD J12 CBUS_DATA<14> 61 AGREES TO THE FOLLOWING
5% L11 GRST
1/16W D15/CAD8 H11 CBUS_DATA<15> 61 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MF-LF GND
402 II NOT TO REPRODUCE OR COPY IT
R7412 A2 A11 D1 F13 H4 K8 M13 N2 III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
10K
1 2 CBUS_MFUNC2_PD 61 SIZE DRAWING NUMBER REV.
5%
1/16W
MF-LF
402 APPLE COMPUTER INC.
D 051-6839 F
SCALE SHT OF
NONE 74 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
I6 CLOCK CLOCK =PCI_CLK33M_USB2 11 62
Page Notes
- =PPVIO_PCI (to 3.3V or 5V)
- =PP3V3_PCI_USB2 (D3cold rail)
D - =PCI_CLK33M_USB2
- =PCI_USB2_REQ_L - =PCI_USB2_IDSEL
D
- =PCI_USB2_GNT_L - =PCI_USB2_RESET_L 10 =PPVIO_PCI_USB2
- =PCI_USB2_INT_L
USB2_NEC
- USB2_NEC
C7500 1
0.1uF
20%
10V
PCI Devices implemented on this page: CERM 2
AD27 (Slot "G") - USB2 (0x1033/0x0035) 402
NOTE: This USB2 implementation supports
H3
M4
C8
D3cold. PCI_AD<0> M5
61 60 59 58 AD0
VDD_PCI
PCI_AD<1> P5
61 60 59 58 AD1
PCI_AD<2> N5
61 60 59 58 AD2
PCI_AD<3> P4
61 60 59 58 AD3
PCI_AD<4> N4
61 60 59 58 AD4
PCI_AD<5> M3 USB2_NEC
61 60 59 58 AD5
PCI_AD<6> N3 CRITICAL
61 60 59 58 AD6
M1
61 60 59 58 PCI_AD<7>
PCI_AD<8> L2
AD7
AD8
U7500
61 60 59 58
61 60 59 58 PCI_AD<9> L1
AD9
NEC_uPD720101_USB2
FBGA-LF
61 60 59 58 PCI_AD<10> K2 AD10
PCI_AD<11> L3
61 60 59 58 AD11
PCI_AD<12> K1
61 60 59 58 AD12
PCI_AD<13> K3
61 60 59 58 AD13
PCI_AD<14> J2
61 60 59 58 AD14
PCI_AD<15> J1
61 60 59 58 AD15
C 61 60 59 58 PCI_AD<16>
PCI_AD<17>
F2
E3
AD16 C
61 60 59 58 11 AD17
PCI_AD<18> E1
61 60 59 58 AD18
PCI_AD<19> D3
61 60 59 58 AD19
PCI_AD<20> D1
61 60 59 58 11 AD20
61 60 59 11 PCI_AD<21> D2 AD21
PCI_AD<22> C2
61 60 59 AD22
PCI_AD<23> C1
61 60 59 AD23
PCI_AD<24> B4
61 60 59 58 AD24
PCI_AD<25> A4
61 60 59 58 AD25
PCI_AD<26> B5
61 60 59 58 AD26
PCI_AD<27> C4
61 60 59 58 AD27
PCI_AD<28> A5
61 60 59 58 AD28
PCI_AD<29> C5
61 60 59 58 AD29
PCI_AD<30> B6
61 60 59 58 AD30
PCI_AD<31> A6
61 60 59 58 AD31
PCI_CBE_L<0> M2
61 60 59 CBE0
PCI_CBE_L<1> J3
=PCI_USB2_IDSEL
61 60 59 CBE1
11
PCI_CBE_L<2> F1
61 60 59 CBE2
USB2_NEC C3
61 60 59 PCI_CBE_L<3> CBE3
R75001
22 J4
5% 61 60 59 PCI_PAR PAR
1/16W F3
MF-LF 61 60 59 6 PCI_FRAME_L FRAME
10 =PP3V3_PCI_USB2 402 2
PCI_IRDY_L F4
61 60 59 6 IRDY
PCI_TRDY_L G1
61 60 59 6 TRDY
USB2_NEC USB2_NEC
B R75011 R75021
61 60 59 6 PCI_STOP_L
PCI_USB2_IDSEL
G3
STOP
B3 IDSEL
B
10K 10K G2
5% 5% 61 60 59 PCI_DEVSEL_L DEVSEL
USB2_NEC 1/16W 1/16W C6
MF-LF MF-LF 11 =PCI_USB2_REQ_L REQ
RP7510 402 2 402 2
=PCI_USB2_GNT_L D6
GNT
47 11
=PCI_USB2_INT_L 3 6 NEC_PERR_L_PU H2 IPD NTEST1 M8 TP_NEC_NTEST1

11 PERR
USB2_NEC H1
5% NEC_SERR_L_PU SERR OD
1/16W
SM-LF
RP7510 NEC_INTA_L C7
INTA OD IPD SMC M7 TP_NEC_SMC
47
2 7 NEC_INTB_L B7
INTB OD
USB2_NEC A7
5% NEC_INTC_L INTC OD
RP7510 1/16W
SM-LF 62 11 =PCI_CLK33M_USB2 A8
PCLK IPD TEB N7 TP_NEC_TEB
47
1 8 IPD AMC P7 TP_NEC_AMC
5% USB2_NEC NEC_VBBRST_L B8 VBBRST (CHIP RESET)
1/16W
SM-LF
R7510 NEC_CRUN_L_PD N6
CRUN IPD TEST L8 TP_NEC_TEST
47 D9
25 22 SYS_WARM_RESET_L 1 2 NEC_PME_L PME OD
USB2_NEC 5% NEC_VCCRST_L C9
VCCRST (PCI RESET)
R7511 1/16W
MF-LF TP_NEC_SMI_L L6
SMI OD NANDTEST M10 TP_NEC_NANDTEST
47 402
M9
25 22 SYS_PME_L 1 2 SRCLK TP_NEC_SRCLK
5% USB2_NEC SRDTA N9 TP_NEC_SRDATA
1/16W
MF-LF R7512 NEC_LEGC_PD L7
LEGC IPD SRMOD P9 TP_NEC_SRMOD
402 47
11 =PCI_USB2_RESET_L 1 2
USB2_NEC USB2_NEC
5%
1/16W
MF-LF R75031 1
R7504
402 4.7K 47
RP7510 & R7510-12 required to 5% 5%
facilitate NAND-tree testing
1/16W
MF-LF
402 2
1/16W
MF-LF
2 402
NEC USB2

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 75 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL DIFFERENTIAL_PAIR UATA100 SERIES TERMINATION

UATA_DD UATA UATA UATA_DD_R<15..8> 6 63
UATA_DD7 UATA UATA UATA_DD_R<7> 6 63

PLACE CLOSE TO I2
UATA_DD UATA UATA UATA_DD_R<6..0> 6 63
UATA_HOST UATA UATA UATA_DA_R<2..0> 6 63 RP8150

33
UATA_CS0_L_R =RP8150P1 1 8 =RP8150P8
UATA_HOST UATA UATA 6 63 6 BI 6
UATA_HOST UATA UATA UATA_CS1_L_R 63 RP8150 5%

1/16W
UATA_HSTROBE UATA UATA UATA_HSTROBE_R 63 33 SM-LF
6 =RP8150P2 2 7 =RP8150P7 BI 6
UATA_HOST UATA UATA UATA_STOP_R 63
UATA_HOST_R UATA UATA UATA_DMACK_L_R 63

5%
1/16W
RP8150
D UATA_HOST_R UATA UATA UATA_RESET_L_R 63 6 =RP8150P3 SM-LF 3
33
6 =RP8150P6 BI 6 D
UATA_DSTROBE UATA UATA UATA_DSTROBE_R 63 RP8150 5%
1/16W
UATA_DEV_R UATA UATA UATA_DMARQ_R 63
33 SM-LF
6 =RP8150P4 4 5 =RP8150P5 BI 6
UATA_DEV_R UATA UATA UATA_INTRQ_R 63
5%
1/16W
RP8151
UATA UATA UATA_DD<15..0> 6 7 64 SM-LF
33
6 =RP8151P1 1 8 =RP8151P8 BI 6
UATA UATA UATA_DA<2..0> 6 7 64
RP8151 5%
1/16W
UATA UATA UATA_CS0_L 6 7 64
33 SM-LF
=RP8151P2 2 7 =RP8151P7
6 BI 6
UATA UATA UATA_CS1_L 7 63 64
UATA UATA UATA_HSTROBE 7 63 64

5%
1/16W
RP8151
SM-LF
33
UATA UATA UATA_STOP 7 63 64 6 =RP8151P3 3 6 =RP8151P6 BI 6
UATA UATA UATA_DMACK_L 7 63 64 RP8151 5%

1/16W
UATA UATA UATA_RESET_L 7 63 64 33 SM-LF
=RP8151P4 4 5 =RP8151P5
6 BI 6
UATA UATA UATA_DSTROBE 7 63 64
UATA UATA UATA_DMARQ 7 63 64

5%
1/16W
RP8152
SM-LF
33
UATA UATA UATA_INTRQ 7 63 64 6 =RP8152P1 1 8 =RP8152P8 BI 6
RP8152 5%
1/16W
33 SM-LF
=RP8152P2 2 7 =RP8152P7
Page Notes One resistor for each of:
- UATA_DD<15..0>(_R)
6
5%
1/16W
RP8152
33
BI 6
SM-LF 3 6
Power aliases required by this page: OMIT - UATA_DA<2..0>(_R) 6 =RP8152P3 =RP8152P6 BI 6
(NONE)
U2100
- UATA_CS0_L(_R)
(IDE_CS1FX_L)
RP8152 5%
1/16W
33 SM-LF
Signal aliases required by this page: I2 6 =RP8152P4 4 5 =RP8152P5 BI 6
(NONE) BGA 5%
1/16W
RP8153
UATA INTERFACE SM-LF
33
=RP8153P1 1 8 =RP8153P8
BOM options provided by this page: 6 BI 6
(11 of 14)
C (NONE)
ATA_D_00_H
ATA_D_01_H
AB6
AB5
0
1
UATA_DD_R<15..0> 6 63
6 =RP8153P2
RP8153
2
33
7
5%
1/16W
SM-LF
=RP8153P7 6
C
BI
AD6
ATA_D_02_H 2 5%
1/16W
RP8153
ATA_D_03_H AD5 3 SM-LF
33
AD7 6 =RP8153P3 3 6 =RP8153P6 BI 6
ATA_D_04_H 4
ATA_D_05_H AE7 5
RP8153 5%
1/16W
33 SM-LF
AE8 =RP8153P4 4 5 =RP8153P5
ATA_D_06_H 6 6 BI 6
AD8
ATA_D_07_H 7 7 5%
1/16W
RP8154
ATA_D_08_H AB4 8 SM-LF
33
AE1 6 =RP8154P1 1 8 =RP8154P8 OUT 6
1
ATA_D_09_H 9
R8151
ATA_D_10_H AD2
10 10K RP8154 5%
1/16W
5% 33 SM-LF
AE2 =RP8154P2 2 7 =RP8154P7
ATA_D_11_H 11 1/16W 6 OUT 6
AD4 MF-LF
ATA_D_12_H 12
2 402
5%
1/16W
RP8154
I2_UATA_VREF AA9
ATA_VREF_H ATA_D_13_H AA6 13 SM-LF
33
AD1 6 =RP8154P3 3 6 =RP8154P6 OUT 6
ATA_D_14_H 14
1
ATA_D_15_H AB7 RP8154 5%
R8100 15
33 1/16W
SM-LF
1K 6 =RP8154P4 4 5 =RP8154P5 OUT 6
1% AC1
UATA_DA_R<2..0> 6 63
1/16W ATA_A_0_H 0 5%
MF-LF
402 ATA_A_1_H AB3
1
1/16W
SM-LF
R8160 (IDE_CS3FX_L)
2 33
AB2 UATA_CS1_L_R 2 1 UATA_CS1_L
ATA_A_2_H 2 63 OUT 7 63 64
5%
1/16W
ATA_RST_L AE6 UATA_RESET_L_R 63
R8161 MF-LF
AB8 33 402
ATA_WR_L UATA_STOP_R 63 63 UATA_RESET_L_R 1 2 UATA_RESET_L OUT 7 63 64
AA8 UATA_HSTROBE_R
ATA_RD_L 63 5%
1/16W
63 UATA_DSTROBE_R AA5
ATA_CHRDY_H MF-LF R8162
AE3
402 22
ATA_CS0_L UATA_CS0_L_R 6 63 63 UATA_DMACK_L_R 1 2 UATA_DMACK_L OUT 7 63 64
B 63
63
UATA_INTRQ_R
UATA_DMARQ_R
AB1
Y9
ATA_INTRQ_H
ATA_DMARQ_H
ATA_CS1_L
ATA_DMACK_L
AA4
AA7
UATA_CS1_L_R
UATA_DMACK_L_R
63
63
R8163
5%
1/16W
MF-LF (IDE_DIOR_L)
B
22 402
63 UATA_HSTROBE_R 1 2 UATA_HSTROBE OUT 7 63 64
5%
1/16W
MF-LF R8164 (IDE_DIOW_L)
402 22
63 UATA_STOP_R 1 2 UATA_STOP OUT 7 63 64
5%
1/16W
R8165 MF-LF
82 402
63 UATA_DMARQ_R 1 2 UATA_DMARQ IN 7 63 64
5%
1/16W
MF-LF R8166 (IDE_IORDY)
402 82
63 UATA_DSTROBE_R 1 2 UATA_DSTROBE IN 7 63 64
5%
1/16W
1 C8166 MF-LF
402
10pF
5%
50V
2 CERM
402
R8167
82
63 UATA_INTRQ_R 1 2 UATA_INTRQ IN 7 63 64
5%
1/16W
MF-LF
402
I2 UATA Interface

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 81 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
HDD CONNECTOR ODD CONNECTOR
64 10 =PP3V3_RUN_HDD
10 7 =PP5V_RUN_ODD
NO STUFF NO STUFF
1 1 1
R8210 R8211 R8212 1
R8255
10K 10K 4.7K
5% 5% 5% 0
1/16W 1/16W 1/16W 5%
MF-LF MF-LF MF-LF 1/8W
402 2 2 402 CRITICAL 2 402 MF-LF
J8200 2 805
M-ST-SM1-LF
1 50
PP5V_RUN_ODD
64 63 7 UATA_RESET_L VOLTAGE=5V
2 49 MIN_LINE_WIDTH=0.5 mm
64 63 7 6 UATA_DD<7> 3 48 UATA_DD<8> 6 7 63 64
4 47
C 64 63 7 6 UATA_DD<6>
5 46
UATA_DD<9> 6 7 63 64 CRITICAL
J8250 C
64 63 7 6 UATA_DD<5> 6 45 UATA_DD<10> 6 7 63 64
M-ST-SM1-LF
64 63 7 6 UATA_DD<4> 7 44 UATA_DD<11> 6 7 63 64 NC 1 50 UATA_RESET_L 7 63 64
8 43 2 49
64 63 7 6 UATA_DD<3> 9 42 UATA_DD<12> 6 7 63 64 64 63 7 6 UATA_DD<8> 3 48 UATA_DD<7> 6 7 63 64

11 40 64 63 7 6 UATA_DD<10> 5 46 UATA_DD<5> 6 7 63 64
64 63 7 6 UATA_DD<0> 13 38 UATA_DD<15> 6 7 63 64
7 44
14 37 64 63 7 6 UATA_DD<12> 8 43 UATA_DD<3> 6 7 63 64
64 63 7 UATA_DMARQ 15 36 UATA_STOP 7 63 64 64 63 7 6 UATA_DD<13> 9 42 UATA_DD<2> 6 7 63 64
64 63 7 UATA_HSTROBE 16 35 UATA_DSTROBE 7 63 64 64 63 7 6 UATA_DD<14> 10 41 UATA_DD<1> 6 7 63 64

17 34 64 63 7 6 UATA_DD<15> 11 40 UATA_DD<0> 6 7 63 64
64 63 7 UATA_DMACK_L 18 33 UATA_INTRQ 7 63 64
12 39
64 63 7 6 UATA_DA<1> 19 32 UATA_DA<2> 6 7 63 64 64 63 7 UATA_DMARQ 13 38 UATA_STOP 7 63 64
64 UATA_PDIAG 20 31 UATA_DASP_L 64 64 63 7 UATA_HSTROBE 14 37 UATA_DSTROBE 7 63 64
64 63 7 6 UATA_DA<0> 21 30 UATA_CS1_L 7 63 64 64 63 7 UATA_DMACK_L 15 36 UATA_INTRQ 7 63 64
64 63 7 6 UATA_CS0_L 22 29 =PP5V_RUN_HDD 7 10 64
16 35 UATA_DA<1> 6 7 63 64
5V_HD_LOGIC 23 28 17 34
64 63 7 6 UATA_DA<2> UATA_DA<0> 6 7 63 64
R8203 24 27 64 63 7 UATA_CS1_L 18 33 UATA_CS0_L 6 7 63 64
0 25 26 19 32
64 10 7 =PP5V_RUN_HDD 1 2 7 PP3V3R5V_RUN_HDD_LOGIC
VOLTAGE=5V 20 31
5% MIN_LINE_WIDTH=0.25 mm
MF-LF 21 30
402
R82001 1
R8201 64 UATA_PDIAG 22 29 UATA_DASP_L 64
3V_HD_LOGIC 20K 10K 23 28
5% 5%
R8202 1/16W
MF-LF
1/16W
MF-LF 24 27
B 64 10 =PP3V3_RUN_HDD 1
0 2
402 2 2 402 25 26 B
5%
1/16W
MF-LF
402
ATA Connectors
Q16C/516S0357/M-ST-SM2-LF
Q41C/516S0335/M-ST-SM1-LF
HDD/ODD Connectors
A SYNC_MASTER=MARIAS-PDIFF

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 82 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
ENET_RX_CLK25M CLOCK CLOCK ENET_CLK25M_TX 11 65
ENET_RX_CLK125M CLOCK CLOCK ENET_CLK125M_RX 11 65
ENET_GBE_REF CLOCK CLOCK ENET_CLK125M_GBE_REF 11 65
ENET_TX_CLK CLOCK CLOCK ENET_CLK125M_GTX_R 65 66
ENET_RXD3_0 ENET ENET ENET_RXD<3..0> 9 11 65
ENET_RXD7_4 ENET ENET ENET_RXD<7..4> 9 11 65
ENET_RX_DV ENET ENET ENET_RX_DV 9 11 65
ENET_RX_CTL ENET ENET ENET_RX_ER 9 11 65
D ENET_TXD3_0
ENET_TXD7_4
ENET
ENET
ENET
ENET
ENET_TXD_R<3..0>
ENET_TXD_R<7..4>
11 65
11 65
D
ENET_TX_EN ENET ENET ENET_TX_EN_R 11 65
ENET_TX_ER ENET ENET ENET_TX_ER_R 11 65
ENET_COL ENET ENET ENET_COL 9 11 65
ENET_RX_CTL ENET ENET ENET_CRS 9 11 65
ENET_MDC ENET ENET ENET_MDC 9 11 65
ENET_MDIO ENET ENET ENET_MDIO 9 11 65
ENET ENET I2_ENET_MDIO 65
Page Notes
- =PP2V5R3V3_PWRON_I2_ENET

(NONE)

(NONE)
NOTE: This page does not provide any 65 10 =PP2V5R3V3_PWRON_I2_ENET

OMIT
series termination. Any
termination, including clock U2100
signals, should be provided by C8459 1 1
C8450 1
C8451 1
C8452 1
C8453 I2
the PHY page or a non-shared 10uF 1uF 1uF 1uF 1uF BGA
20% 10% 10% 10% 10%
schematic page. 6.3V
X5R 2 2
6.3V
CERM 2
6.3V
CERM 2
6.3V
CERM 2
6.3V
CERM ETHERNET INTERFACE
603 402 402 402 402
(12 of 14)
C NOTE: All I2 GPIOs should have a
pull-up or pull-down resistor.
U3
U6
VDD25_0
VDD25_1
C
This page does not provide a U9
VDD25_2
resistor for GPIO 16. It must be 1
C8454 1
C8455 1
C8456 V13
=PP2V5R3V3_PWRON_I2_ENET 10 65 67 66 18 10 =PP3V3_VESTA
1uF 1uF 1uF VDD25_3
provided by the PHY page or a 10% 10% 10% W14
6.3V 6.3V 6.3V VDD25_4 1 1
non-shared schematic page. 2 CERM 2 CERM 2 CERM Y3 R8405 R8420
402 402 402 VDD25_5
Y6
1.5K 10K
NOTE: ENET_RX_DV has a hold spec VDD25_6 5% 5%
1/16W 1/16W
violation on I2. May want to MF-LF 2 MF-LF
lengthen net by ~250ps. Net has a 2

402 Q8420 2
402
2N7002DW-X-F G
ENET_CLK25M_TX W7 W4 ENET_MDC SOT-363
unique ECSet name to allow this. 65 11 ETH_TXCLK_H ETH_MDC_H 9 11 65
ENET_CLK125M_RX W8 W6 I2_ENET_MDIO 6 D S 1 ENET_MDIO

65 11 ETH_RXCLK_H ETH_MDIO_H 65 9 11 65
ENET_RXD<0> W2 V8 ENET_TXD_R<0>
65 11 9 ETH_RXD_0_H ETH_TXD_0_H 11 65
W3 V4 NO STUFF
65 11 9 ENET_RXD<1> ETH_RXD_1_H ETH_TXD_1_H ENET_TXD_R<1> 11 65
65 11 9 ENET_RXD<2> V2
ETH_RXD_2_H ETH_TXD_2_H V7 ENET_TXD_R<2> 11 65
R8421
U1 V6
0
65 11 9 ENET_RXD<3> ETH_RXD_3_H ETH_TXD_3_H ENET_TXD_R<3> 11 65 1 2
5%
1/16W
ENET_RXD<4> V3 V5 ENET_TXD_R<4> MF-LF
65 11 9 ETH_RXD_4_H ETH_TXD_4_H 11 65
V1 T4
402
65 11 9 ENET_RXD<5> ETH_RXD_5_H ETH_TXD_5_H ENET_TXD_R<5> 11 65
ENET_RXD<6> T1 T5 ENET_TXD_R<6>
65 11 9 ETH_RXD_6_H ETH_TXD_6_H 11 65
ENET_RXD<7> T3 T6 ENET_TXD_R<7>
65 11 9 ETH_RXD_7_H ETH_TXD_7_H 11 65
ENET_RX_DV W9 T7 ENET_TX_EN_R
65 11 9 ETH_RXDV_H ETH_TXEN_H 11 65
ENET_RX_ER W1 T8 ENET_TX_ER_R
65 11 9 ETH_RXER_H ETH_TXER_H 11 65
65 10 =PP2V5R3V3_PWRON_I2_ENET
ENET_COL AA3
65 11 9 ETH_COL_H
B R8410 1
10K
65 11 9 ENET_CRS W5
ETH_CRS_H
B
5% AA2 V9
1/16W 65 11 ENET_CLK125M_GBE_REF ETH_GREFCLK_H ETH_GTXCLK_H ENET_CLK125M_GTX_R 65 66
MF-LF
402
2
Signal Pin Y1 AA1 Pin Signal
ENET_ENERGYDET EXT_05_H GPIO_16_H ENET_RESET_L 11
I2_ENET_PVT U10
ETH_PVT_H
1
R8400 These GPIOs are referenced
1K
1%
1/16W to the Ethernet I/O rail
MF-LF
402
2
I2 Ethernet Interface

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 84 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
(PROVIDED BY LINK PAGE) CLOCK CLOCK ENET_CLK125M_GBE_REF_R 66 L8520

ENET_CLK125M_RX_R FERR-EMI-600-OHM =PP2V5_ENETFW
(PROVIDED BY LINK PAGE) CLOCK CLOCK 66 10 69
ENET_CLK25M_TX_R PP2V5_VESTA_XTALVDD1 1 2
(PROVIDED BY LINK PAGE) CLOCK CLOCK 66
VOLTAGE=2.5V
MIN_LINE_WIDTH=0.5 mm SM
ENETCONN ENETCONN ENETCONN ENETCONN_0 ENETCONN_0_P 66 67 MIN_NECK_WIDTH=0.25 mm
ENETCONN ENETCONN ENETCONN ENETCONN_0 ENETCONN_0_N 66 67

1
C8520 1
C8521
ENETCONN ENETCONN ENETCONN ENETCONN_1 ENETCONN_1_P 66 67
0.001uF 10UF
20% 20%
ENETCONN_1_N 50V 6.3V
ENETCONN ENETCONN ENETCONN ENETCONN_1 66 67 2 CERM 2 X5R
ENETCONN_2_P 402 603
ENETCONN ENETCONN ENETCONN ENETCONN_2 66 67
ENETCONN ENETCONN ENETCONN ENETCONN_2 ENETCONN_2_N 66 67
D ENETCONN
ENETCONN
ENETCONN
ENETCONN
ENETCONN
ENETCONN
ENETCONN_3
ENETCONN_3
ENETCONN_3_P
ENETCONN_3_N
66 67
66 67
L8510
FERR-EMI-600-OHM D
PP2V5_VESTA_BIASVDD1 1 2
VESTA_CLK25M_XTAL XTAL XTAL VESTA_CLK25M_XTALI 66 VOLTAGE=2.5V
MIN_LINE_WIDTH=0.5 mm SM
XTAL XTAL VESTA_CLK25M_XTALO 66 MIN_NECK_WIDTH=0.25 mm
XTAL XTAL VESTA_CLK25M_XTALO_R 66

1 C8510
0.1uF
20%
10V
2 CERM
Page Notes 402
L8530
Power aliases required by this page: FERR-EMI-600-OHM =PP1V2_ENETFW 10 69
- =PP2V5_ENETFW PP1V2_VESTA_PLLVDD1 1 2
VOLTAGE=1.2V
- =PP1V2_ENETFW MIN_LINE_WIDTH=0.5 mm SM
1 1
Signal aliases required by this page: C8530 C8531
(NONE) 0.001uF 10uF
20% 20%
50V 6.3V
2 CERM 2 CERM
BOM options provided by this page: 402 1206-1
(NONE) ESR < 0.5 ohms
Place close to PHY
N1
P1
M1
Net Spacing Type: ENET_MDI R8560
Place close to link XTALVDD1 BIASVDD1 PLLVDD1 0
Line To Line: 0.38 mms 1 2 =VESTA_CLK125M_GBE_REF OUT 11
Length Tolerance: 50 mils R8569 5%

0 1/16W
R8561
Primary Max Sep: 5 mils 65 IN ENET_CLK125M_GTX_R 1 2 ENET_CLK125M_GTX A4 GTXCLK CLK125 D1 66 ENET_CLK125M_GBE_REF_R MF-LF
OMIT 402 0
Secondary Max Sep: 100 mils 5% 1 2 =VESTA_CLK25M_TX OUT 11
1/16W
Secondary Length: 500 mils MF-LF
402
VESTA ENET TXC A6 66 ENET_CLK25M_TX_R 5%
1/16W
U8500 R8562 MF-LF
NOTE: Target differential impedance for 0 402
BCM5462 RXC C1 66 ENET_CLK125M_RX_R 1 2 =VESTA_CLK125M_RX OUT 11
C ENET data pairs is 100 ohms.
=ENET_TXD<0> B6 TXD[0]
FBGA-200
2 OF 3
RXD[0] F4 =ENET_RXD_R<0>
5%
1/16W
C
11
11
IN
IN =ENET_TXD<1> C6 TXD[1] RXD[1] F5 =ENET_RXD_R<1>
OUT
OUT
11
11
MF-LF
402 I2BORG SPECIFIC
Not convention-compliant,
Vesta Ethernet LowPwr 11
IN
IN
=ENET_TXD<2>
=ENET_TXD<3>
C7
D6
TXD[2]
TXD[3]
RXD[2] E5
RXD[3] E4
=ENET_RXD_R<2>
=ENET_RXD_R<3>
OUT
OUT
11
11
’=VESTA_’ should be
replaced with ’ENET_’
Disables Vesta Ethernet Circuit 11 IN =ENET_TXD<4> E6 TXD[4] RXD[4] E3 =ENET_RXD_R<4> OUT 11
(6 nets)
11 IN =ENET_TXD<5> C5 TXD[5] RXD[5] D5 =ENET_RXD_R<5> OUT 11
11 IN =ENET_TXD<6> B5 TXD[6] RXD[6] D4 =ENET_RXD_R<6> OUT 11
11 IN =ENET_TXD<7> A5 TXD[7] RXD[7] D3 =ENET_RXD_R<7> OUT 11
67 65 18 10 =PP3V3_VESTA
11 IN =ENET_TX_EN B4 TX_EN RX_DV D2 =ENET_RX_DV_R OUT 11
11 IN =ENET_TX_ER C4 TX_ER RX_ER C2 =ENET_RX_ER_R OUT 11

R8580 1 RC time constant not
=PP3V3_ENET
1K critical. R < 3.9K =VESTA_MDC =ENET_COL_R
10 5% 11 IN
G1 MDC COL F3 OUT 11
1/16W to counter internal
MF-LF 11 BI =VESTA_MDIO G2 MDIO CRS G3 =ENET_CRS_R OUT 11
402
2
pulldown.
VESTA_ENET_LOWPWR H5 LOWPWR RBC0 A3 NC? TP_VESTA_RBC0
RBC1 B3 NC? TP_VESTA_RBC1
6 3 1
C8580
D D 0.1uF TP_VESTA_PHYA<0> L5 PHYA[0] TRD+[0] R4 ENETCONN_0_P
Q8580 Q8580 20% BI 66 67
10V TP_VESTA_PHYA<1> ENETCONN_0_N
2N7002DW-X-F 2N7002DW-X-F 2 CERM
L4 PHYA[1] TRD-[0] R5 BI 66 67
SOT-363 SOT-363
VESTA_RESET 2 5 402 TP_VESTA_PHYA<2>
18 IN G S G S L3 PHYA[2] ENETCONN_1_P
TP_VESTA_PHYA<3>
TRD+[1] R7 BI 66 67
L2 PHYA[3] ENETCONN_1_N
1 4
TP_VESTA_PHYA<4>
TRD-[1] R6 BI 66 67
L1 PHYA[4]
TRD+[2] R8 ENETCONN_2_P BI 66 67
TRD-[2] R9 ENETCONN_2_N BI 66 67
Circuit ensures Vesta LOWPWR signal is low when TP_VESTA_EN_10B K3 EN_10B
B Vesta RESET* is asserted, and allows LOWPWR to
TP_VESTA_RGMIIEN B8 RGMIIEN TRD+[3] R11 ENETCONN_3_P BI 66 67 B
TP_VESTA_FDX C8 FDX TRD-[3] R10 ENETCONN_3_N BI 66 67
assert when ethernet link is unpowered. TP_VESTA_F1000 K4 F1000

TP_VESTA_SPD0 SPD0 =VESTA_ENERGYDET 1 1 1 1
K5 INTR*/ENERGYDET D10 OUT 11
R8590 R8592 R8594 R8596
TP_VESTA_MANMS D9 MANMS 49.9 49.9 49.9 49.9
1% 1% 1% 1%
TP_VESTA_HUB A9 HUB SLAVE*/AN_EN C10 TP_VESTA_AN_EN 1/16W 1/16W 1/16W 1/16W
TP_VESTA_ER H3 ER QUALITY*/TXC_RXC_DELAY A8 TP_VESTA_TXC_RXC_DELAY 402 402 402 402
2 2 2 2
Vesta Config Straps: TP_VESTA_LINKSPD1_L
LINK1* A10
PHYA<4..0> - PHY Address Select MANMS - Manual Master/Slave Configuration Select TP_VESTA_TEST<0> M4 TEST[0] LINK2* B11 TP_VESTA_LINKSPD2_L R8591 1 R8593 1 R8595 1 R8597 1
49.9 49.9 49.9 49.9
(Internal Pull-downs) Sets manual master/slave configuration enable bit TP_VESTA_TEST<1> M5 TEST[1] FDXLED* B10 TP_VESTA_FDXLED_L 1% 1% 1% 1%
1/16W 1/16W 1/16W 1/16W
(Internal Pull-down) TP_VESTA_TVCO N3 TVCO XMTLED* B12 TP_VESTA_XMTLED_L MF-LF MF-LF MF-LF MF-LF
EN_10B - TBI Interface Select 402 2 402 2 402 2 402 2
Put crystal circuit close to PHY ACTLED* A11 TP_VESTA_ACTLED_L
1 - TBI/RTBI Mode HUB - Repeater Select
66 VESTA_CLK25M_XTALI N2 XTALI ENET_MDI0 ENET_MDI1 ENET_MDI2 ENET_MDI3
0 - GMII/RGMII Mode Sets Hub/DTE bit and master/slave configuration value bit
66 VESTA_CLK25M_XTALO_R P2 XTALO RDAC1 R1 VESTA_RDAC1_PD
(Internal Pull-down) (Internal Pull-down) 1
C8590 1
C8592 1
C8594 1
C8596
1
XTALGND BIASGND PLLGND1 0.01UF 0.01UF 0.01UF 0.01UF
RGMIIEN - RGMII Enable ER - Edge Rate Select R8501 R8509 1 20% 20% 20% 20%
P3
R2
M2
0 1.24K 16V 16V 16V 16V
1 - RGMII/RTBI Mode 1 - Rise time approx. 5 ns 2 CERM 2 CERM 2 CERM 2 CERM
5% 1% 402 402 402 402
0 - GMII/TBI Mode 0 - Rise time approx. 4 ns CRITICAL 1/16W 1/16W
MF-LF MF-LF
(Internal Pull-down) (Internal Pull-down) Y8500 2
402 402
2
25.0000M PLACE RESISTORS CLOSE TO PHY
FDX - Full-Duplex Select AN_EN - Auto-Negotiation Select 1 2
Sets manual duplex mode bit 1 - Auto-negotiation enabled

8X4.5MM-SM2
VESTA_CLK25M_XTALO 66
(Internal Pull-up) 0 - Auto-negotiation disabled
(Internal Pull-up) C8500 1 1 C8501

F1000 - Speed Select
See table below TXC_RXC_DELAY

33pF
5%
33pF
5%
Vesta Ethernet PHY
50V 50V
CERM 2 2 CERM
A (Internal Pull-up)
SPD0 - Speed Select

1 - If RGMII Mode enabled, RXC clock and
GTXCLK are delayed by 1.9 ns

402 402 SYNC_MASTER=MARIAS

A
0 - No clock delay
See table below
(Internal Pull-down) THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
(Internal Pull-down) CRYSTAL LOAD CAPACITANCE IS 20PF PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AN_EN F1000 SPD0 Description I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
0 0 0 Force 10BASE-T II NOT TO REPRODUCE OR COPY IT
0 0 1 Force 100BASE-TX III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
0 1 X Force 1000BASE-T (test use only)
1 0 0 Auto-negotiate advertise 10BASE-T
1
1
0
1
1
0
Auto-negotiate advertise 10/100BASE-TX
Auto-negotiate advertise 10/100/1000BASE-T APPLE COMPUTER INC.
D 051-6839 F
SCALE SHT OF
1 1 1 Auto-negotiate advertise 1000BASE-T
NONE 85 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE Ethernet routing priority:
ELECTRICAL_CONSTRAINT_SET SPACING PHYSICAL DIFFERENTIAL_PAIR 1. Decoupling caps
ENETRJ45_0_P
2. TX SERIES TERMINATION - LOCATE NEAR LINK
I743 ENETCONN ENETCONN ENET_RJ45_0 67
3. RX SERIES TERMINATION - LOCATE NEAR PHY
I744 PROVIDED ENETCONN ENETCONN ENET_RJ45_0 ENETRJ45_0_N 67
I745 ENETCONN ENETCONN ENET_RJ45_1 ENETRJ45_1_P 67

All differential signals should be close,
I746 BY ENETCONN ENETCONN ENET_RJ45_1 ENETRJ45_1_N 67
parallel, matched lengths, with minimum
I747 ENETCONN ENETCONN ENET_RJ45_2 ENETRJ45_2_P 67
via count, and short if possible
I748 ETHERNET ENETCONN ENETCONN ENET_RJ45_2 ENETRJ45_2_N 67
I749 ENETCONN ENETCONN ENET_RJ45_3 ENETRJ45_3_P 67 Must maintain 50-ohms trace impedance on all
I750 PHY ENETCONN ENETCONN ENET_RJ45_3 ENETRJ45_3_N 67 MDI pairs and all RJ45 pairs
D Sandwich each RJ54 pair between chassis grounds D

Page Notes
- _PP2V5_ENET
- _GND_CHASSIS_ENET
NO STUFF
Signal aliases required by this page: R8620
(NONE) 1
0 2
BOM options provided by this page: 5%
1/10W
(NONE) MF-LF
603
Q8620
TSSOP
SI6467BDQ-E3
6 7
8
10 =PP2V5_ENET PP2V5_ENET_CTAP
VOLTAGE=2.5V
1 5
3
R8621 1 1 C8600 1 C8601 1 C8602 1 C8603
2
100K 1uF 1uF 1uF 1uF
5% 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V
1/16W C8620 2 CERM 2 CERM 2 CERM 2 CERM
4
MF-LF 402 402 402 402
402 2 1000pF
ENET_CTAP_EN_L 1 2
Place one cap at each pin of transformer
10%
25V
X7R
3 402 1000BT-824-00275
CRITICAL
D Q8420 T8600
XFR-SM
2N7002DW-X-F 1 16
C 66 65 18 10 =PP3V3_VESTA 5 G S
SOT-363
66 ENETCONN_0_P 67 ENETRJ45_0_P
C
3 14 ENET_CTAP0
4
CRITICAL
66 ENETCONN_0_N 2 15 67 ENETRJ45_0_N J8600
RJ45
CHIP
SIDE
SIDE
LINE
4 NC1 13
NC4 11 RT-TH-LF
5 NC2 12
NC3 9
66 ENETCONN_1_P 7 10 67 ENETRJ45_1_P
6 11 ENET_CTAP1 1
2
66 ENETCONN_1_N 8 9 67 ENETRJ45_1_N 3
Transformers should be 4
mirrored on opposite SYM_VER2 5
sides of the board 1000BT-824-00275

CRITICAL
6
T8601
XFR-SM
7
66 ENETCONN_2_P 1 16 67 ENETRJ45_2_P 8
3 14 ENET_CTAP2
10
12
66 ENETCONN_2_N 2 15 67 ENETRJ45_2_N
CHIP
SIDE
SIDE
LINE
4 NC1 13 Short shielded RJ-45
NC4
5 NC2 12
NC3
66 ENETCONN_3_P 7 10 67 ENETRJ45_3_P
514-0059
6 11 NO STUFF
ENET_CTAP3
R8610
B 66 ENETCONN_3_N 8 9 67 ENETRJ45_3_N 1
0 2 B
5%
1/8W
SYM_VER2 MF-LF
805
Place close to connector
R86001 R86011 1
R8602 1
R8603
75 75 75 75
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
402 2 402 2 2 402 2 402
C8604
100pF
ENET_CTAP_COMMON 1 2 =GND_CHASSIS_ENET 2
MIN_NECK_WIDTH=0.25 mm 10%
3KV
CERM
1808
Ethernet Connector
A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 86 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
FW_D FW FW FW_D_R<7..0> 6 9 68
FW_CTL FW FW FW_CTL_R<1..0> 9 68 71
FW_LREQ FW FW FW_LREQ_R 9 68 71
FW FW FW_LPS_R 9 68 71
FW FW FW_LINKON 68 69
FW_PCLK CLOCK CLOCK FW_CLK98M_PCLK 68 69
FW_LCLK CLOCK CLOCK FW_CLK98M_LCLK_R 68 69
D FW_PINT FW FW FW_PINT 68 69 D
Page Notes
(NONE)

(NONE)

(NONE)
OMIT
C U2100 C
I2
BGA
FIREWIRE INTERFACE
(13 of 14)
FW_CLK98M_PCLK K7
69 68 FWR_PCLK_H 49MHz
SYSCLK (Legacy)
FW_LINKON M4 M3 FW_D_R<0>
69 68 FWR_LINKON_H FWR_D_0_H 6 9 68
M2 FW_D_R<1>
FWR_D_1_H 6 9 68
I2_FW_PVT M9 L1 FW_D_R<2>
FWR_PVT FWR_D_2_H 6 9 68
K4 FW_D_R<3>
FWR_D_3_H 6 9 68
1 K3 FW_D_R<4>
R8800 FWR_D_4_H 6 9 68
N9 FW_D_R<5>
1K FWR_D_5_H 6 9 68
1% K2
1/16W FWR_D_6_H FW_D_R<6> 6 9 68
MF-LF J4
402 FWR_D_7_H FW_D_R<7> 6 9 68
2
M8 FW_CTL_R<0>
FWR_CNTL_0_H 9 68 71
M7 FW_CTL_R<1>
FWR_CNTL_1_H 9 68 71
K6 FW_LREQ_R
FWR_LREQ_H 9 68 71
K5 FW_LPS_R
FWR_LPS_H 9 68 71
FW 800 SIGNALS
FW_PINT K8 M5 FW_CLK98M_LCLK_R
69 68 FWR_PINT_L FWR_LCLK_H 68 69
B B
I2 FireWire Interface

A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 88 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
(PROVIDED BY LINK PAGE) CLOCK CLOCK FW_CLK98M_PCLK_R 69
CLOCK CLOCK FW_CLK98M_LCLK 69

L8900
FERR-EMI-600-OHM L8906
FW_TPA0 FW_TP FW_TP FW_TPA0 FW_TPA0_P 69 70 69 66 10 =PP1V2_ENETFW FERR-EMI-600-OHM
1 2
=PP3V3_ENETFW 10
FW_TPA0 FW_TP FW_TP FW_TPA0 FW_TPA0_N 69 70 PP1V2_VESTA_PLLVDD2 1 2
VOLTAGE=1.2V PP3V3_VESTA_FAVDDH
FW_TPB0 FW_TP FW_TP FW_TPB0 FW_TPB0_P 69 70
SM MIN_LINE_WIDTH=0.5 mm VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm SM
FW_TPB0 FW_TP FW_TP FW_TPB0 FW_TPB0_N 69 70 MIN_NECK_WIDTH=0.25 mm
1 C8900 C8901 1
FW_TPA1_P 10uF 0.001uF

1 C8906 1 C8907 1 C8908 C8917 1
FW_TPA1 FW_TP FW_TP FW_TPA1 69 70
20% 20% 0.1uF 0.1uF 0.1uF 10UF
FW_TPA1_N 6.3V 50V 20% 20% 20% 20%
FW_TPA1 FW_TP FW_TP FW_TPA1 69 70 ESR < 0.5 ohms 2 CERM CERM 2 10V 10V 10V 6.3V
2 2 2 2
D FW_TPB1
FW_TPB1
FW_TP
FW_TP
FW_TP
FW_TP
FW_TPB1
FW_TPB1
FW_TPB1_P
FW_TPB1_N
69 70
69 70
1206-1 402 CERM
402
CERM
402
CERM
402
X5R
603 D
FW_TPA2 FW_TP FW_TP FW_TPA2 FW_TPA2_P 69 70
FW_TPA2 FW_TP FW_TP FW_TPA2 FW_TPA2_N 69 70 L8901 L8909

FW_TPB2 FW_TP FW_TP FW_TPB2 FW_TPB2_P =PP2V5_ENETFW FERR-EMI-600-OHM FERR-EMI-600-OHM =PP2V5_ENETFW
69 70 69 66 10 10 66 69
FW_TPB2_N 1 2 PP2V5_VESTA_BIASVDD2 PP2V5_VESTA_FAVDDM 1 2

FW_TPB2 FW_TP FW_TP FW_TPB2 69 70
VOLTAGE=2.5V VOLTAGE=2.5V
SM MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm SM
VESTA_CLK24M_XTAL XTAL XTAL VESTA_CLK24M_XTALI 69 MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm
XTAL XTAL VESTA_CLK24M_XTALO 69 C8903 1 1 C8909 1 C8911 C8918 1
XTAL XTAL VESTA_CLK24M_XTALO_R 69

0.1uF 0.1uF 0.1uF 10UF
20% 20% 20% 20%
10V 10V 10V 6.3V
CERM 2 2 CERM 2 CERM X5R 2
402 402 402 603
Page Notes
L8902 L8913
- =PPFW_PHY_CPS FERR-EMI-600-OHM FERR-EMI-600-OHM =PP1V2_ENETFW 10 66 69
- =PP3V3_FW 1 2 1 2
PP2V5_VESTA_XTALVDD2 PP1V2_VESTA_FAVDDL
- =PP3V3_ENETFW SM
VOLTAGE=2.5V VOLTAGE=1.2V
SM
- =PP2V5_ENETFW MIN_NECK_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm
- =PP1V2_ENETFW 1 C8904 C8905 1 1 C8913 1 C8914 1 C8915 C8919 1
10UF 0.001uF 0.1uF 0.1uF 0.1uF 10UF

20% 20% 20% 20% 20% 20%
Signal aliases required by this page: 6.3V 50V 10V 10V 10V 6.3V
2 X5R CERM 2 2 CERM 2 CERM 2 CERM X5R 2
- NONE 603 402 402 402 402 603

=PPFW_PHY_CPS
N15
R14
P15
K11
K12
K13
L11
L12
M11
M12
L10
M10
N11
N12
10
- VESTA_BILINGUAL_EN12
XTALVDD2
BIASVDD2
PLLVDD2
If stuffed, adds external pull-down 1 FAVDDH FAVDDM FAVDDL
to counter internal pull-up in Vesta.
R8914
390K
C See straps table for more information.
- VESTA_DS_ONLY_EN0
5%
1/16W
MF-LF
C
2 402
If stuffed, adds external pull-up to
counter internal pull-down in Vesta. VESTA_CPS R13 CPS TDBL[0] A14 TP_VESTA_TDBL<0>
See straps table for more information. TDBL[1] B13 TP_VESTA_TDBL<1>
69 VESTA_BILINGUAL_EN12_L C11 ESDET0 (Int PU) Place close to PHY
- VESTA_PORT1_DISABLE VESTA FW TDBL[2] B14 TP_VESTA_TDBL<2>
69 VESTA_PORT1_DISABLE_L C12 ESDET1 (Int PU) R8902
If stuffed, adds external pull-down Place close to link
69 VESTA_PORT2_DISABLE_L C13 ESDET2 (Int PU) U8500 22
to counter internal pull-up in Vesta. R8905 BCM5462 PLI_PCLK E15 69 FW_CLK98M_PCLK_R 1 2 FW_CLK98M_PCLK OUT 68
See straps table for more information. 22 FBGA-200 5%

68 IN FW_CLK98M_LCLK_R 1 2 69 FW_CLK98M_LCLK D15 PLI_LCLK 3 OF 3 1/16W
- VESTA_PORT2_DISABLE PLI_INT D13 FW_PINT OUT 68 MF-LF
5% OMIT 402
If stuffed, adds external pull-down 1/16W PLI_LINK D14 FW_LINKON OUT 68
MF-LF 9 6 BI FW_D<0> E12 PLI_DATA[0]
to counter internal pull-up in Vesta. 402 FW_TPBIAS0 OUT 70
9 6 BI FW_D<1> E11 PLI_DATA[1] MIN_LINE_WIDTH=0.25 mm
See straps table for more information.
FW_D<2>
TPBIAS[0] L13 MIN_NECK_WIDTH=0.25 mm
9 6 BI
F11 PLI_DATA[2] FW_TPA0_P
- VESTA_PWR_CLASS_0
FW_D<3>
TPAP[0] L15 BI 69 70
9 6 BI
F12 PLI_DATA[3] FW_TPA0_N
If stuffed, adds external pull-down TPAN[0] L14 BI 69 70
9 6 BI FW_D<4> F13 PLI_DATA[4] FW_TPB0_P
to counter internal pull-up in Vesta.
FW_D<5>
TPBP[0] M15 BI 69 70
9 6 BI
G13 PLI_DATA[5]
See straps table for more information. TPBN[0] M14 FW_TPB0_N BI 69 70
9 6 BI FW_D<6> G12 PLI_DATA[6] FW_TPBIAS1 OUT 70
9 6 BI FW_D<7> G11 PLI_DATA[7] MIN_LINE_WIDTH=0.25 mm
Net Spacing Type: FW_TP TPBIAS[1] J13 MIN_NECK_WIDTH=0.25 mm
TPAP[1] J15 FW_TPA1_P BI 69 70

Line To Line: 0.38 mms 71 9 BI FW_CTL<0> E14 PLI_CTL[0]
TPAN[1] J14 FW_TPA1_N BI 69 70
Length Tolerance: 100 mils 71 9 BI FW_CTL<1> E13 PLI_CTL[1]
TPBP[1] K15 FW_TPB1_P BI 69 70
Primary Max Sep: 7.5 mils
TPBN[1] K14 FW_TPB1_N BI 69 70
Secondary Max Sep: 100 mils 1 1 71 9 IN FW_LPS D11 PLI_LPS 70 69 10 =PP3V3_FW
R8998 R8999 FW_TPBIAS2 OUT 70
Secondary Length: 500 mils 71 9 IN FW_LREQ D12 PLI_LREQ MIN_LINE_WIDTH=0.25 mm
150 150 TPBIAS[2] H13 MIN_NECK_WIDTH=0.25 mm
1% 1%
NOTE: Target differential impedance for 1/16W 1/16W TPAP[2] G15 FW_TPA2_P BI 69 70
FW data pairs is 110 ohms.

MF-LF
402 2
MF-LF VESTA_LPWR_1394 J3 LPWR_1394
TPAN[2] G14 FW_TPA2_N R8916 1 1
R8915
2 402
69 70
B R8906 1
69
69
VESTA_DS_ONLY_EN0
VESTA_PWR_CLASS_MSB
A13
A12
DS_ONLY_EN0 (Int PD)
PWR_CLASS (Int PU)
TPBP[2] H15 FW_TPB2_P
BI
BI 69 70
10K
5%
1/16W
10K
5%
1/16W
B
TPBN[2] H14 FW_TPB2_N BI 69 70 MF-LF MF-LF
1K 402
2 2
402
1%
1/16W TP_VESTA_TEST_1394<0> J5 TEST_1394[0]
MF-LF SDC H1 I2C_VESTA_SCL
402 2 TP_VESTA_TEST_1394<1> J4 TEST_1394[1]
SDA H2 I2C_VESTA_SDA
TP_VESTA_TVCO_24 N13 TVCO_24
Put crystal circuit close to PHY
RDAC2 R15 VESTA_RDAC2_PD
69 VESTA_CLK24M_XTALI P14 XTALI_24
69 VESTA_CLK24M_XTALO_R P13 XTALO_24
R8909 1
BIASGND PLLGND2 2.0K
1
P12
N14
R8921 1%
0 R8903 1 1
R8904 1/16W
MF-LF
5% 1K 10K 402
2
CRITICAL 1/16W 1% 1%
MF-LF 1/16W 1/16W
=PP3V3_FW
Y8920 2
402 MF-LF MF-LF
70 69 10 402 402
24.576M 2 2
1 2
VESTA_DS_ONLY_EN0
1 VESTA_CLK24M_XTALO
R8911 8X4.5MM-SM1 69
1K
Vesta Config Straps: 5%
1/16W C8920 1 C8921 1
MF-LF 18pF 18pF
DS_ONLY_EN12 - Port 1&2 Data/Strobe 402
2 5% 5%
50V 50V
1 - Port 1&2 Data/Strobe mode only CERM 2 CERM 2
VESTA_DS_ONLY_EN0 69 402 402
0 - Port 1&2 Bilingual mode
(Internal Pull-up)
VESTA_PWR_CLASS_MSB 69
DS_ONLY_EN0 - Port 0 Data/Strobe
VESTA_PWR_CLASS_0
1 - Port 0 Data/Strobe mode only CRYSTAL LOAD CAPACITANCE IS 12PF
0 - Port 0 Bilingual mode
1
R8912 VESTA_BILINGUAL_EN12_L 69 Vesta FireWire PHY
1K VESTA_BILINGUAL_EN12
A (Internal Pull-down)
PORT1_ENABLE - Port 1 Enable

5%
1/16W
MF-LF
402
1
R8931
1K
VESTA_PORT1_DISABLE_L
VESTA_PORT1_DISABLE
69
SYNC_MASTER=MARIAS

A
2
1 - Port 1 Enabled 5%
1 VESTA_PORT2_DISABLE_L
0 - Port 1 Disabled (saves power)
1/16W
MF-LF
R8933 69
2 402
1K VESTA_PORT2_DISABLE PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
(Internal Pull-up) 5% 1 AGREES TO THE FOLLOWING
PORT2_ENABLE - Port 2 Enable
1/16W
MF-LF
R8935 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
2
402 1K
1 - Port 2 Enabled 5% II NOT TO REPRODUCE OR COPY IT
1/16W
0 - Port 2 Disabled (saves power) MF-LF III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
(Internal Pull-up) 2 402
PWR_CLASS - FireWire Power Class
1 - Sets Power Class to 0x4

0 - Sets Power Class to 0x0 APPLE COMPUTER INC.
D 051-6839 F
SCALE SHT OF
(Internal Pull-up)
NONE 89 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
FW FW FW_PORT1_TPA_FL FW_PORT1_TPA_P_FL 70
Cable Power
PROVIDED FW FW FW_PORT1_TPA_FL FW_PORT1_TPA_N_FL 70
"Snapback" & "Late VG" Protection
FW FW FW_PORT1_TPB_FL FW_PORT1_TPB_P_FL
BY FW FW FW_PORT1_TPB_FL FW_PORT1_TPB_N_FL
70
PP3V3_FW_ESD
10 =PPFW_PORT1 L9010
70 70 FERR-250-OHM
FW FW FW_PORT2_TPA_FL FW_PORT2_TPA_P_FL 70
DP9010 1 2 PPFW_PORT1_VP PORT 1
BAV99DW-X-F VOLTAGE=33V
PHY FW FW FW_PORT2_TPA_FL FW_PORT2_TPA_N_FL 70
C9011 1
SOT-363 SM MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm BILINGUAL
FW FW FW_PORT2_TPB_FL FW_PORT2_TPB_P_FL 70
0.001uF
5 1 C9014
PAGE FW FW FW_PORT2_TPB_FL FW_PORT2_TPB_N_FL 70
20%
50V 3 20%
0.001uF Q16C/514S0106/1394B
CERM 2 50V
2 CERM Q41C/514S0105/1394B-Q41
D
402
D
Page Notes C9010 1
DP9010
BAV99DW-X-F
SOT-363
4 402
FL9010
CRITICAL
J9010
Power aliases required by this page: Termination 0.001uF
20%
2 90-OHM-300mA
2012H
1394B-Q41
F-RT-SM-LF
- _PPFW_PORT1 SYM_VER-1
- _PPFW_PORT2
Place close to FireWire PHY 50V
CERM 2
6
1 4
14
402 12
- _PPFW_PORT3 69 FW_TPBIAS1 1
10
- _PP3V3_FW 69 FW_TPBIAS0
FW_PORT1_TPB_N 2 3 FW_PORT1_TPB_N_FL 1
70 70 TPB-
- _GND_CHASSIS_FW_PORT1
- _GND_CHASSIS_FW_PORT2 1 C9050 1 C9060 (FW_PORT1_BREF) 9 TPB<R> OUTPUT
FW_PORT1_TPB_P 70FW_PORT1_TPB_P_FL 2 TPB+
- _GND_CHASSIS_FW_PORT3 1uF 1uF 70
10% 10% (PPFW_PORT1_VP) 8 VP
2 6.3V
CERM 2 6.3V
CERM
Signal aliases required by this page: 402 402 NC 7 NC
(NONE) (GND_FW_PORT1_VG) 6 VG
NOTE: This page is expected to contain the 70 FW_PORT1_TPA_N 70 FW_PORT1_TPA_N_FL 3 TPA-
necessary aliases to map the FW_PORT1_AREF 5 TPA<R> INPUT
FireWire TPA/TPB pairs to their R90501 1
R9051 R90601 1
R9061 70 FW_PORT1_TPA_P 70 FW_PORT1_TPA_P_FL 4 TPA+
56.2 56.2 56.2 56.2 11
appropriate connectors and/or to 1% 1% 1% 1%
properly terminate unused signals.
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
1/16W
MF-LF
DP9011 13
402 2 2 402 402 2 2 402
BAV99DW-X-F NO STUFF NO STUFF 15
SOT-363
BOM options provided by this page: FW_TPA0_P FW_PORT1_TPA_P 70 2 C9015 1 FL9011
90-OHM-300mA
C9017 1 C9019 1
(NONE)
69
MAKE_BASE=TRUE DP9011 0.1uF 2012H 0.01uF 0.01uF
69 FW_TPA0_N FW_PORT1_TPA_N 70 10% SYM_VER-1 20% 20%
6 BAV99DW-X-F 50V 50V 16V
MAKE_BASE=TRUE X7R 2 CERM 2 CERM 2
NOTE: FireWire TPA/TPB pairs are NOT 69 FW_TPB0_P FW_PORT1_TPB_P 70
MAKE_BASE=TRUE
C9012 1 SOT-363 603-1
1 4
603 402
constrained on this page. It is 69 FW_TPB0_N FW_PORT1_TPB_N 70 0.001uF 1 5
MAKE_BASE=TRUE 20% NO STUFF NO STUFF
50V 1
assumed that FireWire PHY page will CERM 2 3 R9011 2 3 1 C9016 1 C9018
provide the appropriate constraints 69 FW_TPA1_P FW_PORT2_TPA_P 70
MAKE_BASE=TRUE
402
C9013 1
5%
1M 0.01uF 0.01uF
to apply to entire TPA/TPB XNets. 69 FW_TPA1_N FW_PORT2_TPA_N 70 0.001uF 4 1/16W 20% 20%
20% 16V 16V
MAKE_BASE=TRUE 50V MF-LF 2 CERM 2 CERM
C 1394b implementation based on Apple

FireWire Design Guide (FWDG 0.6, 5/14/03)
69
69
FW_TPB1_P
FW_TPB1_N
FW_PORT2_TPB_P 70
MAKE_BASE=TRUE
FW_PORT2_TPB_N 70
MAKE_BASE=TRUE
CERM 2
402
2 402 402 402
C
=GND_CHASSIS_FW_PORT1 2
1 1 1 1
R9052 R9053 R9062 R9063 AREF needs to be isolated from
56.2 56.2 56.2 56.2
1%
1/16W
1%
1/16W
1%
1/16W
1%
1/16W
all local grounds per 1394b spec
402 2 2 402 402 2 2 402 When a bilingual device is
connected to a beta-only device,
FW_TPA0_C FW_TPA1_C there is no DC path between them
1
R9054 1
R9064 (to avoid ground offset issue)
C9054 1 4.99K C9064
1%
1 4.99K
1%
270pF 1/16W 270pF 1/16W BREF should be hard-connected to
5% MF-LF 5% MF-LF
25V
CERM 2 2 402
25V
CERM 2 2 402 logic ground for speed signaling
402 402
Cable Power and connection detection currents
PPFW_PORT2_VP_F
per 1394b V1.33
VOLTAGE=33V
3rd TPA/TPB pair unused F9020 L9020

FERR-250-OHM
PPFW_PORT2_VP
VOLTAGE=33V
10 =PPFW_PORT2 1.5AMP-33V MIN_LINE_WIDTH=0.5 mm
1 2 1 2 MIN_NECK_WIDTH=0.25 mm
69 FW_TPBIAS2 NC_FW_TPBIAS2
MAKE_BASE=TRUE SM
NO_TEST=YES SM-LF
FW_TPA2_P NC_FW_TPA_P2
1 C9024
69
MAKE_BASE=TRUE 0.001uF
NO_TEST=YES 20%
50V
2 CERM
69 FW_TPA2_N NC_FW_TPA_N2
MAKE_BASE=TRUE
"Snapback" & "Late VG" Protection 402
NO_TEST=YES
B XW9070
SM
70 PP3V3_FW_ESD
B
69 FW_TPB2_P 1 2 FW_TPB2_PD
NO_TEST=YES
SM DP9020 DP9020
69 FW_TPB2_N 1 2 BAV99DW-X-F BAV99DW-X-F
NO_TEST=YES SOT-363 SOT-363
XW9071 C9020 1 2 C9021 1
5
0.001uF 0.001uF
R90701 20% 20%
1K
5%
50V
CERM 2
6 50V
CERM 2
3 PORT 2
402 402
1/16W
MF-LF
402 2
1 4 1394A EMI
FW_PORT2_TPA_P 4 3
70
SYM_VER-2
CRITICAL R9099
0
J9020 1 2
70 FW_PORT2_TPA_N 1
SM1
2 1394A 5%
1/16W
F-RT-TH-LF
ESD Rail 260-OHM-330MA MF-LF
402 =GND_CHASSIS_FW_EMI 2
6
PP3V3_FW_ESD_F FL9020 70 FW_PORT2_TPA_P_FL
TPO (TPA+)
VOLTAGE=3.3V 5
MIN_LINE_WIDTH=0.38 mm 70 FW_PORT2_TPA_N_FL (TPA-)
MIN_NECK_WIDTH=0.25 mm 70 FW_PORT2_TPB_P 4 SYM_VER-2 3 TPO#
70 FW_PORT2_TPB_P_FL 4 (TPB+)
L9090 TPI
69 10 =PP3V3_FW R9090 400-OHM-EMI PP3V3_FW_ESD 70 70 FW_PORT2_TPB_N 1 2 70 FW_PORT2_TPB_N_FL 3
TPI# (TPB-)
1
604 2 1 2 VOLTAGE=3.3V SM1
1% SM-1 MIN_NECK_WIDTH=0.25 mm DP9021 DP9021 260-OHM-330MA
FL9021 (PPFW_PORT2_VP) VP
1/16W BAV99DW-X-F BAV99DW-X-F
C9090 1 MF-LF 1 C9091 1 C9092 3
SOT-363 SOT-363 2
VGND
0.1uF
20%
402
0.1uF
20%
0.001uF
10%
D9090 2 5 (GND_FW_PORT2_VG)
10V 10V 50V BZX84C2V7-X-F 7 8 9 10
CERM 2
402
2 CERM
402
2 CERM
402
1
SOT23
C9022 1
6
C9023 1
3
1 C9025 C9026 1 FireWire Ports
0.001uF 1 0.001uF 4 0.01uF 0.01uF
A 20%
50V
CERM 2
20%
50V
CERM 2
20%
50V
2 CERM
20%
16V
CERM 2
514-0255
SYNC_MASTER=MARIAS-PDIFF

A
402 402 603 402

=GND_CHASSIS_FW_PORT2 2 AGREES TO THE FOLLOWING
DRAWING APPLE COMPUTER INC.

D 051-6839 F
TITLE=PLASMA SCALE SHT OF
ABBREV=DRAWING
LAST_MODIFIED=Tue Nov 29 17:35:04 2005
NONE 90 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
Place series terminators approximately halfway between Vesta and NB.

(They should probably be slightly closer to Vesta than the NB.).
RP9100
1
0 8
6 =RP9100P1 =RP9100P8 6
5%
1/16W
RP9100
SM-LF 0
6 =RP9100P2 2 7 =RP9100P7 6
RP9100 5%
1/16W
0 SM-LF
6 =RP9100P3 3 6 =RP9100P6 6
5%
1/16W
RP9100
SM-LF 4
0 5
6 =RP9100P4 =RP9100P5 6
RP9101 5%
1/16W
0
C 6 =RP9101P1 1 8 SM-LF
=RP9101P8 6 C
5%
1/16W
RP9101
SM-LF 0
6 =RP9101P2 2 7 =RP9101P7 6
RP9101 5%
1/16W
0 SM-LF
6 =RP9101P3 3 6 =RP9101P6 6
5%
1/16W
RP9101
SM-LF 0
6 =RP9101P4 4 5 =RP9101P5 6
5%
1/16W
SM-LF
R9100
0
68 9 FW_CTL_R<0> 1 2 FW_CTL<0> 9 69
5%
1/16W
MF-LF R9101
402
1
0 2
68 9 FW_CTL_R<1> FW_CTL<1> 9 69
5%
1/16W
MF-LF
402
R9102
1
0 2
68 9 FW_LPS_R FW_LPS 9 69
5%
1/16W
MF-LF R9103
402
1
0 2
68 9 FW_LREQ_R FW_LREQ 9 69
B 5%
1/16W
MF-LF
B
402
FireWire Series Term


A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 91 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
USB2_0 USB2 USB2 USB2_I2_0 USB2_I2_P<0> 11 72
USB2_0 USB2 USB2 USB2_I2_0 USB2_I2_N<0> 11 72
D USB2_3 USB2 USB2 USB2_I2_3 USB2_I2_N<3> 6 72

D
USB2_I2_XTAL XTAL XTAL I2_CLK30M_USB2_XOUT_R 72
(USB2_I2_XTAL) XTAL XTAL I2_CLK30M_USB2_XOUT 72
(USB2_I2_XTAL) XTAL XTAL I2_CLK30M_USB2_XIN 72
Page Notes
- =PP3V3_PWRON_USB

- =RP92xxPy (pinswappable USB pulldowns)

(NONE)
Net Spacing Type: USB2

Line To Line: 19.5 mils
Length Tolerance: 50 mils
OMIT
Primary Max Sep: 7.5 mils
Secondary Max Sep: 100 mils U2100
C Secondary Length: 500 mils I2
BGA
C
NOTE: Target differential impedance for
USB INTERFACE
USB2 data pairs is 90 ohms. R9250
10 =PP1V5_PWRON_I2_USBPLL (14 of 14)
4.7 R8 R6
1 2 PP1V5_PWRON_I2_PLLUSBAVDD PLLUSB_AVDD USB_VD_0_P USB2_I2_P<0> 11 72
VOLTAGE=1.5V R7
5% MIN_LINE_WIDTH=0.25 mm USB_VD_0_N USB2_I2_N<0> 11 72
C9250 1 MF-LF
402
1 C9251
1uF 0.1uF USB_VD_1_P N7 USB2_I2_P<1> 6 72
10% 20%
6.3V 10V N6 USB2_I2_N<1>
CERM 2 2 CERM USB_VD_1_N 6 72
402 402
N4 USB2_I2_P<2>
R9 USB_VD_2_P 11 72
PLLUSB_VSSA N3
USB_VD_2_N USB2_I2_N<2> 11 72
N2 USB2_I2_P<3>
USB_VD_3_P 6 72
Put crystal circuit close to I2 N1
N5 USB_VD_3_N USB2_I2_N<3> 6 72
72 I2_CLK30M_USB2_XOUT_R USB_XTALOSC_HI
72 I2_CLK30M_USB2_XIN P10
NO STUFF USB_XTALOSC_LO R4
USB_VD_4_P USB2_I2_P<4> 11 72
R9220 USB_VD_4_N R3 USB2_I2_N<4> 11 72
10M
1 2
R1 USB2_I2_P<5>
5% USB_VD_5_P 11 72
1/16W
T9 R2
R9221 1 MF-LF
402
I2_USB2_VREF USB_VREF USB_VD_5_N USB2_I2_N<5> 11 72
0
5% 1
1/16W
MF-LF
CRITICAL R9200
402 2 Y9220 1K
1%
30.0000M 1/16W
1 2
MF-LF
402
72 I2_CLK30M_USB2_XOUT 2
B 8X4.5MM-SM1
B
C9221 1
C9220 1
22pF 22pF
5% 5%
50V 50V
CERM 2 CERM 2
402 402
Crystal load capacitance is 16pF

RP9210
15K
5%
1 8 =RP9210P8 6
2 7 =RP9210P7 6
3 6 =RP9210P6 6
4 5 =RP9210P5 6
1/16W
SM-LF
RP9211
15K
5%
1 8 =RP9211P8 6
2 7 =RP9211P7 6
3 6 =RP9211P6 6 One pair for each port USB2_*<0..5>
4 5 =RP9211P5 6
1/16W
SM-LF
I2 USB Interface
RP9212
A 15K
5%
SYNC_MASTER=MARIAS

A
1 8 =RP9212P8 6
2 7 =RP9212P7 6 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
3 6 PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
=RP9212P6 6 AGREES TO THE FOLLOWING
4 5 =RP9212P5 6 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
1/16W II NOT TO REPRODUCE OR COPY IT
SM-LF
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 92 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
I30 USB2 USB2 USB2_NEC_0 USB2_NEC_P<0> 11 73
I31 USB2 USB2 USB2_NEC_0 USB2_NEC_N<0> 11 73
PROVIDED BY I2 PAGES
USB2 USB2 USB2_NEC_3 USB2_NEC_N<3> 11 73
D
I37
D
USB2_NEC
USB2_NEC_XTAL XTAL XTAL NEC_CLK30M_XT1
I40
XTAL XTAL NEC_CLK30M_XT2
73
L9335 PP3V3_PWRON_NEC_AVDD
VOLTAGE=3.3V
I41 73
73 10 =PP3V3_PWRON_USB2 FERR-EMI-100-OHM MIN_LINE_WIDTH=0.5 mm
I42 XTAL XTAL NEC_CLK30M_XT2_R 73 MIN_NECK_WIDTH=0.25 mm
1 2
SM USB2_NEC USB2_NEC USB2_NEC
USB2_NEC
C9335 C9336 C9337
Page Notes R9335
1
4.7 2
10uF
20%
6.3V
X5R
0.1uF
20%
10V
CERM 2
1
0.1uF
20%
10V
CERM 2
1
Power aliases required by this page: 5% 603 402 402

- =PP3V3_PWRON_USB2 1/10W
MF-LF
603
(NONE)
USB2_NEC USB2_NEC USB2_NEC USB2_NEC USB2_NEC USB2_NEC
P12
A13
A12
L13
J13
H13
F13
D13
G12
N10
N12
C9320 1 C9321 1 C9322 1 C9323 1 C9324 1 C9325 1
P2
P3
A3
E2
N8
H4
D7
BOM options provided by this page: USB2_NEC
USB2_NEC 10uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20%
0.1uF
20% VDD
R9300
6.3V 10V 10V 10V 10V 10V 1
39.2 2
X5R 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2
AVDD
Net Spacing Type: USB2 603 402 402 402 402 402 1%
1/16W
RSDM1 M14 USB_NEC_N<0> MF-LF
NOTE: Target differential impedance for M13
402
USB2_NEC_N<0>
DM1 (USB2_NEC_N<0>) 11 73
USB2 data pairs is 90 ohms. USB2_NEC USB2_NEC USB2_NEC USB2_NEC USB2_NEC L14 USB2_NEC_P<0>
DP1 (USB2_NEC_P<0>)
C9326 1 C9327 1 C9328 1 C9329 1 C9330 1
USB2_NEC RSDP1 K13 USB_NEC_P<0> USB2_NEC
11 73
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

20%
10V
20%
10V
20%
10V
20%
10V
20%
10V CRITICAL R9301
CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 39.2 2
402 402 402 402 402 U7500 1
1%
NEC_uPD720101_USB2 1/16W
C FBGA-LF
MF-LF
402
USB2_NEC
C
R9302
1
39.2 2
73 10 =PP3V3_PWRON_USB2
1%
1/16W
RSDM2 K14 USB_NEC_N<1> MF-LF
402
DM2 K12 (USB2_NEC_N<1>) USB2_NEC_N<1> 11 73
USB2_NEC 8 7 6 5 USB2_NEC J14
DP2 (USB2_NEC_P<1>) USB2_NEC_P<1> 11 73
R93102 RP9310 RSDP2 J12 USB_NEC_P<1> USB2_NEC
10K 10K R9303
5% 5%
1/16W 1/16W 1
39.2 2
MF-LF
402 1 SM-LF
1%
1 2 3 4 1/16W
MF-LF
402
USB2_OC<0> B12 OCI1
B11 OCI2 USB2_NEC
USB2_OC<1> R9304
USB2_OC<2> B10 OCI3 36
1 2
USB2_OC<3> A10 OCI4
1%
USB2_OC<4> B9 OCI5 1/16W USB2_NEC
RSDM3 H11 USB_NEC_N<2> MF-LF
DM3 G11 (USB2_NEC_N<2>)
402
USB2_NEC_N<2>
RP9300
TP_USB2_PWREN<0> C12 PPON1 11 73
15K
A11 PPON2 DP3 G13 (USB2_NEC_P<2>) USB2_NEC_P<2> 11 73 5%
TP_USB2_PWREN<1>
C11 PPON3 RSDP3 G14 USB_NEC_P<2> USB2_NEC 1 8 =RP9300P8 6
TP_USB2_PWREN<2>
C10 PPON4
R9305 2 7 =RP9300P7 6
TP_USB2_PWREN<3> 36 3 6
A9 PPON5
1 2 =RP9300P6 6
TP_USB2_PWREN<4>
1% 4 5 =RP9300P5 6
1/16W
MF-LF 1/16W
402 SM-LF
B USB2_NEC
R9306
USB2_NEC
RP9301 B
1
36 2 15K
5%
1%
1/16W 1 8 =RP9301P8 6
RSDM4 F12 USB_NEC_N<3> MF-LF
402 2 7 =RP9301P7 6
73 10 =PP3V3_PWRON_USB2 DM4 F14 (USB2_NEC_N<3>) USB2_NEC_N<3> 11 73
3 6 =RP9301P6 6
DP4 E12 (USB2_NEC_P<3>) USB2_NEC_P<3> 11 73
4 5 =RP9301P5 6
USB2_NEC USB2_NEC RSDP4 E14 USB_NEC_P<3> USB2_NEC
R93401 1
R9341 R9307 1/16W
SM-LF
36
1.5K 1.5K 1 2
5% 5%
1/16W 1/16W 1%
MF-LF MF-LF 1/16W
402 2 MF-LF
2 402 402
NEC_NC1_PU P6 NC1
NEC_NC2_PU M6 NC2
RSDM5 E13 NC
DM5 D14
DP5 C13
RSDP5 C14 NC
73 NEC_CLK30M_XT1 L9 XT1/SCLK
73 NEC_CLK30M_XT2_R P8 XT2
USB2_NEC
2
R9345
100
5%
NEC USB2 Interface
1/16W
RREF P11 NEC_RREF_PD
A OMIT MF-LF SYNC_MASTER=MARIAS SYNC_DATE=08/24/2005
A
TABLE_5_HEAD
AVSS(R)
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION CRITICAL 1 402 USB2_NEC
TABLE_5_ITEM
Y9345 1 NOTICE OF PROPRIETARY PROPERTY

197S0087 1 XTAL,CER,30.0000MHZ,LW PROF,8X4.5MM,SMD Y9345 CRITICAL USB2_NEC 30.0000M
1 2
NEC_CLK30M_XT2 73 R9338
9.09K THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
USB2_NEC USB2_NEC VSS AVSS 1% PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
P10
N14
H14
B14
N13
B13
M11
L12
H12
D12
J11
F11
P13
M12
N11
8X4.5MM-SM
B1
N1
A2
B2
N2
G4
D8
MF-LF
C9345 1 1 C9346 R9339 402 2 I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
22pF 22pF 0 Tie to GND at ball N11 II NOT TO REPRODUCE OR COPY IT
5% 5% 2 1
50V 50V
CERM 2 2 CERM
5% GND_NEC_AVSS_R
402 402 1/10W VOLTAGE=0V
MF-LF MIN_LINE_WIDTH=0.5 mm SIZE DRAWING NUMBER REV.
Y9345 LOAD CAPACITANCE IS 16pF

USB2_NEC
APPLE COMPUTER INC.
D 051-6839 F
SCALE SHT OF
NONE 93 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
AUDIO BOARD CONNECTOR

Place all shorts at output of 3.3V and 5V regulator
PLACE SHORTS AT POWER SUPPLY

CRITICAL
XWA051 JA000
QT500406-L121
SM
C 10 =PP5V_PWRON_AUDIO_PVDD 1 2 7 PP5V_PWRON_AUDIO_PVDD
VOLTAGE=5V
M-ST-SM
41 42 C
1 2
3 4
XWA050
SM 5 6
10 =PP5V_PWRON_AUDIO_AVDD 1 2 7 PP5V_PWRON_AUDIO_AVDD 7 8
VOLTAGE=5V 9 10
13 14
XWA033
SM
22 7 I2S0_DEV_TO_SB_DTI 15 16 =FTP_SLEEP_LED 7
7 6 I2S0_SB_TO_DEV_DTO 17 18 (SLEEP_LED_RETURN)
10 =PP3V3_PWRON_AUDIO_AVDD 1 2 7 PP3V3_PWRON_AUDIO_AVDD
VOLTAGE=3.3V 22 7 AUDIO_I2S_DTIB_SEL 19 20 =SLEEP_LED_CONN 11
MIN_LINE_WIDTH=0.38 mm 21 22
MIN_NECK_WIDTH=0.25 mm 22 7 AUDIO_SPKR_MUTE_L =I2C_AUDIO_SCL 7 8
22 7 AUDIO_LO_MUTE_L 23 24 =I2C_AUDIO_SDA 7 8
22 7 AUDIO_EXT_MCLK_SEL 25 26 AUDIO_SPDIFRX_RESET_L 7 22
22 7 AUDIO_GPIO_11 AUDIO_SPDIF_RXERR_INT 27 28 AUDIO_CODEC_RESET_L 7 22

22 7 AUDIO_LI_OPTICAL_PLUG_L I2S0_MCLK 6 7
22 7 AUDIO_LI_DET_L 31 32 I2S0_SYNC 6 7
22 7 AUDIO_LO_OPTICAL_PLUG_L 33 34 =PP3V3_RUN_AUDIO 7 10
22 7 AUDIO_LO_DET_L 35 36
37 38 I2S0_BITCLK 6 7
39 40 NO STUFF
1 CA010
43 44 0.001uF
CA033 1 CA051 1 20%
2 50V
0.1uF 0.1uF VER 1 CERM
402
10% 10%
B 16V 2
X5R
402
16V 2
X5R
402
NO STUFF
CA011 1 B
516S0154 0.001uF
PLACE SHORTS AT POWER SUPPLY
1 CA050 20%
50V
0.1uF CERM 2
10% 402
16V
2 X5R
XWA001
SM
402
1 2 7 GND_AUDIO_AGND
VOLTAGE=0V
XWA000
SM
1 2 7 GND_AUDIO_PGND
VOLTAGE=0V
Audio Board Connector

A SYNC_MASTER=N/A

SYNC_DATE=N/A
A
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 100 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AGP TABLE_SPACING_RULE
AUDIO
TABLE_SPACING_RULE
TABLE_SPACING_RULE
TABLE_SPACING_RULE
AUDIO 251 * 0.25 MM =STANDARD =STANDARD =STANDARD =STANDARD
AGP 401 * 0.4 MM =STANDARD =STANDARD =STANDARD =STANDARD
TABLE_SPACING_RULE TABLE_PHYSICAL_RULE
AGP_STB 601 * 0.6 MM 2.5 MM =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
AUDIO * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE
TABLE_PHYSICAL_RULE
AGP
TABLE_PHYSICAL_RULE
* =STANDARD =60_OHM_SE =60_OHM_SE =60_OHM_SE
TABLE_SPACING_RULE
I2S
AGP_STB * =STANDARD =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
D TABLE_SPACING_RULE
D
TABLE_SPACING_RULE
CLOCK I2S
TABLE_PHYSICAL_RULE
251 * 0.25 MM =STANDARD =STANDARD =STANDARD =STANDARD
TABLE_SPACING_RULE TABLE_PHYSICAL_RULE
CLOCK 251 * 0.25 MM =STANDARD =STANDARD =STANDARD =STANDARD I2S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
TABLE_SPACING_RULE
ENETCONN
CLOCK * =STANDARD =50_OHM_SE =50_OHM_SE =50_OHM_SE
TABLE_SPACING_RULE
TABLE_SPACING_RULE
ENET (Ethernet Digital) TABLE_SPACING_ASSIGNMENT
ENETCONN
TABLE_PHYSICAL_RULE
501 * 0.50 MM 3.81 MM =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
TABLE_SPACING_RULE TABLE_SPACING_ASSIGNMENT TABLE_PHYSICAL_RULE

ENET_SELF =STANDARD * =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD ENET ENET * ENET_SELF ENETCONN * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
TABLE_SPACING_RULE
ENET 201 * 0.2 MM =STANDARD =STANDARD =STANDARD =STANDARD
TABLE_PHYSICAL_RULE
TABLE_SPACING_RULE
FW_TP
TABLE_PHYSICAL_RULE
TABLE_SPACING_RULE
ENET * =STANDARD =50_OHM_SE =50_OHM_SE =50_OHM_SE
FW_TP 501 * 0.50 MM 3.81 MM =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF
TABLE_PHYSICAL_RULE
TABLE_SPACING_RULE
FW (FireWire Digital) TABLE_SPACING_ASSIGNMENT TABLE_PHYSICAL_RULE
FW_TP * =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF
TABLE_SPACING_RULE TABLE_SPACING_ASSIGNMENT
FW_SELF =STANDARD * =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD FW FW * FW_SELF
TABLE_SPACING_RULE
FW 201 * 0.2 MM =STANDARD =STANDARD =STANDARD =STANDARD
I2_FBCLK / XTAL
C TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
I2_FBCLK * * CLOCK
C
FW * =STANDARD =50_OHM_SE =50_OHM_SE =50_OHM_SE
XTAL * * CLOCK
TABLE_PHYSICAL_ASSIGNMENT
TABLE_SPACING_RULE
I2C TABLE_PHYSICAL_ASSIGNMENT
I2_FBCLK * CLOCK
TABLE_SPACING_RULE TABLE_PHYSICAL_ASSIGNMENT
I2C 201 * 0.2 MM =STANDARD =STANDARD =STANDARD =STANDARD XTAL * CLOCK
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
I2C * =STANDARD =50_OHM_SE =50_OHM_SE =50_OHM_SE
TABLE_SPACING_RULE
MaxBus
TABLE_SPACING_RULE
MAXBUS 151 * 0.15 MM =STANDARD =STANDARD =STANDARD =STANDARD
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
MAXBUS * =STANDARD =50_OHM_SE =50_OHM_SE =50_OHM_SE
TABLE_SPACING_RULE
PCI
TABLE_SPACING_RULE
PCI =STANDARD * =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD
B TABLE_PHYSICAL_RULE B
TABLE_PHYSICAL_RULE
PCI * =STANDARD =50_OHM_SE =50_OHM_SE =50_OHM_SE
TABLE_SPACING_RULE
RAM
TABLE_SPACING_RULE
RAM 201 * 0.2 MM =STANDARD =STANDARD =STANDARD =STANDARD
TABLE_SPACING_RULE
RAM_DIFF 251 * 0.25 MM 2.5 MM =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
RAM * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE
TABLE_PHYSICAL_RULE
RAM_DIFF * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
TABLE_SPACING_RULE
UATA
TABLE_SPACING_RULE
UATA 151 * 0.15 MM =STANDARD =STANDARD =STANDARD =STANDARD
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
UATA * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE Spacing & Physical Constraints
A TABLE_SPACING_RULE
USB2
SYNC_MASTER=MARIAS

A
TABLE_SPACING_RULE THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
USB2 501 * 0.50 MM 3.81 MM =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF AGREES TO THE FOLLOWING
TABLE_PHYSICAL_RULE I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
TABLE_PHYSICAL_RULE
USB2 * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 110 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
TABLE_SPACING_RULE
TABLE_SPACING_RULE
DVO 151 * 0.15 MM =STANDARD =STANDARD =STANDARD =STANDARD
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
DVO
DVO * =STANDARD =50_OHM_SE =50_OHM_SE =50_OHM_SE
TABLE_SPACING_RULE
TABLE_SPACING_RULE
TV 151 * =75_OHM_SE =75_OHM_SE =75_OHM_SE =75_OHM_SE =75_OHM_SE
TABLE_SPACING_RULE
TV_CONN 151 * =TV =TV =TV =TV =TV
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
S-VIDEO
TV * =75_OHM_SE =75_OHM_SE =75_OHM_SE =75_OHM_SE
TABLE_PHYSICAL_RULE
TV_CONN * =TV =TV =TV =TV
TABLE_SPACING_RULE
TABLE_SPACING_RULE
VGA 151 * =75_OHM_SE =75_OHM_SE =75_OHM_SE =75_OHM_SE =75_OHM_SE
TABLE_SPACING_RULE
B VGA_CONN 151 * =VGA =VGA =VGA =VGA =VGA

B
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
VGA
VGA * =75_OHM_SE =75_OHM_SE =75_OHM_SE =75_OHM_SE
TABLE_PHYSICAL_RULE
VGA_CONN * =VGA =VGA =VGA =VGA
TABLE_SPACING_RULE
TABLE_SPACING_RULE
LVDS 151 * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
LVDS
LVDS * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
TABLE_SPACING_RULE
TABLE_SPACING_RULE
TMDS 251 * 0.25 MM =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
TABLE_SPACING_RULE
TMDS_CONN =TMDS * =TMDS =TMDS =TMDS =TMDS =TMDS
TABLE_PHYSICAL_RULE
TABLE_PHYSICAL_RULE
TMDS
TMDS * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
TABLE_PHYSICAL_RULE
TMDS_CONN * =TMDS =TMDS =TMDS =TMDS Spacing & Physical Constraints 2
A TABLE_SPACING_RULE
TABLE_SPACING_RULE
SYNC_MASTER=MARIAS

A
THERM 251 * 0.25 MM =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF
TABLE_PHYSICAL_RULE PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
TABLE_PHYSICAL_RULE
THERM AGREES TO THE FOLLOWING
THERM * Y 0.25 MM =100_OHM_DIFF =100_OHM_DIFF II NOT TO REPRODUCE OR COPY IT
APPLE COMPUTER INC.

D 051-6839 F
SCALE SHT OF
NONE 111 115
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
*** Signal Cross-Reference for the entire design *** =GND_CHASSIS_LCD3 2D4> 56B6< =PP3V3_PCI_USB2 10B3< 62B6< =RP5610P3 6B5> 43C2< AC_DET_DIV 12C7< CBUS_BVD2_L 61B2< 61C4< EXT_TMDS_D1_CMF 54D2< FB_B_ADDR<8> 50B4< 50B7< FW_D<5> 6A6> 69B5<>
=GND_CHASSIS_LCD4 2D4> 56A5<> =PP3V3_PCI_ZDB 10B3< 23C5< =RP5610P4 6B5> 43C2< AC_ENABLE_GATE 12D5<> CBUS_CE1_L 61C1< 61C4> EXT_TMDS_D2_CMF 54C1< FB_B_ADDR<9> 50B4< 50B7< FW_D<6> 6A6> 69B5<>
1V5RUN_EN 16A6<> 26C6< =GND_CHASSIS_SVIDEO_HOLE 2D1<> 2D4> =PP3V3_PWRON_AUDIO_AVDD 10B4> 74B7<> =RP5611P1 6B5> 43B2< AC_ENABLE_L 12C5<> CBUS_CE2_L 61B2< 61B4> FAN1_PWM 7C5> 27C1<> 31B4<> FB_B_ADDR<10> 50B4< 50B7< FW_D<7> 6A6> 69B5<>
1V8RUN_EN_L 16A4<> 26B4<> =GND_CHASSIS_TV 2D4> 57A7<> =PP3V3_PWRON_BT 10B4> 60C6<> =RP5611P2 6B5> 43C2< AC_GTR_18V 13C3<> CBUS_DATA<0> 61A1< 61A4<> FAN1_TACH 7C5> 27C1< 31B4<> FB_B_ADDR<11> 50B4< 50B7< FW_D_R<0> 6A8< 68C3<
1V8_1V5PWRON_EN_L 26D4< =GPUVCORE_PGOOD 26A8< 45C6> =PP3V3_PWRON_CPUVCORE_OFFSET 10B3> 36B7< =RP5611P3 6B5> 43C2< ADAPTER_I_REG 13D3<> CBUS_DATA<1> 61A1< 61A4<> FAN2_PWM 7C5> 27C1<> 31B3<> FB_B_ADDR_R<11..0> 48D2< 48D5> FW_D_R<7..0> 9B3> 68D6>
1V20_REF 12C7< 14C8< =GPU_AGP_VREF 11C7> 44B4< =PP3V3_PWRON_CPUVCORE_VID 10B4> 36C8< 36D6< =RP5611P4 6B5> 43C2< ADT7467_ADR_ENABLE_L 27C2<> CBUS_DATA<2> 61A1< 61A4<> FAN2_TACH 7C5> 27C1< 31B3<> FB_B_ADDR_R<12..0> 42B6> FW_D_R<1> 6A8< 68C3<
1V65_REF 13A5< =I2C_ADT7467_SCL 8B1> 27C4< =PP3V3_PWRON_DS1775 10B4> 30D6< =RP6720P1 6D4> 54C8< AGP8X_DET_PU 44B6< CBUS_DATA<3> 61A4<> 61C1< FAN2558_ADJ_CPU0 37C5<> FB_B_BA<0> 50A4< 50A7< FW_D_R<2> 6A8< 68C3<
1_5V_BOOST 16C6<> =I2C_ADT7467_SDA 8B1> 27C4<> =PP3V3_PWRON_I2_AGPPCI 10B5< 19A5< =RP6720P2 6D4> 54B8< AGP_AD<0> 43D3< 44D6<> CBUS_DATA<4> 61A4<> 61C1< FAN2558_EN_CPU0 37C5<> FB_B_BA<1..0> 48C1> 50D1> FW_D_R<3> 6A8< 68B3<
1_5V_BST 16C5<> =I2C_AUDIO_SCL 7A7> 8D1> 74B3<> =PP3V3_PWRON_I2_IO1 10B5< 19C5< =RP6720P3 6D4> 54B8< AGP_AD<15..0> 43D6> CBUS_DATA<5> 61A4<> 61C1< FB_4_85V_BU 14A5< FB_B_BA<1> 50A4< 50A7< FW_D_R<4> 6A8< 68B3<
1_5V_DH 16C6<> =I2C_AUDIO_SDA 7A7> 8D1> 74B3<> =PP3V3_PWRON_I2_IO2 10B5< 19B5< =RP6720P4 6D4> 54B8< AGP_AD<1> 43D3< 44D6<> CBUS_DATA<6> 61A4<> 61C1< FB_A_ADDR<0> 49B4< 49B7< FB_B_BA_R<1..0> 48C2< 48C5> FW_D_R<5> 6A8< 68B3<
1_5V_DL 16B6<> =I2C_BATT_SCL 8B4> 12A5< =PP3V3_PWRON_I2_MAXBUS 10B4> 19B5< =RP6720P5 6D4< 54B7< AGP_AD<2> 43C3< 44C6<> CBUS_DATA<7> 61A4<> 61C1< FB_A_ADDR<11..0> 48D3> 49D1> FB_B_BA_R<2..0> 42B6> FW_D_R<6> 6A8< 68B3<
1_5V_FB 16B7< =I2C_BATT_SDA 8B4> 12A5< =PP3V3_PWRON_I2_MISC 10B5< 22B6< 22C7< =RP6720P6 6D4< 54B7< AGP_AD<3> 43C3< 44C6<> CBUS_DATA<8> 61A2< 61A4<> FB_A_ADDR<1> 49B4< 49B7< FB_B_CAS_L 48B1< 50A4< 50A7< 50C1> FW_D_R<7> 6A8< 68B3<
1_5V_ILIM 16C5<> =I2C_DS1775_SCL 7C5> 8B1> 30C6<> =PP3V3_PWRON_INVERTER 10B4> 56B4< =RP6720P7 6D4< 54B7< AGP_AD<4> 43C3< 44C6<> CBUS_DATA<9> 61A2< 61A4<> FB_A_ADDR<2> 49B4< 49B7< FB_B_CAS_L_R 42B6> 48B2< 48B5> FW_LINKON 68C5< 68D6> 69C2>
1_5V_LX 16B5<> =I2C_DS1775_SDA 7C5> 8B1> 30C6<> =PP3V3_PWRON_JTAG_ASIC 9C8< 10B5< =RP6720P8 6D4< 54C7< AGP_AD<5> 43C3< 44C6<> CBUS_DATA<10> 61A2< 61A4<> FB_A_ADDR<3> 49B4< 49B7< FB_B_CKE 48B1< 50A4< 50A7< 50D1> FW_LPS 9A3> 69B5< 71B4<
1_8V_BOOST 16C4<> =I2C_GPU_TMDS_SCL 8A5< 51B3<> =PP3V3_PWRON_LCD 10B4> 56C8<> =RP6721P1 6D4> 54B8< AGP_AD<6> 43C3< 44C6<> CBUS_DATA<11> 61A4<> 61C2< FB_A_ADDR<4> 49B4< 49B7< FB_B_CKE_R 42B6> 48B2< 48B5> FW_LPS_R 9B3> 68B3< 68D6> 71B6<
1_8V_BST 16C4<> =I2C_GPU_TMDS_SDA 8A5< 51B3<> =PP3V3_PWRON_LEFT_ALS 7B5> 10B4> 31C3<> =RP6721P2 6D4> 54B8< AGP_AD<7> 43C3< 44C6<> CBUS_DATA<12> 61A4<> 61C2< FB_A_ADDR<5> 49B4< 49B7< FB_B_CLKDDR_0_N 48B1< 50A7< 50D1> FW_LREQ 9A3> 69B5< 71B4<
1_8V_DH 16C3<> =I2C_I2_NB_SCL 8C3< 22C2< =PP3V3_PWRON_LTC3412 10B4> 17D6< =RP6721P3 6D4> 54B8< AGP_AD<8> 43C3< 44C6<> CBUS_DATA<13> 61A4<> 61C2< FB_A_ADDR<6> 49B4< 49B7< FB_B_CLKDDR_0_N_R 42C6> 48B2< 48B5<> FW_LREQ_R 9A3> 68B3< 68D6> 71B6<
1_8V_DL 16B3<> =I2C_I2_NB_SDA 8C3< 22C2< =PP3V3_PWRON_MMM 10B4> 29C6< =RP6721P4 6D4> 54B8< AGP_AD<9> 43C3< 44C6<> CBUS_DATA<14> 61A4<> 61C2< FB_A_ADDR<7> 49B4< 49B7< FB_B_CLKDDR_0_P 48B1< 50A7< 50D1> FW_PINT 68B5< 68D6> 69C2>
D
1_8V_FB
1_8V_ILIM
1_8V_LX
16B4<
16C5<>
16B3<>
=I2C_I2_SB_SCL
=I2C_I2_SB_SDA
=I2C_PMU_SCL
8D3< 22C2<
8D3< 22B2<
8C5< 25C5<>
=PP3V3_PWRON_MODEM 10B4> 30B4<>
=PP3V3_PWRON_PMU 10B4> 25B8<
=PP3V3_PWRON_PWRSEQ 10B5< 26C5< 26C7<>
=RP6721P5
=RP6721P6
=RP6721P7
6D4<
6D4<
6D4<
54B7<
54B7<
54B7<
AGP_AD<10>
AGP_AD<11>
AGP_AD<12>
43C3<
43C3<
43C3<
44C6<>
44C6<>
44C6<>
CBUS_DATA<15>
CBUS_DET_1_L
CBUS_DET_2_L
61A4<> 61C2<
61C2< 61C4<
61A2< 61C4<
FB_A_ADDR<8>
FB_A_ADDR<9>
FB_A_ADDR<10>
49B4< 49B7<
49B4< 49B7<
49B4< 49B7<
FB_B_CLKDDR_0_P_R 42C6> 48B2< 48B5<>
FB_B_CLKDDR_1_N 48A1< 50A4< 50D1>
FB_B_CLKDDR_1_N_R 42C6> 48A2< 48B5<>
FW_PORT1_AREF
FW_PORT1_TPA_N
70C2<>
70C5> 70C5<>
FW_PORT1_TPA_N_FL 70C2<> 70D6>
D
1_8V_PVDD_STD 51C1< =I2C_PMU_SDA 8C5< 25C5<> =PP3V3_PWRON_REG 10B6<> 15D1< =RP6721P8 6D4< 54B7< AGP_AD<13> 43C3< 44C6<> CBUS_INPACK_L 61B2< 61B4< FB_A_ADDR<11> 49B4< 49B7< FB_B_CLKDDR_1_P 48B1< 50A4< 50D1> FW_PORT1_TPA_P 70C5> 70C5<>
2V5PWRON_EN_L 26D4< =I2C_PMU_SMB_SCL 8B5< 25C5<> =PP3V3_PWRON_RT_ALS 10B5< 28D5< =RP6722P1 6C4> 54A8< AGP_AD<14> 43C3< 44C6<> CBUS_IORD_L 61B2< 61C4> FB_A_ADDR_R<11..0> 48D4< 48D6> FB_B_CLKDDR_1_P_R 42C6> 48B2< 48B5<> FW_PORT1_TPA_P_FL 70C2<> 70D6>
2V5RUN_EN_L 17A5<> 26C6< =I2C_PMU_SMB_SDA 8B5< 25C5<> =PP3V3_PWRON_RUNFET 10B4> 15B2<> =RP6722P2 6C4> 54A8< AGP_AD<15> 43C3< 44C6<> CBUS_IOWR_L 61B2< 61C4> FB_A_ADDR_R<12..0> 42D6> FB_B_CS_L 48B1< 50A4< 50A7< 50D1> FW_PORT1_TPB_N 70C5> 70D5<>
3V3RUN_EN_L 15B3<> 26C5< =I2C_SI_M_SCL 8A4> 54B6< =PP3V3_PWRON_TPS2211 10B4> 61D4< =RP6722P3 6C4> 54A8< AGP_AD<16> 43C3< 44C6<> CBUS_MFUNC1_PD 61A7<> 61A7< FB_A_BA<0> 49A4< 49A7< FB_B_CS_L_R 42B6> 48B2< 48B5> FW_PORT1_TPB_N_FL 70D2<> 70D6>
3V_BG 15C4<> =I2C_SI_M_SDA 8A4> 54B6< =PP3V3_PWRON_USB2 10A4> 73B6< 73C6< 73D5< =RP6722P4 6C4> 54A8< AGP_AD<31..16> 43D6> CBUS_MFUNC2_PD 61A7<> 61A7< FB_A_BA<1..0> 48C3> 49D1> FB_B_DDRCLK_0_RC 50A7< FW_PORT1_TPB_P 70C5> 70D5<>
3V_BOOST 15C4<> =I2C_SI_S_SCL 8A4> 55B6< =PP3V3_PWRON_VDDSPD 10B5< 40A6<> 41A4<> 41A6<> =RP6722P5 6C4< 54A7< AGP_AD<17> 43C3< 44C6<> CBUS_MFUNC3_PD 61A7<> 61A7< FB_A_BA<1> 49A4< 49A7< FB_B_DDRCLK_1_RC 50A4< FW_PORT1_TPB_P_FL 70D2<> 70D6>
3V_BOOST_ESR 15D3<> =I2C_SI_S_SDA 8A4> 55B6< =PP3V3_PWRON_VGASYNC 10B4> 57C2< 57C2< =RP6722P6 6C4< 54A7< AGP_AD<18> 43C3< 44C6<> CBUS_MFUNC4_PD 61A7<> 61A7< FB_A_BA_R<1..0> 48C4< 48C6> FB_B_DQ<0> 50B5<> FW_PORT2_TPA_N 70A5<> 70C5>
3V_ITH 15C4<> =I2C_SODIMM_SCL 8C1> 40A6<> 41A6<> =PP3V3_RUN_AUDIO 7A7> 10B3< 74B3<> =RP6722P7 6C4< 54A7< AGP_AD<19> 43C3< 44C6<> CBUS_MFUNC5_PD 61A7<> 61A7< FB_A_BA_R<2..0> 42D6> FB_B_DQ<63..0> 48A1> 50C1> FW_PORT2_TPA_N_FL 70A3<> 70D6>
3V_ITH_RC 15C3< =I2C_SODIMM_SDA 8C1> 40A6<> 41A6<> =PP3V3_RUN_FANTACH 10B1> 27D2< =RP6722P8 6C4< 54A7< AGP_AD<20> 43C3< 44C6<> CBUS_MFUNC6_PD 61A7<> 61A7< FB_A_CAS_L 48B3< 49A4< 49A7< 49C1> FB_B_DQ<1> 50B5<> FW_PORT2_TPA_P 70B5<> 70C5>
3V_PMU_VTAP 14B3< =I2VCORE_PGOOD 20C4> 26B8< =PP3V3_RUN_FWPORTPWRSW 10B1> 18C8< =RP6723P1 6C4> 54A8< AGP_AD<21> 43B3< 44C6<> CBUS_OE_L 61B1< 61C4> FB_A_CAS_L_R 42D6> 48B4< 48B6> FB_B_DQ<2> 50B5<> FW_PORT2_TPA_P_FL 70A3<> 70D6>
3V_RSNS 15D2< =I2_AGP_FBCLK_IN 21C5> 43A5< =PP3V3_RUN_HDD 10B1> 64B8< 64C7< =RP6723P2 6C4> 54A8< AGP_AD<22> 43B3< 44C6<> CBUS_READY 61B1< 61C4< FB_A_CKE 48B3< 49A4< 49A7< 49D1> FB_B_DQ<3> 50B5<> FW_PORT2_TPB_N 70A5<> 70C5>
3V_RUNSS 15C4< =I2_AGP_VREF 11C7> 43B5< =PP3V3_RUN_KEYBRD_LED 10B1> 28B6< =RP6723P3 6C4> 54A8< AGP_AD<23> 43B3< 44C6<> CBUS_REG_L 61B2< 61C4> FB_A_CKE_R 42D6> 48B4< 48B6> FB_B_DQ<4> 50B5<> FW_PORT2_TPB_N_FL 70A3<> 70D6>
3V_SNSM 15C4< =I2_MAXBUS_FBCLK_IN 21D1> 32A6< =PP3V3_RUN_PCI1510_R 10B1> 61D7< =RP6723P4 6C4> 54A8< AGP_AD<24> 43B3< 44C6<> CBUS_RESET_L 61B2< 61C4> FB_A_CLKDDR_0_N 48B3< 49A7< 49D1> FB_B_DQ<5> 50B5<> FW_PORT2_TPB_P 70A5<> 70C5>
3V_SNSP 15C4< =I2_PCI_FBCLK_IN 21B5> 59A5< =PP3V3_RUN_PWRSEQ 10B3< 26B7< =RP6723P5 6C4< 54A7< AGP_AD<25> 43B3< 44C6<> CBUS_SUSPEND_PU 61A7< 61B7< FB_A_CLKDDR_0_N_R 42D6> 48B4< 48B6<> FB_B_DQ<6> 50A5<> FW_PORT2_TPB_P_FL 70A3<> 70D6>
3V_SW 15C4<> =I2_STOPCPU_L 11B3> 22A5< =PP3V3_RUN_RUNFET 10B3< 15B1<> =RP6723P6 6C4< 54A7< AGP_AD<26> 43B3< 44C6<> CBUS_VCCD0_L 61C5<> FB_A_CLKDDR_0_P 48B3< 49A7< 49D1> FB_B_DQ<7> 50A5<> FW_POWERDOWN 22A7< 22C5<
3V_TG 15D4<> =I2_STOPXTAL_L 11B3> 22A5< =PP3V3_RUN_SI 10B1> 54C2< 54C3< 54C5< 55C3< =RP6723P7 6C4< 54A7< AGP_AD<27> 43B3< 44C6<> CBUS_VCCD1_L 61C5<> FB_A_CLKDDR_0_P_R 42D6> 48B4< 48B6<> FB_B_DQ<8> 50A5<> FW_TPA0_C 70C7<
3V_VOSNS 15C4<> =JTAG_BBANGER_TCK 9D8< 25B5<> 55D3< 55D3< =RP6723P8 6C4< 54A7< AGP_AD<28> 43B3< 44B6<> CBUS_VPPD0 61C5<> FB_A_CLKDDR_1_N 48A3< 49A4< 49D1> FB_B_DQ<9> 50A5<> FW_TPA0_N 69B2<> 69D6> 70C7<
5V3V3PWRON_EN_L 26D6< =JTAG_BBANGER_TDI 9D8< 25B5<> =PP3V3_VESTA 10D4> 18A2< 18A6< 18A8< 65C2<> =RP6821P1 6C4> 55B8< AGP_AD<29> 43B3< 44B6<> CBUS_VPPD1 61C5<> FB_A_CLKDDR_1_N_R 42D6> 48A4< 48B6<> FB_B_DQ<10> 50A5<> FW_TPA0_P 69B2<> 69D6> 70C7<
5V3VPWRON_EN_L_RC 15B6< =JTAG_BBANGER_TMS 9D8< 25B5<> 66C7< 67C6<> =RP6821P2 6C4> 55B8< AGP_AD<30> 43B3< 44B6<> CBUS_VS1 61B2< 61C4<> FB_A_CLKDDR_1_P 48B3< 49A4< 49D1> FB_B_DQ<11> 50A5<> FW_TPA1_C 70C6<
5VRUNHD_EN_L 15B5<> 26D5< =JTAG_BBANGER_TRST_L 9D8< 25C5<> =PP3V3_VESTA_1V2REG 10D4> 18C5< =RP6821P3 6C4> 55B8< AGP_AD<31> 43B3< 44B6<> CBUS_VS2 61B2< 61C4<> FB_A_CLKDDR_1_P_R 42D6> 48B4< 48B6<> FB_B_DQ<12> 50A5<> FW_TPA1_N 69B2<> 69D6> 70C7<
5VRUN_EN_L 15A5<> 26D5< =JTAG_CPU0_TCK 9D5> 34D6< =PP3V3_VESTA_2V5REG 10D4> 18D3<> =RP6821P4 6C4> 55B8< AGP_AD_STB0_N 43B2< 43C3< 43D6> 44B4<> CBUS_WAIT_L 61B2< 61B4< FB_A_CS_L 48B3< 49A4< 49A7< 49D1> FB_B_DQ<13> 50A5<> FW_TPA1_P 69B2<> 69D6> 70C7<
5VTPAD_EN_L 26D4< =JTAG_CPU0_TDI 9D6> 34D6< =PP3V3_VESTA_REG 10D6< 18D3< =RP6821P5 6C4< 55B7< AGP_AD_STB0_P 43B2< 43C3< 43D6> 44B4<> CBUS_WE_L 61B1< 61C4> FB_A_CS_L_R 42D6> 48B4< 48B6> FB_B_DQ<14> 50A5<> FW_TPA2_N 69B2<> 69D6> 70B7<
5V_BG 15C5<> =JTAG_CPU0_TDO 9D6< 34D6> =PP4V85_ALL_A29_DET 10C6> 12D4< =RP6821P6 6C4< 55B7< AGP_AD_STB1_N 43A2< 43B3< 43D6> 44B4<> CBUS_WP_L 61A1< 61B4< FB_A_DDRCLK_0_RC 49A7< FB_B_DQ<15> 50A5<> FW_TPA2_P 69B2<> 69D6> 70B7<
5V_BOOST 15C5<> =JTAG_CPU0_TMS 9D5> 34D6< =PP4V85_ALL_VREG 10C8< 14B4<> =RP6821P7 6C4< 55B7< AGP_AD_STB1_P 43B2< 43B3< 43D6> 44B4<> CHARGE_DISABLE 13A7<> FB_A_DDRCLK_1_RC 49A4< FB_B_DQ<16> 50A5<> FW_TPB0_N 69B2<> 69D6> 70C7<
5V_BOOST_ESR 15D6<> =JTAG_CPU0_TRST_L 9D5> 34D6< =PP5V_FAN1_PWR 7C5> 10C1> 31B4<> =RP6821P8 6C4< 55B7< AGP_ATI_RESET_L 44C4< CLKLVDS_L_N 7C7> 53A7> 53C1> 56B5<> FB_A_DQ<0> 49A5<> FB_B_DQ<17> 50A5<> FW_TPB0_P 69B2<> 69D6> 70C7<
5V_ITH 15C5<> =JTAG_I2_TCK 9B6> 22B5< =PP5V_FAN2_PWR 7C5> 10C1> 31B3<> =RP6822P1 6C4> 55B8< AGP_BUSY_L 43D2< 43D5< 44B4> CLKLVDS_L_P 7C7> 53A7> 53C1> 56B5<> FB_A_DQ<63..0> 48A3> 49C1> FB_B_DQ<18> 50A5<> FW_TPB1_N 69B2<> 69D6> 70C7<
5V_ITH_RC 15C6< =JTAG_I2_TDI 9C6> 22B5< =PP5V_PWRON_AUDIO_AVDD 10C4> 74C7<> =RP6822P2 6C4> 55A8< AGP_CBE_L<0> 43C3< 44C4<> CLKLVDS_U_N 7C7> 53B7> 53D1> 56B5<> FB_A_DQ<1> 49A5<> FB_B_DQ<19> 50A5<> FW_TPB1_P 69B2<> 69D6> 70C7<
5V_RSNS 15D7< =JTAG_I2_TDO 9C6< 22B2< =PP5V_PWRON_AUDIO_PVDD 10C4> 74C7<> =RP6822P3 6C4> 55A8< AGP_CBE_L<1..0> 43D6> CLKLVDS_U_P 7C7> 53B7> 53D1> 56B5<> FB_A_DQ<2> 49A5<> FB_B_DQ<20> 50A5<> FW_TPB2_N 69B2<> 69D6> 70B7<>
5V_RUNSS 15C5< =JTAG_I2_TMS 9B6> 22B5< =PP5V_PWRON_CPUVCORE_PWRSEQ 10C3> 36C8< =RP6822P4 6C4> 55A8< AGP_CBE_L<1> 43C3< 44C4<> COMM_DTR_L 24C2<> FB_A_DQ<3> 49A5<> FB_B_DQ<21> 50A5<> FW_TPB2_P 69B2<> 69D6> 70B7<>
5V_SNSM 15C5< =JTAG_I2_TRST_L 9B6> 22A5< =PP5V_PWRON_CPUVCORE_VDD 10C4> 36C6<> =RP6822P5 6C4< 55A7< AGP_CBE_L<2> 43B3< 44C4<> COMM_RTS_L 24C2<> FB_A_DQ<4> 49A5<> FB_B_DQ<22> 50A5<> FW_TPB2_PD 70B6<>
5V_SNSP 15C5< =JTAG_VESTA_TCK 9A6> 18A6< =PP5V_PWRON_GPUVCORE_PWRPLAY 10C3> 45B5< =RP6822P6 6C4< 55A7< AGP_CBE_L<3..2> 43D6> COMP_DISABLE 57A4<> FB_A_DQ<5> 49A5<> FB_B_DQ<23> 50A5<> FW_TPBIAS0 69B2> 70D7<
5V_SW 15C5<> =JTAG_VESTA_TDI 9A6> 18A6< =PP5V_PWRON_INVERTER 10B4> 56C4<> =RP6822P7 6C4< 55A7< AGP_CBE_L<3> 43B3< 44C4<> COMP_ENABLE 57A3<> FB_A_DQ<6> 49A5<> FB_B_DQ<24> 50B5<> FW_TPBIAS1 69B2> 70D7<
5V_TG 15C5<> =JTAG_VESTA_TDO 9A6< 18A6> =PP5V_PWRON_LEFT_USB 7B5> 10C4> 31B3<> =RP6822P8 6C4< 55B7< AGP_CLK66M_GPU 11C7< 44C4< 44D6> COMP_RC 14C6< FB_A_DQ<7> 49A5<> FB_B_DQ<25> 50B5<> FW_TPBIAS2 69B2> 70B7<
5V_VOSNS 15C5<> =JTAG_VESTA_TMS 9A6> 18A6< =PP5V_PWRON_LTC1625_EXTVCC 10C4> 14D7<> =RP6823P1 6C4> 55A8< AGP_CLK66M_GPU_R 11C8< 43D3< 43D6> CPU0_BMODE0_L 34C7< 34D4< FB_A_DQ<8> 49A5<> FB_B_DQ<26> 50B5<> GAIN_SETTING2 28C4<>
1625_BG 14C5<> =JTAG_VESTA_TRST_L 9A6> 18A6< =PP5V_PWRON_LTC1778_GPU_EXTVCC 10C3> 45D6< =RP6823P2 6C4> 55A8< AGP_DEVSEL_L 6B6< 43C5< 43D6> 44C4<> CPU0_BMODE1_L 34A8< 34D4< FB_A_DQ<9> 49A5<> FB_B_DQ<27> 50B5<> GND_AUDIO_AGND 7A7> 74B6<>
1625_BST 14C5< =MAXBUS_CPU0_CLK 11D4> 33C1< 33D6> =PP5V_PWRON_LTC3707_EXTVCC 10C4> 15D5< =RP6823P3 6B4> 55A8< AGP_FRAME_L 6B6< 43D5< 43D6> 44C4<> CPU0_DFS2_L 34A8< 34D4<> FB_A_DQ<10> 49A5<> FB_B_DQ<28> 50B5<> GND_AUDIO_PGND 7A7> 74A6<>
1625_BST_ESR 14C5<> =PCI_AIRPORT_GNT_L 11D1> 60C3<> =PP5V_PWRON_MAX1715_VDD 10C4> 16D5<> =RP6823P4 6B4> 55A8< AGP_GNT_L 6B6< 43C6> 43D3< 44C4< CPU0_DFS4_L 34A8< 34D4<> FB_A_DQ<11> 49A5<> FB_B_DQ<29> 50B5<> GND_BATT_CONN 12A7<>
1625_COMP 13D2< 14C6< =PCI_AIRPORT_IDSEL 11C1> 60C7< =PP5V_PWRON_PMU_SUPPLY 10C4> 14B4<> =RP6823P5 6B4< 55A7< AGP_INT_L 22D5< 43C2< 44C4> CPU0_EXT_QUAL 34A6< 34D4< FB_A_DQ<12> 49A5<> FB_B_DQ<30> 50B5<> GND_GPU_TV1 57B8<>
1625_DIV 14C8< =PCI_AIRPORT_INT_L 11C1> 60B3<> =PP5V_PWRON_PWRSEQ 10C4> 26D7< =RP6823P6 6B4< 55A7< AGP_IRDY_L 6B6< 43C5< 43C6> 44C4<> CPU0_L1TSTCLK 34A6< 34D6< FB_A_DQ<13> 49A5<> FB_B_DQ<31> 50B5<> GND_GPU_TV2 57A8<>
1625_ENABLE 14D7<> =PCI_AIRPORT_REQ_L 11D1> 60C5<> =PP5V_PWRON_REG 10C6<> 15D8< =RP6823P7 6C4< 55A7< AGP_PAR 43C6> 43D5< 44C4> CPU0_L2TSTCLK 34A8< 34D6< FB_A_DQ<14> 49A5<> FB_B_DQ<32> 50B3<> GND_I2VCORE 20C4<>
1625_ENABLE_L 14D7<> =PCI_AIRPORT_RESET_L 11C1> 60C3<> =PP5V_PWRON_RIGHT_USB 7B5> 10C4> 31B7<> =RP6823P8 6C4< 55A7< AGP_PIPE_L 43B2< 43C5< 43C6> CPU0_LVRAM_L 34A8< 34D4<> FB_A_DQ<15> 49A5<> FB_B_DQ<33> 50B3<> GND_INVERTER 7B7> 56B2<>
C 1625_FCB
1625_INTVCC
1625_RUNSS
14C6<
14C5<>
14C6<
=PCI_CBUS_GNT_L 11C1> 61A7<
=PCI_CBUS_IDSEL 11C1> 61B8<
=PCI_CBUS_INT_L 11C1> 61A7<>
=PP5V_PWRON_RUNFET 10C4> 15B5<>
=PP5V_PWRON_SLEEPLED 10B4> 24B7<
=PP5V_PWRON_TPS2211 10C4> 61D4<
=RP7250P1
=RP7250P2
=RP7250P3
6B5>
6B5>
6B5>
59D2<
59D2<
59D2<
AGP_RBF_L
AGP_REQ_L
AGP_SBA<0>
6B6< 43C5< 43C6> 44B4>
6B6< 43C6> 43D5< 44C4<>
43C5< 44B6>
CPU0_MAX1717_AB_SEL 11A4
CPU0_PLL_CFG<0> 34D1< 34D6<
CPU0_PLL_CFG<1> 34D1< 34D6<
FB_A_DQ<16>
FB_A_DQ<17>
FB_A_DQ<18>
49B5<>
49B5<>
49A5<>
FB_B_DQ<34>
FB_B_DQ<35>
FB_B_DQ<36>
50B3<>
50B3<>
50B3<>
GND_NEC_AVSS_R
GND_PMU_AVSS
GND_TV1
73A3<
25A3<> 25D3< 28D3< 29B3< 31B4<
57B7<>
C
1625_SGND 14B7<> =PCI_CBUS_REQ_L 11C1> 61A7> =PP5V_PWRON_TRACKPAD 10B4> 15B8<> =RP7250P4 6B5> 59D2< AGP_SBA<7..0> 43D6> CPU0_PLL_CFG<2> 34D1< 34D6< FB_A_DQ<19> 49B5<> FB_B_DQ<37> 50B3<> GND_TV2 57A7<>
1625_TG 14C5<> =PCI_CBUS_RESET_L 11C1> 61A7< =PP5V_RUN_DVI_DDC 10C1> 57D4< =RP7251P1 6B5> 59C2< AGP_SBA<1> 43C5< 44B6> CPU0_PLL_CFG<3> 34D1< 34D6< FB_A_DQ<20> 49A5<> FB_B_DQ<38> 50A3<> GOV_RESET_L 11B4< 25C2<>
1625_VFB 14B5<> =PCI_CLK33M_AIRPORT 11D1> 60B5<> 60D6> =PP5V_RUN_FANPWM 10C1> 27D2< =RP7251P2 6A5> 59C2< AGP_SBA<2> 43C5< 44B6> CPU0_PLL_CFG<4> 34D1< 34D6< FB_A_DQ<21> 49B5<> FB_B_DQ<39> 50A3<> GPUPVDD_EN 26A5< 51D3<>
1625_VIN 14C6< =PCI_CLK33M_CBUS 11C1> 61A7< 61D1> =PP5V_RUN_HDD 7B7> 10C1> 64B5<> 64B8< =RP7251P3 6A5> 59C2< AGP_SBA<3> 43C5< 44B6> CPU0_PLL_CFG<5> 34D1< 34D4<> FB_A_DQ<22> 49B5<> FB_B_DQ<40> 50A3<> GPUVCORE_PGOOD 26A7<
1625_VSW 14C4<> =PCI_CLK33M_USB2 11C1> 62B5< 62D6> =PP5V_RUN_HDDFET 10C3< 15B4<> =RP7251P4 6A5> 59C2< AGP_SBA<4> 43C5< 44B6> CPU0_PULLDOWN 33C3<> FB_A_DQ<23> 49B5<> FB_B_DQ<41> 50A3<> GPUVCORE_SHDN_L 26B5<> 45C7<
1772_ACIN 13B5< =PCI_CLK33M_ZDBOUT_R<0> 11D4< 23B4> 23D6> =PP5V_RUN_KEYBRD_LED 10C1> 28B5< =RP8150P1 6C7> 63D2< AGP_SBA<5> 43C5< 44B6> CPU0_SMI_L 34A6< 34D4< FB_A_DQ<24> 49B5<> FB_B_DQ<42> 50A3<> GPUVDD15_EN 26A5< 46B5<>
1772_ACOK_L 13B5<> 13C4<> =PCI_CLK33M_ZDBOUT_R<1> 11C4< 23B4> 23D6> =PP5V_RUN_ODD 7B7> 10C1> 64C4< =RP8150P2 6C7> 63D2< AGP_SBA<6> 43C5< 44B6> CPU0_SRESET_L 34A6< 34D4< FB_A_DQ<25> 49B5<> FB_B_DQ<43> 50A3<> GPU_AGPTEST 44B6<>
1772_BST 13B4<> =PCI_CLK33M_ZDBOUT_R<2> 11C4< 23B4> 23D6> =PP5V_RUN_PWRSEQ 10C1> 26A7< 26C8< =RP8150P3 6C7> 63D2< AGP_SBA<7> 43C5< 44B6> CPU0_TEMP 25A6> FB_A_DQ<26> 49B5<> FB_B_DQ<44> 50A3<> GPU_AUXWIN_PU 53B5<> 53C4<
1772_BST_ESR 13C3< =PCI_CLK33M_ZDBOUT_R<3> 11B4< 23B4> 23D6> =PP5V_RUN_RUNFET 10C3< 15A4<> =RP8150P4 6C7> 63D2< AGP_SB_STB_N 43A2< 43C5< 43D6> 44B4<> CPU0_VID_AB_SEL 11A4 FB_A_DQ<27> 49B5<> FB_B_DQ<45> 50A3<> GPU_DVI_DDC_CLK 51B3<> 57D1<>
1772_CCI 13B5<> =PCI_CLK33M_ZDB_IN 11D1> 23B5< 23D6> =PP5V_SUPERCAP 14A4< 31A6< =RP8150P5 6C7< 63D1<> AGP_SB_STB_P 43B2< 43C5< 43D6> 44B4<> CPU1_TEMP 25A6> FB_A_DQ<28> 49B5<> FB_B_DQ<46> 50A3<> GPU_DVI_DDC_DATA 51B3<> 57C1<>
1772_CCS 13B5< =PCI_USB2_GNT_L 11C1> 62B5< =PP5V_TPAD 10C1> 30D6< =RP8150P6 6C7< 63D1<> AGP_ST<0> 43B3< 44B4< CPUVCORE_VSENSE_R 36C2<> FB_A_DQ<29> 49B5<> FB_B_DQ<47> 50A3<> GPU_DVI_HPD 51B3< 57C1<>
1772_CCV 13B5<> =PCI_USB2_IDSEL 11B1> 62B6< =PP5V_TPAD_FET 10C3< 15A6<> =RP8150P7 6C7< 63D1<> AGP_ST<3..0> 43D6> CPU_AVDD_EN 26B5< 37C6<> FB_A_DQ<30> 49B5<> FB_B_DQ<48> 50B3<> GPU_DVOD<0> 6D3> 54B6<
1772_CCV_RC 13B5< =PCI_USB2_INT_L 11B1> 62B7< =PP12V8_LTC1625_VREG 10D8< 14C3<> =RP8150P8 6C7< 63D1<> AGP_ST<1> 43B3< 44B4< CPU_BVSEL<0> 34C6< 34D6< FB_A_DQ<31> 49B5<> FB_B_DQ<49> 50B3<> GPU_DVOD<0..11> 54D6>
1772_CELLS 13B4< =PCI_USB2_REQ_L 11C1> 62B5> =PP12V8_PBUSB_HOLDUP_CAPS 10D6> 31D3< =RP8151P1 6C7> 63D2< AGP_ST<2> 43B3< 44B4< CPU_BVSEL<1> 34B6< 34D4<> FB_A_DQ<32> 49A3<> FB_B_DQ<50> 50B3<> GPU_DVOD<1> 6D3> 54B6<
1772_CLS 13A4< =PCI_USB2_RESET_L 11B1> 62A7< =PP12V8_PBUS_PMU_SUPPLY 10D6> 14A7<> =RP8151P2 6C7> 63D2< AGP_STOP_L 6B6< 43C5< 43C6> 44C4<> CPU_CHKSTP_OUT_L 33B1<> 34B8< FB_A_DQ<33> 49B3<> FB_B_DQ<51> 50B3<> GPU_DVOD<2> 6D3> 54B6<
1772_CSIN 13B4<> =PP1V2_ENETFW 10D4> 66D2< 69C1< 69D5< =PP14VR24V_ALL_PBUS_A 10D8< 13D5< =RP8151P3 6C7> 63D2< AGP_SUS_STAT_L_PU 44B4<> CPU_LSSD_MODE_L 34B8< 34D6< FB_A_DQ<34> 49B3<> FB_B_DQ<52> 50B3<> GPU_DVOD<3> 6D3> 54B6<
1772_CSIP 13B4<> =PP1V2_VESTA 10D4> 18B7< =PP24V_ADAPTER_CONN 10C8< 31D7<> =RP8151P4 6C7> 63C2< AGP_TRDY_L 6B6< 43C5< 43C6> 44C4<> CPU_MCP_L 34A8< 34D4< FB_A_DQ<35> 49B3<> FB_B_DQ<53> 50B3<> GPU_DVOD<4> 6C3> 54B6<
1772_CSSN 13C5< =PP1V2_VESTA_REG 10D6< 18C1< =PP24V_ADAPTER_PMU_SUPPLY 10C6> 14A7< =RP8151P5 6C7< 63C1<> AGP_VREF 11C8< CPU_PMON_IN_L 34A8< 34D4< FB_A_DQ<36> 49B3<> FB_B_DQ<54> 50B3<> GPU_DVOD<5> 6C3> 54B6<
1772_CSSP 13C5< =PP1V05R1V3_GPU_VCORE 10A6> 46D6< =PP24V_ADAPTER_RAW 10C6> 12D8<> =RP8151P6 6C7< 63D1<> AGP_WBF_L 43B2< 43C5< 43C6> 44B4> CPU_VCORE_SNUB 36B3< FB_A_DQ<37> 49A3<> FB_B_DQ<55> 50B3<> GPU_DVOD<6> 6C3> 54B6<
1772_DCIN 13B5< =PP1V5R1V8_MAXBUS 10A1> 21C8< 32D1< 33A5< 33B8< =PP24V_PBUSA_HOLDUP_CAPS 10D6> 31D5< =RP8151P7 6C7< 63D1<> AIRPORT_CLKRUN_L_PD 60C4<> CURRENT_THRESHOLD 13C4< FB_A_DQ<38> 49B3<> FB_B_DQ<56> 50A3<> GPU_DVOD<7> 6C3> 54B6<
1772_DHI 13B4<> 33C8< 34B5< 34B7< 34C4< 34C4< 34D4< =PPAVDD_CPU0 10C1> 35B6< =RP8151P8 6C7< 63D1<> ALS_0_OUT 7B5> 25A6> 31C4<> CY25811_S0 52A6< FB_A_DQ<39> 49B3<> FB_B_DQ<57> 50A3<> GPU_DVOD<8> 6D3> 54A6<
1772_DLO 13B4<> =PP1V5R1V8_PWRON_I2_MAXBUS 10A4> 32A5< =PPBUS_DVI_PWRSW 10C6> 57A4<> =RP8152P1 6C7> 63C2< ALS_1_OUT 25A6> 28D3< CY25811_S1 52A6< FB_A_DQ<40> 49A3<> FB_B_DQ<58> 50A3<> GPU_DVOD<9> 6D3> 54A6<
1772_DLOV 13B4<> =PP1V5R1V8_RUN_I2_MAXBUS 10A1> 32B5< =PPBUS_FWPWRSW 10D6> 18D8< =RP8152P2 6C7> 63C2< ALS_GAIN_BOOST 7B5> 25A6> 28C5<> 31B3<> DVI_DDC_CLK 57D2<> FB_A_DQ<41> 49A3<> FB_B_DQ<59> 50A3<> GPU_DVOD<10> 6D3> 54A6<
1772_GND 13A5<> =PP1V5R3V3_DVO_VREF 47C1> 54A2< =PPBUS_FW_FET 10D6< 18D5<> =RP8152P3 6C7> 63C2< ANALOG_AC_DET 12C3< DVI_DDC_CLK_UF 57B4<> 57C3<> FB_A_DQ<42> 49A3<> FB_B_DQ<60> 50A3<> GPU_DVOD<11> 6D3> 54A6<
1772_ICHG 13B5<> =PP1V5_AGP 10A6> 43A5< 43C1< 44B2< 44B7< =PPBUS_INVERTER 10D6> 56C3< =RP8152P4 6C7> 63C2< ATI_AGP_FBSKEW<0> 51B5<> DVI_DDC_DATA 57C2<> FB_A_DQ<43> 49A3<> FB_B_DQ<61> 50A3<> GPU_DVOD<12> 6C3> 55B6<
1772_ICTL 13B5<> 44C6< 47C2< =PPBU_RUN_FW 10C1> 18D6<> =RP8152P5 6C7< 63C1<> ATI_AGP_FBSKEW<1> 51B5<> DVI_DDC_DATA_UF 57C3<> FB_A_DQ<44> 49A3<> FB_B_DQ<62> 50A3<> GPU_DVOD<12..19> 55D6>
1772_IINP 13B5< =PP1V5_GPU 10A1> 10A8< =PPFW_P3V3VESTA 10D4> 18D6<> =RP8152P6 6C7< 63C1<> ATI_BUS_CFG<0> 51B5<> DVI_HPD 57C2<> FB_A_DQ<45> 49A3<> FB_B_DQ<63> 50A3<> GPU_DVOD<13> 6C3> 55B6<
1772_LDO 13C4<> =PP1V5_GPU_DVO 10A6> 47C2< =PPFW_PHY_CPS 10D4> 69C5< =RP8152P7 6C7< 63C1<> ATI_BUS_CFG<1> 51B5<> DVI_HPD_DIV 57A4< FB_A_DQ<46> 49A3<> FB_B_DQM<0> 50A7< GPU_DVOD<14> 6C3> 55B6<
1772_LX 13B4<> =PP1V5_GPU_PWRSEQ 10A6> 52C4<> =PPFW_PORT1 10D4> 70D3< =RP8152P8 6C7< 63C1<> ATI_BUS_CFG<2> 51B5<> DVI_HPD_UF 57A5< 57C3<> FB_A_DQ<47> 49A3<> FB_B_DQM<7..0> 48A1> 50C1> GPU_DVOD<15> 6C3> 55B6<
1772_REF 13B5<> =PP1V5_GPU_VDD15 10A6> 46B5<> =PPFW_PORT2 10D4> 70B4< =RP8153P1 6C7> 63C2< ATI_CLK27M 51C3< 52C6< 52D6> DVI_TURN_ON 57B4<> FB_A_DQ<48> 49B3<> FB_B_DQM<1> 50A7< GPU_DVOD<16> 6C3> 55B6<
1772_VCTL 13B5< =PP1V5_I2_AGP 10A4> 43C7< =PPI2C_GPU 8B5< 10B1> =RP8153P2 6C7> 63C2< ATI_CLK27M_R 52C6< 52D6> DVI_TURN_ON_BASE 57B2<> FB_A_DQ<49> 49B3<> FB_B_DQM<2> 50A7< GPU_DVOD<17> 6C3> 55B6<
1778_BG 45C5<> =PP1V5_PWRON_I2PLL_LDO 10D3< 20B3<> =PPI2C_I2_NB 8C2< 10B5< =RP8153P3 6C7> 63C2< ATI_CLK27M_SS 51B5<> 52A5< 52D6> DVI_TURN_ON_ILIM 57B3< FB_A_DQ<50> 49B3<> FB_B_DQM<3> 50A7< GPU_DVOD<18> 6C3> 55B6<
1778_BST 45C5<> =PP1V5_PWRON_I2_PLL 10D1> 19C5< =PPI2C_I2_SB 8D2< 10B3< =RP8153P4 6C7> 63C2< ATI_CLK27M_SSIN 52A6< 52C5< 52D6> ENETCONN_0_N 66B1<> 66D6> 67C5<> FB_A_DQ<51> 49B3<> FB_B_DQM<4> 50A4< GPU_DVOD<19> 6C3> 55B6<
1778_BST_RC 45C4<> =PP1V5_PWRON_I2_USBPLL 10D1> 72C7< =PPI2C_SYS0 8B5< 10C6> =RP8153P5 6C7< 63C1<> ATI_CLK27M_SS_R 52A6<> 52D6> ENETCONN_0_P 66B1<> 66D6> 67C5<> FB_A_DQ<52> 49B3<> FB_B_DQM<5> 50A4< GPU_DVOD<20> 6C3> 55B6< 55D6>
1778_FCB 45C6< =PP1V5_PWRON_REG 10A6<> 16B8<> =PPI2C_SYS1 8C5< 10B5< =RP8153P6 6C7< 63C1<> ATI_DBI_HI_PU 44B6<> ENETCONN_1_N 66B1<> 66D6> 67B5<> FB_A_DQ<53> 49B3<> FB_B_DQM<6> 50A4< GPU_DVOD<21> 6C3> 55B6<
1778_GND 45B6<> =PP1V5_PWRON_RUNFET 10A4> 16A8<> =PPJTAG_CPU 9D8< 10A1> =RP8153P7 6C7< 63C1<> ATI_DBI_LO_PU 44B6<> ENETCONN_1_P 66B1<> 66D6> 67C5<> FB_A_DQ<54> 49B3<> FB_B_DQM<7> 50A4< GPU_DVOD<21..23> 55D6>
1778_ION 45C5< =PP1V5_RUN_RUNFET 10A3< 16A6<> =PPVBATT_BATT 10C6> 13D2< =RP8153P8 6C7< 63C1<> ATI_MEMTYPE 51A7< 51B5<> ENETCONN_2_N 66B1<> 66D6> 67B5<> FB_A_DQ<55> 49B3<> FB_B_DQM_R<0> 42B6> GPU_DVOD<22> 6B3> 55B6<
1778_ITH 45C6<> =PP1V8R2V5_GPU_FB_VIO 10A6> 47C8< 48A8< =PPVBATT_BATTERY_PMU_SUPPLY 10C6> 14A7< =RP8154P1 6C7> 63C2< ATI_OSC_OE 52C7< ENETCONN_2_P 66B1<> 66D6> 67B5<> FB_A_DQ<56> 49A3<> FB_B_DQM_R<7..0> 48A2< 48C5> GPU_DVOD<23> 6B3> 55B6<
1778_ITH_RC 45C7< =PP1V8_FB_VDD 10A6> 49D5< 49D8< 50D5< 50D8< =PPVBATT_BATT_PBUSA 10D8< 13D2<> =RP8154P2 6C7> 63B2< ATI_PVDD_BYP 51D2<> ENETCONN_3_N 66B1<> 66D6> 67B5<> FB_A_DQ<57> 49A3<> FB_B_DQM_R<1> 42B6> GPU_DVOD_R<0> 6D4< 53C7<>
1778_TG 45C5<> =PP1V8_FB_VDDQ 10A6> 49D5< 49D8< 50D5< 50D8< =PPVBATT_BATT_PBUSB 10D8< 13D1<> =RP8154P3 6B7> 63B2< ATI_R2SET 53B6<> ENETCONN_3_P 66B1<> 66D6> 67B5<> FB_A_DQ<58> 49A3<> FB_B_DQM_R<2> 42B6> GPU_DVOD_R<23..0> 53D1>
1778_VFB 45C5< =PP1V8_GPU 10A1> 10A8< =PPVBATT_BATT_VSNS 10C8< 12B6< =RP8154P4 6B7> 63B2< ATI_RSET 53B6<> ENETRJ45_0_N 67C4<> 67D6> FB_A_DQ<59> 49A3<> FB_B_DQM_R<3> 42B6> GPU_DVOD_R<1> 6D4< 53C7<>
B 1778_VRNG
3707_FCB
3707_FSET
45C6<
15C5<
15C5<
=PP1V8_GPU_AVDD 10A8< 53C2<
=PP1V8_GPU_DVO 10A6> 47C2<
=PP1V8_GPU_LVDS_PLL 47C2< 51D1>
=PPVBATT_ISNS_N 10C8< 12B4<>
=PPVCORE_CPU0 10C4> 35C4< 35C8< 35D4<
=PPVCORE_CPU_ADT7467 10C4> 27C4<
=RP8154P5
=RP8154P6
=RP8154P7
6B7<
6B7<
6C7<
63B1>
63B1>
63B1>
ATI_X1CLK_SKEW<0> 51B5<>
ATI_X1CLK_SKEW<1> 51B5<>
AUDIO_CODEC_RESET_L 7A7> 22C5< 74B3<>
ENETRJ45_0_P
ENETRJ45_1_N
ENETRJ45_1_P
67C4<> 67D6>
67B4<> 67D6>
67C4<> 67D6>
FB_A_DQ<60>
FB_A_DQ<61>
FB_A_DQ<62>
49A3<>
49A3<>
49A3<>
FB_B_DQM_R<4>
FB_B_DQM_R<5>
FB_B_DQM_R<6>
42B6>
42B6>
42B6>
GPU_DVOD_R<2>
GPU_DVOD_R<3>
GPU_DVOD_R<4>
6D4< 53C7<>
6D4< 53C7<>
6C4< 53C7<>
B
3707_INTVCC 15D5<> =PP1V8_GPU_MEMVMODE 10A6> 48A6< =PPVCORE_CPU_REG 10C6< 36C1< =RP8154P8 6C7< 63C1> AUDIO_EXT_MCLK_SEL 7A7> 22C5< 74B4<> ENETRJ45_2_N 67B4<> 67D6> FB_A_DQ<63> 49A3<> FB_B_DQM_R<7> 42B6> GPU_DVOD_R<5> 6C4< 53C7<>
3707_SGND 15C7<> =PP1V8_GPU_PANEL_IO 10A6> 47B2< =PPVCORE_GPU_REG 10A8<> 45C3<> =RP9100P1 6A7> 71C6< AUDIO_GPIO_11 7A7> 22C5< 74B5< ENETRJ45_2_P 67B4<> 67D6> FB_A_DQM<0> 49A7< FB_B_DQS<0> 50B7<> GPU_DVOD_R<6> 6C4< 53C7<>
3707_STBYMD 15C5<> =PP1V8_GPU_PWRSEQ 10A6> 52D4<> =PPVCORE_PWRON_I2 10A6> 19D6< =RP9100P2 6A7> 71C6< AUDIO_I2S_DTIB_SEL 7A7> 22C5< 74B4<> ENETRJ45_3_N 67B4<> 67D6> FB_A_DQM<7..0> 48A3> 49C1> FB_B_DQS<7..0> 48A1> 50C1> GPU_DVOD_R<7> 6C4< 53C7<>
=1V8_1V5PWRON_EN_L 16C8<> 26D3> =PP1V8_GPU_TPVDD 10A8< 53D4< =PPVCORE_PWRON_I2_REG 10A8<> 20C2< =RP9100P3 6A7> 71C6< AUDIO_LI_DET_L 7A7> 22D5< 74B4<> ENETRJ45_3_P 67B4<> 67D6> FB_A_DQM<1> 49A7< FB_B_DQS<1> 50B7<> GPU_DVOD_R<8> 6D4< 53C7<>
=1V8_1V5PWRON_PGOOD 16C6> 26B8< =PP1V8_PWRON_DDR2 10A4> 40B8< 40C3< 40D4<> 40D6<> =PPVIN_ALL_BATT_CHGR 10D6> 13C2<> =RP9100P4 6A7> 71C6< AUDIO_LI_OPTICAL_PLUG_L 7A7> 22D5< 74B4<> ENET_CLK25M_TX 11A7< 65C5< 65D6> FB_A_DQM<2> 49A7< FB_B_DQS<2> 50A7<> GPU_DVOD_R<9> 6D4< 53C7<>
=2V5PWRON_EN_L 17C7<> 26D3> 41C3< 41D4<> 41D6<> =PPVIN_ALL_LTC1625 10D6> 14D3<> =RP9100P5 6A7< 71C4< AUDIO_LO_DET_L 7A7> 22C5< 74B4<> ENET_CLK25M_TX_R 66C4<> 66D6> FB_A_DQM<3> 49A7< FB_B_DQS<3> 50B7<> GPU_DVOD_R<10> 6D4< 53C7<>
=2V5PWRON_PGOOD 17C4> 26B8< =PP1V8_PWRON_I2_RAM 10A4> 38D3< =PPVIN_ALL_LTC3707 10D6> 15D5<> =RP9100P6 6A7< 71C4< AUDIO_LO_MUTE 22C7<> ENET_CLK125M_GBE_REF 11A7< 65B5< 65D6> FB_A_DQM<4> 49A4< FB_B_DQS<4> 50B4<> GPU_DVOD_R<11> 6D4< 53C7<>
=5V3V3PWRON_EN_L 15B6< 26D5> =PP1V8_PWRON_REG 10A6<> 16C1<> =PPVIN_ALL_MAX1715 10D6> 16C3<> 16C7<> 16D5< =RP9100P7 6A7< 71C4< AUDIO_LO_MUTE_L 7A7> 22C6<> 74B4<> ENET_CLK125M_GBE_REF_R 66C4<> 66D6> FB_A_DQM<5> 49A4< FB_B_DQS<5> 50A4<> GPU_DVOD_R<12> 6C4< 53C7<>
=5V3VPWRON_PGOOD 15C4<> 26B8< =PP1V8_PWRON_RUNFET 10A4> 16B5<> =PPVIN_BATT_CHRG_VSNS 10C6> 13A4< =RP9100P8 6A7< 71C4< AUDIO_LO_OPTICAL_PLUG_L 7A7> 22C5< 74B4<> ENET_CLK125M_GTX 66C6< FB_A_DQM<6> 49A4< FB_B_DQS<6> 50B4<> GPU_DVOD_R<13> 6C4< 53C7<>
=5VPWRONTPAD_EN_L 15A8<> 26D3> =PP1V8_RAM_I2_VREF 10A1> 38A6< =PPVIN_CPU0_AVDD 10B3< 37C7< =RP9101P1 6A7> 71C6< AUDIO_SPDIFRX_RESET_L 7A7> 22C5< 74B3<> ENET_CLK125M_GTX_R 65B3< 65D6> 66C7< FB_A_DQM<7> 49A4< FB_B_DQS<7> 50B4<> GPU_DVOD_R<14> 6C4< 53C7<>
=ADT7467_THERM_L 11B3> 27C2< =PP1V8_RUN_RUNFET 10A3< 16A3<> =PPVIN_CPUVCORE_MAX1717 10D6> 36D4<> =RP9101P2 6A7> 71C6< AUDIO_SPDIF_RXERR_INT 74B4<> ENET_CLK125M_RX 11A7< 65C5< 65D6> FB_A_DQM_R<0> 42C6> FB_B_DQS_R<0> 42B6> GPU_DVOD_R<15> 6C4< 53B7<>
=AGP_GPU_RESET_L 11C7> 44D4< =PP1V8_RUN_TBEN_SYNC 10A1> 21B5< =PPVIN_GPU_LVDDR_LDO 10B6> 52B4< =RP9101P3 6A7> 71C6< AUDIO_SPKR_MUTE 22B2<> ENET_CLK125M_RX_R 66C4<> 66D6> FB_A_DQM_R<7..0> 48A4< 48C6> FB_B_DQS_R<7..0> 48A2< 48C5> GPU_DVOD_R<16> 6C4< 53B7<>
=AGP_VREF 11C7> 44B2< =PP2V5R3V3_PWRON_I2_ENET 10B5< 65B6< 65C3< 65C7< =PPVIN_LTC1778_GPU 10D6> 45D5<> =RP9101P4 6A7> 71C6< AUDIO_SPKR_MUTE_L 7A7> 22B1<> 74B4<> ENET_COL 9B3> 11A7< 65B5< 65D6> FB_A_DQM_R<1> 42C6> FB_B_DQS_R<1> 42B6> GPU_DVOD_R<17> 6C4< 53B7<>
=CLK33M_TBEN_SYNC 11D1> 21A5< 21D6> =PP2V5_ENET 10A4> 67C6<> =PPVIN_PWRON_I2PLLVDD 10A4> 20B6<> =RP9101P5 6A7< 71C4< BATT0_DET_L 12A7<> ENET_CRS 9B3> 11A7< 65B5< 65D6> FB_A_DQM_R<2> 42C6> FB_B_DQS_R<2> 42B6> GPU_DVOD_R<18> 6C4< 53B7<>
=CPU0_MAX1717_AB_SEL 11A3> 36A7< 36C7< =PP2V5_ENETFW 10D4> 66D2< 69D1< 69D5< =PPVIO_BU_BATT 7B5> 10D8< 31B6<> =RP9101P6 6A7< 71C4< BATTV_HIGH 13B7<> ENET_CTAP0 67C4<> FB_A_DQM_R<3> 42C6> FB_B_DQS_R<3> 42B6> GPU_DVOD_R<19> 6C4< 53B7<>
=CPU0_VID_AB_SEL 11A3> 36D3<> =PP2V5_GPU 10B1> 10B8< =PPVIO_PCI_USB2 10B3< 62D5< =RP9101P7 6A7< 71C4< BATTV_LOW 13B8<> ENET_CTAP1 67C4<> FB_A_DQM_R<4> 42C6> FB_B_DQS_R<4> 42B6> GPU_DVOD_R<20> 6C4< 53B7<>
=CPU_HRESET_L 11B3> 34A8< 34C6< 34D4< =PP2V5_GPU_A2VDD 10A6> 53B2< =PPVOUT_BATT_CHRG 13B1> =RP9101P8 6A7< 71C4< BATT_14PBUS_EN 13C1<> ENET_CTAP2 67B4<> FB_A_DQM_R<5> 42C6> FB_B_DQS_R<5> 42B6> GPU_DVOD_R<21> 6C4< 53B7<>
=ENET_COL_R 11A6> 66B3> =PP2V5_GPU_LVDS_IO 10B6> 47B1< =PPVOUT_BU_BATT 7B5> 10D8< 31A6< =RP9210P5 6B4< 72A4< BATT_14V_GATE 13C1<> ENET_CTAP3 67B4<> FB_A_DQM_R<6> 42C6> FB_B_DQS_R<6> 42B6> GPU_DVOD_R<22> 6B4< 53B7<>
=ENET_CRS_R 11A6> 66B3> =PP2V5_GPU_PVDD 10B6> 51D3< =PPVOUT_CPU0_AVDD 10C3< 37C3< =RP9210P6 6B4< 72A4< BATT_24PBUS_EN 13C2<> ENET_CTAP_COMMON 67A3< FB_A_DQM_R<7> 42C6> FB_B_DQS_R<7> 42B6> GPU_DVOD_R<23> 6B4< 53B7<>
=ENET_RXD_R<0> 66C3> =PP2V5_GPU_PWRSEQ 10B6> 52D4<> =PPVREF_PMU 10B6> 25B5< =RP9210P7 6B4< 72A4< BATT_24V_GATE 13C1<> ENET_CTAP_EN_L 67C6<> FB_A_DQS<0> 49A7<> FB_B_DQ_R<7..0> 42B6> GPU_DVOVMODE 53C7<
=ENET_RXD_R<7..0> 11A6> =PP2V5_PWRON_REG 10A6<> 17C2< =RAM_VREF_A 40A6> 40D2< 40D6<> =RP9210P8 6B4< 72A4< BATT_CLK 12A7<> ENET_ENERGYDET 65B5< FB_A_DQS<7..0> 48A3> 49C1> FB_B_DQ_R<63..0> 48A2< 48D6< GPU_DVO_CLKP 6C3> 54A6< 54C6> 55A6< 55C6>
=ENET_RXD_R<1> 66C3> =PP2V5_PWRON_RUNFET 10A4> 17B5<> =RAM_VREF_B 40A6> 41D2< 41D6<> =RP9211P5 6B4< 72A4< BATT_DATA 12A7<> ENET_MDC 9B3> 11A7< 65C3< 65D6> FB_A_DQS<1> 49B7<> FB_B_DQ_R<15..8> 42A6> GPU_DVO_CLKP_R 6C4< 53C7<> 53D1>
=ENET_RXD_R<2> 66C3> =PP2V5_RUN_PCI1510 10B1> 61C8< =ROM_PWD_L 11A4> 58B6< =RP9211P6 6B4< 72A4< BATT_DIV 13A5< ENET_MDI0 66A3< FB_A_DQS<2> 49B7<> FB_B_DQ_R<23..16> 42A6> GPU_DVO_DE 6C3> 54A6< 54C6> 55B6< 55C6>
=ENET_RXD_R<3> 66C3> =PP2V5_RUN_RUNFET 10B3< 17B4<> =RP1150P1 6D7> 11D8< =RP9211P7 6B4< 72A4< BATT_ISNS 12A3< 25A3> ENET_MDI1 66A2< FB_A_DQS<3> 49B7<> FB_B_DQ_R<31..24> 42A6> GPU_DVO_DE_R 6C4< 53C7<> 53D1>
=ENET_RXD_R<4> 66C3> =PP2V5_VESTA 10D4> 18B2< =RP1150P2 6D7> 11D8< =RP9211P8 6B4< 72A4< BATT_ISNS_R 12A4<> ENET_MDI2 66A2< FB_A_DQS<4> 49B4<> FB_B_DQ_R<39..32> 42A6> GPU_DVO_HSYNC 6C3> 54A6< 54D6> 55B6<
=ENET_RXD_R<5> 66C3> =PP2V5_VESTA_LDO 10D6< 18D1<> =RP1150P3 6D7> 11D8< =RP9212P5 6B4< 72A4< BATT_LOW 13A6<> ENET_MDI3 66A2< FB_A_DQS<5> 49A4<> FB_B_DQ_R<47..40> 42A6> GPU_DVO_HSYNC_R 6C4< 53C7<> 53D1>
=ENET_RXD_R<6> 66C3> =PP2V7R5V5_PWRON_I2VCORE 10B4> 20D7< =RP1150P4 6D7> 11D8< =RP9212P6 6B4< 72A4< BATT_LOW_L 13B6<> ENET_MDIO 9B3> 11A7< 65C1<> 65D6> FB_A_DQS<6> 49B4<> FB_B_DQ_R<55..48> 42A6> GPU_DVO_VSYNC 6C3> 54A6< 54C6> 55A6< 55D6>
=ENET_RXD_R<7> 66C3> =PP2V8_GPU_LVDDR_LDO 10B8< 52B1<> =RP1150P5 6D7< 11D7< =RP9212P7 6B4< 72A4< BKFD_PROT_EN_L 13C8<> ENET_RESET_L 11A8< 65B3< FB_A_DQS<7> 49B4<> FB_B_DQ_R<63..56> 42A6> GPU_DVO_VSYNC_R 6C4< 53C7<> 53D1>
=ENET_RX_DV_R 11A6> 66C3> =PP2V8_GPU_LVDS_IO 10B6> 47A1< =RP1150P6 6D7< 11D7< =RP9212P8 6B4< 72A4< BKFD_PROT_GATE 13D8<> ENET_RXD<0> 65B5< FB_A_DQS_R<0> 42D6> FB_B_RAS_L 48B1< 50A4< 50A7< 50D1> GPU_HSYNC_BUF 57B1<>
=ENET_RX_ER_R 11A6> 66B3> =PP3V3_ADT7467 10B4> 27D5< =RP1150P7 6D7< 11D7< =RP9300P5 6B4< 73B1< BRIGHT_PWM 7B7> 56B2<> ENET_RXD<3..0> 65D6> FB_A_DQS_R<7..0> 48A4< 48C6> FB_B_RAS_L_R 42B6> 48B2< 48B5> GPU_MEMTEST 48A5<>
=ENET_TXD<0> 66C6< =PP3V3_AGP 10B6> 43D1< 44B4< 44C7< =RP1150P8 6D7< 11D7< =RP9300P6 6B4< 73B1< BRIGHT_PWM_F 56B3<> ENET_RXD<7..0> 9B3> 11A7< FB_A_DQS_R<1> 42D6> FB_B_WE_L 48B1< 50A4< 50A7< 50C1> GPU_MEMVMODE0 48A6<
=ENET_TXD<7..0> 11A6> =PP3V3_ALL_A29_DET 10C6> 12D3<> =RP1151P1 6D7> 11D8< =RP9300P7 6B4< 73B1< CBUS_ADDR<0> 61B1< 61B4> ENET_RXD<1> 65B5< FB_A_DQS_R<2> 42D6> FB_B_WE_L_R 42B6> 48B2< 48B5> GPU_MEMVMODE1 48A6<
=ENET_TXD<1> 66C6< =PP3V3_ALL_AC_DETECT 10C6> 12C7<> =RP1151P2 6D7> 11C8< =RP9300P8 6B4< 73B1< CBUS_ADDR<1> 61B1< 61B4> ENET_RXD<2> 65B5< FB_A_DQS_R<3> 42D6> FB_C0_VREF 49C6< GPU_MVREFD 48A7<
=ENET_TXD<2> 66C6< =PP3V3_ALL_BATT0_DET 10B6> 12B7< =RP1151P3 6D7> 11C8< =RP9301P5 6A4< 73B1< CBUS_ADDR<2> 61B1< 61B4> ENET_RXD<3> 65B5< FB_A_DQS_R<4> 42D6> FB_C1_VREF 49C4< GPU_MVREFS 48A8<
=ENET_TXD<3> 66C6< =PP3V3_ALL_BATT_CHGR 10C6> 13A6<> 13A8< 13C8< =RP1151P4 6D7> 11C8< =RP9301P6 6A4< 73B1< CBUS_ADDR<3> 61B1< 61B4> ENET_RXD<4> 65B5< FB_A_DQS_R<5> 42D6> FB_D0_VREF 50C6< GPU_RSTB_MSK 51B4<
=ENET_TXD<4> 66C6< =PP3V3_ALL_DEBUG 10B6> 24C3<> =RP1151P5 6D7< 11C7< =RP9301P7 6A4< 73B1< CBUS_ADDR<4> 61B1< 61B4> ENET_RXD<7..4> 65D6> FB_A_DQS_R<6> 42D6> FB_D1_VREF 50C4< GPU_SSIN_PD 51B4<
=ENET_TXD<5> 66C6< =PP3V3_ALL_HALL_EFFECT 10C6> 30D6< =RP1151P6 6D7< 11C7< =RP9301P8 6A4< 73B1< CBUS_ADDR<5> 61B1< 61B4> ENET_RXD<5> 65B5< FB_A_DQS_R<7> 42D6> FP_PWR_EN_L 56C4<> GPU_TESTEN 51B4<
=ENET_TXD<6> 66C6< =PP3V3_ALL_LTC1625_SW 10C6> 14C7<> =RP1151P7 6D7< 11C7< =SI_TMDS_RESET_L 11C7> 54B6< 55B6< CBUS_ADDR<6> 61B1< 61B4> ENET_RXD<6> 65B5< FB_A_DQ_R<7..0> 42C6> FWPWR_ACIN 18B7<> GPU_TV_C 53B4< 53C1> 57A8<
=ENET_TXD<7> 66C6< =PP3V3_ALL_PBUS_ILIM 10C6> 13C3< 13D4< =RP1151P8 6D7< 11D7< =SLEEP_LED_CONN 11A3> 74B3<> CBUS_ADDR<7> 61B1< 61B4> ENET_RXD<7> 65B5< FB_A_DQ_R<63..0> 48A4< 48D8< FWPWR_EN 18C7<> GPU_TV_COMP 53B4<> 53C1> 57A8<
=ENET_TX_EN 11A6> 66C6< =PP3V3_ALL_PMU 10C6> 24A7< 24D7< 25B6< 25C8< =RP3510P1 6B7> 32D2< =SLEEP_LED_IOUT 11A5< 24B6< CBUS_ADDR<8> 61B1< 61B4> ENET_RX_DV 9B3> 11A7< 65B5< 65D6> FB_A_DQ_R<15..8> 42C6> FWPWR_EN_L 18C7< GPU_TV_Y 53B4<> 53C1> 57A8<
A =ENET_TX_ER
=FTP_GND
=FTP_SLEEP_LED
11A6> 66B6<
7C5> 7C5> 7C7> 10D2>
7C5> 74C2>
25D5<
=PP3V3_ALL_PWRSEQ 10B6> 26B7<> 26D5<
=PP3V3_ALL_VREG 10C8< 14A2<
=RP3510P2
=RP3510P3
=RP3510P4
6B7>
6B7>
6B7>
32D2<
32D2<
32D2<
=SPI_I2_CLK
=SPI_I2_MISO
=SPI_I2_MOSI
22A5<
22B2>
22B5<
CBUS_ADDR<9>
CBUS_ADDR<10>
CBUS_ADDR<11>
61B1< 61B4>
61B4> 61C1<
61B1< 61B4>
ENET_RX_ER
ENET_TXD<7..0>
ENET_TXD_R<0>
9B3> 11A7< 65B5< 65D6>
9B3> 11A7
65B3<
FB_A_DQ_R<23..16> 42C6>
FB_A_DQ_R<31..24> 42C6>
FB_A_DQ_R<39..32> 42C6>
FWPWR_EN_L_DIV
FWPWR_PWRON
FWPWR_RUN
18C7<>
26D4<
18C7<>
GPU_VCORE_HI
GPU_VCORE_HI_L
45B4<>
45A5< 51B8<>
GPU_VCORE_HI_L_RC 45A5<>
A
=FWPWR_PWRON 18C8<> 26D3> =PP3V3_AUDIO_MUTESEQ 10B5< 22B2< 22D7< =RP3511P1 6B7> 32D2< =SPI_I2_REQ 11A5< 22A7< 22C5< CBUS_ADDR<12> 61B1< 61B4> ENET_TXD_R<3..0> 65D6> FB_A_DQ_R<47..40> 42C6> FW_CLK98M_LCLK 69C5< 69D6> GPU_VCORE_SW 45C4<>
=GND_CHASSIS_DVI1 2D4> 57D3<> =PP3V3_BATT_IMON 10B6> 12A5< =RP3511P2 6B7> 32C2< =SYSCLK_TBEN_SYNC 11D4> 21A5< 21D6> CBUS_ADDR<13> 61B1< 61B4> ENET_TXD_R<7..0> 11A8< FB_A_DQ_R<55..48> 42C6> FW_CLK98M_LCLK_R 68B3< 68D6> 69C6< GPU_VGA_B 53C1> 53C4<> 57C8<
=GND_CHASSIS_DVI2 2D4> 57C3<> =PP3V3_DDC_DVI 10B1> 57B4<> 57D2<> =RP3511P3 6B7> 32C2< =TPS2211_SHDN_L 10B3< 61D5< CBUS_ADDR<14> 61B1< 61B4> ENET_TXD_R<1> 65B3< FB_A_DQ_R<63..56> 42C6> FW_CLK98M_PCLK 68C5< 68D6> 69C1> GPU_VGA_G 53C1> 53C4<> 57C8<
=GND_CHASSIS_DVI3 2D4> 57C2< =PP3V3_DDC_LCD 7B7> 10B1> 56C7<> =RP3511P4 6B7> 32C2< =VCORE_PGOOD 26B5< 36B4> CBUS_ADDR<15> 61B1< 61B4> ENET_TXD_R<2> 65B3< FB_A_RAS_L 48B3< 49A4< 49A7< 49D1> FW_CLK98M_PCLK_R 69C3<> 69D6> GPU_VGA_HSYNC 53B5<> 57B2<
=GND_CHASSIS_DVI4 2D4> 57B2< =PP3V3_ENET 10A5< 66B7<> =RP3512P1 6B7> 32C2< =VESTA_CLK25M_TX 11A6> 66C2> CBUS_ADDR<16> 61B1< 61B4< ENET_TXD_R<3> 65B3< FB_A_RAS_L_R 42D6> 48B4< 48B6> FW_CTL<0> 69B6<> 71B4< GPU_VGA_R 53C1> 53C4<> 57B8<
=GND_CHASSIS_DVI_HOLE 2D2<> 2D4> =PP3V3_ENETFW 10D4> 69D1< =RP3512P2 6B7> 32C2< =VESTA_CLK125M_GBE_REF 11A6> 66C2> CBUS_ADDR<17> 61B2< 61B4> ENET_TXD_R<4> 65B3< FB_A_WE_L 48B3< 49A4< 49A7< 49C1> FW_CTL<1..0> 9B3> GPU_VGA_VSYNC 53B5<> 57C2<
=GND_CHASSIS_ENET 2D4> 67A2<> =PP3V3_FW 10D4> 69A8< 69B2< 70A8< =RP3512P3 6B7> 32C2< =VESTA_CLK125M_RX 11A6> 66C2> CBUS_ADDR<18> 61B2< 61B4> ENET_TXD_R<7..4> 65D6> FB_A_WE_L_R 42D6> 48B4< 48B6> FW_CTL<1> 69B6<> 71B4< GPU_VREFG 51A5<
=GND_CHASSIS_FW_EMI 2D4> 70A1< =PP3V3_GPU 10B1> 10B8< =RP3512P4 6B7> 32C2< =VESTA_ENERGYDET 11A6> 66B3> CBUS_ADDR<19> 61B2< 61B4> ENET_TXD_R<5> 65B3< FB_B_ADDR<0> 50B4< 50B7< FW_CTL_R<0> 68B3< 71B6< GPU_VSYNC_BUF 57C1<>
=GND_CHASSIS_FW_HOLE 2D1<> 2D4> =PP3V3_GPU_CLOCKS 10B1> 52B8< 52C8< =RP3513P2 6B7> 32B2< =VESTA_MDC 11A6> 66B6< CBUS_ADDR<20> 61B2< 61B4> ENET_TXD_R<6> 65B3< FB_B_ADDR<11..0> 48D1> 50D1> FW_CTL_R<1..0> 9B3> 68D6> HIGH_GPU_VCORE_DIV 45B3<
=GND_CHASSIS_FW_PORT1 2D4> 70C1<> =PP3V3_GPU_GPIOS 10B6> 51A7< 51B8< 53C4< =RP3513P3 6B7> 32B2< =VESTA_MDIO 11A6> 66B6<> CBUS_ADDR<21> 61B2< 61B4> ENET_TXD_R<7> 65B3< FB_B_ADDR<1> 50B4< 50B7< FW_CTL_R<1> 68B3< 71B6< HIGH_GPU_VCORE_L 45B3<>
=GND_CHASSIS_FW_PORT2 2D4> 70A2<> =PP3V3_GPU_PWRSEQ 10B6> 52D2<> =RP3513P4 6B7> 32B2< A29_CLS_ADJ 13A5<> CBUS_ADDR<22> 61A4> 61B2< ENET_TX_EN 9B3> 11A7 FB_B_ADDR<2> 50B4< 50B7< FW_D<0> 6A6> 69C5<> HPD_4V_REF 57A4<
=GND_CHASSIS_INVERTER1 2C4> 56B3< =PP3V3_GPU_VDDR3 10B6> 47D3< =RP3514P1 6A7> 32B2< A29_CURRENT_ADJ 13C4<> CBUS_ADDR<23> 61A4> 61B2< ENET_TX_EN_R 11A8< 65B3< 65D6> FB_B_ADDR<3> 50B4< 50B7< FW_D<7..0> 9B3> HPD_BASE 57A2<>
=GND_CHASSIS_INVERTER2 2C4> 56A2< =PP3V3_I2_PCISLOTEGPIOS 10B5< 22B7< =RP3514P2 6A7> 32B2< A29_DETECT 12D1< 13A5<> 13C4<> CBUS_ADDR<24> 61A4> 61B2< ENET_TX_ER 9B3> 11A7 FB_B_ADDR<4> 50B4< 50B7< FW_D<1> 6A6> 69B5<> HPD_ON 57A3<>
=GND_CHASSIS_INV_GND_CLIP 2D1<> 2D4> =PP3V3_PCI 10B1> 59D1< =RP3514P3 6A7> 32B2< A29_DET_L 12C2< CBUS_ADDR<25> 61A4> 61B2< ENET_TX_ER_R 11A8< 65B3< 65D6> FB_B_ADDR<5> 50B4< 50B7< FW_D<2> 6A6> 69B5<> HPD_ON_RC 57A3<
=GND_CHASSIS_LCD1 2D4> 56C5<> =PP3V3_PCI_AIRPORT 10B1> 60C3<> =RP5610P1 6B5> 43B2< A29_DET_REF 12C2< CBUS_ADDR_16_R 61B5<> EXT_TMDS_CLK_CMF 54D2< FB_B_ADDR<6> 50B4< 50B7< FW_D<3> 6A6> 69B5<> HPD_PWR_SNS_EN 51B5<> 57A4<>
=GND_CHASSIS_LCD2 2D4> 56C6< =PP3V3_PCI_ROM 10B5< 58B6< 58C5<> =RP5610P2 6B5> 43C2< AB_SEL_LOW 36A6<> CBUS_BVD1_L 61A2< 61C4< EXT_TMDS_D0_CMF 54D1< FB_B_ADDR<7> 50B4< 50B7< FW_D<4> 6A6> 69B5<> HPD_PWR_SW 57A4<>
112
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
I2C_GPU_TMDS_SCL 8A5< 8D6> MAXBUS_CPU0_DRDY_L 6B8< 32C6> 32D5< 33D3< PCI_AD<20> 11C2< 59B3< 59D6> 60C3<> 61B7<> PP3V3_PWRON_NEC_AVDD 73D4< RAM_DATA_A<14> 40D6<> RAM_DQS_A_P<6> 40A6<> TPS2211_SHTDWN_L 61C5< UATA_DD_R<11> 6C8<
I2C_GPU_TMDS_SDA 8A5< 8D6> MAXBUS_CPU0_DRDY_L_R 33D4<> 62C5<> PP3V3_PWRON_REG 10B6< RAM_DATA_A<15> 40D6<> RAM_DQS_A_P<7> 40A4<> TP_AIRPORT_ALT_ANTENNA 60B3<> UATA_DD_R<12> 6C8<
I2C_I2_NB_SCL 8C2< 8D6> MAXBUS_CPU0_HIT_L 6B8< 32C6> 32D5< 33D4> PCI_AD<21> 11B2< 59B3< 59D6> 60C5<> 61B7<> PP3V3_RUN 10B2 RAM_DATA_A<16> 40C6<> RAM_DQS_B_N<0> 39B5< 41D6<> TP_AIRPORT_PME_L 60C3<> UATA_DD_R<13> 6C8<
I2C_I2_NB_SDA 8C2< 8D6> MAXBUS_CPU0_INT_L 6B8< 32D3< 34D4< 62C5<> PP3V3_RUN_PCI1510 61C8< 61D5< RAM_DATA_A<17> 40C4<> RAM_DQS_B_N<1> 39A5< 41D6<> TP_ATI_GPIO8 51B5<> UATA_DD_R<14> 6C8<
I2C_I2_SB_SCL 8D2< 8D6> MAXBUS_CPU0_QACK_L 32D3< 33B1< PCI_AD<22> 59B3< 60C5<> 61B7<> 62C5<> PP3V3_SI_M_AVCC 54C4< RAM_DATA_A<18> 40C6<> RAM_DQS_B_N<2> 39A5< 41C6<> TP_ATI_GPIO9 51B5<> UATA_DD_R<15> 6C8<
I2C_I2_SB_SDA 8D2< 8D6> MAXBUS_CPU0_QREQ_L 32B2< 32D5< 33C1> PCI_AD<23..22> 59D6> PP3V3_SI_M_PVCC 54C4< RAM_DATA_A<19> 40C4<> RAM_DQS_B_N<3> 39A5< 41C4<> TP_ATI_GPIO10 51B5<> UATA_DMACK_L 7B7> 63B1> 63C6> 64B4<> 64B7<>
I2C_PMU_SCL 8C5< 8D6> MAXBUS_CPU1_BG_L 6B8< 32C6> 32D3< PCI_AD<23> 59B3< 60C3<> 61B7<> 62C5<> PP3V3_SI_M_VCC 54C5< RAM_DATA_A<20> 40D6<> RAM_DQS_B_N<4> 39A5< 41B6<> TP_ATI_GPIO11 51B5<> UATA_DMACK_L_R 63B2< 63B3< 63D6>
I2C_PMU_SDA 8C5< 8D6> MAXBUS_CPU1_BR_L 6B8< 32C6> 32D5< PCI_AD<24> 59B3< 60C3<> 61B7<> 62C5<> PP3V3_SI_S_AVCC 55C5< RAM_DATA_A<21> 40C6<> RAM_DQS_B_N<5> 39A5< 41B4<> TP_ATI_GPIO12 51B5<> UATA_DMARQ 7B7> 63B1< 63C6> 64B4<> 64B7<>
I2C_PMU_SMB_SCL 8B5< 8D6> MAXBUS_CPU1_DBG_L 6A8< 32C6> 32D3< PCI_AD<31..24> 58C3<> 59D6> PP3V3_SI_S_PVCC 55D5< RAM_DATA_A<22> 40C4<> RAM_DQS_B_N<6> 39A5< 41A6<> TP_CPU0_CLKOUT 33C1> UATA_DMARQ_R 63B2< 63B5< 63D6>
I2C_PMU_SMB_SDA 8B5< 8D6> MAXBUS_CPU1_DRDY_L 6B8< 32C6> 32D5< PCI_AD<25> 59B3< 60C5<> 61B7<> 62C5<> PP3V3_SI_S_VCC 55C5< RAM_DATA_A<23> 40D4<> RAM_DQS_B_N<7> 39A5< 41A4<> TP_CPU0_HPR_N 34C4<> UATA_DSTROBE 7B7> 63A1< 63C6> 64B2<> 64B5<>
I2C_VESTA_SCL 69B3<> MAXBUS_CPU1_HIT_L 6B8< 32C6> 32D5< PCI_AD<26> 59B3< 60C5<> 61B7<> 62C5<> PP3V3_VESTA 10D5 RAM_DATA_A<24> 40C4<> RAM_DQS_B_P<0> 41D6<> TP_CPU0_OVDDSENSE1 33B8< UATA_DSTROBE_R 63A2< 63B5< 63D6>
I2C_VESTA_SDA 69B3<> MAXBUS_CPU1_INT_L 6B8< 32D3< PCI_AD<27> 59A3< 60C5<> 61B7<> 62B5<> PP3V3_VESTA_FAVDDH 69D2< RAM_DATA_A<25> 40C4<> RAM_DQS_B_P<7..0> 39B5> TP_CPU0_OVDDSENSE2 33B8< UATA_HSTROBE 7B7> 63B1> 63D6> 64B4<> 64B7<>
I2PLLVDD_ADJ 20A4< MAXBUS_CPU1_QREQ_L 32A2< 32D5< PCI_AD<28> 59A3< 60C3<> 61B7<> 62B5<> PP4V6_ALL_RAW 14B3<> RAM_DATA_A<26> 40C6<> RAM_DQS_B_P<1> 41D6<> TP_CPU0_PMON_OUT_L 34D4> UATA_HSTROBE_R 63B2< 63B3< 63D6>
I2PLLVDD_BYP 20A4<> MAXBUS_DATA<0> 32C3< 33D6<> PCI_AD<29> 59A3< 60C5<> 61B7<> 62B5<> PP4V85_ALL 10C7 RAM_DATA_A<27> 40C6<> RAM_DQS_B_P<2> 41C6<> TP_CPU0_SENSEGND1 35B6< UATA_INTRQ 7B7> 63A1< 63C6> 64B2<> 64B5<>
I2S0_BITCLK 6D6> 7A7> 74B3<> MAXBUS_DATA<0..40> 32D6> PCI_AD<30> 59A3< 60C5<> 61B7<> 62B5<> PP4V85_ALL_ESR 14A4< RAM_DATA_A<28> 40C4<> RAM_DQS_B_P<3> 41C4<> TP_CPU0_SENSEGND2 35B6< UATA_INTRQ_R 63A2< 63B5< 63D6>
I2S0_BITCLK_R 6D8< 22B2< 22D6> MAXBUS_DATA<63..0> 9C3> PCI_AD<31> 59A3< 60C3<> 61B7<> 62B5<> PP5V_INV_SW 7B7> 56C2<> RAM_DATA_A<29> 40C6<> RAM_DQS_B_P<4> 41B6<> TP_CPU0_SENSEVDD1 35B8< UATA_PDIAG 64B4<> 64B7<>
I2S0_DEV_TO_SB_DTI 7A7> 22B5< 22D6> 74C4<> MAXBUS_DATA<1> 32C3< 33D6<> PCI_AIRPORT_GNT_L 6B6< 11D2 PP5V_INV_SW_F 56C3<> RAM_DATA_A<30> 40C6<> RAM_DQS_B_P<5> 41B4<> TP_CPU0_SENSEVDD2 35B8< UATA_RESET_L 7B7> 63B1> 63C6> 64C2<> 64C7<>
I2S0_MCLK 6D6> 7A7> 74B3<> MAXBUS_DATA<2> 32C3< 33D6<> PCI_AIRPORT_IDSEL 60C5<> PP5V_LTC1625_EXTVCC_SW 14D6<> RAM_DATA_A<31> 40C4<> RAM_DQS_B_P<6> 41A6<> TP_CPU0_TEMP_ANODE 34D4<> UATA_RESET_L_R 63B2< 63B3< 63D6>
D
I2S0_MCLK_R 6D8< 22B2< 22D6>
I2S0_SB_TO_DEV_DTO 6D6> 7A7> 74B4<>
I2S0_SB_TO_DEV_DTO_R 6D8< 22B2< 22D6>
MAXBUS_DATA<3>
MAXBUS_DATA<4>
MAXBUS_DATA<5>
32C3< 33D6<>
32C3< 33D6<>
32C3< 33D6<>
PCI_AIRPORT_INT_L 11C2
PCI_AIRPORT_REQ_L 6A6< 11D2
PCI_CBE_L<0> 59B3< 60B5<> 61B7<> 62B5<>
PP5V_MAX1715_VCC 16D5<
PP5V_PWRON 7C7> 10C5<>
PP5V_PWRON_AUDIO_AVDD 7A7> 74C6<>
RAM_DATA_A<32>
RAM_DATA_A<33>
RAM_DATA_A<34>
40B4<>
40B6<>
40B6<>
RAM_DQS_B_P<7>
RAM_DQS_P_R<0>
41A4<>
38C6>
RAM_DQS_P_R<7..0> 38C3<> 39B6<
TP_CPU0_TEMP_CATHODE 34D4<>
TP_ENET_ENERGYDET 11A7<
TP_EXTTMDS_RESET_L 11C8< 51B5<>
UATA_STOP
UATA_STOP_R
7B7> 63B1> 63D6> 64B2<> 64B5<>
63B2< 63B3< 63D6>
USB2_I2_LEFT_PORT_N 6B3> 11B8< 11C5<
D
I2S0_SYNC 6D6> 7A7> 74B3<> MAXBUS_DATA<6> 32C3< 33D6<> PCI_CBE_L<3..0> 59D6> PP5V_PWRON_AUDIO_PVDD 7A7> 74C6<> RAM_DATA_A<35> 40B4<> RAM_DQS_P_R<1> 38C6> TP_GOV_RESET_L 11B3> USB2_I2_LEFT_PORT_P 6B3> 11B8< 11C5<
I2S0_SYNC_R 6D8< 22B2< 22D6> MAXBUS_DATA<7> 32C3< 33D6<> PCI_CBE_L<1> 59B3< 60B3<> 61B7<> 62B5<> PP5V_PWRON_REG 10C6< RAM_DATA_A<36> 40B4<> RAM_DQS_P_R<2> 38C6> TP_I2_PENDINT 22A2< USB2_I2_N<0> 11B7> 72C4< 72D6>
I2S1_BITCLK 6D6> 30A5<> MAXBUS_DATA<8> 32C3< 33D6<> PCI_CBE_L<2> 59B3< 60B3<> 61B7<> 62B5<> PP5V_RUN 7C7> 10C2 RAM_DATA_A<37> 40B4<> RAM_DQS_P_R<3> 38C6> TP_JTAG_CPU_TDO 9D5> USB2_I2_N<1> 6B3> 72C4< 72D6>
I2S1_BITCLK_R 6D8< 22B2< 22D6> MAXBUS_DATA<9> 32C3< 33D6<> PCI_CBE_L<3> 59A3< 60C5<> 61B7<> 62B5<> PP5V_RUN_DDC 57B4<> 57D3<> RAM_DATA_A<38> 40B6<> RAM_DQS_P_R<4> 38C6> TP_JTAG_I2_TDO 9C5> USB2_I2_N<2> 11B7> 72B4< 72D6>
I2S1_DEV_TO_SB_DTI 22B5< 22D6> 30A5<> MAXBUS_DATA<10> 32C3< 33D6<> PCI_CBUS_GNT_L 6A6< 11C2 PP5V_RUN_DDC_FUSE 57D4< RAM_DATA_A<39> 40B6<> RAM_DQS_P_R<5> 38C6> TP_JTAG_VESTA_TCK 9A5<> USB2_I2_N<3> 6B3> 72B4< 72D6>
I2S1_MCLK 6D6> 30A4<> MAXBUS_DATA<11> 32C3< 33D6<> PCI_CBUS_IDSEL 61B7< PP5V_RUN_DDC_PULLUPS 57D2<> RAM_DATA_A<40> 40B6<> RAM_DQS_P_R<6> 38C6> TP_JTAG_VESTA_TDI 9A7< USB2_I2_N<4> 11B7> 72B4< 72D6>
I2S1_MCLK_R 6D8< 22B2< 22D6> MAXBUS_DATA<12> 32C3< 33D6<> PCI_CBUS_INT_L 11C2 PP5V_RUN_HDD 10C2 RAM_DATA_A<41> 40A4<> RAM_DQS_P_R<7> 38C6> TP_JTAG_VESTA_TDO 9A5> USB2_I2_N<5> 11B7> 72B4< 72D6>
I2S1_SB_TO_DEV_DTO 6D6> 30A5<> MAXBUS_DATA<13> 32C3< 33D6<> PCI_CBUS_REQ_L 6B6< 11C2 PP5V_RUN_ODD 64C3<> RAM_DATA_A<42> 40A6<> RAM_ODT<0> 39B7< 40B4<> TP_JTAG_VESTA_TMS 9A5<> USB2_I2_P<0> 11B7> 72C4< 72D6>
I2S1_SB_TO_DEV_DTO_R 6D8< 22B2< 22D6> MAXBUS_DATA<14> 32C3< 33D6<> PCI_CBUS_RESET_L 61A7< PP5V_TPAD 10C2 RAM_DATA_A<43> 40B4<> RAM_ODT<1..0> 39A6> TP_LVDS_L3_N 53A7> USB2_I2_P<1> 6B3> 72C4< 72D6>
I2S1_SYNC 6D6> 30A5<> MAXBUS_DATA<15> 32C3< 33D6<> PCI_CLK33M_AIRPORT 11D2< PP5V_TPAD_F 7D5> 30D5<> RAM_DATA_A<44> 40A6<> RAM_ODT<1> 39B7< 41B4<> TP_LVDS_L3_P 53A7> USB2_I2_P<2> 11B7> 72C4< 72D6>
I2S1_SYNC_R 6D8< 22B2< 22D6> MAXBUS_DATA<16> 32C3< 33D6<> PCI_CLK33M_AIRPORT_R 11D3< PP12V8_ALL_PBUSB 7D7> 10D7<> RAM_DATA_A<45> 40A4<> RAM_ODT_R<0> 38B3> 38D6> 39B8< TP_LVDS_U3_N 53B7> USB2_I2_P<3> 6B3> 72B4< 72D6>
I2VCORE_ITH 20C5<> MAXBUS_DATA<17> 32C3< 33D6<> PCI_CLK33M_CBUS 11C2< PP24V_ADAPTER 7D7> 10C7 RAM_DATA_A<46> 40B6<> RAM_ODT_R<1> 38B3> 38C6> 39B8< TP_LVDS_U3_P 53B7> USB2_I2_P<4> 11B7> 72B4< 72D6>
I2VCORE_ITH_RC 20C6< MAXBUS_DATA<18> 32C3< 33D6<> PCI_CLK33M_CBUS_R 11C3< PP24V_ADAPTER_ILIM_P 13D7<> RAM_DATA_A<47> 40B4<> RAM_RAS_L 39A6> 39B7< 40B4<> 41B4<> TP_MAXBUS_CLK_CPU1_R 11D7< 32D3< 32D6> USB2_I2_P<5> 11B7> 72B4< 72D6>
I2VCORE_MODE 20C5<> MAXBUS_DATA<19> 32C3< 33D6<> PCI_CLK33M_TBEN_SYNC 11D2< PP24V_ADAPTER_SW 12D4<> 13C6< 13D8<> RAM_DATA_A<48> 40A4<> RAM_RAS_L_R 38B3> 38D6> 39B8< TP_MAXBUS_CPU1_QACK_L 11A5< 32D3< USB2_I2_RIGHT_PORT_N 6B3> 11B8< 11C5<
I2VCORE_MODE_VDIV 20C5< MAXBUS_DATA<20> 32C3< 33D6<> PCI_CLK33M_TBEN_SYNC_R 11D3< PP24V_ADAPT_PMU_ILIM 14A7<> RAM_DATA_A<49> 40A6<> RAM_VREF 40A7< TP_MAXBUS_TBEN_I2 32A3< USB2_I2_RIGHT_PORT_P 6B3> 11B8< 11C5<
I2VCORE_RT 20C5< MAXBUS_DATA<21> 32C3< 33C6<> PCI_CLK33M_USB2 11C2< PP24V_ALL_PBUSA 7D7> 10D7 RAM_DATA_A<50> 40A4<> RAM_WE_L 39A6> 39B7< 40B6<> 41B6<> TP_NEC_AMC 62A3< USB2_LEFT_PORT_N 7B5> 11C7< 31B3<>
I2VCORE_RUNSS 20C5<> MAXBUS_DATA<22> 32C3< 33C6<> PCI_CLK33M_USB2_R 11C3< PPAVDD_CPU0 10C2 RAM_DATA_A<51> 40A6<> RAM_WE_L_R 38B3> 38D6> 39B8< TP_NEC_NANDTEST 62A3< USB2_LEFT_PORT_P 7B5> 11D7< 31B3<>
I2VCORE_SW 20C4<> MAXBUS_DATA<23> 32C3< 33C6<> PCI_CLK33M_ZDB 11D2< PPBUS_DVI_PWRSW 10D6<> RAM_DATA_A<52> 40A6<> ROM_CS_L 58B6< 59C3< 60B3<> TP_NEC_NTEST1 62B3< USB2_NEC_LEFT_PORT_N 6B3> 11B6< 11C5<
I2VCORE_VFB 20C5<> MAXBUS_DATA<24> 32C3< 33C6<> PCI_CLK33M_ZDB_R 11D3< PPBUS_FWPWRSW_F 18D7<> RAM_DATA_A<53> 40A4<> ROM_OE_L 58B6< 59C3< 60B3<> TP_NEC_SMC 62B3< USB2_NEC_LEFT_PORT_P 6B3> 11B6< 11D5<
I2_ACS_REF 32A5< MAXBUS_DATA<25> 32C3< 33C6<> PCI_CLK_DELAY_ADJ 23B5<> PPBUS_FW_FET_D 18D6<> RAM_DATA_A<54> 40A6<> ROM_ONBOARD_CS_L 58B6< 60B3<> TP_NEC_SMI_L 62A5> USB2_NEC_N<0> 11B5> 73C2<> 73D7>
I2_AGP_FBCLK_IN 21C4< 21D6> MAXBUS_DATA<26> 32B3< 33C6<> PCI_DEVSEL_L 59C5< 59D2< 59D6> 60B5<> 61A7<> PPBUS_INVERTER 7B7> 56C2<> RAM_DATA_A<55> 40A4<> ROM_WE_L 58B6< 59C3< 60B3<> TP_NEC_SRCLK 62A3> USB2_NEC_N<1> 11B5> 73C2<> 73D7>
I2_AGP_FBCLK_MATCHED 21C3< 21D6> MAXBUS_DATA<27> 32B3< 33C6<> 62B5<> PPFW_CABLE_POWER 10D5 RAM_DATA_A<56> 40A4<> ROM_WP_L 58B5< TP_NEC_SRDATA 62A3<> USB2_NEC_N<2> 11B5> 73B2<> 73D7>
I2_AGP_FBCLK_OUT 21C5< 43A2< 43D6> MAXBUS_DATA<28> 32B3< 33C6<> PCI_FRAME_L 6A6< 59C5< 59D6> 60C3<> 61B7<> PPFW_PORT1_VP 70D2<> RAM_DATA_A<57> 40A6<> RT_ALS_OP_COMP 28D4< TP_NEC_SRMOD 62A3< USB2_NEC_N<3> 11B5> 73B2<> 73D7>
I2_AGP_FBCLK_OUT_R 43A3< 43D6> MAXBUS_DATA<29> 32B3< 33C6<> 62B5<> PPFW_PORT2_VP 70B3<> RAM_DATA_A<58> 40A4<> RT_ALS_OP_IN 28D5< TP_NEC_TEB 62B3< USB2_NEC_P<0> 11B5> 73C2<> 73D7>
I2_AGP_PVTREF 43A5< MAXBUS_DATA<30> 32B3< 33C6<> PCI_IRDY_L 6B6< 59C5< 59D6> 60C5<> 61B7<> PPFW_PORT2_VP_F 70B3< RAM_DATA_A<59> 40A6<> RT_ALS_OUT_FB 28D4<> TP_NEC_TEST 62A3< USB2_NEC_P<1> 11B5> 73C2<> 73D7>
I2_AUDIO_LO_MUTE_L 22C5< 22C7<> MAXBUS_DATA<31> 32B3< 33C6<> 62B5<> PPVBATT_BATT 10C7 RAM_DATA_A<60> 40A6<> RT_ALS_PHOTODIODE 28D5<> TP_PCI_CLK33M_SLOTA_R 11D4< 59C3< 59D6> USB2_NEC_P<2> 11B5> 73B2<> 73D7>
I2_AUDIO_SPKR_MUTE_L 22B2<> 22C5< MAXBUS_DATA<32> 32B3< 33C6<> PCI_PAR 59C5< 59D6> 60B5<> 61B7<> 62B5<> PPVBATT_BATTPOS_CONN 12B7<> RAM_DATA_A<61> 40A6<> SCCA_RXD 7B5> 22B6< 24C2<> TP_PCI_CLK33M_SLOTD_R 11D4< 59C3< 59D6> USB2_NEC_P<3> 11B5> 73B2<> 73D7>
I2_CLK18M_XIN 22A5< 22D6> MAXBUS_DATA<33> 32B3< 33C6<> PCI_PERR_L 61B7<> 61C7< PPVBATT_BATT_CHRG_VSNS 10C7 RAM_DATA_A<62> 40A4<> SCCA_TXD_L 7B5> 22B2< 24C1<> TP_PCI_CLK33M_ZDBOUT3 11B2> USB2_NEC_RIGHT_PORT_N 6B3> 11B6< 11C5<
I2_CLK18M_XOUT 22A6< 22D6> MAXBUS_DATA<34> 32B3< 33C6<> PCI_RESET_L 11A5< 11B2< 11C2< 11C2< 11C8< PPVBATT_BATT_PBUSA_FUSE 13B1< 13D2<> RAM_DATA_A<63> 40A4<> SI_HTPLG 54B6< 55B6< TP_PMU_AN_P0_0 11B1> 25C5<> USB2_NEC_RIGHT_PORT_P 6B3> 11B6< 11C5<
I2_CLK18M_XOUT_R 22A5< 22D6> MAXBUS_DATA<35> 32B3< 33C6<> 25A7< 25C2<> PPVBATT_BATT_PBUSB_FUSE 13D1<> RAM_DATA_B<0> 41D6<> SI_IDCK_N 54A4< 54A6< 55A6< TP_PMU_AN_P0_1 11B1> 25C5<> USB2_OC<0> 73B6<
I2_CLK30M_USB2_XIN 72B6< 72D6> MAXBUS_DATA<36> 32B3< 33C6<> PCI_SERR_L 61B7< 61B7> PPVBATT_BATT_RAW 12B5<> RAM_DATA_B<63..0> 39B5> SI_M_A1 54B6< TP_PMU_AN_P0_2 11B1> 25C5<> USB2_OC<1> 73B6<
I2_CLK30M_USB2_XOUT 72B7< 72D6> MAXBUS_DATA<37> 32B3< 33C6<> PCI_SLOTA_GNT_L 11D3< 59C3< 59C6> PPVBATT_ISNS_VINN 12A4<> 12D6> RAM_DATA_B<1> 41D4<> SI_M_EXTSWING 54A3< TP_PMU_AN_P0_3 11B1> 25C5<> USB2_OC<2> 73B6<
I2_CLK30M_USB2_XOUT_R 72B6< 72D6> MAXBUS_DATA<38> 32B3< 33C6<> PCI_SLOTA_INT_L 11C3< 22D5< 59C2< PPVBATT_ISNS_VINP 12A5<> 12D6> RAM_DATA_B<2> 41D4<> SI_M_MSEN 54B3<> TP_PMU_AN_P0_4 11B1> 25C5<> USB2_OC<3> 73B6<
I2_ENET_MDIO 65C4<> 65D6> MAXBUS_DATA<39> 32B3< 33C6<> PCI_SLOTA_REQ_L 11D3< 59C5< 59C6> PPVCC_CBUS_SW 61B1< 61B2< 61D2<> RAM_DATA_B<3> 41D6<> SI_SYNC 54B6<> 55B6<> TP_PMU_AN_P0_5 11B1> 25C5<> USB2_OC<4> 73B6<
I2_ENET_PVT 65B5< MAXBUS_DATA<40> 32B3< 33C6<> PCI_SLOTD_GNT_L 11C3< 59C3< 59C6> PPVCORE_CPU_ADT7467 10C4<> RAM_DATA_B<4> 41D4<> SI_S_A1 55B6< TP_PMU_AN_P0_6 25A8< 25C5<> USB2_RIGHT_PORT_N 7B5> 11C7< 31B7<>
I2_EXT_08 22D5< MAXBUS_DATA<41> 21B8< 32B3< 32D6> 33C6<> PCI_SLOTD_INT_L 11C3< 22D5< 59C2< PPVCORE_GPU_REG 10A8< RAM_DATA_B<5> 41D4<> SI_S_EXTSWING 55B4< TP_PMU_AN_P0_7 25A8< 25C5<> USB2_RIGHT_PORT_P 7B5> 11C7< 31B7<>
I2_EXT_13 22C5< MAXBUS_DATA<42> 21B8< 32B3< 32D6> 33C6<> PCI_SLOTD_REQ_L 11C3< 59C5< 59C6> PPVCORE_PWRON_I2 10A7<> RAM_DATA_B<6> 41D6<> SI_S_MSEN 55B4<> TP_PMU_AN_P10_0 25A8< 25B2<> USB_BT_N 11C5< 60B5<>
I2_EXT_14 22C5< MAXBUS_DATA<43> 21B8< 32B3< 32D6> 33C6<> PCI_SLOTE_GNT_L 11C3< 22B7< 22C5< PPVCORE_PWRON_I2_REG 10A8< RAM_DATA_B<7> 41D6<> SI_TMDS_CLKN 54B3< 54C6> 54D7< TP_PMU_AN_P10_1 25A8< 25B2<> USB_BT_P 11D5< 60B5<>
I2_FW_PVT 68C5< MAXBUS_DATA<44> 21B8< 32B3< 32D6> 33C6<> PCI_SLOTE_INT_L 11B3< 22B7< 22C5< PPVCORE_RUN_CPU 7C7> 10C5<> RAM_DATA_B<8> 41D4<> SI_TMDS_CLKP 54B3< 54C6> 54D7< TP_PMU_AN_P10_2 25A8< 25B2<> USB_I2_BT_N 6B3> 11B8< 11C4<
I2_GPIO_11 22A6< 22C5< MAXBUS_DATA<45> 32B3< 33C6<> PCI_SLOTE_REQ_L 11C3< 22A7< 22C5< PPVCORE_RUN_GPU 7D7> 10A7<> RAM_DATA_B<9> 41D6<> SI_TMDS_DN<0> 54B3< 54C6> 54D7< TP_PMU_AN_P10_3 25A7< 25B2<> USB_I2_BT_P 6B3> 11B8< 11C4<
I2_GPIO_EXT_02 11A5< 22A7< 22C5< MAXBUS_DATA<45..53> 32D6> PCI_STOP_L 6B6< 59C5< 59D6> 60B5<> 61B7<> PPVIN_1778_VIN 45C5< RAM_DATA_B<10> 41D6<> SI_TMDS_DN<1> 54B3< 54C6> 54D5< TP_PMU_AN_P10_4 25A7< 25B2<> USB_I2_TPAD_N 6B3> 11B8< 11C4<
C I2_MAXBUS_FBCLK_IN 21D3< 21D6>

I2_MAXBUS_FBCLK_MATCHED 21D4< 21D6>
I2_MAXBUS_FBCLK_OUT 21D6< 32A2< 32D6>
MAXBUS_DATA<46>
MAXBUS_DATA<47>
MAXBUS_DATA<48>
32B3<
32B3<
32B3<
33C6<>
33B6<>
33B6<>
PCI_TRDY_L
62B5<>
6B6< 59C5< 59D6> 60B3<> 61A7<>
62B5<>
PPVIN_ALL_ADAPT_OR_BATT 14A6<>
PPVIN_CPU0_AVDD 37C6<
PPVIN_VESTA3V3 18D5<>
RAM_DATA_B<11>
RAM_DATA_B<12>
RAM_DATA_B<13>
41D4<>
41D4<>
41D4<>
SI_TMDS_DN<2>
SI_TMDS_DN<3>
SI_TMDS_DN<4>
54B3< 54C6> 54D5<
55B4< 55C6> 55D2<
55B4< 55C6> 55D2<
TP_PMU_AN_P10_5 11A1>
TP_PMU_AN_P10_6 11B3>
TP_PMU_AN_P10_7 25A4<
25A7< 25B2<>
25A7< 25B2<>
25B2<>
USB_I2_TPAD_P
USB_NEC_BT_N
USB_NEC_BT_P
6B3> 11B8< 11C4<
6A3> 11B6< 11C4<
6A3> 11B6< 11D4<
C
I2_MAXBUS_FBCLK_OUT_R 32A4< 32D6> MAXBUS_DATA<49> 32B3< 33B6<> PCI_USB2_GNT_L 11C2 PPVOUT_1778_VCC 45C5<> RAM_DATA_B<14> 41D6<> SI_TMDS_DN<5> 55B4< 55C6> 55D2< TP_PMU_P3_0 11A3> 25A5< 25B5<> USB_NEC_N<0> 73C3<>
I2_MEM_VREF 38A5< MAXBUS_DATA<50> 32B3< 33B6<> PCI_USB2_IDSEL 62B5< PPVOUT_BATT_CHRG_R 13B2< RAM_DATA_B<15> 41D6<> SI_TMDS_DP<0> 54B3< 54C6> 54D7< TP_PMU_P3_1 11A3> 25A5< 25B5<> USB_NEC_N<1> 73C3<>
I2_PCI_FBCLK_IN 21B4< 21D6> MAXBUS_DATA<51> 32B3< 33B6<> PCI_USB2_INT_L 11B2 PPVOUT_BU_BATT 31A7<> RAM_DATA_B<16> 41C6<> SI_TMDS_DP<1> 54B3< 54C6> 54D5< TP_PMU_P3_2 11A3> 25A5< 25B5<> USB_NEC_N<2> 73B3<>
I2_PCI_FBCLK_MATCHED 21C3< 21D6> MAXBUS_DATA<52> 32A3< 33B6<> PCI_USB2_REQ_L 11C2 PPVOUT_CPU0_AVDD_R 37C4<> RAM_DATA_B<17> 41C4<> SI_TMDS_DP<2> 2B4> 54B3< 54C6> 54D5< TP_PMU_P3_3 11A3> 25A5< 25B5<> USB_NEC_N<3> 73B3<>
I2_PCI_FBCLK_OUT 21C5< 59A2< 59D6> MAXBUS_DATA<53> 32A3< 33B6<> PMU_BATT0_CHARGE 13A8<> 25C2<> PPVOUT_VESTA1V2 18C4< RAM_DATA_B<18> 41D6<> SI_TMDS_DP<3> 55B4< 55C6> 55D2< TP_PMU_P7_0 25A8< 25C2<> USB_NEC_P<0> 73C3<>
I2_PCI_FBCLK_OUT_R 59A4< 59D6> MAXBUS_DATA<54> 21B8< 32A3< 32D6> 33B6<> PMU_BATT1_CHARGE 25A4> PPVPP_CBUS_SW 61B1< 61B2< 61D2<> RAM_DATA_B<19> 41C4<> SI_TMDS_DP<4> 55B4< 55C6> 55D2< TP_PMU_P7_1 25A8< 25C2<> USB_NEC_P<1> 73C3<>
I2_SD_REF 38A5< MAXBUS_DATA<55> 32A3< 33B6<> PMU_BATT1_DET_L 25A4> PWRON_REGS_PGOOD 26B7< RAM_DATA_B<20> 41C6<> SI_TMDS_DP<5> 55B4< 55C2< 55C6> TP_PMU_P7_2 25A7< 25C2<> USB_NEC_P<2> 73B3<>
I2_TST_PLLEN 22B5< MAXBUS_DATA<55..61> 32D6> PMU_BOOT_BUSY 24C1<> 25C2<> RAM_ADDR<0> 39D7< 40B4<> 41B4<> RAM_DATA_B<21> 41C6<> SI_TMDS_RESET_L 11C8 TP_PMU_P7_4 11B1> 25A5< 25C2<> USB_NEC_P<3> 73B3<>
I2_TST_TEI 22B5< MAXBUS_DATA<56> 32A3< 33B6<> PMU_BOOT_CNVSS 24C2<> 25B5< RAM_ADDR<13..0> 39A6> RAM_DATA_B<22> 41D4<> SI_VREF 54A3< 54A3< 55A4< TP_PMU_P7_5 11B3> 25A5< 25C2<> USB_NEC_TPAD_N 6A3> 11B6< 11C4<
I2_UATA_VREF 63B5< MAXBUS_DATA<57> 32A3< 33B6<> PMU_BOOT_RP_L 24C1<> 25C2> RAM_ADDR<1> 39D7< 40B6<> 41B6<> RAM_DATA_B<23> 41C4<> SLEEP_LED_I 24B6< TP_USB2_PWREN<0> 73B5> USB_NEC_TPAD_P 6A3> 11B6< 11C4<
I2_USB2_VREF 72B5< MAXBUS_DATA<58> 32A3< 33B6<> PMU_BOOT_RXD 24C1<> 25C2<> RAM_ADDR<2> 39D7< 40B4<> 41B4<> RAM_DATA_B<24> 41C4<> SLEEP_LED_IOUT 11A4 TP_USB2_PWREN<1> 73B5> USB_TPAD_N 7D5> 11C5< 30C6<>
IAC_FB 13D4< MAXBUS_DATA<59> 32A3< 33B6<> PMU_BOOT_SCLK 24C2<> 25C2<> RAM_ADDR<3> 39D7< 40B6<> 41B6<> RAM_DATA_B<25> 41C4<> SLEEP_LED_L 24B7< TP_USB2_PWREN<2> 73B5> USB_TPAD_P 7D5> 11C5< 30C6<>
IAC_RC_COMP 13D4< MAXBUS_DATA<60> 32A3< 33B6<> PMU_BOOT_TXD 24C1<> 25C2<> RAM_ADDR<4> 39D7< 40B4<> 41B4<> RAM_DATA_B<26> 41C6<> SLEEP_LED_SW_L 24B7< TP_USB2_PWREN<3> 73B5> VCORE_BOOST 36C4<>
INV_ON_PWM 53B8<> 56B4< MAXBUS_DATA<61> 32A3< 33B6<> PMU_CHARGE_V 11B4< 13B8<> RAM_ADDR<5> 39D7< 40B6<> 41B6<> RAM_DATA_B<27> 41C6<> SOFTMODEM_FC_RGDT 30A4<> TP_USB2_PWREN<4> 73B5> VCORE_BST 36C5<>
JTAG_ASIC_TCK 9B8< MAXBUS_DATA<62> 21B8< 32A3< 32D6> 33B6<> PMU_CLK10M_XIN 25B5< 25D6> RAM_ADDR<6> 39C7< 40C4<> 41C4<> RAM_DATA_B<28> 41C4<> SPI_CHGR_TO_PMU_MISO 25A4> TP_VCORE_PGOOD 26B4> VCORE_CC 36B6<>
JTAG_ASIC_TMS 9B8< MAXBUS_DATA<63> 32A3< 32D6> 33B6<> PMU_CLK10M_XOUT 25A6< 25D6> RAM_ADDR<7> 39C7< 40C4<> 41C4<> RAM_DATA_B<29> 41C6<> SPI_PMU_CHGR_CLK 25A4> TP_VESTA_2_5V_EN 18A3< VCORE_CPU0_SHDN_L 26B4<> 36C7<>
JTAG_ASIC_TRST_L 9B8< MAXBUS_DTI<0> 32A3< 33D4< PMU_CLK10M_XOUT_R 25B5<> 25D6> RAM_ADDR<8> 39C7< 40C6<> 41C6<> RAM_DATA_B<30> 41C6<> SPI_PMU_CHGR_CS 25A4> TP_VESTA_ACTLED_L 66A3> VCORE_DH 36B5<>
JTAG_CPU_TCK 9D7< MAXBUS_DTI<2..0> 9C3> 32C6> PMU_CLK32K_XIN 25B3<> 25D6> RAM_ADDR<9> 39C7< 40C6<> 41C6<> RAM_DATA_B<31> 41C4<> SPI_PMU_TO_CHGR_MOSI 25A4> TP_VESTA_AN_EN 66B3<> VCORE_DL 36B5<>
JTAG_CPU_TDI 9D7< MAXBUS_DTI<1> 32A3< 33D4< PMU_CLK32K_XOUT 25B1< 25D6> RAM_ADDR<10> 39C7< 40B6<> 41B6<> RAM_DATA_B<32> 41B4<> STOP_AGP_L 43D2< 43D3< 44B4< TP_VESTA_DNC_B9 18A6<> VCORE_FB 36B5<
JTAG_CPU_TMS 9D7< MAXBUS_DTI<2> 32A3< 33D4< PMU_CLK32K_XOUT_R 25B3<> 25D6> RAM_ADDR<11> 39C7< 40C4<> 41C4<> RAM_DATA_B<33> 41B6<> SYS_ACIN 12C6<> 13C8<> 18B8< 25C2<> TP_VESTA_DNC_C9 18A6<> VCORE_GND 36B5<>
JTAG_CPU_TRST_L 9D7< MAXBUS_EDTI 33A5< 33D4< PMU_CPU_CLK_EN 11B4< 25C5<> RAM_ADDR<12> 39C7< 40C6<> 41C6<> RAM_DATA_B<34> 41B6<> SYS_ACIN_L 12C5<> 13C3<> TP_VESTA_DNC_E9 18A6<> VCORE_GNDA 36B5<>
JTAG_I2_TDI 9C7< MAXBUS_GBL_L 9C3> 32B5< 32C6> 33C1<> PMU_CPU_HRESET_L 11B4< 25B5<> RAM_ADDR<13> 39C7< 40B4<> 41B4<> RAM_DATA_B<35> 41B4<> SYS_ACIN_L_RC 13C2<> TP_VESTA_EN_10B 66B6< VCORE_GNDDIV 36A4< 36B5<
JTAG_VESTA_TRST_L 9A8< MAXBUS_SHD0_L 33A5< 33C1<> PMU_CUSTOMER_RESET 24C7<> RAM_ADDR_R<0> 39D8< RAM_DATA_B<36> 41B4<> SYS_AC_DET 12C6<> 25C2<> TP_VESTA_ER 66B6< VCORE_GNDDIV_TEST 36A3<>
KBDLED_ANODE 7C5> 28A4< 30C6<> MAXBUS_SHD1_L 33A5< 33C1<> PMU_INT_L 22B6< 22D5< 25B2<> RAM_ADDR_R<13..0> 38D3> 38D6> RAM_DATA_B<37> 41B4<> SYS_AC_DET_L 12C6<> 24D8<> TP_VESTA_F1000 66B6< VCORE_GNDSNS 36A2<> 36A4< 36D6>
KBDLED_RETURN 7C5> 28A4<> 30C6<> MAXBUS_TA_L 6B8< 32A3< 32D6> 33D4< PMU_POWER_UP_L 25B5<> 25C7< 26D8< RAM_ADDR_R<1> 39D8< RAM_DATA_B<38> 41B6<> SYS_ADAPTER_ANALOG_AC_DET 7C5> 12D4< 31C7<> TP_VESTA_FDX 66B6< VCORE_GNDSNS_TEST 36A3<>
LCD_DIGON_L 56C8< MAXBUS_TBEN 21B2< 33C1< PMU_RESET_L 24B2< 24C2<> 24D6<> 25B5< RAM_ADDR_R<2> 39D8< RAM_DATA_B<39> 41B6<> SYS_BATT0_DET_L 12A5< 24C8<> 25C2<> TP_VESTA_FDXLED_L 66B3> VCORE_ILIM 36C6<>
LCD_PWREN_L 56C7<> MAXBUS_TBEN_SYNC 21B2<> PMU_SB_NMI_L 22B6< 22D5< 25B2<> RAM_ADDR_R<3> 39D8< RAM_DATA_B<40> 41B6<> SYS_CHARGE_LED_L 7C5> 24A6< 31D7<> TP_VESTA_HUB 66B6< VCORE_LX 36B5<>
LTC1625_ITH 13D3<> MAXBUS_TBST_L 9C3> 32B5< 32C6> 33C1> PMU_SYS_CLK_EN 11B4< 25C5<> RAM_ADDR_R<4> 39D8< RAM_DATA_B<41> 41A4<> SYS_COLD_RESET_L 25B7< 25C2<> TP_VESTA_LINKSPD1_L 66B3> VCORE_REF 36B6<>
LTC3412_GND 17B5<> MAXBUS_TEA_L 6A8< 32A3< 32D6> 33D4< PP1V2_VESTA 10D5 RAM_ADDR_R<5> 39D8< RAM_DATA_B<42> 41A6<> SYS_KBDLED 25C2<> 28A5<> TP_VESTA_LINKSPD2_L 66B3> VCORE_SEL_OFF_PU 36B6<>
LTC3412_ITH 17C5<> MAXBUS_TSIZ<0> 32B5< 33C1> PP1V2_VESTA_AVDDL 18B6< RAM_ADDR_R<6> 39C8< RAM_DATA_B<43> 41B4<> SYS_LED 24B8< 25C2<> TP_VESTA_MANMS 66B6< VCORE_SEL_ON 36B6<>
LTC3412_ITH_RC 17C6< MAXBUS_TSIZ<2..0> 9C3> 32C6> PP1V2_VESTA_FAVDDL 69C2< RAM_ADDR_R<7> 39C8< RAM_DATA_B<44> 41A6<> SYS_LID_OPEN 25C5<> 30C6< TP_VESTA_PHYA<0> 66B6< VCORE_SNS 36A2<> 36D6>
LTC3412_RT 17C5< MAXBUS_TSIZ<1> 32B5< 33C1> PP1V2_VESTA_PLLVDD1 66D4< RAM_ADDR_R<8> 39C8< RAM_DATA_B<45> 41A4<> SYS_LID_OPEN_F 7C5> 30C5<> TP_VESTA_PHYA<1> 66B6< VCORE_TIME 36B4<>
LTC3412_RUNSS 17C5<> MAXBUS_TSIZ<2> 32B5< 33C1> PP1V2_VESTA_PLLVDD2 69D4< RAM_ADDR_R<9> 39C8< RAM_DATA_B<46> 41B6<> SYS_ONEWIRE 24A7< 25B2<> TP_VESTA_PHYA<2> 66B6< VCORE_TON 36B6<
LTC3412_SW 17C4<> MAXBUS_TS_L 6B8< 32D5< 32D6> 33C3<> PP1V5R1V8_I2_MAXBUS 32B6< RAM_ADDR_R<10> 39C8< RAM_DATA_B<47> 41B4<> SYS_OVERTEMP_L 7C5> 11B4< 25B7< 25C2<> 30C6<> TP_VESTA_PHYA<3> 66B6< VCORE_VCC 36C6<
LTC3412_SYNC 17C5<> MAXBUS_TT<0> 32B5< 33C1<> PP1V5R3V3_GPU_VDDR4 47C3< 53C8< 53D8< RAM_ADDR_R<11> 39C8< RAM_DATA_B<48> 41A4<> SYS_PME_L 22A2< 25B7< 25C2<> 62A7< TP_VESTA_PHYA<4> 66B6< VCORE_VID<0> 36A2<> 36B8<
LTC3412_VFB 17C5<> MAXBUS_TT<4..0> 9C3> 32C6> PP1V5_GPU 10A7< RAM_ADDR_R<12> 39C8< RAM_DATA_B<49> 41A6<> SYS_PMU_ANALOG_AC_DET 11B4< 12C2< TP_VESTA_RBC0 66B3<> VCORE_VID<1> 36A2<> 36B8< 36D1<>
LTC3412_VFB_DIV 17C5< MAXBUS_TT<1> 32B5< 33C1<> PP1V5_GPU_AGP 47C3< RAM_ADDR_R<13> 39C8< RAM_DATA_B<50> 41A4<> SYS_POWERUP 26D5<> TP_VESTA_RBC1 66B3<> VCORE_VID<2> 36A2<> 36B8< 36D1<>
LVDS_DDC_CLK 7B7> 51B3<> 56C7<> MAXBUS_TT<2> 32B5< 33C1<> PP1V5_GPU_PSNECK 52C3<> RAM_BA<0> 39C7< 40B6<> 41B6<> RAM_DATA_B<51> 41A6<> SYS_POWER_BUTTON_L 24B2< 24C8<> 25B7< 25C5<> 30C6< TP_VESTA_REGCTL1 18A3< VCORE_VID<3> 36A2<> 36B8< 36D1<>
LVDS_DDC_DATA 7B7> 51B3<> 56C7<> MAXBUS_TT<3> 32B5< 33C1<> PP1V5_GPU_VDD15 46B2< RAM_BA<2..0> 39A6> RAM_DATA_B<52> 41A6<> 36A3<> 57B1<> TP_VESTA_REGCTL2 18A3< VCORE_VID<4> 36A2<> 36B8< 36D1<>
LVDS_L0_N 7C7> 53A7> 53D1> 56C5<> MAXBUS_TT<4> 32B5< 33C1<> PP1V5_GPU_VDD15_F 46B4<> RAM_BA<1> 39B7< 40B4<> 41B4<> RAM_DATA_B<53> 41A4<> SYS_POWER_BUTTON_L_F 7C5> 30C5<> TP_VESTA_REGSEN1 18A3< VCORE_VID_A<1> 36C2< 36D3< 36D4<
LVDS_L0_P 7C7> 53A7> 53D1> 56C5<> MAXBUS_WT_L 9C3> 32B5< 32C6> 33C1> PP1V5_PWRON 10A5<> RAM_BA<2> 39B7< 40C6<> 41C6<> RAM_DATA_B<54> 41A6<> SYS_POWER_UP_L 26D6<> TP_VESTA_REGSEN2 18A3< VCORE_VID_A<2> 36C2< 36D3< 36D4<
B LVDS_L1_N
LVDS_L1_P
LVDS_L2_N
7C7> 53A7> 53D1> 56C5<>
7C7> 53A7> 53D1> 56C5<>
7C7> 53A7> 53D1> 56B5<>
MM3120_SW 28B4<>
MMM_ACC_PWRDOWN 25A7> 29C6<>
MMM_ACC_SELFTEST 25A7> 29C6<>
PP1V5_PWRON_I2PLL 10D2
PP1V5_PWRON_I2_PLL1AVDD 19C4<
PP1V5_PWRON_I2_PLL2AVDD 19C4<
RAM_BA_R<0>
RAM_BA_R<2..0>
RAM_BA_R<1>
39C8<
38C3> 38D6>
39B8<
RAM_DATA_B<55>
RAM_DATA_B<56>
RAM_DATA_B<57>
41A4<>
41A4<>
41A6<>
SYS_PWRSEQ_1
SYS_PWRSEQ_1_L
SYS_PWRSEQ_2
11B2< 26D8<>
26D4<>
11B2< 26D8<>
TP_VESTA_REGSUP1 18A3<
TP_VESTA_REGSUP2 18A3<
TP_VESTA_RGMIIEN 66B6<
VCORE_VID_A<3>
VCORE_VID_A<4>
VCORE_VID_B<1>
36C2< 36D3< 36D4<
36C2< 36D3< 36D4<
36D3< 36D3<
B
LVDS_L2_P 7C7> 53A7> 53D1> 56B5<> MMM_FFIRQ_L 22B6< 22C5< 25A7> PP1V5_PWRON_I2_PLL3AVDD 19C4< RAM_BA_R<2> 39B8< RAM_DATA_B<58> 41A4<> SYS_PWRSEQ_2_L 26D6<> TP_VESTA_SPD0 66B6< VCORE_VID_B<2> 36D3< 36D3<
LVDS_U0_N 7C7> 53B7> 53D1> 56B5<> MMM_SIRQ_L 22B6< 22C5< 25A7> PP1V5_PWRON_I2_PLL4AVDD 19B4< RAM_CAS_L 39A6> 39B7< 40B6<> 41B6<> RAM_DATA_B<59> 41A6<> SYS_PWRSEQ_3_L 11B2< 26C8<> TP_VESTA_TDBL<0> 69C2> VCORE_VID_B<3> 36D3< 36D3<
LVDS_U0_P 7C7> 53B7> 53D1> 56B5<> MMM_X_AXIS 25A7> 29C3<> 29D6> PP1V5_PWRON_I2_PLL5AVDD 19B4< RAM_CAS_L_R 38B3> 38D6> 39B8< RAM_DATA_B<60> 41A6<> SYS_PWRSEQ_3_LS5 26C7<> TP_VESTA_TDBL<1> 69C2> VCORE_VID_B<4> 36D3< 36D3<
LVDS_U1_N 7C7> 53B7> 53D1> 56B5<> MMM_Y_AXIS 25A7> 29C3<> 29D6> PP1V5_PWRON_I2_PLL6AVDD 19B4< RAM_CKE<0> 39B4> 40C6<> RAM_DATA_B<61> 41A6<> SYS_PWRSEQ_4 11B2< 26B8<> TP_VESTA_TDBL<2> 69C2> VESTA1V2_ITH 18C3<>
LVDS_U1_P 7C7> 53B7> 53D1> 56B5<> MMM_Z_AXIS 25A7> 29B3<> 29D6> PP1V5_PWRON_I2_PLL7AVDD 19A4< RAM_CKE<3..0> 39A6> RAM_DATA_B<62> 41A4<> SYS_PWRSEQ_5 11B2< 26B8<> TP_VESTA_TEST<0> 66B6< VESTA1V2_ITH_RC 18C3<
LVDS_U2_N 7C7> 53B7> 53D1> 56B5<> MODEM_RESET_L 22C5< 30A4<> PP1V5_PWRON_I2_PLL9AVDD 19A4< RAM_CKE<1> 39B4> 40C4<> RAM_DATA_B<63> 41A4<> SYS_PWRSEQ_6_L 11B2< 26A8<> TP_VESTA_TEST<1> 66B6< VESTA1V2_MODE 18C4<>
LVDS_U2_P 7C7> 53B7> 53D1> 56B5<> MODEM_RING2SYS_L 22B6< 22D5< 25C5<> 30A4<> PP1V5_PWRON_I2_PLLUSBAVDD 72C5< RAM_CKE<2> 39B4> 41C6<> RAM_DATA_R<7..0> 38C6> SYS_PWRSEQ_6_LS5 26A7<> TP_VESTA_TEST_1394<0> 69B5< VESTA1V2_RT 18C4<>
MAX1715_EN_L_RC 16C7<> MUTE_CONTROL 22B1<> 22C6<> PP1V5_PWRON_REG 10A6< RAM_CKE<3> 39B4> 41C4<> RAM_DATA_R<63..0> 38D6<> 39B6< SYS_PWRSEQ_FINAL 11A2< 26A8<> TP_VESTA_TEST_1394<1> 69B5< VESTA1V2_SGND 18B3<>
MAX1715_GND 16B5<> 16C5< NB_SUSPENDACK_L 22A2< 25C5<> PP1V5_RUN 10A2 RAM_CKE_R<0> 39B6< RAM_DATA_R<15..8> 38C6> SYS_PWRSEQ_TPAD_L 11B2< 26C5< TP_VESTA_TVCO 66A6<> VESTA1V2_SW 18C3<>
MAX1715_ON 16D6< NB_SUSPENDREQ_L 22A5< 25A7< 25C5<> PP1V8R2V5_GPU_FB_VIO 47C6< RAM_CKE_R<1..0> 38D6> RAM_DATA_R<23..16> 38C6> SYS_RESET_BUTTON_L 24B2< 25B7< 25C5<> 36A3<> TP_VESTA_TVCO_24 69B5<> VESTA1V2_VFB 18C3<>
MAX1715_REF 16B5<> NC_FW_TPA_N2 70B6> PP1V8_GPU 10A7< RAM_CKE_R<3..0> 38B3> RAM_DATA_R<31..24> 38C6> SYS_SLEEP 25A7< 25B5<> TP_VESTA_TXC_RXC_DELAY 66B3<> VESTA2V5_NOISE 18D2<>
MAX1715_SKIP 16C4< NC_FW_TPA_P2 70B6> PP1V8_GPU_A2VDDQ 53A2< RAM_CKE_R<1> 39B6< RAM_DATA_R<39..32> 38C6> SYS_WARM_RESET_L 22A2<> 22A5< 25A7< 25C2<> 62A7< TP_VESTA_XMTLED_L 66A3> VESTA3V3_SW 18D4<>
MAX1715_TON 16C5< NC_FW_TPBIAS2 70B6> PP1V8_GPU_AVDD 53C2< RAM_CKE_R<2> 39B6< RAM_DATA_R<47..40> 38C6> SYS_WATCHDOG 22A2< 25B5<> TV_C 53C1> 57A7<> VESTA_BILINGUAL_EN12_L 69A6< 69C5<
MAX4172_OUT 13D5<> NC_MAXBUS_CPU1_QACK_L 11A4> PP1V8_GPU_LVDS_PLL 47B2< RAM_CKE_R<3..2> 38D6> RAM_DATA_R<55..48> 38C6> TBEN_SYNC_CLR_L 21A4<> TV_COMP 53C1> 57A7<> VESTA_CLK24M_XTALI 69B5< 69D6>
MAX8860_CC 52B3<> NC_MAXBUS_TBEN_I2 6B8< PP1V8_GPU_MEMPLL 51C3< RAM_CKE_R<3> 39B6< RAM_DATA_R<63..56> 38B6> TBEN_SYNC_F1 21B4<> TV_Y 53C1> 57A7<> VESTA_CLK24M_XTALO 69A4< 69D6>
MAX8860_FAULT_L 52B3<> NEC_CLK30M_XT1 73A5< 73D7> PP1V8_GPU_PANEL_IO 47B1< 53C4< RAM_CLKDDR_0_N 39A6> 39D4> 40D4<> RAM_DQM<7..0> 39A6> 39B6 TBEN_SYNC_F2 21B3<> UATA_CS0_L 6C6> 7B7> 63D6> 64B2<> 64B7<> VESTA_CLK24M_XTALO_R 69B5<> 69D6>
MAXBUS_AACK_L 6B8< 32D3< 32D6> 33C1< NEC_CLK30M_XT2 73A5< 73D7> PP1V8_GPU_PLL 51C3< RAM_CLKDDR_0_N_R 38A3> 38D6> 39D6< RAM_DQM_A<0> 40D4<> THERM1_A_N 27B6< 27B8< 27D6> UATA_CS0_L_R 6C8< 63B3< 63D6> VESTA_CLK25M_XTALI 66A6< 66D6>
MAXBUS_ADDR<0> 32C5< 33C3<> NEC_CLK30M_XT2_R 73A5<> 73D7> PP1V8_GPU_PSNECK 52D3<> RAM_CLKDDR_0_P 39A6> 39D4> 40D4<> RAM_DQM_A<7..0> 39B5> THERM1_A_P 27B6< 27B8< 27D6> UATA_CS1_L 7B7> 63B1> 63D6> 64B4<> 64B5<> VESTA_CLK25M_XTALO 66A5< 66D6>
MAXBUS_ADDR<31..0> 9C3> 32D6> NEC_CRUN_L_PD 62A5<> PP1V8_GPU_PVDD 26A6<> 51D2<> RAM_CLKDDR_0_P_R 38B3> 38D6> 39D6< RAM_DQM_A<1> 40D4<> THERM1_M_N 27C6< 27C8< 27D6> UATA_CS1_L_R 63B2< 63B3< 63D6> VESTA_CLK25M_XTALO_R 66A6<> 66D6>
MAXBUS_ADDR<1> 32C5< 33C3<> NEC_INTA_L 62B5<> PP1V8_GPU_TPVDD 53C5< RAM_CLKDDR_1_N 39A6> 39D4> 40A4<> RAM_DQM_A<2> 40C4<> THERM1_M_P 27C6< 27C8< 27D6> UATA_DA<0> 6C6> 64B2<> 64B7<> VESTA_CPS 69C5<>
MAXBUS_ADDR<2> 32C5< 33C3<> NEC_INTB_L 62B5<> PP1V8_GPU_VDDDI 53B2< RAM_CLKDDR_1_N_R 38A3> 38D6> 39D6< RAM_DQM_A<3> 40C6<> THERM2_A_N 27A8< 27B6< 27D6> UATA_DA<2..0> 7B7> 63D6> VESTA_DS_ONLY_EN0 69A6< 69B5<
MAXBUS_ADDR<3> 32C5< 33C3<> NEC_INTC_L 62B5<> PP1V8_GPU_VDD_MEM_CLK 47A4< RAM_CLKDDR_1_P 39A6> 39D4> 40A4<> RAM_DQM_A<4> 40B4<> THERM2_A_P 27B6< 27B8< 27D6> UATA_DA<1> 6B6> 64B2<> 64B7<> VESTA_ENET_LOWPWR 66B6<>
MAXBUS_ADDR<4> 32C5< 33C3<> NEC_LEGC_PD 62A5< PP1V8_PWRON 7C7> 10A5<> RAM_CLKDDR_1_P_R 38A3> 38D6> 39D6< RAM_DQM_A<5> 40B6<> THERM2_M_N 27B8< 27C6< 27D6> UATA_DA<2> 6C6> 64B4<> 64B5<> VESTA_LPWR_1394 69B5<
MAXBUS_ADDR<5> 32C5< 33C3<> NEC_NC1_PU 73A5<> PP1V8_PWRON_REG 10A6< RAM_CLKDDR_2_N 39A6> 39C4> 41D4<> RAM_DQM_A<6> 40A4<> THERM2_M_P 27C6< 27C8< 27D6> UATA_DASP_L 64B2<> 64B5<> VESTA_PORT1_DISABLE_L 69A6< 69C5<
MAXBUS_ADDR<6> 32C5< 33C3<> NEC_NC2_PU 73A5<> PP1V8_RUN 10A2 RAM_CLKDDR_2_N_R 38A3> 38D6> 39C6< RAM_DQM_A<7> 40A6<> THERM_D1_N 27B5< 27C4<> 27C5< 27D6> UATA_DA_R<0> 6C8< VESTA_PORT2_DISABLE_L 69A6< 69C5<
MAXBUS_ADDR<7> 32C5< 33C3<> NEC_PERR_L_PU 62B5<> PP1VR1V3_GPU_VDDCI 46C2< RAM_CLKDDR_2_P 39A6> 39D4> 41D4<> RAM_DQM_B<0> 41D4<> THERM_D1_P 27B5< 27C4<> 27C5< 27D6> UATA_DA_R<2..0> 63B3> 63D6> VESTA_PWR_CLASS_MSB 69A6< 69B5<
MAXBUS_ADDR<8> 32C5< 33C3<> NEC_PME_L 62A5<> PP2V5R2V8_GPU_LVDS_IO 47B2< RAM_CLKDDR_2_P_R 38A3> 38D6> 39D6< RAM_DQM_B<7..0> 39B5> THERM_D2_N 27B5< 27C4<> 27C5< 27D6> UATA_DA_R<1> 6B8< VESTA_RDAC1_PD 66A4<>
MAXBUS_ADDR<9> 32C5< 33C3<> NEC_RREF_PD 73A3<> PP2V5_ENET_CTAP 67C5<> RAM_CLKDDR_3_N 39A6> 39C4> 41A4<> RAM_DQM_B<1> 41D4<> THERM_D2_P 27B5< 27C4<> 27C5< 27D6> UATA_DA_R<2> 6C8< VESTA_RDAC2_PD 69B3<>
MAXBUS_ADDR<10> 32C5< 33C3<> NEC_SERR_L_PU 62B5<> PP2V5_GPU 10B7< RAM_CLKDDR_3_N_R 38A3> 38D6> 39C6< RAM_DQM_B<2> 41C4<> TMDS_CLKN 54B1> 54D2< 54D5< 57C6<> UATA_DD<0> 6C6> 64B2<> 64C7<> VESTA_RESET 18A7<> 66B8<
MAXBUS_ADDR<11> 32C5< 33C3<> NEC_VBBRST_L 62A5< PP2V5_GPU_A2VDD 53B2< RAM_CLKDDR_3_P 39A6> 39C4> 41A4<> RAM_DQM_B<3> 41C6<> TMDS_CLKP 54B1> 54D3< 54D5< 57C6<> UATA_DD<15..0> 7B7> 63D6> VESTA_RESET_L 18A6<>
MAXBUS_ADDR<12> 32C5< 33C3<> NEC_VCCRST_L 62A5< PP2V5_GPU_PSNECK 52D3<> RAM_CLKDDR_3_P_R 38A3> 38D6> 39C6< RAM_DQM_B<4> 41B4<> TMDS_CONN_CLKN 57C4<> 57C5<> 57D6> UATA_DD<1> 6B6> 64B2<> 64C7<> VESTA_RESET_L_RC 18A7<>
MAXBUS_ADDR<13> 32C5< 33C3<> OVER_18V_ADJ 13C3<> PP2V5_PWRON 7C7> 10A5<> RAM_CS_L<0> 39C4> 40B4<> RAM_DQM_B<5> 41B6<> TMDS_CONN_CLKP 57C4<> 57C5<> 57D6> UATA_DD<2> 6C6> 64B2<> 64C7<> VGA_B 53C1> 57C4<> 57C6<
MAXBUS_ADDR<14> 32C5< 33C3<> PANEL_PWR_EN 53B8<> 56B4<> 56C8< PP2V5_PWRON_REG 10A6< RAM_CS_L<3..0> 39A6> RAM_DQM_B<6> 41A4<> TMDS_CONN_DN<0> 57D4<> 57D5<> 57D6> UATA_DD<3> 6C6> 64C2<> 64C7<> VGA_G 53C1> 57C3<> 57C6<
MAXBUS_ADDR<15> 32C5< 33C3<> PCI1510_VR_EN_L 61C7< PP2V5_RUN 10B2 RAM_CS_L<1> 39C4> 40B6<> RAM_DQM_B<7> 41A6<> TMDS_CONN_DN<1> 57D3<> 57D5<> 57D6> UATA_DD<4> 6C6> 64C2<> 64C7<> VGA_HSYNC 57B1< 57C4<>
MAXBUS_ADDR<16> 32C5< 33C3<> PCI_AD<0> 59C3< 60B5<> 61C7<> 62D5<> PP2V5_VESTA 10D5 RAM_CS_L<2> 39C4> 41B4<> RAM_DQM_R<0> 38C6> TMDS_CONN_DN<2> 57D3<> 57D5<> 57D6> UATA_DD<5> 6C6> 64C2<> 64C7<> VGA_R 53C1> 57B6< 57C3<>
MAXBUS_ADDR<17> 32C5< 33B3<> PCI_AD<16..0> 59D6> PP2V5_VESTA_BIASVDD1 66D4< RAM_CS_L<3> 39C4> 41B6<> RAM_DQM_R<7..0> 38B3> 39B6< TMDS_CONN_DN<3> 57C3<> 57C5<> 57D6> UATA_DD<6> 6C6> 64C2<> 64C7<> VGA_VSYNC 57C1< 57C3<>
MAXBUS_ADDR<18> 32C5< 33B3<> PCI_AD<20..0> 58C5<> PP2V5_VESTA_BIASVDD2 69D4< RAM_CS_L_R<0> 39C6< RAM_DQM_R<1> 38C6> TMDS_CONN_DN<4> 57C3<> 57C5<> 57D6> UATA_DD<7> 6C6> 64C2<> 64C7<> VIA_ACK_L 22B5< 25B2<>
MAXBUS_ADDR<19> 32C5< 33B3<> PCI_AD<1> 59C3< 60B5<> 61C7<> 62C5<> PP2V5_VESTA_FAVDDM 69D2< RAM_CS_L_R<1..0> 38D6> RAM_DQM_R<2> 38C6> TMDS_CONN_DN<5> 57B5<> 57C4<> 57D6> UATA_DD<8> 6C6> 64C4<> 64C5<> VIA_CLK 22B5< 25B2<>
MAXBUS_ADDR<20> 32C5< 33B3<> PCI_AD<2> 59C3< 60B3<> 61C7<> 62C5<> PP2V5_VESTA_XTALVDD1 66D4< RAM_CS_L_R<3..0> 38C3> RAM_DQM_R<3> 38C6> TMDS_CONN_DP<0> 57D4<> 57D5<> 57D6> UATA_DD<9> 6C6> 64C4<> 64C5<> VIA_PMU_TO_SB 22B5< 25B2<>
MAXBUS_ADDR<21> 32C5< 33B3<> PCI_AD<3> 59C3< 60B5<> 61C7<> 62C5<> PP2V5_VESTA_XTALVDD2 69C4< RAM_CS_L_R<1> 39C6< RAM_DQM_R<4> 38C6> TMDS_CONN_DP<1> 57D3<> 57D5<> 57D6> UATA_DD<10> 6C6> 64C4<> 64C5<> VIA_REQ_L 22B2< 25B2<> 25B7<
A MAXBUS_ADDR<22> 32C5< 33B3<>

MAXBUS_ADDR<23> 32C5< 33B3<>
MAXBUS_ADDR<24> 32C5< 33B3<>
PCI_AD<4>
PCI_AD<5>
PCI_AD<6>
59C3< 60B3<> 61C7<>
59C3< 60B5<> 61C7<>
59C3< 60B5<> 61C7<>
62C5<>
62C5<>
62C5<>
PP2V8_GPU_LVDDR 10B7
PP3V3R5V_RUN_HDD_LOGIC 7B7> 64B7<>
PP3V3_ADT7467 27D3<
RAM_CS_L_R<2>
RAM_CS_L_R<3>
39C6<
RAM_CS_L_R<3..2> 38D6>
39C6<
RAM_DQM_R<5>
RAM_DQM_R<6>
RAM_DQM_R<7>
38C6>
38C6>
38C6>
TMDS_CONN_DP<2>
TMDS_CONN_DP<3>
TMDS_CONN_DP<4>
57C5<> 57D3<> 57D6>
57C3<> 57C5<> 57D6>
57C3<> 57C5<> 57D6>
UATA_DD<11>
UATA_DD<12>
UATA_DD<13>
6C6> 64C4<>
6C6> 64C4<>
6C6> 64B4<>
64C5<>
64C5<>
64C5<>
VIA_SB_TO_PMU
VID_MUX_OE_L
22B2< 25B2<>
36D3<>

A
MAXBUS_ADDR<25> 32B5< 33B3<> PCI_AD<7> 59B3< 60B5<> 61C7<> 62C5<> PP3V3_ALL 7C7> 10C7 RAM_DATA<63..0> 39A6> 39B6 RAM_DQS<7..0> 39A6> 39B6 TMDS_CONN_DP<5> 57B5<> 57C4<> 57D6> UATA_DD<14> 6C6> 64B4<> 64C5<>
MAXBUS_ADDR<26> 32B5< 33B3<> PCI_AD<8> 59B3< 60B5<> 61C7<> 62C5<> PP3V3_ALL_ESR 14A2< RAM_DATA_A<0> 40D6<> RAM_DQS_A_N<0> 39B5< 40D6<> TMDS_D3_CMF 55C1< UATA_DD<15> 6C6> 64B4<> 64C5<>
MAXBUS_ADDR<27> 32B5< 33B3<> PCI_AD<9> 59B3< 60B5<> 61C7<> 62C5<> PP3V3_ALL_HALL_EFFECT_R 7C5> 30D5<> RAM_DATA_A<63..0> 39B5> RAM_DQS_A_N<1> 39A5< 40D6<> TMDS_D4_CMF 55C1< UATA_DD_R<0> 6C8< THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
MAXBUS_ADDR<28> 32B5< 33B3<> PCI_AD<10> 59B3< 60B3<> 61C7<> 62C5<> PP3V3_ALL_PMU_AVCC 10B7< 25D3< RAM_DATA_A<1> 40D4<> RAM_DQS_A_N<2> 39A5< 40C6<> TMDS_D5_CMF 55B1< UATA_DD_R<6..0> 63D6> PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
MAXBUS_ADDR<29> 32B5< 33B3<> PCI_AD<11> 59B3< 60B3<> 61C7<> 62C5<> PP3V3_FW_ESD 70A6<> 70B5<> 70D5<> RAM_DATA_A<2> 40D4<> RAM_DQS_A_N<3> 39A5< 40C4<> TMDS_DN<0> 54B1> 54D1< 54D5< 57D6<> UATA_DD_R<15..0> 63C3> AGREES TO THE FOLLOWING
MAXBUS_ADDR<30> 32B5< 33B3<> PCI_AD<12> 59B3< 60B5<> 61C7<> 62C5<> PP3V3_FW_ESD_F 70A7< RAM_DATA_A<3> 40D6<> RAM_DQS_A_N<4> 39A5< 40B6<> TMDS_DN<1> 54B1> 54D2< 54D4< 57D6<> UATA_DD_R<1> 6B8< I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
MAXBUS_ADDR<31> 32B5< 33B3<> PCI_AD<13> 59B3< 60B3<> 61C7<> 62C5<> PP3V3_GPU 10B7< RAM_DATA_A<4> 40D6<> RAM_DQS_A_N<5> 39A5< 40B4<> TMDS_DN<2> 54B1> 54C1< 54D4< 57D6<> UATA_DD_R<2> 6C8<
MAXBUS_ARTRY_L 6A8< 32C6> 32D5< 33C1<> PCI_AD<14> 59B3< 60B3<> 61C7<> 62C5<> PP3V3_GPU_OSC 52C6< RAM_DATA_A<5> 40D4<> RAM_DQS_A_N<6> 39A5< 40A6<> TMDS_DN<3> 55C1< 55C6> 55D1< 57C6<> UATA_DD_R<3> 6C8< II NOT TO REPRODUCE OR COPY IT
MAXBUS_CI_L 9C3> 32B5< 32C6> 33C1> PCI_AD<15> 59B3< 60B3<> 61C7<> 62C5<> PP3V3_GPU_PSNECK 52D2<> RAM_DATA_A<6> 40D6<> RAM_DQS_A_N<7> 39A5< 40A4<> TMDS_DN<4> 55B1< 55C6> 55D1< 57C6<> UATA_DD_R<4> 6C8<
MAXBUS_CLK_CPU0 11D5< PCI_AD<16> 59B3< 60B3<> 61C7<> 62C5<> PP3V3_GPU_SS 52B6< RAM_DATA_A<7> 40D4<> RAM_DQS_A_P<0> 40D6<> TMDS_DN<5> 55B1< 55C6> 55D1< 57B6<> UATA_DD_R<5> 6C8<
MAXBUS_CLK_CPU0_R 11D6< 32D3< 32D6> PCI_AD<17> 11C2< 59B3< 59D6> 60C3<> 61C7<> PP3V3_GPU_VDDR3 47D3< 51B6< RAM_DATA_A<8> 40D4<> RAM_DQS_A_P<7..0> 39B5> TMDS_DP<0> 54B1> 54D2< 54D5< 57D6<> UATA_DD_R<6> 6C8<
MAXBUS_CLK_CPU1_R 11D6< 62C5<> PP3V3_LCD_CONN 7B7> 56C5<> RAM_DATA_A<9> 40D6<> RAM_DQS_A_P<1> 40D6<> TMDS_DP<1> 54B1> 54D3< 54D4< 57D6<> UATA_DD_R<7> 6C8< 63D6> SIZE DRAWING NUMBER REV.
MAXBUS_CLK_TBEN_SYNC 11D5< PCI_AD<18> 59B3< 60B5<> 61B7<> 62C5<> PP3V3_LCD_SW 56C6<> RAM_DATA_A<10> 40D6<> RAM_DQS_A_P<2> 40C6<> TMDS_DP<2> 54B1> 54C2< 54D4< 57C6<> UATA_DD_R<8> 6C8<
MAXBUS_CPU0_BG_L 6B8< 32C6> 32D3< 33C3<
MAXBUS_CPU0_BR_L 6B8< 32C6> 32D5< 33C3>
MAXBUS_CPU0_DBG_L 6B8< 32C6> 32D3< 33D4<
PCI_AD<19..18>
PCI_AD<19>
59D6>
59B3< 60C5<> 61B7<> 62C5<>
PP3V3_PWRON 7C7> 10B5<>
PP3V3_PWRON_AUDIO_AVDD 7A7> 74B6<>
PP3V3_PWRON_DS1775_R 7D5> 30D5<>
RAM_DATA_A<11>
RAM_DATA_A<12>
RAM_DATA_A<13>
40D4<>
40D4<>
40D4<>
RAM_DQS_A_P<3>
RAM_DQS_A_P<4>
RAM_DQS_A_P<5>
40C4<>
40B6<>
40B4<>
TMDS_DP<3>
TMDS_DP<4>
TMDS_DP<5>
55C2<
55B2<
55C6>
55C6>
55D1<
55D1<
55B2< 55C1< 55C6> 57B6<>
57C6<>
57C6<>
UATA_DD_R<15..8>
UATA_DD_R<9>
UATA_DD_R<10>
63D6>
6C8<
6C8< APPLE COMPUTER INC.
D 051-6839 F
SCALE SHT OF
NONE 113 115 113
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
*** Part Cross-Reference for the entire design *** C1991 CAP 18 C3565 CAP 32 C4764 CAP 38 C6023 CAP 47 C6607 CAP 53 C9325 CAP 73 L9020 IND 70 R1330 RES 13
C1992 CAP 18 C3566 CAP 32 C4765 CAP 38 C6024 CAP 47 C6610 CAP 53 C9326 CAP 73 L9090 IND 70 R1340 RES 13
BS0200 PCB_STANDOFF 2 C1993 CAP 18 C3567 CAP 32 C4766 CAP 38 C6025 CAP 47 C6611 CAP 53 C9327 CAP 73 L9335 IND 73 R1341 RES 13
C1200 CAP 12 C1994 CAP 18 C3568 CAP 32 C4767 CAP 38 C6026 CAP 47 C6615 CAP 53 C9328 CAP 73 PD3100 PHOTODIODE_2P 28 R1342 RES 13
C1210 CAP 12 C1995 CAP 18 C3569 CAP 32 C4768 CAP 38 C6027 CAP 47 C6616 CAP 53 C9329 CAP 73 Q1208 TRA_2N7002DW 12 R1343 RES 13
C1220 CAP 12 C2101 CAP 19 C3570 CAP 32 C4769 CAP 38 C6028 CAP 47 C6617 CAP 53 C9330 CAP 73 Q1210 TRA_IRF7416 12 R1344 RES 13
C1252 CAP 12 C2103 CAP 19 C3572 CAP 32 C4771 CAP 38 C6030 CAP 47 C6621 CAP 53 C9336 CAP 73 Q1220 TRA_2N7002 12 R1346 RES 13
C1301 CAP 13 C2104 CAP 19 C3573 CAP 32 C4772 CAP 38 C6031 CAP 47 C6622 CAP 53 C9337 CAP 73 Q1300 TRA_RLA130 13 R1347 RES 13
C1302 CAP 13 C2105 CAP 19 C3574 CAP 32 C4773 CAP 38 C6032 CAP 47 C6625 CAP 53 C9345 CAP 73 Q1301 TRA_IRF7811W 13 R1348 RES 13
C1305 CAP 13 C2107 CAP 19 C3576 CAP 32 C4775 CAP 38 C6040 CAP 47 C6720 CAP 54 CA010 CAP 74 Q1340 TRA_2N7002DW 13 R1352 RES 13
C1308 CAP 13 C2121 CAP 19 C3579 CAP 32 C4778 CAP 38 C6043 CAP 47 C6723 CAP 54 CA050 CAP 74 Q1360 TRA_IRF7416 13 R1360 RES 13
C1310 CAP 13 C2123 CAP 19 C3581 CAP 32 C4780 CAP 38 C6045 CAP 47 C6725 CAP 54 D1300 DIODE_SCHOT 13 Q1390 TRA_IRF7416 13 R1370 RES 13
C1311 CAP_P 13 C2124 CAP 19 C3582 CAP 32 C4781 CAP 38 C6046 CAP 47 C6726 CAP 54 D1303 DIODE 13 Q1392 TRA_2N7002DW 13 R1380 RES 13
D
C1312
C1313
C1314
CAP
CAP
CAP
13
13
13
C2125
C2126
C2127
CAP
CAP
CAP
19
19
19
C3583
C3584
C3585
CAP
CAP
CAP
32
32
32
C4782
C4783
C4784
CAP
CAP
CAP
38
38
38
C6047
C6048
C6049
CAP
CAP
CAP
47
47
47
C6727
C6728
C6729
CAP
CAP
CAP
54
54
54
D1319
D1400
D1410
DIODE 13
DIODE_SCHOT 14
DIODE_SCHOT 14
Q1395
Q1400
Q1401
TRA_SUD45P03 13
TRA_RLA130 14
TRA_IRF7811W 14
R1381
R1382
R1383
RES
RES
RES
13
13
13
D
C1315 CAP 13 C2128 CAP 19 C3586 CAP 32 C4785 CAP 38 C6050 CAP 47 C6740 CAP 54 D1420 DIODE 14 Q1430 TRA_FDG6324L 14 R1384 RES 13
C1316 CAP 13 C2129 CAP 19 C3587 CAP 32 C4786 CAP 38 C6051 CAP 47 C6760 CAP 54 D1450 DIODE_SCHOT 14 Q1501 TRA_RLA130 15 R1385 RES 13
C1317 CAP 13 C2130 CAP 19 C3588 CAP 32 C4787 CAP 38 C6052 CAP 47 C6762 CAP 54 D1451 DIODE 14 Q1502 TRA_IRF7811W 15 R1386 RES 13
C1319 CAP 13 C2131 CAP 19 C3589 CAP 32 C4788 CAP 38 C6053 CAP 47 C6764 CAP 54 D1452 DIODE_SCHOT 14 Q1533 TRA_2N7002 15 R1387 RES 13
C1320 CAP 13 C2132 CAP 19 C3590 CAP 32 C4789 CAP 38 C6054 CAP 47 C6766 CAP 54 D1460 DIODE_SCHOT 14 Q1535 TRA_SI3443DV 15 R1390 RES 13
C1322 CAP 13 C2134 CAP 19 C3600 CAP 33 C4791 CAP 38 C6056 CAP 47 C6802 CAP 55 D1501 DIODE_SCHOT 15 Q1552 TRA_IRF7811W 15 R1392 RES 13
C1324 CAP 13 C2136 CAP 19 C3671 CAP 33 C4793 CAP 38 C6058 CAP 47 C6830 CAP 55 D1533 DIODE 15 Q1585 TRA_SI3443DV 15 R1396 RES 13
C1327 CAP 13 C2139 CAP 19 C3674 CAP 33 C4796 CAP 38 C6061 CAP 47 C6833 CAP 55 D1601 DIODE_SCHOT 16 Q1602 TRA_IRF7805 16 R1410 RES 14
C1361 CAP 13 C2142 CAP 19 C3677 CAP 33 C5008 CAP 40 C6064 CAP 47 C6836 CAP 55 D1970 DIO_MBRM140T3_SM 18 Q1652 TRA_IRF7805 16 R1420 RES 14
C1370 CAP 13 C2143 CAP 19 C3678 CAP 33 C5009 CAP 40 C6065 CAP 47 C6837 CAP 55 D1975 DIODE_SCHOT_3P2 18 Q1680 TRA_SI6467BDQ 16 R1421 RES 14
C1371 CAP 13 C2144 CAP 19 C3679 CAP 33 C5010 CAP 40 C6066 CAP 47 C6838 CAP 55 D2710 DIODE 25 Q1685 TRA_SI3446DV 16 R1422 RES 14
C1380 CAP 13 C2146 CAP 19 C3680 CAP 33 C5011 CAP 40 C6067 CAP 47 C6839 CAP 55 D3900 DIODE_3P_C 36 Q1740 TRA_2N7002DW 17 R1425 RES 14
C1384 CAP 13 C2147 CAP 19 C3681 CAP 33 C5012 CAP 40 C6068 CAP 47 C6900 CAP 56 D3901 DIODE_SCHOT 36 Q1780 TRA_SI6467BDQ 17 R1427 RES 14
C1386 CAP 13 C2148 CAP 19 C3682 CAP 33 C5013 CAP 40 C6069 CAP 47 C6901 CAP 56 D4610 DIODE_SCHOT 37 Q1950 TRA_2N7002DW 18 R1430 RES 14
C1400 CAP 14 C2150 CAP 19 C3684 CAP 33 C5015 CAP 40 C6071 CAP 47 C6911 CAP 56 D5823 DIODE_SCHOT 45 Q1965 TRA_NDS9407 18 R1451 RES 14
C1401 CAP 14 C2151 CAP 19 C3685 CAP 33 C5016 CAP 40 C6072 CAP 47 C6920 CAP 56 D7010 DIODE_SCHOT 57 Q2470 TRA_2N7002DW 22 R1452 RES 14
C1402 CAP 14 C2152 CAP 19 C3686 CAP 33 C5017 CAP 40 C6073 CAP 47 C6921 CAP 56 D9090 ZENER 70 Q2480 TRA_2N7002DW 22 R1453 RES 14
C1403 CAP 14 C2153 CAP 19 C3687 CAP 33 C5018 CAP 40 C6074 CAP 47 C6950 CAP 56 DP1390 DPAK3P 13 Q2481 TRA_2N7002DW 22 R1461 RES 14
C1404 CAP 14 C2154 CAP 19 C3688 CAP 33 C5019 CAP 40 C6075 CAP 47 C6951 CAP 56 DP1620 DPAK3P 16 Q2600 TRA_2N3906 24 R1501 RES 15
C1405 CAP 14 C2155 CAP 19 C3689 CAP 33 C5020 CAP 40 C6076 CAP 47 C6952 CAP 56 DP1960 DPAK3P 18 Q2601 TRA_2N7002 24 R1502 RES 15
C1408 CAP 14 C2158 CAP 19 C3692 CAP 33 C5023 CAP 40 C6079 CAP 47 C6955 CAP 56 DP9010 DIODE_DUAL_6P 70 Q2910 TRA_2N7002DW 26 R1505 RES 15
C1412 CAP 14 C2161 CAP 19 C3695 CAP 33 C5209 CAP 41 C6082 CAP 47 C7011 CAP 57 DP9021 DIODE_DUAL_6P 70 Q2948 TRA_2N7002 26 R1512 RES 15
C1420 CAP 14 C2162 CAP 19 C3698 CAP 33 C5210 CAP 41 C6083 CAP 47 C7013 CAP 57 F1390 FUSE 13 Q3001 TRA_2N3904 27 R1530 RES 15
C1427 CAP 14 C2166 CAP 19 C3802 CAP 35 C5214 CAP 41 C6087 CAP 47 C7042 CAP 57 F9020 FUSE 70 Q3103 TRA_2N7002DW 28 R1535 RES 15
C1450 CAP 14 C2167 CAP 19 C3803 CAP 35 C5215 CAP 41 C6088 CAP 47 C7050 CAP 57 FL7040 FILTER_LC 57 Q3900 TRA_HAT2168H 36 R1551 RES 15
C C1453
C1460
C1461
CAP
CAP
CAP
14
14
14
C2170
C2171
C2172
CAP
CAP
CAP
19
19
19
C3806
C3807
C3808
CAP
CAP
CAP
35
35
35
C5218
C5219
C5220
CAP
CAP
CAP
41
41
41
C6091
C6092
C6093
CAP
CAP
CAP
47
47
47
C7061
C7062
C7063
CAP
CAP
CAP
57
57
57
FL9010 FILTER_4P 70
FL9011 FILTER_4P 70
FL9020 FILTER_4P 70
Q3940
Q5800
Q5801
TRA_2N7002DW 36
TRA_SI7860DP 45
TRA_SI7892DP 45
R1554
R1555
R1560
RES
RES
RES
15
15
15
C
C1501 CAP 15 C2173 CAP 19 C3809 CAP 35 C5221 CAP 41 C6094 CAP 47 C7064 CAP 57 FL9021 FILTER_4P 70 Q5884 TRA_2N7002DW 45 R1561 RES 15
C1502 CAP 15 C2174 CAP 19 C3810 CAP 35 C5222 CAP 41 C6095 CAP 47 C7065 CAP 57 G6500 OSC 52 Q5950 TRA_SI3446DV 46 R1562 RES 15
C1503 CAP_P 15 C2175 CAP 19 C3811 CAP 35 C5223 CAP 41 C6096 CAP 47 C7066 CAP 57 J1250 CON_M8RT_S_SM 12 Q6900 TRA_SI3443DV 56 R1601 RES 16
C1504 CAP 15 C2176 CAP 19 C3812 CAP 35 C5649 CAP 43 C6097 CAP 47 C7067 CAP 57 J2690 CON_M16ST_D_SMA 24 Q6901 TRA_2N7002 56 R1602 RES 16
C1510 CAP 15 C2177 CAP 19 C3813 CAP 35 C5650 CAP 43 C6190 CAP 48 C7070 CAP 57 J3320 CON_M16ST_D_SMA 30 Q6950 TRA_FDG6324L 56 R1620 RES 16
C1511 CAP 15 C2178 CAP 19 C3814 CAP 35 C5651 CAP 43 C6191 CAP 48 C7079 CAP 57 J3350 CON_F14RT_S2MT_SM 30 Q7011 TRA_2N7002DW 57 R1621 RES 16
C1512 CAP 15 C2179 CAP 19 C3815 CAP 35 C5652 CAP 43 C6192 CAP 48 C7100 CAP 58 J3400 CON_M8RT_S_SM 31 Q7014 TRA_2N7002DW 57 R1630 RES 16
C1513 CAP 15 C2180 CAP 19 C3816 CAP 35 C5653 CAP 43 C6193 CAP 48 C7101 CAP 58 J3410 CON_F14RT_S2MT_SM 31 Q7075 TRA_TP0610 57 R1631 RES 16
C1514 CAP 15 C2181 CAP 19 C3817 CAP 35 C5654 CAP 43 C6200 CAP 49 C7102 CAP 58 J3430 CON_F14RT_S2MT_SM 31 Q7076 TRA_2N7002DW 57 R1632 RES 16
C1515 CAP 15 C2182 CAP 19 C3818 CAP 35 C5655 CAP 43 C6201 CAP 49 C7400 CAP 61 J3450 CON_4RT_WRIB 31 Q7080 TRA_DUAL_MMDT3904 57 R1633 RES 16
C1520 CAP 15 C2183 CAP 19 C3819 CAP 35 C5656 CAP 43 C6202 CAP 49 C7401 CAP 61 J3460 CON_4RT_WRIB 31 Q7081 TRA_TP0610 57 R1634 RES 16
C1521 CAP 15 C2184 CAP 19 C3820 CAP 35 C5657 CAP 43 C6203 CAP 49 C7402 CAP 61 J3999 CON_12 36 Q8420 TRA_2N7002DW 65 67 R1640 RES 16
C1522 CAP 15 C2185 CAP 19 C3821 CAP 35 C5658 CAP 43 C6204 CAP 49 C7403 CAP 61 J5000 CON_F200RT_DDR2DIMM_SM1 40 Q8580 TRA_2N7002DW 66 R1641 RES 16
C1523 CAP 15 C2186 CAP 19 C3822 CAP 35 C5659 CAP 43 C6210 CAP 49 C7404 CAP 61 J5200 CON_F200RT_DDR2DIMM_SM1 41 Q8620 TRA_SI6467BDQ 67 R1651 RES 16
C1530 CAP 15 C2187 CAP 19 C3823 CAP 35 C5660 CAP 43 C6211 CAP 49 C7405 CAP 61 J6900 CON_F30RT_S2MT_SM 56 R0820 RES 8 R1652 RES 16
C1531 CAP 15 C2188 CAP 19 C3830 CAP 35 C5661 CAP 43 C6212 CAP 49 C7406 CAP 61 J6950 CON_4RT_WRIB 56 R0821 RES 8 R1670 RES 16
C1532 CAP 15 C2189 CAP 19 C3831 CAP 35 C5662 CAP 43 C6213 CAP 49 C7407 CAP 61 J7000 CON_F30RT_T6MT_TH1 57 R0830 RES 8 R1671 RES 16
C1533 CAP 15 C2190 CAP 19 C3832 CAP 35 C5663 CAP 43 C6214 CAP 49 C7408 CAP 61 J7060 CON_F5RT_MINIDIN_TH 57 R0831 RES 8 R1680 RES 16
C1536 CAP 15 C2191 CAP 19 C3833 CAP 35 C5664 CAP 43 C6215 CAP 49 C7410 CAP 61 J7300 CON_M80ST_D2MT_SM3 60 R0840 RES 8 R1720 RES 17
C1551 CAP 15 C2192 CAP 19 C3834 CAP 35 C5665 CAP 43 C6216 CAP 49 C7411 CAP 61 J7490 CON_M80ST_D4MT_SM 61 R0841 RES 8 R1722 RES 17
C1552 CAP 15 C2193 CAP 19 C3835 CAP 35 C5666 CAP 43 C6217 CAP 49 C7450 CAP 61 J8200 CON_M50SM_5MM 64 R0842 RES 8 R1723 RES 17
C1553 CAP_P 15 C2194 CAP 19 C3836 CAP 35 C5667 CAP 43 C6218 CAP 49 C7451 CAP 61 J8250 CON_M50SM_5MM 64 R0843 RES 8 R1724 RES 17
C1554 CAP 15 C2195 CAP 19 C3837 CAP 35 C5668 CAP 43 C6219 CAP 49 C7490 CAP 61 J8600 CON_RJ45_SHORT_4MT_TH 67 R0850 RES 8 R1730 RES 17
C1560 CAP 15 C2196 CAP 19 C3838 CAP 35 C5669 CAP 43 C6220 CAP 49 C7491 CAP 61 J9010 CON_F9RT_1394B_S6MT_SMA 70 R0851 RES 8 R1731 RES 17
C1561 CAP 15 C2197 CAP 19 C3839 CAP 35 C5670 CAP 43 C6221 CAP 49 C7500 CAP 62 J9020 CON_F6RT_S4MT_TH1 70 R0950 RES 9 R1732 RES 17
C1562 CAP 15 C2199 CAP 19 C3840 CAP 35 C5671 CAP 43 C6241 CAP 49 C8166 CAP 63 JA000 CON_M40ST_D4MT_SM 74 R0980 RES 9 R1733 RES 17
C1563 CAP 15 C2200 CAP 20 C3841 CAP 35 C5672 CAP 43 C6245 CAP 49 C8450 CAP 65 L1250 IND 12 R0981 RES 9 R1950 RES 18
C1573 CAP 15 C2215 CAP 20 C3847 CAP 35 C5802 CAP_P 45 C6260 CAP 49 C8456 CAP 65 L1400 IND_3P 14 R1015 RES 10 R1965 RES 18
C1580 CAP 15 C2216 CAP 20 C3848 CAP 35 C5803 CAP_P 45 C6261 CAP 49 C8459 CAP 65 L1501 IND 15 R1018 RES 10 R1966 RES 18
C1582 CAP_P 15 C2254 CAP 20 C3850 CAP 35 C5805 CAP 45 C6263 CAP 49 C8501 CAP 66 L1601 IND 16 R1033 RES 10 R1991 RES 18
B C1592
C1601
C1602
CAP
CAP
CAP
15
16
16
C2411
C2500
C2501
CAP
CAP
CAP
22
23
23
C3856
C3857
C3858
CAP
CAP
CAP
35
35
35
C5824
C5825
C5830
CAP
CAP
CAP
45
45
45
C6269
C6270
C6271
CAP
CAP
CAP
49
49
49
C8580
C8590
C8592
CAP
CAP
CAP
66
66
66
L2200 IND
L3130 IND
L3350 IND
20
28
30
R1136
R1137
R1140
RES
RES
RES
11
11
11
R1997
R1998
R2101
RES
RES
RES
18
18
19
B
C1605 CAP_P 16 C2701 CAP 25 C3861 CAP 35 C5885 CAP 45 C6300 CAP 50 C8600 CAP 67 L3900 IND_3P 36 R1162 RES 11 R2104 RES 19
C1620 CAP 16 C2702 CAP 25 C3900 CAP 36 C5900 CAP 46 C6301 CAP 50 C8601 CAP 67 L5800 IND_3P 45 R1163 RES 11 R2105 RES 19
C1632 CAP 16 C2740 CAP 25 C3910 CAP_P 36 C5904 CAP 46 C6310 CAP 50 C8620 CAP 67 L6010 IND 47 R1167 RES 11 R2204 RES 20
C1653 CAP_P 16 C3000 CAP 27 C3914 CAP_P 36 C5908 CAP 46 C6314 CAP 50 C8904 CAP 69 L6041 IND 47 R1173 RES 11 R2209 RES 20
C1903 CAP 18 C3450 CAP_P 31 C3963 CAP 36 C5955 CAP 46 C6368 CAP 50 C9017 CAP 70 L6952 IND 56 R1225 RES 12 R2365 RES 21
C1911 CAP 18 C3453 CAP_P 31 C4600 CAP 37 C5958 CAP 46 C6371 CAP 50 C9020 CAP 70 L7000 FILTER_4P 57 R1228 RES 12 R2385 RES 21
A C1921
C1922
C1923
CAP
CAP
CAP
18
18
18
C3462
C3463
C3464
CAP_P
CAP_P
CAP_P
31
31
31
C4626
C4627
C4705
CAP
CAP
CAP
37
37
38
C5992
C5993
C5994
CAP
CAP
CAP
46
46
46
C6401
C6402
C6403
CAP
CAP
CAP
51
51
51
C9024
C9025
C9026
CAP
CAP
CAP
70
70
70
L7004
L7005
L7006
FILTER_4P
FILTER_4P
FILTER_4P
57
57
57
R1255
R1256
R1300
RES
RES
RES
12
12
13
R2401
R2410
R2411
RES
RES
RES
22
22
22
A
114
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R2601 RES 24 R4610 RES 37 R6882 RES 55 RP3511 RPAK4P 32 ZT0201 MTGHOLE 2
R2696 RES 24 R4810 RES 39 R7011 RES 57 RP4803 RPAK4P 39 ZT0250 HOLE_VIA 2
R2751 RES 25 R4865 RES 39 R7031 RES 57 RP4877 RPAK4P 39
D
R2761
R2765
R2766
RES
RES
RES
25
25
25
R5001
R5002
R5600
RES
RES
RES
40
40
43
R7041
R7042
R7050
RES
RES
RES
57
57
57
RP5610
RP5611
RP6100
RPAK4P
RPAK4P
RPAK4P
43
43
48
D
R3011 RES 27 R6108 RES 48 R7511 RES 62 SH0200 SHLD_3P_EMI 2
C R3012
R3013
R3020
RES
RES
RES
27
27
27
R6109
R6153
R6154
RES
RES
RES
48
48
48
R7512
R8100
R8151
RES
RES
RES
62
63
63
SP0201 SPKR_CLIP_P84 2
C
R3021 RES 27 R6155 RES 48 R8160 RES 63 SP0204 SPKR_CLIP_P84 2
R3100 RES 28 R6158 RES 48 R8163 RES 63 T8600 XFR_1000BT_82400275 67
R3101 RES 28 R6159 RES 48 R8164 RES 63 T8601 XFR_1000BT_82400275 67
R3102 RES 28 R6190 RES 48 R8165 RES 63 U1200 COMPARATOR_LMC7211 12
R3104 RES 28 R6192 RES 48 R8167 RES 63 U1250 INA138 12
R3105 RES 28 R6193 RES 48 R8200 RES 64 U1300 MAX1772 13
R3131 RES 28 R6196 RES 48 R8202 RES 64 U1370 AMP_MAX4172 13
R3132 RES 28 R6197 RES 48 R8203 RES 64 U1380 OPAMP_LMC7111 13
R3220 RES 29 R6198 RES 48 R8210 RES 64 U1400 LTC1625 14
R3321 RES 30 R6240 RES 49 R8212 RES 64 U1450 VREG_LP2951 14
R3352 RES 30 R6241 RES 49 R8255 RES 64 U1460 VREG_LP2951 14
R3411 RES 31 R6291 RES 49 R8420 RES 65 U1970 VREG_LM2594 18
R3500 RES 32 R6295 RES 49 R8421 RES 65 U1980 VREG_MM1572FN 18
R3506 RES 32 R6340 RES 50 R8509 RES 66 U2100 I2 19 22 32 38 43 59 63 65 68 72
R3514 RES 32 R6345 RES 50 R8561 RES 66 U2250 VREG_LT1962 20
R3550 RES 32 R6346 RES 50 R8562 RES 66 U2390 SN74AUC1G74 21
R3601 RES 33 R6395 RES 50 R8590 RES 66 U2500 CLK_DR_CDCVF2505 23
R3610 RES 33 R6396 RES 50 R8591 RES 66 U2700 M30280F8 25
R3611 RES 33 R6400 RES 51 R8592 RES 66 U3000 ADT7467 27
R3620 RES 33 R6420 RES 51 R8593 RES 66 U3100 OPAMP_MAX4236EUTT 28
R3702 RES 34 R6421 RES 51 R8594 RES 66 U3130 MM3120 28
R3703 RES 34 R6422 RES 51 R8595 RES 66 U3220 KXM52 29
R3704 RES 34 R6423 RES 51 R8596 RES 66 U3600 A8 33 34 35
R3706 RES 34 R6451 RES 51 R8600 RES 67 U3990 PI3B3257 36
R3707 RES 34 R6452 RES 51 R8601 RES 67 U4600 FAN2558 37
R3720 RES 34 R6453 RES 51 R8602 RES 67 U5700 M11P 44 46 47 48 51 53
R3722 RES 34 R6455 RES 51 R8610 RES 67 U6200 SDRAM_DDR_K4D553235F 49
B R3723
R3724
R3725
RES
RES
RES
34
34
34
R6456
R6457
R6458
RES
RES
RES
51
51
51
R8620
R8621
R8800
RES
RES
RES
67
67
68
U6250
U6300
U6350
SDRAM_DDR_K4D553235F 49
B
R3726 RES 34 R6459 RES 51 R8902 RES 69 U6400 VREG_MM1571J 51
R3727 RES 34 R6460 RES 51 R8903 RES 69 U6510 CLK_GEN_CY25811 52
R3729 RES 34 R6462 RES 51 R8905 RES 69 U6700 SIL1178CS48 54
R3730 RES 34 R6463 RES 51 R8906 RES 69 U6800 SIL1178CS48 55
R3731 RES 34 R6470 RES 51 R8909 RES 69 U6953 NC7S32 56
R3752 RES 34 R6490 RES 51 R8911 RES 69 U7050 741G32 57
R3753 RES 34 R6498 RES 51 R8912 RES 69 U7051 741G32 57
R3757 RES 34 R6500 RES 52 R8915 RES 69 U7100 FEPR_1MX8 58
R3758 RES 34 R6501 RES 52 R8916 RES 69 U7400 PCI1510GGU 61
R3759 RES 34 R6502 RES 52 R8921 RES 69 U7450 PWR_CNTRL_TPS2211 61
R3761 RES 34 R6503 RES 52 R8931 RES 69 U7500 UPD720101_FBGA_SPLIT 62 73
R3765 RES 34 R6510 RES 52 R8933 RES 69 U8500 BCM5462 18 66 69
R3766 RES 34 R6511 RES 52 R8935 RES 69 XW1012 SHORT 10
A R3973
R3974
R3975
RES
RES
RES
36
36
36
R6742
R6752
R6754
RES
RES
RES
54
54
54
R9301
R9302
R9303
RES
RES
RES
73
73
73
XW6591 SHORT
XW6592 SHORT
XW6593 SHORT
52
52
52
A
R3982 RES 36 R6764 RES 54 R9310 RES 73 XWA000 SHORT 74
R3987 RES 36 R6801 RES 55 R9341 RES 73 Y2410 CRYSTAL 22
R3988 RES 36 R6802 RES 55 R9345 RES 73 Y2740 CRYSTAL 25
R3989 RES 36 R6803 RES 55 RP0990 RPAK4P 9 Y2750 CRYSTAL 25
115
8 7 6 5 4 3 2 1

820-1810 - 051-6839 - F000 (Project Q41C)

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8 7 6 5 4 3 2 1

F 412044 PRODUCTION RELEASED

3 3 System Block Diagram MARIAS 08/24/2005 43 56 I2 AGP Interface MARIAS 08/24/2005

5 5 Revision History N/A N/A 45 58 GPU VCore Supply MARIAS 08/24/2005

9 9 JTAG Connections MARIAS 08/24/2005 49 62 GPU Frame Buffer A MARIAS 08/24/2005

10 10 Power Synonyms MARIAS 08/24/2005 50 63 GPU Frame Buffer B MARIAS 08/24/2005

11 11 Signal Synonyms MARIAS 08/24/2005 51 64 GPU (M11) GPIOs/Straps MARIAS 08/24/2005

12 12 Power Inputs MARIAS 08/24/2005 52 65 GPU (M11) Clocks/Misc MARIAS 08/24/2005

17 17 2.5V Supply MARIAS 08/24/2005 57 70 External Display Conns MARIAS-PDIFF 06/02/2005

18 19 Vesta Power & Misc MARIAS 08/24/2005 58 71 BootROM MARIAS 08/24/2005

19 21 I2 Power MARIAS 08/24/2005 59 72 I2 PCI Interface MARIAS 08/24/2005

20 22 I2 Power Supplies MARIAS 08/24/2005 60 73 Q85 AIRPORT/BT CONN MARIAS-MDIFF N/A

21 23 I2 Supplemental MARIAS 08/24/2005 61 74 Cardbus MARIAS 08/24/2005

22 24 I2 Miscellaneous MARIAS 08/24/2005 62 75 NEC USB2 MARIAS 08/24/2005

23 25 PCI Clock Buffer MARIAS 08/24/2005 63 81 I2 UATA Interface MARIAS 08/24/2005

24 26 LEDs/Reset/Debug MARIAS 08/24/2005 64 82 HDD/ODD Connectors MARIAS-PDIFF 06/02/2005

26 29 Power Sequencing MARIAS 08/24/2005 66 85 Vesta Ethernet PHY MARIAS 08/24/2005

27 30 Fan Controller MARIAS 08/24/2005 67 86 Ethernet Connector N/A N/A

28 31 ALS Support MARIAS 08/24/2005 68 88 I2 FireWire Interface MARIAS 08/24/2005

30 33 Q41C Internal I/O I N/A N/A 70 90 FireWire Ports MARIAS-PDIFF 06/02/2005

32 35 I2 Processor Interface MARIAS 08/24/2005 72 92 I2 USB Interface MARIAS 08/24/2005

33 36 A8 MaxBus (CPU0) MARIAS 08/24/2005

73 93 NEC USB2 Interface MARIAS 08/24/2005

37 46 CPU AVDD Supply MARIAS 08/24/2005 77 112 Cross Reference Page

38 47 I2 Memory Interface MARIAS 08/24/2005 78 113 Cross Reference Page

39 48 Memory Series Termination MARIAS-NDIFF N/A 79 114 Cross Reference Page

40 50 DDR2 SO-DIMM Slot A MARIAS-MDIFF N/A 80 115 Cross Reference Page

DIMENSIONS ARE IN MILLIMETERS

METRIC Apple Computer Inc.

X.XXX PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

DO NOT SCALE DRAWING

826-4393 1 LBL,P/N LABEL,PCB,28MM X 6MM [EEE:TML] CRITICAL EEE_TML

RELEASE SCALE SCHEM,MLB,Q41C

BOM OPTIONS Module Components TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,1MM MM

PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION

343S0383 1 IC,ASIC,I2,REV1.2,NB/SB,974 BGA U2100 CRITICAL

337S3135 1 IC,PMU05,BLANK,QFP U2700 CRITICAL PMU_BLANK

341S1772 1 IC,PMU05,Vxxx,QFP U2700 CRITICAL PMU_PROG

337S3277 1 IC,A7PM,R1.6,1.67GHZ,LGA,1.28V,25W,85C U3600 CRITICAL A7PM_1P67_LGA

335S0088 1 BOOTROM,BLANK U7100 CRITICAL BOOTROM_BLANK

NOTICE OF PROPRIETARY PROPERTY

AGREES TO THE FOLLOWING

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE DRAWING NUMBER REV.

343S0356 ? U8500 v1.4 is alt to v1.3

APPLE COMPUTER INC.

337S3181 337S3277 A7PM_1P67_LGA U3600 v1.5 is alt to v1.6 NONE

A P.33-35 SYNC_MASTER=MARIAS SYNC_DATE=08/24/2005

NOTICE OF PROPRIETARY PROPERTY

Config Connector Connector Connector Connector SIZE DRAWING NUMBER REV.

P.7 P.56 P.56 P.57 P.57 APPLE COMPUTER INC.

POWER SYSTEM ARCHITECTURE

>~13.44V TURNS-ON BACKLIGHT VCC VRAM CORE

INVERTER VRAM I/O

NO INRUSH PROTECTION 1V8_RUN

NOTICE OF PROPRIETARY PROPERTY

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.

NOTICE OF PROPRIETARY PROPERTY

SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.

D I2S Series Rs Lower DVO Series Rs D