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Procedia Computer Science 166 (2020) 187–194

3rd International Conference on Mechatronics and Intelligent Robotics (ICMIR-2019)

Research on LFMCW Radar Velocity Ranging Optimization

System Based on FPGA
Ying Liang11, Ke Li Li11, Fang Hong Bi11, Kun Zhang11, Jun Yang1,**
1,**

11
School
School of
of Information
Information Science
Science and
and Engineering,
Engineering, Yunnan
Yunnan University
University Yunnan
Yunnan Kunming
Kunming 650091,China
650091,China

Abstract
Abstract

Linear
Linear frequency
frequency modulation
modulation continuous
continuous wavewave (LFMCW)
(LFMCW) radar radar is
is widely
widely used
used in
in the
the field
field of
of velocity
velocity measurement
measurement andand ranging
ranging
because
because of
of its
its high
high precision
precision and
and good
good range
range resolution.
resolution. The
The traditional
traditional LFMCW
LFMCW radar radar uses
uses aa single
single core
core FFT
FFT to to do
do data
data
processing,
processing, which
which isis not
not very
very fast.
fast. This
This article
article utilize
utilize that
that advantages
advantages ofof fast
fast and
and high
high degree
degree of
of integration
integration of
of FPGA,
FPGA, andand propose
propose
aa double-core
double-core FFT
FFT processor
processor based
based onon the
the use
use of
of the
the optimized
optimized CORDIC
CORDIC parallel
parallel algorithm
algorithm to to improve
improve data
data processing
processing speed,
speed,
enhance
enhance real
real time,
time, design
design and
and realize
realize the
the calculation
calculation module
module ofof the
the double-core
double-core FFT FFT data
data processing
processing module
module and
and the
the distance
distance
measuring
measuring speed,
speed, and
and finishes
finishes the
the design
design ofof the
the LFMCW
LFMCW radar radar speed
speed measuring
measuring andand measuring
measuring system
system with
with real
real time
time and
and quick
quick
advantages.
advantages. The
The experimental
experimental results
results show
show that
that the
the system
system has
has the
the characteristics
characteristics ofof fast
fast data
data processing
processing and
and high
high reliability,
reliability, and
and
can
can measure
measure the
the moving
moving vehicle
vehicle in
in real
real time
time and
and effectively.
effectively.
© 2020 The Authors. Published by Elsevier B.V.
© 2019
© 2019 The
The Authors.
Authors. Published
Published by
by Elsevier
Elsevier B.V.
B.V.
This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Peer-review
Peer-review under responsibility
responsibility of
of organizing
organizing committee
committee of the 3rd
3rd International Conference
Conference on Mechatronics
Mechatronics and
and Intelligent
Intelligent
Peer-review under responsibility of the scientific committeeofofthe
under the 3rd International
International Conference on
on Mechatronics and Intelligent
Robotics (ICMIR-2019)
Robotics (ICMIR-2019)
Robotics, ICMIR-2019.
Keywords: Ranging
Keywords: Ranging;; Speed;
Speed; FPGA;
FPGA; Optimized
Optimized CORDIC
CORDIC parallel
parallel algorithm;
algorithm; Dual-Core
Dual-Core FFT
FFT

1.
1. Introduction
Introduction

Traditional
Traditional LFMCW
LFMCW radar
radar mostly
mostly uses
uses single-core
single-core FFT
FFT processor
processor for
for data
data processing,
processing, and
and its
its computing
computing power,
power,
computing
computing speed and accuracy cannot meet the
speed and accuracy cannot meet the real-time
real-time and
and accuracy requirements of current speed-measuring
accuracy requirements of current speed-measuring

*
* *
Corresponding
Corresponding Author.
*
Author. Tel.+(86)
Tel.+(86) 13608716820
13608716820
*E-mail: junyang@ynu.edu.cn.
*E-mail: junyang@ynu.edu.cn.

2019
2019 The
The Authors.
Authors. Published
Published by
by Elsevier
Elsevier B.V.
B.V. This
This is
is an
an open
open access
access article
article under
under the
the CC
CC BY-NC-ND
BY-NC-ND license
license
https://creativecommons.org/licenses/by-nc-nd/4.0/)
https://creativecommons.org/licenses/by-nc-nd/4.0/)
Selection
Selection and
and peer-review
peer-review under
under responsibility
responsibility of
of the
the scientific
scientific committee
committee of
of the
the 3rd
3rd International
International Conference
Conference on
on Mechatronics
Mechatronics and
and Intelligent
Intelligent
Robotics
Robotics (ICMIR-2019)
(ICMIR-2019)

1877-0509 © 2020 The Authors. Published by Elsevier B.V.

This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Peer-review under responsibility of the scientific committee of the 3rd International Conference on Mechatronics and Intelligent Robotics,
ICMIR-2019.
10.1016/j.procs.2020.02.046
188 Ying Liang et al. / Procedia Computer Science 166 (2020) 187–194
Author name / Procedia Computer Science00 (2018) 000–000

ranging radars.[1] Therefore, this paper proposes the dual-core FFT processor used in the radar ranging radar.
Considering that FPGA technology has abundant resources and is easier to design and implement the parallel
structure and flow structure. It has prominent advantages in the calculation of large points of FFT. In this paper,
based on the FPGA, completed the design of the speed measurement and ranging system based on the optimized
CORDIC parallel algorithm of the dual-core FFT processor., finally achieving a great real-time performance and
high efficiency advantage of speed of LFMCW radar ranging system.

2. Introduction to Relevant Technologies

2.1 LFMCW Radar Ranging and Speed Measurement Principle

The radar of chirped continuous wave measures the distance and radial velocity of the target by transmitting a
chirped continuous wave signal and using the frequency of the transmitted wave over time and the received echo
frequency difference.[2]
The common forms of using linear frequency modulation have two types which are both sawtooth modulation
and triangular modulation. The former is applied to the occasion where only the target distance is detected, and the
latter can also obtain the corresponding information of speed. It solves the distance-Doppler coupling phenomenon
well.[3] Therefore, the present design that uses a signal of triangular wave to modulated radar signal, and its variation
be shown in Fig.1, where ft, fr, T, B denote respectively the transmit signal frequency, the received signal frequency
sweep cycle, sweep bandwidth.
f

（a）
ft B

fr
f0

τ(t) T t

fb

t
fb

Figure.1 Modulation Triangle Waveform


fb
When the target velocity is 0,  f
b fb , it can be known from the triangle relation that the beat frequency fb
in Fig.1 is:
4B
fb 
 t  R (1)
Tc
Where μ is the slope of frequency modulation and R is the distance. When the target object moves, its speed
needs to be calculated using the Doppler shift method. Set of the Doppler frequency is fd, and the radial velocity of
the target object relative to the radar is v, then
(2)
R
f b

 fb  Tc
8B

cf d c  fb  fb 
 

v  (3)
2 f0 4 f0
2.2 Fast Fourier Transform
[4]
The algorithm of Fourier transform fastly is improved by the DFT (Discrete Fourier Transform) algorithm.
DFT and its inverse transformation are as follows:
N 1
X k 
  x  n W
n 0
nk
N   n  N  1 （4）
 Ying Liang et al. / Procedia Computer Science 166 (2020) 187–194 189
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1 N 1
x  n 
N n 0
x  k WN nk 0  n  N  1 （5）

Where x(n) is a sequence of length N and X(n) is the frequency domain of x. It can be seen from the above two
formulas that the calculation of DFT is particularly large, considering the symmetry and periodicity of the twirl
factor, the long sequences can be converted to short sequences for calculation.
In summary, the role of FFT is that converting a long sequence of length N into a plurality of shorter sequences
for simplified calculation.

2.3 CORDIC Algorithm

CORDIC (coordinate rotation digital computer) algorithm is a method of approximation by replacing
multiplication operations with shift operations and addition and subtraction operations. [5] It’s principle is shown in
Fig.2, v1 is the point after v2 is rotated by θ.

y2 v  x 2 ,y 2 

y1 v  x1 ,y 1 

θ
O x2 x1 x

Figure 2 Schematic Diagram of the CORDIC Algorithm

The traditional CORDIC algorithm is iterative sequence, which will undoubtedly affect the operation speed and
accuracy. This paper adopts an optimized parallel CORDIC algorithm, which uses the rotation compensation
strategy to reduce the number of iterations and improve the speed of the algorithm while maintaining accuracy.

3. System Hardware Structure Design

Data
FFT data computing
processing module
Signal module
acquisition PC
module

Storage module

Figure 3 System Top Map

The top diagram of the system designed in this paper is shown in Fig.3. Complete system function, in addition to
the above mentioned several modules, also need some peripheral equipment, such as: PLL, Flash, JIAG UART, etc.,
the use of SGDMA bus connection between the modules for data transmission.

3.1 Signal Acquisition Module

This design adopts with low power consumption, programmable, dormant AD9833 modulation signal generator
to generate triangular wave to IVS - 167 radar transceiver signal modulation, and then use the 16-bit ADS8509 serial
190 Ying Liang et al. / Procedia Computer Science 166 (2020) 187–194
Author name / Procedia Computer Science00 (2018) 000–000

analog-to-digital converter, the Quartus II 13.0 platforms provide FIR IP check signal modulus conversion and filter
processing, to achieve a small space occupied, high speed, strong stability, low resource consumption, etc of the data
acquisition module.

3.2 FFT Data Processing Module

This design uses the optimized CORDIC parallel algorithm to design the dual-core 1024 16-bit FFT data
processing module, whose structure is shown in Fig.4. Due to space constraints, this paper will only introduce the
design of important modules different from single-core FFT data processing, such as system clock analysis, dual-
port RAM and CORDIC module.

control

Address pipeline
Address generator

Address pipeline

CORDIC 1 Data conversion 1

Dual-Port RAM

CORDIC 2 Data conversion 2

Figure 4 FFT Data Processing Module Structure Diagram

3.2.1 System Clock Analysis

The number of clocks used in a dual-core system is 4, and the relationship between each clock is different from
that of a single core, as shown in Fig.5:

Figure 5 Clock Relationship

3.2.2 Dual Port RAM Module

In the dual-core FFT processing module, when reading and writing to RAM, the operation must be completed
within the specified time, otherwise the whole FFT system will be in a state of chaos. Because butterfly operation is
double input and double output, RAM must be double port to meet the requirements. In order to avoid conflicts in
the related read and write operations, the RAM of the dual-port RAM uses two pieces of memory and "ping-pong
operation" internally, uses two buffer units to realize the alternation of read and write operations. And the
corresponding enable signal is required. The simulation generation components are shown in Fig.6:
 Ying Liang et al. / Procedia Computer Science 166 (2020) 187–194 191
Author name / Procedia Computer Science00 (2018) 000–000 5

Figure 6 Dual Port RAM Module Component Diagram

3.2.3 CORDIC Algorithm

The optimized CORDIC algorithm structure is shown in Fig.7. This algorithm adds a rotation compensation to the
parallel algorithm, and the high part rotation direction calculation and rotation compensation can be performed at the
same time as the low part rotation, reducing the extra time loss.

θ Low rotation direction cosθ

Low rotation
calculation
High
part
rotation sinθ

High part
The rotations
rotation direction
cancel out
calculation

Figure 7 Optimized CORDIC Parallel Algorithm Structure

3.3 Implementation of Target Information Algorithm

According to the analysis in section 1.1, the target distance can be obtained by using the distance calculation
formula (3) after finding the difference frequency. The velocity information of moving targets should be collected
based on Doppler principle, and then the Doppler frequency can be calculated. Finally, the radial velocity can be
calculated from the relationship between the radial velocity and the Doppler frequency (4). The component diagram
generated after realizing this module in FPGA is shown in Fig.8:

Figure.8 Data Calculation Module Component Diagram

192 Ying Liang et al. / Procedia Computer Science 166 (2020) 187–194
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4. Test Results and Analysis

4.1 FFT Data Processing Module Simulation

The simulation results in ModelSim and the calculation results of the dual-core FFT function provided by
MATLAB are compared, and the results are shown in Fig.9.

Figure.9 FFT Function Provided by MATLAB and FFT Module Simulation Comparison Diagram

By Fig.9, the data obtained by the FFT data processing module is consistent with the simulation results by
MATLAB, which verifies the correctness of the function of the FFT module.

4.2 Radar Ranging and Speed Test

The test results of moving target with this system are shown in Fig.10. Target parameters such as sweep band
width B, speed v, distance R can be displayed, thus the system has real-time performance.

Figure 10 Test Results

4.3 Accuracy Test

The simulation scenario was tested for many times, and the test results are shown in Table.1 below.

Table.1 Results and Error Analysis of Ranging and Speed Test

Analysis of radar ranging speed measurement results

Actual Test Actual Test

error error
distance（m） distance（m） speed（km/h） speed（km/h）

30 30.3 1.00% 19.7 19.7 0.00%

50 51.1 2.20% 30.9 31 0.33%

 Ying Liang et al. / Procedia Computer Science 166 (2020) 187–194 193
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75 74.2 1.07% 40.8 41.2 1.00%

100 101.7 1.70% 80.1 80.2 0.13%

As can be seen from the table above, in the distance test of 30 to 200 meters, the distance measurement error shall
not exceed 2.5 percent. Therefore, the system can measure the effective distance of the target within a distance of
200 meters. In the speed measurement experiment, the collected data interval is 100Km/h, and the error is less than
1%, indicating that the system also has a good speed measurement ability.

4.4 Performance Analysis

The performance of the dual-core FFT data processing module and the single-core FFT processor, which are the
key parts of this design, are compared, as shown in Table.2:

Table.2 Performance comparison of single dual-core FFT data processing module

Dual-Core FFT Single-core FFT

Actual fmax 27MHz 27MHz

Total logic elements 22,923/33,216（69%） 14,409/33,216（43%）

Logic registers 6,022/33,216 （18%） 4,982/33,216 （15%）

Time to complete 1024 data points 101.1μs 189μs

As can be seen from Table 2, the demand for dual-core FFT resources is increased by about 60% compared with
single-core FFT, and the demand for registers is increased by nearly 20%. The time to complete 1024 point data
processing is greatly reduced. It follow that using that dual-core FFT in case of limit resources, the data processing
ability is greatly improved, and data calculation speed is improve.

5. Summary

In this paper, the optimization design of a radar ranging speed measurement system is completed. The ranging
and velocity measurement method of linear frequency modulation continuous wave is studied, and the distance-
velocity coupling problem caused by the Doppler effect is analyzed. On the Quartus 13.0 platform with the Verilog
HDL programming language to design and implement a radar range algorithm and a dual-core FFT data processing
module that optimizes CORDIC parallel algorithms. Finally, the test proves that the system can effectively test the
distance and speed of the target, and has the advantages of high real-time and precision, logic programmable,
parallel processing and strong anti-interference ability.

Acknowledgments

The author, Ying Liang, thanks the postgraduate project of Yunnan university school of information for
supporting the publication of this paper "research on key technologies of intelligent home robot voice control system
based on FFT dual-core processor".

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