1st Hourly Examination – Spring 2021

Subject: FPGA Based System Design Day: Wednesday

Instructor: Muhammad Amin Qureshi / Taha Hasan Submission Date: 07-04-2021
Program: BS (CS) / BE (Electronic Engineering) Max. Marks: 13
Time Allowed: Can be attempted between 11:45am and 02:45pm only

FACULTY OF ENGINEERING, SCIENCE AND TECHNOLOGY

Please follow the instructions carefully:
1. Write your answers in a Word file and upload the file before the due date on Blackboard.
2. Write your name and registration ID on the first page of your Word file.
3. Answer scripts can only be uploaded on Blackboard any time before its deadline.
4. To avoid any unforeseen problems, you are advised NOT to wait for the last minute to
upload your answer script.
5. Submission of answer copy(ies) will be considered acceptable through Blackboard only.
Therefore, do not submit your document through email or any other medium.
6. Use 12 pt. font size and Times New Roman font style along with 1-inch page margins.
7. You can give your answers in hand written form if you are facing any difficulty in type-
written form.
8. If you are giving hand written answers then you must use blank sheets with sufficient margin
on left and right side.
9. After completing the paper, you are required to make its viewable Snap Shot
(preferably Scan) and paste them on a word file or create a single PDF file.
10. Please make sure that your hand written file is sufficiently visible and readable. You must
avoid any blur or dull pictures. Don’t use pencil at all.
11. Strictly follow the sequence of the questions.
12. Follow the requirements of the word limit and the marking criteria while writing your
answers.

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13. Provide relevant, original and conceptual answers, as this exam aims to test your ability to
examine, explain, modify or develop concepts discussed in class.
14. Do not copy answers from the internet or other sources. The plagiarism of your answers may
be checked through Turnitin.
15. Recheck your answers before the submission on BlackBoard to correct any content or
language related errors.
16. Double check your word file before uploading it on BlackBoard to ensure that you have
uploaded the correct file with your answers.

Course Learning Outcome Guide

Question 1 CLO1, CLO2

Question 2 CLO1

Question 3 CLO2

Question 1: [3 Marks]
Short Questions and Answers

1) Which combinational logic circuit implements a Lookup Table (LUT)?

2) What is the b vector length in input [3:13] b;

3) If a net is not declared explicitly, Verilog assumes its type automatically. What type of a net is

assumed if it is not declared explicitly?

4) What is the correct way to instantiate built-in AND gate primitive in Verilog, if Out1 is the

output and in1, in2, in3 are the inputs?

5) What is the correct syntax for writing numbers in Verilog? For example, if you want to assign

a hexadecimal value A0EF to a signal, how would you do it?

6) How can a 2-to-1 multiplexer be implemented using a conditional operator?

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Question 2: [4 Marks]

a) Briefly explain the CAD flow (software configuration flow) of FPGA depicting how
hardware is mapped on an FPGA in various steps after writing the HDL code.
b) Compare ASIC with FPGA in terms of Power, Speed, Size, NRE cost, Volume of
production, and other design factors.
c) What is the routing architecture in an FPGA comprised of? How are the wires
interconnected and signals transported between logic blocks? Give a brief overview.

Question 3: [6 Marks]
a) Write the Verilog code of a Half Adder using built-in gate primitives.
b) Write the hierarchical Verilog code of a Full Adder by instantiating the Half Adder module
you made in part a.
c) Write the hierarchical Verilog code of a 16-bit Ripple Carry Adder using the module you
made the part b.

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