Professional Documents
Culture Documents
P-Tile Avalon Streaming IP For PCI Express Design Example User Guide
P-Tile Avalon Streaming IP For PCI Express Design Example User Guide
IP Version: 3.1.0
Contents
Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example Send Feedback
User Guide
2
UG-20234 | 2020.10.05
Send Feedback
The PIO design example automatically creates the files necessary to simulate and
compile in the Intel® Quartus® Prime software. The design example covers a wide
range of parameters. However, it does not cover all possible parameterizations of the
P-Tile Hard IP for PCIe.
The simulation testbench instantiates the PIO design example and a Root Port BFM to
interface with the target Endpoint.
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
1. Design Example Description
UG-20234 | 2020.10.05
Figure 1. Block Diagram for the Platform Designer PIO Design Example Simulation
Testbench
PCIe Example Design Simulation Testbench
The test program writes to and reads back data from the same location in the on-chip
memory. It compares the data read to the expected result. The test reports,
"Simulation stopped due to successful completion" if no errors occur.
Figure 2. Platform Designer System Contents for P-Tile Avalon-ST PCI Express PIO
Design Example
The Platform Designer generates this design for up to Gen4 x16 variants.
Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example Send Feedback
User Guide
4
1. Design Example Description
UG-20234 | 2020.10.05
The SR-IOV design example automatically creates the files necessary to simulate and
compile in the Intel Quartus Prime software. You can download the compiled design to
an Intel Stratix® 10 DX Development Kit.
The simulation testbench instantiates the SR-IOV design example and a Root Port BFM
to interface with the target Endpoint.
Figure 3. Block Diagram for the Platform Designer SR-IOV Design Example Simulation
Testbench
PCIe SR-IOV Example Design Simulation Testbench
The test program writes to and reads back data from the same location in the on-chip
memory across 2 PFs and 32 VFs per PF. It compares the data read to the expected
result. The test reports, "Simulation stopped due to successful completion" if no errors
occur.
Send Feedback Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example
User Guide
5
1. Design Example Description
UG-20234 | 2020.10.05
Figure 4. Platform Designer System Contents for P-Tile Avalon-ST with SR-IOV for PCI
Express Design Example
Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example Send Feedback
User Guide
6
UG-20234 | 2020.10.05
Send Feedback
Using Intel Quartus Prime software, you can generate a programmed I/O (PIO) design
example for the Intel FPGA P-Tile Avalon-ST Hard IP for PCI Express* IP core. The
generated design example reflects the parameters that you specify. The PIO example
transfers data from a host processor to a target device. It is appropriate for low-
bandwidth applications. This design example automatically creates the files necessary
to simulate and compile in the Intel Quartus Prime software. You can download the
compiled design to your FPGA Development Board. To download to custom hardware,
update the Intel Quartus Prime Settings File (.qsf) with the correct pin assignments .
Compilation Functional
(Simulator) Simulation
Design
Example Compilation Hardware
Generation (Quartus Prime) Testing
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
2. Quick Start Guide
UG-20234 | 2020.10.05
pcie_ed.qpf
pcie_ed.qsf
pcie_ed.tcl
pcie_ed.qsys
pcie_ed.sof
Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example Send Feedback
User Guide
8
2. Quick Start Guide
UG-20234 | 2020.10.05
1. In the Intel Quartus Prime Pro Edition software, create a new project (File ➤ New
Project Wizard).
2. Specify the Directory, Name, and Top-Level Entity.
3. For Project Type, accept the default value, Empty project. Click Next.
4. For Add Files click Next.
5. For Family, Device & Board Settings under Family, select Intel Agilex™ or
Intel Stratix 10.
6. If you selected Intel Stratix 10 in the last step, select Stratix 10 DX in the
Device pull-down menu.
7. Select the Target Device for your design.
8. Click Finish.
9. In the IP Catalog locate and add the Intel P-Tile Avalon-ST Hard IP for PCI
Express.
10. In the New IP Variant dialog box, specify a name for your IP. Click Create.
11. On the Top-Level Settings and PCIe* Settings tabs, specify the parameters for
your IP variation. If you are using the SR-IOV design example, do the following
steps to enable SR-IOV:
a. On the PCIe0 Device tab under the PCIe0 PCI Express / PCI Capabilities
tab, check the box Enable multiple physical functions.
b. On the PCIe0 Multifunction and SR-IOV System Settings tab, check the
box Enable SR-IOV support and specify the number of PFs and VFs.
c. On the PCIe0 MSI-X tab under the PCIe0 PCI Express / PCI Capabilities
tab, enable the MSI-X feature as required.
d. On the PCIe0 Base Address Registers tab, enable BAR0 for both PF and VF.
12. On the Example Designs tab, make the following selections:
a. For Example Design Files, turn on the Simulation and Synthesis options.
If you do not need these simulation or synthesis files, leaving the
corresponding option(s) turned off significantly reduces the example design
generation time.
b. For Generated HDL Format, only Verilog is available in the current release.
c. For Target Development Kit, select either the Intel Stratix 10 DX P-Tile
ES1 FPGA Development Kit or the Intel Agilex F-Series P-Tile ES0 FPGA
Development Kit.
13. Select Generate Example Design to create a design example that you can
simulate and download to hardware. If you select one of the P-Tile development
boards, the device on that board overwrites the device previously selected in the
Intel Quartus Prime project if the devices are different. When the prompt asks you
Send Feedback Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example
User Guide
9
2. Quick Start Guide
UG-20234 | 2020.10.05
to specify the directory for your example design, you can accept the default
directory, ./intel_pcie_ptile_ast_0_example_design, or choose another
directory.
14. Click Finish. You may save your .ip file when prompted, but it is not required to
be able to use the example design.
15. Open the example design project.
16. Compile the example design project to generate the .sof file for the complete
example design. This file is what you download to a board to perform hardware
verification.
17. Close your example design project.
Note that you cannot change the PCIe pin allocations in the Intel Quartus Prime
project. However, to ease PCB routing, you can take advantage of the lane
reversal and polarity inversion features supported by this IP.
Change to
Run Analyze
Testbench
<Simulation Script> Results
Directory
Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example Send Feedback
User Guide
10
2. Quick Start Guide
UG-20234 | 2020.10.05
Send Feedback Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example
User Guide
11
2. Quick Start Guide
UG-20234 | 2020.10.05
2.3.1. Testbench
The testbench uses a test driver module, altpcietb_bfm_rp_gen4_x16.sv, to
initiate the configuration and memory transactions. At startup, the test driver module
displays information from the Root Port and Endpoint Configuration Space registers, so
that you can correlate to the parameters you specified using the Parameter Editor.
The example design and testbench are dynamically generated based on the
configuration that you choose for the P-Tile IP for PCIe. The testbench uses the
parameters that you specify in the Parameter Editor in Intel Quartus Prime.
This testbench simulates up to a ×16 PCI Express link using the serial PCI Express
interface. The testbench design does allow more than one PCI Express link to be
simulated at a time. The following figure presents a high level view of the PIO design
example.
Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example Send Feedback
User Guide
12
2. Quick Start Guide
UG-20234 | 2020.10.05
• pcie_ed_dut.ip: This is the Endpoint design with the parameters that you
specify.
//Directory path
<project_dir>/intel_pcie_ptile_ast_0_example_design/ip/pcie_ed
In addition, the testbench has routines that perform the following tasks:
• Generates the reference clock for the Endpoint at the required frequency.
• Provides a PCI Express reset at start up.
For more details on the Root Port BFM, refer to the TestBench chapter of the Intel
FPGA P-Tile Avalon streaming IP for PCI Express User Guide.
Related Information
Intel FPGA P-Tile Avalon streaming IP for PCI Express User Guide
Send Feedback Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example
User Guide
13
2. Quick Start Guide
UG-20234 | 2020.10.05
The figure below shows the PIO design example simulation design hierarchy. The tests
for the PIO design example are defined with the apps_type_hwtcl parameter set to
3. The tests run under this parameter value are defined in
ebfm_cfg_rp_ep_rootport, find_mem_bar and downstream_loop.
The testbench starts with link training and then accesses the configuration space of
the IP for enumeration. A task called downstream_loop (defined in the Root Port
PCIe BFM altpcietb_bfm_rp_gen4_x16.sv) then performs the PCIe link test. This
test consists of the following steps:
1. Issue a memory write command to write a single dword of data into the on-chip
memory behind the Endpoint.
2. Issue a memory read command to read back data from the on-chip memory.
3. Compare the read data with the write data. If they match, the test counts this as
a Pass.
4. Repeat Steps 1, 2 and 3 for 10 iterations.
The first memory write takes place around 219 us. It is followed by a memory read at
the Avalon-ST RX interface of the P-tile Hard IP for PCIe. The Completion TLP appears
shortly after the memory read request at the Avalon-ST TX interface. The memory
write and read transactions and the Completion TLP are shown in the following
waveforms.
Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example Send Feedback
User Guide
14
2. Quick Start Guide
UG-20234 | 2020.10.05
Figure 13. Simulation Waveforms for the PIO Design Example for the P-Tile Avalon-ST
IP for PCIe
The figure below shows the SR-IOV design example simulation design hierarchy. The
tests for the SR-IOV design example are performed by the task called sriov_test,
which is defined in altpcietb_bfm_cfbp.sv.
The SR-IOV testbench supports up to two Physical Functions (PFs) and 32 Virtual
Functions (VFs) per PF.
The testbench starts with link training and then accesses the configuration space of
the IP for enumeration. After that, it performs the following steps:
1. Send a memory write request to a PF followed by a memory read request to read
back the same data for comparison. If the read data matches the write data, it is
a Pass. This test is performed by the task called my_test (defined in
altpcietb_bfm_cfbp.v). This test is repeated twice for each PF.
2. Send a memory write request to a VF followed by a memory read request to read
back the same data for comparison. If the read data matches the write data, it is
a Pass. This test is performed by the task called cfbp_target_test (defined in
altpcietb_bfm_cfbp.v). This test is repeated for each VF.
The first memory write takes place around 263 us. It is followed by a memory read at
the Avalon-ST RX interface of PF0 of the P-tile Hard IP for PCIe. The Completion TLP
appears shortly after the memory read request at the Avalon-ST TX interface. The
memory write and read transactions and the Completion TLP associated with both PFs
and VFs are shown in the following waveforms.
Send Feedback Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example
User Guide
15
2. Quick Start Guide
UG-20234 | 2020.10.05
Figure 15. Simulation Waveforms for the SR-IOV Design Example for the P-Tile Avalon-
ST IP for PCIe
In addition, you can use the driver to change the value of the following parameters:
• The BAR being used
• The selected device (by specifying the bus, device and function (BDF) numbers for
the device)
(1) Throughout this user guide, the terms word, DWORD and QWORD have the same meaning that
they have in the PCI Express Base Specification. A word is 16 bits, a DWORD is 32 bits, and a
QWORD is 64 bits.
Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example Send Feedback
User Guide
16
2. Quick Start Guide
UG-20234 | 2020.10.05
Table 2. Test Operations Supported by the P-Tile Avalon-ST PCIe Design Examples
Supported by P-Tile Avalon-ST PCIe
Operations Required BAR
Design Example
Note: (*) These test operations are available only when the SR-IOV design example is
selected.
Send Feedback Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example
User Guide
17
2. Quick Start Guide
UG-20234 | 2020.10.05
You can run the Intel FPGA IP PCIe link test in manual or automatic mode. Choose
from:
• In automatic mode, the application automatically selects the device. The test
selects the Intel PCIe device with the lowest BDF by matching the Vendor ID.
The test also selects the lowest available BAR.
• In manual mode, the test queries you for the bus, device, and function
number and BAR.
For the Intel Stratix 10 DX or Intel Agilex Development Kit, you can determine the
BDF by typing the following command:
$ lspci -d 1172
4. Here are sample transcripts for automatic and manual modes:
Automatic mode:
Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example Send Feedback
User Guide
18
2. Quick Start Guide
UG-20234 | 2020.10.05
Manual mode:
Related Information
PCIe Link Inspector Overview
Use the PCIe Link Inspector to monitor the link at the Physical, Data Link and
Transaction Layers.
Send Feedback Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example
User Guide
19
2. Quick Start Guide
UG-20234 | 2020.10.05
6. Enter option 8 to perform a link test for every enabled virtual function allocated
for the physical function. The link test application will do 100 memory writes with
a single dword of data each and then read the data back for checking. The
application will print the number of virtual functions that failed the link test at the
end of the testing.
Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example Send Feedback
User Guide
20
2. Quick Start Guide
UG-20234 | 2020.10.05
Send Feedback Intel® FPGA P-Tile Avalon® Streaming IP for PCI Express* Design Example
User Guide
21
UG-20234 | 2020.10.05
Send Feedback
A.1. Intel FPGA P-Tile Avalon Streaming IP for PCI Express Design
Example User Guide Revision History
Document Version Intel Quartus IP Version Changes
Prime Version
2020.10.05 20.3 3.1.0 Removed the Registers section since the Avalon Streaming
design examples have no control register.
2020.07.10 20.2 3.0.0 Added simulation waveforms, test case descriptions and
test result descriptions for the design examples.
Added simulation instructions for the ModelSim simulator to
the Simulating the Design Example section.
2020.05.07 20.1 2.0.0 Updated the document title to Intel FPGA P-Tile Avalon
streaming IP for PCI Express Design Example User Guide to
meet new legal naming guidelines.
Updated the VCS interactive mode simulation command.
2019.11.13 19.3 1.0.0 Added Gen4 x8 Endpoint and Gen3 x8 Endpoint to the list
of supported configurations.
Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,
Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in ISO
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services 9001:2015
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any Registered
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.