Manual AC450

APC2 FUNCTION BLOCKS
for APC2
Function Blocks
Code: 3AFY 61281240

Revision: C
Language: EN
3AFY61281240
Issued by: FIDRI/EIE

Date: 10.05.1996
File: 61281240.DOC
Created with: Word for Windows 2.0
Designer 3.1
Table of revisions:
Date: Code: Rev.: Remark:

1996-05-10 3AFY61281240 A First issue
1996-10-05 3AFY61281240 B Second issue
1997-11-17 3AFY61281240 C
Table of references:
For information on: See:
The technical data and specifications are valid at the time of printing.
We reserve the right to subsequent alterations.
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CONTENTS
1. INTRODUCTION TO DRIVE APPLICATION CONTROLLER FUNCTION
BLOCKS AND DATA BASE ELEMENTS. .................................................................................... 7
2. APC FUNCTION ELEMENTS ACCORDING TO TYPE............................................................. 11
3. SHORT FORM DESCRIPTION - FUNCTION ELEMENTS........................................................ 15
4. SHORT FORM DESCRIPTION - DATA BASE ELEMENTS ..................................................... 18
5. EXECUTION TIMES FOR PC ELEMENTS ............................................................................... 19
6. SPACE REQUIREMENTS FOR PC ELEMENTS ...................................................................... 26
7. SPACE REQUIREMENTS FOR "Inline" CODE ......................................................................... 31
PC ELEMENTS ................................................................................................................ 32
Absolute Value Element ABS............................................................................................ 32
Read ACS Parameters ACSPR ........................................................................................ 33
Write ACS Parameters ACSPW........................................................................................ 37
Transmit/Receive ACS Datasets ACSRX.......................................................................... 41
Adder ADD ....................................................................................................................... 46
Adder ADD-MR................................................................................................................. 47
DataSet receiver for AF100 AFREC.................................................................................. 48
DataSet transmitter for AF100 AFTRA.............................................................................. 52
Analog input AIAPC.......................................................................................................... 56
Analog Input Extended IO AIEXT...................................................................................... 58
And Gate AND.................................................................................................................. 61
And Gate AND-O.............................................................................................................. 62
Analog Output Extended IO AOEXT ................................................................................. 64
Analog output AOMEAS ................................................................................................... 66
Average AVG ................................................................................................................... 67
Read one bit BGET........................................................................................................... 68
Block Header BLOCK ....................................................................................................... 69
Set one bit BSET .............................................................................................................. 70
Comment C ...................................................................................................................... 71
Comparator COMP........................................................................................................... 72
Comparator COMP-R ....................................................................................................... 73
Control Module Header CONTRM..................................................................................... 75
Code Converter CONV ..................................................................................................... 77
Code Converter CONV-BI................................................................................................. 78
Code Converter CONV-IB................................................................................................. 81
Counter COUNT ............................................................................................................... 84
Data Logger DATALOG.................................................................................................... 86
Initialize DCB channel DCBINIT........................................................................................ 89
Read from DCB dataset DCBRD ...................................................................................... 94
Receive DCB dataset DCBREC........................................................................................ 97
Transmit Dataset to DCB DCBTRA................................................................................... 104
Write to DCB dataset DCBWR.......................................................................................... 110
Demultiplexer DEMUX-MI ................................................................................................. 113
Derivator DER .................................................................................................................. 115
Digital Input DIAPC........................................................................................................... 117
Digital Input Extended IO DIEXT....................................................................................... 119
Divider DIV ....................................................................................................................... 122
Divider DIV-MR................................................................................................................. 123
Digital Output DOAPC ...................................................................................................... 124
Digital Output Extended IO DOEXT .................................................................................. 125
Diagnostic Function Block for DriveLink DRDIAG.............................................................. 127
Drive Fault DRFLT............................................................................................................ 130
Drive Parameter Download DRPAR.................................................................................. 131
Drive Link Receive DRREC............................................................................................... 134
Drive Link Transmit DRTRA.............................................................................................. 137
Drive Parameter Upload DRUPL....................................................................................... 140
Error Detection ERROR.................................................................................................... 143
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Event Detection EVENT.................................................................................................... 144

Event Logger EVLOG ....................................................................................................... 145
Event Detection EVT ........................................................................................................ 149
Queue Register FIFO ....................................................................................................... 150
Filter FILT-1P ................................................................................................................... 152
Filter FILTI........................................................................................................................ 154
Function Parameter to Integer Conversion FPI ................................................................. 155
Function Header FUNCM.................................................................................................. 156
Function Generator FUNG-1V .......................................................................................... 157
Two Integer to Integer Long conversion IIL ...................................................................... 159
Integer Long to two Integer conversion ILI ...................................................................... 160
Integrator INT ................................................................................................................... 161
Inverter INV ...................................................................................................................... 163
IO Bus Read IOBUSRD.................................................................................................... 164
IO Bus Write IOBUSWR ................................................................................................... 168
Limiter LIM-N.................................................................................................................... 172
Master Header MASTER .................................................................................................. 175
Maximum Selector MAX ................................................................................................... 177
DataSet receiver for MB90 MB90REC .............................................................................. 178
DataSet transmitter for MB90 MB90TRA .......................................................................... 182
Minimum Selector MIN...................................................................................................... 186
Mono Function MONO...................................................................................................... 187
Element for Copying Data MOVE...................................................................................... 189
Multiplier MUL................................................................................................................... 190
Integer scaling element MULDIV....................................................................................... 191
Multiplexer MUX-I ............................................................................................................. 192
Multiplexer MUX-MI .......................................................................................................... 193
Multiplexer MUX-MN......................................................................................................... 195
Multiplexer MUX-N............................................................................................................ 197
Multiplexer for text MUXA-I ............................................................................................... 198
Or Gate OR ...................................................................................................................... 199
Or gate OR-A ................................................................................................................... 200
Oscillator for sine wave OSC-SIN ..................................................................................... 202
Panel Control PC Element PANCON ................................................................................ 203
Input from Panel Bus PANREC......................................................................................... 207
Output to Panel Bus PANTRA .......................................................................................... 210
Parameter PAR ................................................................................................................ 213
Program Header PCPGM ................................................................................................. 215
PDP-Function PDP........................................................................................................... 217
PI-Function PI................................................................................................................... 219
PII regulator PII ................................................................................................................ 222
Ramp Generator RAMP.................................................................................................... 225
S-RAMP Generator RAMP-S1 .......................................................................................... 228
S-Ramp generator RAMP-SSH......................................................................................... 231
Register REG ................................................................................................................... 234
Group Data Register REG-G ............................................................................................ 236
Memory Monitoring RWM ................................................................................................. 238
Save parameter SAVE...................................................................................................... 241
Shift Register SHIFT......................................................................................................... 242
Slave Header SLAVEM..................................................................................................... 244
Speed and Position Measuring SPEEDP .......................................................................... 245
Square Root Element SQRT............................................................................................. 250
Memory Element SR......................................................................................................... 251
Memory Element SR-AA................................................................................................... 252
Memory Element SR-AO .................................................................................................. 253
Memory Element SR-D ..................................................................................................... 254
Memory Element SR-OA .................................................................................................. 255
Memory Element SR-OO .................................................................................................. 256
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Subtractor SUB................................................................................................................. 257

Switch SW........................................................................................................................ 258
Switch SW-C .................................................................................................................... 259
Element for Calculation of System Load SYSL.................................................................. 260
Time Delay On TON ......................................................................................................... 261
Time Delay Off TOFF ....................................................................................................... 261
Time Delay On TON-RET ................................................................................................. 263
Trigger Element TRIGG.................................................................................................... 264
Watchdog WDOG............................................................................................................. 265
Exclusive Or Gate XOR .................................................................................................... 267
DATA BASE ELEMENTS ................................................................................................. 268
ACS Link ACS00, ACS01, ACS02 .................................................................................... 268
Boolean Data DAT(B) ....................................................................................................... 270
Integer Data DAT(I) .......................................................................................................... 272
IntegerInteger Data DAT(II) .............................................................................................. 273
IntegerLong Data DAT(IL)................................................................................................. 274
Real Data DAT(R)............................................................................................................. 275
Drives Communication Board DCB00 ............................................................................... 276
DI Calculated DIC............................................................................................................. 278
Drive Link DRL00.............................................................................................................. 279
DataSet Peripheral DSP ................................................................................................... 280
Event Set (Send) EVS(S).................................................................................................. 283
Event Logger Buffer EVT00,EVT01 .................................................................................. 286
MasterBus 90 Link MB90.................................................................................................. 287
Panel Link PAN00............................................................................................................. 289
Boolean Param PARDAT(B)............................................................................................. 290
Integer Param PARDAT(I) ................................................................................................ 293
IntegerLong Param PARDAT(IL)....................................................................................... 294
Real Param PARDAT(R) .................................................................................................. 295
Save Parameter SAVE00 ................................................................................................. 296
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1. INTRODUCTION TO DRIVE APPLICATION

CONTROLLER FUNCTION BLOCKS AND DATA
BASE ELEMENTS.
Summary
ABB APC (Application Controller) is a microcomputer COMP
based control system designed specially for electrical (C1, C2)
1 I1 I1 > I2 5
drive applications. The system provides the programming language, 2 I2 I1 = I2 6
methods and tools for process control functions. I1 < I2 7
The programming language is based on software
implemented logic elements (function blocks) and data base
elements. Many of the function block (FB) elements are the Figure 1. Graphic Symb
same as found in the other industrial controllers of the ABB
MasterPiece family (e.g. Advant Controller 110 and Advant Controller 55). The remaining
FB elements and all of the data base elements are specific for the Drive product APC.
Note: Within the Master Piece product family the Function Blocks are
referred to as the PC elements.
The Programming Language

The Function Block (or element) is the smallest unit of the application programming language.
Each element performs a complete function, such as a logical AND gate, a timer or a feedback
control element.
Call
Each element has an unique call name that enables it to be accessed regardless of the APC
system the element is in. Many of the elements have call parameters which allow size, function,
data type, and other properties to be determined.
Call Name
The nemonic call name provides information about the basic function of the element. Further
information about the function of the element or the data types for which the element is
intended is given by a suffix to the name. E.g. COMP-I, comparator for integers, and COMP-R,
comparator for real numbers, see table 1.
Table 1 Suffix
Suffix Description
B Boolean
I Integer
R Real number
T Time
G Group data
M Memory function Multiplier in compound elements
L Load function
Limiting function
Threshold function
R Read/Write
W
N 1-of-N addressing
D Data
P Number of poles
V Variable
O OR function in compound elements
A AND function in compound elements
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Call Parameters
For structure elements the call parameters determine cyclicity, COUNT
place in the (C1)
cycle time table (determines the order of execution for Function 1 >L >0 10
2 U/D-N =0 11
blocks having the same cyclicity) and, for a slave element, the
identity of its master header. For a function element, the call 3 >C <0 12
4 R
parameters may specify the size, data type, number of inputs
5 EN
and outputs, etc.
21 I O 22
Graphic Symbol
Each Function block has a graphic symbol similar to that Figure 2. Graphic
shown in figure 1. Normally, the call name of the element is Symbol
written in the uppermost part of the symbol.For certain
functions, e.g. AND and Or, the name is replaced by a symbol.
When the element has supervisory control signals, the terminals for these signals
are collected in a separate part of the symbol according to figure 2.
Connection of Function element Inputs and Outputs

Only inputs and outputs with the same data type can be interconnected. If, for example,
an output with data of the type is to be connected to an input of the type R, a code
conversion element, e.g. CONV ( I,R) must be inserted in the data path.
Table 2 Data types

Designation Data type
I Integer, 16 bit
IL Integer, 32 bit
R Real number
B Boolean
T Time
T Time, real representation
R
G Group data, i.e. a collection of data with one of
the above data types
A Array
The range of allowable integer values is as follows.

Error Handling
Integer Overflow
For I = -32768 .. 32767

For IL = -2147483648 .. 2147483647
When the range is exceeded the output is set to the respective limiting value.
Overflow Real Numbers

The range of allowable real numbers is 9.2 x 10 18 ... -0.1 x 10 18.
When the range is exceeded the output is set to the respective limiting value. The smallest
magnitude that can be represented by a real number is 5.0 x 10 -20. Any output with an absolute
value smaller than this is set to 0.0.
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Element Libraries for Drive APC and other

Master Piece Products.
Each standard system has an element library which MAX (C1,C2)
contains a defined subset of the total number of the 1 DEADB
available function elements. The Technical Description 11 IA1 A 30
contains the definition of the Function Blocks (PC 12 IA2 O 31
Elements) and the Data Base elements.
10 + C2 IAC2
Figure 3.Graphic Symbol with

Programming with the PC Language a
When programming an APC based control system, FB variable number of
elements are selected from the APC FB element library connections.
and included in a APC software desing template. The
FB elements are then interconnected on the diagram to define the data interchange between the
elements.
The information on the draft APC program is used when entering the APC program in source
code form using a system tool. The tool translates the program into object code, which is loaded
into the target system.
The Data Sheets

An element description starts with a short Summary that describes the main function of the
element. The graphic symbol of the element is shown to the right of the summary. Symbols
with a variable number of connections are shown as in figure 3.
The calling of the element is described under the heading Call.
ELEMENT(C1,C2, ... Cn)

If the element has call parameters, these are described in a table where their permissible values
are stated. Element terminals are described under the heading Connections. This section
provides a table giving each terminal number, name, type and application. The type of
connection is given as xy, where x is I or O if it is an input or an output terminal, and Y
denotes the data type previously described in Table 2.
The descriptions finish with a detailed functional description under the heading Function.
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Subtractor SUB The call name of the element.
Summary
Short description of the
SUB is used for subtraction of two integers or function of the element.
real numbers. 1 - 20
Call SUB 2 C1 The graphic symbol
Call Parameters Figure 1. of the element.
Table 1. Call, with table over the
Parameter Description Permissible values parameters, if any.
C1 Data type I, IL, R The terminals of the
Connections element are described
Table 2. in a table.
No Name Type Description
1 - IC1 Input for minuend
2 - IC1 Input for subtrahend Detailed description of the
20 - OC1 Output for difference elements function.
Function
The value at input 2 subtracted from valve at input 1
and the result is stored at output 20.
Overflow
If the maximum positive or negative values are exceeded, the
output is limited to the highest or lowest allowable for the
data type.
Figure 4. Description, schematic outline .
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2. APC FUNCTION ELEMENTS ACCORDING TO TYPE

Structure Elements
Block Header BLOCK
Control Module Header CONTRM
Function Header FUNCM
Master Header MASTER
Program Header PCPGM
Slave Header SLAVEM
Combinational Elements
And Gate AND
And gate with Or-ed inputs AND-O
Inverter INV
Or Gate OR
Or gate with And-ed inputs OR-A
Threshold element THRESH-L
Exclusive Or Gate XOR
Bitwise operation on the Integer data type

Read one bit BGET
Set one bit BSET
Memory Elements
Memory element SR
Memory element SR-AA
Memory element SR-AO
Memory element SR-D
Memory element SR-OA
Memory element SR-OO
Time Elements
Mono Function MONO
Sine Wave Oscillator OSC-SIN
Time Delay Off TOFF
Time Delay On TON
Time Delay On Retriggerable TON-RET
Trigger Element TRIGG
Register
Queue Register FIFO
Data Copying Element MOVE
Register REG
Group Data Register REG-G
Shift Register SHIFT
Switches
Switch SW
Switch SW-C
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Code Converters
Code Converter CONV
Code Converter CONV-BI
Code Converter CONV-IB
Function Parameter to Integer Conversion FPI
Two Integers to Integer Long Conversion IIL
Integer long to two Integers Conversion ILI
Multiplexers
Demultiplexer DEMUX-MI
Multiplexer MUX-I
Multiplexer MUX-MI
Multiplexer MUX-MN
Multiplexer MUX-N
Multiplexer MUXA-I
Arithmetic Elements
Absolute Value element ABS
Adder ADD
Adder with a multiplication ADD-MR
Divider DIV
Divider with multiplied inputs DIV-MR
Limiter LIM-N
Multiplier MUL
Integer scaling element MULDIV
Square root Element SQRT
Subtractor SUB
Counters
Counter COUNT
Comparators
Comparator COMP
Comparator COMP-R
Maximum Selector MAX
Minimum Selector MIN
Function Generators
Function Generator FUNG-1V
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Feedback and Filter

Algorithms
Average of n-samples AVG
Derivator DER
Single pole Filter FILT-1P
Single pole Filter for Integer signals FILTI
Integrator INT
PDP -controller PDP
PI-controller PI
PI controller with integer calculation PII
Ramp generator RAMP
S-ramp generator RAMP-S1
SSH-ramp generator RAMP-SSH
Communication Elements
ACS parameter read ACSPR
ACS parameter write ACSPW
Transmit and/or receive datasets to/ from ACSRX
an ACS 600 MultiDrive or ACS 600
SingleDrive.
Receive dataset from AF100 AFREC
Transmit dataset to AF100 AFTRA
Initialize DCB channels DCBINIT
Read dataset from DCB DCBRD
Receive and Transmit dataset from/to DCB DCBREC
board.
Receive and Transmit dataset from/to DCB DCBTRA
board.
Write dataset to DCB DCBWR
Diagnostic counters of the Drive Links DRDIAG
Reveceive signals from a drive DRREC
Transmit signals to a dri DRTRA
Send parameters to a drive DRPAR
Read parameters from a drive DRUPL
MasterBus 90 receive MB90REC
MasterBus 90 transmit MB90TRA
Receive and Transmit dataset from/to ACS ACSRX
600 MultiDrive or ACS 600 SingleDrive.
Panel controllerfor APC 700 PAN element PANCON
Receive from bus panel PANREC
Transmit to bus panel PANTRA
Status supervision
System load measurement SYSL
Memory monitoring RWM
Watchdog WDOG
Parameter handling elements

Parameter stored to FPROM PAR
Save parameter or reference value SAVE
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I/O handling elements

Read basic analog inputs AIAPC
Read extended Analog inputs AIEXT
Write to analog outputs on Speed Measurement AOMEAS
board
Write to extended analog outputs AOEXT
Read basic digital inputs DIAPC
Read extended digital inputs DIEXT
Write to basic digital outputs DOAPC
Write to extended digital outputs DOEXT
IO Bus read IOBUSRD
IO Bus write IOBUSWR
Read speed measurement SPEEDP
Event handling elements

Error reading from a drive DRFLT
Error recording element ERROR
Event recorder EVENT
Event logger EVLOG
Event recorder with acknowledgement EVT
Data logging elements

Datalogging element DATALOG
Other elements
Comment C
Data Base elements

ACS link ACS00, ACS01, ACS02
Boolean Data DAT(B)
Integer Data DAT(I)
IntegerInteger Data DAT(II)
IntegerLong Data DAT(IL)
Real Data DAT(R)
Drive Communication Board configuration DCB00
DI Calculated DIC
Drive link configuration DRL00
DataSet Peripheral DSP
Event Srt (Send) EVS(S)
Event logger configuration EVT00/EVT01
AF100 or MasterBus 90 configuration MB90
Panel link configuration PAN00
Boolean Param PARDAT(B)
Integer Param PARDAT(I)
IntegerLong Param PARDAT(IL)
Real Param PARDAT(R)
Memory reservation for saved values SAVE00
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3. SHORT FORM DESCRIPTION - FUNCTION ELEMENTS
Element Description
ABS Calculates the absolute value of an integer or a real number. The result is
multiplied by a scale factor.
ACSPR The element is used to read parameter values from an ACS 600 MultiDrive or
ACS 600 SingleDrive.
ACSPW The element is used to write parameter values to an ACS 600 MultiDrive or
ACS 600 SingleDrive.
ACSRX Transmit and reveive datasets to/from and ACS 600 MultiDrive or ACS 600
SingleDrive.
ADD Adds up to 19 integers or real numbers
ADD-MR Adds and subtracts signal values and multiplies the result by another value.
AFREC Receives a Data Set over the AF100 bus.
AFTRA Sends a Data Set over the AF100 bus.
AIAPC Reads basic analog input channels from the APC board.
AIEXT Reads analog input channels from the extension IO board.
AND Gives the boolean product of up to 19 boolean values
AND-O Performs a combination of the AND and OR functions on the input signal
groups.
AOEXT Writes to the analog output channels on the extension IO board.
AOMEAS Writes to the analog output channels on the speed measurement board.
AVG Calculates the average of a selected number of signal samples.
BGET Reads the value of the selected bit from an integer or integer long value.
BLOCK Module header for conditionally executed blocks.
BSET Sets the value of the selected bit in an integer or integer long value.
C Write comments in application program.
COMP Comparates two values with equal datatype
COMP-R Comparates two real numbers.
CONTRM Module header for control modules.
CONV Conversion of data between the types I, IL, R, T and TR.
CONV-BI Converts data in BC, BCD, 1-of-N code and Gray code given at a number of
boolean inputs into data in integer form (I or IL).
CONV-IB Converts data in integer form (I or IL) into data in BC, BCD, 1-of-N code
and Gray code at a number of boolean outputs.
COUNT Pre-settable counter for counting pulses, up or down. With checking of the
value relative to 0.
DATALOG Logs the selected data
DCBINIT Initializes the communication channels on the DCB.
DCBRD Reads a fraction of a dataset received from the DCB.
DCBREC Receives a dataset from the DCB.
DCBTRA Transmits a dataset to the DCB.
DCBWR Writes a fraction of a dataset for the DCB.
DEMUX-MI Signal demultiplexer with the memory.
DER Gives derivation effect. The element has inputs and outputs for limit values,
setting of gain, filter function for restricting the derivation effect and the
possibility of following and external reference.
DIAPC Reads basic digital input channels from the APC board.
DIEXT Reads digital input channels from the extension IO board.
DIV Divides two real numbers or two integers. For integers the quotient is obtained
along with the remainder at a separate output.
DIV-MR Performs compounded multiplication/division operations on the input signal
groups.
DOAPC Writes to the digital output channels on the APC board.
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Element Description
DOEXT Writes to the digital output channels on the extension IO board.
DRDIAG Displays and optionally clears the diagnostic counters of the drive links.
DRFLT Detects drive faults and writes them to the Event Logger.
DRPAR Sends parameter values to a drive controller (drive).
DRREC Receives signal values from a drive controller.
DRTRA Sends values for drive signals to a drive controller.
DRUPL Reads (drive) parameter values from a drive controller.
ERROR Writes detected error codes to the Event Logger.
EVENT Detects the boolean event and writes the associated information to the Event
Logger.
EVLOG Manages the Event Logger operation.
EVT Detects both edges of event signal, allows acknowledgement.
FIFO Queue register with up to 9 queues each with a maximum of 64 places.
FILT-1P 1-pole low-pass filter with options for limiting the output signal and for
following an external reference.
FILTI Single pole Filter for integer signals.
FPI Converts a function parameter value to a normal integer.
FUNCM Module header for function module.
FUNG-1V Generates a piece-wise linear function of one variable using tables, with up
to 255 elements.
IIL Packs two integers into an integer long value.
ILI Unpacks an integer long to two integer values.
INT Gives integration effect. The element has inputs and outputs for limit
values, setting of gain and following with an external reference.
INV Inverts a boolean value.
IOBUSRD Reads data from special boards via parallel I/O bus.
IOBUSWR Writes data to special boards via parallel I/O bus.
LIM-N Limits integers, real numbers or time values. Several limit values may be
selected.
MASTER Module header for master modules.
MAX Selects the largest of up to 19 integers or real numbers.
MB90REC Receives a Data Set over the MB90 bus.
MB90TRA Sends a Data Set over the MB90 bus.
MIN Selects the smallest of up to 19 integers or real numbers.
MONO Generates a pulse with a given duration when the input changes from 0 to 1.
The pulse duration is specified at an input. Retriggability is controlled with an
input.
MOVE Moves data from one place in the database to another.
MUL Multiplies of up to 19 integers or real numbers.
MULDIV Scaling element for the integer long data.
MUX-I Selector for up to 19 inputs. Integer address.
MUX-MI Selector for up to 19 inputs. Integer address and memory.
MUX-MN Selector for up to 19 inputs. 1-of-N address and memory.
MUX-N Data multiplexer with 1 out of N addressing.
MUXA-I Multiplexer for text arrays with integer addrress.
OR Gives the boolean sum of up to 19 boolean values.
OR-A Performs a combination of the AND and OR functions on the input signal
groups.
OSC-SIN Sine wave generator.
PANCON Panel controller element.
PANREC Receives a dataset from the panel link.
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Element Description
PANTRA Transmits a dataset over the panel link.
PAR Defines the parameter that can be modified by a tool and stored in the FPROM.
PCPGM Module header for program.
PDP Gives proportional effect and limited derivation effect. The element permits
limiting of the output signal and following.
PI Standard PI regulator for serial compensation in feedback systems. The element
permits limiting of the output signal and following.
PII PI controller for the signals represented as integers with the integer long
arithmetics.
RAMP Limits the rate of change of a signal. The element permits limiting of the
output signal and tracking.
RAMP-S1 Reference signal generator with the second derivative limitation.
RAMP-SSH Generates on S-shaped output signal when reaching the level of the input
signal.
REG Memory element with an optional number of positions.
REG-G Assembles simple variables into one single variable of group type.
RWM Monitors the memory.
SAVE Saves the signal/parameter value to the battery backed RWM area.
SHIFT Shift register with optional length.
SLAVEM Module header for a slave. Subordinate to a MASTER.
SPEEDP Calculates the speed and position measured with the YPH107 board.
SQRT Calculates the square root of a real number. The result is multiplied by a scale
factor.
SR Memory for boolean variables. The element has one Set and one Reset input.
SR-AA SR flip flop with combinatory S, R inputs: A for AND function.
SR-AO SR flip flop with combinatory S, R inputs. A for AND, O for OR function.
SR-D Memory for Boolean variables. The element has one Set and one Reset input
and data and clock inputs for clocking in data.
SR-OA SR flip flop with combinatory S, R inputs. A for AND, O for OR function.
SR-OO SR flip flop with combinatory S, R inputs. O for OR function.
SUB Subtracts one real number or one integer from another.
SW Switching element with up to 9 closing channels.
SW-C Switching elements with up to 9 change-over channels.
SYSL Calculates and indicates the system load.
THRESH-L Determines when more than a given number of boolean signals are set to 1.
TOFF Delay for turning a boolean signal off.
TON Delay for turning a boolean signal on.
TON-RET Delay for turning a boolean signal on with accumulating time measurement.
TRIGG Provides a pulse during one program cycle when the input signal changes from
0 to 1.
WDOG Watchdog functions for CPU and I/O-boards.
XOR Give a signal when just one of several input signals is true
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4. SHORT FORM DESCRIPTION - DATA BASE

ELEMENTS
Element Description
ACS00, ACS01, The elements are used to define the ACS communication boards, the types of
ACS02 the drives (ACS 600 MultiDrive or ACS 600 SingleDrive) connected to these
boards.
DAT(B) Boolean data value.
DAT(I) Integer data value.
DAT(II) Integer Integer data value.
DAT(IL) Integer long data value.
DAT(R) Real data value.
DCB00 Reserves memory for buffers of the DCB driver.
DIC Event channel element.
DRL00 Reserves memory for a drive link.
DSP Represents a block of data to be received or sent over AF100.
EVS(S) Transports time-tagged events.
EVT00/EVT01 Reserves the memory for Event Loggers.
MB90 Reserves memory and activates the MB 90/AF100 dataset driver.
PAN00 Reserves the memory and initiates the panel link.
PARDAT(B) Boolean parameter value.
PARDAT(I) Integer parameter value.
PARDAT(II) Integer Integer parameter value.
PARDAT(IL) Interger long parameter value.
PARDAT(R) Real parameter value.
SAVE00 Reserves the storage area in RWM memory to be used by the SAVE elements.
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5. EXECUTION TIMES FOR PC ELEMENTS

Recalculation Execution Times
Name Execution time, Typical (µs) Notes
ABS 14 C1 = I
39 C1 = IL
63 C1 = R
ACSPR
ACSPW
ACSRX 144 + 79 x C2 EN = 1
103 EN = 0
ADD 9 + 2 x C2 C1 = I
9 + 3 x C2 C1 = IL
32 xC2 C1 = R
ADD-MR 20 + 35 x C1 + 35 x C2
AFREC 97 + 12 x C1 + 9 x C2 + 9 x C3 ACT = 1
28 ACT = 0
AFTRA 108 + 12 x C1 + 9 x C2 + 9 x C3 ACT = 1
26 ACT = 0
AIAPC 187
AIEXT 55
AND* 7 + 2 x C1 (1.4 + 1.2 x C1), ( )

= "Inline" time
AND-O 16 + 3 x C1 + 3 x C2 + 3 x C3 + 3 x C4 +3 x C5 + 3 x C6
AOEXT 36
AOMEAS 41
AVG 45 C1 = I
69 C1 = IL
204 C1 = R
19 C1 = I & SET = 1
31 C1 = IL & SET = 1
75 C1 = R & SET = 1
BGET 12 C1 = I
12 C1 = IL
BLOCK 8
BSET 16 EN = 1
11 EN = 0
C
COMP 18 C1 = I, IL, B, T
20 C1 = R, TR
24 C1 = A
COMP-R 47 + 20 x (C1 + C2)
19
3AFY61281240

CONTRM 690
CONV 15 I → IL
44 I→R
49 I → T, TR
20 IL → I
52 IL → T, TR
39
R, TR → I, IL
81
R→T
19
129 R → TR
97 T → I, IL
15 T → R, TR
97 TR → R
TR → T
CONV-BI 37 + 3 x C3 C1 = I, C2 = 1 (BC → I)
45 + 6 x C3 C1 = I, IL C2 = 2 (BCD → I, IL)
31 + 3 x C3 C1 = I, IL C2 = 3 (1of N → I, IL)
39 + 7 x C3 C1 = I, IL C2 = 4 (Gray → I, IL)
40 + 3 x C3 C1 = I, IL C2 = 5 (16/32BC → I, IL)
40 + 3 x C3
C1 = IL, C2 = 1 (BC → IL)
15
R = 1 or L passive
CONV-IB 37 + 4 x C3 C1 = I, C2 = 1 (I → BC)
78 + 4 x C3 C1 = I, C2 = 2 I → BCD)
36 + 4 x C3 C1 = I, C2 = 3 (I → 1 of N)
32 + 5 x C3 C1 = IL, C2 = 2 (IL → BC)
78 + 5 x C3 C1 = IL, C2 = 2 (IL → BCD)
36 + 4 x C3
C1 = IL, C2 = 3 (IL → 1 of N)
13
R = 1 or L passive
COUNT 39 EN = 1 & R = 0
14 EN = 0 & R = 0
27 R=1
DATALOG 53 EN = 1 & CLEAR = 0
21 EN = 0 & CLEAR = 0
18 CLEAR = 1
DCBINIT 147
DCBRD 42 + 2 x C2 EN = 1
23 EN = 0
DCBREC 78 EN = 1
58 EN = 0
DCBTRA 101 EN = 1
50 EN = 0
DCBWR 36 + 2 x C2 EN = 1
16 EN = 0
DEMUX-MI 38 + 3 x C3 C1 = I, IL, B
40 + 3 x C3 C1 = R ,TR
39 + 3 x C3 C1 = T
40 R = 1 or L passive
20
3AFY61281240

DER 174 BAL = 0 & RDER = 0
68 BAL = 0 & RDER = 1
39 BAL = 1
DIAPC 127
DIEXT 56
DIV 22 C1 = I
54 C1 = IL
72 C1 = R
DIV-MR 49 x C1 + 49 x C2
DOAPC 11
DOEXT 59
DRDIAG
DRFLT 35 ACT = 1
23 ACT = 0
DRPAR 148 + 6 x C1 DWL active
76 + 5 x C1 DWL passive
DRREC 53 C1 = 0
44 + 8 x C2 C1 = 1
DRTRA 53 C1 = 0
44 + 8 x C2 C1 = 1 or C1 = 2
DRUPL 165 + 7 x C1 UPL active
86 + 10 x C1 UPL passive
ERROR 18 No events
47 events
EVENT 17 No events
127 events
EVLOG 127 ENABLE = 0
397 ENABLE = 1
EVT 28 ACK = 1
17 ACK = 0
FIFO 76 + 7 x C2 C1 = I
75 + 8 x C2 C1 = IL, R
90 + 14 x C2 C1 = B
77 + 11 x C2 C1 = T
74 + 10 x C2 C1 = TR
31 R=1
FILT-1P 215 BAL = 0
41 BAL = 1
FILTI 32
FPI 4
FUNCM 0
FUNG-1V 274 BAL = 0

241 BAL = 1
IIL 10
21
3AFY61281240

ILI 10
INT 123 BAL & RINT = 0

32 BAL or RINT = 1
INV 7
IOBUSRD 18 + 11 x C1 + 12 x C2 + 14 x (C3 +C4) EN = 1

5 EN = 0
IOBUSWR 18 + 11 x C1 + 12 x C2 + 14 x (C3 +C4) EN = 1
5 EN = 0
LIM-N 27 + 4 x C2 C1 = I
36 + 3 x C2 C1 = IL
42 + 3 x C2 C1 = R
37 + 3 x C2 C1 = T
39 + 3 x C2 C1 = TR
MASTER 690
MAX 17 + 5 x C2 C1 = I
21 + 7 x C2 C1 = IL
98 + 10 x C2 C1 = R
MB90REC 113 + 6 x C1 + 9 x C2 + 9 x C3 ACT = 1
29 ACT = 0
MB90TRA 123 + 7 x C1 + 9 x C2 + 9 x C3 ACT = 1
27 ACT = 0
MIN 17 + 5 x C2 C1 = I
21 + 7 x C2 C1 = IL
98 + 10 x C2 C1 = R
MONO 22
MOVE 9 + 3 x C2 C1 = I
7 + 4 x C2 C1 = IL, R
8 + 5 x C2 C1 = B
8 + 3 x C2 C1 = T
12 + 5 x C2 C1 = TR
MUL 4 + 6 x C2 C1 = I
27 x C2 C1 = IL
45 x C2 C1 = R
MULDIV 22
MUX-I 16 C1 = I
17 C1 = IL, R, B, TR
19 C1 = T
MUX-MI 28 C1 = I, IL, R
29 C1 = B, TR
31 C1 = T
19 RESET = 1
MUX-MN 32 + 2 x C2 C1 = I
33 + 2 x C2 C1 = IL, R, B, TR
36 + 2 x C2 C1 = T
27 RESET = 1
22
3AFY61281240

MUX-N 23 + 2 x C2 C1 = I, IL, R, B
26 + 2 x C2 C1 = T
24 + 2 x C2 C1 = TR
MUXA-I 35 C2 = 20
OR 7 + 2 x C1 (1.4 + 1.2 x C1), () = "Inline" time
OR-A 6 + 3 x (C1 + C2 + C3 + C4 + C5 + C6)
OSC-SIN 159 EN = 1
12 EN = 0
PANCON 173 U=1
119 U=0
PANREC 69 + 7 x C1 + 11 x C2 + 12 x C3 RESET = 0
76 RESET = 1
PANTRA 69 + 7 x C1 + 11 x C2 + 12 x C3 RESET = 0
76 RESET = 1
PAR 74 C1 = I
82 C1 = IL
90 C1 = R
41 S=0
PCPGM 690
PDP 261 BAL = 0

39 BAL = 1
PI 269 REVACT = 1
285 REVACT = 0
189 RINT = 1
PII 111 RESET = 0
30 RESET = 1
RAMP 201 BAL = 0
43 BAL = 1
RAMP-S1 897 BAL = 0
129 BAL = 1
RAMP-SSH 601 BAL = 0
105 BAL = 1
REG 21 + 5 x C2 C1 = I
19 + 6 x C2 C1 = IL, R, B
19 + 9 x C2 C1 = T
21 + 7 x C2 C1 = TR
16 S=0
REG-G 21 + 3 x C2 C1 = I
24 + 3 x C2 L1 = IL
25 +3 x C2 C1 = R
22 + 4 x C2 C1 = B
26 + 3 x C2 C1 = T
27 + 3 x C2 C1 = TR
22 S=0
23
3AFY61281240

RWM 28 SEL = -2 or -1
549 SEL = 0
86 SEL = XXY & Y = 0
60 SEL = XXY other conversions
SAVE 24 C1 = I, IL
25 C1 = R
26 C1 = B
17 EN = 0
SHIFT 20 C1 = I
22 L1 = IL, R
41 C1 = B
26 C1 = T, TR
21 R=1
SLAVEM 0
SPEEDP 227 C1 = I, IL
427 L1 = R
SQRT 161
SR* 10
SR-AA 13 + 2 x C1 + 2 x C2
SR-AO 13 + 2 x C1 + 2 x C22
SR-D 18 S=0&R=0
11 S = 1 or R = 1
SR-OA 13 + 2 x C1 + 2 x C2
SR-OO 13 + 2 x C1 + 2 x C2
SUB 11 C1 = I
13 C1 = IL
44 C1 = R
SW 17 + 5 x C2 C1 = I
18 + 6 x C2 C1 = IL, R, B
17 + 9 x C2 C1 = T
18 + 7 x C2 C1 = TR
10 ACT = 0
SW-C 14 + 6 x C2 C1 = I
13 +7 x C2 C1 = IL, R, B
13 + 10 x C2 C1 = T
14 + 8 x C2 C1 = TR
SYSL 48 C1 = 0
109 C1 = 1
TOFF 23 I=1
9 I=0
TON 21 I=1
9 I=0
24
3AFY61281240

TON-RET 25 I=1
18 I=0&R=0
9 I=0&R=1
TRIGG 11
WDOG 109 with one YPQ 111

62 without YPQ 111
XOR* 9 (3.5), ( ) = "inline" time
"inline" begin + 5.2 onetime overhead for a inline sequence!

end
*) these elements are available as "inline" code (see section 6.1 Space Requirements for
"Inline" Coded PC Elements)
In execution time calculation FCB uses formulas which are in bold text.
25
3AFY61281240
6. SPACE REQUIREMENTS FOR PC ELEMENTS

The following pages show the space requirements for PC elements when all the inputs of each
element are connected to the output of another element.
Name PC Statement(byte) Local Data Area(byte) Notes
ABS 12 2 C1 = I
4 C1 = IL
ACSPR
ACSPW
ACSRX
ADD 2 x C2 + 8 2 C1 = I
4 C1 = IL, R
ADD-MR 10 + 2C1 + 2C2 0
AFREC
AFTRA
AIAPC 22 30
AIEXT 20 2
AND 2 x C1 + 8 2
AND-O 12 + 6C1 +6C2 + X0

6C3 + 6C4 + 6C5 + 6C6
AOEXT 16 2
AOMEAS 16 2
AVG 16 12 + 2 x C2
BGET 12 0
BLOCK 10 2
BSET 16 0
COMP
COMP-R 4 x (C1 + C2) + 16 8 + 2 x (C1 +C2)
CONTRM 32
CONV
CONV-BI 2 x C3 + 22 6 C1 = I
8 C1 = IL
26
3AFY61281240

CONV-IB 2 x C3 + 22 12 + 2 x C3
COUNT 28 10 C1 = I
12 C1 = IL
DATALOG 36 22 + 2 x C2 XC1 = B, I
36 22 + 4 x C2 XC1 = IL, R
DCBINIT
DCBRD
DCBREC
DCBTRA
DCBWR
DEMUX-MI 20 + 2 x C2 X2
DER 32 44
DIAPC 18 18
DIEXT 48 6
DIV 16 4 C1 = I
8 C1 = IL
DIV-MR 8 + 2C1 + 2C2 0
DOAPC 8 0
DOEXT 28 2
DRDIAG
DRFLT 14 30
DRPAR X20 + 6 x C1 X24
DRREC X22 + 2 x C2 X38
DRTRA X20 + 2 x C2 X38
DRUPL 20 + 2 x C2 24
ERROR 12 84
EVENT 14 24
EVLOG 42 3684
EVT
27
3AFY61281240

FIFO 4 x C2 + 22 16 + 2 x (C2 + C2 x C3) C1 = I, B
16 + 4 x (C2 + C2 x C3) C1 = IL, R, T, TR
FILT-1P 12 12
FILTI 28 40
FPI
FUNCM 0 0
FUNG-1V 24 36
IIL 10 0
ILI 10 0
INT 30 28
INV 8 2
IOBUSRD
IOBUSWR
LIM-N 6 x C2 + 22 14 C1 = I
20 C1 = IL, R, T,TR
MASTER 32 4
MAX 2 x C2 + 12 4
MB90REC 22 + 2 x C1 + 2 x C2 + 2 x C3 14
MB90TRA 20 + 2 x C1 + 2 x C2 + 2 x C3 14
MIN 2 x C2 + 12 4 C1 = I
6 C1 = IL
MONO 16 12
MOVE 4 x C2 + 6 2 x C2 C1 = B, I
4 x C2 C1 = IL, R, T, TR
MUL 2 x C2 + 8 2 C1 = I
4 C1 = IL, R
MULDIV 14 0
MUX-I 2 x C2 + 12 4 C1 = B, I
6 C1 = IL, R, T, TR
MUX-MI 2 x C2 + 20 6 C1 = B, I
C1 = IL, R, T, TR
MUX-MN 4 x C2 + 18 6 C1 = B, I
8 C1 = IL,R, T, TR
MUX-N 10 + 2 X C2 0
28
3AFY61281240

MUXA-I 12 + 2 X C1 0
ACSRX
OR 2 x C1 + 8 2
OR-A 12 + 2C1 + 2C2 + 2C3
OSC-SIN 16 16
PANCON 50 52
PANREC 26 + 2C1 + 2C2 + 2C3 6
PANTRA 26 + 2C1 + 2C2 + 2C3 6
PAR 24 6
PCPGM 20 2
PDP 30 48
PI 36 36
PII 32 20
RAMP 32 52
RAMP-S1 42 54
RAMP-SSH 44 66
REG 4 x C2 + 14 2 + 2 x C2 C1 = B, I
2 + 4 x C2 C1 = IL, R, T, TR
REG-G 26 + 2 x C2 + 2 x C3 6 + 2 x C5 C1 = B, I
6 + 4 x C5 C1 = IL, R, T, TR
29
3AFY61281240

RWM
SAVE 20 4
SHIFT 22 2 + 2 x C2 C1 = B, I
2 + 4 x C2 C1 = IL, R, T, TR
SLAVEM - -
SPEEDP 48 X72
SQRT 12 6
SR 9 2
SR-AA 8 + 2C1 + 2C2 + 2C3 + 2C4 0

+ 2C5 + 2C6
SR-AO 8 + 2C1 + 2C2 + 2C3 + 2C4 0
+ 2C5 + 2C6
SR-D 16 4
SR-OA 8 + 2C1 + 2C2 + 2C3 + 2C4 0

+ 2C5 + 2C6
SR-OO 8 + 2C1 + 2C2 + 2C3 + 2C4 0
+ 2C5 + 2C6
SUB 12 2 C1 = I
4 C1 = IL, R
SW 4 x C2 + 8 2 x C2 C1 = B, I
4 x C2 C1 = IL, R, T, TR
SW-C 6 x C2 + 8 2 x C2 C1 = B, I
4 x C2 C1 = IL, R, T, TR
SYSL 8 + 8 x C1 8 + 6 x C1
TOFF 14 12
TON 14 12
TON-RET 16 12
TRIGG 10 4
WDOG
XOR 10 2
30
3AFY61281240
7. SPACE REQUIREMENTS FOR "Inline" CODE

Name PC Statement(byte) (inline) Local Data Area(byte) Notes
AND 4 2
OR 4 2
XOR 6 2
SR 8 2
"Inline" Connection Elements

INV 0 2
GET 4 2
PUT 10 2
Generation of "Inline" Code

It is the responsibility of the FCB to decide whenever it is possible to use "inline" PC elements
instead of the normal PC elements. From the user viewpoint there is no difference between a
normal PC element and the corresponding "inline" element.
"Inline" PC elements are used for speed optimization of binary operations.
31
3AFY61281240
PC ELEMENTS
Absolute Value Element ABS
Summary
ABS (ABSolute value) is used to obtain the absolute value of an integer or a K I (C1)
1 I
real number. The absolute value can be multiplied with an optional value. 2 K O 5
Figure 1. PC
Call ABS (C1) Element ABS
Call Parameters Table 1
Parameter Description Permissible values
C1 Data type I, IL, R
Connections Table 2
No Name Type Application
1 I IC1 Input. Input for number, whose absolute values is to be obtained.

2 K OC1 Input for multiplication factor K.
5 O OC1 Output. Output for the product input K and the absolute value of
value I.
Function
The value at input K is multiplied by the absolute value of input I and the result is stored at output O.
32
3AFY61281240
Read ACS Parameters ACSPR

Summary
The ACSPR (ACS Parameter Read) element is used to ACSPR (C1)
F1 DRNR
read parameter values from an ACS 600 MultiDrive or 1 EN ERR 5
ACS 600 SingleDrive. 2 > RESET RDY 6
3 > GET LINK 7
4 CNTRL
11 PAR1 VAL1 12
EC1 13
1 + 10 x C2 PAR x C2 VAL x C2 2 + 10 x C2
EC x C2 3 + 10 x C2
ERRC 99
Figure 1. PC Element ACSPR
Call ACSPR (C1,C2,C3) Table 1
C1 Block number 2 to 5 (or 2 if the target drive is ACS 600

SingleDrive)
C2 Number of parameters 1 to 8
C3 Data type of parameters I = Integer (normal or scaled, see Table 3 below)
R = Real
Connections Table 2
No Name Type Description Value
F1 DRNR II Target DRive NumbeR 1 to 12

1 EN IB ENable the block 0 or 1
2 RESET IB RESET the error code ERRC and ERR 0->1
3 GET IB GET parameter values 0->1
4 CNTRL II Operation CoNTRoL see Table 3
5 ERR OB ERRor in the FB or ACS link operation
6 RDY OB The read operation is ReaDY without
errors
7 LINK OI Current status of the ACS LINK see Table 4
11 PAR1 II PARameter number of the first
parameter
12 VAL1 OI VALue of the first partameter
13 EC1 OI Error Code of the first parameter see Table 6
n1 PARxC2 II PARameter number of the last (C2)
parameter
n2 VAL x C2 OI VALue of the last (C2) parameter
n3 EC x C2 OI Error Code of the last (C2) parameter see Table 6
99 ERRC OI ERRor Code of the whole block see Table 5
33
3AFY61281240
Bits of the CNTRL terminal Table 3
Bit # Description
0 If C3 = I and this bit = 1 then the data type of parameters is scaled integer.
Bit # Description
1 ACS link is broken
2 ACS link initialization (by the ACS comm board) after startup is not ready.
Initialisation of the ACS Links

Before ACSPR function blocks can be executed you must initialise (with DB elements ACS00,
ACS01 and ACS02) the ACS links to the drives that are used in the application program.
ACS01 is needed only if you have more than four drives and ACS02 is needed only if you have more
than eigth drives.
Use of a ACSPR Block

The target drive number of a ACSPR block is defined with the function parameter DRNR
(drives 1 to 4 are defined with DB element ACS00, drives 5 to 8 are defined with ACS01 and drives 9
to 12 are defined with ACS02, see the description of these DB elements).
Call parameter C1 defines the number (2 to 5 or 2 if ACS 600 SingleDrive) of the ACSPR block
(block number 1 is reserved for the "Basic" ACSRX block).
Every block number belongs to a drive and maximum number of blocks (ACSRX, ACSPR and
ACSPW) / drive is 5 (or 2 if ACS 600 SingleDrive).
The value of this call parameter is displayed inside the graphical ACSPR block by FCB.
Call parameter C2 defines the number (1 to 8) of the parameters.
Call parameter C3 defines the data type (Integer or Real) of all parameters of this block.
If the data type is integer and bit 0 of the CNTRL terminal is 1 then the data type is scaled integer.
The inputs PAR1 to PAR x C2 define the parameter numbers (number = 100 x group + index).
A 0->1 transition in the GET input starts the parameter read process (the actual reading is done as a
background operation while the other blocks are executing).
The RDY output is set to 0.
The read values of the parameters are in the VAL1 to VAL*C2 outputs. These values have been read
from the target drive after the previous execution of the ACSPR block (they are not read from the
drive during the current execution of this block).
The receipt of new valid values from all parameters of the ACSPR block is acknowledged by setting
the RDY output to 1 (it remains in this state until a new parameter read is started).
Error handling
Whole Block
In an error situation the ERR output is set to 1 and the ERRC output indicates the applicable error
code (see Table 5).
Errors are originated either from the execution of the ACSPR block itself (error codes 70nn to 82nn)
or from the DB element ACS0n that defines the target drive of the ACSPR block (error codes 87nn to
89nn).
34
3AFY61281240
The ERR and ERRC outputs retain the status of the last occurred error.
A 0->1 transition in the RESET input clears the ERR and ERRC outputs if the error situation is no
more in effect (because the ERR output does not automatically go to the 0 state when the error
disappears, it is possible that the ERR and RDY outputs are in the 1 state at the same time).
A new parameter read operation can be started without clearing of the ERR and ERRC outputs (if the
error situation is still in effect then the read operation does not start and there is error code 30 in the
ECn outputs, see Table 6).
Error Codes (ERRC) Table 5

Error code = 7000 + error_number 34 (see below) or
Error code = 7000 + drive_number (1 to 12) x 100 + error_number (see below) or
Error code = 8700 + ACS0n_number (0 to 2) x 100 + error_number (see below)
Error # Description
1 Invalid drive type definition (DRTYPEn) in DB element ACS0n

2 ACS 600 MultiDrive(s) specified in ACS00 but the first ACS communication board is
YPQ112B
3 ACS communication board should be YPQ112B but it is YPQ112A
4 The first ACS communication board is missing
5 Invalid first ACS communication board YPQ112B
6 The third ACS communication board is missing
7 Invalid first ACS communication board YPQ112A
8 Invalid board (other than YPQ112A or YPQ112B)
9 Invalid second ACS communication board YPQ112B
10 The second ACS communication board is missing
11 Invalid third ACS communication board YPQ112B
12 DB element ACS01 without ACS00
13 DB element ACS02 but the first ACS communication board is YPQ112A
16 Initialization error in ACS communication board
31 Call parameter C1 is not in the range 2 to 5 (or 2 if ACS 600 SingleDrive)
32 Call parameter C2 is not in the range 1 to 8
33 ACS link timeout
34 Drive number (DRNR) is not in the range 1 to 12
35 DB element ACS00 does not exist
38 This block number (C1) is already in use with this drive (DRNR)
50 Application IDs in the DB element (APPIDn) and in the drive are different
52 Call parameter C3 is neither I nor R
35
3AFY61281240
Individual Parameters
The ECn outputs indicate the statuses of individual parameter read operations (see Table 6).
The ECn outputs retain their codes until a new parameter read is started
(a 0->1 transition in the RESET input does not clear ECn outputs).
Error Codes (ECn) Table 6
Error Code Description
0 Value is OK. No errors found

2 Parameter number PARn does not exist in the drive
4 Communication break
30 Cannot start the read operation (reason: see the ERRC output of this block)
31 The read operation is in progress.
32 Parameter number PARn has been changed during the read operation
33 Parameter type (the CNTRL input) has been changed during the read operation
40 Communication error in ACS communication board
Related documents
Description of DB elements ACS00, ACS01 and ACS02.
36
3AFY61281240
Write ACS Parameters ACSPW

Summary
The ACSPW (ACS Parameter Write) element is used to ACSPW (C1)
F1 DRNR
write parameter values to an ACS 600 MultiDrive or ACS 1 EN ERR 5
600 SingleDrive. 2 > RESET RDY 6
3 > PUT LINK 7
4 CNTRL
11 PAR1
12 VAL1 EC1 13
1 + 10 x C2 PAR x C2
2 + 10 X C2 VAL x C2 EC x C2 3 + 10 x C2
ERRC 99
Figure 1. PC Element ACSPW
Call ACSPW (C1,C2,C3) Table 1
C1 Block number 2 to 5 (or 2 if the target drive is ACS 600

SingleDrive)
C2 Number of parameters 1 to 8
C3 Data type of parameters I = Integer (normal or scaled, see Table 3 below)R =
Real
Connections Table 2

2 RESET IB RESET the error code ERRC and ERR 0->1
3 PUT IB GET parameter values 0->1
6 RDY OB The read operation is ReaDY without
errors
11 PAR1 II PARameter number of the first
parameter
12 VAL1 II Parameter VALue of the first parameter
13 EC1 OI Error Code of the first parameter see Table 6
n1 PAR*C2 II PARameter number of the last (C2)
parameter
n2 VAL*C2 II Parameter VALue of the last (C2)
parameter
n3 EC*C2 OI Error Code of the last (C2) parameter see Table 6
99 ERRC OI ERRor Code of the whole block see Table 5
37
3AFY61281240
Bit # Description
Bits of the LINK terminal Table 4
Bit # Description
0 ACS link is OK
2 ACS link initialization (by the ACS comm board) after startup is not ready

Before ACSPW function blocks can be executed you must initialise (with DB elements ACS00,
than eigth drives.
Use of a ACSPW Block

The target drive number of a ACSPW block is defined with the function parameter DRNR
(drives 1...4 are defined with DB element ACS00, drives 5...8 are defined with ACS01 and drives
9...12 are defined with ACS02, see the description of these DB elements).
Call parameter C1 defines the number (2...5 or 2 if ACS 600 SingleDrive) of the ACSPW block
(block number 1 is reserved for the "Basic" ACSRX block).
Every block number belongs to a drive and maximum number of blocks (ACSRX, ACSPR and
ACSPW) / drive is 5 (or 2 if ACS 600 SingleDrive).
The value of this call parameter is displayed inside the graphical ACSPW block by FCB.
Call parameter C2 defines the number (1...8) of the parameters.
Call parameter C3 defines the data type (Integer or Real) of all parameters of this block.
If the data type is integer and bit 0 of the CNTRL terminal is 1 then the data type is scaled integer.
The inputs PAR1...PAR*C2 define the parameter numbers (number = 100*group + index).
The new values of the parameters are in the VAL1...VAL*C2 inputs.
A 0->1 transition in the PUT input starts the parameter write process (the actual writing is done as a
background operation while the other blocks are executing).
The RDY output is set to 0.
Successfull write of all parameters is acknowledged by setting the RDY output to 1 (it remains in this
state until a new parameter write is started).
Error handling
Whole Block
code (see Table 5).
Errors are originated either from the execution of the ACSPW block itself (error codes 70nn...82nn)
or from the DB element ACS0n that defines the target drive of the ACSPW block (error codes
87nn...89nn).
38
3AFY61281240
The ERR and ERRC outputs retain the status of the last occurred error.
A 0->1 transition in the RESET input clears the ERR and ERRC outputs if the error situation is no
more in effect (because the ERR output does not automatically go to the 0 state when the error
disappears, it is possible that the ERR and RDY outputs are in the 1 state at the same time).
A new parameter write operation can be started without clearing of the ERR and ERRC outputs (if the
error situation is still in effect then the write operation does not start and there is error code 30 in the
ECn outputs, see Table 6).
Error Codes (ERRC) Table 5

Error code = 7000 + drive_number (1...12) * 100 + error_number (see below) or
Error code = 8700 + ACS0n_number (0...2) * 100 + error_number (see below)
Error # Description

2 ACS 600 MultiDrive specified in ACS00 but the first comm board is YPQ112b
3 ACS communication board should be YPQ112b but it is YPQ112a
5 Invalid first ACS communication board YPQ112b
7 Invalid first ACS communication board YPQ112a
8 Invalid board (other than YPQ112a or YPQ112b)
9 Invalid second ACS communication board YPQ112b
11 Invalid third ACS communication board YPQ112b
13 DB element ACS02 but the first ACS communication board is YPQ112a
31 Call parameter C1 is not in the range 2...5 (or 2 if ACS 600 SingleDrive)
32 Call parameter C2 is not in the range 1...8
33 ACS link timeout
34 Drive number (DRNR) is not in the range 1...12
50 Application IDs in the DB element (APPIDn) and in the drive are
52 Call parameter C3 is neither I or R
Individual Parameters
The ECn outputs indicate the statuses of individual parameter write operations (see Table 6).
The ECn outputs retain their codes until a new parameter write is started
(a 0->1 transition in the RESET input does not clear ECn outputs).
Error Codes (ECn) Table 6
0 The write operation was OK. No errors found

2 Parameter number PARn does not exist in the drive
3 Parameter value VALn is invalid
4 Communication break
39
3AFY61281240
30 Cannot start the write operation (reason: see the ERRC output of this block)
31 The write operation is in progress
32 Parameter number PARn has been changed during the write operation
33 Parameter type (the CNTRL input) has been changed during the write
operation
40 Communication error in ACS communication board
Related documents
40
3AFY61281240
Transmit/Receive ACS Datasets ACSRX

Summary
The ACSRX (ACS Receive Xmit) element is used to ACSRX C1
transmit and/or receive datasets to/from an ACS 600 F1 DRNR
MultiDrive or ACS 600 SingleDrive. 1 EN ERR 4
2 > RESET RDY 5
3 CNTRL LINK 6
21 DS1
22 WR1
23 I11 O11 26
24 I21 O21 27
25 I31 O31 28
11+10*C2 DS*C2
12+10*C2 WR*C2
13+10*C2 I1*C2 O1*C2 16+10*C
14+10*C2 I2*C2 O2*C2 17+10*C
15+10*C2 I3*C2 O3*C2 18+10*C
ERRC 99
Figure 1. PC Element
ACSRX
Call ACSRX (C1,C2) Table 1
Parameter Description Permissible Values
C1 Block number 1 = basic block

2 to 5 (or 2 if the target drive is ACS 600 SingleDrive) =
other block
C2 Number of datasets 1 to 4
Connections Table 2

2 RESET IB RESET the error code ERRC 0->1
5 RDY OB Data ReaDY. New valid data received
21 DS1 II DataSet number of the first transmit dataset 1 to 254
22 WR1 IB Enable the WRite of the first transmit dataset 0 or 1
23 I11 II First Integer of the first transmit dataset
24 I21 II Second Integer of the first transmit dataset
25 I31 II Third Integer of the first transmit dataset
26 O11 OI First integer of the first received dataset
27 O21 OI Second integer of the first received dataset
28 O31 OI Third integer of the first received dataset
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Table 2 continued
n1 DS*C2 II DataSet number of the last (C2) transmit 1 to 254

dataset
n2 WR*C2 IB Enable the WRite of the last (C2) transmit 0 or 1
dataset
n3 I1*C2 II First integer of the last (C2) transmit dataset
n4 I2*C2 II Second integer of the last (C2) transmit
dataset
n5 I3*C2 II Third integer of the last (C2) transmit dataset
n6 O1*C2 OI First integer of the last (C2) received dataset
n7 O2*C2 OI Second integer of the last (C2) received
dataset
n8 O3*C2 OI Third integer of the last (C2) received dataset
99 ERRC OI ERRor Code see Table 5
Bit # Description
0 This block is a synchronizing block (this block must be a "Basic" block, too)
Bits of the LINK terminal Table 4
Bit # Description
0 ACS link is OK
2 ACS link initialization (by the ACS comm board) after startup is not ready

Before ACSRX function blocks can be executed you must initialise (with DB elements ACS00,
than eigth drives.
Use of a ACSRX Block

The target drive number of a ACSRX block is defined with the function parameter DRNR
(drives 1 to 4 are defined with DB element ACS00, drives 5 to 8 are defined with ACS01 and drives 9
to 12 are defined with ACS02, see the description of these DB elements).
Call parameter C1 defines the number of the ACSRX block:

- 1 = Basic (of this DRNR)
- 2 to 5 (or 2 if ACS 600 SingleDrive) = Other (of this DRNR)
Every drive that is used in the application program has a "Basic" ACSRX block (and optional "Other"
ACSRX blocks) of its own.
Maximum number of blocks (ACSRX, ACSPR and ACSPW) / drive is 5 (or 2 if ACS 600
SingleDrive).
The value of this call parameter is displayed inside the graphical ACSRX block by FCB.
Call parameter C2 defines the number (1...4) of the transmit datasets.
The inputs DS1 to DS*C2 define the dataset numbers (1 to 254) of the transmit datasets.
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3AFY61281240
The values of the transmit datasets are in the I11...I3*C2 inputs. One dataset contains always three 16
bit integers. If other number types are needed then these must be packed/unpacked in the APC by
using e.g. function blocks IIL, ILI and CONV.
If the WR input of a transmit dataset is set to 1 then the ACSRX block transmits the values of this
dataset to the target drive and automatically receives the values of a dataset whose dataset number =
transmit dataset number + 1 (a ACSRX block only starts this transmit/receive process during its
execution and the actual transmitting/receiving is done as a background operation while the other
blocks are executing).
If the WR input of a transmit dataset is set to 0 then the ACSRX block does not transmit the values of
this dataset to the target drive but only reads the values of a dataset whose dataset number = transmit
dataset number + 1.
The values of the received datasets are in the O11...O3*C2 outputs. These values have been received
from the target drive after the previous execution of the ACSRX block (they are not read from the
drive during the current execution of this block).
The receipt of new valid values from all receive datasets of the ACSRX block is acknowledged by
setting the RDY output to 1 for one execution cycle of this block. This output is set to 0 if new valid
dataset values have not been received since the last execution of this block (either the cycle time of
this block is too short or the ACS communication link is invalid).
Note: Application programs both in the APC and in the target drive must interpret the meaning of the
values in the transmit and receive datasets in the same way. This is left on the responsibility of the
application programmer(s).
The Application Identifier (a 16 bit integer defined by the drive application programmer) of the target
drive application assists in verifying the correct meaning of the dataset values (see the APPIDn inputs
in the ACS DB elements and error number 50 in Table 5).
Execution Sequence of the ACSRX Blocks of a ACS Comm Board

The ACS communication time of a ACS communication board is divided into fixed-length time slots.
The length of a time slot = the time that is needed to process all datasets in all "Basic" blocks of the
drives that are connected to this communication board.
Every second time slot is always reserved for all datasets in all "Basic" blocks.
Every second time slot is reserved for the datasets in the "Other" blocks and for other ACS
communication (if the number of all "Other" datasets is greater or equal than the number of all
"Basic" datasets then two or more two-slot sequences are needed to process all "Other" datasets).
This time slot sequence is illustrated in Figure 2:
All All All →

“Basic” datasets “Basic” datasets “Basic” datasets
Part of (or all) Part of (or all) →
“Other”datasets “Other”datasets
Figure 2. Processing of the Datasets of the ACSRX Blocks of a ACS Comm Board
Synchronization of the ACSRX Blocks of a ACS Comm Board

If bit 0 in the CNTRL inputs of all "Basic" blocks of a ACS communication board is set to 0 then the
ACSRX communication in this communication board is freewheeling (as described in the previous
chapter).
If bit 0 in the CNTRL input of one "Basic" block is set to 1 then all ACSRX communication in this
communication board is frozen until this "Basic" block has been executed (the EN input of this block
must be set to 1). Execution of this synchronizing block starts the time slot for all "Basic" blocks and
after that slot all "Other" blocks are processed once.
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3AFY61281240
This ACSRX communication sequence is repeated every time the synchronizing block is executed.
Note 1: The cycle time of the synchronizing block must be longer than the time it takes to process all
ACSRX blocks of this communication board (if it is shorter then the ACSRX communication is
freewheeling). This is left on the responsibility of the application programmer.
The RDY output of an "Other" block can be used to check that the cycle time is long enough.
Note 2: If more than four drives are used then the synchronization between the ACS communication
boards is left on the responsibility of the application programmer.
Error handling
code (see Table 5).
Errors are originated either from the execution of the ACSRX block itself (error codes 70nn to 82nn)
or from the DB element ACS0n that defines the target drive of the ACSRX block (error codes 87nn to
89nn).
The ERR output is set to 0 with the first successful response.

The ERRC output retains the code of the last occurred error. A 0->1 transition in the RESET input
clears the ERRC output if the error situation is no more in effect.
Error Codes Table 5

Error code = 7000 + drive_number (1 to 12) * 100 + error_number (see below) or
Error code = 8700 + ACS0n_number (0...2) * 100 + error_number (see below)
Error # Description

2 ACS 600 MultiDrive(s) specified in ACS00 but the first ACS communication board is
YPQ112B
3 ACS communication board should be YPQ112b but it is YPQ112A
5 Invalid first ACS communication board YPQ112B
7 Invalid first ACS communication board YPQ112A
8 Invalid board (other than YPQ112A or YPQ112B)
9 Invalid second ACS communication board YPQ112B
11 Invalid third ACS communication board YPQ112B
13 DB element ACS02 but the first ACS communication board is YPQ112A
31 Call parameter C1 is not in the range 1 to 5 (or 1 to 2 if ACS 600 SingleDrive)
32 Call parameter C2 is not in the range 1 to 4
33 ACS link timeout
34 Drive number (DRNR) is not in the range 1 to 12
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Error # Description
39 Dataset number (DSn) is not in the range 1 to 254

40 to 49 Communication error in ACS communication board
50 Application IDs in the DB element (APPIDn) and in the drive are different
Related documents
45
3AFY61281240
Adder ADD
Summary
ADD is used to calculate the sum of up to 19 integers or real numbers. 1 + 20
2
C2
Call ADD (C1, C2) ADD

C2 Number of inputs 2 to 19
Connections Table 2
1 - IC1 Input for addend.

2 - IC1 Input for addend.
.
.
.
C - IC1 Input for addend.
20 - OC1 Output for sum.
Function
The values at inputs 1 to C2 are added and the sum is stored at output 20.
Overflow
If the maximum positive or negative values are exceeded, the output islimited to the highest or lowest
allowable value for the data type.
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3AFY61281240
Adder ADD-MR
Summary
ADDer with Multiplier of Real numbers is used for the addition of an 1 50
optional number of real numbers. The numbers are added in
*
two groups, each of a maximum of 19 numbers, after which the second 11
.. +
group is subtracted from the first. The result is multiplied with a real
10 + C1
number.
31 -
.. -
30 + C2 -
Call ADD-MR (C1,C2) ADD-MR
Parameter Significance Permissible values
C1 Number of positive inputs in the 1 to 19

addition element.
C2 Number of negative inputs in the 1 to 19
addition element.
Connections Table 2
No Name Type Description Values
1 - IR Input for the multiplication factor.

11 - IR Input for augend with positive weight factor.
12 - IR Input for addend with positive weight factor.
...
10+C1 - IR Input for addend with positive weight factor.
31 - IR Input for augend with negative weight factor.
32 - IR Input for addend with negative weight factor.
...
30+C2 - IR Input for addend with negative weight factor.
50 - OB Output for result.
Function
The sum of the real numbers at the inputs 31 to 30 + C2 is subtracted from the sum of the inputs 11 to
10 + C1. The result is multiplied with the value at input 1. The result is stored at the output 50.
Overflow
If the maximum positive or negative real number is exceeded, the output is limited to the greatest or
lowest representable value respectively.
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DataSet receiver for AF100 AFREC

Summary
Advant Fieldbus 100 RECeive element is used to receive data on the AFREC
high speed serial bus AF100. Data types are determined by the call F1 IDENT ERR 10
parameters and can be I, IL, or R and should equal the call parameters F2 STATION RDY 11
of the transmitting AFTRA function block. The AFREC function block 1 ACT
can be used to trigger interrupt events. I1 21
I... 20 + ...
I*C1 20 + C1
IL1 51
IL... 50 + ...
IL*C2 50 + C2
R1 71
R... 70 +...
RC3 70 + C3
ERRC 99
Call AFREC (C1, C2, C3)
Figure 1. PC
Element AFREC
C1 Number of I values. 0 to 8
C2 Number of IL values 0 to 8
C3 Number of R values 0 to 8
Where: 0 < C1 + C 2 + C 3 ≤ 8
Connections Table 2
F1 IDENT II Dataset IDENTity number. 1 to 50

F2 STATION II Node number of the sender. 1 to 79
1 ACT IB Input. ACTivates dataset reception. 1=active
10 ERR OB Communication ERRor.
11 RDY OB Output data has been updated.
21 I1 OI Output. I value number 1.
...
20+C1 IC1 OI Output. I value number C1.
51 IL1 OIL Output. IL value number 1.
...
50+C2 ILC2 OIL Output. IL value number C2.
71 R1 OR Output. R value number 1.
...
70+C3 RC3 OR Output. R value number C3.
99 ERRC OI ERRor Code. * see Table 3
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Error Codes Table 3
Error Code # Description
Communication startup errors:

3001 Bus coupler hardware missing.
3002 Bus coupler self-test failed.
3003 Not enough memory available in system-RWM.
3004 DB-element MB90 missing.
3005 Station address in the hardware is not equal to the NODE parameter of the
database element MB90.
3101 Signal address already reserved (by another function block in the same
APC)
3102 STATION value is equal to the address defined in the MB90 database
element.
3103 Illegal Function parameter.
3104 Illegal Call parameter.
3201 Communication port cannot be allocated for the dataset
3401 Time-out waiting for a BA. to request or to confirm the dataset
configuration
Run time errors (may occur even after successful start-up):
3402 Time-out waiting for address frames from the BA.

3403 No response to address frame from the data source station
3501 CRC-error (data frame corrupted during transfer)
When recorded in the error logs, the first two digits of an error code (above) are translated to texts:
3000 to 3099 MB90 START FAILED

3100 to 3199 MB90 DATASET REJ.
3200 to 3299 MB90 FULL (LOCAL)
3400 to 3499 MB90 PARTNER FAIL
3500 to 3599 MB90 DISTURBANCE
Function
Upon initialization the AFREC function block:
• Checks that the DB-element has been initialized.

• Checks the existence and condition of the bus coupler.
• Checks the legality of the IDENT and STATION parameters.
• Allocates a communication port for the dataset.
The dataset is introduced if necessary to the Bus Administrator. The specified dataset should be sent
from an APC by a AFTRA function block or from a Advant Controller 110 station using the dataset
database element.
AFREC captures from AF100 the dataset telegrams tagged with the specified signal address. The
signal address is computed using the STATION and IDENT parameters.
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3AFY61281240
To enable the receive function of a communication port, the STATION and IDENT of the AFREC
function block must equal the station and ident numbers found in the sending block. Additionally, the
length of the telegram must equal the length specified by the AFREC function block. Identical values
for call parameters should therefore be used in transmitting and receiving blocks (to avoid
mismatching length values).
The STATION parameter of the AFREC must be equal to the NODE value of MB90 DB-element in
the sending station. The IDENT parameter must be equal to IDENT of the sending AFTRA.
RDY is set (to 1) if a new data set telegram was transferred after the previous execution, and the
output terminals were updated. Updating of output data (and all other output pins as well) can be
temporarily or permanently disabled by resetting the input ACT (to 0).
Boolean values must be unpacked from integers ( I ) or long integers (IL). Packed booleans from
Advant Controller 110 stations must be unpacked from pairs of integers or long integers. All data
types on AFREC and Advant Controller 110 stations occupy 4 bytes even if integer (I) data types are
used. The order of the data in the dataset received by the AFREC function block is always: I values, IL
values, and then R values. It is important to keep track of this order when receiving from Advant
Controller 110 stations. When receiving integers (I) sent by MB90TRA, the first, third, fifth etc.
integer is not available.
Fault Handling
The ERR output is set (to 1) when a reception does not occur within 4 receiving intervals. A
diagnostic error code is loaded to output ERRC (see table 3). The ERR output will reset (to 0) or set
(to 1) depending on the communication status, but the last error code will always remain at the ERRC
output even when ERR is reset (ERRC is assumed to be cleared by specific action using the tools,
during the next restart of the station, or by a 0-pulse in the ACT-pin.)
A mismatch between the NODE value and hardware switch settings disables all dataset
communications from and to the station. However, service communications to the station are still
possible via MB90.
During communication start-up the ERRC output may contain the value -1. This indicates only that
the configuration message has not been received from the bus administrator and is not an error
condition.
Event Triggering
Note: This feature is available only in releases 1.1 and later.
In each APC station there can be one (and only one) AFREC, AFTRA, MB90REC, or MB90TRA
function block that specifies an interrupting dataset. A negative value on the IDENT input is used to
denote that the transfer of the dataset should cause an interrupt and start an event driven application
task in the station. A AFREC or AFTRA function block with a negative IDENT input will operate,
with respect to data transfer, exactly the same as if the IDENT was positive. The bus administrator
does not know of the existence of dataset interrupts.
AFREC will be typically used. to specify the triggering dataset, although AFTRA may be used as well.
In each APC station there can be only one control module CONTRM that is executed due to interrupts
from AF100. This CONTRM must have C2 defined as 255 (denotes event task) and C3 defined as 2
(MB90 event task).
50
3AFY61281240
The event triggering AFREC function block will normally reside in the MB90 event CONTRM. This
minimizes the delay between the physical data received and the actual updating of the output data of
the AFREC function block.
Note: that the first event triggered by a AF function block is generated after the configuration
message is received from the Bus Administrator. This first event does not signify that data has been
captured by the AF bus coupler.
The input ACT of the interrupting dataset function block must never be reset (to 0), otherwise the
following deadlock situation will occur:
• the respective dataset will be discarded.

• no MB90 interrupts will be generated.
• the event task will no longer be executed.
• if the AF function block is contained under the event CONTRM then setting ACT (to 1 from 0)
will have no effect. If the function block is outside the event task, then setting the ACT input (to 1
from 0) will enable events to be triggered.
It is not necessary that the interrupting dataset is the same in all APC stations.
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DataSet transmitter for AF100 AFTRA

Summary
Advant Fieldbus 100 TRAnsmit element is used to cyclically send AFTRA
data on the high speed serial bus. The data values are updated F1 IDENT ERR 10
each time the function block is executed. The actual cyclic F2 SCAN
transmission of the data is independent of the function block 1 ACT
execution. However, the sending interval is configured by this 21 ERRC 99
I1
block. Data types are determined by the call parameters and 20 + ... I...
can be I, IL, or R. 20 + C1 I*C1
51 IL1
50 + ... IL...
50 + C2 IL*C2
71 R1
70 +... R...
Call AFTRA (C1, C2, C3) 70 + C3 RC3
Figure 1. PC
Call Parameters Table 1 Element AFTRA
Where: 0 < C1 + C 2 + C 3 ≤ 8
Connections Table 2

F2 SCAN II Transmission interval. 1 to 4096 ms
See table 3
1 ACT IB Input. ACTivates dataset transmission. 1=Active
21 I1 II Input. I value number 1.
...
20+C1 IC1 II Input. I value number C1
51 IL1 IIL Input. IL value number 1.
...
50+C2 ILC2 IIL Input. IL value number C2.
71 R1 IR Input. R value number 1.
...
70+C3 RC3 IR Input. R value number C3.
99 ERRC OI ERRor Code. see Table 4
52
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SCAN Values Table 3
Value of SCAN Actual transmission interval used
1 1
2 2
3 to 5 4
6 to 11 8
12 to 23 16
24 to 47 32
48 to 95 64
96 to 191 128
192 to 383 256
384 to 767 512
768 to 1535 1024
1536 to 3071 2048
3072 to 4096 4096
ErrorCodes Table 4

3005 Station address in the hardware is not equal to the NODE parameter of the
database element MB90.
3101 Signal address already reserved (by another function block in the same
APC).
3103 Illegal IDENT-value.
3104 Illegal (Call) Parameter or SCAN-value.
3105 More than one interrupting dataset.
3201 Communication port cannot be allocated for the dataset.
3301 Time slots cannot be allocated for the dataset.
3302 Dataset identifier reserved by another station.
3401 Time-out waiting for a BA to request or to confirm the dataset
configuration.

3300 to 3399 MB90 FULL(GLOBAL)
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Function
Upon initialization the AFTRA function block:

The dataset is introduced to the Bus Administrator. After approval, the transmission of the dataset is
started instantaneously, and repeated at intervals as determined by the parameter SCAN.
Time-out of approval message and/or disappearance of cyclic time slots for the dataset will be detected
and signaled at AFTRA error pins.
The dataset configured by a AFTRA function block can be received by AFREC function blocks in
other APCs or by a dataset database element in a Advant Controller 100 station. Each AFTRA
IDENT value should be unique for a station. To be received correctly there should be at the other end
of a link a receiver block AFREC with identical call parameter and IDENT values. The STATION
value of the receiving block must equal the station number of the transmitting APC.
The station numbers of transmitting stations are declared using the NODE parameter of the DB
element MB90. The matching address value must be also set on the AF100 bus coupler board
(YPK112A) using the provided hardware switches. If the NODE value is 127 or 255, all hardware
settings (within supported address range 1 to 79 = 00H to 4FH) are correct, and the station number for
AFTRA is copied from the hardware switches. (Note: Hardware address switches are read as
hexadecimal values, e.g., station 33 must be 21H in the set -up switches.)
SCAN determines the transmission interval for the dataset on AF100 (i.e., how often the data values
are transmitted). See table 3 for possible values. The transmission interval can be clearly shorter than
the execution interval of AFTRA provided there is capacity on AF100. (Or the opposite case, if
AF100 is severely loaded, there is free capacity available in APC, and the transmission delays should
be minimal.)
Transmission can be initially and/or dynamically deactivated by reseting (to 0) the input ACT. Even
then the AFTRA function block will present a dataset to the bus administrator and a communication
port is locally reserved in the dual port memory of YPK112A. However, the transmit function
associated with the signal address will be disabled, and therefore the receiving blocks in other stations
will show an error.
Boolean values must be packed into integers ( I ) or long integers (IL). Packed booleans intended for
Advant Controller 100 stations must be packed to long integers. All data items sent by AFTRA always
occupies 4 bytes. The order of the data in the dataset sent by the AFTRA function block is always: I
values, IL values, and then R values. It is important to keep track of this order when transmitting to
Advant Controller 100 stations. It is recommended not to use integer (I) values, because then the first,
third, fifth, etc. word of the transmitted telegrams will not be utilized.
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3AFY61281240
Fault Handling
The ERR output is set (to 1) when a transmission does not occur within 4 sending intervals as defined
by cycle time of the function block. A diagnostic error code is loaded to output ERRC (see table 4).
The ERR output will reset (to 0) or set (to 1) depending on the communication status, but the last
error code will always remain at the ERRC output even when ERR is reset (ERRC is assumed to be
cleared by specific action using the tools during the next restart of the station or by a zero-pulse in the
ACT-pin).
possible via AF100.
condition.
Event Triggering
In each APC station there can be one (and only one) AFREC or AFTRA function block that specifies
an inter-rupting dataset. A negative value on the IDENT input is used to denote that the transfer of
the dataset should cause an interrupt and start an event driven application task in the station. A
AFREC or AFTRA function block with a negative IDENT input will operate, with respect to data
transfer, exactly the same as if the IDENT was positive. The bus administrator does not know of the
existence of dataset interrupts.
AFTRA may be used to specify the event triggering dataset, although AFREC or MB90REC will be
typically used.
from AF100. This CONTRM must have C2 defined as 255 (denotes event task) and
C3 defined as 2 (MB90 event task).
The event triggering AFTRA function block will normally reside in the MB90 event CONTRM. This
minimizes the delay between the physical data transmitted and the actual updating of data for next
transmission.
Note: that the first event triggered by a AF100 function block is generated after the configuration
message is received from the Bus Administrator. This first event does not signify that actual data has
been sent by the AF100 bus coupler.

• if the AF function block is contained under the event CONTRM then setting ACT (to 1 from 0)
will have no effect. If the function block is outside the event task, then setting the ACT input (to 1
from 0) will enable events to be triggered.
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Analog input AIAPC

Summary
AIAPC (Analog Input APC) element is used to read the two analog input AIAPC
channels available directly on the APC board. F1 CONV1 ERR 10
F2 CONV2 O1 11
The filtering time constant and conversion parameters for each channel are
defined with the input parameters. 1 T1
2 T2 O2 12
ERRC 99
Call AIAPC Figure 1. PC Element
AIAPC
Connections Table 1
F1 CONV1 II CONVersion parameter for analog input see table 2

channel #1
F2 CONV2 II CONVersion parameter for analog input see table 2
channel #2
1 T1 II Filtering Time for 1 analog input channel 1 to 32767 [ms]
2 T2 II Filtering Time for 2 analog input channel 1 to 32767 [ms]
10 ERR OB ERRor 0 = no error,
1 = active error
11 O1 OI Output of channel 1 after filter. see table 2
12 O2 OI Output of channel 2 after filter. see table 2
99 ERRC OI ERRor Code see table 3
Input scaling Table 2
Signal ranges CONVx Function parameter Output range
-10 to +10V/-20 to +20mA 1 -32760 to 32760

4 to 20mA 2 0 to 32760
0 to +1 V / 0 to 2mA 3 0 to 32760
0 to +10V/0 to 20mA 4 0 to 32760
Error Codes Table 3
0 no fault
4101 Conversion not ready
4102 ADMUX not changing
4165 CONV1 = 2 and < 4mA
4166 CONV2 = 2 and < 4mA
4167 CONV1, 2 = 2 and both channels < 4 mA
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Function
The APC board hardware include always two basic analog input channels. The AIAPC element
provides the application software with a direct access to those channels.
The selection of the ranges is determined by the conversion parameters CONV1 and CONV2.
The input parameters T1 and T2 define the filtering time constants for channel 1 and 2 respectively.
All the input parameters can be changed "on line" and they take effect during the first execution cycle
of the AIAPC element.
The filtering formula:
I + T / Tc * O(n −1)
O(n ) =
T Tc +1
I = input value
T = filtering time
Tc = cycle time of the task
O(n) = output value
O(n-1) = output value of previous execution cycle
Note: AIAPC function block reads input signal and calculates filtered value (not I/O board or
background program). Cycle time of the task appoint how often new value is gott to a filtering
calculation.
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Analog Input Extended IO AIEXT

Summary
AIEXT (Analog Input Extended IO) element is used to read the value of the AIEXT
an analog input signal from YPQ110 or YPQ111 I/O board connected to the F1 BOARD ERR 10
F2 CHNR 11
APC board parallel bus. The hardware address and channel number of the O
I/O board are defined with function parameters. The filtering time constant F3 CONV ERRC 99
and input scaling for analog input channel are defined with input 1 T
parameters. Output of the element is an Integer. Figure 1. PC Element

AIEXT
Call AIEXT
Connections Table 1
F1 BOARD II Hardware address of the I/O BOARD 0 to 15

F2 CHNR II Input CHannel NumbeR on the board 1 to 8
F3 CONV II Input scaling for analog input channel see table 2
1 T II Filtering Time for analog input channel 5 to 32767 [ms]
10 ERR OB ERRor 0 = no error, 1=
active error
11 O OI Output of the channel after filter. see table 2
99 ERRC OI ERRor Code see "Error codes"
Input scaling Table 2
Signal ranges CONV Function parameter Output range
-1 to +1 V / -2 to 2mA 0 -32760 to 32760

-10 to +10V/-20 to +20mA 1 -32760 to 32760
4 to 20mA 2 0 to 32760
Output scaling
The output signal range is fixed to: -32760 to 32760 for any input signal range.
The practical range however is: -32753 to 32752 and this is due to the 12 bit resolution of the A/D
converter. For example if the input conversion parameter is selected to be "1" then the output value
+32752 corresponds +9,995V and the +10,000V, that can not measured by the A/D converter
corresponds to value +32760.
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Error Codes
The AIEXT element generates Error codes according to the general formula for I/O extension board:
5000 + 100*BOARD(NR) + combination of I/O board faults or range faults.
Hardware faults of YPQ110 board:
Code# Description
1 parallel bus error

64+2 power fail
64+4 AI converter gain error
64+8 AI converter offset error
64+16 AO1 fault
64+32 AO2 fault
Range faults of YPQ110 board:
When the selected input range is 4 to 20mA and the current falls below 3,5mA then the following
code indicates the affected channel number:
Code# Description
1 Channel 1 range fault

Range faults are detected only if there are no hardware faults with number below 16.
Code# Description

10 several AI rance faults
11 AI1 rance fault
12 AI2 rance fault
13 AI3 rance fault
14 AI4 rance fault
15 AI5 rance fault
16 A16 rance fault
17 A17 rance fault
18 A18 rance fault
39 illegal identification (wrong board or channel number)

40 board missing
66 power fail
68 reference voltage fault (10V or 0V)
80 several AO faults
81 AO1 fault
82 AO2 fault
83 AO3 fault
84 AO4 fault
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Function
The I/O extension board YPQ110 hardware includes four and YPQ111 hardware includes eight
analog input channels. One AIEXT element provides the application software with a direct access to
one of those channels.
The address is defined with the function parameter "BOARD" and it must have the same value as the
address selector on the corresponding I/O board. Channel number is defined with the function
parameter "CHNR". The function parameters "BOARD" and "CHNR" are read during the system
"Power up" or after a program download.
The selection of the ranges is determined by the conversion parameter "CONV".
The input parameter " T " defines the filtering time constant for the channel. All the input parameters
can be changed "on line" and they take effect during the first execution cycle of the AIEXT element.
ERR and ERR are used to hardware fault indication of the I/O board.
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And Gate AND

Summary
AND elements are used to form general combinatory expressions with Boolean -1 20
&
variables. -2
The elements can have a maximum of 19 inputs. C1
Figure 2. PC
Element AND
Call AND (C1) Table 1
Connections Table 2
1 - IB Input
2 - IB Input
C1 - IB Input
20 - OB Output
AND Element
The output signal is set to 1 if all inputs are 1.
See the truht table below.
Table 4 Truht table AND (3)

1 2 3 20
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
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And Gate AND-O

Summary
AND with OR gates on the inputs is used to form general combinatory 1 60
expressions with boolean variables.
&
-
C1
11
- 1
10 + C2
51
- 1
50 + C6
Call AND-O (C1,C2,C3,Cn) Figure 1. PC Element
AND-O
.
C1 Number of inputs in the AND part of the element. 0 to 9

C2 Number of inputs in the first OR gate of the element. 0 to 9
C3 Number of inputs in the second OR gate of the 0 to 9
element.
...
Cn Number of inputs in the last OR gate of the element. 0 to 9
Where: 1≤ n ≤6
1 ≤ C1 + C 2 +.. + Cn ≤ 40
Connections Table 2
No Type Description
1 IB Input direct to the AND gate in the element.

2 IB Input direct to the AND gate in the element.
...
C1 IB Input direct to the AND gate in the element.
11 IB Input to the first OR gate in the element.
12 IB Input to the first OR gate in the element.
...
10+C2 IB Input to the first OR gate in the element.
21 IB Input to the second OR gate in the element.
22 IB Input to the second OR gate in the element.
...
10*(n-1) + 1 IB Input to the last OR gate in the element.
10*(n-1) + 2 IB Input to the last OR gate in the element.
...
10*(n-1) + Cn IB Input to the last OR gate in the element.
60 OB Output.
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Function
This function provides faster execution than if separate elements are used. The inputs only need to be
tested until the value of the output can be determined. If input 1 is 0, then the output can be reset to 0)
irrespective of all other inputs. See the example of AND-O (3,3,3) as shown in figure 2 and in table 3.
Truth table AND-O (3,3,3) Table 3
1 2 3 11 12 13 21 22 23 60
0 x x x x x x x x 0
1 0 x x x x x x x 0
1 1 0 x x x x x x 0
1 1 1 0 0 0 x x x 0
1 1 1 0 0 1 0 0 0 0
1 1 1 0 0 1 0 0 1 1
1 1 1 0 0 1 0 1 x 1
1 1 1 0 0 1 1 x x 1
1 1 1 0 1 x 0 0 0 0
1 1 1 0 1 x 0 0 1 1
1 1 1 0 1 x 0 1 x 1
1 1 1 0 1 x 1 x x 1
1 1 1 1 x x 0 0 0 0
1 1 1 1 x x 0 0 1 1
1 1 1 1 x x 0 1 x 1
1 1 1 1 x x 1 x x 1
x indicates that the input has no effect on the value of the output or the execution time of the function
block.
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Analog Output Extended IO AOEXT

Summary
AOEXT (Analog Output Extended IO) element is used to write to one of the AOEXT
analog output channels of the YPQ110 or YPQ111 I/O board connected to F1 BOARD ERR 10
F2 CHNR ERRC 99
the APC board parallel bus. The board hardware address and the channel
1 I
number are defined with the function parameters. Datatype of the input
signal to the element is an Integer.
Call AOEXT AOEXT
Connections Table 1
F1 BOARD II Hardware address of the I/O BOARD 0 to 15

F2 CHNR II AO CHaNnel numbeR on I/O board 1 to 4
1 I II Input value for element -32.767 to
+32.767
1 = active error
99 ERRC OI ERRor Code *see "Error
codes"
Error Codes
The AOEXT element generates Error codes according to the general formula for I/O extension board:
Code# Description

64+2 power fail
64+4 AI converter gain error ( applicable to AI)
64+8 AI converter offset error (applicable to AI)
64+16 AO1 fault
64+32 AO2 fault

They are detected only if there are no hardware faults, and although not related with the AO
functions, they may be also shown (see AIEXT).
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Code# Description

11 AI1 rance fault
12 AI2 rance fault
13 AI3 rance fault
14 AI4 rance fault
15 AI5 rance fault
16 A16 rance fault
17 A17 rance fault
18 A18 rance fault
39 illegal identification (wrong card or channel number)

40 board missing
66 power fail
81 AO1 fault
82 AO2 fault
83 AO3 fault
84 AO4 fault
Function
The I/O extension board hardware includes two (YPQ110) or four (YPQ111) analog output channels.
One AOEXT element provides the application software with a direct access to the D/A converter of
one of those channels.
The address is defined with the function parameter "BOARD" and it must have the same value as the
address selector on the corresponding I/O board. Channel number is defined with the function
parameter "CHNR". The function parameters "BOARD" and "CHNR" are read during the system
"Power up" or after a program download.
The input signal range is ( -32767 to +32767) and it corresponds with the (-10 to 10 V ) output signal
voltage range.
ERR and ERR are used to hardware fault indication of the I/O board .
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Analog output AOMEAS

Summary
AOMEAS (Analog Output for MEASuring ) element is used in the AOMEAS
application program to write to the analog output channel of YPH107 or F1 BOARD ERR 10
YPH108 board connected to the APC board parallel bus. The hardware F2 CHNR ERRC 99
address and the channel number of the I/O board are defined with function 1 I
parameters. Datatype of the input signal is an Integer.
Call AOMEAS AOMEAS
Connections Table 1
F1 BOARD II Hardware address of the I/O BOARD 0 to 15 (YPH107)

(Add 100 for YPH108)
F2 CHNR II AO CHannel NumbeR on I/O board 1 to 2
1 I II Input value for element -32767 to +32767
1= active error
99 ERRC OI ERRor Code *see "Error
codes"
Error Codes
The AOMEAS element generates Error codes according to the general formula for I/O extension
board:
ERRC = 5000 + 100*ADDR + CODE#
ADDR is the actual I/O address of YPH107/YPH108 (0 to 15)
Hardware faults of YPH107 board Table 2
Code# Description
1 Paraller bus error

2 Power supply fault
Function
The optional speed measuring board YPH107/YPH108 includes two analog output channels. One
AOMEAS element provides the application software with a direct access to the D/A converter of one
of those channels. The address is defined with the function parameter "BOARD" and it must have the
same value as the address selector on the corresponding I/O board. Channel number is defined with
the function parameter "CHNR".
The input signal range is ( -32767 to +32767) and it corresponds to the (-10 to 10 V ) output signal
voltage range.
ERR and ERRC are used to indicate hardware and bus errors.
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Average AVG
Summary
AVeraGe element is used to calculate the floating average of an optional AVG(C1, C2)
number of integers or real numbers. 1 SET O 10
2 I OF 11
AVG
Call AVG (C1,C2)

C2 Number of samples 2 to 255
Connections Table 2
1 SET IB Input for storage of a new sample value

each time the element is executed.
2 I IC1 Input of signal whose floating average is to
be calculated.
10 O OC1 Output for the calculated floating average.
11 OF OC1 Output for First value in the sample queue.
Function
New data is entered into the queue by replacing the oldest sample with the current value of I. The
floating average is calculated by summing all values in the queue and then dividing by the number
queue places C2 as shown in figure 1 below:
C2
∑I
1
O = n
C2 n =1
Figure 2. Floating Average calculation
Output of data
When the input SET is 1, data at I is loaded to the outputs O and OF. The number of values sampled
is set to 1.
When the input SET is reset (to 0), the last value loaded at OF remains and O is calculated as in
figure 1 above. If the number of sampled values, i.e., the number of times the element has been
executed after SET has gone from 1 to 0, is less than C2 then this value is substituted as the divisor in
calculation shown in figure 2, above.
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Read one bit BGET

Summary
BGET is used to read one selected bit from an integer or long integer. The BGET
integer usually contains packed boolean data. 1 BITNR
2 I O 10
Call BGET BGET
C1 Data Type I, IL
Connections Table 1
1 BITNR II The selected BIT NumbeR to read. 0 to 15(C1=I) or

0 to 31 (C1=IL)
2 I II Input. Data input
10 O OB Output. Status of the bit selected
Function
The bit value of input I, specified by BITNR, is loaded to output O. If BITNR is not in the range
0 to 15 (C1=I) or 0 to 31 (C1=IL), then output O is set to 0.
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Block Header BLOCK

Summary
Block header BLOCK is used to enable/disable the execution of several PC BLOCK
elements. 1 ON RUN 5
Figure 1. PC
Call BLOCK Element BLOCK
Connections Table 1
1 ON IB Control input which is set (to 1) for normal execution

5 RUN OB RUN indicates execution of the elements in the block.
Function
BLOCK is used to enable/disable a number of PC elements in a control module,
slave or sequence step. A block may not contain structure elements.
Execution
For normal execution of a block, the supervisory execution unit must be under normal execution, and
the input ON of the block header must be set to 1. The block will execute according to the conditions
of the supervisory execution unit. If the ON input is set to 0 after the block has been executed, the
calculated data remains until the next time the block is executed. If the supervisory execution
unit is executed in the reset mode, the elements in the block are also executed in
that mode, irrespective of the state of the ON input.
Run
The output RUN is set only if normal execution is progress, i. e. the supervisory
execution unit is under normal execution and the ON input of the block is set.
ON RUN
1 5
Normal execution of
PC elements
Figure 2. Function diagram
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Set one bit BSET

Summary
BSET is used to set one selected bit of an integer or long integer value. The BSET(C1)
integer usually contains packed boolean data. 1 EN
2 BITNR
3 BIT
4 I O 10
BSET
Call BSET(C1)
C1 Data Type I, IL
Connections Table 1
1 EN IB ENable. If EN is reset (to 0), then the current

value I is loaded unchanged to output O.
2 BITNR II Input for selecting the BIT NumbeR to set 0 to 15(C1=I) or
0 to 31(C1=IL)
3 BIT IB Input. Value of the BIT 0 to 1
4 I II Input. Data input
10 O OI Output. Output of data
Function
If the value of input EN is set (to 1) then the data bit, determined by BITNR, is replaced by the value
of the input BIT and the result is loaded to output O.
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Comment C
Summary
C (C1, C2) is used to write comments in application program.
Call C (C1, C2)
Connection Table 1
C1 Number of string values 1 to 32

C2 Nr. of characters in string 1 to 30
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Comparator COMP
Summary
COMP (COMParator)is used to compare inputs. COMP
(C1, C2)
1 I1 I1 > I2 5
2 I2 I1 = I2 6
I1 < I2 7
Call COMP (C1, C2)

Figure 1. PC
Connections Table 1 Element COMP
C1 Data type B, I, IL, R, T, TR, A

C2 Length of the array 0 to 80
1 I1 IC1 Input 1. Input, whose value is compared with input I2.

2 I2 IC1 Input 2. Input, whose value is compared with input I1.
5 I1>I2 OB Input 1>Input 2. Output which is set if input I1 is greater than input I2.
6 I1=I2 OB Input 1=Input 2. Output which is set if input I1 is equal to input I2.
7 I1<I2 OB Input 1<Input 2. Output which is set if input I1 is less than input I2.
Function
The values at the two inputs are compared and the result of the comparison can be read at the outputs
I1<I2, I1=I2 or I1>I2.
If the type of inputs is array, outputs I1 > I2 and I1 < I2 are set based on the first not aqual characters
of the input arrays.
Example: If I1 = "AAAA" and I2 = "AAXA" then I1 < I2.
At startup, output I1=I2 is set before the first execution regardless of the values of inputs I1 and I2.
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Comparator COMP-R
Summary
COMP-R (COMParator - Real)is used for limit value COMP-R
(C1, C2)
monitoring of real numbers with relation to several limits. I
1
10 HHYS I<H1 20
11 H1 I>H1 21
12 H2 I>H2 22
10+C1 HC1 I>HC1 20+C1
30 LHYS I>L1 40
31 L1 I<L1 41
32 L2 I<L2 42
30+C2 LC2 I<LC2 40+C2

Call COMP-R (C1,C2) Table 1
Figure 1. PC Element COMP-R
C1 Number of limit values for high level 1 to 9

C2 Number of limit values for low level 1 to 9
Connections Table 2
1 I IR Input 1. Input, whose value is compared with limit values H1 to

HC1 and L1 to LC2.
10 HHYS IR High HYSteresis. Hysteresis common for all H values. The
hysteresis is the difference between the I-value at which the H
outputs are set and the value at which they are reset.
11 H1 IR High 1. Upper limit value 1.
12 H2 IR High 2. Upper limit value 2.
.
.
.
10+C1 HC1 IR High C1. Upper limit value C1.
20 I<H1 OB Input < H1. Output which is set if I is less than H1.
21 I≥H1 OB Input ≥ H1. Output which is set if I is greater than or equal to H1.
22 I≥H2 OB Input ≥ H2. Output which is set if I is greater than or equal to H2.
.
.
.
20+C1 I≥HC1 OB Input ≥ HC1. Output which is set if I is greater than or equal to
HC1.
30 LHYS IR Low HYSteresis. Hysteresis common for all L values. The
hysteresis is the difference between the I value at which the L
outputs are reset and the value at which they are set.
31 L1 IR Low 1. Lower limit value 1.
32 L2 IR Low 2. Lower limit value 2.
.
.
.
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3AFY61281240
Connections Table 2 continued
30+C2 LC2 IR Low C2. Lower limit value C2.

40 I>L1 OB Input > L1. Output which is set if I is greater than L1.
41 I≥L1 OB Input ≥ L1. Output which is set if I is less than or equal to L1.
42 I≥L2 OB Input ≥ L2. Output which is set if I is less than or equal to L2.
.
.
.
40+C2 I≥LC2 OB Input ≥ LC2. Output which is set if I is less than or equal to LC2.
Function
Input signal I is compared with the limit value specified at inputs H1 to HC1 and L1 to LC2. For
upper limits, the output for the different limits will be set when input I becomes equal to or greater
than the limit value. For lower limits, the output is set when I becomes less than or equal to the limit
value.
Limits can be set optionally within the range -9.2 x 10 -18 to 9.2 x 10 18.
The lowest allowable positive and negative values are 5.0 x 10-20 and -5.0 x 10 20.
The element sets 20 (I<H1) and 40 (I>L1) to 1 before the first execution, regardless of the value at
input I.
Hysteresis
The input HHYS gives the hysteresis for all limits at high level, and LHYS for all limits at low level.
The hysteresis is the difference between the I values at which the different outputs are set and the
values at which they are reset.
At high level, the outputs will be reset when I becomes lower than the limit minus the hysteresis
HHYS. At low level, the outputs will be reset when I becomes greater than the limit value plus the
hysteresis LHYS.
HHYS I<H1
10 H1 I>H1 20
11 H2 I>H2 21
12 22
HC1 I>HC1
10 + C1 20 + C1
I
1
LHYS I>L1
30 L1 I<L1 40
31 L2 I<L2 41
32 42
LC2 I<LC2
30 + C2 40 + C2
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Control Module Header CONTRM

Summary
CONTRM (CONTRol Module) is used for structuring and execution CONTRM(C1, C2, C3)
1 ON 5
control of control modules. Function modules, blocks, and elements RUN
2 > SINGLE 6
can be included in a control module. MODP
3 R
Call CONTRM (C1, C2, C3) CONTRM
C1 Cyclicity in ms Allowed values are between 2 ms and 2000 ms in

steps of 2 ms.
C2 Place in the cycle time table 1 to 251: place in the cycle time table,
and/ or scheduling strategy. cyclic activation.
252: activation at initialization after
power down.
253: activation at power down.
C3 Currently not used
Connections Table 2
1 ON IB Control input which is set (to 1 ) with normal execution.

2 SINGLE IB If input ON and R are 0, elements in the control module can
be executed once by setting SINGLE.
3 R IB Reset. Input for clearing elements in the control module are
executed.
5 RUN OB RUN indicates that elements in the control module are
executed.
6 MODP OB MODify Permission. Is always true.
Function
The control module header CONTRM is a supervisory execution controlling element for a control
module. The call parameter C1 is used to specify how often the control module is to be executed. Call
parameter C2 is used to specify the execution sequence of execution units with the same cycle time.
When and how the control module is to be executed is determined with the control inputs ON,
SINGLE and R.
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3AFY61281240
Normal Execution
The input ON is set for normal execution. The control module is then executed in accordance with the
call parameters C1 and C2. If ON input is reset after execution of the control module, the calculated
data remains until the next time the control module is executed. The ON input overrides the SINGLE
input, i.e. if ON is set, SINGLE has no effect.
The execution is performed in three steps:

1 Reading variables from the I/O devices, common data area, and afrom other modules.
2 Element execution.
3 Writing variables to the I/O devices, common data area, and to other modules.
SINGLE Execution
In the SINGLE input is set when the ON input is reset, the control module is executed once in
accordance with normal execution.
Clearing
If input R is set, the control module is executed in the reset mode. This means that all outputs of the
elements within the control module are given default values which in most cases are the 0 -value of the
data.
Input R overrides the inputs ON and SINGLE.
RUN
Output RUN is set only if normal execution is in progress, i.e. if ON is set, or if the control module is
being SINGLE executed. With SINGLE execution, the RUN output is set during one cycle only.
MODP
Is always true.
Effects from PCPGM

ON and R inputs on the program header override the inputs on the control module header. The input
ON on PCPGM must be set to permit normal execution or reset execution of the elements in the
control module.
PCPGM
RUN 5
ON &
R Reading variables from the
1 ON I/O devices, common data
area and other modules.
2 SINGLE 1
> Normal execution of
elements.
Writing variables to the I/O
devices, common data area
and other modules.
3 R &
1
Execution of elements in
reset mode.
MODP 6
Always = true
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Code Converter CONV

Summary
CONV (CONVerter) converts integer, read time and time -real data from one CONV (C1,C2)
representation to eachother. 1 1 O 5
ERR 6
Call CONV (C1, C2)
CONV
C1 Data type at input I, IL, R, T, TR

C2 Data type at output I, IL, R, T, TR
Connections Table 2
1 I IC1 Input. Input for data to be converted.

5 O OC2 Output. Output for converted data.
6 ERR OB ERRor. Output which is set (to 1) if a limit is reached at
output O.
Function
Data at input I with data type in accordance with call parameter C1 is converted to data with data type
according to call parameter C2 at the output O.
When conversion is to the data types I and IL (integer) and T (time), overflow can accur at the max or
min limit values. The error signal output ERR is set when overflow occurs.
Rounding Off
When converting from real numbers to integers, the number is rounded up when the decimal is 0.5 or
greater, and down when the decimal is less than 0.5.
When converting from T to R, I or IL the value given is the number of entire seconds from midnight.
When converting from R, I or IL to T the input value is treated as the number of entire seconds from
midnight.
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3AFY61281240
Code Converter CONV-BI

Summary
CONV-BI (CONVerter - Boolean to Integer) converts data from BC, CONV-BI
BCD, 1-of-N, Gray code or 16/32 bit BC formed from Boolean (C1,C2,C3)
1 S ERR 5
variables into integers. The element has a memory function for
2 >L
storage of converted data. 3 R
4 SIGN
I1 I1 0 50
I2 I2
Call CONV-BI (C1, C2, C3)

10 + C3 IC3
Call Parameters Table 1 Figure 1. PC Element

CONV-BI
C1 Data type I, IL
C2 Type of input code 1 to 5
1 for BC
2 for BCD
3 for 1-of-N code
4 for Gray code
5 for 16/32 bit BC*
C3 Number of inputs for data to be 1 to 31
converted.
If C2 = 5 then C3 must be 31.
* When C2 = 5 the output O cannot be interpreted as I/IL by the aid.
Number of inputs required with Table 2

Number of inputs required with
Code I IL
BC 15 31
BCD 18 31
1-of-N 31 31
Gray 15 31
16/32 bit BC 15 + SIGN 31 + SIGN
Connections Table 3
1 S IB Set. Input for storage of a new value each time the element is
executed. When this input is reset (to 0), the latest calculated
value will remain at the outputs.
2 L IB Load. Dynamic input for loading data.
3 R IB Reset. Input for clearing the output. This input overrides S
and L inputs.
4 SIGN IB Input set (to 1) with negative data values. If C2 = 5, SIGN is
used as the most significant input to get a 16/32 bit
conversion.
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3AFY61281240
Connections Table 3 continued
5 ERR OB ERRor. Output which is set when more than one input is set
with conversion of 1-of-N code or if the integer value to be
stored at the output cannot be represented by the data type.
11 I1 IB* Input 1. Input 1 for BC, BCD, 1-of-N
Gray code or 16/32 bit BC.
12 12 IB* Input 2. Input 2 for BC, BCD, 1-of-N,
. Gray code or 16/32 bit BC.
.
.
10 + C3 IC3 IB* Input C3. Input C3 for BC, BCD, 1-of-N,
Gray code or 16/32 bit BC.
50 O OC1 Output. Output for converted data.
*The data at each of these inputs is of Boolean type, but together they form a value of the type
specified by parameter C1.
Function
The element can convert binary code (BC), binary coded decimal code (BCD), 1-of-N code or Gray
code to integers of data type I (16 bit) or IL (32 bit). With BC the SIGN input can be used as a sign bit
(C2 = 1) or as most significant bit (C2 = 5).
Examples of Input Values with Different Recodings
Input integer value

Input BC with BC without BCD 1-of-N
sign sign
I1 1 1 1 1
I2 2 2 2 2
I3 4 4 4 3
I4 8 8 8 4
I5 16 16 10 5
I6 32 32 20 6
I7 64 64 40 7
I8 128 128 80 8
I9 256 256 100 9
I10 512 212 200 10
. . .
. . .
. . .
I31 230 230
SIGN sign 231
Only one of the inputs may be set with 1-of-N code. All inputs have a fixed value with BC, BCD and
1-of-N codes but not with Gray code.
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3AFY61281240
BC Gray code 1-of-N-code

I4 I3 I2 I1 I4 I3 I2 I1 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
1 0 0 1 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
1 0 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Storage of Data
When input L is set, the code at inputs I1 to IC3 is immediately converted and stored. If input S is set,
the input code is converted and the integer is stored each time the element is executed. When S is
reset (to 0 ) after having been set, the data stored most recently remains. The input S overrides the
input L, i.e. when S is set, L has no effect.
Clearing
The input R clears the output and prevents all further storage of data while R is set.
Supervision
When converting 1-of-N code, the setting of only one of the inputs 1 to IC3 is supervised. If two or
more inputs are set, the value of the input signal with the lowest number is stored. The error signal
output ERR is also set. If the integer value to be stored at the output exceeds the allowable range, the
error signal output is set. In addition, the output is limited to the upper or lower limit value.
CONV-BI
11 I1
12 I2 When
DEC ERR 5
2 1
test
IC3
10 + C3
Test
Con- valid
version data
4 SIGN
I
1 S O 50
C
1
2 L
1
3 R
R
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Code Converter CONV-IB

Summary
CONV-BI (CONVerter -Integer to Boolean) converts data from CONV-IB
integers into BC, BCD, 1-of-N, Gray code 16/32 bit BC formed (C1,C2,C3)
1 S ERR 5
from Boolean variables. The element has a memory function for SIGN
2 >L 6
storage of converted data. ZERO 7
3 R
10 I 01 11
02 12
0C3 10 + C3
Call CONV-IB Table 1 Figure 1. PC Element CONV-IB
C1 Data type I, IL
C2 Type of input code 1 to 4
1 for BC
2 for BCD
3 for 1-of-N code
4 for 16 or 32 bit BC
C3 Number of outputs for converted data. 1 to 32
When C2 = 4, the input 1 cannot be interpreted as I/IL by the aid MasterAid 2XX.
Number of outputs with different codes Table 2

Number of outputs required with
Code I IL
BC 15 31
BCD 18 32
1-of-N 32 32
16 or 32 bit BC 15 + SIGN 31 + SIGN
Connections Table 3
1 S IB Set. Input for storage of a new value each time the element is
executed. When this input is reset (to 0) the latest calculated value
will remain at the outputs.
2 L IB Load. Dynamic input for loading of data.
3 R IB Reset. Input for clearing outputs.This input overriders S and L inputs.
5 ERR OB ERRor. Output which is set when the integer value to be converted
exceeds the allowable range.
6 SIGN OB Output set to 1 with negative data values. If C2 = 4, SIGN is
interpreted as bit 16/32.
7 ZERO OB Output set to 1 when the value at the input I is ZERO.
10 I IC1 Input. Input for the integer value to be converted.
11 O1 OB* Output 1. Output 1 for BC, BCD, 1-of-N code or 16/32 bit BC.
12 O2 OB* Output 2. Output 2 for BC, BCD, 1-of-N code or 16/32 bit BC.
...
10+C3 OC3 OB* Output C3. Output C3 for BC, BCD, 1-of-N code or 16/32 bit BC.
*The data at each of these outputs is of Boolean type, but together they form a value of the type
specified by parameter C2.
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Function
The element can convert integers of the data types I (15 bits) or IL (31 bits) to binary code (BC),
binary coded decimal code (BCD) or 1-of-N code. The data type I/IL can also be converted to 16/32
bit BC. The code conversion to be performed is specified by the call parameters C1 and C2. With
positive data values the output SIGN is reset (to 0) and with negative values, set (to 1). For 16/32 bit
BC SIGN is used as output 16/32.
Ex. of Output Values with Different Recodings
Output integer value

Output BC BCD 1-of-N-code
O1 1 1 1
O2 2 2 2
O3 4 4 4
O4 8 8 4
O5 16 10 5
O6 32 20 6
O7 64 40 7
O8 128 80 8
O9 256 100 9
O10 512 200 10
.
.
.
SIGN 2 31
SIGN is used as a sign for BC, BCD and 1-of-N. Only one of the outputs is set with 1-of-N code.
Storage of Data
When input L is set, the integer at input I is ommediately converted. If input S is set, the input code is
stored and the result is converted each time the element is executed. When S is reset (to 0) after
having been set, the data stored most recently remains until the element is executed once more with
one of the inputs S, L or R set. The input S overrides the input L, i.e. when S is set, L has no effect.
Clearing
The input R clears the output and prevents all further storage of data while R is set.
Supervision
When converting data from integers to 1 -of-N code, the numbers are restricted to - 32 to + 32.
If the integer value to be converted exceeds the allowable output range, the error signal output is set.
In addition, the output is limited to the upper or lower limit value.
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CONV-IB
01 11
10 I 02 12
I
1 S
C
1
2 L Con-
1 version 0C3 10 + C3
3 R
R ZERO 7
SIGN 6
Test
ERR 5
valid
data
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Counter COUNT
Summary
COUNT (COUNTer) is a presettable counter for counting pulses, up or COUNT
down. The countger also monitors the relation of the counter value to 0. (C1)
1 >L >0 10
2 U/D-N =0 11
3 >C <0 12
4 R
5 EN
21 I O 22
Call COUNT (C1) Figure 1. PC Element

COUNT
C1 Data type I, IL
Connections Table 2
1 L IB Load. Loads the counter with the value at input I.

2 U/D-N IB Up/Down-N. Input which determines if the counter
is to count up (U/D-N = 1) or down (U/D-N = 0).
3 C IB Clock. When this input changes from 0 to 1 the
counter counts up or down is accordance with the
status of the input U/D-N.
4 R IB Reset. Input which clears the counter and prevents
all further counting or loading.
<this input overrides all other inputs!
5 EN IB ENable. Input which is set to 1 to permit counting
or loading. Reset execution is, however, performed
independently of EN.
10 >0 OB Output which is set when the value of the counter is
greated than 0.
11 =0 OB Output which is set when the value of the counter is
0.
12 <0 OB Output which is set when the value of the counter is
0.
21 I IC1 Input. Input for new value when loading.
22 O OC1 Output. Output for counter value.
Function
When input C is set, the counter value immediately increases or decreases. The value increases if
U/D-N = 1 and decreases if U/D-N = 0. The duration of the counter period may not be less than 2 x
the cycle time of the program.
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When the input L is set, the counter is loaded with the value at input I. If both input L and input C are
set simultaneously, the counter is first loaded after which an up or down count is performed. The
input EN must be set for the counter to count or load a new value.
Clearing
The input R clears the counter and prevents all further counting or loading. R overrides EN.
Supervision
The status outputs specity the relation of the counter value to zero (> 0, = 0, < 0).
When the counter reaches its least or greatest value for the data type, all counting ceases..
COUNT
COUNTER
2 U/D-N
UPCOUNT1
5 EN &
3 C
1
DOWNCOUNT
&
1 L
1
& SWITCH
ACT
21 I O 22
PRESET VALUE
VALUE
4 R
RESET
COMP-I
< 0 10
I2 I1 > I2
= 0 11
I1 = I2
D=0 > 0 12
I1 I1 < I2
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Data Logger DATALOG

Summary
DATALOG function block is a single channel data logger used to DATALOG
(C1,C2,C3)
record a stream of variable samples into the buffer. One value is stored
1 CLEAR ACT 10
into the buffer every time the function block is executed.
2 EN RUN 11
Logger operation can be controlled from both the application program
3 > TRIGG RDY 12
via input terminals 1 to 4 or the Drive Tool via a special Command
4 POSTNR FULL 13
(CMD) word internal to the DATALOG element structure. Multiple
DATALOG elements can be implemented under the same CONTRM. 21 I O 31
22 ELEM LAST 32
TIME 33
Call DATALOG (C1,C2,C3)
Call Parameters Table 1 DATALOG
C1 Data type I, IL, R,B

C2 Storage unit size 2 to 250 samples */
C3 Number of storage units in a buffer 1 to 4 */
*/ The total capacity of the Data logger buffer is calculated as C2 x C3.

Any combination of valid C2 and C3 is acceptable.
Connections Table 2
1 CLEAR IB Logger reset.

2 EN IB Sampling ENable.
3 TRIGG IB Init for the logging termination sequence.
4 POSTNR II Number of samples to be collected
after trigger.
10 ACT OB Logger Not in RESET mode.
11 RUN OB Logger in RUN mode ( sampling ).
12 RDY OB Sampling terminated, data available in the buffer.
13 FULL OB Logger buffer FULL.
21 I IC1 Input data to log.
22 ELEM II Location number of the logged sample.
31 O OC1 Value of the sample selected by ELEM.
32 LAST OI Location number of the latest sample.
33 TIME OIL TIME stamp for the TRIGG or, the last sample if logger stopped
but not triggered or, the first sample if logger is running.
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Function
DATALOG samples input data into its internal buffer. The logger operation can be controlled both by
the application program or by the Drive Tool.
The FB input terminals CLEAR, ENABLE and TRIGG are used by the application program for this
purpose.
The Drive Tool accesses the internal DATALOG element Status and Command (CMD) words. The
Status word includes the same information as the DATALOG FB output terminals: ACT, RUN, RDY
POST and FULL. The CMD word includes the CLEAR, ENABLE and STOP individual control bits.
The resultant control signals are formed in a following way:

Signal CLEAR = ( input CLEAR ) OR (CMD bit CLEAR)
Signal ENABLE = (input ENABLE) OR (CMD bit ENABLE)
Signal TRIGG = input TRIGG
Signal STOP = CMD bit STOP
There are 4 possible states that the DATALOG operation can enter: RESET, RUN, RDY and POST.
RESET
RUN=1 CLEAR=1, or
STOP= 1->0
CLEAR=1 CLEAR=1
EN=0, or
STOP=0->1
RUN RDY
TRIGG=0->1 POST_CNT=0
POST
Figure 2. State Diagram of

DATALOG Element
RESET state (the highest priority)

Entered in the system "Power up" mode and also when:
CLEAR signal becomes 1, or STOP changes from 1 to 0.
In this state:
• Sampling is stopped.
• The buffer is cleared and LAST points to the first (sample) position in the buffer.
• The time mark is cleared.
• ACT, RUN, RDY and FULL are all reset (to 0).
This RESET state is terminated after one cycle if the EN = 1
RUN state
Entered from the RESET state when EN signal becomes 1. The Time of the first recorded data sample
is recorded for the TIME output. In this state:
• Input data are collected.
• ACT is set to 1,
• RUN is set to 1,
• RDY is set to 0,
• FULL reflects the current buffer status.
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3AFY61281240
If the EN signal changes from 1 to 0 or the STOP signal changes from 1 to 0 then the TIME stamp is
updated with the current time and LAST is updated with the current sample location (number) after
which the RDY state is entered.
POST state
The state POST is entered when the signal TRIGG becomes active. It executes the following logging
termination sequence:
1. update the TIME stamp with the current time

2. collect "POSTNR" additional input data samples,
3. freeze the content of the logger buffer and then
4. enter the RDY state.
RDY state
Entered from the RUN state when EN becomes 0 or the STOP changes from 1 to 0 or, from the POST
state after the sampling termination procedure has been completed. In this state:
• Sampled data are frozen in the buffer.

• ACT is set to 1 ,
• RUN is set to 0 ,
• RDY is set to 1,
• FULL reflects current buffer status.
FULL is set when the buffer becomes full. Recording continues by overwriting the oldest sampled
value. Recording can be stopped when the buffer is full by a feedback connection from the output
FULL to input ENABLE.
Data samples in the buffer are numbered 1. (C2 x C3). ELEM indicates the number of the sample to
be moved to the DATALOG OUT terminal. If is out of range then OUT is zero.
TIME Output
The TIME is expressed as a 32 bit integer. It is read from the system clock and represents the number
of the 100us ticks since midnight.
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Initialize DCB channel DCBINIT

Summary
DCBINIT initializes one DCB channel. At least one DCBINIT is DCBINIT
compulsory for each channel to be used by other DCB function blocks. FI CHAN ERR 10
Both the "Special routine" execution and "Normal routine" execution of F2 CLASS FAIL 11
DCBINIT must occur before respective executions of other DCB F3 IND1 BOARD 12
function blocks. F4 VAL1 PROTS 13
The parameters for DCB usage are classified as:
F5 IND2 HWVERS 14
1. APC parameters = parameters that tune the DCB driver
F6 VAL2 SWVERS 15
within APC-system software.
2. DCB parameters = parameters that are downloaded to DCB F7 IND3 DATE 16
during start-up. F8 VAL3

All parameters of both types will get their default values when the first F9 IND4
instance of DCBINIT for the particular communication channel is F10 VAL4
executed.
F11 LAST
However, the user may overwrite some or all of these default values by
assigning other values into the "data pins" of DCBINIT. With one Figure 1. PC Element
DCBINIT instance, up to 4 parameter values can be modified. If more DCBINIT
changes are needed, additional DCBINITs can be used. APC and DCB
parameters cannot be modified by same DCBINIT instance (because
CLASS pin cannot have two values assigned simultaneously).
The CLASS pin of first DCBINIT instance may have any boolean value, and if no parameters need
adjustments from their default values, no further DCBINIT (with the other value in CLASS pin) is
required.
The last (and only last) DCBINIT instance (for each channel) must have a TRUE value in the LAST
pin.
Call DCBINIT
Connections Table 1
No Name Type Description Default
F1 CHAN II Channel number 1

F2 CLASS II APC = 0 , DCB = 1 1
F3 IND1 II Parameter index 0
F4 VAL1 II Parameter value 0
F11 LAST II Last DCBINIT for CHAN if 1 1
10 ERR OB Error
11 FAIL OI Type of error
12 BOARD OA20 Board type
13 PROTS OA20 Available protocols
14 HWVERS OA20 Hardware version
15 SWVERS OA20 Software version
16 DATE OI Date
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Function
Initialization ( special mode )
Typically, the first execution of each DCBINIT instance is run before the existence or type of the
actual DCB board is yet verified. The first DCBINIT for the specified channel has therefore
preparatory responsibilities for download, (but does not yet download anything to the board):
1 Check that the channel number is in the allowed range (1 to 4).

2 Check that DCB00 exists and has specified some system memory for the channel.
3 Check that this is not an instance after the "last instance".
4 Record that at least one DCBINIT instance is now found for the channel.
5 Check that the protocol defined in DCB00 has default values in APC-system software (i.e. it
is a protocol known by APC-system software).
7 Allocate the "parameter modification and download area" from the system RWM of the
channel, and copy the default values of both DCB and APC parameters there from the
DCBPAR table of the system software.
(Note: This memory as well as the system buffers are taken from the area of data buffers
defined by RECS pin of DCB00 and therefore RECS pin should have higher value than the
number of DCBRECs and DCBTRAs.)
8 Initialize the "common pointers" and variables in system RWM of the channel ("common" =
common for all DCBTRA and DCBREC function blocks and DCBdriver).
9 Set a flag PROTOCOL_EXIST.
10 Set preliminarily flags APC_PAR_OK and DCB_PAR_OK. (These flags may be cleared
later, if some faulty values are presented in "data pins" of DCBINIT(s).
11 Overwrites either DCB_parameters or APC_parameters according to CLASS pin and the
INDx and VALx pin pairs. The index-value pairs are first checked to verify that:
- the IND pin refers to some really existing parameter, i.e. the equivalent parameter is defined
in default parameters
- the VAL pin value is within the allowed range. (Each parameter has its own range specified
in the default parameter table.)
Note 1: The IND values of parameters are just their "names" and have nothing common with their
location in parameter areas.
Note 2: IND value = 0 means that no parameter value is assigned in resp. VAL pin. Any IND pin may
be connected to zero or non zero. (If a zero value is found in the IND pin, it is not interpreted as an
end indicator of user inputs, i.e. all IND pins are scanned for non zero values anyway).
If an illegal IND value or resp. VAL value is found, then either flag APC_PAR_ERR or
DCB_PAR_ERR is set (depending on CLASS pin) and the FAIL-output pin will show the number
and type of the user’s error:
Unknown IND value = 16110 + pin ID (1..4)

Too low VAL value = 16120 + pin ID (1..4)
Too high VAL value = 16130 + pin ID (1..4)
All VAL values (and their limits) are interpreted as16-bit integers, i.e. between -32768 and 32767. If
the actually required parameter value is a 16-bit binary value, a hexadecimal value, or an unsigned
decimal value between 32767 and 65535, the user must first convert it to a signed 16- bit integer.
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If any IND or VAL pin has an unacceptable value, the rest of the pins are not processed, i.e. the FAIL
output will show information about the first found error.
The parameters with IND values 1 to 4 in APC class (CLASS=0) have special predefined meanings:
1= Number of buffers for error messages which come spontaneously from DCB board.
2= Number of buffers for unexpected messages (=unexpected by DCB or APC).
3= Number of buffers where incoming messages may be stored temporarily, if the actual
target buffer is reseved by function blocks when the message comes from DCB.
4= Number of special buffers, e.g. to request and receive diagnostic information from DCB.
5= Last allowed memory page to be used in APC-DCB communication.
The other DCBINITs for the same channel:

Any number of DCBINITs is allowed, and any parameter value will be adjusted as many times as it
occurs in IND -VAL pin pairs of DCBINITs. The only rule or restrictions are:
1= One, and only one DCBINIT (per channel) must have LAST pin connected to "1".
2= No DCBINITs after the above mentioned DCBINIT are allowed, (= they are
ignored).
The additional functions of DCBINIT where LAST pin is set are:

(Note: that if the DCBINIT instance is the only one of its kind, the above described functions are then
executed there, too:)
The downloadable parameter block (i.e. DCB parameters) is prepended with:
1 the indicator of a basic parameter block (= always 0).

2 board type defined to be necessary for the protocol.(This value is taken from the
header record of the default parameters
(and may not be modified by the user).
3 channel number (from CHAN pin).
4 identifier code of the desired protocol (from PROTOCOL pin of DCB00).
Initializes those pointers, variables and constants of DCB-system software in APC whose values
depend on the above mentioned parameters of class "APC".
Check that there is at least some space left for application VCIs (i.e. data buffers).
Initialize the system VCIs.
The logical summing of all errors of all DCBINITs occurs now, too. If no errors are found yet, set a
flag DCB_INIT_OK.
The last function of DCBINIT (independent of the LAST-pin value) is to set output pin ERR to true or
false, and FAIL pin to zero, if no errors are encountered during this block instance.
Normal Execution
If no system memory for the channel was found during special mode, then there is no nonzero pointer
value in Hisdat (internal storage of the function block instance), and the program does not try to make
more checking.
If the LAST pin is zero, the block does nothing more. But if it is set, the block triggers (=enables) the
actual downloading of parameters to the DCB board by first checking that the special mode
initialization succeeded ( DCBINIT_OK) and, if so, by setting the INIT_NORM_MODE_DONE.
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Note: however, that DCBINIT does not do the actual downloading. And, therefore, it does not show
any error codes either when the actual download fails. A failure where the good parameter values are
impossible to download due to wrong DCB board type, can be seen from the ERRC pin of DCBTRA
or DCBREC, but not from DCBINIT.
However, DCBINIT in cyclic task can show the contents of DCB board initial identification message
or show error code, if such message never comes.
Adjustable Parameter Values of the Protocols (Class = 1)
Sami protocol (protocol 1)

INDEX NAME DEFAULT MIN MAX
5 baud_rate 9600 1200 19200

6 write_interval 100 5 2000
7 serial_timeout 400 100 2000
105 vci_max 50 13 60
S3964 (protocol 3) and S3964R protocol (protocol 4)

4 master_slave 0 0 1
5 baud_rate 9600 1200 19200
105 vci_max 50 13 60
AB-DF1 protocol (protocol 5)

5 baud_rate 9600 1200 19200
15 own_id 0 0 255
16 parity 1 0 1
17 resp_timeout 2000 100 10000
105 vci_max 32 8 100
MODBUS protocol (protocol 6)

5 baud_rate 9600 1200 19200
7 diagnost_interval 2000 50 30000
15 own_stationid 0 0 247
16 parity 1 0 2
17 resp_timeout 2000 100 30000
18 max_vetries 3 0 10
19 retry_aft_brk 0 0 30000
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MFB protocol (protocol 9)

21 unit_no1 100 100 416(*)
22 unit_no2 0 100 416(*)
23 unit_no3 0 100 416(*)
24 unit_no4 0 100 416(*)
25 unit_no_sync 0 100 416
26 min_interval 10 2 20
(*) = These parameter values are set automatically and must not be specified by user with
DCBINIT.
Note: that almost all parameters above are specific for a channel. But the write_interval (=index 6
with all above listed protocols) is common to both (all) channels of the DCB board and, therefore, the
minimum value defined for some channel will be used for all channels. (Write_interval specifies how
often the DCB board will cause a communication interrupt to APC. It should be optimized by the
application designer so that unnecessary frequent interrupts would not disturb the APC processor,
but frequent enough that the data flow from DCBTRAs is not delayed too much. The DCB driver
cannot send any data to DCB board without first getting an interrupt request from there).
Placement of DCBINIT (with LAST = 1):

DCBINIT may reside either in a cyclic task or in a "Init -task". But in both cases it
must be executed before any other DCB blocks. When the application program is
written with FCB this rule means that the "DCBINIT -task" must be in tree
representation after all other tasks which contain DCB -blocks.
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Read from DCB dataset DCBRD

Summary
DCBRD reads a fraction of a dataset. The reception of the dataset is DCBRD
controlled by a DCBREC function block. A complete dataset can be read (C1,C2)
by a sequence of one or several DCBRD blocks. F1 OFFSET ERR 10
DCBRD blocks can be inserted and associated with the respective 1 ADDR
DCBREC block easiest by using protocol specific type circuits. 2 EN STATUS 11
3 LAST
OUT1 21
OUTC2 20 + C2
Call DCBRD Table 1 DCBRD
C1 Datatype I, IL or R
C2 Number of data outputs 1 to 16
Connections Table 2
F1 OFFSET II Offset of data fraction from beginning of dataset

1 ADDR IIL Internal address of dataset within system RWM.
2 EN IB If set, then the appl. program permits reading.
3 LAST IB Set to indicate the last DCBRD of the sequence.
10 ERR OB Set, if DCBRD or DCBREC programmed wrong
11 STATUS OI Status word
21 OUT1 OC1 Output 1
20+C2 OUTC2 OC1 Output C2
Status
Individual bits whose values can be extracted, if needed, from the STATUS word by a BITGET
function block.
bit 0 ERR Set in initialization error (= output terminal 10)
bit 1 Not used.
bit 2 DESTRUCT Set if destructed. Cleared if successfully
reconstructed.
bit 3 FIRST_CYCLE 1 = after initialization cycle, 0 = always
afterwards.
bit 4 OFFS_ERR 1 = this block tries to access too far in the buffer.
bit 5 to 8 Not used.
bit 9 RD_DONE Set if data is read, else cleared.
Function
The operation of DCBRD is controlled by an overriding DCBREC by the internal flags which are
invisible to the application programmer. The DCBREC is able to control DCBRD if its terminal
ADDRD is connected to terminal ADDR of the DCBRD. The DCBRD blocks should succeed the
matching DCREC, and they both must be inserted in the same CNTRM (or respective execution unit).
DCBRD has no access to any data from DCB board, if the DCBREC is missing or inoperative.
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ADDR is the base address of the dataset.

ADDR must be connected to the output terminal ADDRD of DCBREC. ADDR must never be
connected elsewhere.
OFFSET is the offset of here accessed data fraction from beginning of the data area of the internal
buffer, which is common to DCBREC, DCBRD(s) and DCB driver software. (ADDR value points to
the data byte with offset = 0).
DCBRD block will read C2 elements of datatype C1 into the data output pins starting from physical
address ADDR + OFFSET.
At initialization (in special mode), DCBRD checks if ADDR , OFFSET and C2 are legal. DCBRD is
not permitted to read from outside the range of the data buffer. If such an error is detected then output
ERR and STATUS.ERR are set. (And all reading will be prohibited during successive execution
cycles). Additionally, during the first cycle the DCBRD(s) will configure the data type and the data
length into the header part of the data buffer.
(The first DCBRD sets the data type of the message. A succeeding DCBRDs change the datatype to
"mixed type" if their datatypes are different.
The length of dataset is automatically configured so that each DCBRD computes the end-offset of its
data fragment, compares it with the value stored in dataset header (by other DCBRD instance) and
updates the value, if smaller. This automatic length configuration is participated by every DCBRD,
regardless of input value in EN pin).
Note: however, that this automatic length configuration may be overwritten by a length value
connected in SPECIAL pin of DCBREC, and thus it is possible to specify a shorter dataset than the
DCBRDs would configure.
At runtime (normal mode), DCBRD moves the contents of the dataset fraction to its output terminals
and sets STATUS.RD_DONE, if and when the associated DCBREC requests it to do so (presuming
EN input of DCBRD is = 1). This happens typically (and only) when DCB driver has positioned new
data from the DCB board into the data buffer.
But the DCB driver does not position only new data: It puts also the length (or amount) of the
received data in the data buffer header part. And DCBRD will check that the length of new data block
is sufficient for all of its output pins. And if not, DCBRD will show an error in ERR (but not in
STATUS.ERR).
Additionally, DCBRD will signal this kind of failure to its parent DCBREC, which will show SHORT
bit in its own STATUS output.
In order to provide data consistency, DCBREC has reserved, i.e. locked, the data buffer for DCBRDs’
disposal when it noticed that there are new data. While this locking prevails DCB driver cannot
position any new data into the buffer. And therefore DCBRD, whose LAST pin = 1, will release the
buffer from locked state. Any DCBRD instance, which executes after the data buffer is already
released back to DCB driver, will execute as "No Operation" block.
It is extremely important that every DCBREC block has at least one matching DCBRD block where
LAST pin is = 1. Otherwise the whole DCB driver will run out of its temporary storage buffers.
Because DCBRD updates the data output pins only when new data is passed by DCB driver (and
indicated by DCBREC), it is often useful to program the application program so that
STAT.RD_DONE is continuously monitored:
1= new data available on output pins and
0= old data (or no data) available on output pins.
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Errors
Reading is prohibited forever and the ERR terminal and STATUS.ERR bit are set if some of the
following programming errors is found:
- DCBREC is missing or inoperative.
- DCBREC is not in the same task.
- ADDR is not connected to a DCBREC.
- ADDR or OFFSET is odd.
- OFFSET is out of range of data buffer.
- C2 too great (together with OFFSET value) and causes reading of data outside the range of
data buffer.
During normal runtime, DCBRD checks and compares the length of just recently received data to the
required length specified by OFFSET and calls parameters C1 and C2, and if too short, sets the ERR
terminal, but does not set any error bit in STAT output. This kind of error may arise and disappear
any time. Therefore it has no influence on the next execution cycle of the DCBRD.
Note: that DCBRD does not check that read data makes sense. It is the application programmers’
responsibility to check that C1, C2 and OFFSET correspond to the structure of the received dataset.
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Receive DCB dataset DCBREC

Summary
DCBREC controls the receive process of one dataset over a Drive DCBREC
Communication Board (DCB). Actual access to the received data is FI CHAN ERR 10
possible through (one or sequence of) DCBRD blocks. The DCBRD F2 SPEC
blocks must succeed (= i.e. follow) the respective DCBREC block in the F3 STATION STATUS 11
same task. F4 IDENT ADDRD 12
DCBREC (and succeeding DCBRDs) can be used associated with
F5 CONFIG
various protocols.
1 EN
In application programming, protocol -specific type circuits composed of
one DCBREC and DCBRDs may be used, and thus relieve the user from 2 >CLEAR ERRC 99
entering the multiple function blocks which are necessary for receiving a
dataset from DCB board. The standard-type circuits for certain protocols Figure 1. PC Element
will be available for users (table 2). DCBREC
In order to make DCBREC operative (really receiving) it is necessary that:

The DB element DCB00 be inserted, and there be declared appropriate number of buffers and size of
each buffer (=sufficient for the protocol and the assumed maximum dataset length).
The protocol declared by the DCB00 element must be resident in firmware of the DCB hardware (i.e.
the DCB board must be of correct type).
At least one DCBINIT function block for the DCB channel must be included in the application
program (and in such a place that all DCBINITs of the channel are executed before any DCBREC
comes to execution).
Call DCBREC
Connections Table 1
F1 CHAN II Channel number 1

F2 SPEC II Message priority ** 0
F3 STATION II Station number ** 0
F4 IDENT II Message identity ** 0
F5 CONFIG II Configuration word 0
1 EN IB Enabled if set
2 CLEAR IB Clear when 0 ->1
10 ERR OB Error
12 ADDRD OIL Base address of dataset
99 ERRC OI Error code
** The significance depends on the protocol
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STAT output word consists of the bits:

bit 0 ACT Set in normal operation if EN = 1 and ERR = 0
bit 1 INIT Set when initialization is OK.
bit 2 CLEAR Set if the dataset has been cleared.
bit 3 FIRST_CYCLE Set on init, Reset when cyclic operation of DCB
begun.
bit 4 RDY Set if ready for normal operation.
bit 5 BUSY Request of data sent, but response not yet
arrived.
bit 6 DONE Set on reception of new data.
bit 7 SHORT Set if the message was too short for any DCBRD
bit 14 DESTRUCT Set by Destruct, reset by successful Construct.
bit 15 ERR Set on error.
Any STAT bit can be extracted by the function block BITGET if the signal is needed for other
function blocks in the appl. program.
Function Parameters
CHAN ( F1 )
The used communication channel of the DCB board.
E.g. with the multiprotocol UART board YPK113, CHAN may be 1 or 2. (DCBREC allows channel
numbers 1 to 4, but the presently available hardware, and DCB00 DB-element support max. 2
channels).
SPEC ( F2 )
Special parameter, which can mean e.g. the message priority.
Typically, non zero values of SPEC specify the length of the dataset to be less than what would result
from automatic length configuration based on offsets and lengths of DCBRDs. (If SPEC=0, automatic
length configuration will be used).
STATION
Remote station number for multinode serial buses.
In MasterFieldBus the station numbers are not declared here, but implicitly as node number in the
IDENT pin. (See below).
In protocols like SAMI and S3964, where there are no station numbers to use, this pin can be used for
some other purposes, e.g. in S3964 protocol, the data type definition for the message headers may be
defined by using this pin.
IDENT
The message identifier ( table 2 )
CONFIG
Specifies desired operation mode:
0= receive new application data values, when such arrive, but do not send any inquiry
messages (=passive receiver).
1= request and receive new application data values (=active receiver). The length of requested
data can be specified through pin SPEC (as a number of bytes). However, if SPEC has the
default value 0, the requested length = max. offset accessed by the associated DCBRDs.
2= connect succeeding DCBRDs to the specified special system buffer (=system VCI). The
system VCI number (=data buffer number) must be specified in SPEC pin. Otherwise the
operation resembles operation with CONFIG=0, i.e. the DCBRDs will get only new data
from the VCI, but no inquiries are made in order to get new data from DCB board.
3= request and receive local diagnostic data values from the DCB board. The ID-number of the
diagnostics buffer must be given through SPEC pin.
4= receive data via memory bank 2 (without requests).
5= receive inquiries via memory bank 2 (without requests).(CONFIG values 4 and 5 are
defined only for certain protocols and DCB boards.)
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Table 2 ( protocol-specific values for function parameters )

Protocol SAMI S3964 MFB
1 CHAN 1 or 2 1 or 2 1
2 SPEC independent of protocol:
0 = autoconfiguration of data length,
if CONFIG=0 or 1
nonzero = length of dataset,
if CONFIG=0 or 1
VCI number if CONFIG=2 or 3
3 STATION *** *** ***
4 IDENT 1 to 4000 256*DB+OFFSET 100*BUSN0+NODENO
5 CONFIG independent of protocol:
0 = passive receiver,
1 = active receiver,
2 = read spontaneously received
diagnostics
3= request diagnostics from DCB
*** = value is irrelevant.
Other Inputs
EN specifies whether receiving of new data values is locally supported or not. (If and so far as EN=0,
the DCBRD blocks are not requested to fetch new values from the DCB data buffers, or to send new
data inquiries to the DCB board.)
CLEAR is a dynamic input, which normally should be tied to 0. A rising edge on this pin will cause
abortion of any waiting processes concerning this function block. It will also restart the "FirstCycle"
phase in the operation sequence of the block.
Outputs
ERR is true if the dataset at the moment is disabled from receiving, because there is some failure, fault
or error preventing it.
STATUS is a word where various status information about the latest execution of the block instance is
packed.
ADDRD is an interconnection "hook" which must be used to associate the DCBRD instances to their
"parent" DCBREC.
ERRC is a numeric error code which describes the type of the present error situation. When the
communication continues without errors, the ERRC value will be automatically cleared.
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Functions
Allocation of VCI (=VCI record)
At initialization ( in special mode), DCBREC allocates for communication one VCI record from
system RWM. The VCI record is used as message buffer between DCBRD(s) and the driver.
Each VCI contains:

- handshaking, syncronization and coordination area for DCBRDs, DCBREC, DCB driver and
DCB-initialization task (= 24 bytes).
- a descriptor of record’s contents, which is passed to the DCB along with actual data (= 8
bytes).
- actual data (where the first word two bytes have such a special treatment that they are
initialized to the same value as found in IDENT-pin, when the VCI area is created by
DCBREC). The whole data area, and only the data area is accessible to DCBRDs to read the
received user data
The parameter RECS1 ( or RECS2 for CHAN 2 ) of the DB element DCB00 determines the total
number of VCI records and the parameter RECSIZE1 ( or RECSIZE2 for CHAN 2 ) the size of the
VCI record. Record size must be (see above) 32 higher than the actually needed data length for the
longest dataset of the channel.
The driver writes the received data into appropriate locations of the VCI record. DCBREC computes
(during initialization) the base address of the dataset within the VCI record and outputs the value on
terminal ADDRD. This terminal must be connected by the user (or type circuit) to the associated
DCBRDs, because it is the only way the DCBRDs can find their data buffer. (See below.)
ERR and STATUS.ERR are set if a VCI record cannot be allocated (due to missing DCB00,
DCBINIT or small insufficient memory).
Dataset Structure
The dataset is a continuous sequence of words (or more precisely, even number of bytes). After
reception of new data by the DCB driver, the DCBREC instance must detect the reception and enable
the successive sequence of DCBRD blocks to read the contents of the dataset. Each DCBRD reads a
number of items specified by its own size and starting from offset value given in OFFSET pin. A
DCBRD block is able to read part or whole dataset from dedicated VCI record if (and only if) its input
terminal ADDR is connected to the output terminal ADDRD of the DCBREC.
Any sequence of DCBRD blocks is allowed, as far as they are in the same task and after the associated
DCBREC. DCBRD blocks are protected from reading beyond the length of VCI. Each DCBRD
instance is also prevented from reading missing data. (Data is missing, if the dataset has not been
received since last execution of DCBREC, or if the length of received data is too short compared with
the size and starting offset of DCBRD.) However, DCBREC does not indicate it as an error condition,
presuming that some of the first DCBRDs were successful (=got enough data) even if some later
DCBRDs were disabled due to too short dataset. In the status word of DCBREC such a case is notified
by a SHORT bit. (To achieve this kind of size adaptivity, the DCBRD blocks must be arranged in
ascending order by their OFFSET pins, because any error in execution of DCBRDs disables the
remaining DCBRDs until they all are again enabled by DCBREC when next data comes from DCB
board.
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It is even possible to avoid SHORT indication in DCBREC status word, if the user knows that the
dataset will be too short for the last DCBRD(s). The method is to connect a TRUE Boolean value to
the LAST pin of the last DCBRD to be satisfied. Then the remaining DCBRDs are not even tried to
execute, and no flagging of data shortage will occur. The signal values for LAST pins may be even
derived from an output pin of the first DCBRD, which has to be executed anyway (and can never be
the last DCBRD of such adaptive configuration). I.e. the length of a dataset may be dynamically
declared within it, and still avoid all indications about errors or abnormalities. However, the last
really programmed DCBRD should have a constant TRUE value in its LAST pin, because if no
DCBRD knows to be the "last one", the VCI record will be left continuously reserved, and
consequently the DCB driver will never be able to put new data there.
Note: that several DCBRDs associated with same DCBREC may have the LAST input = 1. If so, all
DCBRDs after the first one, which had LAST=1, will be considered as "NoOperation" blocks, and
they do not update their output pins by anyway, i.e. they do not show any error code either.
Note: as well that any DCBREC block without any associated DCBRD causes similar functions, as if
there were DCBRDs, but without any one of them being the "last". Then reception of a dataset results
in continuous reservation status of the VFI area for the presumed DCBRDs, and consequently the
DCB driver is never again able to store new data into that buffer. The DCB driver will then very soon
run out of its temporary buffers, which are intended to store the data only temporarily while the final
destination buffer is reserved for DCBRDs. Especially notice that DCBRDs are as necessary when
DCBREC CONFIG-pin is 2 or 3 as they are in normal cases when CONFIG-pin = 0 or 1 (or 4 or 5).
Type Circuits
A type circuit consists of one DCBREC and a sequence of succeeding DCBRD blocks. A type circuit
may also include other kinds of function blocks. Type circuits are protocol specific.
The use of type circuits ensures that even the less "professional" programmers get their DCBRD
blocks in the same task and after the DCBREC and the last DCBRD block is flagged to be such. (If a
DCBRD is placed elsewhere, then ERR and STAT.ERR will be set and the DCBREC bypassed later.)
Standard type circuits are:

COM-CVI1 for MFB protocol
SAMI-IN for SAMI protocol
S5-IN for Siemens protocol S3964(R)
AB_IN for Allen-Bradley DF1 protocol.
Type circuits can be redesigned by adding , deleting or modifying DCBRD blocks. For MFB and
SAMI protocols this is not possible. Type circuits may contain also other function blocks to generate
LAST and ENABLE signals for the DCBRDs and to analyze the Statuswords of DCBREC and/or
DCBRDs. E.g. a timer circuit may monitor inside a type circuit that the DONE bit of DCBREC is not
zero for too long.
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Communication between DCBREC <-->DCBRD

DCBREC communicates with a DCBRD if terminals ADDRD and ADDR respectively are connected
together.
ADDRD is set by DCBREC, if initialization and buffer allocation succeeds. Otherwise ADDRD will
be left as 0, and thus prevents all functions of connected DCBRDs as well.
If no error has been detected before or during the initial phases of link establishment, DCBREC will
clear the "FirstCycle" bit in STATW and enter continuous operation.
(The state "First cycle" typically lasts for several execution cycles (if execution cycle is short) and
changes to normal operating state just after DCB board has got its parameters downloaded, accepted
them, and asks for normal cyclic data for the first time.)
The data area for this type of communication is in the same buffer as the data for DCBRDs, but in
negative offsets relative to ADDRD. Therefore this communication is invisible and protected from
application program.
Synchronization with DCB Driver

The data area for this type of communication is the same as used between DCBREC and DCBRDs
(i.e. in negative offsets).
The overall operation mode of DCBRDs, DCBREC and DCB driver depends on the value of the
function parameter CONFIG:
CONFIG = 0
The contents of data buffer is passed to DCBRD blocks every time, when first written by DCB
driver. No request for new data is sent to DCB board from DCBREC. The users must take care
by some other means that the desired data is (cyclically) sent from the remote communication
partner station.
CONFIG = 1
Whenever DCBREC is idle (or ready from previous dialog), it will send a data request message
to DCB board, and then wait for a response message. When the response message comes, it is
passed to DCBRDs just as in case CONFIG=0. The length of data may be specified through
SPECIAL pin. The start offset will be always=0, the IDENT pin value is used to specify which
data is requested from the remote station.
CONFIG = 2
This mode is very similar to CONFIG=0, but the IDENT pin has now no significance. Instead,
the SPECIAL pin shall specify which one of the system buffers is desired to access by
DCBRDs. There are system buffers of 4 types:
- error buffers (= for error messages from DCB board)
- unexpected buffers (= for unknown messages)
- temporary buffers (= for messages which cannot be stored directly to final buffer)
- special buffers (= for diagnostic messages from DCB boards)
The number of buffers of each type is normally a constant characteristic to the DCB board and
protocol. That is why it is impossible to declare here the exact value for SPECIAL pin in order
to access a specific system buffer of a specific type. (The application programmer does not
(normally) have any influence on the number of system buffers of each type.) And respectively
a DCBREC instance with CONFIG pin = 2 or 3 does not allocate any new buffer, but just
connects the associated DCBRDs to an already existing system buffer.
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CONFIG = 3
This mode is very similar to above (CONFIG=2) but with the difference that SPECIAL pin
must refer to a special (=diagnostic) buffer, and the data from the DCB board does not come
spontaneously but because it is requested by this DCBREC block.
CONFIG = 4
This mode is similar to CONFIG=0, except that the input data will be passed from DCB board
through a different memory page (=page 2).
CONFIG = 5
This mode is similar to CONFIG = 4, except that the input data is assumed to be a data
request. The CONFIG values 3, 4 and 5 must never be used if the connected DCB board does
not support them.
The last DCBRD is responsible for releasing the data buffer from the "reserved" state where it was put
by DCBREC. This will happen even if the ENABLE input of that DCBRD is =0.
DCBREC sets output bit STAT:DONE whenever it detects new data in the data buffer written there by
the DCB driver.
(Note: this happens before DCBRDs have yet processed the data, and even if they would fail to read
it from the buffer).
Startup of Communication
DCBREC has principally 3 different execution branches:
1. Initialization: Data buffer allocation and most checking about correct configuration is done during
this phase. Initializations are done in "Speta-branch" and therefore executed immediately after the
power assertion or after program download, but never thereafter. When the application is
temporarily blocked and then deblocked, this initialization code will not be executed at all. It is also
assumed inherently by DCBREC that Speta-branch will be run through only once, and therefore
DCBREC must not be enclosed in such CNTRM as is continuously run with RESET input = 1.
2. "First Cycle" phase: During this phase DCBREC is waiting that DCB board startup succeeds and
normal cyclic communication from DCB board to APC board starts.
3. Normal cyclic execution: It is possible to go back to "First Cycle"-phase by asserting a rising edge in
CLEAR pin.
Summary
All programming changes which have influence on the initial parameters of attached DCB board,
must be made so that the complete APC application program is stopped (=blocked) and then a new
(off-line generated) application program is downloaded, and then enabled (=deblocked). Anyway,
switching the power of APC station off and on is not necessary to trigger the initialization process of
DCB board to re-occur.
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Transmit Dataset to DCB DCBTRA

Summary
DCBTRA controls the transmission of one dataset over a Drive DCBTRA
Communication Board (DCB). A sequence of DCBWR blocks updates FI CHAN ERR 10
the contents of the dataset. The DCBWR blocks must precede the F2 SPEC
respective DCBTRA, and all of them must be in the same task. F3 STATION STATUS 11
DCBTRA (and preceding DCBWRs) can be used associated with various F4 IDENT ADDWR 12
protocols.
F5 CONFIG
In application programming, protocol -specific type circuits composed of
one DCBTRA and DCBWRs may be used, and thus relieve the user from 1 EN
entering the multiple function blocks which are necessary for sending a 2 >CLEAR ERRC 99
dataset from APC. The standard -type circuits for certain protocols will
be available for users (table 2). Figure 1. PC Element
DCBTRA
In order to make DCBTRA operative (really transmitting) it is necessary
that:
The DB element DCB00 be inserted, and there be declared appropriate number of buffers and size of
each buffer (=sufficient for the protocol and the intended maximum dataset length).
The protocol declared by the DCB00 element must be resident in firmware of the DCB hardware (i.e.
the DCB board must be of correct type).
At least one DCBINIT function block for the DCB channel must be included in the application
program (and in such a place that all DCBINITs of the channel are executed before any DCBTRA
comes to execution).
Call DCBTRA
Connections Table 1
F1 CHAN II CHANnel number 1

F2 SPEC II E.g. message priority ** 0
F3 STATION II STATION number ** 0
F4 IDENT II Message IDENTity ** 0
F5 CONFIG II CONFIGuration word 0
1 EN IB ENabled if set
2 CLEAR IB CLEAR when 0 ->1
10 ERR OB ERRor
11 STAT OI STATus word
12 ADDWR OIL Base address of dataset
99 ERRC OI ERRor Code
** The significance depends on the protocol.
STAT output word consists of the bits:

bit 0 ACT Set in normal operation when EN = 1.
bit 1 INITOK Set when initialization is OK.
bit 2 CLEAR Set when dataset has been cleared.
bit 3 FIRST_CYCLE Set on init. or after CLEAR assertion. Reset after
the first cycle.
bit 4 RDY Set if ready to transmit.
bit 5 BUSY Set when waiting for acknowledgement.
bit 6 DONE Set after each data transfer to DCB board (CONFIG
= 0) or on positive acknowledgement (CONFIG = 1)
and after each auto-answer (CONFIG =3).
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bit 7 FAIL Set on negative acknowledgement (CONFIG = 1).

bit 8 REQUEST Set on external request (CONFIG = 2).
bit 9 to 13 Not used
bit 14 DESTRUCT Set by Destruct, reset at successful Construct.
bit 15 ERR Set on error.
Any STAT bit can be extracted by the function block BITGET if the signal is needed for other
function blocks in the application program.
Function Parameters
CHAN ( F1 )
The used communication channel of the DCB board.
E.g. with the multiprotocol UART board YPK113, CHAN may be 1 or 2. (DCBTRA allows channel
numbers 1 to 4, but the presently available hardware and DCB00 DB-element support max.2
channels).
SPEC ( F2 )
Special parameter, which can mean e.g. the message priority.
Typically nonzero values of SPEC specify the length of the dataset to be less than what would result
from automatic length configuration based on offsets and lengths of DCBWRs. (If SPEC=0, automatic
length configuration will be used).
STATION (F3)
Remote station number for multinode serial buses.
In MasterFieldBus the station numbers are not declared here, but implicitly as node number in the
IDENT pin. (See below.)
IDENT (F4)
The message identifier ( table 2 ).
CONFIG (F5)
Specifies desired operation mode:
0= transmit new values every time (presuming that DCBWRs have written new values in buffer
since last execution of DCBTRA).
1= prepare and transmit new values just after the previous transmission is acknowledged by the
remote station (and the acknowledgement passed to this DCBTRA by the local DCBboard), or
the transmission efforts are considered useless and stopped. While the acknowledgement is
waited for, the DCBWRs are disabled (relieved) to write anything into the transmission buffer,
and thus the next values for transmission will be brand-new, i.e. written just after the
acknowledgement of previous transmission was received.
2= send only answers to received inquiry commands (and then wait first for data from the
associated DCBWRs).
3= Auto-Answer mode, i.e. send only answers, but allow the associated DCBWRs to prepare
continuously answer data into the transmission buffer. When the data request comes from the
remote station, the reply message will be sent immediately by the DCB driver and contains the
prepared data from the last executed DCBWRs.
4= transmit a reply message via memory bank 2.
5= transmit a confirmation message via memory bank 2.(CONFIG values 4 and 5 are defined only
for certain protocols and DCB boards.)
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Table 2 (protocol-specific values for function parameters)

Protocol SAMI S3964 MFB
1 CHAN 1 or 2 1 or 2 1
2 SPEC *** *** ***
3 STATION *** *** ***
4 IDENT 1 to 4000 256*DB+OFFSET 100*BUSN0+NODENO
5 CONFIG 0 1 to 3 0
*** = value is irrelevant
Other Inputs
EN specifies whether sending of new data values is locally supported or not. (If and so far as EN=0,
the DCBWR blocks are not requested to update the DCB-data buffers, and the DCB-driver software
will not send respective data to the DCB board).
CLEAR is a dynamic input, which normally should be tied to 0. A rising edge on this pin will cause
abortion of any waiting processes concerning this function block. It will also restart the "FirstCycle"
phase in the operation sequence of the block.
Outputs
ERR is true if the dataset at the moment is disabled from transmission, because there is some failure,
fault or error preventing it.
STATUS is a word where various status information about the latest execution of the block instance is
packed.
ADDWR is an interconnection "hook" which must be used to associate the DCBWR instances to their
"parent" DCBTRA.
ERRC is a numeric error code which describes the type of the present error situation. When the
communication continues without errors, the ERRC value will be automatically cleared.
Functions
Allocation of VCI
At initialization ( in special mode), DCBTRA allocates for communication one VCI record from
system RWM (from the area which was allocated to the channel due to input values of DCB00).
The VCI record is used as data buffer between DCBWRs and the DCB driver.
Each VCI contains:
- handshaking, syncronization and coordination area for DCBWRs, DCBTRA, DCB driver
and DCB-initialization task (= 24 bytes).
- a descriptor record is which is passed to the DCB along with actual data (= 8 bytes).
- actual data, (where the first word two bytes have such a special treatment that they are
initialized to the same value as found in IDENT pin, when the VCI area is created by
DCBTRA) The whole data area, and only the data area is accessible to DCBWRs to write
user data.
The DB element DCB00 terminals RECS1 and RECSIZE1 ( RECS2 and RECSIZE2 for CHAN 2 )
determine the number and size of the available VCI records for a channel (independent of the other
channel). Record size in DCB00 must be (see above) 32 higher than the actually needed data length
for the longest dataset of the channel.
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DCBTRA computes the base address of the dataset and outputs the value on terminal ADDWR. This
terminal must be connected by the user (or type circuit) to the associated DCBWRs, because it is the
only way the DCBWRs can find their data buffer. (See below.)
If a VCI record cannot be allocated then ERR and STAT.ERR are set.
Dataset Structure
The dataset is a continuous sequence of words (or actually, even number of bytes) which are updated
by a sequence of DCBWR blocks. Each DCBWR writes a specified number of words or double words
(=integers, long integers or reals) starting from OFFSET. Allowed values of OFFSET are (0 to end of
data area in VCI record).
OFFSET value must be given as a "byte offset" regardless of data type. (The purpose of this is to allow
character data in future, although present DCBWRs write only words and double-words).
A DCBWR block is connected to the dataset specified by its input terminal ADDR ( = connected to
the output terminal ADDWR of resp. DCBTRA).
Any sequence of DCBWR blocks is allowed. DCBWR blocks are prevented from writing over the
limits of the allocated data area in the VCI record, (but no safeguarding method prevents subsequent
DCBWR instances from overwriting each other’s updated data. It is possible as well to leave some
parts in the beginning, middle or end of the data area without any writing DCBWR. Those data-items
will be transmitted as zeroes, if there is some really written data after them, but the unwritten area at
the end of data area will not be sent at all. (An exception is when a remote station asks for certain
data length, then the answer data length will be as defined in the request, and even unwritten values
from the end of buffer may be included in the response message. And another exception is if there is a
smaller value connected on input pin SPECIAL: Then the data updated by DCBWRs in higher offsets
will never be passed to DCB board.)
A single data set may (in principle) contain both integer, long integers and reals. However, some
protocols, or their applications, (e.g. S3964), forbid such conventions.
The only limitation to the dataset composing DCBWRs are, that

1. All DCBWRs must be in the same task.
2. They must be located in execution order before resp. DCBTRA.
Type Circuits
A type circuit consists of one DCBTRA and a sequence of preceding DCBWR blocks. The type circuit
may also include other kinds of function blocks. Type circuits are protocol specific (or even
application specific ?).
Use of type circuits ensures that the DCBWR blocks reside in the same task and precede the
DCBTRA. If a DCBWR is placed elsewhere, then ERR and STAT.ERR will be set and DCBTRA
bypassed later.
Standard type circuits are:

COM_CVO1 for MFB protocol
SAMI_OUT for SAMI protocol
S5_OUT for Siemens protocol S3964R
AB_OUT for Allen-Bradley DF1 protocol
Use of provided type circuits ensures as well that the CONFIG and SPEC inputs are connected to
appropriate constants, and the connection between DCBWRs and DCBTRA is made automatically.
Type circuits can be redesigned by adding, deleting or modifying DCBWR blocks. For MFB and
SAMI protocols this is not possible.
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Communication between DCBTRA <-->DCBWR

DCBTRA communicates with a DCBWR if terminals ADDWR and ADDR respectively are connected
together.
ADDWR is set by DCBTRA if initialization and buffer allocation succeeds. Otherwise ADDWR will
be left as 0, and thus prevents all functions of connected DCBWRs as well.
If no error has been detected before or during the initial phases of link establishment, DCBTRA will
clear the "FirstCycle" bit in STATW and enter continuous operation.
(The state "First cycle" typically lasts for several execution cycles (if execution cycle is short) and
changes to normal operating state just after DCB board has got its parameters downloaded, accepted
them, and asks for normal cyclic data for the first time.)
The data area for this type of communication is in the same buffer as the data from DCBWRs, but in
negative offsets relative to ADDWR. Therefore this communication is invisible and protected from
application program.
The overall operation mode of DCBWRs, DCBTRA and DCB driver depends on the value of the
function parameter CONFIG:
CONFIG = 0
The data buffer is continuously assembled, and passed to DCB board whenever possible. No
remote acknowledgement is required before next transmission. The user must be careful not to
send more often than physically possible, because the FIFO output buffer in DCB board may
become full (and even if not full, it is most efficient to have only one copy of the dataset in
transmission FIFO, otherwise newer data transmissions will be delayed, because DCB must
send all data in the same order as passed by DCB driver (i.e. older copies first).
CONFIG = 1
A new message is not written, or sent, before the previous has been acknowledged.
DCBTRA sets the BUSY bit in STATW which his reset after the DCB board has responded
with a positive or negative acknowledgement (or after a long time-out by the DCBTRA itself).
CONFIG = 2
A new message is prepared and loaded on request from DCB board (i.e. typically on external
request from the external communication channel). The STATW output will indicate when
such a request is active. However, the application designer does not need to interprete or
connect this bit anywhere. The respective information is passed internally to DCBWRs, and
can be seen there as DONE bit whenever they produce an answering dataset for such external
request.
CONFIG = 3
New messages are prepared continuously, but presented to the driver only if, and when,
externally requested. The driver checks and sees if a flag AutoAnswer is set, and if the data
buffer contains valid data, it gives the data immediately back to the DCB board (and from
there the DCB-board firmware shall pass it to the external requester).
CONFIG = 4
This mode is similar to CONFIG=0, except that the message will be passed to DCB board
through a different memory page.
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CONFIG = 5
This mode is similar to CONFIG=0, except that the message will be passed to DCB board
through a different memory page. (Difference between CONFIG 4 and 5 is that they introduce
different type of a message to the DCB board. The CONFIG values 4 and 5 must never be
used if the connected DCB board does not support them.)
Start-up of communication
DCBTRA has principally 3 different execution branches:
1. Initialization: Data buffer allocation and most checking about correct configuration is done
during this phase.Initializations are done in "Speta-branch" and therefore executed
immediately after the power assertion or after program download, but never thereafter.
When the application is temporarily blocked and then deblocked, this initialization code
will not be executed at all. It is also assumed inherently by DCBTRA that Speta-branch
will be run through only once, and therefore DCBTRA must not be enclosed in such
CNTRM as is continuously run with RESET input = 1.
2. "First Cycle" phase: During this phase DCBTRA is waiting until DCB board start-up
succeeds, and normal cyclic communication from DCB board to APC board starts.
3. Normal cyclic execution: It is possible to go back to "First Cycle" phase by asserting a
rising edge in CLEARpin
Summary
All programming changes, that have influence on the initial parameters of attached DCB board, must
be made so that the complete APC application program is stopped (=blocked) and then a new (off-line
generated) application program is downloaded and then enabled (=deblocked). Anyway, switching the
power of APC station off and on is not necessary to trigger the initialization process of DCB board to
re-occur.
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Write to DCB dataset DCBWR

Summary
DCBWR writes a fraction of a dataset. The transmission of the dataset is DCBWR
controlled by a DCBTRA block. A complete dataset can be built up by a (C1,C2)
F1 OFFSET ERR 10
sequence of one or several DCBWR blocks.
DCBWR blocks can be inserted and associated with the respective 1 ADDR
DCBTRA block easiest by using protocol-specific type circuits. 2 EN STATUS 11
21 IN1
20 + C2 INC2
Call DCBWR Table 1 DCBWR
C1 Datatype I, IL or R
C2 Number of data inputs 1 to 16
Connections Table 2
F1 OFFSET II Offset of data fraction from beginning of dataset.

1 ADDR IIL Internal ADDRess of dataset within system RWM.
2 EN IB If set, writing is permitted by the appl. program.
10 ERR OB Set if DCBWR or DCBTRA programmed wrong.
21 IN1 IC1 INput 1
20+C2 INC2 IC1 INput C2
Status
Individual bits whose values can be extracted, if needed, from the STATUS word by a BITGET
function block.
bit 0 ERR Set in initialization error (= output terminal 10).

bit 1 Not used.
bit 2 DESTRUCT Set if destructed, Cleared if successfully
reconstructed.
bit 3 FIRST_CYCLE 1 = after initialization cycle, 0 = always
afterwards.
bit 4 OFFS_ERR 1 = this block tries to access too far in the buffer.
bit 9 WR_DONE Set if data has been written.
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Function
The operation of DCBWR is controlled by an overriding DCBTRA by the internal flags which are
invisible to the application programmer. The DCBTRA is able to control DCBWR if its terminal
ADDWR is connected to terminal ADDR of the DCBWR. The DCBWR block should precede the
matching DCBTRA, and they both must be inserted in the same CNTRM (or respective execution
unit).
DCBWR has no influence on DCB board, if the DCBTRA is missing or inoperative.
ADDR is the base address of the dataset.

ADDR must be connected to the output terminal ADDWR of DCBTRA. ADDR must never be
connected elsewhere.
OFFSET is the offset of this data fraction from beginning of the data area of the internal buffer, which
is common to DCBTRA, DCBWR(s) and DCB-driver software. (ADDR value points to the data byte
with offset = 0).
DCBWR block will write C2 elements of datatype C1 into the data area starting from physical address
ADDR + OFFSET.
During the first cycles of program execution DCBWR checks that ADDR, OFFSET and C2 are legal.
DCBWR is not permitted to exceed the range of the allocated data buffer (defined in DCB00 data base
element). If a programming error is detected, then the outputs ERR and STATUS.ERR are set. (And
all writing will be prohibited during successive execution cycles.) Additionally during the first cycle,
the DCBWR(s) will configure the data type and the data length into the header part of the data buffer.
(The first DCBWR sets the data type of the message. A succeeding DCBWRs change the datatype to
"mixed type" if their datatypes are different.
The length of dataset is automatically configured so that each DCBWR computes the end-offset of its
data fragment, compares it with the value stored in dataset header (by other DCBWR instance) and
updates the greater value, if necessary. This automatic length configuration is participated by every
DCBWR, regardless of input value in EN pin).
Note: however, that this automatic length configuration may be overwritten by a length value
connected in SPECIAL pin of DCBTRA, and thus it is possible to specify a shorter dataset than the
DCBWRs would configure.
After the first cycles ( in normal mode ) DCBWR copies input data to the data buffer (into the location
specified by OFFSET), if, and when the associated DCBTRA requests it to do so (presuming EN input
of DCBWR is = 1). The circumstances or conditions when this happens are:
- continuously, if DCBTRA CONFIG value = 0 (for immediate spontaneous

transmission),
- after an acknowledgement of previous transmission has come from DCB board, if
DCBTRA CONFIG value = 1,
- after a new inquiry message has come from DCB board, if
DCBTRA CONFIG value = 2,
- continuously (in order to prepare for new inquiry messages from DCB board), if
DCBTRA CONFIG value = 3.
If DCBTRA does not request new data, or if the EN-input pin = 0, DCBWR does not update the data
in the data buffer (and thus there will remain the old values written before EN changed to 0).
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Errors
Writing is prohibited and the ERR terminal is set if :
- DCBTRA is missing or inoperative,
- DCBTRA not in the same task,
- ADDR is not connected to a DCBTRA,
- ADDR or OFFSET is odd,
- OFFSET is out of range of data buffer,
- C2 too great (together with OFFSET value) and causes writing of data outside the
range of data buffer.
Note: that DCBWR can not detect if it is programmed to overlay data written by some other DCBWR
instance associated with the same dataset. However, it is protected by system software so that
DCBWRs associated with different datasets (i.e. different DCBTRAs) cannot conflict or interfere with
each other.
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Demultiplexer DEMUX-MI
Summary
DEMUltipleXer with Memory and Integer address is a function block DEMUX-MI
used as a demultiplexer with a memory function. An optional number (C1,C2)
1 S 5
of outputs can be specified. Integer, real, boolean, or time datatypes can AERR
2 L
be used.
3 R
11 A
31 I OA1 51
.. ..
OA * C2 50 + C2
Call DEMUX-MI (C1,C2)

Call Parameters Table 1 DEMUX-MI
C1 Data type I, IL, R, B, T, TR

C2 Number of outputs1 to 19
Connections Table 2
No Nam Type Description Values

e
1 S IB Set. Input for loading of new values each time the
element is executed. When the input S is reset (to 0),
the outputs will retain their most recently loaded values.
2 L IB Load. Dynamic input for loading of data from the input
I to the output addressed by the input A.
3 R IB Reset. Input for resetting the outputs. This input
overrides
the inputs S and L.
5 AERR OB Address ERRor. Set (to 1) when input A is greater than
call parameter C2 or a negative value.
11 A II Address. Selection of which output, the value loaded at
I should be stored. If the value is 0, 0 is stored at all
outputs.
31 I IC1 Input. Data input.
50 OA1 OC1 Output Address 1. The first output from the
demultiplexer.
.
.
.
50+C2-1 OAC2 OC1 Output Address C2. The last output from the
demultiplexer.
Function Addressing
The input address A (1 to C2) specifies at which output (OA1 to OAC2) the data value at input I is to
be stored. If A is 0 then the value 0 is store at all outputs.
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Loading
If the value of L is 1 when the function block DEMUX-MI is executed and the value of L was 0
during the previous execution, then the value at input I is loaded. If the input S is set, new data from
the input I is loaded each time the function block is executed. When S is reset (to 0 from 1), the data
most recently loaded remains until one of the inputs S, L, or R are set.
The input S overrides the input L. When S is set L has no meaning.
Clearing
When the input R is set (to 1) the data outputs (OA1 to OAC2) are reset (to 0) and data is not loaded
at the input I.
Supervision
The value of the input address A is checked each execution of the function block. If it is greater than
the number of outputs specified by the call parameter C2 or it is a negative number, then the AERR
output is set (to 1). The data value 0 is stored at all outputs.
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Derivator DER
Summary
DER (DERivator is used to give derivation effect. The derivation DER
1 I O 10
effect can be limited with the filter function, which serves as a low O = HL
2 K 11
pass filter. O = LL
3 TD 12
The output signal can be limited with limit values specified at special 4 ERR 13
TF
inputs. 5 RDER
The balancing function permits the output signal to track an external 6 BAL
reference and permits a bumpless return to the normal function. 7 BALREF
All transfers from static states are bumpless. 8 OHL
9 OLL
Call DER
Figure 1. PC Element DER
Connections Table 1
1 I IR Input. Input for actual value.

2 K IR Input for setting gain.
3 TD ITR Time Derivation. Input for time constant for derivation.
4 TF ITR Time filter. Input for filter time constant.
5 RDER IB Rset DERivator. Input for clearing derivator.
6 BAL IB BALance. Input for activation of tracking.
7 BALREF IR BALance REFerence. Input for reference value when
tracking.
8 OHL IR Output High Limit. Input for upper limit value.
9 OLL IR Output Low Limit. Input for lower limit value.
10 O OR Output. Output signal.
11 O = HL OB Output = High Limit. Output which is set to 1 if the
output reaches to the upper limit value.
12 O = LL OB Output = Low Limit. Output which is set to 1 if the
output reaches the lower limit value.
13 ERR OB ERRor. Output which is set to 1 if OHL is less than OLL.
Function
The step response in the time plane for a TD
derivator is: K
O(t) = K (TD/TF)e -VTF x I(t) TF
where I(t) specifies the magnitude of the
step.
The transfer function for a DER function
is:
t
G(s) = K(s x TD)/(1 + s x TF) TF
This has been implemented in the DER Figure 2. Step response
element as a recursive algorithm.
The design of the algorithm is such that
normal functioning is maintained even during limiting. This ensures a controlled return to a dynamic
state.
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Gain, Derivation-, Filter- and

Sampling Time IgIGI
Certain constants are precalculated to
TD
make the execution time of the element as K
short as possible. The results are stored TF
internally in the element. These constants
are recalculated if TD, TF or K are
changed by more than 1/128 of their
previous value, or if the sampling time TS
Igω
is changed. When recalculating a test is
performed to check whether TD and TF ≥ 1
2 x TS. If not, TD and/or TF are equal to TF
2 x TS.
Clearing of the Derivator

Both the output O(t) and the internal state of
G
the output are cleared when RDER goes to 1.
Tracking + 90
If BAL is set to 1, the derivator immediately + 45
goes into tracking and the output O is set to
the value of the input BALREF. If the value at
Igω
BALREF exceeds the output signal limits, the
1
output is set to the applicable limit value.
Return to dynamic state is bumpless. TF
Figure 3. Bode diagram
Limitation Function
The limitation function limits the output signal to
the values at the inputs OHL for upper limit and
OLL for the lower limit. If the actual value
exceeds the upper limit, the output O = HL is set
to 1. If it falls below the lower limit, the output O OHL
= LL is set to 1. The element checks that the upper
limit value OHL is greater than the lower limit
t
value OLL. If not, the output ERR is set to 1.
While the error status persists, the outputs O =
HL, O = LL and O retain the values they had in Figure 4. Function in a limiting state
the sample before the error occurred. After an
7 OHL
8 OLL
ACT
O 10
5 BAL
ACT
6 BALREF
I1 0 =HL 11
I1 > I2
1 DER I2
I
2 I1 O = LI 12
K I1 < I2
3 I2
TD
4 TF t I1 ERR 13
I1 < I2
I2
5 RDER RESET
1 PRESET
ACT
error, the return to a dynamic state is bumpless, such as in the case of tracking above.
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Digital Input DIAPC

Summary
Digital Input APC element is used to read the four digital input channels DIAPC
O1 11
available directly on the APC board. A common input time constant for signal T
O2 12
filtering is defined by an input parameter.
O3 13
O4 14
O 19
Call DIAPC
Figure 1. PC
Element DIAPC
Connections Table 1
1 T II Filtering Time for the digital inputs 0..32767 [ms]

signals in mill-seconds.
11 O1 OB Output of channel 1 after filtering. See table 1.
19 O OI Packed value of input channels 1 to 4 See table 2.
without filtering.
State Voltages Table 2
State Signal voltage
Off (0) 0 to +5 VDC

On (1) +19 to +30 VDC
Note: Input channel 1 is hardware filtered 0.48 ms. Input channels 2 to 4 are hardware filtered 4.8
ms.
Function
The APC board hardware includes four onboard digital input channels. The DIAPC element provides
application software a direct access to those channels.
The DIAPC element reads all inputs simultaneously without any drivers. Every input channel is
filtered using the filtered time constant specified by the input T. This time constant defines the time
required for a channel to be in an on or off state before a new state is accepted.
If the time constant T is equal to or less than 0 then there is no filtering on the input channels. If T is
greater than 0 but less than the execution interval (cycle time) of the DIAPC element then an input
must be in the same state a minimum of two execution cycles before the new state is accepted.
The filtered values of the input channels can be read at outputs O1 to O4. The packed value,
according to table 1 below, of the four input channels is loaded to output O.
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Packed Output Table 3
Channel Packed Output O

1 2 3 4 O
0 0 0 0 0
1 0 0 0 1
0 1 0 0 2
1 1 0 0 3
0 0 1 0 4
1 0 1 0 5
0 1 1 0 6
1 1 1 0 7
0 0 0 1 8
1 0 0 1 9
0 1 0 1 10
1 1 0 1 11
0 0 1 1 12
1 0 1 1 13
0 1 1 1 14
1 1 1 1 15
Note: When used with AC voltage signals, filter time should be set to a minimum 10ms.
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Digital Input Extended IO DIEXT

Summary
Digital Input EXTended element is used to read the eight digital input DIEXT
channels available when an extended I/O board YPQ110 or YPQ111 is F1 BOARD ERR 10
connected to the APC board. A common input time constant for signal 1 T1 01 11
filtering is defined by an input parameter. 2 T2 02 12
3 T3 03 13
4 T4 04 14
5 T5 05 15
6 T6 06 16
7 T7 07 17
8 T8 08 18
O 19
OF 20
99
Call DIEXT ERRC
Connections Table 1 DIEXT
F1 BOARD II Hardware address of the extended I/O 0 to 15 or 100 to 115

board on the parallel bus.
1 T1 II Filtering time for digital input signal 1 0 to 255 [ms]
2 T2 II Filtering time for digital input signal 2
10 ERR OB Error detection
11 O1 OB Output 1 of the channel after filtering
19 O OI Packed signal output before filtering
20 OF OI Packed signal output after filtering
99 ERRC OI ERRor Code See "Error Codes"
State Voltages Table 2
State detected Signal voltage

by a digital input
Off (0) 0 to +5 VDC
On (1) +19 to +30 VDC
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Error Codes
The DIEXTelement generates Error codes according to the general formula for I/O extension board:
Code# Description

64+2 power fail
64+16 AO1 fault
64+32 AO2 fault
Range faults are detected only if there are no hardware faults and although not related to the DI
Code# Description

11 AI1 rance fault
12 AI2 rance fault
13 AI3 rance fault
14 AI4 rance fault
15 AI5 rance fault
16 A16 rance fault
17 A17 rance fault
18 A18 rance fault

40 board missing
66 power fail
81 AO1 fault
82 AO2 fault
83 AO3 fault
84 AO4 fault
Function
The YPQ110 extended I/O board includes eight and the YPQ111 extended I/O board sixteen digital
input channels. The DIEXT element provides application software with a direct access to eight
channels.
The address is defined with function parameter BOARD and it must have same value as the address
selector in I/O board, or value of address selector + 100.Board numbers 100 to 115 mark upper part of
digital inputs (inputs 9 to 16) on hardware address 0 to 15 (YPQ111).
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The DIEXT element reads all inputs simultaneously. Every input channel is filtered with the time
constant specified by the input T. This time constant defines the period of time during which the
detected state should remain unchanged in order to be accepted for the input signal value.
If the time constant T is equal to or less than 0 then there is no filtering on the input channels.
ERR and ERRC are used to indicate a hardware fault of the I/O board.
Note: When used with AC voltage signals, filter time should be set to a minimum 10ms.
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Divider DIV
Summary
DIV is used for division of two integers or real numbers. When dividing integers, 1 DIV 20
the quotient is obtained with the remainder at a separate input. 2 REM 21
Figure 1. PC
Call DIV (C1) Table 1 Element DIV
Connections Table 2
1 - IC1 Input for dividend.

2 - IC1 Input for divisor.
20 - OC1 Output for quotient.
21 REM OC1 REMainder. Output for remainder.
Applies only with division of integers.
Function
The value at input 1 is divided by the value at input 2. The quotient is stored at output 20. When
dividing integers, the remainder is stored at the output REM.
Overflow
If the maximum positive or negative values are exceeded, the output is limited to the highest or lowest
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Divider DIV-MR
Summary
DIVider with Multiplier Real numbers is used for the division of two 1 DIV-MR
... . 40
products of real numbers. X
C1 .
21
...
X
20 + C2
Call DIV-MR (C1,C2) Figure 1. PC Element DIV-
MR
C1 Number of inputs in the first 1 to 19

multiplication element.
C2 Number of inputs in the second 1 to 19
multiplication element.
Connections Table 2
1 - IR Factor for the dividend.

2 - IR Factor for the dividend.
... - IR Factor for the dividend.
C1 - IR Factor for the dividend.
21 - IR Factor for the divisor.
22 - IR Factor for the divisor.
.... - IR Factor for the divisor.
20+C2 - IR Factor for the divisor.
40 - OB Output for quotient.
Function
The product of the real numbers at the inputs 1 to 3C1 is divided by the product of the real values at
the inputs 21 to 20 + C2. The quotient is stored at the output 40.
Overflow
If the maximum positive or negative real number is exceeded, the output is limited to the greatest or
lowest representable value respectively.
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Digital Output DOAPC

Summary
Digital Output APC element is used to update the two digital output channels DOAPC
available directly on the APC board. 1 I1
2 I2
Figure 1. PC
Element DOAPC
Call DOAPC
Connections Table 1
1 I1 IB Input to channel 1.
2 I2 IB Input to channel 2.
Function
The APC board hardware includes two digital output channels. The DOAPC element provides
application software with a direct access to those channels.
The DOAPC element writes both outputs simultaneously to the output channels.
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Digital Output Extended IO DOEXT

Summary
DOEXT (DIgital output EXTended I/O) element is used to control DOEXT
eight digital output channels on the optional YPQ110 or YPQ111 I/O F1 BOARD ERR 10
board, which is connected to the parallel APC bus. The hardware 1 I1 ERRC 99
address of the I/O board is selected with a function parameter. 2 I2
3 I3
4 I4
5 I5
6 I6
7 I7
8 I8
Call DOEXT
DOEXT
Connections Table 1
F1 BOARD II Hardware address of the I/O board in the parallel bus

1 I IB Boolean input to write to the digital output 1 on I/O board.
10 ERR OB Boolean output to indicate error
99 ERRC OI ERRor Code *see "Error Codes"
Function
The YPQ110and YPQ111 extended I/O board hardware includes eight digital output channels. The
DOEXT element provides the application software with a direct access to those channels. The
DOEXT element writes to all of the channels simultaneously.
The address is defined with function parameter BOARD and it must have same value as the address
selector on I/O board.
ERR and ERRC are used to hardware fault indication of I/O board.
Error Codes
The DOEXT element generates Error codes according to the general formula for I/O extension board:

Only two of the I/O Board hardware faults are meaningful for the operation of the DOEXT element:
5000 + 100*BOARD(NR) +1 IO parallel bus error

5000 + 100*BOARD(NR) +2 IO board power failure
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Code# Description
1 Parallel bus error

64+2 Power fail
64+16 AO1 fault
64+32 AO2 fault
Range faults are detected only if there are no hardware faults and although not related to DO
Code# Description

11 AI1 rance fault
12 AI2 rance fault
13 AI3 rance fault
14 AI4 rance fault
15 AI5 rance fault
16 A16 rance fault
17 A17 rance fault
18 A18 rance fault

40 board missing
66 power fail
81 AO1 fault
82 AO2 fault
83 AO3 fault
84 AO4 fault
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Diagnostic Function Block for DriveLink

DRDIAG
Summary
The DRDIAG (DRive DIAGnostic) block is used to give
indications or warnings about misbehaviour or
undesired occurrences in communications between APC
and underlying ABB drives DDC-units (= Digital Drive
Controller -units).
These warnings or alarms are most useful, when given
before the actual communications is considerably
disturbed or handicapped by these occurrences. And
because the respective error indicators of actual
operational function blocks (DRREC, DRTRA etc.)
indicate errors just after the physical circumstances are
so severe, that they really prevent communication, this
diagnostic function block is written for and available to
the service personnel to find and remove the potential
communication faults before they really have any
damaging influence on the system.
Call DRDIAG(C1,C2)

Figure 1. PC Element DRDIAG
Parameter Description Permissible

values
C1 ID number of first drive 1 to 4
This value specifies which drive is the first one to have
dedicated output pins for STATUS, BREAKS, BRTIME,
FAILCNT, FAILRATE, WORST and REASON.
C2 Number of drives 1 to 4
this value specifies how many drives will have dedicated
output pins for STATUS, BREAKS, BRTIME, FAILCNT,
FAILRATE, WORST and REASON starting from drive C1.
The sum C1+C2 can be less but not higher than the number
of drives specified by DRL00, all drives must be assigned to
contiguous ID-numbers.
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Connections Table 2
1 ENABLE IB Enable or bypass all functions 0 = bypass

2 RESET IB Reset all error counters of drive link
communication software (on either
edge of this Boolean signal)
O10..13 STATUS OI Status of each links:
0= link broken
1= link exist, but APC aplication not running
2= link exist, and APC application running but no datasets
configured
3= link exist, but drive has not responded yet to START
CYCLIC-cmd.
4= link exist, and cyclic datasets operational.
If the status value is 65 to 68, it indicates, that the link is presumably broken, and APC is sending
continuously GetLinkStatus requests to the drive. However, if the drive responds with good response
(= LINK OK), APC may change the state back to original, by subtracting 64 from this value.
If the status value is 128 to 134, it indicates, that the link status is just changing into 128 lower value,
and APC is just waiting for confirmation from the drive, that link change command is accepted there
as well. E.g. if STATUS = 132, it means, that APC has sent START_CYCLIC_COMMUNICATION
command to the drive, but has not yet received any response.
Table 2 continued
O15..18 BREAKS OI Number of link breaks caused by multiple consecutive

failures at the link (blocking of APC-program causes
also an analogous link break, but because intentional,
they are not counted into these values.)
O20..23 BRTIME OI Longest duration of a break at each link. (unit = poll
interval)
O25..28 FAILCNT OI Number of malfunctions at each link
O30..33 FRATE OI Failure rate at each link (100 * percentage of
malfunctions / all poll cycles, i.e. 100 means, that 1
percent of all cycles have failed
O35..38 WORST OI Length of the worst occurred communication
disturbance. (Communication disturbance = period of
sequential poll failures.) If communication disturbance
lasts longer than 100 ms (= 50, 25, 16 or 12 sequential
polls depending on number of drives) the link is
considered to be broken. (see outputs O15..18) The
critical number of sequential failures may be defined to
be longer by assigning it to SCAN-value of "basic
DRREC". If it is there specified higher than 255, a break
will never be caused by decision of APC, (but even in
that case the drive may cause a link break, which is
detected, recorded, and reacted by APC. The exception to
this rule is SCAN values >900: then the critical value of
failures is SCAN - 900. WORST-pin can count only up
to 255.
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Table 2 continued
O40..43 REASON OI Most recent reason to send NACK or to repeat

transmission.
1 = CRC-error,
2 = frame overwritten in receiver due to delayed DMA,

3 = carrier detect lost during reception,
4 = abort-flag within the frame,
5 = bit count not divisible by 8,
6 = too long frame to fit in the reception buffer,
7 = message came too late,
8 = no frame was received in time,
9 = the frame was sent by another drive than presumed.
98 ERR OB Execution successful/failed 0 = good value
99 ERRC OI Why execution failed:
0= success
1= illegal DR_ID value (no such drive exists)
Application guidelines
DRDIAG function block causes some processor load, although does not do anything "useful".
Therefore it is recommended to be located in a seldom driven task. It is also thought that the
ENABLE-pin of DRDIAG could be tied continuously to 0, and only temporarily forced to 1 while the
service technician is looking at the diagnostic outputs. Note: that all diagnostic counters are
operational and count upwards if respective errors occur, even if DRDIAG block is disabled by
ENABLE = 0. ENABLE-pin has influence only on the updating of the output pins, and the actual
error counters do not reside in those output pins.
DRDIAG is thought to be inserted in 2 alternative ways (assuming full 4 drive configuration):
1. Insert DRDIAG only once and assign values C1=1 and C2=4.
The advantage is, that the user may easier compare the behaviour of the
links with each other, but the disadvantage is the big size of the block
picture.
2 Insert DRDIAG 4 times with values C1= 1,2,3 and 4, and C2 = 1 in all
instances. The advantage of this method is, that physical size of the block
pictures and the number of output pins in each block is not so extensive.
DRDIAG is thought to be used for 2 basically different purposes:
1. To enable observation of the drive link physical quality, by showing the

contents of various cumulative error counters, the seriousness of worst
occurred disturbance and the type of last occurred malfunction
2. To enable clearing i.e. restart of all error counters (typically this is desired
after the old contents of the counters is observed and recorded by service
technician) The APC system software never clears the error counters by
itself, except after power down/up sequence.
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Drive Fault DRFLT

Summary
DR_FLT (DRive FauLT) element is used to read fault information DRFLT
(number and time) from an ABB drive and write the appropiate Drive Fault FI DRNR ERR 10
Event to the selected Event Logger buffer. F2 LOGNR
1 ACT
Call DRFLT Figure 1. PC Element

DRFLT
Connections Table 1
F1 DRNR II The drive number from which the faults are 1 to 4

received.
F2 LOGNR II The number of the Event logger buffer to be used. 1 to 8
1 ACT IB Activate the upload of drive fault buffer
10 ERR OB ERRor
Function
When the ACT input of the DRFLT element is set to 1 the DRFLT element sends the "fault upload "
requests to the selected ( by DRNR parameter) drive. In return the drive sends the fault messages one
by one until its fault logger is empty. For each received fault type the DRFLT writes a new Drive Fault
event into a selected Event Logger buffer.
The recorded errorcode is a combination of the drive node number (the high byte) and the uploaded
fault code (the lower byte).
Date and time are included in the fault message from the drive and recorded unchanged. (The drive
clocks are synchronized to the APC clock by the broadcasting block DRTIME running as a
background task).
The combined errorcode is converted into English text by DRFLT element.
The ACT signal can be used to selectively activate or disactivate the operation of the DRFLT based on
the existence of the active alarms or faults. Those states are indicated by specific bits of drive Status
word that is received in the basic message from each drive.
The stored in the Event Logger drive faults can be read by Drive tool and/or other special PC
elements.
The simple panel display may use eg the following presentation form:
DR2 OVER CURRENT 123
1992 10 06 11:25:31 ,0571
Related documents
APC FB descriptions of EVT00, EVT01, EVENT, ERROR and PANCON.
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Drive Parameter Download DRPAR

Summary
The DRPAR (DRive PARameter down load) element is used to DRPAR
down load the parameter values to ABB drives. The destinations of F1 DRNR ERR 10
the transmitted data are selected by the drive number and 1 RESET
parameter indices. The definition of those parameters is given in 2 DWL RDY 11
the applicable drive software description.
21 IND1 EC1 41
The drive signals are handled by another type of PC element: IND*C1 EC*C1
20 + C1 40 + C1
the DRTRA function block. I1
31
30 + C1 I*C1 ERRC 99
Call DRPAR (C1) Table 1 Figure 1. PC Element DRPAR
C1 Number of transmitted integers 1 to 5
Connections Table 2
F1 DRNR II Node number of drive controller on the Drive Link 1 to 4

1 RESET IB Reset for the error outputs and the link init "0->1" = True
2 DWL IB Read parameter indices and send transmission "0->1" = True
request to drive
11 RDY OB The last parameter Download is OK.
12 ERR OB Error detected
21 IND1 II Drive parameter index for the first transmitted
value
20+C1 IND*C1 II Drive parameter index for the last (C1)
transmitted value
31 I1 II First (signal) value to transmit
30+C1 I*C1 II Last (C1) (signal) value to transmit
41 EC1 OI Error type for input I1 see :Table 4
40+C1 EC*C1 OI Error type for input IC1 see :Table 4
99 ERRC OI ERRor CODE for the element see :Table 3
Drive Link
The APC controller communicates with the drive controllers, by polling them one by one at 2 ms
intervals. Within one polling session the request and response frames are exchanged.
Drive Link protocol supports two groups of the messages:
The Cyclic communication group and the Message based communication group. In a cyclic
communication the messages are not acknowledged and the previously received values are used until
the new ones are received correctly. In message based communication every message is checked for
errors and re transmitted if necessary. The parameter downloading belongs to this group.
Before any of the Drive Link function blocks can be used the Drive Link has to be initialised with the
DB element "DRL00". This DB element activates the drive nodes and for each such node defines the
data area called "Drive Buffer". The Drive Buffer contains the records that are used by Drive Link as
a transmit and receive buffers for cyclic and parameter messages. The number of available buffers is
specified by the "NODRBUFx" parameter of the DRL00 DB element. The cyclic messages occupy the
buffer space permanently. The parameter messages are removed from the buffer once they have been
successfully transmitted .
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Function
The DRPAR element is used by an application program to modify the values of the drive controller
parameters. The drive node number is defined with the function parameter "DRNR".
The indices "IND1".."IND*C2" define the drive parameter numbers for which the data from inputs
"I" to "I*C2" are sent.
During the normal operation when a "0->1" transition is applied to the "DWL" input, the DRPAR
element reads parameter indices and input values and sends a new message during the first execution
cycle. The "RDY" output is set to "0" and returns to "1" state when the parameter download is
completed successfully.
It is also possible that at the given moment there is no free space in the Drive Buffer. If within the
next second the element fails to pass the message into the buffer the element aborts the attempts and
indicates the appropriate error message.
Initialisation of the communication link.

At start up or after the link has recovered from a "failure to operate" state a new parameter download
message is sent if the "DWL" input is set to "1".
Error Handling
The "ERR" indication output is set whenever the Drive link or the drive controller responds
incorrectly.
The "ERRC" displays the appropriate error code.
The "ECx" outputs indicate applicable error codes for the individual parameter inputs.
The new parameter download operation can be initiated without a prior reset of the existing error
condition. The "ERR" and "ERRC" indications are cleared with the "RESET" input set to 1.
It is then possible for both "RDY" and "ERR" outputs to indicate status "1" at the same time.
The "ECx" individual error codes outputs are cleared with a new download operation.
Function Block Error Codes (ERRC) Table 3
24x02 Someone of the sent values rejected by the drive

2x03 Drive link Time-out
2x10 No response from drive node
2x12 Not enough tra/rec buffers available
2x13 Wrong contents in drive response
2x19 DB base element not defined.
2x21 Previous dialog operations still active
Note: x = node number 1 to 4
Parameter Error Codes (Ecx) Table 4
8 Length of the transmitted frame is false

11 No parameter with this index
12 No such parameter group
13 The value is to small
14 The value is to large
15 The value was not accepted
32 Number of parameters has a bad value
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In most of the typical drive control applications the Drive link communication needs can be handled
with ease. In some cases, however, when it is necessary to optimise the use of APC resources the
system limitations can be considered.
The first limitation is set by the Drive Buffer storage capacity. The reservation of the buffer space by
different Drive link function blocks is based on "first come first served" principle. This should be kept
in mind when planning for very extensive use of both the cyclic and the (cyclically initiated)
parameter messages.
The second limitation comes from the implemented communication protocol and the link speed. The
message based communication has usually lower priority then a cyclic one but for one out of every
five communication sessions (polls) it is given the higher priority.
In order to secure the Drive Link efficient support of various data transmission functions
between APC and DDCs the following rule of thumb should be used when configuring the
elements for each Drive link node:
K1 K2 Kn 0.4
+ +... + ≤
Texc .1 Texc . 2 Texc . n # DDC
where: Texc.n is the N-th execution cycle time expressed in milliseconds,
Kn is the total number of DRxxx (see note below) elements and those of DRPAR
and DRUPL elements that perform continuous cyclic parameter down- or
upload, executed at the same n -th cycle time,
#DDC is the number of DDCs on the same Drive Link.
Note: the formula should be checked separately for DRxxx = DRTRA and DRREC
Related documents
Description of DRTRA, DRREC and DRUPL PC elements.
Description of DRL00 DB element.
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Drive Link Receive DRREC

Summary
The DRREC (DRive RECeive) element is used to receive the DRREC (C1)
signal and control word values from an ABB drive controller. F1 DRNR ERR 10
The definition of those signals is given in the applicable drive F2 SCAN RDY 11
software description. 1 RESET
2 CHG
The DRREC element uses only the cyclic type of messages
supported by the Drive Link protocol. 21 IND1 O1 31
The source for the received data is selected via the the element 20 + C2 INC2 O*C2 30 + C2
input parameters specifying the drive number and signal indices. ERRC 99
The upload of drive parameters is handled by another type of PC
Figure 1. PC Element DRREC
element: the DRUPL function block.
Call DRREC (C1,C2) Table 1
Parameter Description Permissible Values
C1 Selection of transmission mode 0 = basic cyclic message

1 = normal cyclic message
C2 Number of transmitted integers 3 if C1 = 0
1 to 8 if C1 =1
Connections Table 2
F1 DRNR II The selected drive controller node no significance if 1 to 4

number C1 = 2
F2 SCAN II Updating interval in the drive Note: insignificant [ms]
controller when C1=0
1 RESET IB Reset the element function 0->1
2 CHG IB Download data set description to drive 0->1
10 ERR OB Error in the FB or Drive link operation
11 RDY OB Link ReaDY. New valid data received
21 IND1 II Drive signal index for the first
received value
20+C2 IND*C2 II Drive signal index for the last (C2)
received value
31 O1 II First received value
30+C2 O*C2 II Last (C2) received value
99 EERC O1 ERRor CODE
see "Error codes"
Drive Link
Drive Link protocol supports two groups of the messages: The Cyclic communication group and the
Message based communication group. In cyclic communication the messages are not acknowledged
and the previously received values are used until the new ones are received correctly. In message
based communication every message is checked for errors and re transmitted if necessary.
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successfully transmitted .
Function
The DRREC element allows an application program to receive the drive controller signal values using
the cyclic transmission. The node number of the source drive is defined with the function parameter
"DRNR". The indices "IND1".."IND*C2" define the signals numbers in the drive of which values are
sent to the "O1".."O*C2" outputs.
With the function parameter "C1" the DRREC element defines one of the two possible messages:
• Basic
• Cyclic
The Basic message is received from a drive during every communication session. The basic message
can contain only three signal values and typically is used for the most critical control signals. Only
one basic message per drive can be configured with a DRREC element.
The Cyclic message is received from a drive controller at intervals specified by the "SCAN"
parameter of the DRREC element. A number of the additional signals values and status words can be
sent this way but unjustified, from the process control needs point of view, short execution intervals
should be avoided since the communication capacity is limited.
The receipt of the new valid signal values is acknowledged by a state 1 on the "RDY" output for one
execution cycle of the element. If no new values have been received since the last execution the output
"RDY" is set to 0.

The dataset description is sent to the drive as:
• one message at start up, or
• one message after the link has recovered from a failure (Time-out) and the drive reports the loss
of the valid dataset description ( "no dataset descriptions available" error message).
The cyclic transfer of the signal values starts only after the drive has acknowledged the possession of
the valid data set description. Otherwise the Error state is entered and the "ERRC" output indicates
applicable error code .
Download of new dataset description

During a normal operation a download of new dataset description is made when "CHG" input signal
is set to 1 and at least one of the indices have been changed. The "READY" output is forced to 0 until
the new descriptions are successfully transmitted and new values received.
Error handling
When the link or the drive responds incorrectly the " ERR" output is set to 1 and the " ERRC" output
indicates the applicable error code.
The "ERR" is set to 0 with the first successful response. The "ERRC" output retains the code of the
last occurred error.
If there is a fault in a dataset description the "RESET" have to be pulled high before a new message
with dataset description is sent. In that case the "RESET" function also clears the "ERRC" output.
During the normal operation the "RESET" function is internally blocked.
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3AFY61281240

2x20 Incorrect number of signals:
If call parameter C1 is "0" then only 3 signals are allowed.
2x23 Temporary link disturbance
24x08 Incorrect length of the received frame
24x11 No signal with this index
24x12 No such signal group
24x16 One of the signals is write protected
24x20 Illegal dataset number
24x21 Too many signals in the dataset
24x22 No space available for dataset definition
24x23 Illegal SCAN value (= rejected by the drive)
24x24 Cyclic overload (rejected by the drive)
Note: x = node number 1..4
parameter messages.
DRREC and other elements for each Drive link node:
K1 K2 Kn 0.4
+ +... + ≤
Kn is the total number of DRREC elements and those of DRPAR and DRUPLelements that
perform continuous cyclic parameter down- or upload,executed at the same N -th cycle time,
Related documents
Descripton of DRTRA, DRPAR and DRUPL PC elements.
Descripton of DRL00 DB element.
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Drive Link Transmit DRTRA

Summary
The DRTRA (DRive TRAnsmit) element is used to send to an ABB DRTRA (C1)
drive controller the set of reference and control values for the selected F1 DRNR ERR 10
drive signals and command words. The definition of those signals is 1 RESET RDY 11
given in the applicable drive software description. 2 CHG
The DRTRA element can create different types of cyclic messages
21 IND1 ERRC 99
supported by the Drive Link protocol. 20 + C2 IND*C2
The destinations of the transmitted data are selected by drive signal 31 IN1
indices. 30 + C2 IN*C2
The drive parameters are handled by another type of PC element :
the DRPAR function block.
DRTRA
Call DRTRA (C1,C2) Table 1
C1 Selection of transmission mode0 = basic cyclic message

1 = normal cyclic message
2 = broadcast message
C2 Number of transmitted integers 3 if C1 = 0
1 to 8 if C1 = 1
1 to 5 if C1 = 2
Connections Table 2
F1 DRNR II The selected drive controller node number 1 to 4

no significance if
C1 = 2
1 RESET IB Element function reset 0->1
2 CHG IB Downloads data set description to drive 0->1
10 ERR OB Error in the FB or Drive link operation
11 RDY OB Link ReaDY. Previous data values have been
successfully transmitted.
21 IND1 II Drive signal index for the first transmitted signal
value
20+C2 IND*C2 II Drive signal index for the last (C2) transmitted
signal value
31 IN1 II First signal value to transmit
30+C2 IN*C2 II Last (C2) signal value to transmit
99 ERRC OI ERRor CODE see "Error codes"
Drive Link
Drive Link protocol supports two groups of the messages: the Cyclic communication group and the
Message based communication group. In a cyclic communication the messages are not
acknowledged and the previously received values are used until the new ones are received correctly. In
message based communication every message is checked for errors and re transmitted if necessary.
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successfully transmitte .
Function
The DRTRA element is used by an application program for cyclic transmission of data to the drive
controller. The drive node number is defined with the function parameter "DRNR". The indices
"IND1".."IND*C2" define the signals numbers in the drive for which the data from inputs
"I1".."I*C2" are sent.
With the function parameter "C1" the DRTRA element defines one of the three possible messages:
• Basic
• Cyclic
• Broadcast
The Basic message is transmitted to a drive during every communication session. The basic message
can contain only three signals and typically is used for the most critical control signals. Only one
basic message per drive can be configured by a DRTRA element.
The Cyclic message is transmitted at the execution interval of the DRTRA element. Most of the
additional references and control signals can be sent this way. Unjustified, from the process control
needs point of view, short execution intervals should be avoided since the communication capacity is
limited.
The Broadcast message is transmitted to all drives at the same time and has the highest priority. It is
sent during the first communication cycle after the execution of the relevant DRTRA element. There
can be only one broadcast message configured in the APC.
The successfull transmission of the input values from the previous execution cycle of the element is
acknowledged with the state 1 on the "RDY" output pin.

The dataset description is sent to the drive:
• in one message at start up, or
• in one message after the link has recovered from a failure (Time-out) and the drive reports the
loss of the valid dataset description ( "no dataset descriptions available" error message).
The cyclic transfer of the signal values starts only after the drive has acknowledged the possession of
the valid data set description. Otherwise the Error state is entered with the "ERRC" output indicating
applicable error code .
Download of new dataset description

During a normal operation a download of a new dataset description is made when "CHG" input signal
is set to 1 and at least one of the indices have been changed. The "READY" output is set to 0 until
the new description and data are successfully transmitted.
Error handling
If, during the normal operation, the drive fails to respond within one execution the "READY" output
is sets to 0.
When the link or the drive responds incorrectly the " ERR" output is set to 1 and the " ERRC" output
indicates the applicable error code. The "ERR" is set to 0 with the first successful response. The
"ERRC" output retains the code of the last occurred error.
If there is a fault in a dataset description the "RESET" have to be pulled high before a new message
with dataset description is sent. In that case the "RESET" function also clears the "ERRC" output.
During the normal operation the "RESET" function is internally blocked.
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Error Codes Table 3

2x20 Incorrect number of signals:
If call parameter C1 is "0" then only 3 signals are allowed.
2x22 Previous data not yet sent
2x23 Temporary link disturbance
24x08 Incorrect length of the received frame
24x11 No signal with this index
24x12 No such signal group
24x16 One of the signals is write protected
24x20 Illegal dataset number
24x21 Too many signals in the dataset
24x22 No space available for dataset definition
Note: x = node number 1..4
different Drive link function blocks is based on "first come first serve" principle. This should be kept
parameter messages.
DRTRA and other elements for each Drive link node:
K1 K2 Kn 0.4
+ +... + ≤
Kn is the total number of DRTRA elements and those of DRPAR and DRUPL elements that
perform continuous cyclic parameter down- or upload, executed at the same N -th cycle time,
Related documents
Descripton of DRREC, DRREC and DRUPL PC elements.
Descripton of DRL00 DB element.
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Drive Parameter Upload DRUPL

Summary
The DRUPL (DRive Parameter UPLoad) element is used to DRUPL
upload parameters from ABB drives. The source of the received F1 DRNR ERR 10
data is defined by the drive number and parameter indices. The 1 RESET RDY 11
definition of those parameters is given in the applicable drive 2 UPL
software description. The download of the drive parameters is 21 31

IND1 O1
handled by another type of PC element: the DRPAR function 0 + C1 IND*C1 O*C1 30 + C1
block. EC*C1 40 + C1
ERRC 99
Figure 1. PC Element DRUPL

Call DRUPL (C1) Table 1
C1 Number of received data 1 to 5
Connections Table 2
F1 DRNR II Node number of drive controller on the Drive Link 1 to 4

1 RESET IB Reset for the error outputs and the link init "0->1" = True
2 UPL IB Read parameter indices and values,Send "0->1" = True
transmission request to drive
10 ERR OB Error detected
11 RDY OB The last parameter upload is OK. Data valid
21 IND1 II Drive parameter index for the first received value
20+C1 IND*C1 II Drive parameter index for the last (C1) received
value
31 O1 II Received value of the first parameter
30+C1 O*C1 II Received value of the last (C1) parameter
41 EC1 OI Error type for output O1 see :Table 4
40+C1 EC*C1 OI Error type for output O*C1 see :Table 4
99 ERRC OI ERRor CODE for the element see :Table 3
Drive Link
Drive Link protocol supports two groups of the messages: the Cyclic communication group and the
Message based communication group. In a cyclic communication the messages are not
acknowledged and the previously received values are used until the new ones are received correctly. In
message based communication every message is checked for errors and re transmitted if necessary.
The parameter downloading belongs to this group.
successfully transmitted.
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3AFY61281240
Function
The DRUPL element is used by an application program to read the values of the drive controller
parameters. The drive node number is defined with the function parameter "DRNR" and the
parameter indices with signal inputs "IND1" to "IND*C2" .
During the normal operation when a "0->1" transition is applied to the "UPL" input the DRUPL
element reads parameter indices and sends a new request message during the first execution cycle.
The "RDY" output is set to "0" and returns to "1" state when the parameter upload is successfully
completed. The valid parameter values are moved to the "O1" to "O*C2" outputs.
It is also possible that at the given moment there is no free space in the Drive Buffer. If within the
next second the element fails to pass the message into the buffer the element aborts the attempts and
indicates the appropriate error message.

At start up or after the link has recovered from a "failure to operate" state a new parameter download
message is sent if the "UPL" input is set to "1".
Error Handling
The "ERR" indication output is set whenever the Drive link or the drive controller responds
incorrectly.
The "ERRC" displays the appropriate error code.
The "ECx" outputs indicate applicable error codes for the individual parameter outputs.
The new parameter upload operation can be initiated without a prior reset of the existing error
condition. The "ERR" and "ERRC" indications are cleared with the "RESET" input set to "1".
It is then possible for both "RDY" and "ERR" outputs to indicate status "1" at the same time.
The "ECx" individual error code outputs are cleared with a new download operation.
Function Block Error Codes (ERRC) Table 3
24x02 Someone of the sent values rejected by the drive

2x21 Previous dialog operations still active
Note: x = node number 1 to 4
Parameter Error Codes (Ecx) Table 4
8 length of the transmitted frame is false

11 no parameter with this index
12 no such parameter group
32 number of parameters has a bad value
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Application Guidelines
parameter messages.
In order to secure the Drive Link efficient support of various data transmission functions between
APC and DDCs the following rule of thumb should be used when configuring the elements for each
Drive link node:
K1 K2 Kn 0.4
+ +... + ≤
Kn is the total number of DRxxx (see note below) elements and those of DRPAR and DRUPL
elements that perform continuous cyclic parameter down- or upload, executed at the same
n -th cycle time,
Note: the formula should be checked separately for DRxxx = DRTRA and DRREC
Related documents
Description of DRTRA, DRREC and DRPAR PC elements.
Description of DRL00 DB element.
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Error Detection ERROR

Summary
The ERROR function block is used to write the Error events into the Event ERROR
Logger buffer. The Error events are created by the ERROR element that FI LOGNR ERR 10
works in concert with the PC element that generates the ERRC (Error Code) 1 I
output signal.
ERROR
Call ERROR
Connections Table 1

1 I II Dynamic Input for the error code .
10 ERR OB ERRor output indication of missing
EVTOx DB element.
Function
All the I/O and communicaton PC elements generate the relevant to their operation error signals and
codes. The error code has the structure 100*group + number. The group indicates the origin of the
fault.
The 2-digit number is a group specific code.
In order to record those errors into the Event Logger the ERRC output of the given PC element has to
be connected to the input "I" of the dedicated ERROR element.
The group code is automatically converted to a descriptive text in English by the ERROR block.
The ERROR element detects the ERRC signal change to a non zero value and writes the relevant
error number, name and time into the Event Logger record. If no text is defined for the group in the
text list then the text ERROR 12345 is recorded.
The number of the Event Logger buffer to which the Error events are written is defined with function
parameter "LOGNR". The Error event information (record) can be read by other special PC elements
or a Drive Tool.
The ERRC terminal of an I/O or COM block can generate a sequence of errorcodes. Each new error
code is separately recorded. The reappearrance of the specific errorcode in the same sequence is
ignored. Errorcode 0 at ERRC clears the errorcode list and enables a new sequence of ERROR
records.
The Error event information stored in the Event Logger can be read and then presented by the simple
panel display in a following form:
EXTIO BUSFLT 5101
1992 10 06 11:25:31 ,0571
Related documents
A list of ERROR group texts:
APC FB descriptions of EVT00, EVT01, EVLOG, DRFLT, EVENT and PANCON.
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Event Detection EVENT

Summary
EVENT element is used to detect boolean events and to write the event EVENT
name and event time into the selected event logger buffer. FI LOGNR ERR 10
1 I
2 TEXT
Figure1. PC
Connections Table 1 Element EVENT

1 I IB Control input for event recording.
2 TEXT IA20 Event description - text string max 20 char
10 ERR OB ERRor output: indication of missing
EVT0x DB element
Function
The " 0->1" input (I) signal transition signifies Event occurence.
The " 1->0 " input (I) signal transition signifies Event disappearence.
Event occurence causes the EVENT FB to read the current date and time and write this information
along with the descriptive text string (from TEXT input) into a new record of the Event Logger
buffer. Certain status flags are also set in the given record internal structure for the logger buffer
maintenance purpose.
Event disappearence causes the EVENT FB to mark the Event staus as "disappeared" in the related
event record of the logger.
Event information stored in the Event Logger records can be read by a Drive Tool and /or
Panel equipments. The simple panel display may use eg the following presentation form:
CONTACTOR FAILURE
1992 10 06 11:25:31,0571
Related documents
APC FB descriptions of: EVT00, EVT01, EVLOG, DRFLT, ERROR and PANCON
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Event Logger EVLOG

Summary
EVLOG elements are used to manage the Event Logger buffers EVLOG
created in the APC’s system RW memory by the DB elements EVT00 F1 LOGNR ERR 10
and EVT01. 2 > CLEAR ALARM 11
Up to 8 such buffers ( numbered respectively from 1 to 8) can be 3 ENABLE ACT 12
declared. 4 OWR OWRACT 13
Each Event Logger buffer consists of the control header and the area FULL 14
FIRST 15
holding event records.
LAST 16
The EVLOG inputs are used to write into the event buffer header and
to acknowledge the selected records. TEXT 31
21 ACK
EVLOG output terminals are used to access the content of the buffer DATE 32
22 RECNR
header and selected records. TIME 33
CODE 34
The EVENT, ERROR and DRFLT function blocks are used to source ERRC 99
different classes of events that can be writen into Event Logger records.
The Event Logger buffer can be accessed by Drive Tool services and
EVLOG
special Panel function blocks over the control header.
Call EVLOG
Connections Table 1
F1 LOGNR II Logger number 1 to 8

2 CLEAR IB Clear buffer event records 0->1 =True
3 ENABLE IB Enable recording of new events 1=True
4 OWR IB Permission to overwrite old records 1=True
10 ERR OB Logger not operative 1=True
11 ALARM OB Uncknowledged event in buffer 1=True
12 ACT OB Logger in RUN state
13 OWRACT OB Logger in "old record overwrite" mode
14 FULL OB Record buffer is full
15 FIRST OI Record number of oldest event record
16 LAST OI Record number of newest event record
21 ACK OB If 1 record RECNO is acknowledged
22 RECNR II Record number moved to out terminals
31 TEXT OA20 Text for RECNO
32 DATE OIL Date for
33 TIME OIL Time for RECNO
34 CODE
99 ERRC Error code
Error Codes Table 2
23321 Missing DB Element for the Event Logger buffer

23322 Multiple EVLOG elements address the same Event Logger buffer.
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Event Logger Structure

Each Event Logger Buffer consists of the Control Header and the event storage area. The event
storage area is divided into Event Records. Each record is assigned a unique order number. The
record can be either occupied or empty. The structure and the length of the Control Header and Event
Record are fixed.
The Event Record fields hold the information about the event’s: type, status, errorcode, date, time
and descriptive message (20 character long).
The Control Header fields hold the information about the number and size of the records, Logger
status, first and last unacknowledged record number and also the special command word (CMD).
The individual bits of this command word have the same function as the EVLOG inputs: CLEAR,
ENABLE and OWR. It allows the selected Logger users like Drive Tool and Panel link to control
the Event Logger by accessing and modifying the status of those bits.
Event Logger operation

The EVLOG performs the variety of tasks associated with the houskeeping of the Event Logger
buffer.
In particular it :
• initializes the buffer after the cold start,
• handles the access requests to the Event Logger from the event sourcing FBs like
EVENT, ERROR and DRFLT,
• handles the access requests to the Event Logger from it users like Drive Tools
and Panel lin k,
• executes the commands from the element input terminals and the command word in the
• buffer header,
• updates output terminals
• removes acknowledged records, creates the new ones and updates of the header data,
EVLOG always write events into a consecutive record locations and in a cyclic manner. It means that
after reaching the last record number in the buffer it moves back to number one .
EVLOG uses the FIRST and LAST record number holders to mark the buffer area that contains
unacknowledged events. Once the new event has been written in, its record number becomes the
LAST. Cleared records become empty. If the record indicated as the FIRST is cleared then the
FIRST is assigned the next consecutive occupied record number.
The new event can be written in only if either the next record is empty or the OWR (= Overwrite
permission ) control inputs are set to "1".
When given access to the logger buffer (see operation ...) the DRFLT, ERROR or EVENT Function
Block reserves the next_free_record and writes there its own message. It retain the number of the
record for future reference. In this way, later, a disappeared event /alarm/ is marked by the FB in the
status of the event record.
Records can be acknowledged directly over the EVLOG inputs. Some of the the Logger users can also
acknowledge the records directly in the buffer. The houskeeping tasks of the EVLOG search for those
records and clear them .
Recording functions
The following event types can be recorded in ther Event Logger:
• APC system errors; sourced by INSERR system routine
• Event ; sourced by EVENT function block
• Drive Fault ; sourced by DRFLT function block
• Error ; sourced by ERROR function block
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Use of Event Loggers

Event Logger users are the application program, the DriveTool, and the (operator or door) panels.
There should be only one main user for each logger. The main user of an event logger can control the
operation of the logger. Other users should only read the contents of the logger buffer.
Logger Control means:

• running and stopping logger operation
• clearing of the logger buffer
• overwriting of records
• acknowledgment of records
The user controls the logger over either the EVLOG input terminals or the system SW services that
provide access to the Logger header CMD word and individual records. The application program have
access only to the EVLOG input terminals. The panel control function block PANCON and the Drive
Tool use system SW services.
Time Output
The TIME is read from a system clock and represents the number of the 100 us ticks since midnight.
Date Output
The DATE represents the number of days since the new year 1980.
Related documents
Descriptions of APC function blocks DATALOG, DRFLT, ERROR, EVENT, and PANCON and
database elements EVT00 and EVT01.
State Diagram for EVLOG
RESET INIT
CLEAR 1 CLEAR 1
ENABLE = 0
ENABLE = 1
ENABLE = 1
RUN STOP
ENABLE = 0 OR
FULL & OVERWR
In State INIT
The special routine is executed during the system "Power on" or ...........????
It initializes the buffer declared by an EVT0x DB-element in the following way:
If the memory check is successful and the NOTCLEAR terminal of the EVT-element is set to 1 the
buffer content is preserved. Otherwise the records are cleared and the buffer header initialized.
Output values on the FIRST and LAST pins of the EVLOG element are zeroed.
During the initialisation the Event buffer is not available to other function blocks.
State STOP is entered after initialisation.
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In State STOP
The new records cannot be created. Existing records however can be acknowledged and their contents
read.
The transition to the RUN state takes place when either the EVLOG’s ENABLE input is set to 1, or
the ENABLE bit in the commandbyte CMD of the buffer header is set internally to 1 ( ??? 0->1 ????)
by the .........?????
In State RUN
New records can be created. Existing records can be read, acknowledged and removed.
State RUN is terminated and the state STOP entered when :

either both the EVLOG’s ENABLE input is set to 0 and the ENABLE bit in the commandbyte
CMD of the buffer
header is set internally to 0 by the .........?????,
or the buffer becomes full and the input OVERWR is set to zero.
(The later case can be eliminated eg by interconnecting terminals FULL and OVERWR .)
State RESET
The EVLOG is forced to enter the RESET state either on :
the 0 -> 1 transition on the CLEAR input,
or 0 -> 1 transition of the CLEAR bit of the header command word CMD.
In the RESET state the records are cleared and the buffer initialized.
When the buffer has been cleared either the state STOP or RUN is entered depending on the status of
the ENABLE signals.
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Event Detection EVT

Summary
EVT element is used to detect boolean events and to write the event name EVT
F1 LOGNR ERR 10
and event time into the selected event logger buffer. 1 I O 11
2 TEXT
3 ACK
Call EVT EVT
Connections Table 1
F1 LOGNR II The number of the Event Logger buffer to be used.

1 I IB Control input for event recording.
2 TEXT IA20 Event description - text string.
3 ACK B Acknowledgement for Event.
10 ERR OB ERRor output
11 O OB output of Event control signal.
Function
The "0 → 1" input (I) signal transition signifies Event occurence.
The "1 → input (I) signal transition signifies Event disappearance.
Event occurance causes the EVENT-function block to read the current date and time and write this
information along with the descriptive text string into new record of the event logger buffer. The
descriptive text string is plus (+) sign and first 19 characters from the text in TEXT-input.
Event disappearance causes the event to be written into new record of the event logger buffer like
during the event occurance but minus (-) sign is indicating the event disappearance.
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Queue Register FIFO

Summary
The queue register FIFO (First In First Out) can FIFO
be used store data to be used later and irrespective (C1, C2,C3)
1 > IN FULL 8
of when the data was stored. The different queues OCC
2 > OUT 9
in the element work in parallel, i.e . reading in, EMPTY 10
3 R
reading out, etc. are performed at the same time
in all of the queues. Data may be of the types 11 I1 01 12
integer, real number, Boolean or time. A 21 I2 02 22
maximum of 9 queues, each with a maximum of
64 queue places, can be selected. 10 x C2 + 1 IC2 0C2 10 + C2 + 2
Figure 1. PC Element FIFO
Call FIFO (C1, C2, C3) Table 1

C2 Number of queues 1 to 9
C3 Number of queue places
in each queue 2 to 64
Connections Table 2
1 IN IB Dynamic input for entering of data in the queues. Data is read

from the inputs 11 to IC2.
2 OUT IB Dynamic input for reading data from the queues.
3 R IB Reset. Input which clears the queue register and prevents all
further entry.
8 FULL OB Output which is set when the queue register is full.
9 OCC OI OCCupied. Output which specifies how many queue places are
occupied.
10 EMPTY OB Output which is set when the queue register is empty.
11 I1 IC1 Input 1. Input data to queue no 1.
12 O1 OC1 Output 1. Output data from queue no. 1
21 12 IC1 Input 2. Input data to queue no. 2.
22 O2 OC1 Output 2. Output data from queue no. 2.
.
.
.
10x0C2+1 IC2 IC1 Input C2. Input data to queue no. C2.
10xC2+2 OC2 OC1 Output C2. Output data from queue no. C2.
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Function
Each queue has a data input I. It is used to enter data at the end of the queue. Each queue has a data
output O. Data from place 1 in each queue is continuously available at the outputsO1 to OC2. If both
dynamic inputs (IN and OUT) are set during the same program cycle, data entry is performed first
and then the output is read.
Entry of Data
Data at the I inputs are placed last in the queues when input IN isset. When the queue register is
empty, data is stored at queue place 1, then at queue place 2, etc.
Output of Data
When input OUT goes to 1, data at each occupied place in all queues are moved forward one place.
Data that occupied queue place 2 now occupies queue place 1, and can be read at outputs O1 to OC2.
The value 0 is entered at the previous last occupied place.
Clearing of the Complete Register

When the input R is set, the complete contents the queues are cleared. All further entry is blocked.
Supervision
The number of occupied queue places is indicated continously by the output OCC. When the queue
register is full, the output FULL is set and when the queue register is empty, the output EMPTY, the
output EMPTY is set.
FIFO
1 8
> IN FULL
2 9
> OUT OCC
3 10
R EMPTY
11 I1 O1 12
21 I2 O2 22
Queue 31 I3 O3 32 Queue
inputs outputs
10 x C2 + 1 IC2 OC2 10 x C2 + 2
C3 - 8 7 6 5 4 3 2 1
Queue place
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Filter FILT-1P
Summary
FILT-1P (FILTer-1Pole) is used as a single pole low-pass filter. The FILTI-1P
1 I O 10
output signal can be limited with limit values specified at special O = HL
2 K 11
inputs. The balancing function permits the output signal to track an O = LL
3 T1 12
external reference and permits a bumpless return to the normal 4 ERR 13
BAL
function. All transfers from static states are bumpless. 5 BALREF
6 OHL
7 OLL
Call FILT -1P

Connections Table 1 FILT-1P

3 T1 ITR Time 1. Input for filter time constant.
tracking.
6 OHL IR Output High Limit. Input for upper
limit value.
7 OLL IR Output LowLimit. Input for lower limit K
value.
10 O OR Output. Output signal. t
11 O=HL OB Output= HighLimit. Output which is T1
set to 1 if the output O reaches the Figure 2. Step response
upper limit value.
12 O=LL OB Output= LowLimit. Output which is set to 1 if
the output O reaches the lower limit value.
13 ERR OB ERRor. Output set to 1 if OHL is
less than OLL:
IgIGI
Function IgK
The step response in the time plane for a single low -pass filter is
O(t) = I(t) K (1-e sT1). The transfer function for a single pole low
pass filter is G(s) = K(1/(1+sT1)). This has been implemented in
the FILT-1P element as a recursive algorithm. Igω
1
Gain, FilterTime and Sampling Time T1
Certain constants are precalculated to make the execution time of
G
the element as short as possible. The result is stored internally in
the element. These constants are recalculated if T1 or K are Igω
45••
changed by more than 1/128 of their previous value, or if the
sampling time TS is changed. When recalculating, a test is -90
performed to check if T1 > 2xTS. If not, T1 is set equal to 2xTS. Figure 3. Bode diagram
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Tracking
If BAL is set to 1, the filter immediately goes into tracking and the output O is set to the value of the
input BALREF. If the value at BALREF exceeds the output signal limits, the output is set to the
applicable limit value. Return to dynamic state is bumpless.
Limitation Function
The limitation function limits the output signal to the limit values at the inputs OHL for upper limit
value and OLL for the lower limit value. If the actual value exceeds the upper limit value, the output
O = HL is set to 1. If it falls below the lower limit value, the output O = LL is set to 1.
When the limitation status has been detected, a check is made each time the element is executed to
determine whether K x I(t) exceeds the output signal limitations. If so, the limitation status remains.
If not, the calculation of the output signal is performed by the algorithm in the normal way. Return
from limitation to a dynamic state is bumpless. The element checks that the upper limit value the is
greater that the lower limit value OLL. if not, the output ERR is set to 1. While the error status
persists, the outputs O = HL, O = LL and O retain the values they had in the sample before the error
occurred. After an error the return to a dynamic state is bumpless, in the same way as in the case of
tracking above.
7 OHL
8 OLL
I1
I1 < I2 1 &
I2
I1 1
I1 < I2 ACT
I2 O 10
4 BAL
ACT
5 BALREF
I1 O =HL 11
I1 > I2
I2
I1 O = LI 12
I1 < I2
I2
I1 ERR 13
ACT I1 < I2
I2
X
1 I FILT-1P
2 K
3 TI
t
1
Preset
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Filter FILTI
Summary
FILTer Integer element is used as a single pole low pass filter for integer FILTI
values. 1 I O 10
2 T1
Call FILTI FILTI
Connections Table 1
1 I II Input to channel 1.
2 T1 II Filter time constant. 0 to 32767 [ms]
10 O OI Output. Filtered value.
Function
The step response in the time plane for a single low pass filter is:
O(t) = I(t)(1 − e− t/T 1 )
The transfer function for a single low pass filter is:
G(s) = 1(1 + sT 1)
The filtering algorithm is calculated using the following formula:
I + (T 1 TS) × O n − 1
O =
T1T2 + 1
Where TS is the cycle time of the element in milliseconds and O n − 1 is the output from the previous
execution cycle. If T1 < 1 then the output O is set to the input I. The internal calculation of the
algorithm is done with 32 bit accuracy to avoid offset errors.
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Function Parameter to Integer

Conversion FPI
Summary
FPI is used to convert an integer function parameter to a normal integer value.
FPI
F1 FP O 10
Call FPI FPI
Connections Table 1
F1 FP II Function Parameter to be converted.

10 O OI Output for the converted value.
Function
The converted integer value can be used as a normal integer type of data.
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Function Header FUNCM

Summary
FUNCM (FUNCtion Module) is used for structuring a PC program. FUNCM
Call FUNCM Figure 1. PC

Element
FUNCM
Function
The purpose of FUNCM is to control the arrangement of the documentation. The element cannot
affect the execution. A function module can be used to provide a subdivision of a PC program, a
control module, a slave, or a sequence step in several functionally associated parts. A function module
can itself contain a control module, slave sequense, or a new function module.
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Function Generator FUNG-1V

Summary
FUNG-1V (FUNction Generator-1 Variable) is used for generation of FUNG-1V
1 X Y 10
an optional function of one variable, y = (f(x). The function is ERR
2 BAL 11
described by a number of co-ordinates. Linear interpolation is used BALREFO
3 BALREF 12
for values between these co-ordinates. A maximum of 255 co- 4 XTAB
ordinates can be specified. 5 YTAB
Y
Call FUNG-1V (C1) FUNG-1V

values
C1 Number of co-ordinates which describe the function 2 to 255
Connections Table 1
1 X IR X-value. Input for X-value.

2 BAL IB BALance. Input for activation of balancing.
3 BALREF IR BALance REFerence. Value which the Y-output is to adopt
with balancing.
4 XTAB IGC1R XTABle. Group data for the X-table with C1 values.
5 YTAB IGC1R YTABle. Group data for the Y-table with C1 values.
10 Y OR Y-value. Output for Y-value.
11 ERR OB ERRor. Error signal which is set (to 1) if
X is outside the value of XTAB or if Y,
on balancing, is outside the YTAB values.
12 BALREFO OR BALance REFerence Output. Output for calculated
X-value with balancing.
Function
The function generator FUNG-1V for one variable calculates an output signal Y for a value at the
input X. The calculation is performed in accordance with a piece by piece linear function which is
determined by the vectors XTAB and YTAB. For each X-value in XTAB, there is a corresponding Y-
value in YTAB.
The Y-value at the output is calculated by means of linear interpolation between the two X-values in
XTAB which are nearest the value at the input X. The values in X-tab must be strictly increasing
from low to high serial numbers in the table.
Interpolation
The function generated is illustrated by the following figure. The interpolation is performed as
follows:
y = Yk + (X - X k)(Yk + 1 - Yk)/(Xk + 1 -Xk)
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Balancing
On activation of the balancing input BAL, the value at Y is set to the value at the input BALREF. The
X-value which corresponds to this Y-value is obtained at the output BALREFO. On balancing the X-
value is calculated by interpolation in the same way the Y-value is calculated during normal
operation. To permit the balancing, the values in YTAB must be strictly increasing or decreasing
from low to high serial numbers in the table.
Error Signal
If the input signal X is outside the range defined by XTAB, the ERR output is set to 1. The Y-value is
then set to the highest or lowest value resp. in YTAB. ERR is also set to 1 if BALREF is outside the
YTAB value range when BAL is set to 1. The value at Y is then set to the value at the input BALREF
and BALREFO is set to the highest or lowest value reps. in XTAB.
Y
YC1
Yk + 1
Y
Yk
Y2
Y1
X1 X2 X
Xk X k+1 XC 1
X
Figure 2. Example of function
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Two Integer to Integer Long conversion IIL

Summary
IIL element is used to pack two Integer values to an Integer long value. IIL
1 L O 10
2 H
Figure 1. PC
Call IIL Element IIL
Connections Table 1
1 L II Input for the 16 less significant bits of the Integer long output.
2 H II Input for the 16 most significant bits of the Integer long output.
10 O OIL Integer long Output.
Function
The IIL element do not care about the sign of the Integer Inputs. The element simply writes the L
input to the 16 less significant bits and the H to the 16 most significant bits to the Integer long output
O.
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Integer Long to two Integer conversion ILI

Summary
ILI element is used to unpack an Integer long value to two Integer values. ILI
1 I L 11
H 12
Figure 1. PC
Call ILI
Element ILI
Connections Table 1
1 I ILI Integer long input.

11 L II Output for the 16 less significant bits of the Integer long input.
12 H II Output for the 16 most significant bits of the Integer long input.
Function
The ILI element do not care about the sign of the Integer outputs. The element simply writes to the L
output the 16 less significant bits and to the H output the 16 most significant bits of the Integer long
input I.
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Integrator INT
Summary
INT (INTegrator ) is used to give an integration effect. The output INT
1 I O 10
signal can be limited with limit values specified at special inputs. The O = HL
2 K 11
balancing function permits the output signal to track an external O = LL
3 TI 12
reference and permits a bumpless return to the normal function. 4 ERR 13
RINT
5 BAL
6 BALREF
7 OHL
8 OLL
Call INT t
Connections Table 1 Figure 1. PC Element INT
1 I IR Input. Input signal.

3 TI ITR Time Integration. Input for time constant
for integration.
4 RINT IB Reset INTegrator. Input for clearing
integrator.
5 BAL IB BALance REFerence. Input for reference
value when tracking
6 BALREF IR BALance REFerence. Input for reference
value when tracking.
7 OHL IR Output High Limit. Input for upper limit
value.
8 OLL IR Output Low Limit. Input for lower limit
value.
11 O = HL OB Output = High Limit. Output which is set
to 1 if the output reaches the upper limit
value.
12 O = LL OB Output = Low Limit. Input which is set to
1 if the output reaches the lower limit value.
13 ERR OB ERRor. Output which is set to 1 if OHL is
less than OLL.
IgIGI
t K Igω
T1
T1
Figure 2. Step response G
Igω
-90
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Function
Transfer Function
The INT function can be written in the time plane as
(0) = K/TI (∫ I(τ) d τ)
The main property when controlling is that the output signal retains its value when the input signal
I(t) = 0.
The step response in the time plane is O (t) = k x I (t) x/TI.
The transfer function for an integrators is
G(s) = K(1/sTI).
Gain, Integration Time Constant and Sampling Time

The constant K x TS/TI is precalculated to reduce the execution time of the element to a minimum.
The result is stored internally in the element. This constant is recalculated if TI or K is changed by
more than 1/128 of their previous values if the sampling time TS is changed. When recalculating, a
test is made to see whether TS/TI <1.TS/TI is otherwise set equal to 1.
Clearing of Integrator
The algorithm is cleared when RINT goes to 1.
Tracking
If BAL is set to 1, the regulator immediately goes into following and the output O is set the value of
the input BALRERF. If the value at BALREF exceeds the output signal limits, the output is set to the
applicable limit value. On return to the normal function the value of output O during the last sample
in tracking remains a further sample time, after which integration will be performed for this value.
Limitation Function
The limitation function limits, the output signal to the value at the inputs OHL for upper limit and
OLL for the lower limit. If the actual value exceeds the upper limit, the output O = HL is set to 1 and
if it falls below the lower limit, the output O = LL is set to 1. The element checks that the upper limit
value OHL is greater than the lower limit value OLL. If not, the output ERR is set to 1. While the
error status persists, the output O = HL, O = LL and O retain the values they had in the sample before
the error occurred. After limitation or error status, normal integration is performed from the current
value.
7 OHL
8 OLL
ACT
O 10
4 BAL
ACT
5 BALREF
I1 O =HL 11
I1 > I2
I2
I1 O = LI 12
I1 < I2
I2
I1 ERR 13
I1 < I2
I2
1 I INT
2 K
3 TI t
4 RINT
Reset
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Inverter INV
Summary
INV is used for inverting Boolean variables. INV is used particularly when reading 1
1 5
signals to the data base.
Call INV Figure 1. PC

Element INV
Connections Table 1
1 - IB Input.
5 - OB Output of inverted input value.
Function
The output signal from the INV element is set (to 1) if the input signal to the element is 0, and is reset
(to 0) when the input signal is 1. See truth table below.
Truth table Table 2

1 5
1 0
0 1
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IO Bus Read IOBUSRD

Summary
IOBUSRD element is used to read data from special boards via IOBUSRD
parallel I/O bus or to facilitate certain functions in those APC (C1,C2,C3,C4)
F1 BOARD ERR 10
hardware test programs, which are written with PC-elements.
The element is usually used as part of special type circuits. The F2 SPEC
main function of the element is specified with SPEC pin. The 1 EN
board identifier address is selected with function parameter
BOARD and the internal addresses of different data types inside 11 AIB1 OIB1 51
the board with inputs AIB1 to 10, AI1 to 10, AIL1 to 10, AR1 to 10 + C1 AIBC1 OIBC1 50 + C1
10. The number of different datatype values to read are selected 21 AI1 61
OI1
with call parameters C1, C2, C3 and C4.
20 + C2 AIC2 OIC2 60 + C2
31 AILB1 OIL1 71
30 + C3 AIBC3 OILC3 70 + C3
41 AR1 OR1 81
40 + C4 ARC4 ORC4 80 + C4
Figure 1. PC Element IOBUSRD
Call IOBUSRD
C1 Number of 8 bit (IB) values to read 0 to 10

C2 Number of Integer values to read 0 to 10
C3 Number of Integer long values to read 0 to 10
C4 Number of floating point values to read 0 to 10
Connections Table 1
F1 BOARD II I/O address of the board in parallel IO bus. 1 to 15

F2 SPEC II Function specifier 0 to 6
1 EN IB To ENable the data read from the selected
addresses.
10 ERR OB Indication of failed operation.
11 AIB1 II First address of the 8 bit values to read from the 0 to 255
board
1C1 AIBC1 II C1th address of the 8 bit values read from the 0 to 255
board
21 AI1 II First address of the Integer values read from the 0 to 254
board
2C2 AIC2 II C2th address of the Integer values read from 0 to 254
the board
31 AIL1 II First address of the Integer long values to read 0 to 252
from the board
3C3 AILC3 II C3th address of the Integer long values read 0 to 252
from the board
41 AR1 II First address of the floating point values to read 0 to 252
from the board.
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Table 1 continued
4C4 ARC4 II C4th address of the floating point values read from 0 to 252
the board
51 OIB1 OI Output for the first 8 bit value read from the board
as Integer
5C1 OIBC1 OI Output for the C1th 8 bit value read from the board
as Integer
61 OI1 OI Output for the first Integer value read from the
board
6C2 OIC2 OI Output for the C2th Integer value read from the
board
71 OIL1 OIL Output for the first Integer long value read from the
board
7C3 OILC3 OIL Output for the C3th Integer long value read from the
board
81 OR1 OR Output for the first floating point value read from
the board
8C4 ORC4 OR Output for the C4th floating point value read from
the board
Function Parameters
When SPEC (=F2) = 0

Function parameter BOARD must have the same value as the hardware address switch of the special
I/O board. The element reads the datas to outputs OIB1 to 10, OI1 to 10, OIL1 to 10, OR1 to 10 from
the selected addresses AIB1 to 10, AI1 to 10, AIL1 to 10, AIR1 to 10 and update only if EN input is
set to value 1. ERR output indicates an I/O bus error, which may result from a faulty or missing I/O
board or read from a nonexisting address from the I/O board.
When SPEC (=F2) = 1

This function is intended for reading data bytes directly from the communications memory (“VK”) of
AF100 bus coupler board YPK112. C1 must be = 0. Function parameter BOARD has no significance.
If EN = 0, the block does nothing. The element reads the data bytes to outputs OI1 to 10 from the
selected addresses AI1 to 10. Allowed range of addresses is 0...32767.
Note, that both odd and even addresses are allowed. The function block IOBUSRD multiplies each
address by two before asserting it to address bus of APC board. ERR output indicates an error in the
call parameters or input values. Call parameters C2 and C3 are allowed to be >0, but respective input
pins AIL1 to 10 and AIR1 to 10 have no significance and outputs OIL1 to 10 and OR1 to 10 are never
updated. For your assistance here are some address values for certain VK locations:
2432...2433 = location for master frame

2460...2463 = PKR of ZGA frames
2464...2467 = PKR of Fcode 8 frames
2484...2487 = PKR of event channel 0 frames
2488...2491 = PKR of Event channel 1 frames
2496...2559 = ZGA data area
2560...2623 = Fcode 8 data area
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2880...2943 = Event channel 0 data area
3072...4095 = PKR area of SA frames
4096...8191 = address lookup table of SA frames
8192...12287 = data area of SA frames
When SPEC (=F2) = 2:

This function is intended for reading data bytes directly from the communications ASIC (“BAP”) of
If EN = 0, the block does nothing. The element reads the data bytes to outputs OI1 to 10 from the
selected addresses AI1 to 10. Allowed range of addresses is 0...63. Note, that only even addresses are
allowed and those addresses are the same as specified in BAP data sheet (i.e. the function block
IOBUSRD multiplies each address by two before asserting it to address bus of APC board). ERR
output indicates an error in the call parameters or input values. Call parameters C2 and C3 are
allowed to be >0, but respective input pins AIL1 to 10 and AIR1 to 10 have no significance and
outputs OIL1 to 10 and OR1 to 10 are never updated.
For your assistance here are the address values for BAP registers:
0 = SRL
2 = SRH
4 = ERL
6 = ERH
8 = SKRL
10 = SKRH
12 = ISR
14 = IMR

This function is intended for reading data bytes directly from the communication ports of AF100 bus
coupler board YPK112. C1 and C2 must be = 4 and C3 must be >= desired read lenght, (which is
specified by input pin AIB2). Function parameter BOARD has no significance. If EN = 0, the block
does nothing. The element makes some verification checks concerning the status of the
communication port, stores results of these checks to OIB1...OIB4, and then reads the data bytes from
PKR area to output pins OI1...OI4 and data bytes to outputs OIL1 to OILx from the specified
communication port. Port number is given at pin AIB1. Allowed range for port ID is either -15...-7 or
0...255.
Negative values indicate variousservice communication ports:
-7 ZGA port
-8 Fcode 8 port
-9 Fcode 9 port
-10 Fcode 10 port
-11 Fcode 11 port
-12 Fcode 12 port
-13 Event channel 0 port
-15 Fcode 15 port
and nonnegative values indicate normal SA ports.
Note, that normally APC uses only such port numbers, which are divisible by 4, but here all ports are
processed according original BAP specifications. If you know the index (in range 1...63) for certain
CDP, you must multiply it by 4 to see respective data with IOBUSRD element. AIB2 specifies how
long CDP should be configured at he port (and how many words are read to output pins OIL1...OILx.
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Note, that the lenght is specified as words, not as bytes. AIB3 specifies the assumed global signal
address for the port (in range 0...4095) and AIB4 specifies how to handle TACK and SZ bits of PKR:
AIB4 = 0 OR 10 => read data from page 0
AIB4 = 1 or 11 => read data from page 1
AIB4 = 2 or 12 => read data from page pointed by SZ bit
AIB4 = 10 => clear TACK bit in PKR area
The checks made for the port are:

1. Has there been a bus transfer (=TACK bit = 1?), sets OIB1 accordingly.
2. Is the Fcode in PKR set according AIB2? Sets OIB2 = 1, if so.
3. Is the lookup table of VK set according AIB3 and AIB1? Sets OIB3 = 1if so.
4. Sets OIB4 according the SZ bit of PKR.
PKR values are copied to OI1...OI3:

OI1 = contains Fcode, PAQ, PAS and TMP
OI2 = contains interrupt enable bits
OI3 = contains SZ, BNIB, TERR and TOB bits
OI4 = contains TACK and T0...T6 bits
Values from data area of the port are copied from one page to outputs OIL1...OILx are copied word by
word (one word to one output). Each word is assumed to exit in VK less significant byte first (= in
Intel order). If you want to see both pages, you must insert respective IOBUSRD twice: one with
AIB4 = 0 and once with AIB = 1 (or 11).
ERR output indicates an error in the call parameters or input values. Call parameters C3 is allowed to
be > AIB1 and C4 > 0, but respective output pins OIL (x+1) to OIC3 and OR1 to ORC4 are never
updated.

This function is intented for generating timestamps at output pin OI1 and for generating wait pauses,
whose duration is specified through input pin AI1. Call parameter C1 must be = 0 and C1 must be =
1. Time values are shown with 100 microrec resolution as 16 bit freerunning counter values. Waiting
delays should be short or at least in low priority task, because the IOBUSRD does not release control
to lower priority task during the wait times. (However higher priority task may execute during a wait
time). Time stamp is generated before the possible waiting starts. If AI1 = 0, no waiting is done, just a
time stamp is stored on OI1.
When SPEC (=F2) = 6

This function is intended for detecting and counting BAP interrupts associated with specified
IMR/ISR bit. Call parameter C1 must be (at least) = 2.
AIB1 specifies the bit # according IMR/ISR structure (range 0...7), and AIB2 = 1 specifies that this
special interrupt service routine shall be used instead of the normal one. Respectively AIB2 = 0
specifies, that the normal interrupt service routine shall be used again.
If AIB2 = 1, OIB1 will shows how many times the specified interrupt has occured since previous
execution of this same block, and OIB2 is a cumulative number of these interrupts. And if AIB2 = 0,
OIB1 will be = 1 and OIB2 = 0.
Note, that this element (=IOBUSRD (SPEC = 6)) does not modify the respective mask bit in IMR. So
if you like to see interrupts, which normally are masked, you must insert a separate
IOBUSWR(SPEC=2), which clears the mask bit from IMR.
Remember to restore normal interrupt connection after using this function by asserting AIB2 =
0 (especially if you had AIB1 = 1,2 or 3).
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IO Bus Write IOBUSWR

Summary
IOBUSWR element is used to write data to special boards via IOBUSWR
parallel I/O bus or to facilitate certain functions in those APC (C1,C2,C3,C4)
F1 BOARD ERR 10
hardware test programs, which are written with PC-elements. The
element is usually used as part of special type circuits. The main F2 SPEC
function of the element is specified with SPEC pin. The board 1 EN
identifier address is selected with function parameter BOARD and
the internal addresses of different data types inside the board with 11 AIB1
inputs AIB1 to 10, AI1 to 10, AIL1 to 10, AR1 to 10, and respective 10 + C1 AIBC1
data with inputs IIB1 to 10, II1 to 10, IIL1 to 10 and IR1 to 10. The 21 AI1
number of different datatype values to write are selected with call
20 + C2 AIC2
parameters C1, C2, C3 and C4.
31 AILB1
30 + C3 AIBC3
41 AR1
40 + C4 ARC4
51 IIB1
50 + C1 IIBC1
61 II1
60 + C2 IIC2
71 IIL1
70 + C3 IILC3
81 IR1
80 + C4 IRC4
IOBUSWR
Call IOBUSWR
C1 Number of 8 bit (IB) values to write 0 to 10

C2 Number of Integer values to write 0 to 10
C3 Number of Integer long values to write 0 to 10
C4 Number of floating point values to write 0 to 10
Connections Table 1
F1 BOARD II I/O address of the board in parallel I/O bus 1 to 15

F2 SPEC II Function specifier 0
1 EN IB To ENable the data write to the selected addresses.
10 ERR OI I/O bus ERR or indication.
11 AIB1 II First address of the 8 bit values to write from the board 0 to 255
1C1 AIBC1 II C1th address of the 8 bit values write from the board 0 to 255
21 AI1 II First address of the Integer values write from the board 0 to 254
2C2 AIC2 II C2th address of the Integer values write from the board 0 to 254
31 AILB1 II First address of the Integer long values to write from the 0 to 252
board
Table 2 continued
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3C3 AIBC3 II C3th address of the Integer long values write from the 0 to 252
board
41 AR1 II First address of the floating point values to write from 0 to 252
the board
4C4 ARC4 II C4th address of the floating point values write from the 0 to 252
board
51 IIB1 II Integer input for the first 8 bit value to write into to
board.
5C1 IIBC1 II Integer input for the C1th 8 bit value to write into to
board.
61 II1 II Input for the first Integer value to write into to board.
6C2 IIC2 II Input for the C2th Integer value to write into the board.
71 IIL1 IIL Input for the first Integer long value to write into the
board.
7C3 IILC3 IIL Input for the C3th Integer long value to write into the
board.
81 IR1 IR Input for the first floating point value to write into the
board.
8C4 IRC4 IR Input for the C4th floating point value to write into the
board.
Function Parameters
When SPEC (=2F) = 0:

Function parameter BOARD must have the same value as the hardware address switch of the special
I/O board. The element writes the selected datas from the inputs IIB1 to 10, II1 to 10, IIL1 to 10 and
IR1 to 10 to the selected addresses AIB1 to 10, AI1 to 10, AIIL1 to 10 and AIR1 to 10 only if EN
inputs is set to value 1. ERR output indicates an I/O bus error, which may result from a faulty or
missing I/O board or write to a nonexisting address within the I/O board.

This function is intended for writing data bytes directly to the communications memory (“VK”) of
If EN = 0, the block does nothing. The element writes the data bytes from inputs II1 to 10 to the
selected addresses AI1 to 10 of VK. Allowed range of addresses is 0...32767.
Note, that both odd and even addresses are allowed. The function block IOBUSWR multiplies each
address by two before asserting it to address bus of APC board. ERR output indicates an error in the
call parameters or input values. Call parameters C2 and C3 are allowed to be >0, but respective input
pins AIL1 to 10, IIL1 to 10, AIR1 to 10 and IR1 to 10 have no significance.
For your assistance here are some address values for certain VK locations:
2432...2433 = location for master frame
2460...2463 = PKR of ZGA frames
2496...2559 = ZGA 8 data area
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3072...4095 = PKR area of SA frames
4096...8191 = address lookup table of SA
frames
8192...12287 = data area of SA frames

This function is intended for writing data bytes directly into the communications ASIC (“BAP”) of
If EN = 0, the block does nothing. The element writes the data bytes from inputs II1 to 10 into the
selected addresses AIB1 to 10 of BAP. Allowed range of addresses is 0...63.
Note, that only even addresses are allowed and those addresses are the same as specified in BAP data
sheet (i.e. the function block IOBUSRD multiplies each address by two before asserting it to address
bus of APC board). ERR output indicates an error in the call parameters or input values. Call
parameters C2 and C3 are allowed to be >0, but respective input pins AIL1 to 10, IIL1 to 10, AIR1 to
10 and IR1 to 10 have no significance.
For your assistance here are the address values for BAP register:
0 = SRL
2 = SHR
4 = ERL
6 = ERH
8 = SKRL
10 = SKRH
12 = ISR
14 = IMR

This function is intended for directly configuring a communication port and writing data bytes to the
associated data page(s) into AF100 bus coupler board YPK112. C1 and C2 must be = 4 and C3 must
be > = desired write length, (which is specified by input pin AIB2). Function parameter BOARD has
no significance. If EN = 0, the block does nothing. The element writes the data bytes from input pins
(AI1...AI4) to PKR area and data bytes from inputs IIL1 to IILx into the specified communication
port’s data page. Port number is given at pin AIB1. Allowed range for port ID is either -15...-7 or
0...255.
Negative values indicate various service communication ports:
-7 ZGA
-8 Fcode 8 port
-9 Fcode 9 port
-10 Fcode 10 port
-11 Fcode 11 port
-12 Fcode 12 port
-15 Fcode 15 port
and nonnegative values indicate normal SA ports.
Note, that normally APC uses only such port numbers, which are divisible by 4, but here all ports are
processed according original BAP specifications. If you know the index (in range 1...63) for certain
CDP, you must multiply it by 4 to directly configure or update respective port with IOBUSWR
element. AIB2 specifies how long CDP should be configured at the port (and how many words are
read from input pins IIL1...IILx.
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Note, that the lenght is specified as words, not as bytes. AIB3 specifies the desired global signal
address for the port (in range 0...4095) and AIB4 specifies how to handle TACK and SZ bits of PKR:
AIB4 = 0 or 10 => write data to page 0
AIB4 = 1 or 11 => write data to page 1
AIB4 = 2 or 12 => write data to page pointed by SZ bit
AIB4 = 3 or 13 => write data to the other page pointed by SZ bit, and invert SZ afterwards
AIB >= 10 => clear TACK bit in PKR area
Note, that II1 must contain correct Fcode. IOBUSWR does not generate or modify it according AIB2.
PAQ or PAS bit (not both) should be set too by data from AIB2.
Note also, that IOBUSWR does not trigger any configuration dialogue with the BusAdministrator of
the AF100. If you configure a transmitting CDP with this method, you must guarantee/provide
respective MasterFrames by other methods:
• use normal AFTRA or MB90TRA PC-element in parallel or
• use an other IOBUSWR with SPEC = 4, i.e. generate master frames by APC board.
However the lookup table in VK will be configured so that location (AIB3) will point to port (AIB1)
PKR values are copied from II1...OI3:

II1 = contains Fcode, PAQ, PAS and TMP
II2 = contains interrupt enable bits
II3 = contains SZ, BNIB, TERR and TOB bits
II4 = contains TACK and T0...T6 bits
Values to data area of the port are copied into one page only from inputs IIL1...IILx. Values are
copied word by word (one word from one input). Each word is assumed to exist in VK less significant
byte first (= in Intel order). If you want to write to both pages, you must insert respective IOBUSWR
twice: once with AIB4 = 0 and once with AIB4 = 1 (or 11) or to insert it only once with AIB4 = 3 (or
13) and then execute it at least twice.
Note that AIB4 = (3 or 13) function is independent of the transmission direction of the port. However
BAP was originally designed so that microprocessor should toggle SZ-bit only in sourcing ports, and
the SZ of sinking ports is toggled by BAP itself.
ERR output indicates an error in the call parameters or input values. Call parameters C3 is allowed to
be >AIB1 and C4 >0, but respective input pins have no significance.

This function is intended for generating MasterFrame to AF100 (or just to AF100 connector of
YPK112 board). Call parameter C1 must be = 0 and C1 must be = 1.
Signal address (or device address if Fcode > = 8) is given through AI1 and Fcode in range 0...15
through II1.
Note that you can generate locally MasterFrames for such CDPs which you have configured with
IOBUSWR (SPEC3) in the same APC,but you have to insert anyway a cable terminator in the BNC
connector of YPK112.
Note also that if you use this method to generate MasterFrames, you must remove “real”
BusAdministrator(s) from the system. And remember, that BAP toggles the reception line some time
after each successfully received MasterFrame, if you do not execute (some of) these IOBUSWR (SPEC
= 4) frequently enough.
After using this function (= when utilizing normal BusAdministrator again) you should always restart
the APC, because otherwise SAT control line remains as output line of MC68302. IOBUSWR (SPEC
= 4) configures the SAT line to be outbut, when first time executed, and thereafter does not touch the
configuration. This decision was made to avoid all disturbances in SAT control line. The other
alternative would have been to configure the line as output every time before issuing MasterFrame and
back to input line immediately thereafter.
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Limiter LIM-N
Summary
LIM-N (LIMiter-1-of-N address) is used for limitation of LIM-N
integers, real numbers or time values. Several limit values can (C1,C2)
1 A1 AERR 10
be selected. A2T ERR
2 11
C2 AC2
21 I O 22
31 HLA1 I>HLA 40
32 HLA2 HLA 41
30 + C2 HLAC2
51 LLA1 I<LLA 60
52 LLA2 LLA 61
50 + C2 LLAC2
Call LIM-N (C1, C2) Table 1 Figure 1. PC Element LIM-N

values
C1 Data type I, IL, R, T, TR
C2 Number of optional limit values 1 to 9
Connections Table 2
1 A1 IB Address 1, Input which, when set, limits the output O to the limit
values connected to the inputs HLA1 and HLL1.
2 A2 IM Address 2. Input which, when set, limits the output O to the limit
values connected to the inputs HLA2 and HLL2.
.
.
.
C2 AC2 IB Address C2. Input which, when set, limits the output O to the
limit values connected tothe inputs HLAC2 and LLAC2.
10 AERR OB Address ERRor. Output which is set when 2 or more of the
inputs A1 to AC2 are set.
11 ERR OB ERRor. Output which is set when the limit for high level is less
than limit for low level.
21 I IC1 Input. Input which is connected to the signal being limited.
22 O OC1 Output. Output for the limited signal.
31 HLA1 IC1 High Limit Address 1, Input for upper limit value which limits
the signal when the input A1 is set.
32 HLA2 IC1 High Limit Address 2. Input for upper limit value which limits
.
.
.
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Table 2 continued
30+C2 HLAC2 IC1 High Limit Address C2. Input for upper limit value which limits
the signal when the input AC2 is set.
40 |>HLA OB Input >High Limit Address. Output which is set when the upper
limit of the element is reached.
41 HLA OC1 High Limit Address. Output which specifies the upper limit
where limiting begins.
51 LLA1 IC1 Low Limit Address 1. Input for lower limit value which limits
52 LLA2 IC1 Low Limit Address 2. Input for lower limit value which limits
.
.
.
50+C2 LLAC2 IC1 Low Limit Address C2. Input for lower limit value which limits
the signal when the input AC2 is set.
60 |<LLA OB Inpu t < Low Limit Address. Output which is set when the lower
limit of the element is reached.
61 LLA OC1 Ligh Limit Address. Output which specifies the lower limit
where limiting begins.
Function
LIM-N is used to limit up to 9 different limits.
Boolean output signals are given when the output is limited.
Selection of Limit Value

The limit value inputs HLA1 to HLAC2 or LLA1 to LLAC2 that will limit the value at output O are
selected with the inputs A1 to AC2. If the input A1 is 1, the output is limited by HLA1 and LLA1, if
A2 is 1, the output is limited by HLA2 and LLA2, etc. if none of the inputs A1 to AC2 is 1, O is
limited to the data value 0. If 2 or more of the inputs A1 to AC2 are set at the same time, the output is
limited by the limit values corresponding to the lowest numbered set input. The error signal output
AERR is set at the same time.
Limiting
When the input I exceeds the selected limit, the output O is limited to the limit value. One of the
outputs |> HLA or |< LLA will then be set depending on which limit was exceeded. The value of the
current limits for high and low level where limiting begins can be read at the outputs HLA and LLA.
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Supervision of Limit Values

The element checks that the limit value HLA is greater than the limit LLA. If HLA is less than LLA,
the error signal output ERR is set. The output O and the limit value outputs |> HLA and |< HLL are
retained from the sample before the error status developed.
LIM-N
1 A1
2 A2 2 AERR 10
test
C2 AC2
COMP
I1 ERR 11
I1 > I2
AO I2
(0)
31 HLA1
COMP
32 HLA2 I1 I > HLA 40
I1 > I2
I2
30 + C2 HLAC2 HLA 41
AO
(0)
51 LLA1
COMP
I1
I < LLA 60
52 LLA2 I1 > I2
I2
50 + C2 LLAC2 LLA 61
21 I O 22
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Master Header MASTER

Summary
The master header MASTER is used for the execution conrol of MASTER (C1,C2)
subordinate slave modules. 1 ON RUN 5
2 > SINGLE MODP 6
3 R
Call MASTER (C1, C2)
MASTER
Connections Table 1
C1 Cyclicity in ms Allowed values are between 2 ms and 2000 ms in steps of

2 ms.
C2 Place in the cycle 1 to 251: place in the cycle table, cyclic activation.
time table and/or
scheduling strategy.
252: activation at initalization after power down
253: activation at power down.
1 ON IB Control input which is set (to 1) with nor mal execution.

2 SINGLE IB If input ON and R are 0, the elements in the slave modules
can be executed once by setting SINGLE to 1.
3 R IB Reset. Input for clearing the slave modules.
6 MODP OB MODify Permission. Output that indicates if the master
and slave modules may be modified from service aids.
Function
Master is a supervisory execution controlling element for a number of slave modules. How often the
master and associated slave modules are to be executed is determined with the call parameter C1. The
place in the cycle time table is determined with the call parameter C2. The execution for execution
units with the same cycle time is based on the place in the cycle time table. When and how the slave
modules are executed is determined by the control inputs ON, SINGLE and R. The master is always
executed regardless of the state of these inputs.
Normal Exception
For normal execution the input ON must be set to 1. The master module and associated slave modules
are then executed as determined by the call parameters C1 and C2.
The order in which the subordinate slave modules are executed is determined by their order in the
documentation. If the ON input is reset after execution of the slave modules, the calculated data
remains until the next execution of the slave modules. The ON input overrides the SINGLE input, i.e.
if ON is set to 1. SINGLE has no effect.
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SINGLE Execution
If the SINGLE input is set when the ON input is reset, the slave modules are executed once as
described above. The calculated data remains until the next execution of the master and slave
modules.
Clearing
If the input R is set, the slave modules are executed in the reset mode. This means that all outputs of
elements in the slave modules are given default values, which in most cases are the U-value of the
data concerned. Input R overrides the inputs ON and single.
RUN
The output RUN is set only during normal execution, i.e. ON is set or SINGLE execution is
performed. With single execution, the RUN output is set for only one cycle.
MODP
Always true.
Effects from PCPGM

The ON and R inputs on the program header override the inputs on the master module header. The
input ON on PCPGM must be set to permit normal execution of master and slave modules.
PCPGM
RUN 5
ON
&
R
Reading of variables from the I/O
1 ON devices, common data areas and
1 other modules.
2 SINGLE
>
Normal execution of elements.
Writing of variables to the I/O

devices, common data areas
and other modules.
3 R &
1
Execution of elements in
reset mode.
MODP 6
Always = true
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Maximum Selector MAX

Summary
MAX (MAXimum selector) is used to select the highest value MAX (C1,C2)
within a set of up to 19 integers or real numbers. 1 DEADB
11 IA1 A 30
12 IA2 O 31
Call MAX (C1, C2)
10 + C2 IAC2
Connections Table 1 Figure 1. PC Element MAX
C1 Data type I,IL,R

1 DEADB IC1 DEADBand. Input for deadband.

11 IA1 IC1 Input Address 1. Input the value of which is
compared with the other inputs.
12 IA2 IC1 Input Address 2. Input which is compared
with the other inputs.
.
.
.
10+C2 IAC2 IC1 Input Address C2. Input which is compared with the other inputs.
30 A O1 Address. Output for the number of the input having the highest value.
31 O OC1 Output. Output for the highest value.
Function
The values at the inputs IA1 to IAC2 are compared and the greatest value is obtained at the output O.
The number of the input with the highest value is obtained at the output A. If the two highest signal
values are equal when the element is executed the first time, the signal with the lowest connection
number is selected highest.
Deadband
The deadband specified at the input DEADB is symmetrical around the value of the highest input.
The upper and lower deadband limits are calculated from the value for the highest input in the
preceding sample. To prevent rapid changes at the output A, the value at A is retained until the value
at the corresponding input is less than the calculated lower deadband limit or until one of the other
inputs exceeds the upper deadband limit.
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DataSet receiver for MB90 MB90REC

Summary
MasterBus 90 RECeive element is used to receive data on the high MB90REC
speed serial bus. Data types are determined by the call parameters and F1 IDENT ERR 10
can be I, IL, or R and should equal the call parameters of the F2 STATION RDY 11
transmitting MB90TRA function block. The MB90REC function block 1 ACT
can be used to trigger interrupt events. I1 21
I... 20 + ...
I*C1 20 + C1
IL1 51
IL... 50 + ...
IL*C2 50 + C2
R1 71
R... 70 +...
RC3 70 + C3
ERRC 99
Call MB90REC (C1, C2, C3)
Figure 1. PC
element MB90REC
Where: 0 < C 1 + 2 × C 2 + 2 × C 3 ≤ 16
Connections Table 2

F2 STATION II Node number of the sender 1 to 79
1 ACT IB Input. ACTivates dataset reception. 1=active
11 RDY OB Output data has been updated.
...
...
...
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Error Codes Table 3
ERRor Code # Description

3005 Station address in the hardware is not equal to the NODE
parameter of the database element MB90.
3101 Signal address already reserved (by another function block in
the same APC).
3102 STATION value is equal to the address defined in the MB90
database element.
3103 Illegal Function parameter.
3104 Illegal Call parameter.
3401 Time-out waiting for a BA. to request or to confirm the dataset
configuration.

3403 No response to address frame from the data source station.
3501 CRC-error (data frame corrupted during transf er).

Function
Upon initialization the MB90REC function block:

The dataset is introduced if necessary to the Bus Administrator. The specified dataset should be sent
from an APC by a MB90TRA function block or from a MasterPiece 90 station using the dataset
database element.
MB90REC captures from MasterBus 90 the dataset telegrams tagged with the specified signal
address. The signal address is computed using the STATION and IDENT parameters.
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To enable the receive function of a communication port, the STATION and IDENT of the MB90REC
function block must equal the station and ident numbers found in the sending block. Additionally, the
length of the telegram must equal the length specified by the MB90REC function block. Identical
values for call parameters should therefore be used in transmitting and receiving blocks (to avoid
mismatching length values).
The STATION parameter of the MB90REC must be equal to the NODE value of MB90 DB-element
in the sending station. The IDENT parameter must be equal to IDENT of the sending MB90TRA.
RDY is set (to 1) if a new data set telegram was transferred after the previous execution, and the
output terminals were updated. Updating of output data (and all other output pins as well) can be
temporarily or permanently disabled by resetting the input ACT (to 0).
Boolean values must be unpacked from integers ( I ) or long integers (IL). Packed booleans from
MasterPiece 90 stations must be unpacked from pairs of integers or long integers. All data types on
MasterPiece 90 stations occupy 4 bytes even if integer (I) data types are used. The order of the data in
the dataset received by the MB90REC function block is always: I values, IL values, and then R values.
It is important to keep track of this order when receiving from MasterPiece 90 stations. When
receiving integers (I) from MasterPiece 90, a dummy integer (I) value must be specified after each
transmitted integer (I) value in order to align the data.
Fault Handling
The ERR output is set (to 1) when a reception does not occur within 4 receiving intervals. A
diagnostic error code is loaded to output ERRC (see table 3). The ERR output will reset (to 0) or set
(to 1) depending on the communication status, but the last error code will always remain at the ERRC
output even when ERR is reset (ERRC is assumed to be cleared by specific action using the tools or
during the next restart of the station.)
possible via MB90.
condition.
Event Triggering
In each APC station there can be one (and only one) MB90 function block that specifies an
interrupting dataset. A negative value on the IDENT input is used to denote that the transfer of the
dataset should cause an interrupt and start an event driven application task in the station. A MB90
function block with a negative IDENT input will operate, with respect to data transfer, exactly the
same as if the IDENT was positive. The bus administrator does not know of the existence of dataset
interrupts.
MB90REC will be typically used. to specify the triggering dataset, although MB90TRA may be used
as well.
from MB90. This CONTRM must have C2 defined as 255 (denotes event task) and C3 defined as 2
(MB90 event task).
The event triggering MB90REC function block will normally reside in the MB90 event CONTRM.
This minimizes the delay between the physical data received and the actual updating of the output
data of the MB90REC function block.
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Note: that the first event triggered by a MB90 function block is generated after the configuration
message is received from the Bus Administrator. This first event does not signify that data has been
captured by the MB90 bus coupler.

• if the MB90 function block is contained under the event CONTRM then setting ACT (to 1 from
0) will have no effect. If the function block is outside the event task, then setting the ACT input
(to 1 from 0) will enable events to be triggered.
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DataSet transmitter for MB90 MB90TRA

Summary
MasterBus 90 TRAnsmit element is used to cyclically send MB90TRA
data on the high speed serial bus. The data values are updated F1 IDENT ERR 10
each time the function block is executed. The actual cyclic F2 SCAN
transmission of the data is independent of the function block 1 ACT
execution. However, the sending interval is configured by this 21 ERRC 99
I1
block. Data types are determined by the call parameters and 20 + ... I...
can be I, IL, or R. 20 + C1 I*C1
51 IL1
50 + ... IL...
50 + C2 IL*C2
71 R1
70 +... R...
Call MB90TRA (C1, C2, C3) 70 + C3 RC3
Call Parameters Table 1 MB90TRA
:KHUH 0 < C 1 + 2 × C 2 + 2 × C 3 ≤ 16
Connections Table 2

F2 SCAN II Transmission interval. 1 to 4096 ms.
See table 3
1 ACT IB Input. ACTivates dataset transmission. 1=Active.
...
20+C1 IC1 II Input. I value number C1.
...
...
99 ERRC OI ERRor Code see Table 4
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SCAN Values Table 3
Value of SCAN Actual transmission interval used
1 1
2 2
3 to 5 4
6 to 11 8
12 to 23 16
24 to 47 32
48 to 95 64
96 to 191 128
192 to 383 256
384 to 767 512
768 to 1535 1024
1536 to 3071 2048
3072 to 4096 4096
ErrorCodes Table 4

3005 Station address in the hardware is not equal to the NODE parameter
of the database element MB90.
3101 Signal address already reserved (by another function block in the
same APC).
3103 Illegal IDENT-value.
3104 Illegal (Call) Parameter or SCAN-value.
3105 More than one interrupting dataset.
3301 Time slots cannot be allocated for the dataset.
3302 Dataset identifier reserved by another station.
3401 Time-out waiting for a BA to request or to confirm the dataset
configuration.

3300 to 3399 MB90 FULL(GLOBAL)
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Function
Upon initialization the MB90TRA function block:

The dataset is introduced to the Bus Administrator. After approval, the transmission of the dataset is
started instantaneously, and repeated at intervals as determined by the parameter SCAN.
Time-out of approval message and/or disappearance of cyclic time slots for the dataset will be detected
and signaled at MB90TRA error pins.
The dataset configured by a MB90TRA function block can be received by MB90REC function blocks
in other APCs or by a dataset database element in a MasterPiece 90 station. Each MB90TRA IDENT
value should be unique for a station. To be received correctly there should be at the other end of a link
a receiver block MB90REC with identical call parameter and IDENT values. The STATION value of
the receiving block must equal the station number of the transmitting APC.
The station numbers of transmitting stations are declared using the NODE parameter of the DB
element MB90. The matching address value must be also set on the MB90 bus coupler board
(YPK112A) using the provided hardware switches. If the NODE value is 127 or 255, all hardware
settings (within supported address range 1 to 79 = 00H...4FH) are correct, and the station number for
MB90TRA is copied from the hardware switches. (Note: Hardware address switches are read as
hexadecimal values, e.g., station 33 must be 21H in the set-up switches.)
SCAN determines the transmission interval for the dataset on MB90 (i.e., how often the data values
are transmitted). See table 3 for possible values. The transmission interval can be clearly shorter than
the execution interval of MB90TRA provided there is capacity on MB90. (Or the opposite case, if
MB90 is severely loaded, there is free capacity available in APC, and the transmission delays should
be minimal.)
Transmission can be initially and/or dynamically deactivated by reseting (to 0) the input ACT. Even
then the MB90TRA function block will present a dataset to the bus administrator and a
communication port is locally reserved in the dual port memory of YPK112A. However, the transmit
function associated with the signal address will be disabled, and therefore the receiving blocks in
other stations will show an error.
Boolean values must be packed into integers ( I ) or long integers (IL). Packed booleans intended for
MasterPiece 90 stations must be packed to long integers. Boolean data on MasterPiece 90 stations
always occupies 4 bytes. The order of the data in the dataset sent by the MB90TRA function block is
always: I values, IL values, and then R values. It is important to keep track of this order when
transmitting to MasterPiece 90 stations. However it is recommended not to use integer (I) values at all
when the receiving station is MasterPiece 90.
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Fault Handling
The ERR output is set (to 1) when a transmission does not occur within 4 sending intervals as defined
by cycle time of the function block. A diagnostic error code is loaded to output ERRC (see table 4).
The ERR output will reset (to 0) or set (to 1) depending on the communication status, but the last
error code will always remain at the ERRC output even when ERR is reset (ERRC is assumed to be
cleared by specific action using the tools. during the next restart of the station or by a zero-pulse in the
ACT-pin).
possible via MB90.
condition.
Event Triggering
In each APC station there can be one (and only one) MB90 function block that specifies an inter-
rupting dataset. A negative value on the IDENT input is used to denote that the transfer of the dataset
should cause an interrupt and start an event driven application task in the station. A MB90 function
block with a negative IDENT input will operate, with respect to data transfer, exactly the same as if
the IDENT was positive. The bus administrator does not know of the existence of dataset interrupts.
MB90TRA may be used to specify the event triggering dataset, although MB90REC will be typically
used.
from MB90. This CONTRM must have C2 defined as 255 (denotes event task) and
C3 defined as 2 (MB90 event task).
The event triggering MB90TRA function block will normally reside in the MB90 event CONTRM.
This minimizes the delay between the physical data transmitted and the actual updating of data for
next transmission.
Note: that the first event triggered by a MB90 function block is generated after the configuration
message is received from the Bus Administrator. This first event does not signify that actual data has
been sent by the MB90 bus coupler.

• if the MB90 function block is contained under the event CONTRM then setting ACT (to 1 from
0) will have no effect. If the function block is outside the event task, then setting the ACT input
(to 1 from 0) will enable events to be triggered.
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Minimum Selector MIN

Summary
MIN (MINimum selector) is used to select the lowest value within MIN (C1,C2)
a set of up to 19 integers or real numbers. 1 DEADB
11 IA1 A 30
12 IA2 O 31
Call MIN (C1, C2)
10 + C2 IAC2
Connections Table 1 Figure 1. PC Element MIN
C1 Data type I,IL,R

C2 Number of input 2 to 19
1 DEADB IC1 DEADBand. Input for deadband.

.
.
.
10+C2 IAC2 IC1 Input Address C2. Input which is
compared with the other inputs.
30 A O1 Address. Output for the number of the
input having the lowest value.
31 O OC1 Output. Output for the lowest value.
Function
The values at the inputs IA1 to IAC2 are compared and the lowest value is obtained at the output O.
The number of the input with the lowest value is obtained at the output A.
I the two smallest signal values are equal when the element is executed the first time, the signal with
the lowest connection number is selected.
Deadband
The deadband specified at the input DEADB is symmetrical around the value of the lowest input
The upper and lower deadband limits are calculated from the value for the lowest input in the
preceding sample.
To prevent rapid changes at the output A, the value at A is retained until the value at the
corresponding input exceeds the calculated upper deadband or until one of the other inputs falls below
the lower deadband limit.
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Mono Function MONO

Summary
The mono function MONO can be used for time limiting of operation of MONO
1 RTG
outputs and automatic functions. The element can also be used for impulse O
2 I 5
extension, stall alarm function, etc. TE
3 TP 6
Call MONO Figure 1. PC Element

MONO
Connections Table 1
1 RTG IB ReTrigG. Input to select whether or not the MONO function

is to be retriggerable. If RTG is set, a retriggerable function is
obtained.
2 I IN Input. Input for start of the MONO function when the input
changes from 0 to 1.
3 TP IT Time Pulse. Input for setting of pulse time.
5 O OB Output. Output which is set when the MONO function starts
and resets (to 0) when the time set has elapsed.
6 TE OT Time Elapsed. Output for time elapsed when Ois set. When
the time set (TP) has elapsed TE will stop.
Function
A memory is set when the input I is set. The
2 O 5
output then goes to 1, see function diagram. I S
When the time set in the timer has elapsed,

the memory is cleared and the output O goes T R
1 &
to 0. TP TE TE 6
MONO Function. Not >1

1
1 RTG
Retriggerable
If the input RTG is reset, the MONO function 3 TP
is not retriggerable. if a new pulse occurs at
the input I before the timer has elapsed, Figure 2. Function diagram
it does not affect the timer. Only when the
time set has elapsed and the output O is reset can the MONO function be restarted by the input I
going from 0 to 1.
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MONO Function, Retriggerable

If RTG is set, a retriggerable MONO function is obtained, i.e. the timer starts from 0 each time a new
pulse occurs at the input I. If a new pulse occurs at the input I before the timer has elapsed, the timer
will restart, i.e. the MONO function is retriggerable.
Conn
21
Conn
50
0 1 2 3 5 10
Figure 3. Time diagram MONO function, not retriggerable.
Conn
21
Conn
50
0 1 2 3 5 10
Conn.3 Time set = 2 s
Conn.1 Ser
Figure 4. Time diagram MONO function, retriggerable.
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Element for Copying Data MOVE

Summary
MOVE copies the value at the input. This may be used to MOVE (C1,C2)
copy the value from one location in the data base to another. 1 A 21
2 O 22
Call MOVE (C1, C2) C2 20 + C2
Figure 1. PC Element MOVE

Connections Table 1
C1 Data type B, I, IL, R, T, TR

C2 Number of inputs
and outputs 1 to 19
1 - IC1 Input for value 1.

2 - IC1 Input for value 2
.
.
.
C2 - IC1 Input for value C2.

21 - OC1 Output for value 1.
22 - OC1 Output for value 2.
.
.
.
20+C2 OC1 Output for value C2.
Function
The element copies the values at the inputs to the respective output. The type of data to be moved is
determined by the call parameter C1. The number of values moved is determined by the call
parameter C2.
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Multiplier MUL
Summary
MUL (MULtiplier) is used for multiplication of up to 19 integers or MUL
real numbers. 1 X 20
2
C1
Call MUL (C1, C2) Figure 1. PC Element MUL
Connections Table 1

1 IC1 Input for multiplicand.

2 IC1 Input for multiplier.
.
.
.
C2 IC1 Input for multiplier.
20 OC1 Output for product.
Function
The values at the inputs 1 to C2 are multiplied and the product is stored at the output 20.
Overflow
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Integer scaling element MULDIV

Summary
MULtiplier DIVider element is used to scale integer values by dividing the MULDIV
product of two integer inputs. 1 I O 10
2 MUL REM
11
3 DIV
Call MULDIV Figure 1. PC Element

MULDIV
Connections Table 1
1 I II Input for multiplicand.

2 MUL II Input for MULtiplier.
3 DIV II Input for DIVisor.
10 O OI Output for quotient.
11 REM OI Output for REMainder.
Function
The product of input I and input MUL is divided by the input DIV. The quotient is loaded at the
output O and the remainder at REM. The element internally uses 32 bit accuracy to perform the
multiplication.
Overflow
If the maximum positive value is exceeded then the output O is limited to +32767. If the minimum
negative value is exceeded then the output O is limited to -32768.
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Multiplexer MUX-I
Summary
MUX-I (MULtipleXer-with Integer address) is used as a MUX-I
selector. MUX-I has up to 19 inputs. The data type can be (C1,C2)
11 A AERR 5
integer, real numbers, Boolean or time.
31 IA1 O 50
32 IA2
Call MUX-I (C1, C2) 30 + C2 IAC2
Figure 1. PC Element MUX-I

Connections Table 1

5 AERR OB Address ERRor. Output which is set when the address value is larger
than the number of inputs, or negative.
11 A II Address. Input for address value which specifies which input is to be
connected to the output O. When A = 0, the output is set to 0.
31 IA1 IC1 Input Address 1. The first input to the selector.
32 IA2 IC1 Input Address 2. The second input to the selector.
.
.
30+C2 IAC2 IC1 Input Address C2. The last input to the selector.
50 O OC1 Output. Data output from the selector.
Function
Addressing
The input, the data value (IA1 to IAC2) which is connected to the output O, is specified with an
address (integer 1 to C2) at the input A. If the address is 0, the data value o is connected to the output
O.
Supervision
The address A is monitored and if its value is greater than the number of inputs or is negative, the
error signal output AERR is set. The data value 0 is then obtained at the output.
11 A A > C2 AERR 5
or
A<0
test
D = 0 AO
31 IA1
32 IA2 O 50
30 + C2 IAC2
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Multiplexer MUX-MI
Summary
MUX-MI (MULtipleXer-with Memory and Integer address) is MUX-MI
used as a selector with memory function. MUX-MI has up to 19 (C1,C2)
1 S
inputs. The data type can be integers, real numbers, Boolean or 2 >L AERR 5
time. 3 R
11 A
31 IA1 O 50
32 IA2
Call MUX-MI (C1, C2) 30 + C2 IAC2
Connections Table 1 Figure 1. PC Element MUX-MI

1 S IB Set. Input for loading of new values each time the element is executed.
When the input S is reset 0, the last value loaded will remain at the
outputs.
2 L IB Load. Dynamic input for loading of the data addressed.
3 R IB Reset. Input for clearing the outputs. This input overrides the S and L
inputs.
5 AERR OB Address ERRor. Output which is set when the address value is greater
than the number of inputs, or negative.
11 A II Address. Input for address value which specifies from which input
data is to be loaded. When A = 0, the output is reset to 0.
.
.
.
Function
Addressing
The input data value (IA1 to IAC2) stored at the output is specified with an address (integer 1 to C2)
at the input A. If the address is 0, the data value 0 is stored.
Loading
The value is loaded when the input L is set to 1. If input S is set, new data is loaded each time the
element is executed. When S is reset after having been set, the data loaded most recently remains until
the element is executed more than once with input S, L, or R set. Input S overrides input L, i.e. when
S is set, L has no function.
Clearing
The input R clears the data output and prevents further storage of data.
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Supervision
The address A is monitored and if its value is greater than the number of inputs, or is negative, the
error signal output AERR is set. The data value 0 is then stored at the output.
11 A A > C2 AERR 5
or
D = 0 AO A<0
test
31 IA1
32 IA2
30 + C2 IAC2
O 50
I
1 S
2 L 1 C
>1
3 R
R
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Multiplexer MUX-MN
Summary
MUX-MN (MULtipleXer-with Memory and 1-of-N address) is MUX-MN
used as a selector with memory function. MUX-MN has up to (C1,C2)
1 S
19 inputs. The data type can be integers, real numbers, Boolean 2 >L
or time. 3 R AERR 5
11 A1
12 A2
10 + C2 AC2
31 IA1 O 50
32 IA2
Call MUX-MN (C1, C2) 30 + C2 IAC2
Connections Table 1 Figure 1. PC Element MUX-MN

1 S IB Set. Input for loading new values each time the element is executed.
When the input S is reset, the last value loaded will remain at the
outputs.
2 L IB Load. Dynamic input for loading of the data addressed.
3 R IB Reset. Input for clearing the output. This input overrides the S and L
inputs.
5 AERR OB Address ERRor. Output which is set when two or more of the inputs
A1 to AC2 are set.
11 A1 IB Address 1. Input to store data from the input IA1 at the output O.
12 A2 IB Address 2. Input to store data from the input IA1 at the output O.
10+C2 AC2 IB Address C2. Input to store data from the input IAC2 at the output O.
Function
Addressing
The input data value (AI to IAC2) stored at the output is specified with the inputs A1 to AC2. If the
input A1 is 1, the value from input IA1 is stored at the output, if A2 is 1, the value from input IA2,
etc. If none of the inputs A1 to AC2 is set to 1, the data value 0 is stored at the output O.
Loading
The value is loaded when the input L is set to 1. If input S is set, new data is loaded each time the
element is executed. When S is reset after having been set, the data loaded most recently remains.
Input S overrides input L, i.e.when S is set, L has no function.
Clearing
The input R clears the data output and prevents further storage of data.
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Supervision
If two or more of the inputs A1..AC2 are set simultaneously, the output AERR is set and the value
from the input which correspond to the address input set with the lowest number is stored at the
output O.
11 A1
12 A2
2 AERR 5
test
10 + C2 AC2
D = 0 AO
31 IA1
32 IA2
30 + C2 IAC2
O 50
I
1 S
2 L 1 C
>1
3 R
R
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Multiplexer MUX-N
Summary
MUltipleXer Array with one of N address is a function block used as a MUX-N
11 A1 AERR 5
selector. An optional number of inputs can be specified. The data type .. ..
can be integer, real number, boolean, or time. A*C2
10 + C2
31 IA1 O 50
.. ..
Call MUX-N (C1,C2) 30 + C2 IA*C2
Call Parameters Table 1 MUX-N
C1 Data Type I, IL, R, B, T, TR

C2 Number of outputs 1 to 19
Connections Table 2
5 AERR OB Address ERRor. Set (to 1) when two or more of the inputs
A1 to AC2 are set at the same time.
11 A1 IB Address 1. Input for connection of IA1 to the output O.
12 A2 IB Address 2. Input for connection of IA2 to the output O.
10+C2 AC2 IB Address C2. Input for connection of IAC to the output O.2
31 IA1 IAC1 Input Address 1. The first input to the selector.
32 IA2 IAC1 Input Address 2. The second input to the selector.
...
30+C1 IAC1 IAC1 Input Address C1. The last input to the selector.
50 O OAC1 Output. Data output from the selector.
Function 11 A1
The value of the input address IA1 to IAC2, 12 A2
which corresponds to the lowest address A1 to 2 AERR 5

test
AC2 that is set (to 1), is connected to the output
10 + C2 AC2
O.
D = 0 AO
31 IA1
If none of the inputs A1 to AC2 is set then the
32 IA2
data value 0 is connected to output O. O 50
Supervision 30 + C2 IAC2
If two or more of the inputs A1 to C2 are set at

the same time, the output AERR is set (to 1) Figure 2. Function diagram
and the input which corresponds
to the address input set with the lowest number is connected to the output O.
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Multiplexer for text MUXA-I

Summary
MUltipleXer Array with Integer address is a function block used as a MUXA-I
selector for text arrays. An optional number of inputs can be specified (C1,C2)
11 A AERR 5
as well as the number of characters in the text arrays.
31 IA1 50
.. ..
30 + C2 IA*C2
Call MUXA-I (C1,C2)
MUXA-I
Call Parameters
C2 Number of characters in the arrays. 1 to 30
Connections Table 2
5 AERR OB Address ERRor. Set (to 1) when input A is greater than

call parameter C1 or a negative value.
11 A II Address. Selection of which input value should be stored
at the output O. If the value is 0,a blank text is stored at
the output.
31 IA1 IAC2 Input Address 1. The first input in the selector.
32 IA2 IAC2 Input Address 2. The second input in the selector.
... IAx IAC2 Input Address x ........
30+C1 IAC1 IAC2 Input Address C1. The last input in the selector.
50 O OAC2 Output. Output from the selector.
Function
The text string at the input (IA1 to IAC1), specified by the input address A (1 to C1), is stored at the
output O. If A is 0, then a blank text string is loaded at O.
Supervision
The value of the input address A is checked each execution of the function block. If it is greater than
the number of outputs specified by the call parameter C1 or it is a negative number, then the AERR
output is set (to 1). A blank text string is loaded at output O.
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Or Gate OR
Summary
OR elements are used to form general combinatory expressions with Boolean 1
1
20
variables. 2
The elements can have a maximum of 19 inputs. C1
Figure 1. PC
Element OR
Call OR (C1) Table 1
Connections Table 2
1 - IB Input
2 - IB Input
C1 - IB Input
20 - OB Output
Function OR Element
The output signal is set if any inputs
are set. See the truth table below 1
1
20
. 2
Table 3 Truth table OR (3) 3
1 2 3 20 Figure 3. PC
Element OR (3)
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
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Or gate OR-A
Summary
OR with AND gates on the inputs is used to form general combinatory OR-A
expressions with boolean variables. 1 1 60
..
C1
11
.. &
10 + C2
..
..
51
.. &
Call OR-A (C1,C2,C3,...Cn) 50 + C6
Figure 1. PC Element OR-A

Call Parameters
C1 Number of inputs in the OR part 0 to 9

of the element.
C2 Number of inputs in the first AND 0 to 9
gate of the element.
C3 Number of inputs in the second 0 to 9
AND gate of the element.
.....
Cn Number of inputs in the last 0 to 9
AND gate of the element.
Where: 1≤ n ≤6
1 ≤ C1 + C 2 +... + Cn ≤ 40
Connections Table 2
1 - IB Input direct to the OR gate in the element.

2 - IB Input direct to the OR gate in the element.
... - IB Input direct to the OR gate in the element.
C1 - IB Input direct to the OR gate in the element.
11 - IB Input to the first AND gate in the element.
12 - IB Input to the first AND gate in the element.
... - IB Input to the first AND gate in the element.
10+C2 - IB Input to the first AND gate in the element.
21 - IB Input to the second AND gate in the element.
22 - IB Input to the second AND gate in the element.
... - IB Input to the second AND gate in the element.
10*(n-1) + 1 - IB Input to the last AND gate in the element.
10*(n-1) + 2 - IB Input to the last AND gate in the element.
... - IB Input to the last AND gate in the element.
10*(n-1) + Cn - IB Input to the last AND gate in the element.
60 - OB Output.
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Function
This function provides faster execution than if separate elements are used. The inputs only need to be
tested until the value of the output can be determined. If input 1 is 1 then the output can be set (to 1)
irrespective of all other inputs.
See the example of OR-A (3,3,3) as shown in figure 1 and in table 3.
Truth table AND-O (3,3,3) Table 3
1 2 3 11 12 13 21 22 23 60
0 0 0 0 0 0 1 1 1 1
0 0 0 0 x x 0 x x 0
0 0 0 0 x x 1 0 x 0
0 0 0 0 x x 1 1 0 0
0 0 0 1 0 x 0 x x 0
0 0 0 1 0 x 1 0 x 0
0 0 0 1 0 x 1 1 0 0
0 0 0 1 1 0 0 x x 0
0 0 0 1 1 0 x 0 x 0
0 0 0 1 1 0 x x 0 0
0 0 0 1 1 1 x x x 1
0 0 1 x x x x x x 1
0 1 x x x x x x x 1
1 x x x x x x x x 1
x indicates that the input has no effect on the value of the output or the execution time of the function
block.
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Oscillator for sine wave OSC-SIN

Summary
OSCillator - SINe wave element is used to generate a sinusoidal signal. The OSC-SIN
1 EN O 5
period and amplitude are controlled by the inputs.
2 TC ERR 6
3 AMP
OSC-SIN
Call OSC-SIN
Connections Table 1
1 EN IB ENable. Input for activation of sine wave generation.

2 TC ITR Time Cycle. Input for period.
3 AMP IR AMPlitude. Input for amplitude.
5 O OR Output. Output for sine wave.
6 ERR OB ERRor. Output which is set (to 1) if the period TC is undersized
Function
If EN is set (to 1) then the OSC-SIN function block AMP
generates a sinusoidal wave with period TC and amplitude
AMP, as shown in figure 2. The sine wave is created from a
table with 256 values per period.
TC
If EN is reset (to 0) the output O is cleared. Figure 2. Generated waveform
When EN is set to 1 after having been 0, the sine wave begins from t=0.
Supervision
If the function block is executed with a time period TC less than 20 times the cycle time of the
function block, then the output ERR is set to 1.
If the cycle time is less than the period TC, the output O is cleared (to 0).
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Panel Control PC Element PANCON

Summary
PANCON is used to control one door panel APC 700 PAN. APC 700 PANCON
F1 STATION ERR 10
PAN has 10 push buttons and a display with two 20 character lines.
F2 LOGNR PB2 11
PANCON reads the pressing of the push buttons and builds two text 12
3 U PB3
lines. The panel operator can select either the Event display or the 13
PB4
Signal display. The event display displays the contents of one event PB5 14
buffer. The Signal display displays two values formatted by the input PB6 15
terminals 21 to 27. PB7 16
PB8 17
PB9 18
PB10 19
21 S_ID S_DISPL 31
22 S1_TEXT
23 S1_FORM
24 S1_IN
25 S2_TEXT
26 S2_FORM
27 S2_IN ERRC 99
Call PANCON PANCON
Connections Table 1
F1 STATION II Hardware ADDRess of the control panel. 1 to 15

F2 LOGNR II Number of event logger where the element reads. -8 to 8
3 U IB Update texts and values.
10 ERR OB ERRor indication output. 1 = active error
11 PB2 OB Push Button 2 from panel keyboard.
21 S_ID IA5 Drive number identification.
22 S1_TEXT IA20 Signal name for the first display row.
23 S1_FORM II Signal value display format on the first display
row.
24 S1_IN IR Signal value for the first display row.
25 S2_TEXT IA20 Signal name for the second display row.
26 S2_FORM II Signal value display format on the second display
row.
27 S2_IN IR Signal value for the second display row.
31 S_DISP OB Indication of signal or event display.
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Cycle time of PANCON

PANCON generates a panel link message every time it is executed.
The panel link protocol software operates cyclically at 100ms intervals. During one transmission
cycle 3 door panels can be served (only 2 if terminals U of the PANCONs are set).
The cycle time of PANCON should not be less than 100ms in order to avoid panel link overload. The
cycle time can be, say 200ms or 400ms without decline of panel performance.
Control terminal functions

Terminal F1 (STATION) should match the panel id number (1 to 15) set by ACV 700 PAN in
internal mode, if no panel with corresponding id number is active on the panel link then ERR is set
and the error code 2xx05 (no response from panel) is output on ERRC.
Terminal F2 (LOGNR) is the number (1 to 8) of the event logger to which PANCON connects the
panel. The logger must exist and be properly programmed, otherwise an error code is output on
ERRC. If LOGNR is 0 then the event display is inactive.
Terminal 3 (U) has the significance "underline" in APC system releases --> 1.0/7. If U is set then the
first character in the text string is sent inverted (underlined).
Terminal 3 (U) has the significance "continuous updating" in APC system releases 1.0/8 -->. If U is
set (1) then is signal display the upper row and the lower row including texts are alternately updated
on every execution cycle.
If U is reset (0) then a message composed of the signal values S1_IN and S2_IN only, is generated on
every execution cycle. The messages update S_ID,S1_TEXT,S2_TEXT,S1_FORM and S2_FORM
every 20th cycle. As a consequence the operation of the panel link is speeded up.
Panel button functions
Panel buttons
The pressing of the push buttons 2 to 10 is indicated at terminals PB2 to PB10. The pushing of a
button generates a pulse at the output.
Function of buttons:
PB1 is used to change operational mode and to switch display.
PB3 to PB5 and PB8 to PB10 can be freely used for application programming.
On Signal display PB2, PB6, PB7 can be freely used for application programming. On Event display
the buttons have dedicated functions.
PB2 is used to scroll up the Event display.
PB6 is used to acknowledge the displayed event.
PB7 is used to scroll down the Event display.
The reply message from APC 700 PAN includes the push button states. PB2 to PB10 are updated
every time PANCON is executed.
Internal operational mode

The panel ( APC 700 PAN ) operates either in internal mode or normal mode.
Internal mode is used to:

Display and set the panel id number.
Display and set the contrast of the panel display.
Display and set the communication timeout time for the panel.
Display the version number of the panel.
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Internal mode is entered by pressing PB1 longer than 5 seconds. Normal mode is reentered by
pressing PB1 longer than 5 seconds.
The value to be set (id number, contrast) is selected by pressing PB1 for a short time. The set point is
changed up/down by the buttons PB2/PB7.
The entered panel id number must match the value on terminal STATION to activate PANCON.
In internal mode PANCON outputs PB2 to PB10 are 0 (false).
Normal operational mode

In normal mode either Event display or Signal display is activated. The display is switched by
pressing PB1 a short time.
Event display
Event display is activated only if an Event logger, the number of which matches terminal LOGNR of
PANCON exists. The Event logger buffer must also contain at least one event.
One event is occupies both lines on the display.
The upper line shows the text string for the event. The text string can be up to 20 characters long. The
lower line shows date and time (100 us resolution) for the event.
Examples:
OVERCURRENT
920324 13:20:24,324
In Event display button states PB3 to PB5 and PB8 to PB10 are transferred to the corresponding
PANCON output terminals. PB2, PB6 and PB7 remain 0 (false).
Signal display
The Signal display displays two signals, each on its own line. The line is composed of a text string
with up to 20 characters followed by the value.
Signal display without signal identification (S_ID = "0")

SPEED(M/MIN) 1124.5
CURRENT(A) 1003
Signal display with signal identification (S_ID = "25.1 ")

25.1 SPEED 1124.5
CURRENT(A) 1003
The text on the upper line is concatenated from the strings S_ID and S1_TEXT.
The text on the lower line is the string S2_TEXT.
S_ID consists of up to 5 characters and can be represent e.g. the drive number. If S_ID begins with
space or "0" then S_ID is omitted and S1_TEXT aligned to the left.
A too long text string is overwritten by value characters from the right.
The value for the upper line is input as a real number to S1_IN.
The value for the lower line is input as a real number to S2_IN.
S1_FORM formats the displayed digits for S1_IN and S2_FORM the digits for S2_IN as follows:
72 = 7 characters, 4 digits before the desimal point and 2 after

43 = 4 characters, 0 digits before the desimal point and 3 after
50 = 5 characters, 5 digits without desimal point
0 = 0 characters, no digits are displayed
On Signal display button states PB2 to PB10 are transferred to the corresponding PANCON output
terminals.
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Advanced PANCON applications

More than 2 signals can be displayed by using text and value multiplexes in the application program.
This technique has been used in the Type Circuits APCPAR and DRUSD, which utilizes the
functionality of PANCON and APC 700 PAN.
APCPAR saves and restores APC parameters.
DRUSD uploads, saves and downloads drive parameters.
Negative logger number indicates enabling of the special scrolling mode of events. In the special
scrolling mode all events since the last clear are scrollable, even if they have been acknowledged.
Logger number 0 means that there is no event logger to be scrolled.
Note: logger number 0 is not allow in APC versions prior 1.0/8 and logger numbers -8 to -1 are not
allowed in APC prior 1.0/9.
Error codes Table 2
ERRor code # Description
2xx02 Invalid ident or object number in response.

2xx05 No response from the panel.
2xx06 Panel too busy to handle received messages.
2xx11 Attempt to delete non-existing buffer.
2xx12 Receive buffers not available. Increase the number of buffers defined
in the PAN00 database element.
2xx18 PAN00 has been defined to be a slave station.
2xx19 DB element PAN00 has not been defined.
Where xx is equal to 50 + node number(1 to 15).
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Input from Panel Bus PANREC

Summary
PANel RECeive element is used to receive data from another APC PANREC
F1 STATION ERR 10
unit or remote I/O. Data types are determined by the call parameters
F2 MASTER RDY 11
and can be I, IL, or R.
F3 DEVICE
F4 IDENT
1 RESET
I1 21
IC1 20 + C1
IL1 51
ILC2 50 + C2
R1 71
RC3 70 + C3
ERRC 99
Call PANREC (C1, C2, C3)
Figure 1. PC element PANREC
Where: 2 × C 1 + 4 × C 2 + 4 × C 3 ≤ 56
Connections Table 2
F1 STATION II Node number of the sending device 1 to 15

F2 MASTER II MASTER/SLAVE selection. 1=MASTER
F3 DEVICE II DEVICE identity number.
F4 IDENT II Message IDENTity number. 1 to 127
1 RESET IB Clears error outputs and initializes the
communication link with a change 0 to 1.
10 ERR OB Initialization or communication ERRor.
11 RDY OB ReaDY. Set after acknowledgment of data.
...
...
...
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Error Codes Table 3
2xx00 No fault.
2xx02 Invalid indent or object number in response.
2xx03 Panel link time-out.
2xx05 No response from node.
2xx06 Target too busy to handle received messages.
2xx12 Receive buffers not available. Increase the number of buffers defined in the
PAN00 database element.
2xx18 Master/Slave conflict between the definition of the PANREC function block
element and the PAN00 database element.
2xx19 Database element PAN00 has not been defined.
Where xx is equal to 50 + node number (0..15).
Function
The PANREC function block receives data from remote I/O units, control panels, or other APC’s on
the panel bus. With the use of the call parameters, a combination of data types can be selected. A
maximum of 28 values (56 bytes), depending on the data type can be received by one element. The
available data types are 2 byte integer, 4 byte integer long, and 4 byte real.
General
The APC uses the panel bus serial link to communicate to other APC’s, remote I/O, and control
panels. The bus is physically connected to the APC board using the 8 pole screw terminal connector
X2. The physical layer of the panel bus is isolated RS-485. The maximum length of the bus is 300
meters and is multi-drop configuration.
Master/Slave Selection
There can be only one master on a panel link bus. The master must be an APC unit. The master can
send messages to slaves in any order. Slaves must always be ready to receive messages from a master
node. Slaves can only respond to requests from the master node; a slave node cannot initiate a receive
request. This means that only one APC node on a panel link bus can transmit and receive data
directly to a AOS (advanced operator station) or to a remote I/O unit. If more than one APC is
connected to a panel link bus then all slave nodes must communicate to AOS and remote I/O units via
application programming in the master APC.
A node is designated as a master node by setting the PAN00 database element parameter NODENO
to 0 and setting the PANREC function block parameter MASTER to 1. If MASTER is set (to 1) then
the STATION input parameter is set to the node number of the transmitting slave. If MASTER is
reset (to 0) then the STATION input parameter must be set to the same value as defined by the
parameter NODENO of the database element PAN00.
Each slave device must have a unique node number (1 to 15). The node number of remote I/O is set
via a hardware switch.
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Message Identification
Identical STATION, IDENT, and DEVICE numbers must be used by the receiving and transmitting
function block elements between a master and slave node. The function block pairs must also have the
same call parameter definition. The combination of STATION, IDENT, and DEVICE must be unique
within each node.
IDENT and DEVICE numbers for remote I/O and AOS units are defined in their respective manuals.
Fault Handling
The error output is set when the link responds incorrectly. If there is a fault creating the transmit and
receive buffer description, the RESET input must be set (to 1) before a retry is made. If there is a
time-out longer than 30 executions of the function block, then the ERROR output is set. The ERROR
output is reset (to 0) after the first successful response from the sending node.
The RDY output is set after each successful receive and reset after every poll that results in no new
data.
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Output to Panel Bus PANTRA

Summary
PANel TRAnsmit element is used to send data to another APC unit PANTRA
F1 STATION ERR 10
or remote I/O YPQ110A. Data types are determined by the call
F2 MASTER RDY 11
parameters and can be I, IL, or R.
F3 DEVICE
F4 IDENT
1 RESET
21 I1
20 + C1 IC1
51 IL1
50 + C2 ILC2
71 R1
70 + C3 RC3
Call PANTRA (C1, C2, C3) ERRC 99

Figure 1. PC Element PANTRA
Where: 2 × C 1 + 4 × C 2 + 4 × C 3 ≤ 56
Connections Table 2
F1 STATION II Node number of the sending device. 1 to 15

F2 MASTER II MASTER/SLAVE selection. 1=MASTER
F3 DEVICE II DEVICE identity number.
F4 IDENT II Message IDENTity number. 1 to 127
1 RESET IB Clears error outputs and initializes the
communication link with a change 0 to 1.
10 ERR OB Initialization or communication ERRor.
11 RDY OB ReaDY. Set after acknowledgment of data.
...
20+C1 IC1 II Input. I value number C1.
...
...
99 ERRC OI ERRor Code. see Table 3
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Error Codes Table 3
2xx00 No fault.
2xx02 Invalid indent or DEVICE number in response.
2xx03 Panel link time-out.
2xx05 No response from node.
2xx12 Transmit buffers not available. Increase the nu mber of buffers defined
in the PAN00 database element.
2xx18 Master/Slave conflict between the definition of the PANTRA function
block element and the PAN00 database element.
2xx19 Database element PAN00 has not been defined.
where xx is equal to 50 + node number (0 to 15).
Function
The PANTRA function block transmits data from remote I/O units, control panels, or other APC’s on
the panel bus. With the use of the call parameters, a combination of data types can be selected. A
maxi-mum of 28 values (56 bytes), depending on the data type can be sent by one element. The
available data types are 2 byte integer, 4 byte integer long, and 4 byte real.
General
The APC uses the panel bus serial link to communicate to other APC’s, remote I/O, and control
panels. The bus is physically connected to the APC board using the 8 pole screw terminal connector
X2. The physical layer of the panel bus is isolated RS-485. The maximum length of the bus is 300
meters and is multi-drop configuration.
Master/Slave Selection
There can be only one master on a panel link bus. The master must be an APC unit. The master can
send messages to slaves in any order. Slaves must always be ready to receive messages from a master
node. Slaves can only respond to requests from the master node; a slave node cannot initiate a
transmit request. This means that only one APC node on a panel link bus can transmit and receive
data directly to a AOS (advanced operator station) or to a remote I/O unit. If more than one APC is
connected to a panel link bus then all slave nodes must communicate to AOS and remote I/O units
via application programming in the master APC.
A node is designated as a master node by setting the PAN00 database element parameter NODENO
to 0 and setting the PANTRA function block parameter MASTER to1. If MASTER is set (to 1) then
the STATION input parameter is set to the node number of the transmitting slave. If MASTER is
reset (to 0) then the STATION input parameter must be set to the same value as defined by the
parameter NODENO of the database element PAN00.
Each slave device must have a unique node number (1 to 15). The node number of remote I/O is set
via a hardware switch.
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Message Identification
Identical STATION, IDENT, and DEVICE numbers must be used by the receiving and transmitting
function block elements between a master and slave node. The function block pairs must also have the
same call parameter definition. The combination of STATION, IDENT, and DEVICE must be unique
within each node.
IDENT and DEVICE numbers for remote I/O and AOS units are defined in their respective manuals.
Fault Handling
The error output is set when the link responds incorrectly. If there is a fault creating the transmit and
receive buffer description, the RESET input must be set (to 1) before a retry is made. If there is a
time-out longer than 30 executions of the function block, then the ERROR output is set. The ERROR
output is reset (to 0) after the first successful response from the sending node.
The RDY output is set after each successful transmission and reset after every poll that does not result
in a succesful acknowledgment.
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Parameter PAR
Summary
The PAR element allows the Drive Tool and FBs to change the parameter PAR (C1)
1 > SET
value. The new parameter value is stored in the Flash PROM and along with
2 I STAT 11
the application program backup is preserved during the system "Power
3 DEF O 12
down". Call parameter C1 defines the datatype of the parameter.
4 NAME ERRC 99
5 MIN
6 MAX
7 UNIT
Call PAR (C1) Table 1 PAR
Connections Table 2
1 SET IB Rising edge SETs value in input I to output O and

saves it also to FPROM if saving is allowed
2 I IC1 Input value to be set
3 DEF IC1 Parameter DEFault value
4 NAME IA20 Input array for parameter NAME 0 to20 characters
5 MIN IC1 MINimum value of the parameter
6 MAX IC1 MAXimum value of the parameter
7 UNIT IA6 6 character input array for parameter UNIT
11 STAT OI STATus of the parameter and FB *see table 4
12 O OC1 Output value of the parameter
99 ERRC OI ERRor Code *see table 3
Function
The PAR element holds the value for the parameter which is identified by a call parameter "C1" and
the "NAME" input. The output "O" shows the actual value of the parameter. Initially when the PAR
function block is loaded for the first time, the output value is set to the value of the "DEF" input. The
"DEF" input should be assigned a constant value. The value of the parameter can be modified by the
Drive Tool and the function blocks. A new parameter value is put into the output and if the function
block has the permission to do saving to FPROM and the application program saved in FPROM
equals the one that is running, it is also saved into FPROM. The parameter function block gets a new
permission to do saving once in a minute and it can have most three of them. Purpose of the method
to use saving permissions protects the FPROM from wearing out. When the application program is
backed up in the Flash PROM (by a "SAVE to FPROM" procedure) each valid change to a parameter
value is automatically saved in the FPROM. During the system "Power up" it is the value stored in the
FPROM that is first transferred to the output "O". After that it is again available for modification.
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Error Codes Table 3
23301 Too high writing frequency.

23302 FPROM writing is occupied - timeout.
23303 FPROM writing timeout.
23304 FPROM writing error.
23305 Previous FPROM writing is not ready, duplicate writing.
23308 Input out of limits during set-action.
23309 Limit error during set -action, max < min.
Status Output Table 4
Output Description
Bit 0 is ’1’ Parameter value in output is saved into FPROM.

Bit 1 is ’1’ SET is done.
Bit 2 is ’1’ Saving in FPROM
Bit 15 is ’1’ Error
Note: APC version prior 1.0/8 don’t have "SET" and "I" inputs, they have "ERR" (B) instead of the
"STAT" output and pin numbering of other pins except "ERRC" have been changed. APC version
prior and 1.0/8 inputs " MIN" and "MAX" are not used.
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Program Header PCPGM

Summary
The program header PCPGM is used for the structuring and execution PCPGM (C1, C2)
control of the application program of a PC system. 1 ON
2 R RUN 5
Call PCPGM (C1, C2) PCPGM
C1 Cyclicity in ms Allowed values are between 2 ms and

20000 ms in steps of 2 ms.
C2 Place in the cycle time 1 to 251: place in the cycle time table, cyclic
table and/or scheduling activation
strategy
252: activation at initalization after power
down.
Connections Table 1
1 ON IB Control input which is to be set (to 1)

with normal execution.
2 R IB Reset. Clears the execution units of the
PC program.
5 RUN OB RUN indicates that the execution units in the
PC program may be executed.
Function
A PC program is the highest level in the PC program structure. The program is intended to perform a
complete control function. The program header PCPGM is used to control the enabling, disabling and
resetting of the complete PC program, irrespective of subordinate execution units. The call parameter
C1 specifies how often the program header is to be executed. The call parameter C2 is used to specify
the position in the cycle time table which determines the execution order of the execution units with
the same cycle time.
The program header cannot have directly subordinate elements. The control inputs ON and R are used
to control when and how the complete PC program with subordinate execution units is to be executed.
PCPGM itself is always executed, irrespective of the inputs ON and R.
Normal Execution
The input ON must be set (to 1) for the normal execution of subordinate execution units to be
possible. At the start of the execution of subordinate execution units a check is performed to ensure
that the program header has RUN status.
Clearing
If the input R is set, the complete PC program is executed in reset mode. Input R overrides input ON.
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RUN
Output RUN is set only if normal execution is permitted, i.e. if the ON input is set and the R input is
reset (to 0).
1 ON RUN 5
&
2 R
Supervisory control
of execution units
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PDP-Function PDP
Summary
PDP (Proportional Derivating Proportional regulator) is used to PDP
1 I O 10
give proportional effect and limited derivation effect. The output O = HL
2 K 11
signal can be limited with limit values specified at special inputs. O = LL
3 T1 12
The balancing function permits the output signal to track an 4 T2 13
ERR
external reference and permits a bumpless return to the normal 5 BAL
function. All transfers from balancing or from limited output signal 6 BALREF
are bumpless. 7 OHL
8 OLL
t
Call PDP
Figure 1. PC Element PDP
Connections Table 1

3 T1 ITR Time 1. Input for time constant for lead.
4 T2 ITR Time 2. Input for time constant for lag.
6 BALREF IR BALance REFerence. Input for reference value when tracking.
7 OHL IR Output Hig Limit. Input for upper limit value.
11 O = HL OB Output = High Limit. Output which is set to 1 if the output O reaches
the upper limit value.
12 O = LL OB Output = Low Limit. Output which is set to 1 if the output O reaches
the lower limit value.
13 ERR OB ERRor. Output which is set to 1 if OHL is less than OLL.
T1 IgIGI
K
T2
IgK
t Igω
T2 1 1
Figure 2. Step response T1 T2
Function G
The step response for a PDP function is: -90
O(t) = I(t)(K + k1e -t∫T2 ) where
k1 = K(T1/T2-1) Ig ω
The transfer function for a PDP function is: Figure 3. Bode diagram
G(s) = K(1 +sT1)/(1 +sT2) where
T2<T1
This has been implemented in the PDP element as a recursive algorithm. The design of this algorithm
is such that normal functioning is maintained even during limiting. This ensures a controlled return
to a dynamic state.
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Gain, Time Constants and Sampling Time

Certain constants are precalculated to make the execution time of
the element as short as possible. The results are stored internally in
the element. These constants are recalculated if T1, T2 or K are OHL
changed by more than 1/128 of their previous value, or if the
sampling time TS is changed. When recalculating, a test is t
performed to check whether T1 and T2 > 2 x TS. If not, T1 or T2 Figure 4. Function in limiting
respectively is set equal to 2 x TS. state
Tracking
If BAL is set to 1, the regulator immediately goes into tracking and the output O is set to value of the
input BALREF. If the value at BALREF exceeds the output signal limits, the output is set to the limit
value. Return to dynamic state is bumpless.
Limitation Function
The limitation function limits the output signal to the limit values at the inputs OHL for the upper
limit and OLL for the lower limit. If the actual value exceeds the upper limit, the output O = HL is set
to 1. If it falls below the lower limit, the output O = LL is set to 1. The element checks that the upper
limit value OHL is greater than the lower limit value OLL. If not, the output ERR is set to 1. While
the error status persists, the outputs O = HL, O = LL and O retain the value they had in the sample
before the error occurred. After an error, the return to a dynamic state is bumpless, as in the case of
tracking.
7 OHL
8 OLL
ACT
O 10
5 BAL
ACT
6 BALREF
I1 O =HL 11
I1 > I2
1 I I2
PDP I1 O = LL 12
2 K I1 < I2
3 TD I2
4 TF I1 ERR 13
I1 < I2
t I2
1 PRESET
ACT
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PI-Function PI
Summary
PI (Proportional Integrating regulator) is used as a standard PI- PI
F1 REVACT O 10
regulator for serial compensation in feed back systems. The control O = HL
1 REFV 11
deviation is calculated internally in the element. The output signal O = LL
2 I 12
can be limited to limits specified at special inputs. The balancing 3 K 13
ERR
function permits the output signal to track an external reference 4 TI DEV 14
and permits a bumpless return to normal function. All transfers 5 RINT
from balancing limited output signal are bumpless. 6 BAL
7 BALREF
8 OHL
t
9 OLL
Call PI Figure 1. PC Element PI
Connections Table 1
FI REVACT IB REVerse ACTion. Parameter input for inverted control

action. REVACT = 1 gives inverted control action.
1 REFV IR REFerence Value. Input for desired value.
4 TI ITR Time Integration. Input for time constant for integration.
5 RINT IB Reset INTegrator. Input for clearing integrator.
tracking.
8 OHL IR Output High Limit. Input for upper limit.
9 OLL IR Output Low Limit. Input for lower limit.
10 O OR Output signal.
11 O = HL OB Output = High Limit. Output which is set to 1 if the output O
reaches the upper limit value.
12 O = LL OB Output = Low Limit. Output which is set to 1 if the output
reaches the lower limit value.
13 ERR OB ERRor. Output set to 1 if OHL is less than OLL.
14 DEV OR DEViation. Output for control deviations, i.e. DEV = 1-
REFV.
Function
Control Deviation
DEV, the control deviation, is calculated as follows even when the regulator is tracking: DEV = 1-
REFV.
Inverted Control Effect

REVACT is a function parameter which controls the direction of the 2K
output signal change in relation to the actual value. If REVACT is set
K
to 0, direct action occurs, i.e. increasing actual value gives increasing
output signal. When REVACT is set to 1, inverted action occurs, i.e. t
increasing actual value gives decreasing output signal. T1
Figure 2. Step Response
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Transfer Function
The PI function can be written in the time plane as
O(t) = K(DEV(t) + ∫tDEV(τ)/TI d τ)
Its main property when controlling is that it permits the integral section to retain its value when the
error DEV(t) = 0, i.e. the output signal is then constant.
The transfer function for a PI function is:
G(s) = K(1 + 1/sTI)
This has been implemented in the PI element as a recursive
algorithm. IgIGI
Gain, Integration Time Constant and Sampling IgK

Time
The constant K x TS/TI is precalculated to make the execution time Igω
of the element as short as possible. The result is stored internally in 1
the element. This constant is recalculated if TI or K is changed T1
more than 1/128 of the preceding value or if the sampling time TS G
is changed. When the value is recalculated, a test is performed to Ig ω
ensure that TS/TI < 1. If not, TS/TI is set to 1. 45
Clearing of Integrator -90

The integration section of the algorithm is cleared when RINT goes Figure 3. Bode Diagram
to 1. If the proportional section of the algorithm exceeds the limits
of the output signal, the limit status remains and the internal status is updated in accordance with the
section "Bumpless transfer from tracking or limitation". When RINT is set permanently to 1, the
element functions as a P-regulator.
Tracking
If BAL is set to 1, the regulator immediately goes into tracking and the output O follows the value of
the input BALREF. If the value at BALREF exceeds the output signal limits, the output is set to the
applicable limit value. On return to a normal function the value to the output O during the last sample
in tracking remains during one sample time. See below under "Bumpless transfer from tracking or
limiting".
Limitation Function
value and OLL for the lower limit value. If the actual value exceeds the upper limit value, the output
O = HL is set to 1. If it falls below the lower limit value, the output O = LL is set to 1. The element
checks that the upper limit value OHL is greater than the lower limit value OLL. If not, the output
ERR is set to 1. While the error status persists, the outputs O = HL. O = LL and O retain the values
they had in the sample before the error occurred.
Bumpless Transfer from Following or Limitation

Transfer from following status (BAL = 1) or from a limited output signals is bumpless. This is
performed by recalculation of internal states, i.e. the integration part according to INT(t) = O(t) - K x
DEV(t).
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8 OHL
9 OLL
ACT
O 10
6 BAL
ACT
7 BALREF
I1 O = HL 11
I1 > I2
F1 REVACT I2
ACT + I1 O = LL 12
1 REFV P I1 < I2
+ I2
2 I
I1 ERR 13
3 K t I I1 < I2
I2
4 TI t Limiting
5 RINT 1
ACT
Reset
Preset
Algorit hm
DEV 14
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PII regulator PII

Summary
PII (Proportional Integrating regulator with Integer calculation) is used
as a PI-regulator for serial compensation in the closed loop control
system where the 16 bit integer representation of the parameters and
signals is sufficient. Control deviation is an input signal to the
controller. The output signal can be limited to limits specified by input
parameters. The Tracking function forces the output signal to follow an
external reference. The transfers from Tracking to normal function with
PI algorithm is bumpless.
Integer calculation inside the element is done with 32 bit resolution
(using long Integers) to assure the adequate regulation accurancy. Figure 1. PC Element PII
Call PII
Connections Table 1
2 I II Input deviation -32767 to +32767

3 KI II Proportional gain 0 to +32767 (%)
4 TI II Time Integration Constant 0 to+32767 (ms)
5 RESET IB RESET the regulator outputs OPI and O to
"0"
6 BAL IB BALance. Forcing the output OPI to follow
the input reference BALREF
7 BALREF II BALance REFerence input 32767 to +32767
8 OHL II Output High Limit. -32767 to +32767
9 OLL II Output Low Limit. -32767 to +32767
10 O OI Regulator output signal -32767 to +32767
11 O=OHL OB Output signal on High Limit
12 O=OLL OB Output signal on Low Limit
13 ERR OB ERRor. OHL is less than OLL.
14 OPI OI Output of PI controller before limits. -32767 to +32767
Gain and Integration Time Constant calibration

The calibration of the Proportional Gain KI is in "%". It means that value KI = 100 corresponds to a
multiplication factor of 1.0 (100%).
The calibration of the Integration Time Constant TI is directly in milliseconds .
Transfer Function
P and I parts of the controller are calculated independently.
The PI function can be written in the time plane as : 2K
t K
O(t) = KI ∗[ I(t)+∫(1/TI) ∗I(t)∗dt] t
0 T1
Figure 2. Step response
The transfer function of the PI function is:
G(s) = KI∗[1+1/(s∗TI)]
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3AFY61281240
This has been implemented in the PII element with a recursive IgIGI
algorithm . The basic form of this algorithm is:
IgK
1. INT(k)=INT(k-1) + KI∗I(k)∗TS/TI
2. O(k)=KI ∗I(k) +INT(k) Igω
1
where : TS is an execution interval of the controller. T1
INT is the integral component G
Ig ω
45
-90
Clearing the requlator output
When the RESET input signal is set to 1 he output of controller is reset to 0 if. The Integrator part of
regulator can be cleared by setting input TI to 0. When TI is set again to value other than 0 is transfer
bumpless.
Limitation function
The OLL and OHL inputs provide the minimum and maximum limit values for the controller output
signal. If the actual value exceeds the maximum limit value, then output "O=HL" is set to 1 and if it
falls below the minimum limit value,then output "O=LL" is set to 1. The Element also compares OHL
with OLL. If OLL value is greater then OHL then the ERR output is set to 1. While the error status
persists, the output limits "O=HL", "O=LL" retain the previously accepted values .
Tracking
When BAL input is set to "1" the regulator "O" output is forced to follow the REFerence value from
the BALREF input. If the BALREF signal exceeds the output limits, the output is set to the applicable
limit value.
Bumpless transfer between Tracking and normal mode

The transfer from Tracking mode is bumpless. This is achieved by internal recalculation of the
integration part in the tracking mode according to:
INT(k) = O(k)- KI∗I(k)
There is no explicit feature in the regulator to support directly the bumpless transfer to the tracking
mode. However such function can be easily implemented, by using the external FB (like e.g. RAMP
element) to back feed the "O "output of the controller to its BALREF input.
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224
3AFY61281240
Ramp Generator RAMP

Summary
RAMP (RAMP generator) is used to limit the rate of change of a RAMP
1 I O 10
signal. The output signal can be limited with limit values specified at 2 STEP+ 0 = HL 11
special inputs. The balancing function permits the output signal to 3 STEP- O = LL 12
track an external reference. 4 SLOPE+ ERR 13
5 SLOPE-
6 BAL
7 BALREF
8 OHL
Call RAMP 9 OLL t
Figure 1. PC Element RAMP

Connections Table 1
1 I IR Input. Input for the start value.

2 STEP+ IR The greatest allowed positive step change.
3 STEP- IR The greatest allowed negative step change.
4 SLOPE+ IR Positive ramp for the output.
5 SLOPE- IR Negative ramp for the output.
7 BALREF IR BALance REFerence. Input for reference value when tracking.
8 OHL IR Output High Limit. Input for upper limit value.
11 O = HL OB Output = High Limit. Output which is set to 1 if the output O reaches
the upper limit value.
12 O = LL OB Output = Low Limit. Output which is set to 1 if the output O reaches
the lower limit value.
13 ERR OB ERRor. Output set to 1 if OHL is less than OLL.
Function
The main property of a RAMP function is that the output signal tracks the input signal while the input
signal is not changed more that the value specified at the step inputs. If the input signal change is
greater than the specified step changes, the output signal is first changed by STEP + STEP -
depending on the direction of change, and then by SLOP + or SLOP -per second, until the values at
the input and output are equal. This means that if STEP- = STEP+ = 0, a pure RAMP i.e. SLOPE/sec.
is obtained at the output. The greatest step change allowed at the output O is specified by the
parameters STEP + and STEP - for the respective direction of change. The ramp which the output
signal is to track is the change at to input I exceeds STEP+ or STEP- is specified by the inputs
SLOPE+ and SLOPE-. All parameters are specified as absolute values with the same units as input I.
The values of the parameters are stored internally in the element. New values are only entered under
stationary conditions, i.e. when I(t) = O(t). Certain constants are recalculated to make the execution
time of the element as short as possible. The result are stored internally in the element. These
constants are recalculated if SLOPE or SLOPE- are changed by more than 1/128 part of their previous
values or if the sampling time TS is changed. Figure 100 shows the relationship between input, output
and internal auxiliary variables when the element functions normally.
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3AFY61281240
Calculation of Output Signal

When calculating output signal o three cases must be distinguished:
- I(t) = O(t -TS)
results in O(t) = I(t)
- I(t) < O(t - TS)
results in calculation of the value of the output in accordance with:
O(t) = min(I(t) and (Step + POs(t - TS) +SLOPE+ x TS), i.e.the least of the values of I(t)
and (Step+ + VPOS(t -TS) + SLOPE- x TS)
- I(t) > O(t - TS)

results in calculation of the value of the output in accordance with:
O(t) = max(I(t), STEP- -VNEG(t - TS) -SLOPE- x TS)
VPOS and VNEG are auxiliary variables with positive and negative steps respectively. These are
calculated in all cases according to:
VPOS(t) = min(O(t), VPOS(t - TS) + SLOPE+ x TS)
VNEG(t) = min(O(t), VNEG(t - TS) - SLOPE- x TS)
If a new step with the same direction of change appears at the input before the internal auxiliary
signal has been updated, the step part of the output signal is reduced. A step with the opposite
derivative, however, takes full effect. This is because the auxiliary variable for the opposite direction
always has been updated to O(t).
Tracking
If BAL is set to 1, the filter immediately goes into tracking and the output O is set to the value of the
input BALREF. If the value at BALREF exceeds the output signal limits, the output is set to the
applicable limit value. During following VPOS(t) = VNEG(t) = O(t) = BALREF(t). Return to normal
function is done as if a unit step had occurred on the input.
Limitation Function
and OLL for the lower limit. If the actual value exceeds the upper limit, the output O = HL is set to 1.
If it falls below the lower limit, the output O = LL is set to 1. In the limiting state VPOS(t), VNEG(t)
and O(t) are set to the applicable limit value. The element checks that the upper limit value OHL is
greater than the lower limit value OLL. If not, the output ERR is set to 1. While the error status
persists, the outputs O = HL, O = LL and O retain the values they had in the sample before the error
occurred.
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3AFY61281240
8 OHL
9 OLL
ACT
O 10
7 BAL
ACT
6 BALREF
I1 O =HL 11
I1 > I2
I2
I1 O = LI 12
I1 < I2
I2
I1 ERR 13
I1 < I2
I2
1 I
2 STEP+
SLOPE+
3 STEP-
1 sec
4 SLOPE+ STEP+
5 SLOPE- t
STEP-
1 sec
SLOPE-
VNEG(t)=O(t)
STEP-
I(t) SLOPE- x TS
SLOPE+ x TS
VNEG(t)
STEP+
O(t)
O(t)
I(t)
VPOS(t)=O(t)
SLOPE+ x TS
O(t)
VPOS(t)
I (t)<STEP-
STEP+
TS
Figure 3. Relation between input, output and auxiliary variables under
mormal conditions
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S-RAMP Generator RAMP-S1

Summary
RAMP-S1 (S-RAMP reference generator ) element provides the signal RAMP-S1
ramp function with the first and second derivative values limitation. 1 I ERR 21
Typically used as a speed reference ramp to generate the output (speed 2 MAXSLOPE O 22
reference) signal with smooth "rounded" transitions. Recommended 3 TMESTRTS DIFF 23
whenever the acceleration (torque) rate of change has to be limited. 4 TMEENDS DVDT 24
5 ENDSLIM START 25
6 BALREF ENDSEC 26
7 BAL
8 HOLD
9 HOLDS
10 HYST
11 OHL
Call RAMP-S1 12 OLL
RAMP-S1
Connections Table 1
1 I IR Input signal
2 MAXSLOPE IR MAXimum SLOPE. Maximum absolute value of signal
acceleration in "signal Units" /seconds (e.g. in m/s/s). Value "0"
connected to this input is internally substituted by the very small
nonzero value.
3 TMESTRTS ITR TiME STaRTS. Time in seconds for the initial S-phase.
The time of second derivative ( = acceleration) absolute value
transition from zero to the MAXSLOPE value.
4 TMEENDS ITR TiME ENDS. Time in seconds for the end S-phase.
The time of second derivative ( = acceleration) absolute value
transition from the MAXSLOPE value to zero.
5 ENDSLIM IR ENDS LIMit. Limit that determines the characteristics of the S-
ramp in the end phase in terms of the under/overshoot.
6 BALREF IR BALance REFerence. Input for reference value for tracking mode.
7 BAL IB BALance. Forcing the tracking mode in which the Output "O"
value follows the BALREF input value.
8 HOLD IB HOLD. Instantaneous freezing of the output "O" value.
Ramping stopped.
9 HOLDS IB HOLD with S function. Forced termination of the ramping
concluded with the end S-phase.
10 HYST IR HYSTeresis. The Hysteresis for the stationary state of the ramp.
The Ramp function is not activated as long as the "DIFF" output
value is within the Hysteresis value.
11 OHL IR Output High Limit. Affects the "I", "O" and "BALREF " signals.
12 OLL IR Output Low Limit. Affects the "I","O" and "BALREF " signals.
21 ERR OB ERRor. Set to "1" when the OHL ≤ OLL.
22 O OR S-Ramp Generator Output signal.
23 DIFF OR The DIFFerence between the input "I" and output "O" signals.
24 DVDT OR DVDT. The actual value of the output signal first derivative*TS.
(The step of the S-Ramp output per execution cycle ! )
25 START OB START. Indication that the Ramp function is activated.
26 ENDSEC OB END SECtor. Indication of the active end S-phase of the ramp.
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3AFY61281240
Function
The S-ramp function is activated when the absolute value of the "DIFF " is greater then the absolute
value of the "HYST". The second derivative of the signal (or in other words the first derivatives rate
of change) is calculated from the parameter "TMSTRTS" and is constant until the end S-phase is
entered. The calculated second derivative is integrated (accumulated) to a first derivative (DVDT)
which is limited by a parameter MAXSLOPE. DVDT is then integrated (accumulated) to the output
signal "O".
When the S-Ramp is activated, the element continuously recalculates the conditions that determine
switching to the end S-phase. During the end S-phase the second derivative is calculated continuously
to assure a correct ending of the ramp. The calculated second derivative is limited in this phase by the
"ENDSLIM" input parameter value. The output of the S-ramp may be overshooting or undershooting
the input "I" setpoint value based on the applied to "ENDSLIM" input limit function. Normally when
no over- or undershoot is required the "ENSDSLIM" should be connected to the "DVDT" output.
While the end S-phase is in progress the operation is unaffected by the changes on the "MAXSLOPE"
and "TMEENDS". The Ramp can force the end S-phase also if the output "O" is calculated to go over
one of the specified limit values "OHL" or "OLL".
The "HOLD" input overrides the normal ramp operation and freezes the value of the output "O"
signal. The "HOLDS" input overrides the" normal ramping" by forcing the end S-phase. The
overriding does not disturb the end S-phase that had been already in progress when "HOLDS" input
became active.
With the "BAL" input set to "1" the output signal "O" is immediately forced to follow the signal value
from the "BALREF" input. In that case the "DVDT", "DIFF", "START" and "ENDSEC" outputs are
all set to "0" and the Hold and Hold_S functions blocked. The value of "BAL" returning to "0" state
reactivates the normal ramp function.
"I" (Input signal)
"BAL" = "HOLD" = "HOLDS" = 0

"O" (Output signal)
"TMEENDS" "TMEENDS"
"TMESTRTS" "TMESTRTS"
"DVDT" "MAXSLOPE"TS"
"MAXSLOPE"TS"
Figure 2. Basic operation of the RAMP-S reference generator
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3AFY61281240
"I"(Input signal)
"O"(Output signal)
"BALREF"
"DV/DT"
"HOLD" t
"HOLD" t
"BAL" t
Figure 3. Effect of the forcing signals on the operation of the RAMP-S generator.
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3AFY61281240
S-Ramp generator RAMP-SSH

Summary
The PC-element RAMP-SSH generates a s-shaped output signal when RAMP-SSH
reaching the level of the input signal. 1 I O 21
2 OHL DVDT 22
3 IOLL ERR 23
4 MAXSLP ENDSPH 24
5 STME
6 MAXSLPF
7 STMEF
8 MAXSLPE
9 STMEE
10 HOLD
11 HOLDS
12 FASTSTOP
13 EMSTOP
14 BAL
Call RAMP-SSH 15 BALREF
Connections Table 1 Figure 1. PC Element

RAMP-SSH
1 I IR Input. Input for the start value concerned.

2 OHL IR Output High Limit. Input for upper high limit.
3 OLL IR Output Low Limit. Input for lower high limit.
4 MAXSLP IR MAXimun SLoPe. Maximum acceleration in the linear phase of the
ramp, at normal run.
5 STME ITR S-TiME. S-time for normal run.
6 MAXSLPE IR MAXimum SLoPe Emergency stop.Maximum acceleration in the
linear phase of the ramp, at faststop.
7 STMEF ITR S-TiME Faststop. S-time for faststop.
8 MAXSLPE IR MAXimum SLoPe Emergency stop. Maximum acceleration in the
linear phase of the ramp, at emergency stop.
9 STMEE ITR S-TiME Emergency. S-time for emergency stop.
10 HOLD IB HOLD. Instantaneous stop of the ramp.
11 HOLDS IB HOLD with S. Stop of the ramp with a s-phase.
12 FASTSTOP IB FASTSTOP. Faststop of the ramp.
13 EMSTOP IB EMergency STOP. Emergency stop of the ramp.
14 BAL IB BALance. Input for activating following.
15 BALREF IR BALanc REFerence. Input for reference value when following.
22 DVDT OR DVDT, (dV/dt) / (cycle time).
23 ERR OB ERRor. Error signal which is set at error conditions.
24 ENDSPH OB END-S PHase. Signal which indicate end -s phase of the ramp
function.
Data
Execution time, max. 1.0 ms
Memory requirement object code
PC statement 68 bytes
Local data area 54 bytes
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3AFY61281240
Function
The s-ramp generator has faciliti es such as:
- operates with both positive and negative reference signals.
- orders for forced breaking adown to zero of the output signal.
- forcel setting if the end-s when the input signal is exceeding the limits.
- adaption of d2V/dt2 in the end s-phase to reduce no of overshoots.
- following of a reference without any s-ramp function. Bump less transition when
switching between input references I and BALREF.
The s-ramp generator is activated when the input signal I ∩ output signal ∩. The ramp starts with the
starts-s phase continues with the linear phase and finish with the end -s phase, in the end -s phase is
the output signal ENDSPH set to true. Depending on the size of the difference of I and O the linear
phase is not always executed.
HOLD and HOLDS is used to stop the s-ramp generator. HOLD stope the s-ramp momentarily
without any s-function and HOLDS stops the s-ramp with a s-function.
FASTSTOP and EMSTOP are conditions to break down the output signal O to zero. When
FASTSTOP or EMSTOP order is released, the s-ramp generator is activated again. The EMSTOP
order has higher priority than FASTSTOP.
When the input BAL is set to true the s -ramp generator is activated until the output signal O has
reached the level of the input signal BALREF. Then the output signal is following BALREF. The
s-ramp generator is activated when BAL is set to false. It is recommended that the function which
generate the BALREF input signal is executed with the same cyclicity as RAMP-SSH.
When the s-ramp generator is activated to reach the level of the BALREF reference, it is
recommended that the parameter STME is set to a minimum value and the parameter MAXSLP is set
to a maximum value.
O I BALREF
OHL
OLL
DVDT
ENDSPH
HOLD
HOLDS
FASTSTOP
EMSTOP
BAL
Figure 2. Timing diagram of the ramp function at HOLD and HOLDS order.
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3AFY61281240
O I BALREF
OHL
OLL
DVDT
ENDSPH
HOLD
HOLDS
FASTSTOP
EMSTOP
BAL
Figure 3. Timing diagram of the ramp function at FASTSTOP, EMSTOP and BAL
order.
233
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Register REG
Summary
Register REG (REGister) is used as a memory REG
element with up to 35 positions. The value of the (C1,C2)
1 S
data can be integer, real number, Boolean or time.
2 >L
3 R
11 I1 01 12
13 I2 02 14
9 + 2 x C2 IC2 OC2 10 + 2 x C2
Call REG (C1, C2)
Figure 1. PC Element REG

C2 Number of positions 1 to 35
Connections Table 1
1 S IB Set. Input for loading new data each time the element is executed
When S is set to 0, the last data loaded remains.
2 L IB Load. Dynamic input for loading data to the register. Loading is
permomed when L goes 1.
3 R IB Reset. Input for clearing the register R prevents all further entry
while is 1.
11 I1 IC1 Input 1. Input data to position 1.
12 O1 OC1 Output 1. Output data from position 1.
13 12 IC1 Input 2. Input data to position 2.
14 O2 OC1 Output 2. Output data from position 2.
.
.
.
9+2xC2 IC2 IC1 Input C2. Input data to position C2.
10+2xC2 OC2 OC1 Output C2. Output data from position C2.
Function
When input L becomes 1, the register is loaded with data from inputs I1 to IC2. Data previously in the
register is replaced. If input S is set, loading is performed as above each time the register is executed.
When S is reset after having been set, the data most recently loaded remains until the element is
executed again, with input S, L or R set. Input S overrides L so that when input S is set, L has no
effect.
Clearing
When input R is set, the register is cleared and all further entry is prevented. R overrides both S and
L.
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3AFY61281240
REG
11 I1 O1 12
I1 O1
1 S
L 1
2 L 1
> 1 R
13 I2 O2 14
I2 O2
L 2
R
9 + 2 x C2 IC2 OC2 10 + 2 x C2
IC2 OC2
L C2
3 R
R
235
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Group Data Register REG-G

Summary
REG-G (REGister-Group data) is used to assemble individual REG-G
(C1,C2,C3,
variables to a single variable of group type. The data type can be C4,C5)
integer, real number, Boolean or time. 1 S AERR 7
2 >L
3 > WR
4 AWR
5 R
6 EXP
11 I1 O 50
12 I2
10 + C2 IC2
Call REG-G (C1,C2,C3,C4,C5) Figure 1. PC Element REG-G

C3 Selection of expander input EXP 0 to 1
C4 Number of places in group data for expander 0 to 254
input EXP
C5 Number of places in group data for the output O 0 to 255
C3+C4=C4
C2+C4=C5
Connections Table 1
1 S IB Set. Input for loading new data each time the element is executed.
The latest loaded data remains when S is reset.
2 L IB Load. Dynamic input for loading data to the register. Loading is
performed when L goes to 1.
3 WR IB WRite. Dynamic input for changing data at the place specified by
AWR.
4 AWR II Address WRite. Input for address to the data to be changed
according to WR
5 R IB Reset. Input for clearing the register. R prevents all further entry
while at 1.
6 EXP IGC4C1 EXPander input. Input for group data to be linked with data at
inputs I1 to IC2.
7 AERR OB Address ERRor. Output which is set (to 1) if the address at AWR
is greater than the number of inputs or is negative.
11 I1 IC1 Input 1. Input data position 1.
12 I2 IC1 Input 2. Input data position 2.
.
.
.
10+C2 IC2 IC1 Input C2. Input data to position C2.
50 O OGC5C1 Output. Output for group data.
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3AFY61281240
Function
REG-G combines individual variables of the same data type into a single group variable. The element
has an expander input EXP for a group variable which can be used when more than 30 variables are
to be linked together. Input S overrides L so that when input S is set, L has no effect.
Normal Assembly
When input S is set, data is continuously assembled at the group variable of the output. The group
variable of the output consists firstly of group data from the input EXP, and then of the values form
the inputs I1..IC2. The element acts as a latch when the input S is reset, the latest data assembled then
remains at the output.
Loading
If input L goes from 0 to 1, an assembly is performed to output O during this program cycle, as during
normal assembly.
Changing of Data at an Optional Place.

One of the ordinary data inputs I1 to IC2 is used for changing data at a specified place in REG-G.
The address (integer 1 to C2) of the place at which data is to be changed is started at the input AWR.
The new data value is entered from the input to the specified place when the input WR goes to 1. If
AWR = 0 and the input WR goes to 1, group data is read from the input EXP to their different places.
Places which correspond to ordinary inputs are not affected.
Clearing
When input R is set, data at all places in the group register are cleared and all further entry is
prevented. R overrides both S and L.
Supervision
The address at the input AWR is checked and its value is greater than the number of inputs or
negative, the error signal output AERR is set. When an error is detected, AERR is set during one
cycle if input WR is set. No place in the register is affected when an error occurs.
REG-G REG
1
1 S
C 1
2 L 1
> 1 R
6 EXP
2
C 2
R
C4
C 3
R
11 I1
I1 O 50
C I1
1
R
12 I2
I2
C I2
1
R
ICR
IC2
10 + C2
C IC2
1
R
5 R
0 1
3 WR 2
> 1
C2
A > C2
4 AWR AERR 7
or
&
A<0
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Memory Monitoring RWM

Summary
RWM (Read-Write Memory monitoring) fetches information about the RWM
APC memory usage. It is used to reveal memory overrun situations before 1 SEL SIZE 11
they occur. AFREE 12
MFREE 13
SQSTAT 14
SYSRWM 20
Call RWM
RWM
Connections Table 1
1 SEL II SELection of data to output terminal SIXE see table 2

11 SIZE OI SIZE of data selected by input (bytes) or
(fractions)
12 AFREE OI Size of the contiguous Area in memory that is (fractions)
FREE.
13 MFREE OI Total number of Memory fractions that is (fractions)
FREE.
14 SQSTAT OI Memory SQueeze (i.e. reorganising the 0: squeeze ready
memory to maximise the contiguous free area) <>0: squeeze
STATUS. requested or active
(internal squeeze
flags)
20 SYSRWM OIL Size of the free SYStem Read-Write Memory (bytes)
area for DB-elements.
Function
The function block fetches information about the usege of the APC memory. The value in output
terminal SIZE depends on the value connected to the input terminal SEL. Examples:
30 = size of task 3 (TADE+PODE+POLO)

152 = size of PODE of task 15
The other outputs are explained in Table 1.
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3AFY61281240
SEL values Table 2

SEL Value SIZE Value Means
-2 Size of the application memory [fractions]

-1 Size of a fraction [bytes]
0 Size of the largest task (TADE+PODE+POLO) [fractions]
XXY (>0) XX: Task number
Y: Domain:
0 = TADE+PODE+POLO
1 = TADE (TAask DEscription domain, size is one fraction)
2 = PODE (PrOgram DEscription domain, contains the function blocks)
3 = POLO (PrOgram LOcal data domain, contains the "signals")
Illegal -1
Memory Problems in APC

Overrun of the memory capacity in APC has caused problems in many projects. The overrun of the
memory capacity may unfortunately occur without any warning during commissioning when the
application program is modified on-line. APC system software release 1.0/9 includes on-line
supervision of free memory and better utilisation of available memory.
Memory Capacity of the APC

Application programs are stored in FPROM and they run in RWM. The size of RWM available for
application programs (target code) is:
APC system software releases È 1.0/8: 117kb divided in 114 fractions of 1024 bytes
APC system software release bytes 1.0/9: 115kb divided in 473 fractions of 256
Target code consists of domains. At least one memory fraction is allocated for each domain.
A task (CONTRM or MASTER) consists of three domains: TADE, PODE and POLO. When the
application program is modified on-line, two versions of the task domains (old and new) will
temporarily exist in the APC. During on-line change a temporary fourth domain PODC (Program
Change domain) is created.
If the on-line change is carried through successfully then the PODC domain and
TADE+PODE+POLO for the old task will be erased.
The total number of fractions needed for all domains including temporary domains, must never even
temporarily exceed the maximum number.
The maximum momentary size of the application program size is:
(Program size) + (for the largest task: TADE+PODE+POLO+PODC )
The reason for overrun of the memory capacity is often on-line change in a large task that is part of a
large application program.
Using RWM to avoid Overrun of Memory

The RWM function block monitors the amount of available RWM memory in the APC. RWM can be
inserted in any slow task. Observing the output terminals helps avoiding overrun of memory:
1) SIZE+PODC>MFREE: An on-line change will fail

2) SIZE+PODC<AFREE: An on-line change will succeed
3) SIZE+PODC>=AFREE if SIZE+PC<MFREE: An on-line change may succeed
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3AFY61281240
PODC means here the size of the temporary domain PODC. The size of a PODC is typically 20...50%
of the total size needed by the task. The size of a PODC can not be measured by the RWM function
block. Instead, it can be measured in PC by using a DOS utility program called DOMSZ, if the
application is programmed using the FCB.
Reduced memory fraction size

The memory fraction size has been reduced from 1024 bytes to 256 bytes in the APC system release
1.0/9. This will improve memory utilisation from 70...75% to 90...95% and allow about 12% larger
application programs.
Guide for using Function Block in the Graphical Application Designer

Note: In the GAD there are no on-line changes. It means that use of the function block in GAD
applications is marginal. The memory usage of an application is available in the compilation report
made by the Compiler.
Definable attributes : Task number / Execution order, Comment text (several languages),
General text (one language)
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Save parameter SAVE

Summary
SAVE parameter element is used to read and write reference or parameter SAVE (C1)
1 EN ERR 10
values to capacitor secured RWM. The data type is selected with a call
2 I O 11
parameter. ERRC
3 DEF 99
SAVE
Call SAVE (C1)
C1 Data type B, I, IL, R
Connections Table 2
1 EN IB ENable recording of present input value.

2 I IC1 Input value to be stored.
3 DEF IC1 DEFault output value in case of stored value is lost
and EN = 0.
10 ERR OB ERRor detection.
11 O OC1 Output value of parameter.
Error Codes Table 3
28019 Database element SAVE00 not defined.

28020 Saved values lost during power off period.
28021 Saved value not found (although other saved values are OK).
28022 All storage space used.
Function
The SAVE function block reads the value saved into the capacitor secured RWM to the output O if the
input EN is reset (to 0). If the input EN is set (to 1), it loads the input I to RWM and to the
output O.
The output ERR is set (to 1) if the database element SAVE00 has not been defined or the RWM has
changed during power down of the system. In the case of a memory change during power down, the
ERR can be reset (to 0) when the input EN is changed from 0 to 1. In the case of a lost value, default
value is written to the output O.
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Shift Register SHIFT

Summary
Shift register SHIFT is used as a shift register of up to 250 positions. Data SHIFT
can be integers, real numbers, Boolean or time. (C1,C2)
2 F/B-N
3 >C
4 R
11 IF OB 12
13 IB OF 14
Call SHIFT (C1, C2)
SHIFT
C1 Data type I,IL,R,B,T,TR

C2 Number of positions 2 to 250
Connections Table 1
2 F/B-N IB Forward/Backward-N. Input for selection of shift direction. Shifting is

forward when F/B-N=1 and backward when F/B-N=0.
3 C IB Control. Dynamic input for shifting.
4 R IB Reset. Input for clearing the shift register. All further shifting is
prevented when R=1.
11 IF IC1 Input Forward. Input data with forward shift.
12 OB OC1 Output Backward. Output data with backward shift.
13 IB IC1 Input Backward. Input data with backward shift.
14 OF OC1 Output Forward. Output data with forward shift.
Function
Forward Shift
When input C goes to 1 and the input F/B-N is 1, data is shifted forward in the register and data is
read into position 1 from input IF. Data which was located at output OF before the shifting, is
replaced at the shift forward by data at the next to last position.
Backward Shift
When input C goes to 1 and the input F/B-N is 0, data is shifted backwards in the register and data is
read into position C2 from input IB. Data which was located at output OB before the shifting, is
replaced at the shift backward by data from position 2.
Clearing
The input R clears the shift register and prevents all further reading into the shift register.
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3AFY61281240
2 F/B-N
FORWARD
&
BACKWARD
3 C &
> 1
11 IF OB 12
1 O
1
R
R 2 BACKWARD
FORWARD
13 IB OF 14
1 O
4 R C2
R
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Slave Header SLAVEM

Summary
SLAVEM (SLAVE Module) is used for execution control of a slave module.
SLAVEM (C1, C2)
Figure 1. PC
Call SLAVEM (C1, C2) Element SLAVEM
C1 Identity of execution controlling master The second part of the

header PC item designation of the master
header.
C2 Currently not used
Function
The slave header SLAVEM is an element header for a slave module. The numerical identity of the
master header associated with the slave module is specified with the call parameter C1. This becomes
the second part of the PC item designation of the master as this must always be at the level directly
subordinate to a program header. How often and in what order the slave module is to be executed in
relation to the other execution units is determined by the supervisory master header.
The slave modules within the same master are executed in the order of the documentation. Blocking
from service aids and PC programs is determined entirely by the master.
Reading variables
from the I/O devices,
common data areas
and other modules.
Normal execution of For all slave modules

elements. of the related Master.
Writing variables to
the I/O devices,
common data areas,
and other modules
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Speed and Position Measuring SPEEDP

Summary
SPEEDP (SPEED and Position measurement) element is used together SPEEDP (C1)
F1 BOARD ERR 10
with the pulse counter board YPH107 and YPH108 for fast and reliable
F2 INPMODE DIRCH 11
speed and position measurement. The element reads the contents of the F3 EDGEMODE
tacho pulse and time counters from the YPH107/YPH108 board and
calculates the actual speed and position. The speed reading can be 21 NBRPPR NFEEDB 31
22 N100 NNOFILT
internally scaled by the element. The position counter can be 32
23 NFILT
synchronised ( = pre-set with the PRECOUNT value) by the application 24 NSCALE
software or by the hardware. Various options for the tacho input types
41 INSIGN SYNCRDY 51
and counting methods can be selected with the input parameters. The PRECOUNT POSACT
42 52
calculation and presentation of the measurement results can be 43 PGMSYNC ERRC 99
performed using the selected data types: Integers, Long Integers or 44 SYNCCOND
Floating point. This allows the user to optimise the execution time of 45 HWSYNCIH
the element based on the application needs. 46 RSYNCRDY
47 SYNCFILT
Call SPEEDP (C1) Table 1 Figure 1. PC Element

SPEEDP
C1 Data type selection for the speed indication I = Integer

outputs
IL = Integer long
R = Floating point
Connections Table 2
F1 BOARD II I/O address of the pulse counter BOARD. *see Table 3

F2 INPMODE II INPut MODE. Configuration of channel inputs. *see Table 5
F3 EDGEMODE II EDGE MODE. Pulse reading mode. *see Table 4
10 ERR OB Hardware or input parameter ERRor.
11 DIRCH OB DIRection CHange after previous read.
21 NBRPPR II NumBeR of Pulses Per Revolution from one
channel of the pulse encoder.
22 N100 II Nominal rotational speed in RPM.
23 NFILT II Speed filtering Time constant [milliseconds]
24 NSCALE IC1 The value of output NNOFILT at the nominal
rotational speed.
31 NFEEDB OC1 Filtered speed.
32 NNOFILT OC1 Unfiltered speed.
41 INSIGN IB INvert SIGN of the position increment.
42 PRECOUNT IIL Initial (=PRECOUNTED) value loaded into
position counter when synchronisation is
activated.
43 PGMSYNC IB PROGram SYNChRonisation "0->1"=True
44 SYNCCOND II SYNChronisation CONDition select.
45 HWSYNCIH IB HardWare SYNChronization inhibition.
46 RSYNCRDY IB Reset SYNCRDY output.
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3AFY61281240
Table 2 continued
47 SYNCFILT IB Filter for external synchronising signal YPH107:

0 = 1 ms,
1 = 10 ms, YPH108: 0 = 100µS, 1 = 5 ms
51 SYNCRDY OB SYNChronization completed.
52 POSACT OIL Accumulated number of the pulses in the position
counter since the last synchronisation (including
PRECOUNT).
99 ERRC IO ERRor Code for the element *see Error
Codes
Configuration of the BOARD parameter
Parameter BOARD Table 3
Parameter Description
ADDR YPH107 is used ADDR is the actual I/O

ADDR+100 Channel 1 of YPH108 is used address of YPH107
ADDR+200 Channel 2 of YPH108 is used or YPH108 (0 to 15).
EXAMPLES:
BOARD = 5 YPH107 is used (I/O address 5)
BOARD = 101 Channel 1 of YPH108 is used (I/O address 1)
BOARD = 213 Channel 2 of YPH108 is used (I/O address 13)
Selection of the pulse counting mode

The value of the parameter EDGEMODE specifies how the pulses from the channel A and B are to be
used for the "speed" and "position" counting.
Parameter EDGEMODE Table 4
Parameter Description Number of total

transition count(EDGENR)
1 Count "0->1" signal transitions on channel A; 1
channel B for direction
2 Count all signal transitions on channel A; B 2
unused
3 Count all signal transitions on channel A channel 2
B for direction
4 Count all signal transitions on channels A and B 4
Configuration of the channel inputs.
Parameter INPMODE..Table 5
Parameter Description
0 Single ended inputs, normal A, B channel functions for counting.

1 Single ended inputs, the functions of channels A and B swapped for
counting.(YPH107 only)
2 Differential inputs, normal A, B channel functions for counting.
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3AFY61281240
Table 5 continued
3 Differential inputs, the functions of channel A and B swapped. (YPH107 only)
4 Same as mode 0 with edge vibration control*) in use. (YPH108 only)
6 Same as mode 2 with edge vibration control*) in use. (YPH108 only)
*) Edge vibration control eliminates edge vibrations of incoming pulses letting through only the first
edge. The use of edge vibration control is recommended (YPH108 only).
Function
Function parameter F1 is used to define hardware address of the YPH107/YPH108 pulse input board
and it must have the value defined in table 3.
The pulse inputs can be configured to use either differential or the single ended channel signals. The
resolution of the measurement for the given speed range can be optimised with the selection of the
appropriate number of pulse transitions to be used for counting. The input parameters "INPMODE"
and "EDGEMODE" are used to select the type of the pulse input and counting mode for the pulse
counter.
The measuring functions of the YPH107/YPH108 pulse input board are accomplished in a following
way:
The 16 bit up/down counter, called "PC", counts the selected (pulse transmitter) channel signal
transitions. The free running 16 bit counter, called "FTC", counts the "TCLK" time base clock.
The pulse time register "TC" is updated with the "FTC" value for every new pulse count of "PC".
At every execution of the SPEEDP element the contents of "PC","TC" and "FTC" are read. Those and
the previously read values are used by the SPEEDP element to calculate the position and the speed.
The calculation and presentation of the actual speed can be performed using different data types
specified by the "C1" function parameter. Significant reduction of the element execution time can be
achieved with the use of Integers or Long Integers instead of Floating point.
By using the proper combination of the "INPMODE" and "EDGEMODE" input parameters it is
possible to bypass some of the pulse tacho defects until the proper tacho unit replacement can take
place.
EXAMPLE: When a two (single ended) channel tacho is used and the EDGEMODE has value "4" it
means that both the negative and positive edges of channels A and B are counted. In the case of a
fault in reading channel A the EDGEMODE must be changed to 2 and INPMODE to 1, which means
that channels A and B are functionally swapped, the inputs are single ended and pulses from only
channel B are calculated.
In the case of a fault in reading channel B the EDGEMODE must be changed to 2 and INPMODE to
0, which means that channels the inputs are single ended and pulses from only channel A are
calculated.
Speed measurement
The actual speed is then calculated by the element according to the formula:
PC( new ) − PC( old )
NNOFILT = ∗ CONST
TC ( new ) − TC ( old )
where:
60∗ TCLK ∗ NSCALE
CONST =
NBPPR∗ EDGENR ∗ N 100
The "NSCALE" and "NBPPR" are read from the element corresponding inputs.
The "EDGENR" (counted edge numbers per pulse) depends on the "EDGEMODE" parameter
(see Table 3 ).
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3AFY61281240
The value of TCLK (time base clock) is internally selected based on the given execution interval (TS)
of the SPEEDP element to get the highest possible resolution for the time counting without the time
counter (TC) overrun.
At low speeds, when PC(new) = PC(old), the speed is estimated with the formula:
1
NNOFILT = ∗ CONST
TC ( sample ) − TC ( old )
Position Measurement
At every execution the element calculates the actual position "POSACT" using the following formula:
− if INSIG = 0 then POSACT(new) = POSACT(old) +(PC(new)-PC(old))
− if INSIG = 1 then POSACT(new) = POSACT(old) - (PC(new)-PC(old))
At synchronisation the current value of the PC (PC( sync): pulse counter value at synchronising) is
copied to a hardware register and the "SYNCRDY" output of the SPEEDP element is set to "1".
During the first execution cycle after synchronisation the "POSACT" is calculated as follows:
POSACT(new) = PRECOUNT + (PC(new)-PC(sync))

The synchronisation mode is defined with the "SYNCCOND" input and can be changed during a
normal execution of the application program. Hardware or software synchronisation can be selected.
Appropriate modes are selected according to the Table 6.
In order to avoid malfunction when switching to hardware synchronisation the synchronisation inhibit
"HWSYNCIH" input should be first set to "1". Once the "SYNCCOND" has been changed the
"HWSYNCIH" can be reset to "0".
Synchronisation mode selection
Parameter SYNCCOND Table 6
Value External signal transition Wait for zero Direction YPH107

"0->1" "1->0" pulse CHZ Forw Backw only
0 (Synchronising only from application program)
1 X - - X X
2 - X - X X
3 X - X X X
4 - X X X X
5 - - X X X
6 X - - X - X
7 - X - X - X
8 X - X X - X
9 - X X X - X
10 - - X X - X
11 X - - - X X
12 - - - - X X
13 X - X - X X
14 - X X - X X
15 - - X - X X
16 (X OR "1") - X - - -
17 - (X OR "0") X X - -
18 (X OR "1") - X X - X
19 - (X OR "0") X X - X
20 (X OR "1") - X - X X
21 - (X OR "0") X - X X
22 ( position counting and synchronisation disabled)
248
3AFY61281240
Application Guidelines
There is a minimum frequency limit for the TCLK. This in turn sets a limitation on the maximum
time counting interval for the time counter TC before the overrun occurs (the overrun happens when
the number of counts exceeds the capacity of the counter). This critical time interval is 64
milliseconds.
Since it is normal for the real execution intervals of the tasks to fluctuate it is important that the
SPEEDP element execution interval provides a safe time margin for the measuring functions. With
that in mind element execution intervals not exceeding 30 milliseconds are recommended.
Error Codes
The SPEEDP element generates Error codes according to the general formula for I/O extension board:
9000 + 100*BOARD + one of the following I/O board faults:
ADDR is the actual I/O address of YPH107/YPH108 (0 to 15):
1= bus error
2= power supply fault
8= pulse input fault*), YPH108 channel 1 and YPH107
10 = power supply and pulse input fault, YPH108 Channel 1 and YPH107
32 = pulse input fault*), YPH108 Channel 2
34 = power supply and pulse input fault, YPH108 Channel 2
*)pulse input fault means that differential input is selected (INPMODE = 2, 3 or 6), but the tacho
input is not differential.
249
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Square Root Element SQRT

Summary
SQRT (SQuare RooT) is used to calculate the square root of a real number. K I
The result can be multiplied by an optional value. 1 I O 5
2 K ERR
6
Call SQRT SQRT
Connections Table 1
1 I IR Input. Input for number whose square root is to be calculated.

2 K IR Input for multiplication factor K.
5 O OR Output. Output for the product of the value at input K and the square
root of the value at input I.
6 ERR OB ERRor. Output which is set if the value at input is negative.
Function
The square root of the value at input I is calculated. The result is multiplied by the value at input K.
The product is stored at the output O.
Supervision
If the value at the input I is negative, the error output ERR is set to 1. The value 0.0 is then stored at
the output O.
250
3AFY61281240
Memory Element SR
Summary
The memory element SR (Set Reset memory ) is used as a memory for boolean 1 S 5
variables. 2 R
Figure 1. PC
Element SR
Call SR
Connections Table 1
1 S IB Set input.
2 R IB Reset input which overrides the set input.
5 OB Output from the memory element.
Function
The element output is set (to 1) if the set input is set at the same time that the reset input is reset (to
O). If the reset input is set, the output is unconditionally reset.
1 S 5
1 &
2 R
251
3AFY61281240
Memory Element SR-AA

Summary
Set Reset with AND set gate and AND reset gate function block is used as 1 20
& S
a memory element for boolean variables. 2
...
C1
11
& R
12
...
Call SR-AA (C1,C2) 10+C2
Call Parameters Table 1 SR-AA
C1 Number of inputs in the set gate 1 to 9

C2 Number of inputs in the reset gate 1 to 9
Connections Table 2
1 - IB Input to the set function.

2 IB Input to the set function.
...
C1 - IB Input to the set function.
11 - IB Input to the reset function.
12 IB Input to the reset function.
...
10+C2 - IB Input to the reset function.
20 OB Memory element output.
Function
The element output O is set to 1 if all the conditions (1 to C1) for the AND set gate are satisfied (set to
1) at the same time at least one of the conditions (11 to C2) for the AND reset gate is not set. If all
conditions for the reset gate are satisfied (all of 11 to C2 are 1) then the output is unconditionally reset
(to 0).
The reset function overrides the set function.
1 20
> 1
& &
2
C!
11
12 &
10+C2
Figure 2. Function diagram SR-AA
252
3AFY61281240
Memory Element SR-AO

Summary
Set Reset with AND set gate and OR reset gate function block is used as a
memory element for boolean variables. 1 20
& S
2
...
C1
11 1 R
12
...
10+C2
Call SR-AO (C1,C2)
Figure 1. PC
Element SR-AO

Parameter Significance Permissible Values

Connections Table 2

...
...
20 - OB Memory element output.
Function
The element output O is set to 1 if all the conditions (1 to C1) for the AND set gate are satisfied (set to
1) at the same time none of the conditions (11 to C2) for the OR reset gate is set. If any condition for
the reset gate is satisfied (any of 11 to C2 is 1) then the output is unconditionally reset (to 0).
1 20
> 1
& &
2
C!
11
12 1
10+C2
Figure 1. Function diagram SR-AO
253
3AFY61281240
Memory Element SR-D

Summary
The memory element SR-D (Set Reset memory-Data input) 1 S 5
2 D
3 > C
4 R
Call SR-D
Figure 1. PC
Connections Table 1 Element SR-D
1 S IB Set input.
2 D IB Data input.
3 C IB Clock. Dynamic input for entry of data from the D-input.
4 R IB Reset input which overrides all other inputs.
5 - OB Output from the memory element.
Function
If only the S and R inputs are used, SR-D functions as an ordinary SR element. When the input R is
reset and the input C goes to 1, the value at the input D is stored at the output 5. When the input R is
set, the output 5 is unconditionally reset, i.e. R overrides the other inputs.
1 S 5
1 S
2 D
&
3 C
> 1
& 1 R
4 R
254
3AFY61281240
Memory Element SR-OA

Summary
Set Reset with OR set gate and AND reset gate function block is used as a 1 20
1 S
memory element for boolean variables. 2
...
C1
11
& R
12
Call SR-OA (C1,C2) ...
10+C2
Call Parameters Table 1 SR-OA

Connections Table 2

...
...
20 - OB Memory element output.
Function
The element output O is set to 1 if one or more of the conditions (1 to C1) for the OR set gate are
satisfied (set to 1) at the same time one of the conditions (11 to C2) for the AND reset gate is not set.
If all conditions for the reset gate are satisfied (all of 11 to C2 is 1) then the output is unconditionally
reset (to 0). The reset function overrides the set function.
1 20
1 > 1
&
2
C!
11
&
12
10+C2
Figure 2. Function diagram SR-OA
255
3AFY61281240
Memory Element SR-OO

Summary
Set Reset with OR set gate and OR reset gate function block is used as a 1 20
1 S
memory element for boolean variables. 2
...
C1
11
1 R
12
...
Call SR-OO (C1,C2) 10+C2
Figure 1. PC
Call Parameters Table 1 Element SR-OO

Connections Table 2

...
C1 IB Input to the set function.
...
10+C2 IB Input to the reset function.
20 OB Memory element output.
Function
The element output O is set to 1 if one or more of the conditions (1 to C1) for the OR set gate are
satisfied (set to 1) at the same time none of the conditions (11 to C2) for the OR reset gate is set. If
any condition for the reset gate is satisfied (any of 11 to C2 is 1) then the output is unconditionally
reset (to 0).
1 20
1 > 1
&
2
C!
11
1
12
10+C2
Figure 2. Function diagram SR-OO
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3AFY61281240
Subtractor SUB
Summary
SUB is used for subtraction of two integers or real numbers 1 - 5
2
Figure 1. PC
Call SUB (C1) Element SUB
Connections Table 1
1 - IC1 Input for minuend.

2 - IC1 Input for subtrahend.
20 - OC1 Output for difference.
Function
The value at input 2 is subtracted from valve at input 1 and the result is stored at output 20.
Overflow
257
3AFY61281240
Switch SW
Summary
SW (SWitch) is used as a connection element for SW
data and has up to 9 channels with closing function. (C1,C2)
1 ACT
The data type can be integer, real number, Boolean
11 12
or time. 21 22
Call SW (C1,C2) 10xC2+1 10xC2+2
Connections Table 1 Figure 1. PC Element SW

C2 Number of channels 1 to 9
1 ACT IB ACTivate. Input for activation of the switch. When the input is set
to 1 the switch is activated.
11 - IC1 Input to channel 1 which is connected to the output for channel 1
when the switch is activated.
12 - OC1 Output from channel 1.
.
.
.
10xC2+1 - IC1 Input to channel C2 which is connected to the output for channel
C2 when the switch is activated.
10x C2+2 - OC1 Output from channel C2.
Function
When the control input ACT is 0, the output data is according to the data type. When ACT is set, data
comes from the inputs 11 to 10xC2+1.
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3AFY61281240
Switch SW-C
Summary
SW-C (SWitch - Changeover) is used as a SW-C
connection element for data and has up to 9 (C1,C2)
1 ACT
channels with switching function. The data type can
11 13
be integer, real number, Boolean or time. 12
21 23
22
10xC2+1 10xC2+3
10xC2+2
Figure 1. PC Element SW-C
Call SW-C (C1,C2)

C2 Number of channels 1 to 9
Connections Table 1
1 ACT IB ACTivate. Input for activation of the switch. When the input is set
to 1 the switch is activated.
11 - IC1 Input for channel 1 which is connected to the output for channel 1
when the switch is not activated.
13 - IC1 Output from channel 1.
when the switch is not activated.
.
.
.
C2 when the switch is activated.
C2 when the switch is not activated.
10xC2+3 - OC1 Output from channel C2.
Function
When the control input ACT is 0, the data from the inputs 12 to 10xC2+2 are connected to the
appropriate outputs. When ACT is set, data comes from the inputs 11 to 10xC2+1.
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3AFY61281240
Element for Calculation of System Load

SYSL
Summary
SYSL (SYStem Load) calculates the system load. If the system is overloaded SYSL (C1)
1 MAXL LOAD 5
this is indicated. Inputs and outputs for handling of maximum load may be
2 HYS OVERL 6
selected with a call parameter. L>ML 7
Figure 1. PC
Element SYSL
Call SYSL (C1)
C1 Determines whether 0 to 1
inputs and outputs for
the maximum load is
to be included in the
element
Connections Table 1
1 MAXL IR MAXimum Load. Input for maximum system load.

2 HYS IS HYSteris. Input for hysteresis for maximum system load.
5 LOAD OR Output for system load in percent.
6 OVERL OB OVERLoad. Output that is set to 1 when the system is fully
loaded.
7 L>ML OB Load >Maximum Load. Input that is set to 1 when the load
exceeds the value specified t the input MAXL.
These connections are only included if the call parameter C1 = 1.
Function
If the system is fully loaded the output OVERL is set to 1. The system load in percent (%) is given at
the output LOAD. If the call parameter C1 has been set to 1 the element will have inputs MAXL and
HYS, for maximum load and hysteresis respectively. When the load MAXL is exceeded the output
L>ML is set to one. L>ML is reset when the load lowers to below MAXL-HYS. If MAXL the MAXL
is used. If MAXL or HYS is negative the value 0 is used.
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3AFY61281240
Time Delay On TON

Time Delay Off TOFF
Summary
Time delay on TON (Timer-ON-delay) and time delay off TOFF T
(Timer OFF-delay) of Boolean variables for use in connection with 1 I O 5
combinatory expressions. 2 TD TE 6
Figure 1. PC Element TON
Call TON, TOFF T

1 I O 5
2 TD TE 6
Connections Table 1
TOFF
1 I IB Input for start of time delay.

2 TD IT Time Delay. Input for present time. Max 23h 59m 59.999s.
5 O OB Output. Output which is set (TON) or reset (TOFF) when the preset
time has elapsed.
6 TE OT Time Elapsed. Output which specifies how long I has been set (TON)
or reset (TOFF). When the preset time (TD) has elapsed, TE stops.
Function
TON
The input variable to the input I is obtained delayed at output O when the input variable changes from
0 to 1 in accordance with the time pulse diagram, figure 127. The output signal returns when the
input variable changes from 1 to 0.
TOFF
The input variable to the input I is obtained delayed at output O when the input variable changes form
1 to 0 in accordance with the time pulse diagram, figure 128. The output signal is set when the input
variable changes from 0 to 1.
261
3AFY61281240
3s
1
1
0
0 1
0
0 1 2 3 4 5 6 7 8 9 10
Figure 3. Example of time diagram for TON with preset time 3 s.
3s
1 1
0
1
0
0
0 1 2 3 4 5 6 7 8 9 10
Figure 4. Example of time diagram for TOFF with preset time 3 s.
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3AFY61281240
Time Delay On TON-RET

Summary
TON-RET (Time delay ON-RETentive) switch-on delay with T
1 I O 5
accumulation time measurement of Boolean variables for use in
2 TD
connection with combinatory expressions. TON-RET is used for e.g.
3 TE 6
operational time monitoring.
Time delay on TON (Timer-ON-delay) and time delay off TOFF Figure 1. PC Element
(Timer OFF-delay) of Boolean variables for use in connection with TON-RET
combinatory expressions.
Call TON-RET
Connections Table 1
1 I IB Input for start of time delay when the input changes from 0 to 1. The
time circuit maintains its status even when the input returns to 0.
2 R IB Reset. Input which resets the timer. R must be reset (to 0) for the
timer to function.
3 TD IT Time Delay. Input for preset time, i.e. the time during which the
input I must be set (to 1).Max 23h 59m 59s.
5 O OB Output which is set when the preset time has elapsed.
6 TE OT Time Elapsed. Output which indicates the time during which I has
been set to 1.
Function
The input variable to the input I is obtained delayed at the output O when the input variable changes
from 0 to 1 in accordance with the time pulse diagram in figure 128. If the input variable returns to 0,
the time which has elapsed remains in the timer and when the variable returns to 1, the time
continues from the value which applied when the variable went to 0. The input R must be reset (to 0)
when the timer functions. If R is set (to 1) both outputs O and TE are reset.
1s 2s = 3s
1
I
0
1
R
0
1
O
0
0 1 2 3 4 5 6 7 8 9 10
Figure 2. Example of time diagram with preset time 3 s.
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Trigger Element TRIGG

Summary
The triggering element TRIGG is used for reducing impulse times at the start of 1 5
> 1
automatic procedures and for calculating functions.
Figure 1. PC
Call TRIGG Element TRIGG
Connections Table 1
1 - IB Input for start of trigger pulse.

5 - OB Output for trigger pulse.
Function
When the input signal is set (to 1) the output signal is also set. The output signal is cleared during the
next program cycle, irrespective of the value of the input signal. For the output signal to be set, the
input signal must have been 0 for the duration of one program cycle.
The output signal from the element may only be used with its own execution unit, otherwise, detection
of it is not certain.
Conn 1
1 0
1 program cycle
Conn 1
5 0
Figure 2. Time diagram
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Watchdog WDOG
Summary
The WATCHDOG function of the APC board and max. four W DOG
F = 2000 - F1 APCT ERR 10
I/O boards is controlled by the WDOG function block. F = 2000 - F2 IOBT ERR1 31
F = 0 - F3 BOARD1 TRIP1 32
F = 1 - F4 BOARD2 ERR2 33
F = 2 - F5 BOARD3 TRIP2 34
F = 3 - F6 BOARD4 ERR3 35
-1 > RESET TRIP3 36
ERR4 37
Call WDOG - 21 APCSEL TRIP4 38
- 22 IOBSEL ERRC 99
Connections Table 1 Figure 1. PC Element WDOG
F1 APCT II Time for APC watchdog counter

F2 IOBT II Time for watchdog of I/O-Boards
F3 BOARD1 II Node number of I/O-BOARD
1 RESET IB RESET for error and trip outputs
10 ERR OB ERRor
21 APCSEL II Function SELector for APC-board watchdog
22 IOBSEL II Function SELector for I/O-Board watchdog
31 ERR1 OB ERRor of the I/O-board BOARD1
32 TRIP1 OB Watchdog TRIP of the I/O-board BOARD1
General
The APC and I/O (YPQ111A) boards have own watchdog functions, which control the status of the
APC application software. The watchdogs will trip if they are not refreshed in a specified time.
A watchdog tripping of the APC board will light up the red led on the board and clear all digital
outputs of the board. If the switch S3 is in position 1-2, the tripping will cause a restart of the APC.
An older APC version than 1.1/0 will not clear the digital outputs if the switch is not in position 1-2
when the APC restarts. A tripping of the I/O boards will clear digital and analog outputs and a
tripping alarm will be saved in the system alarm buffer.
There is also a counter on the APC board which controls the status of the system software so that the
system software would refresh the counter within a certain time period. If it is not refreshed and fault
alarms (STALL ERROR) will be saved into the systems alarm buffer and the APC attempts a restart,
then the red led will be lit during the startup.
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When the application program is stopped with the FCB command block, the control of the APC board
watchdog will be changed from the WDOG function block to the system software. In this case the
program will not restart nor will the red led light up.
The digital outputs will, however, be reset if the WDOG function block was controlling the APC
board watchdog (APCSEL>0) before the block command.
The watchdog of the I/O boards will trip, if they were controlled by the WDOG function block before
the block command.
If the WDOG function block is not used, the system software controls the watchdogs of the APC and
I/O boards, so that no tripping will occur.
Function
The watchdog control of the APC board will be activated by setting the APCSEL input > 0. The time
(ms) in which the refreshing of the system software shall be done is defined to the counter with the
function parameter APCT(normally the system software will refresh the counter at 2 ms intervals).
The refreshing of the APC watchdog must be done at least every 100 ms (30 ms recommended). The
refreshing cycle which the watchdog requires ie. the tripping time, cannot be changed in the program.
The watchdog control of the I/O boards will be activated by setting the input IOBSEL > 0. The
IOBSEL selections are as follows:
IOBSEL= 0 The watchdog function is not in use.

1 Effective tripping state is in input TRIPx and the refreshing of the watchdog will be
continued after tripping.
2 Output TRIPx is latched. The refreshing of the watchdog will be continued after
tripping.
>2 Output TRIPx is latched. The refreshing of the watchdog will be not continued after
tripping.
The function parameter IOBT defines the time during which the watchdogs of the I/O boards shall be
refreshed.
The boards on which watchdog control shall be used are defined with function parameter BOARD
1...4. The node number of the board will be set in the parameter. The value -1 means that there is no
board.
The ERR output is set if the function block has detected a fault. ERR 1...4 is set if an error has been
found on the board. Outputs ERR 1...4 will also set the ERR output.
TRIP 1...4 output will show the detected watchdog tripping on the board (the function depends on the
IOBSEL selection). TRIP 1...4 output will also set if communication with the I/O board is not
successful within the time IOBT.
The ERRC output will report the error code of the first detected fault or even a later detected error
code 23317.
The pulse of the input RESET will clear the TRIP and ERROR outputs. This pulse will also start a
refreshing of the I/O boards after tripping if the IOBSEL. >2.
ERRor Codes Table 1

ERRor code # Description
5x39 Illegal identification: I/O-board type is not YPQ111A.
5x40 I/O-board is missing
5x45 I/O-board failure. Program on I/O-board is damaged.
23317 Programming error.
1. Task cycle time is longer than the required updating interval of the APC-
watchdog (cycle time must be =<100 ms). In this case, control of the APC
watchdog (RC-circuit) is automatically moved over to system program.
2. Task cycle time is longer than watchdog time IOBT.
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Exclusive Or Gate XOR

Summary
XOR (eXclusive OR) is used to generate combinatory expressions with Boolean 1 =1 5
variables. 2
Figure 1. PC
Element XOR
Call XOR
Connections Table 1
1 - IB Input
2 - IB Input
5 - OB Output
Function
The output signal from the XOR element is 1 if the input signals are different and 0 if they are equal,
see table 103. By inverting the output of the XOR element, a is obtained if the signals are equal.
Table 2 Truth table

1 2 5
0 0 0
0 1 1
1 0 1
1 1 0
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DATA BASE ELEMENTS

ACS Link ACS00, ACS01, ACS02
Summary
DB elements ACS00, ACS01 and ACS02 are used to define the ACS ACS00
NAME
communication boards, the types of the drives (ACS 600 MultiDrive or ACS 600 BUS
SingleDrive) connected to these boards and the application identifiers of the STATION
connected drives. POSITION
TYPE
IMPL
DRTYPE1
APPID1
DRTYPE2
APPID2
DRTYPE3
APPID3
DRTYPE4
APPID4
Figure 1. DB
Call ACS00, ACS01, ACS02 Element ACS00
Connections Table 1
Terminal Value Default Description

name entered by value
NAME system This terminal is for internal use only.
BUS system This terminal is for internal use only.
STATION system This terminal is for internal use only.
POSITION system This terminal is for internal use only.
TYPE user YPQ112A Board type (YPQ112A or YPQ112B). ACS00
YPQ112B Board type (only YPQ112B. Others
IMPL system This terminal is for internal use only.
DRTYPE1 user NO_DRIVE Drive type of the first drive of this communication
board (NO_DRIVE, ACS600 MultiDrive or
ACS600 SingleDrive).
APPID1 user 0 Application identification number of the first drive
of this communication board
(see chapter "Application Identifiers").
DRTYPE2 user NO_DRIVE Drive type of the second drive of this
communication board
APPID2 user 0 Application identification number of the
second drive of this communication board.
DRTYPE3 user NO_DRIVE Drive type of the third drive of this communication
board
APPID3 user 0 Application identification number of the third drive
of this communication board.
DRTYPE4 user NO_DRIVE Drive type of the fourth drive of this
communication board
APPID4 user 0 Application identification number of the fourth
drive of this communication board.
Note 1: The parameters indicated as "Entered by the system" are not modifiable by the USER.
Note 2: DRTYPEn can be ADS600 only in ACS00.
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ACS DB Elements, YPQ112 Boards and Drive Numbers

Max. four drives can be connected to one ACS communication board. There are two communication
board types:
- YPQ112A is used with ACS 600 MultiDrive and ACS 600 SingleDrive.
- YPQ112B is used if only ACS 600 SingleDrive are connected to this board.
ACS00 defines the first communication board. If there are only ACS 600 SingleDrive connected to
this board then this board must be YPQ112B (in I/O board addresses 8 to 11) else this board must be
YPQ112A (in I/O board addresses 8 to 15).
The drive numbers of the drives connected to this board are 1 to 4.
ACS01 defines the second communication board (this board must be YPQ112B in I/O board addresses
4 to 7). It is possible to connect only ACS 600 SingleDrive to this board.
You can use ACS01 only if you have defined ACS00.
ACS02 defines the third communication board (this board must be YPQ112B in I/O board addresses
12 to 15). It is possible to connect only ACS 600 SingleDrive to this board.
You can use ACS02 only if you have defined ACS00 (with ACS 600 drives only) and you have
defined ACS01.
Note: The above mentioned drive numbers 1 to 12 are logical drive numbers that are used in the
DRNR inputs of ACS blocks (e.g. ACSRX).
The real drive number of a drive must always be 1 (one) in every drive connected to an YPQ112!
Application Identifiers
The Application Identifier of a drive application is a 16 bit integer defined by the drive application
programmer. The value of an APPIDn input must be the same as the value of the Application
Identifier in the corresponding drive.
Note: Application Identifiers are not currently used (the only legal value of an APPIDn input is the
default value 0).
Related documents
Description of function block ACSPR, ACSRX and ACSPW.
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Boolean Data DAT(B)

Summary
The DAT(B) element contains 32 packed boolean data values. The data values are given a NAME
and a valid flag.
By means of the call name DAT(B) the Engineering Station will create 1 data base element of type
Boolean Data.
Picture Boolean Data element, Overview

DATx
Boolean Data
NAME VALID
VALUE Base part
VALUE2 VALUE11-VALUE20
VALUE4
VALUE5
VALUE6
VALUE7
VALUE8
VALUE9
VALUE10
Base part
VALUE11 VALUE21
VALUE12 VALUE22
VALUE13 VALUE23
VALUE14 VALUE24
VALUE15 VALUE25
VALUE16 VALUE26
VALUE17 VALUE27
VALUE18 VALUE28
VALUE19 VALUE29
VALUE20 VALUE30
VALUE11 - VALUE20 VALUE31
VALUE32
VALUE21 - VALUE32
Picture Boolean Data element, Base part

DATx
Boolean Data
MOTOR1SETUP NAME VALID
VALUE Base part
VALUE4
VALUE5
VALUE6
VALUE7
VALUE8
VALUE9
VALUE10
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Terminals Boolean Data element, Base part

Terminal Value Default PC con- Description Remarks
Name entered value nection
by data
type
NAME user * - Unique element NAME. Default Max 12
name from superior Data Set characters.
element. When created Example if
independently default name is DS is named
DATx. SET1:
SET1.B1
VALID PC 0 B(r/w) VALID. Has to be set by PC -
element (or MMI,..).
VALUE system 0 B(r/w) Boolean VALUE. -
VALUE2 system 0 B(r/w) Boolean VALUE. -
. -
.
.
VALUE10 system 0 B(r/W) Boolean VALUE. -
Picture Boolean Data element, VALUE11-VALUE20

DATx
Boolean Data
VALUE11
VALUE12 Base part
VALUE15
VALUE16
VALUE17
VALUE18
VALUE19
VALUE20
Picture Boolean Data element, VALUE21-VALUE32

DATx
Boolean Data
VALUE21
VALUE22 Base part
VALUE26
VALUE27
VALUE28
VALUE29
VALUE30
VALUE31
VALUE32
Terminals Boolean Data element, VALUE11-VALUE32

by data
type
. -
.
.
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Integer Data DAT(I)

Summary
The DAT(I) element contains one integer data value. The data value is given a NAME and a VALID
flag.
By means of the call name DAT(I) the Engineering Station will create 1 data base element of type
Integer Data.
Picture Integer Data element

DATx
Integer Data
COUNTVALUE4 NAME VALID
VALUE
Terminals Integer Data element

by data
type
NAME user * - Unique element NAME. Max 12
Default name from superior characters.
Data Set element. When Example if DS
created independently default is named SET1:
name is DATx. SET1.I1
vALUE system 0 I(r/w) On integer VALUE. -32768..+32767
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IntegerInteger Data DAT(II)

Summary
The DAT(II) element contains 2 packed integer data values. The data values are given a NAME
and a VALID flag.
By means of the call name DAT(II) the Engineering Station will create 1 data base element of type
Integer Data.
Picture DAT(II) element
Terminals DAT(II) element

by data
type
name is DATx. SET1.I1
VALUE system 0 I(r/w) On integer VALUE. -32768..+32767
VALUE2 system 0 I(r/w) On integer VALUE. -32768..+32767
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IntegerLong Data DAT(IL)

Summary
The DAT(IL) element contains one integer long data value. The data value is given a NAME and a
VALID flag.
By means of the call name DAT(IL) the Engineering Station will create 1 data base element of type
IntegerLong Data.
Picture IntegerLong Data element

DATx
IntegerLong Data
COUNTVALUE7 NAME VALID
VALUE
Terminals IntegerLong Data element

by data
type
name is DATx. SET1.IL1
VALUE system 0 IL(r/w) On integer long VALUE. -2147483648..
+2147483647
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Real Data DAT(R)

Summary
The DAT(R) element contains one real data value. The data value is given a NAME and a VALID
flag.
By means of the call name DAT(R) the Engineering Station will create 1 data base element of type
Real Data.
Picture Real Data element

DATx
Real Data
SETPOINT4 NAME VALID
VALUE
Terminals Real Data element

by data
type
name is DATx. SET1.R1
VALUE system 0 R(r/w) On real VALUE. -
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Drives Communication Board DCB00

Summary
DB element DCB00 is necessary for initialization and usage of a DCB board DCB00
NAME
(=DriveCommunicationsBoard) in APC.
STATION
DCB interface is a programming and hardware standard used to link the APC POSITION
with various types of DCB-daughter boards (= in order to interface an APC TYPE
station to various types of communication systems which presume attached STN
stations to use specific communication protocol).
PROTOCOL
DCB00 defines and allocates a memory area from APC system RWM for HDSIZE1
communication data buffers called VCIs (=Virtual Connector Interface) and is a RECS1
prerequisite for function block DCBINIT to activate the attached DCB board at RECSIZE1
the moment when APC application program is deblocked for execution. DCB HDSIZE2
board is actually activated by downloading the configuration parameters for
RECS2
DCB board from the APC. DCB00 allocates memory area for these parameters
RECSIZE2
as well, and therefore the APC application programmer needs to specify a few
buffers more by the RECS pins of DCB00 than actually needed for DCBTRAs, Figure 1. DB
DCBRECs and system VCIs of the desired protocol. Element DCB00
DCB00 block is used also to specify which protocol to use in the communication. The DCB boards
may be "multiprotocol boards", which need such specification from the user. This definition is also
compared with the initial identification message from the DCB board, and thus it is possible to verify
that installed DCB hardware is equal or compatible with the assumptions of APC application
program(mer).
All other communication parameters will be initialized either to their default values (which are
dependent on the protocol) or to values introduced by application programmer through DCBINIT
blocks.
The communication channels of DCB boards are principally independent of each other and may be
parameterized individually. However, there is one exception. Both channels have to execute the same
protocol.
Call DCB00
Connections Table 1
Terminal name Value entered by Default value Description
NAME user DCB*- Any name below 20 characters can be

fed
STATION system 1 Station number, for internal use only
POSITION system 2 Order in DB element library, for
internal use only.
TYPE user YPK114 Type of the DB element (no meaning
for APC).
STN user 0 (No meaning for APC).
PROTOCOL user 9 A code number to specify the desired
protocol.
HDSIZE1 system 68 Mem_size for channel #1 specific
parameters and variables.
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Terminal name Value entered by Default Description
RECS1 user 20 Number of data buffers (VCIs) for channel #1.

RECSIZE1 user 84 Max. size of a data buffer (VCI) for channel #1.
HDSIZE2 system 68 Mem_size for channel #2 specific parameters and
variables.
RECS2 user 0 Number of data buffers (VCIs) for channel #2.
RECSIZE2 user 42 Max. size of a data buffer (VCI) for channel #2.
Valid codes for the protocol (+ required space for APC and DCB
parameters and applicable values for RECS and RECSIZE)
Code Protocol APC_par DCB_par sysVCIs RECS1 RECSIZE RECS2

name
1 SAMI 20 bytes 42 bytes 5 0 or 7... 42... 0 or >7
protocol
3 S3964 20 bytes 42 bytes 5 0 or 7... 42... 0 or >7
(Siemens)
4 S3964R 20 bytes 42 bytes 5 0 or 7... 42... 0 or >7
(Siemens)
5 DF1 (Allen- 20 bytes 42 bytes 5 0 or 7 to 32 34... 0 or >7 to 32
Bradley)
6 MODBUS 20 bytes 42 bytes 5 0 or 7 to 32 34 to 254 0 or >7 to 32
protocol
9 MFB 20 bytes 52 bytes 6 7... 120 0
(MasterField
Bus)
Note 1: Usable data area of each VCI buffer is 32 less than specified with RECSIZE.
Note 2: Space for APC parameters and DCB parameters is allocated from the same pool as the VCIs,
i.e. the product RECS * RECSIZE must be high enough to provide memory for APC parameters, for
DCB parameters, for all sysVCIs and for all application VCIs (one application VCI for each
DCBREC and DCBTRA).
Note 3: Each VCI (= system VCI or application VCI) takes the same amount of memory, i.e.
RECSIZE bytes.
Related documents
Descripton of DCBINIT, DCBTRA, DCBREC, DCBRD and DCBWR PC elements.
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DI Calculated DIC
Summary
The DI Calculated element is an event channel element used for detection of calculated digital
events.
An event is detected when the boolean value (terminal VALUE) changes from 0 to 1 or vice versa,
and event generation is deblocked (terminal NORM_TR=1). There is a filtering facility to suppress
event generation in case of rapidly changing values.
Picture DI Calculated element

DICx
DI Calculated
DIC1 NAME VALUE
1 ACT ERR
0 NORM_TR
0 NORM_POS
0 AL_DIAL
640ms SCANT
0 FILT_FTR
Terminals DI Calculated element

Terminal Value Default PC Description Remark
Name entered value connection s
by data type
NAME user DICx - Unique NAME of the event Max. 20
channel character
s.
ACT user 1 - Element is: -
0=not ACTive
1=ACTive
NORM_TR user/PC 0 B(r/w) NORMal TReatment. Not
0=event detection disabled allowed
1=event detection enabled to change
on-line.
NORM_POS user 0 - NORMal POSition for this -
channel.
AL_DIAL user 0 - DIAL the master on ALarm. RCOM
0=no dial on alarm only
1=dial on alarm
SCANTT user 640ms - SCAN Time for event -
detection in milliseconds.
10ms,20ms,40ms,80ms,
160ms,320ms,640ms,
1280ms,2560ms,5120ms,
10240ms,20480ms,40960ms,
81920ms,163840ms,
327680ms
TFILTT_FTR user 0 - FILTer time FacToR. 0 to 32
Filter time = FILt_FtR x
SCANTT
Duration of a value change
before the change is accepted
as event.
VALUE PC 0 B(r/w) Signal VALUE (is watched -
for events)
ERR system - B(r) ERRor flag indicating fatal -
errors.
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Drive Link DRL00

Summary
DB element DRL00 is used for initialisation of the Drive Link controller. DRL00
Drive Link is a communication standard used to link the APC with the ABB NAME
drives. DRL00 activates the drive nodes and for each such node it defines the STATION
area called a Drive Buffer. The Drive Buffer contains the records that are used POSITION
by Drive Link as a transmit and receive buffers for cyclic and parameter TYPE
messages. The number of available buffers is specified by the "NODRBUFx"
NODRBUF1
parameter of the DRL00 DB element. The size of those buffers is written
automatically by the system. BUFSIZE1
The DRL00 element has to be defined in the application prior to any of the NODRBUF2
Drive Link PC elements. BUFSIZE2
NODRBUF3
BUFSIZE3
NODRBUF4
BUFSIZE4
Call DRL00 Figure 1. DB

Element DRL00
Connections Table 1

NAME user - Any name below 20 characters can be feed
POSITION system 1 Order in DB element library, for internal use only
TYPE system DRL00 Type of the DB element
NODRBUF1 user 50 Number of buffers for message receiving and
transmitting for drive 1
BUFSIZE1 system 32 Size of one transmitting and receiving buffer for drive 1
Related documents
Descripton of DRTRA, DRREC, DRPAR and DRUPL PC elements.
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DataSet Peripheral DSP

Summary
The DataSet Peripheral element represents a block of data to be received or sent over Advant
Fieldbus 100 via Data Set Communication. With the element you select address, mode and data
for one data set. The element defines the set, and contains references to separate DAT data base
elements. In these DAT elements the data to be sent or received is stored.
By means of the call name DSP the Engineering Station will create 1 data base element of type
DataSet Peripheral.
Picture Dataset Peripheral, Overview

DSPx
DataSet Peripheral
NAME VALID
ACT ERR Base part
BUS Value references
IDENT
NO_BREC
NO_INT
NO_INTL
NO_REAL
USER
SOURCE
BLOCKED
STATION
CYCLETIM
SORT_REF
Base part
REF1
REF2
REF3
REF4
REF5
REF6
REF7
REF8
Value references
Picture Dataset Peripheral element, Base part

DSPx
DataSet Peripheral
DSP1 NAME VALID
1 ACT ERR Base part
0 BUS Value references
1 IDENT
0 NO_BREC
0 NO_INT
0 NO_INTL
0 NO_REAL
0 USER
RECEIVE SOURCE
0 BLOCKED
1 STATION
512 CYCLETIM
YES SORT_REF
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Terminals Dataset Peripheral element, Base part

by data type
NAME user DSPx Each Data Set must have a Max 20
unique NAME characters
ACT user 1 - The element is: -
0=spare
1=ACTive
BUS user 0 - BUS number of releated Treated as
bus. comment.
IDENT user 1 - IDENTifies the Data Set on 1 to 50
the Advant Fieldbus 100.
NO_BREC user 0 - Number of Boolean RECords 0 to 8
in the set.
NO_INT user 0 - Number of INTeger records 0 to 8
in the set.
NO_INTL user 0 - Number of INTegerLong 0 to 8
records in the set
NO_REAL user 0 - Number of REAL records in 0 to 8
the set.
USER predef 0 - USER -
0=Advant Fieldbus 100
communication
1=not yet defined
2=not yet defined
SOURCE user RECEIVE - SOURCE, Defines the -
direction of the
communication,
RECEIVE,
SEND
BLOCKED predef 0 - For compatibility reasons. -
STATION user 1 - STATION number of 1 to 80
opposite target..
CYCLETIM user 512 - CYCLETIMe, Transmission -
interval in milliseconds.
1, 2, 4, 8, 16, 32, 64, 128,
256, 512, 1024, 2048, 4096
SORT_REF user YES - SORT REFerences, if YES -
then all DAT refs are sorted
in order: B, I, IL, R.
VALID system - B(r) VALID. -
1=Data has been updated.
0=Data has not been received
within 3xCYCLETIM.
Not supported for sending.
ERR system - B(r) ERRor. -
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Picture DataSet Peripheral element, Value references

DSPx
DataSet Peripheral
REF1 Base part
REF2 Value references
REF3
REF4
REF5
REF6
REF7
REF8

by data
type
REF1 user * - REFerence: Name of a DAT -
element.
element.
.
.
.
element.
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Event Set (Send) EVS(S)

Summary
Event Set (EVS) elements are used for transport of time-tagged events from Advant Controller 110
to Advant Controller 400 series. An Event Set element groups a set of Event Channels for sending
or receiving of events.
The Event Set (Send) element collects events from referenced Event Channel elements and sends
them to the evenet receiver when requested.
The maximum number of Event Set elements is restricted to 16 per Advant Controller 110 station.
Picture Event Set (Send) element, Overview

EVSx
Event Set (Send)
NAME Q_EMPTY
ACT ERR Base part
IDENT Event Chan. 1-16
QUEUE Event Chan. 17-32
CLEAR_Q
Base part
REF1 REF17
REF2 REF18
REF3 REF19
REF4 REF20
REF5 REF21
REF6 REF22
REF7 REF23
REF8 REF24
REF9 REF25
REF10 REF26
REF11 REF27
REF12 REF28
REF13 REF29
REF14 REF30
REF15 REF31
REF16 REF32
Event Chan. 1-16 Event Chan. 17-32
Picture Event Set (Send) element, Base part

EVSx
Event Set (Send)
EVS1 NAME Q_EMPTY
1 ACT WARNING Base part
1 IDENT ERR Event Chan. 1-16
NORMAL QUEUE Event Chan. 17-32
0 CLEAR_Q
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Terminals Event Set (Send) element, Base part

by data
type
NAME user EVSx - Unique NAME of the Event Max 20
Set. characters
ACT user 1 - The element is: -
0= not ACTive
1=ACTive
IDENT user 1 - IDENTifies the Event Set 1 to 65535
element in the node. Not allowed
to change
on-line.
QUEUE user NORMAL - Specifies the size of the event Not allowed
QUEUE. NORMAL=(100 to change
entries). on-line.
EXTENDED=(500 entries).
CLEAR_Q predef/PC 0 B(r(w) CLEAR event Queue. Not allowed
0=no action. to change
1=clear event queue. on-line.
Q_EMPTY system - B(r) Flag indicating: -
0=Event Queue is not
EMPTY.
1=Event Queue is EMPTY.
WARNING system - B(r) WARNING flag indicating -
non- fatal errors.
ERR system - B(r) ERRor flag indicating fatal -
errors.
Picture Event Set (Send) element, Event Chan. 1 -16

EVSx
Event Set (Send)
REF1 Base part
REF2 Event Chan. 1-16
REF4
REF5
REF6
REF7
REF8
REF9
REF10
REF11
REF12
REF13
REF14
REF15
REF16
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3AFY61281240
Terminals Event Set (Send) element, Event Chan. 1 -16

by data
type
REF1 user * - REFerence: Name of an event (1)
channel element.
channel element.
. .
.
.
channel element.
(1) The REF1 to REF16 terminals are used to fill in the references to the event channels. References
can be made to the DIC, DIMVB, AIC and AIMVB elements generating events.
Picture Event Set (Send) element, Event Chan. 17 -32

EVSx
Event Set (Send)
REF17 Base part
REF20
REF21
REF22
REF23
REF24
REF25
REF26
REF27
REF28
REF29
REF30
REF31
REF32
Terminals Event Set (Send) element, Event Chan. 17 -32

by data
type
REF17 user * - REFerence: Name of connected (1)
Event Channel elements.
. .
.
.
(1) The REF17 to REF32 terminals are used to fill in the references to the event channels. References
can be made to the DIC, DIMVB, AIC and AIMVB elements generating events.
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3AFY61281240
Event Logger Buffer EVT00,EVT01

Summary
DB elements EVT00 and EVT01 are used to make memory reservation forthe EVT00,EVT01
event logger buffers. Each of the DB elements EVT00 and EVT01 include the NAME
memory allocation for four event logger buffers. STATION
The Event Logger buffer consists of the control header and the area holding POSITION
TYPE
event records. EVT00 and EVT01 define the size of the header as well as the
NOTCLEAR
number and size of the records in event buffer.
HDSIZE1
Each Event Logger buffer is managed by the individual EVLOG PC function
EVTBUFS1
block.PC elements EVENT, ERROR and DRFLT are used to write events to the
BUFSIZE1
Event Logger records. HDSIZE2
The Event Logger buffer can be accessed by Drive Tool services and some special EVTBUFS2
FB like eg panel control block PANCON. BUFSIZE2
HDSIZE3
EVTBUFS3
BUFSIZE3
HDSIZE4
EVTBUFS4
Call EVT00,EVT01 BUFSIZE4
Figure 1. DB
Connections Table 1 Element EVT00

NAME user - Text string up to 20 character long
POSITION system 9 or 13 Order in DB element library, for internal use only
9: for EVT00, 13: for EVT01
TYPE system EVT0x Type of the DB element to be EVT00 or EVT01
NOTCLEAR user 1 1 = event buffer not cleared after system start
0 = event buffer cleared after system start .
HDSIZE1 system 42 Size of event buffer 1 header
EVTBUFS1 user 100 Number of records in event buffer 1
BUFSIZE1 system 36 Size (in bytes) of one record in event buffer1
HDSIZE2 system 42 Size (in bytes) of event buffer 2 header
BUFSIZE2 system 36 Size (in bytes) of one record in event buffer 2
Note: The parameters indicated as "Entered by the system" are not modifiable by the USER
Related documents
PC FB descriptions of: EVLOG, DATALOG, DRFLT, ERROR, EVENT and PANCON.
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3AFY61281240
MasterBus 90 Link MB90

Summary
DB element MB90 is used to reserve memory and to activate the bus driver for MB90
NAME
MasterBus 90 communication. MasterBus 90 is a high speed communication serial
STATION
bus used to link APC station’s and other nodes such as PC-Video and MasterPiece
POSITION
90 stations. The node number of the APC on MasterBus 90 is also defined by this
TYPE
database element and must agree with the hardware setting on the MasterBus 90 bus
NODENO
coupler board (YPK112A). NODSBUF
BUFSIZE
Call MB90
Figure 1. DB
Connections Table 1 Element MB90

NAME user MBx Unique 20 character name.
STATION system 1 Station number. For internal use only.
POSITION system 5 Position in DB element library. For internal use only.
TYPE system MB90 DB element type.
NODENO user 0 APC station number 0 to 79.
NODSBUFS user 63 Number of buffers for message receiving and
transmitting. Set to the number of receiving function
blocks or the number of transmitting function blocks,
whichever number is greater.
BUFSIZE system 16 Size of one transmitting and receiving buffer.
Related documents
See also the description of the MB90REC and MB90TRA function blocks.
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3AFY61281240
1 2 3 4
Sample n Signal 1 = lowest
2 4 1 3
Sample n + 1 Signal 1 is still seen

as lowest
DEADB
2 4 1 3
Sample n + 2 Signal 2 = lowest

DEADB
4 1 2 3

DEADB
1 2 4 3
Sample n + 4 Signal 4 is still

DEADB seen as lowest
1 2 4 3
Sample n + 5 Signal 4 is still

DEADB seen as lowest
4 1 2 3
DEADB
Figure 2. Example of function with deadband
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3AFY61281240
Panel Link PAN00

Summary
DB Element PAN00 is used to reserve memory for Panel Link communication. PAN00
NAME
Panel Link is a communication standard used to link APC stations with panels and
STATION
romote I/O. The node number of the APC on the Panel Link bus is also defined by
POSITION
this database element.
TYPE
NODENO
NODSBUF
BUFSIZE
Call PAN00
Figure 1. DB
Connections Table 1 Element PAN00

NAME user PANx Unique 20 character name.
POSITION system 7 Position in DB element library. For internal use only.
TYPE system PAN00 DB element type.
NODENO user 0 APC station number. Master = 0. Slave = 1 to 16
NODSBUFS user 15 Number of buffers for message receiving and
transmitting. Set to the number of receiving function
blocks or the number of transmitting function blocks,
whichever number is greater.
BUFSIZE system 80 Size of one transmitting and receiving buffer.
Related documents
See also the description of the PANREC and PANTRA function blocks.
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3AFY61281240
Boolean Param PARDAT(B)

Summary
The PARDAT(B) element contains 32 packed boolean data values.Each data value is given an
initial value.
A name and a valid flag is given for the complete element.
By means of the call name PARDAT(B) the Engineering Station will create 1 data base element of
type Boolean Param.
Picture Boolean Param element, Overview

PDx
Boolean Param
NAME VALID
INIVAL VALUE Base part
INIVAL2 VALUE2 VALUE11-VALUE20
INIVAL4 VALUE4
INIVAL5 VALUE5
INIVAL6 VALUE6
INIVAL7 VALUE7
INIVAL8 VALUE8
INIVAL9 VALUE9
INIVAL10 VALUE10
Base part
INIVAL11 VALUE11 INIVAL21 VALUE21

INIVAL31 VALUE31
VALUE11-VALUE20 INIVAL32 VALUE32
VALUE21-VALUE32
Picture Boolean Param element, Base part

PDx
Boolean Param
MMICONNECTED NAME VALID
INIVAL VALUE Base part
INIVAL4 VALUE4
INIVAL5 VALUE5
INIVAL6 VALUE6
INIVAL7 VALUE7
INIVAL8 VALUE8
INIVAL9 VALUE9
INIVAL10 VALUE10
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3AFY61281240
Terminals Boolean Param element, Base part

by data
type
NAME user PDx - Unique element NAME.. Max 20
characters
INIVAL user 0 - INItial VALue (boolean) -
VALUE system 0 B(r/w) Boolean VALUE. -
INIVAL2 user 0 - INItial VALue (boolean) -
. -
.
.
INIVAL10 user 0 - INItial VALue (boolean)
Picture Boolean Param element, VALUE11-VALUE20

PDx
Boolean Param
INIVAL11 VALUE11
INIVAL12 VALUE12 Base part
INIVAL15 VALUE15
INIVAL16 VALUE16
INIVAL17 VALUE17
INIVAL18 VALUE18
INIVAL19 VALUE19
INIVAL20 VALUE20
Picture Boolean Param element, VALUE21-VALUE32

PDx
Boolean Param
INIVAL21 VALUE21
INIVAL22 VALUE22 Base part
INIVAL25 VALUE25
INIVAL26 VALUE26
INIVAL27 VALUE27
INIVAL28 VALUE28
INIVAL29 VALUE29
INIVAL30 VALUE30
INIVAL31 VALUE31
INIVAL32 VALUE32
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3AFY61281240
Terminals Boolean Param element, VALUE11-VALUE32

by data
type
. -
.
.
INIVAL32 user 0 - INItial VALue (boolean)
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3AFY61281240
Integer Param PARDAT(I)

Summary
The PARDAT(I) element contains one integer data value. The data value is given a NAME,
INIT_VALue and a VALID flag.
By means of the call name PARDAT(I) the Engineering Station will create 1 data base element of
type Integer Param.
Picture Integer Param element

PDx
Integer Data
MOTORNOMAX NAME VALID
0 INIT_VAL VALUE
Terminals Integer Param element

by data
type
characters
INIT_VAL user 0 - INITial VALue, an integer -32768 to
value. +32767
VALUE system 0 I(r/w) One integer VALUE. -32768 to
+32767
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3AFY61281240
IntegerLong Param PARDAT(IL)

Summary
The PARDAT(IL) element contains one integer long data value. The data value is given a NAME,
INIT_VALue and a VALID flag.
By means of the call name PARDAT(IL) the Engineering Station will create 1 data base element of
type IntegerLong Param.
Picture IntegerLong Param element

PDx
IntegerLong Param
COUNTVALUEMAX NAME VALID
0 INIT_VAL VALUE
Terminals IntegerLong Param element

by data
type
characters
INIT_VAL user 0 - INITial VALue, an integer -2147483648 to
long value. +2147483647
VALUE system 0 IL(r/w) One integer long VALUE. -2147483648 to
+2147483647
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3AFY61281240
Real Param PARDAT(R)

Summary
The PARDAT(R) element contains one real data value. The data value is given a name, initial
value and a valid flag.
By means of the call name PARDAT(R) the Engineering Station will create 1 data base element of
type Real Param.
Picture Real Param element

PDx
Real Param
MOTORCURRENTMAX NAME VALID
0.0 INIT_VAL VALUE
Terminals Real Param element

by data
type
characters
INIT_VAL user 0.0 - INITial VALue (real). -
VALUE system 0 R(r/w) On real VALUE. -
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3AFY61281240
Save Parameter SAVE00

Summary
DB element SAVE00 is used to reserve memory for the SAVE function block. . SAVE00
NAME
STATION
POSITION
TYPE
NOTCLEAR
HDSIZE
RECORDS
RECSIZE
Call SAVE00 Figure 1. DB
Element
Connections Table 1 SAVE00

NAME user SAVx Unique 20 character name.
POSITION system 8 Position in DB element library. For internal use
only.
TYPE system SAVE00 DB element type.
NOTCLEAR user 1 ?
HDRSIZE system 34 Header size. For internal use only.
RECORDS user 10 Number of buffers for parameters defined by the
SAVE function block.
RECSIZE system 10 Size of one save buffer.
Related documents
See also the description of the SAVE function block.
296

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APC2 FUNCTION BLOCKS

Code: 3AFY 61281240

Issued by: FIDRI/EIE

Date: Code: Rev.: Remark:

For information on: See:

Event Detection EVENT.................................................................................................... 144

Subtractor SUB................................................................................................................. 257

This page is intentionally left blank.

1. INTRODUCTION TO DRIVE APPLICATION

The Programming Language

Connection of Function element Inputs and Outputs

Table 2 Data types

The range of allowable integer values is as follows.

For I = -32768 .. 32767

Overflow Real Numbers

Element Libraries for Drive APC and other

Figure 3.Graphic Symbol with

The Data Sheets

The calling of the element is described under the heading Call.

ELEMENT(C1,C2, ... Cn)

Subtractor SUB The call name of the element.

Figure 4. Description, schematic outline .

2. APC FUNCTION ELEMENTS ACCORDING TO TYPE

Bitwise operation on the Integer data type

Feedback and Filter

Parameter handling elements

I/O handling elements

Event handling elements

Data logging elements

Data Base elements

3. SHORT FORM DESCRIPTION - FUNCTION ELEMENTS

4. SHORT FORM DESCRIPTION - DATA BASE

5. EXECUTION TIMES FOR PC ELEMENTS

AND* 7 + 2 x C1 (1.4 + 1.2 x C1), ( )

Name Execution time, Typical (µs) Notes

Name Execution time, Typical (µs) Notes

FUNG-1V 274 BAL = 0

Name Execution time, Typical (µs) Notes

INT 123 BAL & RINT = 0

IOBUSRD 18 + 11 x C1 + 12 x C2 + 14 x (C3 +C4) EN = 1

Name Execution time, Typical (µs) Notes

OR 7 + 2 x C1 (1.4 + 1.2 x C1), () = "Inline" time

OR-A 6 + 3 x (C1 + C2 + C3 + C4 + C5 + C6)

PDP 261 BAL = 0

Name Execution time, Typical (µs) Notes

Name Execution time, Typical (µs) Notes

WDOG 109 with one YPQ 111

"inline" begin + 5.2 onetime overhead for a inline sequence!

6. SPACE REQUIREMENTS FOR PC ELEMENTS

AND-O 12 + 6C1 +6C2 + X0

COMP-R 4 x (C1 + C2) + 16 8 + 2 x (C1 +C2)

Name PC Statement(byte) Local Data Area(byte) Notes

DRPAR X20 + 6 x C1 X24

DRREC X22 + 2 x C2 X38

DRTRA X20 + 2 x C2 X38

Name PC Statement(byte) Local Data Area(byte) Notes

Name PC Statement(byte) Local Data Area(byte) Notes

OR-A 12 + 2C1 + 2C2 + 2C3

PANREC 26 + 2C1 + 2C2 + 2C3 6

PANTRA 26 + 2C1 + 2C2 + 2C3 6

Name PC Statement(byte) Local Data Area(byte) Notes

SR-AA 8 + 2C1 + 2C2 + 2C3 + 2C4 0

SR-OA 8 + 2C1 + 2C2 + 2C3 + 2C4 0

7. SPACE REQUIREMENTS FOR "Inline" CODE