FACULTY OF COMPUTING AND INFORMATICS

DEPARTMENT OF COMPUTER SCIENCE

QUALIFICATION: Bachelor of (Computer Science, Informatics & Cyber Security)

QUALIFICATION CODE: 07BACS,07BAIF,07BCCS LEVEL: 5
COURSE: Computer Organisation and Architecture COURSE CODE: COA511S
DATE: 11 May 2018 SESSION: THEORY
DURATION: 60 Min MARKS: 40

SUPPLEMENTARY TEST PAPER

EXAMINER(S): MR. JULIUS SILAA (Theory ALL, FT1 & PT2)
MR. JOE EELU (PT1 & PT3)
MS. ALBERTINA SHILONGO (FT3 ,FT5A & FT7)
MS.KATAZO AMUNKETE (FT5B & FT 10B)
MS.TERESIA ANKOME(9 & 10 )
MR.EDWARD NEPOLO( FT2,FT4 & FT6)
MS. EUNICE MBASUVA( FT8)

MODERATOR: MR. SIMON MUCHINENYIKA

THIS PAPER CONSISTS OF 6 PAGES

(INCLUDING THIS FRONT PAGE)

INSTRUCTIONS TO STUDENTS
1. Answer all questions in the space provided in this question paper
2. Ensure that your writing is legible, neat and presentable.
3. No notes or any other additional material may be used in this quiz,
4. Complete the information below accurately

Student Name & Surname___________________, ___________________

Student Number ________________________________________
Practical Group______________ Lecturer’s surname_________________________

SECTION A: Answer All Questions. Each Question weighs 1 Mark. [10 MARKS]
Circle the correct answer

1. Pipelining is a means of introducing parallelism into the essential sequential

nature of a machine-instruction program. [True/False]
2. In a system without virtual memory, the effective address is a
virtual address or a register. [True/False]

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3. A common measure of performance for a processor is the rate at which
instructions are executed, expressed as millions of instructions per second
(MIPS). [True/False]

4.Instruction pipelining is a powerful technique for enhancing performance but requires

careful design to achieve optimum results with reasonable complexity. [True/False]

5. The most fundamental type of machine instruction is the _________ instruction.

A. conversion B. data transfer
C. arithmetic D. logical
6. The ________ determines the opcode and the operand specifiers.

A. decode instruction B. fetch operands

C. calculate operands D. execute instruction

7. _________ instructions provide computational capabilities for processing number

data.

A. Boolean B. Logic

C. Memory D. Arithmetic

8. Which of the following interrelated factors go into determining the use of the addressing
bits?
A. number of operands B. number of register sets
C. address range D. all of the above

9. A ________ is a dispatch able unit of work within a process that includes a

processor context and its own data area for a stack.
A. Process B. Process switch
C. Thread D. Thread switch

10.The _________ contains the address of an instruction to be fetched.

A. instruction register B. memory address register

C. memory buffer register D. program counter

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 SECTION B: Structured questions. Answer All Questions. [30 MARKS]

Question1 (8 marks)

1.a) Why does the program execution speed generally increase as the number of
general purpose registers increase? (2 Marks)

i. Register accesses are fast as compared to main memory, registers usually store data
that is needed immediately or frequently used by the CPU. [2]
ii. Registers mostly store intermediate results. [2]
iii. Adding registers only increases execution speed up to a point. There are a limited
number of intermediate results or frequently used data in any given process or
program. [2] [Any two explained points]
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1.b) Registers are fast stand-alone storage locations that hold data temporarily

in CPU. List any three types of registers and explain their functions. (6 Marks)

Instruction Register -Store the instruction currently being executed [2]

Data Registers- Hold data before it can be processed [2]
Program counter (PC) - indicates where a computer is in its program [2]
Memory buffer register (MBR) stores the data being transferred to and from [2]
Accumulator (AC) Data Register (DR) Memory data Register (MDR) etc.
(Any 3 Registers@1mark and function @1mark)

Question2 (9 marks)

Addressing modes are an aspect of the instruction set architecture in most central

processing unit (CPU) designs. The various addressing modes that are defined in a

given instruction set architecture define how machine language instructions in that

architecture identify the operand(s) of each instruction.

2.a) Explain the following instruction addressing mode (3 Marks)

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 i)Immediate
ii)Direct
iii) Register
i. If data is present in the instruction itself, it is called immediate addressing mode
ii. If data is present at the 16-bit address mentioned in the instruction, it is called direct
addressing mode
iii. If data is present in registers mentioned in the instruction, it is called register addressing
mode.
(allocate 1 mark to each correct explanation)

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2.b) Give an example of each addressing mode listed in question (2a) above. (6 Marks)

i)For example
ADD AL, 01H
SUB BL, 04H

ii)For example,
MOV AX, [1111H]
MOV BX, [4444H]
Here, effective address is
➢ 10H * DS + 1111H for the first example and
➢ 10H * DS + 4444H for the second example

iii) For example,

ADD AX, BX
SUB BL, AL
Here, data i.e. operands is present in registers AX, BX for the first example
(allocate 2 marks to each correct example given. One example is sufficient )
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Question3 (13 marks)

a) What is Instruction pipelining? (2 Marks)

Instruction pipelining is a technique that implements a form of parallelism
called instruction-level parallelism within a single processor. [2]
It therefore allows faster CPU throughput (the number of instructions that
can be Executed in a unit of time) than would otherwise be possible at a
given Clock rate
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b) List the basic five instruction pipeline stages (3 Marks)

Basic five instruction pipeline stages are (IF = Instruction Fetch, ID = Instruction Decode,
EX = Execute, MEM = Memory access, WB = Register write back).
(0.5 marks per stage ,0.5 marks if in a correct order )
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c) Show diagrammatically how instruction pipelining is implemented in typical

modern microprocessor. Your diagram should emphasize how instructions, pipeline
stages and clock cycle are related (8 Marks)

Instructions, pipeline stages and clock cycle labels included [3]

Pipeline parallel stages clearly outline and labeled [4]
General correctness and neatness [1]
Note: In the fourth clock cycle the earliest instruction is in MEM stage, and the
latest instruction has not yet entered the pipeline
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*****END OF TEST1*****

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