ch1 4 First Test Samples v4 Solution PDF

AJMAN UNIVERSITY OF SCIENCE AND TECHNOLOGY
COLLEGE OF INFORMATION TECHNOLOGY

Computer Organization - 3152030
First Exam 1st Sem. 2016-2017
Name…………………………………………………………………ID……………………….
Q1) TRUE OR FALSE. Circle the correct answer (2.5 Marks)
T F 1. Changes in computer technology are finally slowing down.
T F 2. The cache holds recently accessed data.
T F 3. Operations performed by a processor, such as fetching an instruction,

decoding the instruction, performing an arithmetic operation, and so on, are
governed by a system clock.
T F 4. A common measure of performance for a processor is the rate at

which instructions are executed, expressed as millions of instructions per
second (MIPS).
T F 5. A straight comparison of clock speeds on different processors tells the whole

story about performance.
Q2) MULTIPLE CHOICE. Circle the correct answer. (5 Marks)
1. An I/O device is referred to as a __________.
A. CPU B. control device
C. peripheral D. register
2. When data are moved over longer distances, to or from a remote device, the process is
known as __________.
A. data communications B. registering
C. structuring D. data transport
3. The _________ stores data.
A. system bus B. I/O
C. main memory D. control unit
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4. The __________ moves data between the computer and its external environment.
A. data transport B. I/O
C. register D. CPU interconnection
5. _________ provide storage internal to the CPU.
A. Control units B. ALUs
C. Main memory D. Registers
6. The __________ performs the computer’s data processing functions.
A. Register B. CPU interconnection
C. ALU D. system bus
7. The desktop application(s) that require the great power of today’s microprocessor-based
systems include___________.
A. image processing B. speech recognition
C. videoconferencing D. all of the above
8. ___________ potentially increases the amount of work available for the processor to
execute.
A. Branch prediction B. Performance balance
C. Pipelining D. BIPS
9. The __________ is a relatively small fast memory interposed between a larger, slower
memory and the logic that accesses the larger memory.
A. peripheral B. cache
C. processor D. arithmetic and logic unit
10. One increment, or pulse, of a clock is referred to as a __________ .
A. clock cycle B. clock rate
C. clock speed D. cycle time
11. The use of multiple processors on the same chip is referred to as __________ and
provides the potential to increase performance without increasing the clock rate.
A. multicore B. GPU
C. data channels D. MPC
Q3: SHORT ANSWER: Fill in the blanks. (4 Marks)
1. Often referred to as processor the ________ central processing unit (CPU) controls the
operation of the computer and performs its data processing functions.
2. A common example of system interconnection is by means of a ________ system bus,

consisting of a number of conducting wires to which all the other components attach.
3. The major structural components of the CPU are: control unit, register, CPU
interconnection, and __________ arithmetic and logic unit (ALU).
4. The _________ control unit controls the operation of the CPU and hence the computer.
5. __________ Pipelining enables a processor to work simultaneously on multiple

instructions by performing a different phase for each of the multiple instructions at the
same time.
6. With __________ branch prediction the processor looks ahead in the instruction code
fetched from memory and predicts which branches, or groups of instructions, are likely
to be processed next.
Q4) List and explain the various replacement algorithms used in cache memory.
Answer: Replacement Algorithms
Once the cache has been filled, when a new block is brought into the cache, one
of the existing blocks must be replaced. For direct mapping, there is only one possible
line for any particular block, and no choice is possible. For the associative
and set-associative techniques, a replacement algorithm is needed. To achieve high
speed, such an algorithm must be implemented in hardware. A number of algorithms
have been tried. We mention four of the most common. Probably the most
effective is least recently used (LRU): Replace that block in the set that has been in
the cache longest with no reference to it. For two-way set associative, this is easily
implemented. Each line includes a USE bit. When a line is referenced, its USE bit
is set to 1 and the USE bit of the other line in that set is set to 0. When a block is to
be read into the set, the line whose USE bit is 0 is used. Because we are assuming
that more recently used memory locations are more likely to be referenced, LRU
should give the best hit ratio. LRU is also relatively easy to implement for a fully
associative cache. The cache mechanism maintains a separate list of indexes to all
the lines in the cache. When a line is referenced, it moves to the front of the list.
For replacement, the line at the back of the list is used. Because of its simplicity of
implementation, LRU is the most popular replacement algorithm.
Another possibility is first-in-first-out (FIFO): Replace that block in the set
that has been in the cache longest. FIFO is easily implemented as a round-robin
or circular buffer technique. Still another possibility is least frequently used (LFU):
Replace that block in the set that has experienced the fewest references. LFU could
be implemented by associating a counter with each line. A technique not based on
usage (i.e., not LRU, LFU, FIFO, or some variant) is to pick a line at random from
among the candidate lines. Simulation studies have shown that random replacement
provides only slightly inferior performance to an algorithm based on usage [SMIT82].
Q5) List and briefly define two approaches to dealing with multiple interrupts.
Answer: Disable all interrupts while an interrupt is being processed. (2) Define priorities for
interrupts and to allow an interrupt of higher priority to cause a lower-priority interrupt handler
to be interrupted.
Q6) From a user’s point of view, the two most important characteristics of memory
are capacity and performance. List and briefly define three performance parameters.
Answer:• Access time (latency): For random-access memory, this is the time it takes to
perform a read or write operation, that is, the time from the instant that an
address is presented to the memory to the instant that data have been stored
or made available for use. For non-random-access memory, access time is the
time it takes to position the read–write mechanism at the desired location.
• Memory cycle time: This concept is primarily applied to random-access memory
and consists of the access time plus any additional time required before a second
access can commence. This additional time may be required for transients to die
out on signal lines or to regenerate data if they are read destructively. Note that
memory cycle time is concerned with the system bus, not the processor.
• Transfer rate: This is the rate at which data can be transferred into or out of a
memory unit. For random-access memory, it is equal to 1/(cycle time).
For non-random-access memory, the following relationship holds:
Q7) A memory system has 16M bytes and 24-bits address. The memory is organized into blocks
of 8 bytes each, and the cache has total 512K bytes, organized into cache lines of 8 bytes each:
1. Show the format of main memory address with direct mapping, associative and
2-way set associative mapping, respectively.
8 byte per block, so Word should be 3 bits, 16bits for Line and 24-(3+16)=5bits for
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AJMAN UNIVERSITY OF SCIENCE AND TECHNOLOGY

COLLEGE OF INFORMATION TECHNOLOGY

T F 1. Changes in computer technology are finally slowing down.

T F 2. The cache holds recently accessed data.

T F 3. Operations performed by a processor, such as fetching an instruction,

T F 4. A common measure of performance for a processor is the rate at

T F 5. A straight comparison of clock speeds on different processors tells the whole

Q2) MULTIPLE CHOICE. Circle the correct answer. (5 Marks)

1. An I/O device is referred to as a __________.

A. CPU B. control device

A. data communications B. registering

C. structuring D. data transport

3. The _________ stores data.

A. system bus B. I/O

C. main memory D. control unit

A. data transport B. I/O

C. register D. CPU interconnection

5. _________ provide storage internal to the CPU.

A. Control units B. ALUs

C. Main memory D. Registers

6. The __________ performs the computer’s data processing functions.

A. Register B. CPU interconnection

C. ALU D. system bus

A. image processing B. speech recognition

C. videoconferencing D. all of the above

A. Branch prediction B. Performance balance

C. processor D. arithmetic and logic unit

10. One increment, or pulse, of a clock is referred to as a __________ .

A. clock cycle B. clock rate

C. clock speed D. cycle time

C. data channels D. MPC

Q3: SHORT ANSWER: Fill in the blanks. (4 Marks)

2. A common example of system interconnection is by means of a ________ system bus,

5. __________ Pipelining enables a processor to work simultaneously on multiple

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