CIS 5100 Homework Assignment #3 Solutions

Fall 2020, Dr. Song Xing

Stephen D. Burd
Chapter 5: Vocabulary Exercises

1. Dynamic RAM requires frequent __________ to maintain its data content.

Answer: refresh cycles
2. The __________ rate is the speed at which data can be moved to or from a storage device over a
communication channel.
Answer: data transfer
3. The contents of most forms of RAM are __________, making them unsuitable for long-term data
storage.
Answer: volatile
4. __________ and __________ are promising new technologies for implementing NVM that
promise significant increases in longevity.
Answer: magnetoresistive RAM (MRAM), phase-change memory (PCM)

5. __________ is typically stated in milliseconds for secondary storage devices and nanoseconds for
primary storage devices.
Answer: Access time
6. The access method for RAM is __________ or __________ if words are considered the unit of
data access. The access method is __________ if bits are considered the unit of data access.
Answer: random, direct, parallel
7. A(n) __________ mimics the behavior and physical size of a magnetic disk drive but has no
moving parts.
Answer: solid-state drive
8. The data transfer rate of a magnetic or optical disk drive can be calculated by dividing 1 by the
drive’s access time and multiplying the result by the __________.
Answer: data transfer unit size
9. Tape drives are __________ devices. __________ are random or direct access devices.
Answer: serial access, disk drives

10. Modern desktop and laptop computers generally use memory packaged on small standardized
circuit boards called __________.
Answer: SIMMs or DIMMs
11. For most disk drives, the unit of data access and transfer is a(n) __________ or
__________.
Answer: block, sector
12. Software programs stored permanently in ROM are called __________.
Answer: firmware
More exercises

1. big, most significant, little, most significant

2. wait states

3. addressable memory

4. Secondary storage, primary storage

Vocabulary Exercises (Stephen D. Burd, Chapter 6, revision):

Pick your answers from the following key terms:
1. A __________ is the communication channel that connects all computer system components.
Answer: bus， system bus
2. Cache types that are generally implemented on the same chip as the CPU include __________
and __________.
Answer: L1 or level one, and L2 or level two
3. The CPU is always capable of being a(n) __________, thus controlling access to the bus by all
other devices in the computer system.
Answer: bus master
4. A(n) __________ is a reserved area of memory used to resolve differences in data transfer rate or
data transfer unit size.
Answer: buffer
5. A(n) __________ is an area of fast memory where data held in a storage device is prefetched in
anticipation of future requests for the data.
Answer: cache
6. A cache controller is a hardware device that initiates a(n) __________ when it detects a cache
miss.
Answer: cache swap
7. The __________ transmits command, timing, and status signals between devices in a computer
system.
Answer: control bus
8. If possible, the system bus __________ rate should equal the CPU’s speed.
Answer: clock
9. The __________ is a special-purpose register that always points to the next empty address in the
stack
Answer: stack pointer
10. The __________ transfers control to the interrupt handler at the memory address corresponding
to the interrupt code.
Answer: supervisor
11. The set of register values stored in the stack while processing an interrupt is also called the
__________.
Answer: machine state
12. A(n) __________ is a program stored in a separate part of primary storage to process a specific
interrupt.
Answer: interrupt handler
13. During interrupt processing, register values of a suspended process are held on the __________.
Answer: stack
14. A(n) __________ is a signal to the CPU or OS that some device or program requires processing
services.
Answer: interrupt
15. The __________ has a much higher data transfer rate than the system bus because of its shorter
length, higher clock rate, and large number of parallel communication lines.
Answer: memory bus
16. The CPU incurs one or more __________ if it’s idle pending the completion of an I/O operation.
Answer: I/O wait states
17. The system bus can be divided logically into four sets of transmission lines: the __________ bus,
the __________ bus, the _ bus, and the __________ bus.
Answer: address, control, data, power
18. During a(n) __________ operation, one or more register values are copied to the top of the stack.
During a(n) __________ operation, one or more values are copied from the top of the stack to
registers.
Answer: push, pop
19. A(n) __________ is a special-purpose processor dedicated to managing cache content.
Answer: cache controller
20. A(n) __________ is a communication pathway from the CPU to a peripheral device.
Answer: I/O port
21. The _________________ transmits a memory address when primary storage is the sending or
receiving device.
Answer: address bus
22. A(n) __________ controller assumes the role of bus master for all transfers between memory and
other storage or I/O devices, leaving the CPU free to execute computation and data movement
instructions.
Answer: DMA
23. When a read operation accesses data already contained in the cache, it’s called a(n) __________.
Answer: cache hit
24. The __________ defines the format, content, and timing of data, memory addresses, and control
messages sent across the bus.
 Answer: bus protocol
25. In __________ architecture, multiple CPUs and cache memory are embedded on a single chip.
Answer: multicore
26. The term __________ describes methods of increasing processing and other computer system
power by using larger and more powerful computers.
Answer: scaling up
27. __________ architecture is a cost-effective approach to computer system design when a single
computer runs many different applications or services at once.
Answer: multiple-processor
28. Examples of a(n) __________ bus include SATA and SCSI.
Answer: Storage

Review Questions (Chapter 5)

1. Why isn’t flash RAM commonly used to implement primary storage?

Flash RAM wears out after several hundred thousand read/write cycles. Therefore, it
would have to be replaced frequently if used as primary storage in a general-purpose
computer.
2. Describe serial, random, and parallel access. What types of storage devices use each method?
Serial access reads or writes data units in sequential order. Magnetic tape is the only
widely used form of serial access storage. Random access can “jump” directly between
two noncontiguous data units. All primary storage and disk storage devices (including
SSD) use random access. Parallel access reads or writes portions of a data item in parallel
on separate storage devices or media. RAM can also be considered a parallel access
device.
3. In what way(s) is/are SSDs an improvement over magnetic disk drives? In what way(s)
isn't/aren't they an improvement over magnetic disk drives?

By avoiding all mechanical delays in accessing storage locations, SSDs yield a significant
performance improvement compared to magnetic disk drives. However, their lifetime, as
measured in write cycles, is significantly less than magnetic disk drives. Also, their cost per unit
of storage is generally higher than for magnetic disk drives.

Review Questions (Stephen D. Burd, Chapter 6):

1. What characteristics of the CPU and of the system bus should be balanced to achieve maximum
system performance?
Answer: The width of the data bus should equal or exceed CPU word size. The bus clock
rate should match the CPU clock rate, though this is difficult or impossible to achieve.

2. How can a cache be used to improve performance when reading data from and writing data to a
storage device?
 Answer: A cache controller attempts to guess what data will be requested next and
prefetch this data into the cache. If the cache controller guesses correctly, data can be
supplied more quickly. A cache controller confirms a write operation as soon as data is
written to the cache but before it’s written to the storage device. This improves the
performance of a program waiting for write confirmation by reducing the interval
between the write request and the write confirmation.

3. What is a multicore processor? What are its advantages compared with multiple-processor
architecture?
Answer: A multicore processor is a single microchip containing two or more fully
functional CPUs. The main advantage of multicore architecture compared with multi-
CPU architecture with CPUs of equivalent number and power is more efficient inter-CPU
communication, which increases total computational power when multiple CPUs
cooperate on the same task. Multicore processors didn’t become available until the mid-
2000s because that’s when the capabilities of modern semiconductor manufacturing
methods evolved to the point that enough transistors could be placed on a single chip to
implement multiple CPUs and their memory caches.

Problems and Exercises

1. The clock cycle time is 1 divided by the cycle rate, or 1 divided by 2,400,000,000 = approximately
0.4167 nanoseconds.

In the following figure, fetch cycles are shown in red and execution cycles in blue. The memory
access includes the time to transmit the access request and receive the result by the CPU. As the
processor cycle time is 0.4167 nanoseconds, so 24 CPU cycles (10 divided by 0.4167) are
required to complete the fetch operation. Half of the next cycle (the fetch portion) is wasted
waiting for the execution cycle to begin (the execution can’t begin until 10.21 nanoseconds have
elapsed), so 24 wait states are incurred.

2.

Storage device Average access time Data transfer unit size Data transfer rate

RAM 4 ns 8 bytes (1 ÷ .000000004 seconds)

× 64 bits = 16 Gbps
Optical disc 100 ms 512 bytes (1 ÷ .01 seconds) × 512
bytes = 5,120 Bps (or 5.12
kBps) = 40.96 kbps
Magnetic disk 5 ms 1024 bytes (1 ÷ .005 seconds) × 1024
bytes = 204,800 Bps (or
204.8 kBps) = 1.6384
Mbps