nd

2
Assignment
Submitted to :
Ma’am Zoya Arif
Submitted by :
Komal shamoon
BSCS (V)
ROLL NO.
746528
QUESTION 1
ANSWER :
The CPU can initiate a DMA operations through writing values into special registers that
can be independently accessed by means of the tool. the device intimates the
corresponding operation as soon as it gets command from the CPU. While the device is
completed with its operation, it interrupts the CPU to suggest the completion of the
operation.each the device and the CPU can be getting access to memory concurrently. The
memory controller provides get admission to the reminiscence bus in a fair -manner to
those entities. A CPU might consequently be unable to issue-memory operations at top
speeds since it has to complete with the-device so that it will achieve get admission to the
reminiscence bus.
QUESTION 2
ANSWER :
a: LAN
b: WAN
c: LAN and WAN

QUESTION 3
ANSWER :
The greatest chellenge is designing cell operating system structure encompass

 Much less garage potential way the working machine have to managememory
carefully.
 The working machine should additionally manipulate power intake care-complete
 Much less processing strength plus fewer processors mean the operating system
need to carefully apportion processors to programs.
QUESTION 4
ANSWER :
In single processor structures, the memory needs to be up to date when processor problems
updates to caches values.-these updates can be-performed without deley or in a lazy way.
In a multi-processor device, the exclusive processors might be caching the equal
reminiscence area in its-local caches. While updates are made, the alternative cached
locations want to be invalidated or up to date.
In allotted systems, consistency of cached-memory values is not a difficulty. however,
consistency troubles might-arise while a patron caches record data.
QUESTION 5
ANSWER :
basically some thing that gives content, similarly to current ser-vices consisting of file
services, allotted listing services along with domain-name services, and dispensed
lec5f5ec77c51a968271b2ca9862907d offerings.
QUESTION 6
ANSWER :
An HPC cluster is a set of many separate servers (computer systems), referred to as nodes,
that are related through a fast interconnect.
There may be exclusive kinds of nodes for distinct styles of responsibilities.
each of the HPC clusters listed in this has
a headnode or login node, where-in users log in
a specialized facts transfer node
ordinary compute nodes ( in which majority of computations is administered)
“ fats” compute nodes that have at-least 1 TB of reminiscence.
CPU nodes ( on those nodes computations can be run both on CPU cores and on a graphical
processing Unit)
an infinite-band transfer to connect all nodes.
QUESTION 7
ANSWER :
Processor model
The processor version used inside the Illinois SFI examine is a dynamically scheduled
superscalar pipeline. Parent 4.19a shows a diagram of this pipeline. Parent 4.9b shows a key
processor parameters.
To understand the details of this pipeline, the readers are stated as hennessy and Peterson’s
book on pc structure layout[4] . this processor version makes use of alpha ISA but does not
execute floating-factor instructions, synchronizing memory operations, and a few
miscellaneous commands. The processor resembles a modern-day, dynamically schedular
processor.
In laptop science, a generator is a recurring that can be used to manipulate the iterational
behavior of the loop.
All turbines are also iterators.
A model generator permits you to routinely generate structures by specifying the most vital
parameters. there are numerous alternatives for the generation of the beams, frames or
stairways, as an example.